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--------------------------------------------------------------------------------
-- Copyright (C) 1999-2008 Easics NV.
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--
-- Purpose : synthesizable CRC function
-- * polynomial: (0 2 12 16)
-- * data width: 1
--
-- Info : [email protected]
-- http://www.easics.com
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package PCK_CRC16_D1 is
-- polynomial: (0 2 12 16)
-- data width: 1
-- convention: the first serial bit is D[0]
function nextCRC16
(Data: std_logic;
crc: std_logic_vector(15 downto 0))
return std_logic_vector;
end PCK_CRC16_D1;
package body PCK_CRC16_D1 is
-- polynomial: (0 2 12 16)
-- data width: 1
-- convention: the first serial bit is D[0]
function nextCRC16
(Data: std_logic;
crc: std_logic_vector(15 downto 0))
return std_logic_vector is
variable d: std_logic_vector(0 downto 0);
variable c: std_logic_vector(15 downto 0);
variable newcrc: std_logic_vector(15 downto 0);
begin
d(0) := Data;
c := crc;
newcrc(0) := d(0) xor c(15);
newcrc(1) := c(0);
newcrc(2) := d(0) xor c(1) xor c(15);
newcrc(3) := c(2);
newcrc(4) := c(3);
newcrc(5) := c(4);
newcrc(6) := c(5);
newcrc(7) := c(6);
newcrc(8) := c(7);
newcrc(9) := c(8);
newcrc(10) := c(9);
newcrc(11) := c(10);
newcrc(12) := d(0) xor c(11) xor c(15);
newcrc(13) := c(12);
newcrc(14) := c(13);
newcrc(15) := c(14);
return newcrc;
end nextCRC16;
end PCK_CRC16_D1;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hls_saturation_enrcU_DSP48_2 is
port (
a: in std_logic_vector(19 - 1 downto 0);
b: in std_logic_vector(8 - 1 downto 0);
p: out std_logic_vector(27 - 1 downto 0));
end entity;
architecture behav of hls_saturation_enrcU_DSP48_2 is
signal a_cvt: unsigned(19 - 1 downto 0);
signal b_cvt: unsigned(8 - 1 downto 0);
signal p_cvt: unsigned(27 - 1 downto 0);
attribute keep : string;
attribute keep of a_cvt : signal is "true";
attribute keep of b_cvt : signal is "true";
attribute keep of p_cvt : signal is "true";
begin
a_cvt <= unsigned(a);
b_cvt <= unsigned(b);
p_cvt <= unsigned (resize(unsigned (unsigned (a_cvt) * unsigned (b_cvt)), 27));
p <= std_logic_vector(p_cvt);
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity hls_saturation_enrcU is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of hls_saturation_enrcU is
component hls_saturation_enrcU_DSP48_2 is
port (
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
hls_saturation_enrcU_DSP48_2_U : component hls_saturation_enrcU_DSP48_2
port map (
a => din0,
b => din1,
p => dout);
end architecture;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ab
--
-- Generated
-- by: wig
-- on: Mon Apr 10 13:27:22 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ab-rtl-a.vhd,v 1.1 2006/04/10 15:42:07 wig Exp $
-- $Date: 2006/04/10 15:42:07 $
-- $Log: ent_ab-rtl-a.vhd,v $
-- Revision 1.1 2006/04/10 15:42:07 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_ab
--
architecture rtl of ent_ab is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity srom01 is
port (
clk_i : std_logic;
addr_i : std_logic_vector(3 downto 0);
data_o : out std_logic_vector(7 downto 0));
end srom01;
architecture behav of srom01 is
begin
process (clk_i, addr_i)
type mem_type is array (0 to 15) of std_logic_vector (7 downto 0);
constant mem : mem_type := (
x"f0", x"e1", x"d2", x"c3",
x"b4", x"a5", x"96", x"87",
x"78", x"69", x"5a", x"4b",
x"3c", x"2d", x"1e", x"0f");
variable addr : natural range mem_type'range;
begin
if rising_edge(clk_i) then
addr := to_integer (unsigned (addr_i));
data_o <= mem (addr);
end if;
end process;
end behav;
|
library work;
use work.all;
package ShiftReg is
type integer_list_t is array (natural range <>) of integer; -- notice this line
procedure main(new_sample: integer);
end package;
package body ShiftReg is
procedure main(new_sample: integer) is
variable dummy: integer_list_t(0 to 3); -- notice this line
begin
dummy := new_sample & dummy(0 to dummy'high-1); --no error
end procedure;
end package body;
|
library work;
use work.all;
package ShiftReg is
type integer_list_t is array (natural range <>) of integer; -- notice this line
procedure main(new_sample: integer);
end package;
package body ShiftReg is
procedure main(new_sample: integer) is
variable dummy: integer_list_t(0 to 3); -- notice this line
begin
dummy := new_sample & dummy(0 to dummy'high-1); --no error
end procedure;
end package body;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity scaling_values_lut_tb is
end entity;
architecture scaling_values_lut_tb_arq of scaling_values_lut_tb is
signal steps : integer := 0;
signal scaling_value : std_logic_vector(31 downto 0) := (others => '0');
component scaling_values_lut is
generic(TOTAL_BITS: integer := 32);
port(
steps: in integer := 0;
scaling_value: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
for scaling_values_lut_0 : scaling_values_lut use entity work.scaling_values_lut;
begin
scaling_values_lut_0 : scaling_values_lut
generic map(TOTAL_BITS => 32)
port map(
steps => steps,
scaling_value => scaling_value
);
process
type pattern_type is record
i : integer;
sv : std_logic_vector(31 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
(1,"00000000000000001011010100000100"),
(6,"00000000000000001001101101111011"),
(20,"00000000000000001001101101110100")
);
begin
for i in patterns'range loop
-- Set the inputs.
steps <= patterns(i).i;
wait for 1 ns;
assert patterns(i).sv = scaling_value report "BAD SCALING VALUE, GOT: " & integer'image(to_integer(unsigned(scaling_value)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Tue Oct 18 17:47:49 2016
-- Host : chinook.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.2 (Maipo)
-- Command : write_vhdl -force -mode funcsim
-- /afs/ece.cmu.edu/usr/jacobwei/Public/FPGA/FPGA.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_funcsim.vhdl
-- Design : blk_mem_gen_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_mux__parameterized0\ is
port (
\^doutb\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
DOBDO : in STD_LOGIC_VECTOR ( 1 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 6 downto 0 );
clkb : in STD_LOGIC;
DOUTB : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_7\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_8\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_9\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_10\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_11\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_12\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_13\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux";
end \blk_mem_gen_0_blk_mem_gen_mux__parameterized0\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_mux__parameterized0\ is
signal \doutb[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[0]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[1]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[1]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[2]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[2]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal sel_pipe : STD_LOGIC_VECTOR ( 6 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 6 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \doutb[0]_INST_0_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \doutb[1]_INST_0_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \doutb[2]_INST_0_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \doutb[3]_INST_0_i_1\ : label is "soft_lutpair1";
begin
\doutb[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F004F4F0F004040"
)
port map (
I0 => sel_pipe_d1(4),
I1 => \doutb[0]_INST_0_i_1_n_0\,
I2 => sel_pipe_d1(6),
I3 => \doutb[0]_INST_0_i_2_n_0\,
I4 => sel_pipe_d1(5),
I5 => \doutb[0]_INST_0_i_3_n_0\,
O => \^doutb\(0)
);
\doutb[0]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \doutb[0]_INST_0_i_4_n_0\,
I1 => sel_pipe_d1(3),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0),
O => \doutb[0]_INST_0_i_1_n_0\
);
\doutb[0]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_1\(0),
O => \doutb[0]_INST_0_i_2_n_0\,
S => sel_pipe_d1(4)
);
\doutb[0]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => DOUTB(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\(0),
O => \doutb[0]_INST_0_i_3_n_0\,
S => sel_pipe_d1(4)
);
\doutb[0]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00003A0A"
)
port map (
I0 => DOBDO(0),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(0),
I4 => sel_pipe_d1(2),
O => \doutb[0]_INST_0_i_4_n_0\
);
\doutb[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F004F4F0F004040"
)
port map (
I0 => sel_pipe_d1(4),
I1 => \doutb[1]_INST_0_i_1_n_0\,
I2 => sel_pipe_d1(6),
I3 => \doutb[1]_INST_0_i_2_n_0\,
I4 => sel_pipe_d1(5),
I5 => \doutb[1]_INST_0_i_3_n_0\,
O => \^doutb\(1)
);
\doutb[1]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \doutb[1]_INST_0_i_4_n_0\,
I1 => sel_pipe_d1(3),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
O => \doutb[1]_INST_0_i_1_n_0\
);
\doutb[1]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_4\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_5\(0),
O => \doutb[1]_INST_0_i_2_n_0\,
S => sel_pipe_d1(4)
);
\doutb[1]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_2\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_3\(0),
O => \doutb[1]_INST_0_i_3_n_0\,
S => sel_pipe_d1(4)
);
\doutb[1]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00003A0A"
)
port map (
I0 => DOBDO(1),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(1),
I4 => sel_pipe_d1(2),
O => \doutb[1]_INST_0_i_4_n_0\
);
\doutb[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F004F4F0F004040"
)
port map (
I0 => sel_pipe_d1(4),
I1 => \doutb[2]_INST_0_i_1_n_0\,
I2 => sel_pipe_d1(6),
I3 => \doutb[2]_INST_0_i_2_n_0\,
I4 => sel_pipe_d1(5),
I5 => \doutb[2]_INST_0_i_3_n_0\,
O => \^doutb\(2)
);
\doutb[2]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \doutb[2]_INST_0_i_4_n_0\,
I1 => sel_pipe_d1(3),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0),
O => \doutb[2]_INST_0_i_1_n_0\
);
\doutb[2]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_8\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_9\(0),
O => \doutb[2]_INST_0_i_2_n_0\,
S => sel_pipe_d1(4)
);
\doutb[2]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_6\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_7\(0),
O => \doutb[2]_INST_0_i_3_n_0\,
S => sel_pipe_d1(4)
);
\doutb[2]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00003A0A"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\(0),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(2),
I4 => sel_pipe_d1(2),
O => \doutb[2]_INST_0_i_4_n_0\
);
\doutb[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F004F4F0F004040"
)
port map (
I0 => sel_pipe_d1(4),
I1 => \doutb[3]_INST_0_i_1_n_0\,
I2 => sel_pipe_d1(6),
I3 => \doutb[3]_INST_0_i_2_n_0\,
I4 => sel_pipe_d1(5),
I5 => \doutb[3]_INST_0_i_3_n_0\,
O => \^doutb\(3)
);
\doutb[3]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \doutb[3]_INST_0_i_4_n_0\,
I1 => sel_pipe_d1(3),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(0),
O => \doutb[3]_INST_0_i_1_n_0\
);
\doutb[3]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_12\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_13\(0),
O => \doutb[3]_INST_0_i_2_n_0\,
S => sel_pipe_d1(4)
);
\doutb[3]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_10\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_11\(0),
O => \doutb[3]_INST_0_i_3_n_0\,
S => sel_pipe_d1(4)
);
\doutb[3]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00003A0A"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\(1),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(3),
I4 => sel_pipe_d1(2),
O => \doutb[3]_INST_0_i_4_n_0\
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(2),
Q => sel_pipe_d1(2),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(3),
Q => sel_pipe_d1(3),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(4),
Q => sel_pipe_d1(4),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(5),
Q => sel_pipe_d1(5),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(6),
Q => sel_pipe_d1(6),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(1),
Q => sel_pipe(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(2),
Q => sel_pipe(2),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(3),
Q => sel_pipe(3),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(4),
Q => sel_pipe(4),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(5),
Q => sel_pipe(5),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(6),
Q => sel_pipe(6),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_prim_wrapper is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end blk_mem_gen_0_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_prim_wrapper is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized0\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized1\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized10\ is
port (
\doutb[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\addra_13__s_port_]\ : in STD_LOGIC;
clka : in STD_LOGIC;
\addrb[17]\ : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized10\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized10\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized10\ is
signal \addra_13__s_net_1\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\addra_13__s_net_1\ <= \addra_13__s_port_]\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \doutb[1]\(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \addra_13__s_net_1\,
ENBWREN => \addrb[17]\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized11\ is
port (
ENA : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\ : out STD_LOGIC;
ENB : out STD_LOGIC;
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 18 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
\addrb[17]\ : in STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized11\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized11\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized11\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_27_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_28_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_29_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8_n_0\ : STD_LOGIC;
signal \^device_7series.no_bmm_info.sdp.simple_prim18.ram\ : STD_LOGIC;
signal \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\ : STD_LOGIC;
signal \^ena\ : STD_LOGIC;
signal \^enb\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_27\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_28\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_29\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_3\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_4\ : label is "soft_lutpair3";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ <= \^device_7series.no_bmm_info.sdp.simple_prim18.ram\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\ <= \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\;
ENA <= \^ena\;
ENB <= \^enb\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena\,
ENBWREN => \^enb\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena\,
ENBWREN => \^enb\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4_n_0\,
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5_n_0\,
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6_n_0\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7_n_0\,
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8_n_0\,
O => \^ena\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000001000000"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\,
I1 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\,
I2 => addra(14),
I3 => addra(13),
I4 => wea(0),
I5 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000400000"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\,
I1 => addra(12),
I2 => wea(0),
I3 => addra(14),
I4 => addra(13),
I5 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\,
I1 => addra(13),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\,
I3 => wea(0),
I4 => addra(18),
I5 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\,
I1 => addra(12),
I2 => wea(0),
I3 => addra(13),
I4 => addra(14),
I5 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => addra(13),
I1 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\,
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\,
I3 => wea(0),
I4 => addra(18),
I5 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\,
I1 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\,
I2 => addra(13),
I3 => addra(12),
I4 => addra(14),
I5 => wea(0),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26_n_0\,
I1 => addra(15),
I2 => addra(17),
I3 => addra(16),
I4 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000080000000000"
)
port map (
I0 => addra(13),
I1 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\,
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\,
I3 => wea(0),
I4 => addra(18),
I5 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_27_n_0\,
I1 => addra(15),
I2 => addra(17),
I3 => addra(16),
I4 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000000"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\,
I1 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\,
I2 => addra(14),
I3 => addra(13),
I4 => wea(0),
I5 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => addrb(16),
I1 => \addrb[17]\,
O => \^enb\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\,
I1 => addra(13),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\,
I3 => wea(0),
I4 => addra(18),
I5 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\,
I1 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\,
I2 => addra(13),
I3 => addra(12),
I4 => addra(14),
I5 => wea(0),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_28_n_0\,
I1 => addra(15),
I2 => addra(17),
I3 => addra(16),
I4 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000400"
)
port map (
I0 => addra(13),
I1 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\,
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\,
I3 => wea(0),
I4 => addra(18),
I5 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_29_n_0\,
I1 => addra(15),
I2 => addra(17),
I3 => addra(16),
I4 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000010000000000"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\,
I1 => addra(13),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\,
I3 => wea(0),
I4 => addra(18),
I5 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => wea(0),
I1 => addra(14),
I2 => addra(12),
I3 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_27\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF7F"
)
port map (
I0 => wea(0),
I1 => addra(12),
I2 => addra(13),
I3 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_27_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_28\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => wea(0),
I1 => addra(12),
I2 => addra(13),
I3 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_28_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_29\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF7F"
)
port map (
I0 => wea(0),
I1 => addra(14),
I2 => addra(12),
I3 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_29_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"2AFF2A2A"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__2_n_0\,
I1 => addra(13),
I2 => addra(12),
I3 => addra(18),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"8AFF8A8A"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12_n_0\,
I1 => addra(13),
I2 => addra(12),
I3 => addra(18),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"8AFF8A8A"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14_n_0\,
I1 => addra(13),
I2 => addra(12),
I3 => addra(18),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFFFFFFFAFEFEFE"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17_n_0\,
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18_n_0\,
I3 => addra(12),
I4 => addra(13),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"2AFF2A2A"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20_n_0\,
I1 => addra(13),
I2 => addra(12),
I3 => addra(18),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFAFFFEFEFAFE"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23_n_0\,
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24_n_0\,
I3 => addra(12),
I4 => addra(13),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => addra(16),
I1 => addra(15),
I2 => addra(17),
O => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => addra(16),
I1 => addra(17),
O => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized12\ is
port (
ENA : out STD_LOGIC;
ENB : out STD_LOGIC;
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 18 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\addra_13__s_port_\ : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized12\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized12\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized12\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0\ : STD_LOGIC;
signal \^ena\ : STD_LOGIC;
signal \^enb\ : STD_LOGIC;
signal \addra_13__s_net_1\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1\ : label is "soft_lutpair8";
begin
ENA <= \^ena\;
ENB <= \^enb\;
\addra_13__s_net_1\ <= \addra_13__s_port_\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena\,
ENBWREN => \^enb\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena\,
ENBWREN => \^enb\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => addra(17),
I1 => addra(16),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0\,
I2 => addra(13),
I3 => addra(14),
I4 => wea(0),
I5 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0\,
I2 => addra(13),
I3 => addra(12),
I4 => addra(14),
I5 => wea(0),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0\,
I2 => addra(13),
I3 => addra(12),
I4 => addra(14),
I5 => wea(0),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000070000000"
)
port map (
I0 => addra(12),
I1 => addra(13),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23__0_n_0\,
I3 => addra(15),
I4 => addra(16),
I5 => addra(17),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400000000000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0\,
I2 => addra(14),
I3 => addra(13),
I4 => addra(12),
I5 => wea(0),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000070000000"
)
port map (
I0 => addra(12),
I1 => addra(13),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24__0_n_0\,
I3 => addra(15),
I4 => addra(16),
I5 => addra(17),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000010000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0\,
I2 => addra(13),
I3 => addra(14),
I4 => wea(0),
I5 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0\,
I2 => addra(13),
I3 => addra(12),
I4 => addra(14),
I5 => wea(0),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000000000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0\,
I2 => addra(14),
I3 => addra(13),
I4 => addra(12),
I5 => wea(0),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__2_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__0_n_0\,
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__2_n_0\,
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__1_n_0\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__2_n_0\,
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__2_n_0\,
O => \^ena\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000D0000000"
)
port map (
I0 => addra(12),
I1 => addra(13),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25__0_n_0\,
I3 => addra(15),
I4 => addra(16),
I5 => addra(17),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0\,
I2 => addra(13),
I3 => addra(12),
I4 => addra(14),
I5 => wea(0),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000D00000"
)
port map (
I0 => addra(12),
I1 => addra(13),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26__0_n_0\,
I3 => addra(15),
I4 => addra(16),
I5 => addra(17),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => addra(18),
I1 => wea(0),
I2 => addra(14),
I3 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_23__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => addra(18),
I1 => wea(0),
I2 => addra(13),
I3 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_24__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => addra(18),
I1 => wea(0),
I2 => addra(14),
I3 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_25__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => addra(18),
I1 => wea(0),
I2 => addra(14),
I3 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_26__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addrb(17),
I1 => addrb(16),
I2 => addrb(18),
O => \^enb\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addra(18),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0\,
I2 => wea(0),
I3 => \addra_13__s_net_1\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000010000"
)
port map (
I0 => addra(13),
I1 => addra(14),
I2 => addra(18),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0\,
I4 => wea(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8AFF8A8A"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__2_n_0\,
I1 => addra(13),
I2 => addra(12),
I3 => addra(18),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__2_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFCCFE"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__2_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__2_n_0\,
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__0_n_0\,
I3 => addra(18),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__1_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"2AFF2A2A"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__2_n_0\,
I1 => addra(13),
I2 => addra(12),
I3 => addra(18),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__2_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFCCFE"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__2_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__0_n_0\,
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_21__0_n_0\,
I3 => addra(18),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_22__0_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => addra(16),
I1 => addra(15),
I2 => addra(17),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized13\ is
port (
ENA : out STD_LOGIC;
ENB : out STD_LOGIC;
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 18 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\addra_13__s_port_\ : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized13\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized13\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized13\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0\ : STD_LOGIC;
signal \^ena\ : STD_LOGIC;
signal \^enb\ : STD_LOGIC;
signal \addra_13__s_net_1\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9\ : label is "soft_lutpair10";
begin
ENA <= \^ena\;
ENB <= \^enb\;
\addra_13__s_net_1\ <= \addra_13__s_port_\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena\,
ENBWREN => \^enb\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena\,
ENBWREN => \^enb\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => addra(16),
I1 => addra(17),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0\,
I2 => addra(13),
I3 => addra(14),
I4 => wea(0),
I5 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000008000000"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(13),
I3 => addra(14),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0\,
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(13),
I3 => addra(14),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0\,
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0\,
I2 => addra(13),
I3 => addra(14),
I4 => wea(0),
I5 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => addra(18),
I1 => wea(0),
I2 => \addra_13__s_net_1\,
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000010000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0\,
I2 => addra(13),
I3 => addra(14),
I4 => wea(0),
I5 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0\,
I1 => addra(12),
I2 => wea(0),
I3 => addra(13),
I4 => addra(14),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000080000"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(13),
I3 => addra(14),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0\,
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000040000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0\,
I2 => addra(13),
I3 => addra(14),
I4 => wea(0),
I5 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__0_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__1_n_0\,
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__1_n_0\,
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__0_n_0\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__0_n_0\,
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__1_n_0\,
O => \^ena\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000040000"
)
port map (
I0 => addra(13),
I1 => addra(14),
I2 => addra(18),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0\,
I4 => wea(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addrb(16),
I1 => addrb(17),
I2 => addrb(18),
O => \^enb\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addra(18),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0\,
I2 => wea(0),
I3 => \addra_13__s_net_1\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000010000"
)
port map (
I0 => addra(13),
I1 => addra(14),
I2 => addra(18),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0\,
I4 => wea(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__0_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8AFF8A8A"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__0_n_0\,
I1 => addra(13),
I2 => addra(12),
I3 => addra(18),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__1_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF2FFF2222"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__0_n_0\,
I1 => addra(18),
I2 => addra(12),
I3 => addra(13),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__0_n_0\,
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__1_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2AFF2A2A"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__0_n_0\,
I1 => addra(13),
I2 => addra(12),
I3 => addra(18),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__0_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF2F2222"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__1_n_0\,
I1 => addra(18),
I2 => addra(12),
I3 => addra(13),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__1_n_0\,
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__1_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => addra(16),
I1 => addra(15),
I2 => addra(17),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized14\ is
port (
ENA : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC;
ENB : out STD_LOGIC;
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 18 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized14\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized14\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized14\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0\ : STD_LOGIC;
signal \^device_7series.no_bmm_info.sdp.simple_prim18.ram\ : STD_LOGIC;
signal \^ena\ : STD_LOGIC;
signal \^enb\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0\ : label is "soft_lutpair12";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ <= \^device_7series.no_bmm_info.sdp.simple_prim18.ram\;
ENA <= \^ena\;
ENB <= \^enb\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena\,
ENBWREN => \^enb\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena\,
ENBWREN => \^enb\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => addra(16),
I1 => addra(17),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0\,
I2 => addra(13),
I3 => addra(14),
I4 => wea(0),
I5 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000008000000"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(13),
I3 => addra(14),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0\,
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(13),
I3 => addra(14),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0\,
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0\,
I2 => addra(13),
I3 => addra(14),
I4 => wea(0),
I5 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => addra(18),
I1 => wea(0),
I2 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\,
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000010000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0\,
I2 => addra(13),
I3 => addra(14),
I4 => wea(0),
I5 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0\,
I1 => addra(12),
I2 => wea(0),
I3 => addra(13),
I4 => addra(14),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000080000"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(13),
I3 => addra(14),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0\,
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000040000"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0\,
I2 => addra(13),
I3 => addra(14),
I4 => wea(0),
I5 => addra(18),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__1_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__2_n_0\,
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__0_n_0\,
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__2_n_0\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__1_n_0\,
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__0_n_0\,
O => \^ena\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000040000"
)
port map (
I0 => addra(13),
I1 => addra(14),
I2 => addra(18),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0\,
I4 => wea(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_2__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => addrb(16),
I1 => addrb(17),
I2 => addrb(18),
O => \^enb\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addra(18),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0\,
I2 => wea(0),
I3 => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\,
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_3__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000010000"
)
port map (
I0 => addra(13),
I1 => addra(14),
I2 => addra(18),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0\,
I4 => wea(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_10__1_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_4__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8AFF8A8A"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_11__1_n_0\,
I1 => addra(13),
I2 => addra(12),
I3 => addra(18),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_12__0_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_5__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF2FFF2222"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_13__1_n_0\,
I1 => addra(18),
I2 => addra(12),
I3 => addra(13),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_14__1_n_0\,
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_15__2_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_6__2_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2AFF2A2A"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_16__2_n_0\,
I1 => addra(13),
I2 => addra(12),
I3 => addra(18),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_17__1_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_7__1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF2F2222"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_18__0_n_0\,
I1 => addra(18),
I2 => addra(12),
I3 => addra(13),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_19__0_n_0\,
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_20__2_n_0\,
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_8__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => addra(16),
I1 => addra(15),
I2 => addra(17),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => addra(14),
I1 => addra(13),
O => \^device_7series.no_bmm_info.sdp.simple_prim18.ram\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized15\ is
port (
\doutb[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\ : out STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
\addra[17]\ : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\addra_13__s_port_\ : in STD_LOGIC;
\addra[17]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized15\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized15\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized15\ is
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram_0\ : STD_LOGIC;
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram_1\ : STD_LOGIC;
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram_2\ : STD_LOGIC;
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram_3\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_5_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_6_n_0\ : STD_LOGIC;
signal \addra_13__s_net_1\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__2\ : label is "soft_lutpair13";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_7\ : label is "soft_lutpair13";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram_0\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram_1\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram_2\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\ <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram_3\;
\addra_13__s_net_1\ <= \addra_13__s_port_\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_9__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => addrb(16),
I1 => addrb(17),
O => \^device_7series.no_bmm_info.sdp.simple_prim36.ram_2\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \doutb[2]\(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^device_7series.no_bmm_info.sdp.simple_prim36.ram_0\,
ENBWREN => \^device_7series.no_bmm_info.sdp.simple_prim36.ram_1\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3_n_0\,
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0\,
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_5_n_0\,
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_6_n_0\,
O => \^device_7series.no_bmm_info.sdp.simple_prim36.ram_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => addrb(18),
I1 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram_2\,
I2 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram_3\,
O => \^device_7series.no_bmm_info.sdp.simple_prim36.ram_1\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000010000000000"
)
port map (
I0 => addra(13),
I1 => addra(14),
I2 => \addra[17]\,
I3 => wea(0),
I4 => \addra[17]_0\,
I5 => addra(15),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000080000000000"
)
port map (
I0 => addra(13),
I1 => addra(14),
I2 => \addra[17]\,
I3 => wea(0),
I4 => \addra[17]_0\,
I5 => addra(15),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_4_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00040000"
)
port map (
I0 => \addra[17]\,
I1 => wea(0),
I2 => \addra_13__s_net_1\,
I3 => \addra[17]_0\,
I4 => addra(15),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_5_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040000000000"
)
port map (
I0 => addra(13),
I1 => addra(14),
I2 => \addra[17]\,
I3 => wea(0),
I4 => \addra[17]_0\,
I5 => addra(15),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_6_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => addrb(16),
I1 => addrb(15),
I2 => addrb(17),
O => \^device_7series.no_bmm_info.sdp.simple_prim36.ram_3\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized16\ is
port (
\doutb[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
\addra[17]\ : in STD_LOGIC;
\addrb[17]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized16\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized16\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized16\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(13 downto 1) => addra(12 downto 0),
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13 downto 1) => addrb(12 downto 0),
ADDRBWRADDR(0) => '0',
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 2),
DOBDO(1 downto 0) => \doutb[3]\(1 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \addra[17]\,
ENBWREN => \addrb[17]\,
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized17\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized17\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized17\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized17\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized18\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized18\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized18\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized18\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized19\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized19\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized19\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized19\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
\wea[0]\ : in STD_LOGIC;
clka : in STD_LOGIC;
\addrb[18]\ : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized2\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \wea[0]\,
ENBWREN => \addrb[18]\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \wea[0]\,
ENBWREN => \addrb[18]\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized20\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized20\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized20\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized20\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized21\ is
port (
\doutb[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\addra_13__s_port_]\ : in STD_LOGIC;
clka : in STD_LOGIC;
\addrb[17]\ : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized21\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized21\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized21\ is
signal \addra_13__s_net_1\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\addra_13__s_net_1\ <= \addra_13__s_port_]\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \doutb[3]\(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \addra_13__s_net_1\,
ENBWREN => \addrb[17]\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
\doutb[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\addra_13__s_port_]\ : in STD_LOGIC;
clka : in STD_LOGIC;
\addrb[17]\ : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \addra_13__s_net_1\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\addra_13__s_net_1\ <= \addra_13__s_port_]\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 0) => addra(14 downto 0),
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 0) => addrb(14 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => \doutb[0]\(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \addra_13__s_net_1\,
ENBWREN => \addrb[17]\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
DOBDO : out STD_LOGIC_VECTOR ( 1 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\ : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_1\ : out STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\addra[17]\ : in STD_LOGIC;
\addra[17]_0\ : in STD_LOGIC;
\addrb[17]\ : in STD_LOGIC;
\addrb[17]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\ : STD_LOGIC;
signal \^device_7series.no_bmm_info.sdp.simple_prim18.ram_1\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\ <= \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_1\ <= \^device_7series.no_bmm_info.sdp.simple_prim18.ram_1\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(13 downto 1) => addra(12 downto 0),
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13 downto 1) => addrb(12 downto 0),
ADDRBWRADDR(0) => '0',
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 2),
DOBDO(1 downto 0) => DOBDO(1 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\,
ENBWREN => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_1\,
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000100000000000"
)
port map (
I0 => addra(13),
I1 => addra(14),
I2 => wea(0),
I3 => \addra[17]\,
I4 => \addra[17]_0\,
I5 => addra(15),
O => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00100000"
)
port map (
I0 => addrb(14),
I1 => addrb(13),
I2 => \addrb[17]\,
I3 => \addrb[17]_0\,
I4 => addrb(15),
O => \^device_7series.no_bmm_info.sdp.simple_prim18.ram_1\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
\doutb[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
\addra[17]\ : in STD_LOGIC;
\addra[17]_0\ : in STD_LOGIC;
\addra_13__s_port_\ : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\addrb[17]\ : in STD_LOGIC;
\addrb[17]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_4__0_n_0\ : STD_LOGIC;
signal \addra_13__s_net_1\ : STD_LOGIC;
signal ram_ena : STD_LOGIC;
signal ram_enb : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\addra_13__s_net_1\ <= \addra_13__s_port_\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13 downto 2) => addrb(11 downto 0),
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 4),
DOBDO(3 downto 0) => \doutb[3]\(3 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ram_ena,
ENBWREN => ram_enb,
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => addra(15),
I1 => \addra[17]\,
I2 => \addra[17]_0\,
I3 => \addra_13__s_net_1\,
I4 => wea(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_4__0_n_0\,
O => ram_ena
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000002000"
)
port map (
I0 => addrb(15),
I1 => \addrb[17]\,
I2 => \addrb[17]_0\,
I3 => addrb(13),
I4 => addrb(12),
I5 => addrb(14),
O => ram_enb
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => addra(13),
I1 => addra(12),
I2 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized6\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized7\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized7\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized7\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized7\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized8\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized8\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized8\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized8\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized9\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized9\ : entity is "blk_mem_gen_prim_wrapper";
end \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized9\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized9\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => dina(0),
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3) => '1',
WEA(2) => '1',
WEA(1) => '1',
WEA(0) => '1',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_prim_width is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end blk_mem_gen_0_blk_mem_gen_prim_width;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.blk_mem_gen_0_blk_mem_gen_prim_wrapper
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized0\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized0\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized1\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized1\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized10\ is
port (
\doutb[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\addra_13__s_port_]\ : in STD_LOGIC;
clka : in STD_LOGIC;
\addrb[17]\ : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized10\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized10\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized10\ is
signal \addra_13__s_net_1\ : STD_LOGIC;
begin
\addra_13__s_net_1\ <= \addra_13__s_port_]\;
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized10\
port map (
addra(14 downto 0) => addra(14 downto 0),
\addra_13__s_port_]\ => \addra_13__s_net_1\,
addrb(14 downto 0) => addrb(14 downto 0),
\addrb[17]\ => \addrb[17]\,
clka => clka,
clkb => clkb,
dina(0) => dina(0),
\doutb[1]\(0) => \doutb[1]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized11\ is
port (
ENA : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\ : out STD_LOGIC;
ENB : out STD_LOGIC;
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 18 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
\addrb[17]\ : in STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized11\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized11\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized11\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized11\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\,
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(18 downto 0) => addra(18 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
\addrb[17]\ => \addrb[17]\,
clka => clka,
clkb => clkb,
dina(0) => dina(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized12\ is
port (
ENA : out STD_LOGIC;
ENB : out STD_LOGIC;
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 18 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\addra_13__s_port_\ : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized12\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized12\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized12\ is
signal \addra_13__s_net_1\ : STD_LOGIC;
begin
\addra_13__s_net_1\ <= \addra_13__s_port_\;
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized12\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(18 downto 0) => addra(18 downto 0),
\addra_13__s_port_\ => \addra_13__s_net_1\,
addrb(18 downto 0) => addrb(18 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized13\ is
port (
ENA : out STD_LOGIC;
ENB : out STD_LOGIC;
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 18 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\addra_13__s_port_\ : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized13\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized13\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized13\ is
signal \addra_13__s_net_1\ : STD_LOGIC;
begin
\addra_13__s_net_1\ <= \addra_13__s_port_\;
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized13\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(18 downto 0) => addra(18 downto 0),
\addra_13__s_port_\ => \addra_13__s_net_1\,
addrb(18 downto 0) => addrb(18 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized14\ is
port (
ENA : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC;
ENB : out STD_LOGIC;
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 18 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized14\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized14\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized14\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized14\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\,
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(18 downto 0) => addra(18 downto 0),
addrb(18 downto 0) => addrb(18 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized15\ is
port (
\doutb[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : out STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
\addra[17]\ : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\addra_13__s_port_\ : in STD_LOGIC;
\addra[17]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized15\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized15\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized15\ is
signal \addra_13__s_net_1\ : STD_LOGIC;
begin
\addra_13__s_net_1\ <= \addra_13__s_port_\;
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized15\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\,
addra(15 downto 0) => addra(15 downto 0),
\addra[17]\ => \addra[17]\,
\addra[17]_0\ => \addra[17]_0\,
\addra_13__s_port_\ => \addra_13__s_net_1\,
addrb(18 downto 0) => addrb(18 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
\doutb[2]\(0) => \doutb[2]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized16\ is
port (
\doutb[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
\addra[17]\ : in STD_LOGIC;
\addrb[17]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized16\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized16\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized16\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized16\
port map (
addra(12 downto 0) => addra(12 downto 0),
\addra[17]\ => \addra[17]\,
addrb(12 downto 0) => addrb(12 downto 0),
\addrb[17]\ => \addrb[17]\,
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
\doutb[3]\(1 downto 0) => \doutb[3]\(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized17\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized17\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized17\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized17\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized17\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized18\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized18\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized18\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized18\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized18\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized19\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized19\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized19\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized19\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized19\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized2\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
\wea[0]\ : in STD_LOGIC;
clka : in STD_LOGIC;
\addrb[18]\ : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized2\
port map (
DOUTB(0) => DOUTB(0),
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
\addrb[18]\ => \addrb[18]\,
clka => clka,
clkb => clkb,
dina(0) => dina(0),
\wea[0]\ => \wea[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized20\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized20\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized20\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized20\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized20\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized21\ is
port (
\doutb[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\addra_13__s_port_]\ : in STD_LOGIC;
clka : in STD_LOGIC;
\addrb[17]\ : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized21\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized21\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized21\ is
signal \addra_13__s_net_1\ : STD_LOGIC;
begin
\addra_13__s_net_1\ <= \addra_13__s_port_]\;
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized21\
port map (
addra(14 downto 0) => addra(14 downto 0),
\addra_13__s_port_]\ => \addra_13__s_net_1\,
addrb(14 downto 0) => addrb(14 downto 0),
\addrb[17]\ => \addrb[17]\,
clka => clka,
clkb => clkb,
dina(0) => dina(0),
\doutb[3]\(0) => \doutb[3]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized3\ is
port (
\doutb[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\addra_13__s_port_]\ : in STD_LOGIC;
clka : in STD_LOGIC;
\addrb[17]\ : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized3\ is
signal \addra_13__s_net_1\ : STD_LOGIC;
begin
\addra_13__s_net_1\ <= \addra_13__s_port_]\;
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized3\
port map (
addra(14 downto 0) => addra(14 downto 0),
\addra_13__s_port_]\ => \addra_13__s_net_1\,
addrb(14 downto 0) => addrb(14 downto 0),
\addrb[17]\ => \addrb[17]\,
clka => clka,
clkb => clkb,
dina(0) => dina(0),
\doutb[0]\(0) => \doutb[0]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized4\ is
port (
DOBDO : out STD_LOGIC_VECTOR ( 1 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\ : out STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\addra[17]\ : in STD_LOGIC;
\addra[17]_0\ : in STD_LOGIC;
\addrb[17]\ : in STD_LOGIC;
\addrb[17]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized4\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_1\ => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\,
DOBDO(1 downto 0) => DOBDO(1 downto 0),
addra(15 downto 0) => addra(15 downto 0),
\addra[17]\ => \addra[17]\,
\addra[17]_0\ => \addra[17]_0\,
addrb(15 downto 0) => addrb(15 downto 0),
\addrb[17]\ => \addrb[17]\,
\addrb[17]_0\ => \addrb[17]_0\,
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized5\ is
port (
\doutb[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
\addra[17]\ : in STD_LOGIC;
\addra[17]_0\ : in STD_LOGIC;
\addra_13__s_port_\ : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\addrb[17]\ : in STD_LOGIC;
\addrb[17]_0\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized5\ is
signal \addra_13__s_net_1\ : STD_LOGIC;
begin
\addra_13__s_net_1\ <= \addra_13__s_port_\;
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized5\
port map (
addra(15 downto 0) => addra(15 downto 0),
\addra[17]\ => \addra[17]\,
\addra[17]_0\ => \addra[17]_0\,
\addra_13__s_port_\ => \addra_13__s_net_1\,
addrb(15 downto 0) => addrb(15 downto 0),
\addrb[17]\ => \addrb[17]\,
\addrb[17]_0\ => \addrb[17]_0\,
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(3 downto 0),
\doutb[3]\(3 downto 0) => \doutb[3]\(3 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized6\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized6\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized7\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized7\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized8\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized8\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized9\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
ENA : in STD_LOGIC;
clka : in STD_LOGIC;
ENB : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized9\ : entity is "blk_mem_gen_prim_width";
end \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized9\;
architecture STRUCTURE of \blk_mem_gen_0_blk_mem_gen_prim_width__parameterized9\ is
begin
\prim_noinit.ram\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_wrapper__parameterized9\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 18 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end blk_mem_gen_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_generic_cstr is
signal \ramloop[0].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_0\ : STD_LOGIC;
begin
\has_mux_b.B\: entity work.\blk_mem_gen_0_blk_mem_gen_mux__parameterized0\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\(0) => \ramloop[1].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0\(0) => \ramloop[2].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_1\(0) => \ramloop[3].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_10\(0) => \ramloop[18].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_11\(0) => \ramloop[19].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_12\(0) => \ramloop[20].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_13\(0) => \ramloop[21].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_2\(0) => \ramloop[7].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_3\(0) => \ramloop[8].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_4\(0) => \ramloop[9].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_5\(0) => \ramloop[10].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_6\(0) => \ramloop[12].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_7\(0) => \ramloop[13].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_8\(0) => \ramloop[14].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_9\(0) => \ramloop[15].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(3) => \ramloop[6].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(2) => \ramloop[6].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(1) => \ramloop[6].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\(0) => \ramloop[6].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\(1) => \ramloop[17].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\(0) => \ramloop[17].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[11].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[16].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[22].ram.r_n_0\,
DOBDO(1) => \ramloop[5].ram.r_n_0\,
DOBDO(0) => \ramloop[5].ram.r_n_1\,
DOUTB(0) => \ramloop[0].ram.r_n_0\,
addrb(6 downto 0) => addrb(18 downto 12),
clkb => clkb,
\^doutb\(3 downto 0) => doutb(3 downto 0)
);
\ramloop[0].ram.r\: entity work.blk_mem_gen_0_blk_mem_gen_prim_width
port map (
DOUTB(0) => \ramloop[0].ram.r_n_0\,
ENA => \ramloop[12].ram.r_n_0\,
ENB => \ramloop[12].ram.r_n_3\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
\ramloop[10].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized9\
port map (
DOUTB(0) => \ramloop[10].ram.r_n_0\,
ENA => \ramloop[15].ram.r_n_0\,
ENB => \ramloop[15].ram.r_n_2\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(1)
);
\ramloop[11].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized10\
port map (
addra(14 downto 0) => addra(14 downto 0),
\addra_13__s_port_]\ => \ramloop[16].ram.r_n_1\,
addrb(14 downto 0) => addrb(14 downto 0),
\addrb[17]\ => \ramloop[16].ram.r_n_2\,
clka => clka,
clkb => clkb,
dina(0) => dina(1),
\doutb[1]\(0) => \ramloop[11].ram.r_n_0\
);
\ramloop[12].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized11\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ => \ramloop[12].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\ => \ramloop[12].ram.r_n_2\,
DOUTB(0) => \ramloop[12].ram.r_n_4\,
ENA => \ramloop[12].ram.r_n_0\,
ENB => \ramloop[12].ram.r_n_3\,
addra(18 downto 0) => addra(18 downto 0),
addrb(16) => addrb(18),
addrb(15 downto 0) => addrb(15 downto 0),
\addrb[17]\ => \ramloop[16].ram.r_n_3\,
clka => clka,
clkb => clkb,
dina(0) => dina(2),
wea(0) => wea(0)
);
\ramloop[13].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized12\
port map (
DOUTB(0) => \ramloop[13].ram.r_n_2\,
ENA => \ramloop[13].ram.r_n_0\,
ENB => \ramloop[13].ram.r_n_1\,
addra(18 downto 0) => addra(18 downto 0),
\addra_13__s_port_\ => \ramloop[15].ram.r_n_1\,
addrb(18 downto 0) => addrb(18 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(2),
wea(0) => wea(0)
);
\ramloop[14].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized13\
port map (
DOUTB(0) => \ramloop[14].ram.r_n_2\,
ENA => \ramloop[14].ram.r_n_0\,
ENB => \ramloop[14].ram.r_n_1\,
addra(18 downto 0) => addra(18 downto 0),
\addra_13__s_port_\ => \ramloop[15].ram.r_n_1\,
addrb(18 downto 0) => addrb(18 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(2),
wea(0) => wea(0)
);
\ramloop[15].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized14\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ => \ramloop[15].ram.r_n_1\,
DOUTB(0) => \ramloop[15].ram.r_n_3\,
ENA => \ramloop[15].ram.r_n_0\,
ENB => \ramloop[15].ram.r_n_2\,
addra(18 downto 0) => addra(18 downto 0),
addrb(18 downto 0) => addrb(18 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(2),
wea(0) => wea(0)
);
\ramloop[16].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized15\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ => \ramloop[16].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ => \ramloop[16].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ => \ramloop[16].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ => \ramloop[16].ram.r_n_4\,
addra(15) => addra(18),
addra(14 downto 0) => addra(14 downto 0),
\addra[17]\ => \ramloop[12].ram.r_n_1\,
\addra[17]_0\ => \ramloop[12].ram.r_n_2\,
\addra_13__s_port_\ => \ramloop[15].ram.r_n_1\,
addrb(18 downto 0) => addrb(18 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(2),
\doutb[2]\(0) => \ramloop[16].ram.r_n_0\,
wea(0) => wea(0)
);
\ramloop[17].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized16\
port map (
addra(12 downto 0) => addra(12 downto 0),
\addra[17]\ => \ramloop[5].ram.r_n_2\,
addrb(12 downto 0) => addrb(12 downto 0),
\addrb[17]\ => \ramloop[5].ram.r_n_3\,
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(3 downto 2),
\doutb[3]\(1) => \ramloop[17].ram.r_n_0\,
\doutb[3]\(0) => \ramloop[17].ram.r_n_1\
);
\ramloop[18].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized17\
port map (
DOUTB(0) => \ramloop[18].ram.r_n_0\,
ENA => \ramloop[12].ram.r_n_0\,
ENB => \ramloop[12].ram.r_n_3\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(3)
);
\ramloop[19].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized18\
port map (
DOUTB(0) => \ramloop[19].ram.r_n_0\,
ENA => \ramloop[13].ram.r_n_0\,
ENB => \ramloop[13].ram.r_n_1\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(3)
);
\ramloop[1].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized0\
port map (
DOUTB(0) => \ramloop[1].ram.r_n_0\,
ENA => \ramloop[13].ram.r_n_0\,
ENB => \ramloop[13].ram.r_n_1\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
\ramloop[20].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized19\
port map (
DOUTB(0) => \ramloop[20].ram.r_n_0\,
ENA => \ramloop[14].ram.r_n_0\,
ENB => \ramloop[14].ram.r_n_1\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(3)
);
\ramloop[21].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized20\
port map (
DOUTB(0) => \ramloop[21].ram.r_n_0\,
ENA => \ramloop[15].ram.r_n_0\,
ENB => \ramloop[15].ram.r_n_2\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(3)
);
\ramloop[22].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized21\
port map (
addra(14 downto 0) => addra(14 downto 0),
\addra_13__s_port_]\ => \ramloop[16].ram.r_n_1\,
addrb(14 downto 0) => addrb(14 downto 0),
\addrb[17]\ => \ramloop[16].ram.r_n_2\,
clka => clka,
clkb => clkb,
dina(0) => dina(3),
\doutb[3]\(0) => \ramloop[22].ram.r_n_0\
);
\ramloop[2].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized1\
port map (
DOUTB(0) => \ramloop[2].ram.r_n_0\,
ENA => \ramloop[14].ram.r_n_0\,
ENB => \ramloop[14].ram.r_n_1\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
\ramloop[3].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized2\
port map (
DOUTB(0) => \ramloop[3].ram.r_n_0\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
\addrb[18]\ => \ramloop[15].ram.r_n_2\,
clka => clka,
clkb => clkb,
dina(0) => dina(0),
\wea[0]\ => \ramloop[15].ram.r_n_0\
);
\ramloop[4].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized3\
port map (
addra(14 downto 0) => addra(14 downto 0),
\addra_13__s_port_]\ => \ramloop[16].ram.r_n_1\,
addrb(14 downto 0) => addrb(14 downto 0),
\addrb[17]\ => \ramloop[16].ram.r_n_2\,
clka => clka,
clkb => clkb,
dina(0) => dina(0),
\doutb[0]\(0) => \ramloop[4].ram.r_n_0\
);
\ramloop[5].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized4\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ => \ramloop[5].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_0\ => \ramloop[5].ram.r_n_3\,
DOBDO(1) => \ramloop[5].ram.r_n_0\,
DOBDO(0) => \ramloop[5].ram.r_n_1\,
addra(15) => addra(18),
addra(14 downto 0) => addra(14 downto 0),
\addra[17]\ => \ramloop[12].ram.r_n_1\,
\addra[17]_0\ => \ramloop[12].ram.r_n_2\,
addrb(15) => addrb(18),
addrb(14 downto 0) => addrb(14 downto 0),
\addrb[17]\ => \ramloop[16].ram.r_n_4\,
\addrb[17]_0\ => \ramloop[16].ram.r_n_3\,
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
wea(0) => wea(0)
);
\ramloop[6].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized5\
port map (
addra(15) => addra(18),
addra(14 downto 0) => addra(14 downto 0),
\addra[17]\ => \ramloop[12].ram.r_n_2\,
\addra[17]_0\ => \ramloop[12].ram.r_n_1\,
\addra_13__s_port_\ => \ramloop[15].ram.r_n_1\,
addrb(15) => addrb(18),
addrb(14 downto 0) => addrb(14 downto 0),
\addrb[17]\ => \ramloop[16].ram.r_n_3\,
\addrb[17]_0\ => \ramloop[16].ram.r_n_4\,
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(3 downto 0),
\doutb[3]\(3) => \ramloop[6].ram.r_n_0\,
\doutb[3]\(2) => \ramloop[6].ram.r_n_1\,
\doutb[3]\(1) => \ramloop[6].ram.r_n_2\,
\doutb[3]\(0) => \ramloop[6].ram.r_n_3\,
wea(0) => wea(0)
);
\ramloop[7].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized6\
port map (
DOUTB(0) => \ramloop[7].ram.r_n_0\,
ENA => \ramloop[12].ram.r_n_0\,
ENB => \ramloop[12].ram.r_n_3\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(1)
);
\ramloop[8].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized7\
port map (
DOUTB(0) => \ramloop[8].ram.r_n_0\,
ENA => \ramloop[13].ram.r_n_0\,
ENB => \ramloop[13].ram.r_n_1\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(1)
);
\ramloop[9].ram.r\: entity work.\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized8\
port map (
DOUTB(0) => \ramloop[9].ram.r_n_0\,
ENA => \ramloop[14].ram.r_n_0\,
ENB => \ramloop[14].ram.r_n_1\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 18 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_top : entity is "blk_mem_gen_top";
end blk_mem_gen_0_blk_mem_gen_top;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_top is
begin
\valid.cstr\: entity work.blk_mem_gen_0_blk_mem_gen_generic_cstr
port map (
addra(18 downto 0) => addra(18 downto 0),
addrb(18 downto 0) => addrb(18 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(3 downto 0),
doutb(3 downto 0) => doutb(3 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_v8_2_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 18 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end blk_mem_gen_0_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.blk_mem_gen_0_blk_mem_gen_top
port map (
addra(18 downto 0) => addra(18 downto 0),
addrb(18 downto 0) => addrb(18 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(3 downto 0),
doutb(3 downto 0) => doutb(3 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_v8_2 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 18 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 18 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 18 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 19;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 19;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "3";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "36";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "Estimated Power for IP : 16.198881 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 307200;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 307200;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 4;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 4;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 307200;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 307200;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "NO_CHANGE";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 4;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is 4;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "blk_mem_gen_v8_2";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of blk_mem_gen_0_blk_mem_gen_v8_2 : entity is "yes";
end blk_mem_gen_0_blk_mem_gen_v8_2;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_v8_2 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
rdaddrecc(18) <= \<const0>\;
rdaddrecc(17) <= \<const0>\;
rdaddrecc(16) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(18) <= \<const0>\;
s_axi_rdaddrecc(17) <= \<const0>\;
s_axi_rdaddrecc(16) <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.blk_mem_gen_0_blk_mem_gen_v8_2_synth
port map (
addra(18 downto 0) => addra(18 downto 0),
addrb(18 downto 0) => addrb(18 downto 0),
clka => clka,
clkb => clkb,
dina(3 downto 0) => dina(3 downto 0),
doutb(3 downto 0) => doutb(3 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0 is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 18 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
clkb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 18 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of blk_mem_gen_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of blk_mem_gen_0 : entity is "blk_mem_gen_0,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of blk_mem_gen_0 : entity is "blk_mem_gen_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=4,C_READ_WIDTH_A=4,C_WRITE_DEPTH_A=307200,C_READ_DEPTH_A=307200,C_ADDRA_WIDTH=19,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=4,C_READ_WIDTH_B=4,C_WRITE_DEPTH_B=307200,C_READ_DEPTH_B=307200,C_ADDRB_WIDTH=19,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=36,C_COUNT_18K_BRAM=3,C_EST_POWER_SUMMARY=Estimated Power for IP _ 16.198881 mW}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of blk_mem_gen_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of blk_mem_gen_0 : entity is "blk_mem_gen_v8_2,Vivado 2015.2";
end blk_mem_gen_0;
architecture STRUCTURE of blk_mem_gen_0 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 18 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 18 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 19;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 19;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "3";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "36";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 16.198881 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 307200;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 307200;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 4;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 4;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 307200;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 307200;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "NO_CHANGE";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 4;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 4;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.blk_mem_gen_0_blk_mem_gen_v8_2
port map (
addra(18 downto 0) => addra(18 downto 0),
addrb(18 downto 0) => addrb(18 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(3 downto 0) => dina(3 downto 0),
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(3 downto 0) => NLW_U0_douta_UNCONNECTED(3 downto 0),
doutb(3 downto 0) => doutb(3 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(18 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(18 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(18 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(18 downto 0),
s_axi_rdata(3 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(3 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
package pack1 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
package pack2 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
use work.pack1;
use work.pack2;
entity no_use_clause is
port (
a : in pack1.my_int1;
b : out pack2.my_int1 );
end entity;
-------------------------------------------------------------------------------
architecture a of no_use_clause is
type my_int1 is range 10 to 50;
begin
process is
begin
-- Should fail as types have same name but from different packages
b <= a;
end process;
process is
variable v : pack2.my_int1;
begin
b <= v; -- OK
end process;
process is
variable v : my_int1;
begin
-- Should fail as local my_int1 distinct from pack1.my_int1
v := a;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack1.all;
entity foo is
generic ( g : my_int1 );
port ( p : in my_int1 );
end entity;
-------------------------------------------------------------------------------
architecture a of foo is
-- Architecture decls exist in same scope as entity so this should
-- generate an error
signal g : my_int1;
begin
end architecture;
-------------------------------------------------------------------------------
architecture b of foo is
-- Should also generate an error
signal p : my_int1;
begin
end architecture;
-------------------------------------------------------------------------------
architecture c of foo is
begin
-- This is OK as processes define a new scope
process is
variable p : my_int1;
variable g : my_int1;
begin
g := 6;
p := 2;
wait for 1 ns;
end process;
end architecture;
-------------------------------------------------------------------------------
entity overload is
port (
SI: in bit;
SO: out bit
);
end ;
architecture behave of overload is
begin
foo_inst:
SO <= SI;
end behave;
-------------------------------------------------------------------------------
use work.all;
entity no_use_clause is
port (
a : in pack1.my_int1; -- OK
b : out my_int1 ); -- Error
end entity;
-------------------------------------------------------------------------------
package pack3 is
type my_enum is (E1, E2, E3);
end package;
-------------------------------------------------------------------------------
use work.pack3.all;
package pack4 is
type my_enum_array is array (integer range <>) of my_enum;
end package;
-------------------------------------------------------------------------------
use work.pack4.all;
architecture a of foo is
signal x : my_enum_array(1 to 3); -- OK
signal y : my_enum_array(1 to 3) := (others => E1);
-- Error: E1 not visible
begin
end architecture;
-------------------------------------------------------------------------------
package pack5 is
function func1(x : integer) return boolean;
function func2(x : integer) return boolean;
function "and"(x, y : integer) return boolean;
end package;
-------------------------------------------------------------------------------
use work.pack5.func1;
architecture a2 of foo is
begin
process is
begin
assert func1(4); -- OK
assert func2(5); -- Error
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack5.not_here; -- Error
architecture a3 of foo is
begin
end architecture;
-------------------------------------------------------------------------------
entity bar is
end entity;
architecture a4 of bar is
begin
process is
use work.pack1.all;
variable x : my_int1; -- OK
begin
x := 5;
end process;
process is
variable x : my_int1; -- Error
begin
end process;
b: block is
use work.pack1;
signal x : pack1.my_int1; -- OK
begin
end block;
end architecture;
-------------------------------------------------------------------------------
use work.pack5."and";
architecture a5 of bar is
begin
process is
begin
assert 1 and 2; -- OK
assert work.pack5."and"(1, 2); -- OK
assert pack5."and"(1, 2); -- OK
end process;
end architecture;
-------------------------------------------------------------------------------
package pack6 is
component bar is
end component;
end package;
-------------------------------------------------------------------------------
use work.pack6.all;
architecture a6 of bar is
begin
process is
begin
report bar'path_name; -- OK (references entity)
end process;
end architecture;
-------------------------------------------------------------------------------
use foo.bar.all; -- Error
architecture a7 of bar is
begin
end architecture;
-------------------------------------------------------------------------------
package pack7 is
function foo(x : in integer) return boolean;
function foo(y : in real) return boolean;
end package;
-------------------------------------------------------------------------------
use work.pack7.foo;
architecture issue62 of bar is
begin
process is
begin
assert foo(integer'(1)); -- OK
assert foo(real'(1.6)); -- OK
end process;
end architecture;
-------------------------------------------------------------------------------
use work.all;
use work.pack1.all;
architecture issue63 of bar is
signal x : my_int1; -- OK
begin
end architecture;
-------------------------------------------------------------------------------
package pack8 is
function min(x, y : in integer) return integer;
end package;
-------------------------------------------------------------------------------
use work.pack8.all; -- OK
architecture unit_decl_crash of bar is
begin
process is
variable x : integer := min(1, 2); -- OK
begin
end process;
end architecture;
-------------------------------------------------------------------------------
architecture labels of bar is
signal mySignalVector: bit_vector (7 downto 0);
signal myOtherSignal: bit := '1';
begin
process
begin
L1:
for i in 0 to 9 loop
for i in 0 to 7 loop
mySignalVector(i) <= myOtherSignal;
report "outer loop i = " & integer'image(L1.i);
report "inner loop i = " & integer'image(i);
report integer'image(L1.x); -- Error
end loop;
end loop;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
architecture more_labels of bar is
begin
p1: process is
variable x : boolean;
begin
p1.x := true; -- OK
for x in 1 to 10 loop
p1.x := false; -- OK
end loop;
end process;
b1: block is
constant x : integer := 2;
begin
process is
variable x : boolean;
begin
x := true; -- OK
assert b1.x = 2; -- OK
end process;
end block;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1041.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01041ent IS
END c06s04b00x00p03n01i01041ent;
ARCHITECTURE c06s04b00x00p03n01i01041arch OF c06s04b00x00p03n01i01041ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if k(1) = 1 then
NULL;
end if;
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n01i01041 - Prefix of an indexed name can only denote an array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01041arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1041.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01041ent IS
END c06s04b00x00p03n01i01041ent;
ARCHITECTURE c06s04b00x00p03n01i01041arch OF c06s04b00x00p03n01i01041ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if k(1) = 1 then
NULL;
end if;
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n01i01041 - Prefix of an indexed name can only denote an array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01041arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1041.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01041ent IS
END c06s04b00x00p03n01i01041ent;
ARCHITECTURE c06s04b00x00p03n01i01041arch OF c06s04b00x00p03n01i01041ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if k(1) = 1 then
NULL;
end if;
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n01i01041 - Prefix of an indexed name can only denote an array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01041arch;
|
-------------------------------------------------------------------------------
--! @project Unrolled (factor 2) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Sbox is
port(
X0In : in std_logic_vector(63 downto 0);
X1In : in std_logic_vector(63 downto 0);
X2In : in std_logic_vector(63 downto 0);
X3In : in std_logic_vector(63 downto 0);
X4In : in std_logic_vector(63 downto 0);
RoundNr : in std_logic_vector(3 downto 0);
X0Out : out std_logic_vector(63 downto 0);
X1Out : out std_logic_vector(63 downto 0);
X2Out : out std_logic_vector(63 downto 0);
X3Out : out std_logic_vector(63 downto 0);
X4Out : out std_logic_vector(63 downto 0));
end entity Sbox;
architecture structural of Sbox is
begin
Sbox: process(X0In,X1In,X2In,X3In,X4In,RoundNr) is
-- Procedure for 5-bit Sbox
procedure doSboxPart (
variable SboxPartIn : in std_logic_vector(4 downto 0);
variable SboxPartOut : out std_logic_vector(4 downto 0)) is
-- Temp variable
variable SboxPartTemp : std_logic_vector(17 downto 0);
begin
-- Sbox Interconnections
SboxPartTemp(0) := SboxPartIn(0) xor SboxPartIn(4);
SboxPartTemp(1) := SboxPartIn(2) xor SboxPartIn(1);
SboxPartTemp(2) := SboxPartIn(4) xor SboxPartIn(3);
SboxPartTemp(3) := not SboxPartTemp(0);
SboxPartTemp(4) := not SboxPartIn(1);
SboxPartTemp(5) := not SboxPartTemp(1);
SboxPartTemp(6) := not SboxPartIn(3);
SboxPartTemp(7) := not SboxPartTemp(2);
SboxPartTemp(8) := SboxPartIn(1) and SboxPartTemp(3);
SboxPartTemp(9) := SboxPartTemp(1) and SboxPartTemp(4);
SboxPartTemp(10) := SboxPartIn(3) and SboxPartTemp(5);
SboxPartTemp(11) := SboxPartTemp(2) and SboxPartTemp(6);
SboxPartTemp(12) := SboxPartTemp(0) and SboxPartTemp(7);
SboxPartTemp(13) := SboxPartTemp(0) xor SboxPartTemp(9);
SboxPartTemp(14) := SboxPartIn(1) xor SboxPartTemp(10);
SboxPartTemp(15) := SboxPartTemp(1) xor SboxPartTemp(11);
SboxPartTemp(16) := SboxPartIn(3) xor SboxPartTemp(12);
SboxPartTemp(17) := SboxPartTemp(2) xor SboxPartTemp(8);
SboxPartOut(0) := SboxPartTemp(13) xor SboxPartTemp(17);
SboxPartOut(1) := SboxPartTemp(13) xor SboxPartTemp(14);
SboxPartOut(2) := not SboxPartTemp(15);
SboxPartOut(3) := SboxPartTemp(15) xor SboxPartTemp(16);
SboxPartOut(4) := SboxPartTemp(17);
end procedure doSboxPart;
variable X2TempIn : std_logic_vector(63 downto 0);
variable TempIn,TempOut : std_logic_vector(4 downto 0);
begin
-- Xor with round constants
X2TempIn(3 downto 0) := X2In(3 downto 0) xor RoundNr;
X2TempIn(7 downto 4) := X2In(7 downto 4) xnor RoundNr;
X2TempIn(63 downto 8) := X2In(63 downto 8);
-- Apply 5-bit Sbox 64 times
for i in X0In'range loop
TempIn(0) := X0In(i);
TempIn(1) := X1In(i);
TempIn(2) := X2TempIn(i);
TempIn(3) := X3In(i);
TempIn(4) := X4In(i);
doSboxPart(TempIn,TempOut);
X0Out(i) <= TempOut(0);
X1Out(i) <= TempOut(1);
X2Out(i) <= TempOut(2);
X3Out(i) <= TempOut(3);
X4Out(i) <= TempOut(4);
end loop;
end process Sbox;
end architecture structural;
|
library ieee;
use ieee.std_logic_1164.all;
use work.my_lib.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity keyboard is
port(
clk: in std_logic;
clr: in std_logic;
PS2C: in std_logic;
PS2D: in std_logic;
keyval1: out std_logic_vector(7 downto 0);
keyval2: out std_logic_vector(7 downto 0);
keyval3: out std_logic_vector(7 downto 0)
);
end keyboard;
architecture Behavioral of keyboard is
type state_type is (start, wait_clk_hi_1, wait_clk_lo_1, get_key_1, wait_clk_hi_2, wait_clk_lo_2, get_key_2, breakkey, wait_clk_hi_3, wait_clk_lo_3, get_key_3);
signal state: state_type;
signal PS2Cf, PS2Df: std_logic;
signal PS2C_filter,PS2D_filter: std_logic_vector(7 downto 0);
signal shift1,shift2,shift3: std_logic_vector(10 downto 0);
signal keyval1s,keyval2s,keyval3s: std_logic_vector(7 downto 0);
signal bit_count: std_logic_vector(3 downto 0);
constant bit_count_max: std_logic_vector(3 downto 0) := "1011";
begin
--filter the signal
filterC: process(clk,clr)
begin
if clr = '1' then
PS2C_filter <= (others=>'0');
PS2Cf <= '1';
else if (clk'event and clk ='1' ) then
--shift down
PS2C_filter(7) <= PS2C;
PS2C_filter(6 downto 0) <= PS2C_filter(7 downto 1);
if PS2C_filter = X"FF" then
PS2Cf <= '1';
else if PS2C_filter = X"00" then
PS2Cf <= '0';
end if;
end if;
end if;
end if;
end process filterC;
--filter the signal
filterD: process(clk,clr)
begin
if clr = '1' then
PS2D_filter <= (others=>'0');
PS2Df <= '1';
else if (clk'event and clk ='1' ) then
--shift down
PS2D_filter(7) <= PS2D;
PS2D_filter(6 downto 0) <= PS2D_filter(7 downto 1);
if PS2D_filter = X"FF" then
PS2Df <= '1';
else if PS2D_filter = X"00" then
PS2Df <= '0';
end if;
end if;
end if;
end if;
end process filterD;
--state machine
skey: process(clk,clr)
begin
if(clr = '1') then
state <= start;
bit_count <= (others=>'0');
shift1 <= (others=>'0');
shift2 <= (others=>'0');
shift2 <= (others=>'0');
keyval1s <= (others=>'0');
keyval2s <= (others=>'0');
keyval3s <= (others=>'0');
else if (clk'event and clk = '1') then
case state is
when start =>
if PS2Df = '1' then
state <=start;
else
state <= wait_clk_lo_1;
end if;
when wait_clk_lo_1 =>
if bit_count < bit_count_max then
if PS2Cf = '1' then
state <= wait_clk_lo_1;
else
state <= wait_clk_hi_1;
shift1 <= PS2Df & shift1(10 downto 1);
end if;
else
state <= get_key_1;
end if;
when wait_clk_hi_1 =>
if PS2Cf = '0' then
state <= wait_clk_hi_1;
else
state <= wait_clk_lo_1;
bit_count <= bit_count + 1;
end if;
when get_key_1 =>
keyval1s <= shift1(8 downto 1);
bit_count <= (others=>'0');
state <= wait_clk_lo_2;
----
when wait_clk_lo_2 =>
if bit_count < bit_count_max then
if PS2Cf = '1' then
state <= wait_clk_lo_2;
else
state <= wait_clk_hi_2;
shift2 <= PS2Df & shift2(10 downto 1);
end if;
else
state <= get_key_2;
end if;
when wait_clk_hi_2 =>
if PS2Cf = '0' then
state <= wait_clk_hi_2;
else
state <= wait_clk_lo_2;
bit_count <= bit_count + 1;
end if;
when get_key_2 =>
keyval2s <= shift2(8 downto 1);
bit_count <= (others=>'0');
state <= breakkey;
when breakkey =>
if keyval2s = X"F0" then
state <= wait_clk_lo_3;
else
if keyval1s = X"E0" then
state <= wait_clk_lo_1;
else
state <= wait_clk_lo_2;
end if;
end if;
when wait_clk_lo_3 =>
if bit_count < bit_count_max then
if PS2Cf = '1' then
state <= wait_clk_lo_3;
else
state <= wait_clk_hi_3;
shift3 <= PS2Df & shift3(10 downto 1);
end if;
else
state <= get_key_3;
end if;
when wait_clk_hi_3 =>
if PS2Cf = '0' then
state <= wait_clk_hi_3;
else
state <= wait_clk_lo_3;
bit_count <= bit_count +1;
end if;
when get_key_3 =>
keyval3s <= shift3(8 downto 1);
bit_count <= (others=>'0');
state <= wait_clk_lo_1;
end case;
end if;
end if;
end process skey;
keyval1 <= keyval1s;
keyval2 <= keyval2s;
keyval3 <= keyval3s;
end Behavioral; |
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sm.vhd
-- Description: This entity contains the MM2S DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sm is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_ftch_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_cmnd_idle : out std_logic ; --
mm2s_sts_idle : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : in std_logic ; --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
packet_in_progress : in std_logic ; --
--
-- DataMover Command --
mm2s_cmnd_wr : out std_logic ; --
mm2s_cmnd_data : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+64+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
mm2s_cache_info : in std_logic_vector
(32-1 downto 0); --
mm2s_desc_baddress : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : in std_logic ; --
mm2s_desc_sof : in std_logic --
);
end axi_dma_mm2s_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant MM2S_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant MM2S_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant MM2S_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_MM2S_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_MM2S_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal mm2s_cs : SG_MM2S_STATE_TYPE;
signal mm2s_ns : SG_MM2S_STATE_TYPE;
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal mm2s_cmnd_wr_i : std_logic := '0';
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal mm2s_desc_flush_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_cmnd_wr <= mm2s_cmnd_wr_i;
mm2s_desc_flush <= mm2s_desc_flush_i;
-- Flush any fetch descriptors if stopped due to errors or soft reset
-- or if not in middle of packet and run/stop clears
mm2s_desc_flush_i <= '1' when (mm2s_stop = '1')
or (packet_in_progress = '0'
and mm2s_run_stop = '0')
else '0';
burst_type <= '1' and (not mm2s_keyhole);
-- A 0 on mm2s_kyhole means increment type burst
-- 1 means fixed burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(mm2s_cs,
mm2s_run_stop,
packet_in_progress,
desc_available,
updt_pending,
-- desc_fetch_done,
desc_update_done,
mm2s_cmnd_pending,
mm2s_stop,
mm2s_desc_flush_i
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
mm2s_cmnd_idle <= '0';
mm2s_ns <= mm2s_cs;
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running or Stopped but in middle of xfer and Descriptor
-- data available, No errors logged, and Room to queue more
-- commands, then fetch descriptor
-- if (updt_pending = '1') then
-- mm2s_ns <= IDLE;
if( (mm2s_run_stop = '1' or packet_in_progress = '1')
-- and desc_available = '1' and mm2s_stop = '0' and queue_more = '1' and updt_pending = '0') then
and desc_available = '1' and mm2s_stop = '0' and updt_pending = '0') then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- coverage off
mm2s_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
mm2s_cmnd_idle <= '1';
write_cmnd_cmb <= '0';
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- error detected or run/stop cleared
if(mm2s_desc_flush_i = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
-- descriptor fetch complete
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- mm2s_ns <= EXECUTE_XFER;
elsif(mm2s_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
mm2s_ns <= IDLE;
-- coverage off
write_cmnd_cmb <= '1';
-- coverage on
else
mm2s_ns <= WAIT_STATUS;
end if;
end if;
else
mm2s_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '0';
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- error detected
-- if(mm2s_stop = '1')then
-- mm2s_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(mm2s_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- mm2s_ns <= IDLE;
-- else
-- mm2s_ns <= WAIT_STATUS;
-- end if;
-- else
-- mm2s_ns <= EXECUTE_XFER;
-- end if;
--
-------------------------------------------------------------------
-- coverage off
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(desc_update_done = '1' or mm2s_stop = '1')then
mm2s_ns <= IDLE;
else
mm2s_ns <= WAIT_STATUS;
end if;
-- coverage on
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cs <= IDLE;
else
mm2s_cs <= mm2s_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- register state machine signals
-------------------------------------------------------------------------------
--SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1'; --desc_fetch_req_cmb ;
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
-- & PAD_VALUE
-- & mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole operation'1' -- mm2s_desc_type IR#545697
& PAD_VALUE
& mm2s_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_cmnd_wr_i <= '0';
-- mm2s_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in mm2s_sg_if.
elsif(write_cmnd_cmb = '1')then
mm2s_cmnd_wr_i <= '1';
-- mm2s_cmnd_data <= mm2s_cache_info
-- & mm2s_desc_blength_v
-- & mm2s_desc_blength_s
-- & MM2S_CMD_RSVD
-- -- Command Tag
-- & '0'
-- & '0'
-- & mm2s_desc_eof -- Cat. EOF to CMD Tag
-- & mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- -- Command
-- & mm2s_desc_baddress
-- & mm2s_desc_sof
-- & mm2s_desc_eof
-- & MM2S_CMD_DSA
-- & burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
-- & mm2s_desc_blength;
else
mm2s_cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
mm2s_cmnd_data <= mm2s_cache_info
& mm2s_desc_blength_v
& mm2s_desc_blength_s
& MM2S_CMD_RSVD
-- Command Tag
& '0'
& '0'
& mm2s_desc_eof -- Cat. EOF to CMD Tag
& mm2s_desc_eof -- Cat. IOC to CMD Tag (ioc changed to EOF)
-- Command
& mm2s_desc_baddress
& mm2s_desc_sof
& mm2s_desc_eof
& MM2S_CMD_DSA
& burst_type -- key Hole Operation'1' -- mm2s_desc_type IR#545697
& mm2s_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for mm2s is Idle.
-------------------------------------------------------------------------------
-- increment with each command written
count_incr <= '1' when mm2s_cmnd_wr_i = '1' and desc_update_done = '0'
else '0';
-- decrement with each status received
count_decr <= '1' when mm2s_cmnd_wr_i = '0' and desc_update_done = '1'
else '0';
-- count number of queued commands to keep track of what datamover is still
-- working on
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-- coverage off
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or mm2s_stop = '1')then
cmnds_queued_shift(0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- coverage on
-- Indicate status is idle when no cmnd/sts queued
--mm2s_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
mm2s_sts_idle <= not cmnds_queued_shift (0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued_shift(3) /= '1') then -- < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift(C_PRMY_CMDFIFO_DEPTH-1));
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
|
entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent is
signal s : std_ulogic;
signal din : std_ulogic_vector(15 downto 0);
signal dout : std_ulogic;
begin
dut: entity work.ent
port map (s, din, dout);
process
begin
s <= '1';
din <= x"00_00";
wait for 1 ns;
assert dout = '0' severity failure;
din <= x"04_00";
wait for 1 ns;
assert dout = '1' severity failure;
din <= x"10_40";
wait for 1 ns;
assert dout = '0' severity failure;
din <= x"80_01";
wait for 1 ns;
assert dout = '0' severity failure;
din <= x"80_00";
wait for 1 ns;
assert dout = '1' severity failure;
s <= '0';
din <= x"80_00";
wait for 1 ns;
assert dout = '0' severity failure;
wait;
end process;
end behav;
|
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VHtsmnrwOK22/NpW1pq59/xiCEreAb/SnL/vux3w7w2raJdfkE4bLdycn9S0DMxUiN0jLJgVfwwi
9g==
`protect end_protected
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkpad
-- File: clkpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DS clock pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity clkpad_ds is
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of clkpad_ds is
signal gnd : std_ulogic;
begin
gnd <= '0';
gen0 : if has_ds_pads(tech) = 0 generate
o <= to_X01(padp)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (tech = virtex2) or (tech = spartan3) or (tech = virtex7) or (tech = kintex7) or (tech =artix7) or (tech =zynq7000) generate
u0 : unisim_clkpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
xc4v : if (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) or
(tech = spartan6) or (tech = virtex6) generate
u0 : virtex4_clkpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_clkpad_ds generic map (level) port map (padp, padn, o);
end generate;
igl2 : if (tech = igloo2) generate
u0 : igloo2_clkpad_ds port map (padp, padn, o);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_clkpad_ds generic map (level) port map (padp, padn, o);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_clkpad_ds generic map (level) port map (padp, padn, o);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_clkpad_ds generic map (level) port map (padp, padn, o);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad_ds port map (padp, padn, o, gnd);
end generate;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:06:07 04/13/2016
-- Design Name:
-- Module Name: Shadow_IMM_Add - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; --Using Unsigned for output
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Shadow_IMM_Add is
Port ( SHADOW : in STD_LOGIC_VECTOR (15 downto 0);
IMM : in STD_LOGIC_VECTOR (3 downto 0);
EX_ADDR : out STD_LOGIC_VECTOR (15 downto 0));
end Shadow_IMM_Add;
architecture Behavioral of Shadow_IMM_Add is
signal RESULT : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');
begin
RESULT <= SHADOW + IMM;
EX_ADDR <= RESULT;
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity Etapa2_vlg_vec_tst is
end Etapa2_vlg_vec_tst;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc305.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p04n01i00305ent IS
END c03s01b04x00p04n01i00305ent;
ARCHITECTURE c03s01b04x00p04n01i00305arch OF c03s01b04x00p04n01i00305ent IS
type REAL4 is range 0.00 to "999"; -- Failure_here
-- ERROR - SEMANTIC ERROR: RANGE CONSTRAINT IN FLOATING POINT TYPE
-- DEFINITION MUST BE OF FLOATING POINT TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b04x00p04n01i00305 - Range constraint must be floating point."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p04n01i00305arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc305.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p04n01i00305ent IS
END c03s01b04x00p04n01i00305ent;
ARCHITECTURE c03s01b04x00p04n01i00305arch OF c03s01b04x00p04n01i00305ent IS
type REAL4 is range 0.00 to "999"; -- Failure_here
-- ERROR - SEMANTIC ERROR: RANGE CONSTRAINT IN FLOATING POINT TYPE
-- DEFINITION MUST BE OF FLOATING POINT TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b04x00p04n01i00305 - Range constraint must be floating point."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p04n01i00305arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc305.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p04n01i00305ent IS
END c03s01b04x00p04n01i00305ent;
ARCHITECTURE c03s01b04x00p04n01i00305arch OF c03s01b04x00p04n01i00305ent IS
type REAL4 is range 0.00 to "999"; -- Failure_here
-- ERROR - SEMANTIC ERROR: RANGE CONSTRAINT IN FLOATING POINT TYPE
-- DEFINITION MUST BE OF FLOATING POINT TYPE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b04x00p04n01i00305 - Range constraint must be floating point."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p04n01i00305arch;
|
--
-- Clock on de0nano
--
-- There is one clock source on de0nano board:
-- * On-board 50MHz clock oscillator.
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.verif.all;
entity Top is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
leds_o : out std_logic_vector(7 downto 0)
);
end entity Top;
architecture RTL of Top is
signal rst, led : std_logic;
begin
rst <= not(rst_n_i);
blink_inst: Blink
generic map (FREQUENCY => 50e6)
port map(clk_i => clk_i, rst_i => rst, blink_o => led);
leds_o <= led & not(led) & led & not(led) & led & not(led) & led & not(led);
end architecture RTL;
|
-------------------------------------------------------------------------------
--
-- Testbench for the T411 system toplevel.
--
-- $Id: tb_t411.vhd,v 1.6 2006-06-05 18:50:45 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
entity tb_t411 is
end tb_t411;
library ieee;
use ieee.std_logic_1164.all;
use work.t400_system_comp_pack.t411;
use work.tb_pack.tb_elems;
use work.t400_opt_pack.all;
architecture behav of tb_t411 is
-- 210.4 kHz clock
constant period_c : time := 4.75 us;
signal ck_s : std_logic;
signal reset_n_s : std_logic;
signal io_l_s : std_logic_vector(7 downto 0);
signal io_d_s : std_logic_vector(1 downto 0);
signal io_g_s : std_logic_vector(2 downto 0);
signal si_s,
so_s,
sk_s : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
reset_n_s <= '1';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
t411_b : t411
generic map (
opt_ck_div_g => t400_opt_ck_div_8_c
)
port map (
ck_i => ck_s,
ck_en_i => vdd_s,
reset_n_i => reset_n_s,
si_i => si_s,
so_o => so_s,
sk_o => sk_s,
io_l_b => io_l_s,
io_d_o => io_d_s,
io_g_b => io_g_s
);
io_l_s <= (others => 'H');
io_d_s <= (others => 'H');
io_g_s <= (others => 'H');
-----------------------------------------------------------------------------
-- Testbench elements
-----------------------------------------------------------------------------
tb_elems_b : tb_elems
generic map (
period_g => period_c,
d_width_g => 2,
g_width_g => 3
)
port map (
io_l_i => io_l_s,
io_d_i => io_d_s,
io_g_i => io_g_s,
io_in_o => open,
so_i => so_s,
si_o => si_s,
sk_i => sk_s,
ck_o => ck_s
);
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.5 2006/05/27 19:10:12 arniml
-- explicitly select clock divider 8
--
-- Revision 1.4 2006/05/23 01:18:26 arniml
-- consider IN port
--
-- Revision 1.3 2006/05/15 21:56:02 arniml
-- moved elements to separate design unit tb_elems
--
-- Revision 1.2 2006/05/06 13:34:25 arniml
-- remove delta cycle filter on sk_s
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libleon3
-- File: libleon3.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 internal components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libfpu.all;
use gaisler.mmuiface.all;
package libleon3 is
component proc3
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := 0;
memtech : integer range 0 to NTECH := 0;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
crami : out cram_in_type;
cramo : in cram_out_type;
tbi : out tracebuf_in_type;
tbo : in tracebuf_out_type;
fpi : out fpc_in_type;
fpo : in fpc_out_type;
cpi : out fpc_in_type;
cpo : in fpc_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end component;
component grfpwx
generic (
fabtech : integer := 0;
memtech : integer := 0;
mul : integer range 0 to 3 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
netlist : integer := 0;
index : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component mfpwx
generic (
tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
rfft : integer range 0 to 2 := 0); -- 0 - no protection, 1 - parity
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component grlfpwx
generic (
tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
pipe : integer := 0;
netlist : integer := 0;
index : integer := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component regfile_3p_l3
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8;
wrfst : integer := 0;
numregs : integer := 64;
testen : integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
end;
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
use work.constants.all;
entity function_1 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_1 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(63 downto 0);
variable rTemp2 : SIGNED(31 downto 0);
variable rTemp3 : SIGNED(31 downto 0);
begin
rTemp1 := (signed(INPUT_1) * signed(INPUT_2));
OUTPUT_1 <= std_logic_vector(rTemp1(32+(FIXED-1)-1 downto FIXED))&'0'; --x1*y1*2
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spictrlx
-- File: spictrlx.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Auto mode: J. Andersson, J. Ekergarn - Aeroflex Gaisler AB
-- Contact: [email protected]
--
-- Description: SPI controller with an interface compatible with MPC83xx SPI.
-- Relies on APB's wait state between back-to-back transfers.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.spi.all;
entity spictrlx is
generic (
rev : integer := 0; -- Core revision
fdepth : integer range 1 to 7 := 1; -- FIFO depth is 2^fdepth
slvselen : integer range 0 to 1 := 0; -- Slave select register enable
slvselsz : integer range 1 to 32 := 1; -- Number of slave select signals
oepol : integer range 0 to 1 := 0; -- Output enable polarity
odmode : integer range 0 to 1 := 0; -- Support open drain mode, only
-- set if pads are i/o or od pads.
automode : integer range 0 to 1 := 0; -- Enable automated transfer mode
acntbits : integer range 1 to 32 := 32; -- # Bits in am period counter
aslvsel : integer range 0 to 1 := 0; -- Automatic slave select
twen : integer range 0 to 1 := 1; -- Enable three wire mode
maxwlen : integer range 0 to 15 := 0; -- Maximum word length;
syncram : integer range 0 to 1 := 1; -- Use SYNCRAM for buffers
memtech : integer range 0 to NTECH := 0; -- Memory technology
ft : integer range 0 to 2 := 0; -- Fault-Tolerance
scantest : integer range 0 to 1 := 0; -- Scan test support
syncrst : integer range 0 to 1 := 0; -- Use only sync reset
automask0 : integer := 0; -- Mask 0 for automated transfers
automask1 : integer := 0; -- Mask 1 for automated transfers
automask2 : integer := 0; -- Mask 2 for automated transfers
automask3 : integer := 0; -- Mask 3 for automated transfers
ignore : integer range 0 to 1 := 0 -- Ignore samples
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spii_ignore : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
attribute sync_set_reset of rstn : signal is "true";
end entity spictrlx;
architecture rtl of spictrlx is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant OUTPUT : std_ulogic := OEPOL_LEVEL; -- Enable outputs
constant INPUT : std_ulogic := not OEPOL_LEVEL; -- Tri-state outputs
constant FIFO_DEPTH : integer := 2**fdepth;
constant SLVSEL_EN : integer := slvselen;
constant SLVSEL_SZ : integer := slvselsz;
constant ASEL_EN : integer := aslvsel * slvselen;
constant AM_EN : integer := automode;
constant AM_CNT_BITS : integer := acntbits;
constant OD_EN : integer := odmode;
constant TW_EN : integer := twen;
constant MAX_WLEN : integer := maxwlen;
constant AM_MSK1_EN : boolean := AM_EN = 1 and FIFO_DEPTH > 32;
constant AM_MSK2_EN : boolean := AM_EN = 1 and FIFO_DEPTH > 64;
constant AM_MSK3_EN : boolean := AM_EN = 1 and FIFO_DEPTH > 96;
constant FIFO_BITS : integer := fdepth;
constant APBBITS : integer := 6+3*AM_EN;
constant APBH : integer := 2+APBBITS-1;
constant CAP_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(0, APBBITS);
constant MODE_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(8, APBBITS);
constant EVENT_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(9, APBBITS);
constant MASK_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(10, APBBITS);
constant COM_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(11, APBBITS);
constant TD_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(12, APBBITS);
constant RD_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(13, APBBITS);
constant SLVSEL_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(14, APBBITS);
constant ASEL_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(15, APBBITS);
constant AMCFG_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(16, APBBITS);
constant AMPER_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(17, APBBITS);
constant AMMSK0_ADDR : std_logic_vector(10 downto 2) := "000010100"; -- 0x050
constant AMMSK1_ADDR : std_logic_vector(10 downto 2) := "000010101"; -- 0x054
constant AMMSK2_ADDR : std_logic_vector(10 downto 2) := "000010110"; -- 0x058
constant AMMSK3_ADDR : std_logic_vector(10 downto 2) := "000010111"; -- 0x05C
constant AMTX_ADDR : std_logic_vector(10 downto 2) := "010000000"; -- 0x200
constant AMRX_ADDR : std_logic_vector(10 downto 2) := "100000000"; -- 0x40
constant SPICTRLCAPREG : std_logic_vector(31 downto 0) :=
conv_std_logic_vector(SLVSEL_SZ, 8) & conv_std_logic_vector(MAX_WLEN, 4) &
conv_std_logic_vector(TW_EN, 1) & conv_std_logic_vector(AM_EN, 1) &
conv_std_logic_vector(ASEL_EN, 1) & conv_std_logic_vector(SLVSEL_EN, 1) &
conv_std_logic_vector(FIFO_DEPTH, 8) & conv_std_logic(syncram = 1) &
conv_std_logic_vector(ft, 2) & conv_std_logic_vector(rev, 5);
-- Returns an integer containing the maximum characted length - 1 as
-- restricted by the maxwlen VHDL generic.
function wlen return integer is
begin -- maxwlen
if MAX_WLEN = 0 then return 31; end if;
return MAX_WLEN;
end wlen;
constant PROG_AM_MASK : boolean :=
AM_EN = 1 and automask0 = 0 and (automask1 = 0 or FIFO_DEPTH <= 32) and
(automask2 = 0 or FIFO_DEPTH <= 64) and (automask3 = 0 or FIFO_DEPTH <= 96);
constant AM_MASK : std_logic_vector(127 downto 0) :=
conv_std_logic_vector_signed(automask3,32) &
conv_std_logic_vector_signed(automask2,32) &
conv_std_logic_vector_signed(automask1,32) &
conv_std_logic_vector_signed(automask0,32);
function check_discont_am_mask return boolean is
variable foundzero : boolean;
begin
if AM_EN = 0 then
return false;
elsif PROG_AM_MASK then
return true;
else
foundzero := false;
for i in 0 to FIFO_DEPTH-1 loop
if AM_MASK(i) = '0' then
foundzero := true;
else
if foundzero then
return true;
end if;
end if;
end loop;
return false;
end if;
end function;
constant DISCONT_AM_MASK : boolean := check_discont_am_mask;
function check_am_mask_end return integer is
variable ret : integer;
begin
ret := 0;
for i in 0 to FIFO_DEPTH-1 loop
if AM_MASK(i) = '1' then
ret := i;
end if;
end loop;
return ret;
end function;
constant AM_MASK_END : integer := check_am_mask_end;
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type spi_mode_rec is record -- SPI Mode register
amen : std_ulogic;
loopb : std_ulogic; -- loopback mode
cpol : std_ulogic; -- clock polarity
cpha : std_ulogic; -- clock phase
div16 : std_ulogic; -- Divide by 16
rev : std_ulogic; -- Reverse data mode
ms : std_ulogic; -- Master/slave
en : std_ulogic; -- Enable SPI
len : std_logic_vector(3 downto 0); -- Bits per character
pm : std_logic_vector(3 downto 0); -- Prescale modulus
tw : std_ulogic; -- 3-wire mode
asel : std_ulogic; -- Automatic slave select
fact : std_ulogic; -- PM multiplication factor
od : std_ulogic; -- Open drain mode
cg : std_logic_vector(4 downto 0); -- Clock gap
aseldel : std_logic_vector(1 downto 0); -- Asel delay
tac : std_ulogic;
tto : std_ulogic; -- Three-wire mode word order
igsel : std_ulogic; -- Ignore spisel input
cite : std_ulogic; -- Require SCK = CPOL for TIP end
end record;
type spi_em_rec is record -- SPI Event and Mask registers
tip : std_ulogic; -- Transfer in progress/Clock generated
lt : std_ulogic; -- last character transmitted
ov : std_ulogic; -- slave/master overrun
un : std_ulogic; -- slave/master underrun
mme : std_ulogic; -- Multiple-master error
ne : std_ulogic; -- Not empty
nf : std_ulogic; -- Not full
at : std_ulogic; -- Automated transfer
end record;
type spi_fifo is array (0 to (1-syncram)*(FIFO_DEPTH-1)) of std_logic_vector(wlen downto 0);
type spi_amcfg_rec is record -- AM config register
seq : std_ulogic; -- Data must always be read out of receive queue
strict : std_ulogic; -- Strict period
ovtb : std_ulogic; -- Perform transfer on OV
ovdb : std_ulogic; -- Skip data on OV
act : std_ulogic; -- Start immediately
eact : std_ulogic; -- Activate on external event
erpt : std_ulogic; -- Repeat on external event, not on period done
lock : std_ulogic; -- Lock receive registers when reading data
ecgc : std_ulogic; -- External clock gap control
end record;
type spi_am_rec is record -- Automode state
-- Register interface
cfg : spi_amcfg_rec; -- AM config register
per : std_logic_vector((AM_CNT_BITS-1)*AM_EN downto 0); -- AM period
--
active : std_ulogic; -- Auto mode active
lock : std_ulogic;
cnt : unsigned((AM_CNT_BITS-1)*AM_EN downto 0);
--
skipdata : std_ulogic;
rxfull : std_ulogic; -- AM RX FIFO is filled
rxfifo : spi_fifo; -- Receive data FIFO
txfifo : spi_fifo; -- Transmit data FIFO
rfreecnt : integer range 0 to FIFO_DEPTH; -- free rx fifo slots
mask : std_logic_vector(FIFO_DEPTH-1 downto 0);
mask_shdw : std_logic_vector(FIFO_DEPTH-1 downto 0);
unread : std_logic_vector(FIFO_DEPTH-1 downto 0);
at : std_ulogic;
--
rxread : std_ulogic;
txwrite : std_ulogic;
txread : std_ulogic;
apbaddr : std_logic_vector(FIFO_BITS-1 downto 0);
rxsel : std_ulogic;
end record;
-- Two stage synchronizers on each input coming from off-chip
type spi_in_local_type is record
miso : std_ulogic;
mosi : std_ulogic;
sck : std_ulogic;
spisel : std_ulogic;
end record;
type spi_in_array is array (1 downto 0) of spi_in_local_type;
-- Local spi out type without ssn
type spi_out_local_type is record
miso : std_ulogic;
misooen : std_ulogic;
mosi : std_ulogic;
mosioen : std_ulogic;
sck : std_ulogic;
sckoen : std_ulogic;
enable : std_ulogic;
astart : std_ulogic;
aready : std_ulogic;
end record;
-- Yet another subset of out type to make it easier for certain tools to
-- place registers near pads.
type spi_out_local_lb_type is record
mosi : std_ulogic;
sck : std_ulogic;
end record;
type spi_reg_type is record
-- SPI registers
mode : spi_mode_rec; -- Mode register
event : spi_em_rec; -- Event register
mask : spi_em_rec; -- Mask register
lst : std_ulogic; -- Only field on command register
td : std_logic_vector(31 downto 0); -- Transmit register
rd : std_logic_vector(31 downto 0); -- Receive register
slvsel : std_logic_vector((SLVSEL_SZ-1) downto 0); -- Slave select register
aslvsel : std_logic_vector((SLVSEL_SZ-1) downto 0); -- Automatic slave select
--
uf : std_ulogic; -- Slave in underflow condition
ov : std_ulogic; -- Receive overflow condition
td_occ : std_ulogic; -- Transmit register occupied
rd_free : std_ulogic; -- Receive register free (empty)
txfifo : spi_fifo; -- Transmit data FIFO
rxfifo : spi_fifo; -- Receive data FIFO
rxd : std_logic_vector(wlen downto 0); -- Receive shift register
txd : std_logic_vector(wlen downto 0); -- Transmit shift register
txdupd : std_ulogic; -- Update txd
txdbyp : std_ulogic; -- txd update bypass
toggle : std_ulogic; -- SCK has toggled
samp : std_ulogic; -- Sample
chng : std_ulogic; -- Change
psck : std_ulogic; -- Previous value of SC
twdir : std_ulogic; -- Direction in 3-wire mode
syncsamp : std_logic_vector(1 downto 0); -- Sample synchronized input
incrdli : std_ulogic;
rxdone : std_ulogic;
rxdone2 : std_ulogic;
running : std_ulogic;
ov2 : std_ulogic;
-- counters
tfreecnt : integer range 0 to FIFO_DEPTH; -- free td fifo slots
rfreecnt : integer range 0 to FIFO_DEPTH; -- free td fifo slots
tdfi : std_logic_vector(fdepth-1 downto 0); -- First tx queue element
rdfi : std_logic_vector(fdepth-1 downto 0); -- First rx queue element
tdli : std_logic_vector(fdepth-1 downto 0); -- Last tx queue element
rdli : std_logic_vector(fdepth-1 downto 0); -- Last rx queue element
rbitcnt : std_logic_vector(log2(wlen+1)-1 downto 0); -- Current receive bit
tbitcnt : std_logic_vector(log2(wlen+1)-1 downto 0); -- Current transmit bit
divcnt : unsigned(9 downto 0); -- Clock scaler
cgcnt : unsigned(5 downto 0); -- Clock gap counter
cgcntblock: std_ulogic;
aselcnt : unsigned(1 downto 0); -- ASEL delay
cgasel : std_ulogic; -- ASEL when entering CG
--
irq : std_ulogic;
--
-- Automode
am : spi_am_rec;
-- Sync registers for inputs
spii : spi_in_array;
-- Output
spio : spi_out_local_type;
spiolb : spi_out_local_lb_type;
--
astart : std_ulogic;
cstart : std_ulogic;
txdupd2 : std_ulogic;
twdir2 : std_ulogic;
end record;
-----------------------------------------------------------------------------
-- Sub programs
-----------------------------------------------------------------------------
-- Returns a vector containing the character length - 1 in bits as selected
-- by the Mode field LEN.
function spilen (
len : std_logic_vector(3 downto 0))
return std_logic_vector is
begin -- spilen
if len = zero32(3 downto 0) then
return "11111";
else
return "0" & len;
end if;
end spilen;
-- Write clear
procedure wc (
reg_o : out std_ulogic;
reg_i : in std_ulogic;
b : in std_ulogic) is
begin
reg_o := reg_i and not b;
end procedure wc;
-- Reverses string. After this function has been called the first bit
-- to send is always at position 0.
function reverse(
data : std_logic_vector)
return std_logic_vector is
variable rdata: std_logic_vector(data'reverse_range);
begin
for i in data'range loop
rdata(i) := data(i);
end loop;
return rdata;
end function reverse;
-- Performs a HWORD swap if len /= 0
function condhwordswap (
data : std_logic_vector(31 downto 0);
len : std_logic_vector(4 downto 0))
return std_logic_vector is
variable rdata : std_logic_vector(31 downto 0);
begin -- condhwordswap
if len = one32(4 downto 0) then
rdata := data;
else
rdata := data(15 downto 0) & data(31 downto 16);
end if;
return rdata;
end condhwordswap;
-- Zeroes out unused part of receive vector.
function select_data (
data : std_logic_vector(wlen downto 0);
len : std_logic_vector(4 downto 0))
return std_logic_vector is
variable rdata : std_logic_vector(31 downto 0) := (others => '0');
variable length : integer range 0 to 31 := conv_integer(len);
variable sdata : std_logic_vector(31 downto 0) := (others => '0');
begin -- select_data
-- Quartus can not handle variable ranges
-- rdata(conv_integer(len) downto 0) := data(conv_integer(len) downto 0);
sdata := (others => '0'); sdata(wlen downto 0) := data;
case length is
when 15 => rdata(15 downto 0) := sdata(15 downto 0);
when 14 => rdata(14 downto 0) := sdata(14 downto 0);
when 13 => rdata(13 downto 0) := sdata(13 downto 0);
when 12 => rdata(12 downto 0) := sdata(12 downto 0);
when 11 => rdata(11 downto 0) := sdata(11 downto 0);
when 10 => rdata(10 downto 0) := sdata(10 downto 0);
when 9 => rdata(9 downto 0) := sdata(9 downto 0);
when 8 => rdata(8 downto 0) := sdata(8 downto 0);
when 7 => rdata(7 downto 0) := sdata(7 downto 0);
when 6 => rdata(6 downto 0) := sdata(6 downto 0);
when 5 => rdata(5 downto 0) := sdata(5 downto 0);
when 4 => rdata(4 downto 0) := sdata(4 downto 0);
when 3 => rdata(3 downto 0) := sdata(3 downto 0);
when others => rdata := sdata;
end case;
return rdata;
end select_data;
-- purpose: Returns true when a slave is selected and the clock starts
function slv_start (
spisel : std_ulogic;
cpol : std_ulogic;
sck : std_ulogic;
fsck_chg : std_ulogic)
return boolean is
begin -- slv_start
if spisel = '0' then -- Slave is selected
if fsck_chg = '1' then -- The clock has changed
return (cpol xor sck) = '1'; -- The clock is not idle
end if;
end if;
return false;
end slv_start;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
function spictrl_resval return spi_reg_type is
variable v : spi_reg_type;
begin
v.mode := ('0','0','0','0','0','0','0','0',"0000","0000",
'0','0','0','0',"00000","00", '0', '0', '0', '0');
v.event := ('0', '0', '0', '0', '0', '0', '0', '0');
v.mask := ('0', '0', '0', '0', '0', '0', '0', '0');
v.lst := '0';
v.td := (others => '0');
v.rd := (others => '0');
v.slvsel := (others => '1');
v.aslvsel := (others => '0');
v.uf := '0';
v.ov := '0';
v.td_occ := '0';
v.rd_free := '1';
for i in 0 to (1-syncram)*(FIFO_DEPTH-1) loop
v.txfifo(i) := (others => '0');
v.rxfifo(i) := (others => '0');
end loop;
v.rxd := (others => '0');
v.txd := (others => '0'); v.txd(0) := '1';
v.txdupd := '0';
v.txdbyp := '0';
v.toggle := '0';
v.samp := '1';
v.chng := '0';
v.psck := '0';
v.twdir := INPUT;
v.syncsamp := (others => '0');
v.incrdli := '0';
v.rxdone := '0';
v.rxdone2 := '0';
v.running := '0';
v.ov2 := '0';
v.tfreecnt := FIFO_DEPTH;
v.rfreecnt := FIFO_DEPTH;
v.tdfi := (others => '0');
v.rdfi := (others => '0');
v.tdli := (others => '0');
v.rdli := (others => '0');
v.rbitcnt := (others => '0');
v.tbitcnt := (others => '0');
v.divcnt := (others => '0');
v.cgcnt := (others => '0');
v.cgcntblock := '0';
v.aselcnt := (others => '0');
v.cgasel := '0';
v.irq := '0';
v.am.cfg := ('0', '0', '0', '0', '0', '0', '0', '0', '0');
v.am.per := (others => '0');
v.am.active := '0';
v.am.lock := '0';
v.am.cnt := (others => '0');
v.am.skipdata := '0';
v.am.rxfull := '0';
for i in 0 to (1-syncram)*(FIFO_DEPTH-1) loop
v.am.rxfifo := (others => (others => '0'));
v.am.txfifo := (others => (others => '0'));
end loop;
v.am.rfreecnt := 0;
v.am.mask := (others => '0');
v.am.mask_shdw := (others => '1');
v.am.unread := (others => '0');
v.am.at := '0';
v.am.rxread := '0';
v.am.txwrite := '0';
v.am.txread := '0';
v.am.apbaddr := (others => '0');
v.am.rxsel := '0';
for i in 1 downto 0 loop
v.spii(i).miso := '1';
v.spii(i).mosi := '1';
v.spii(i).sck := '0';
v.spii(i).spisel := '1';
end loop;
v.spio.miso := '1';
v.spio.misooen := INPUT;
v.spio.mosi := '1';
v.spio.mosioen := INPUT;
v.spio.sck := '0';
v.spio.sckoen := INPUT;
v.spio.enable := '0';
v.spio.astart := '0';
v.spio.aready := '0';
v.spiolb.mosi := '1';
v.spiolb.sck := '1';
v.astart := '0';
v.cstart := '0';
v.txdupd2 := '0';
v.twdir2 := '0';
return v;
end spictrl_resval;
constant RES : spi_reg_type := spictrl_resval;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : spi_reg_type;
type fifo_data_vector_array is array (automode downto 0) of std_logic_vector(wlen downto 0);
type fifo_addr_vector_array is array (automode downto 0) of std_logic_vector(fdepth-1 downto 0);
signal rx_di, rx_do, tx_di, tx_do : fifo_data_vector_array;
signal rx_ra, rx_wa, tx_ra, tx_wa : fifo_addr_vector_array;
signal rx_read, tx_read, rx_write, tx_write : std_logic_vector(automode downto 0);
signal arstn : std_ulogic;
begin
arstn <= apbi_testrst when (scantest = 1) and (apbi_testen = '1') else rstn;
-- SPI controller, register interface and related logic
comb: process (r, rstn, apbi_psel, apbi_penable, apbi_paddr, apbi_pwrite,
apbi_pwdata, apbi_testen, apbi_testrst, apbi_scanen,
apbi_testoen, spii_miso, spii_mosi, spii_sck, spii_spisel,
spii_astart, rx_do, tx_do, spii_cstart, spii_ignore)
variable v : spi_reg_type;
variable apbaddr : std_logic_vector(APBH downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable len : std_logic_vector(4 downto 0);
variable indata : std_ulogic;
variable change : std_ulogic;
variable update : std_ulogic;
variable sample : std_ulogic;
variable reload : std_ulogic;
variable cgasel : std_ulogic;
variable txshift : std_ulogic;
-- automode
variable rstop1 : std_ulogic;
variable rstop2 : std_ulogic;
variable rstop3 : std_ulogic;
variable tstop1 : std_ulogic;
variable tstop2 : std_ulogic;
variable tstop3 : std_ulogic;
variable astart : std_ulogic;
-- fifos
variable rx_rd : std_ulogic;
variable tx_rd : std_ulogic;
variable rx_wr : std_ulogic;
variable tx_wr : std_ulogic;
--
variable fsck : std_ulogic;
variable fsck_chg : std_ulogic;
--
variable spisel : std_ulogic;
--
variable rntxd : std_logic_vector(0 to 31);
variable ntxd : std_logic_vector(wlen downto 0);
variable amask : std_logic_vector(FIFO_DEPTH-1 downto 0);
variable aloop : integer;
begin -- process comb
v := r; v.irq := '0';
apbaddr := apbi_paddr(APBH downto 2); apbout := (others => '0');
len := spilen(r.mode.len); v.toggle := '0'; v.txdupd := '0';
v.syncsamp := r.syncsamp(0) & '0'; update := '0'; v.rxdone := '0';
indata := '0'; sample := '0'; change := '0'; reload := '0';
v.spio.astart := '0'; cgasel := '0'; v.ov2 := r.ov; txshift := '0';
fsck := '0'; fsck_chg := '0'; v.txdbyp := '0';
spisel := r.spii(1).spisel or r.mode.igsel;
ntxd := r.td(wlen downto 0); rntxd := reverse(r.td);
if r.mode.rev = '1' then ntxd := rntxd(31-wlen to 31); end if;
v.spio.aready := '0';
if AM_EN = 1 then
v.txdupd2 := '0';
v.cstart := '0';
if TW_EN = 1 then
v.twdir2 := r.twdir;
end if;
end if;
if PROG_AM_MASK then
amask := r.am.mask;
aloop := FIFO_DEPTH-1;
else
amask := AM_MASK(FIFO_DEPTH-1 downto 0);
aloop := AM_MASK_END;
end if;
rx_rd := '0'; tx_rd := '0'; rx_wr := '0'; tx_wr := '0';
rstop1 := '0'; rstop2 := '0'; rstop3 := '0';
tstop1 := '0'; tstop2 := '0'; tstop3 := '0';
astart := '0'; v.am.txwrite := '0'; v.am.txwrite := '0'; v.am.rxread := '0';
if AM_EN = 1 then
v.am.at := r.event.at;
v.astart := spii_astart;
if r.event.at = '0' then
astart := spii_astart and (not r.astart);
if PROG_AM_MASK then
v.am.mask := r.am.mask_shdw;
end if;
end if;
if spii_cstart = '1' then v.cstart := '1'; end if;
end if;
if (apbi_psel and apbi_penable and (not apbi_pwrite)) = '1' then
if apbaddr = CAP_ADDR then
apbout := SPICTRLCAPREG;
elsif apbaddr = MODE_ADDR then
apbout := r.mode.amen & r.mode.loopb & r.mode.cpol & r.mode.cpha &
r.mode.div16 & r.mode.rev & r.mode.ms & r.mode.en &
r.mode.len & r.mode.pm & r.mode.tw & r.mode.asel &
r.mode.fact & r.mode.od & r.mode.cg & r.mode.aseldel &
r.mode.tac & r.mode.tto & r.mode.igsel & r.mode.cite &
zero32(0);
elsif apbaddr = EVENT_ADDR then
apbout := r.event.tip & zero32(30 downto 16) & r.event.at &
r.event.lt & zero32(13) & r.event.ov & r.event.un &
r.event.mme & r.event.ne & r.event.nf & zero32(7 downto 0);
elsif apbaddr = MASK_ADDR then
apbout := r.mask.tip & zero32(30 downto 16) & r.mask.at &
r.mask.lt & zero32(13) & r.mask.ov & r.mask.un &
r.mask.mme & r.mask.ne & r.mask.nf & zero32(7 downto 0);
elsif apbaddr = RD_ADDR then
apbout := condhwordswap(r.rd, len);
if AM_EN = 0 or r.mode.amen = '0' then
v.rd_free := '1';
end if;
elsif apbaddr = SLVSEL_ADDR then
if SLVSEL_EN /= 0 then apbout((SLVSEL_SZ-1) downto 0) := r.slvsel;
else null; end if;
elsif apbaddr = ASEL_ADDR then
if ASEL_EN /= 0 then
apbout((SLVSEL_SZ-1) downto 0) := r.aslvsel;
else null; end if;
end if;
end if;
-- write registers
if (apbi_psel and apbi_penable and apbi_pwrite) = '1' then
if apbaddr = MODE_ADDR then
if AM_EN = 1 then v.mode.amen := apbi_pwdata(31); end if;
v.mode.loopb := apbi_pwdata(30);
v.mode.cpol := apbi_pwdata(29);
v.mode.cpha := apbi_pwdata(28);
v.mode.div16 := apbi_pwdata(27);
v.mode.rev := apbi_pwdata(26);
v.mode.ms := apbi_pwdata(25);
v.mode.en := apbi_pwdata(24);
v.mode.len := apbi_pwdata(23 downto 20);
v.mode.pm := apbi_pwdata(19 downto 16);
if TW_EN = 1 then v.mode.tw := apbi_pwdata(15); end if;
if ASEL_EN = 1 then v.mode.asel := apbi_pwdata(14); end if;
v.mode.fact := apbi_pwdata(13);
if OD_EN = 1 then v.mode.od := apbi_pwdata(12); end if;
v.mode.cg := apbi_pwdata(11 downto 7);
if ASEL_EN = 1 then
v.mode.aseldel := apbi_pwdata(6 downto 5);
v.mode.tac := apbi_pwdata(4);
end if;
if TW_EN = 1 then v.mode.tto := apbi_pwdata(3); end if;
v.mode.igsel := apbi_pwdata(2);
v.mode.cite := apbi_pwdata(1);
elsif apbaddr = EVENT_ADDR then
wc(v.event.lt, r.event.lt, apbi_pwdata(14));
wc(v.event.ov, r.event.ov, apbi_pwdata(12));
wc(v.event.un, r.event.un, apbi_pwdata(11));
wc(v.event.mme, r.event.mme, apbi_pwdata(10));
elsif apbaddr = MASK_ADDR then
v.mask.tip := apbi_pwdata(31);
if AM_EN = 1 then
v.mask.at := apbi_pwdata(15);
end if;
v.mask.lt := apbi_pwdata(14);
v.mask.ov := apbi_pwdata(12);
v.mask.un := apbi_pwdata(11);
v.mask.mme := apbi_pwdata(10);
v.mask.ne := apbi_pwdata(9);
v.mask.nf := apbi_pwdata(8);
elsif apbaddr = COM_ADDR then
v.lst := apbi_pwdata(22);
elsif apbaddr = TD_ADDR then
-- The write is lost if the transmit register is written when
-- the not full bit is zero.
if r.event.nf = '1' then
v.td := apbi_pwdata;
if AM_EN = 0 or r.mode.amen = '0' then
v.td_occ := '1';
end if;
end if;
elsif apbaddr = SLVSEL_ADDR then
if SLVSEL_EN /= 0 then v.slvsel := apbi_pwdata((SLVSEL_SZ-1) downto 0);
else null; end if;
elsif apbaddr = ASEL_ADDR then
if ASEL_EN /= 0 then
v.aslvsel := apbi_pwdata((SLVSEL_SZ-1) downto 0);
else null; end if;
end if;
end if;
-- Automode register interface
if AM_EN /= 0 then
if apbi_psel = '1' then
v.am.apbaddr := apbaddr(FIFO_BITS+1 downto 2);
if syncram /= 0 then
-- Check if tx queue will be read
if apbaddr(10 downto 9) = AMTX_ADDR(10 downto 9) then
v.am.txread := apbi_pwrite and not r.am.txread;
end if;
if apbaddr(10 downto 9) = AMRX_ADDR(10 downto 9) then
v.am.rxread := not r.am.rxread;
end if;
end if;
end if;
if (apbi_psel and apbi_penable) = '1' then
if apbaddr = AMCFG_ADDR then
apbout := zero32(31 downto 9) & r.am.cfg.ecgc & r.am.cfg.lock &
r.am.cfg.erpt & r.am.cfg.seq & r.am.cfg.strict &
r.am.cfg.ovtb & r.am.cfg.ovdb & r.am.active &
r.am.cfg.eact;
if apbi_pwrite = '1' then
v.am.cfg.ecgc := apbi_pwdata(8);
v.am.cfg.lock := apbi_pwdata(7);
v.am.cfg.erpt := apbi_pwdata(6);
v.am.cfg.seq := apbi_pwdata(5);
v.am.cfg.strict := apbi_pwdata(4);
v.am.cfg.ovtb := apbi_pwdata(3);
v.am.cfg.ovdb := apbi_pwdata(2);
v.am.cfg.act := apbi_pwdata(1);
v.spio.astart := apbi_pwdata(1);
v.am.cfg.eact := apbi_pwdata(0);
end if;
elsif apbaddr = AMPER_ADDR then
apbout((AM_CNT_BITS-1)*AM_EN downto 0) := r.am.per;
if apbi_pwrite = '1' then
v.am.per := apbi_pwdata((AM_CNT_BITS-1)*AM_EN downto 0);
end if;
elsif apbaddr = AMMSK0_ADDR then
if FIFO_DEPTH > 32 then
apbout := amask(31 downto 0);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(31 downto 0) := apbi_pwdata;
end if;
end if;
else
apbout(FIFO_DEPTH-1 downto 0) := amask(FIFO_DEPTH-1 downto 0);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 0) := apbi_pwdata(FIFO_DEPTH-1 downto 0);
end if;
end if;
end if;
elsif apbaddr = AMMSK1_ADDR then
if AM_MSK1_EN then
if FIFO_DEPTH > 64 then
apbout := amask(63 downto 32);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(63 downto 32) := apbi_pwdata;
end if;
end if;
else
apbout(FIFO_DEPTH-33 downto 0) := amask(FIFO_DEPTH-1 downto 32);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 32) := apbi_pwdata(FIFO_DEPTH-33 downto 0);
end if;
end if;
end if;
else
null;
end if;
elsif apbaddr = AMMSK2_ADDR then
if AM_MSK2_EN then
if FIFO_DEPTH > 96 then
apbout := amask(95 downto 64);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(95 downto 64) := apbi_pwdata;
end if;
end if;
else
apbout(FIFO_DEPTH-65 downto 0) := amask(FIFO_DEPTH-1 downto 64);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 64) := apbi_pwdata(FIFO_DEPTH-65 downto 0);
end if;
end if;
end if;
else
null;
end if;
elsif apbaddr = AMMSK3_ADDR then
if AM_MSK3_EN then
apbout(FIFO_DEPTH-97 downto 0) := amask(FIFO_DEPTH-1 downto 96);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 96) := apbi_pwdata(FIFO_DEPTH-97 downto 0);
end if;
end if;
else
null;
end if;
elsif apbaddr(10 downto 9) = AMTX_ADDR(10 downto 9) then
if conv_integer(apbaddr(8 downto 2)) < FIFO_DEPTH then
if syncram = 0 then
apbout(wlen downto 0) :=
r.am.txfifo(conv_integer(apbaddr(FIFO_BITS+1 downto 2)));
else
apbout(wlen downto 0) := tx_do(automode);
end if;
if apbi_pwrite = '1' then
v.am.txwrite := '1';
v.td := apbi_pwdata;
end if;
end if;
elsif apbaddr(10 downto 9) = AMRX_ADDR(10 downto 9) then
if conv_integer(apbaddr(8 downto 2)) < FIFO_DEPTH then
if syncram = 0 then
if r.mode.rev = '0' then
apbout := condhwordswap(reverse(select_data(r.rxfifo(conv_integer(r.am.apbaddr)), len)), len);
else
apbout := condhwordswap(select_data(r.rxfifo(conv_integer(r.am.apbaddr)), len), len);
end if;
else
if r.mode.rev = '0' then
apbout := condhwordswap(reverse(select_data(rx_do(conv_integer(not r.am.rxsel)), len)), len);
else
apbout := condhwordswap(select_data(rx_do(conv_integer(not r.am.rxsel)), len), len);
end if;
end if;
if r.am.unread(conv_integer(r.am.apbaddr)) = '1' then
v.rd_free := '1';
v.am.unread(conv_integer(r.am.apbaddr)) := '0';
v.am.lock := r.am.cfg.lock;
end if;
end if;
end if;
end if;
end if;
-- Handle transmit FIFO
if r.td_occ = '1' and r.tfreecnt /= 0 then
if syncram = 0 then
v.txfifo(conv_integer(r.tdli)) := ntxd;
else
tx_wr := '1';
end if;
v.tdli := r.tdli + 1;
v.tfreecnt := r.tfreecnt - 1;
v.td_occ := '0';
if r.tfreecnt = FIFO_DEPTH then
v.txdbyp := r.running and r.mode.ms and r.txdupd;
v.txdupd := not r.uf;
tx_rd := '1';
end if;
end if;
-- AM transmit FIFO handling when core is not implemented with SYNCRAM
if syncram = 0 and AM_EN /= 0 and r.am.txwrite = '1' then
if r.mode.rev = '0' then
v.am.txfifo(conv_integer(r.am.apbaddr)) := r.td(wlen downto 0);
else
v.am.txfifo(conv_integer(r.am.apbaddr)) := reverse(r.td)(31-wlen to 31);
end if;
end if;
-- Update receive register and FIFO
if r.rd_free = '1' and r.rfreecnt /= FIFO_DEPTH then
if syncram = 0 then
if r.mode.rev = '0' then
v.rd := reverse(select_data(r.rxfifo(conv_integer(r.rdfi)), len));
else
v.rd := select_data(r.rxfifo(conv_integer(r.rdfi)), len);
end if;
else
if r.mode.rev = '0' then
v.rd := reverse(select_data(rx_do(0), len));
else
v.rd := select_data(rx_do(0), len);
end if;
end if;
if not ((ignore > 0) and (spii_ignore = '1')) then
v.rdfi := r.rdfi + 1;
v.rfreecnt := r.rfreecnt + 1;
v.rd_free := '0';
end if;
end if;
if v.rd_free = '1' and r.rfreecnt /= FIFO_DEPTH then rx_rd := '1'; end if;
if r.mode.en = '1' then -- Core is enabled
-- Not full detection
if r.tfreecnt /= 0 or r.td_occ /= '1' then
v.event.nf := '1';
if (r.mask.nf and not r.event.nf) = '1' then
v.irq := '1';
end if;
else
v.event.nf := '0';
end if;
-- Not empty detection
if ((AM_EN = 0 or r.mode.amen = '0') and (r.rfreecnt /= FIFO_DEPTH or r.rd_free /= '1')) or
(AM_EN = 1 and r.mode.amen = '1' and r.am.unread /= zero128(FIFO_DEPTH-1 downto 0)) then
v.event.ne := '1';
if (r.mask.ne and not r.event.ne) = '1' then
v.irq := '1';
end if;
else
v.event.ne := '0';
if AM_EN = 1 then v.am.lock := '0'; end if;
end if;
end if;
---------------------------------------------------------------------------
-- Automated periodic transfer control
---------------------------------------------------------------------------
if AM_EN = 1 and r.mode.amen = '1' then
if r.am.active = '0' then
-- Activation either from register write or external event.
v.am.active := r.spio.astart or (astart and r.am.cfg.eact);
v.am.cfg.act := v.am.active;
v.am.rfreecnt := 0;
for i in 0 to aloop loop
if amask(i) = '1' then
v.am.rfreecnt := v.am.rfreecnt+1;
end if;
end loop;
v.am.skipdata := '0'; v.am.rxfull := '0';
v.am.cnt := unsigned(r.am.per);
v.event.at := v.am.active;
v.tdfi := (others => '0');
-- Check mask to see which word in the FIFO to start with.
for i in 0 to aloop loop
if amask(i) = '1' then
if tstop1 = '0' then
v.tdfi := conv_std_logic_vector(i, r.tdfi'length);
end if;
tstop1 := '1';
end if;
end loop;
if v.am.active = '1' then
v.txdupd2 := '1'; tx_rd := '1';
v.tfreecnt := FIFO_DEPTH;
for i in 0 to aloop loop
if amask(i) = '1' then
v.tfreecnt := v.tfreecnt-1;
end if;
end loop;
end if;
v.rdli := (others => '0');
for i in 0 to aloop loop
if rstop1 = '0' then
if amask(i) = '0' then
v.rdli := v.rdli + 1;
else
rstop1 := '1';
end if;
end if;
end loop;
v.cstart := v.am.active;
else
-- Receive fifo handling
if r.am.rxfull = '1' then -- AM RX fifo is filled
-- Move to receive queue if the queue is empty or if there is no
-- requirement on sequential transfers and the queue is not locked.
if (r.event.ne and (v.am.lock or r.am.cfg.seq)) = '0' then
-- Queue is empty
if syncram = 0 then
v.rxfifo := r.am.rxfifo;
else
v.am.rxsel := not r.am.rxsel;
end if;
v.rdfi := (others => '0');
v.rfreecnt := r.am.rfreecnt;
v.rd_free := '0';
v.am.rxfull := '0';
for i in 0 to aloop loop
if amask(i) = '1' then
v.am.unread(i) := '1';
end if;
end loop;
end if;
if r.event.tip = '0' and r.am.at = '1' then
v.event.at := '0';
end if;
if (r.mask.at and r.event.at) = '1' then
v.irq := '1';
end if;
end if;
if r.am.cfg.act = '0' then v.am.active := r.running; end if;
v.am.cfg.eact := '0';
if (r.am.cnt = 0 and r.am.cfg.erpt = '0') or (astart = '1' and r.am.cfg.erpt = '1') then
-- Only allowed to start new transfer if previous transfer(s) is finished
if r.event.tip = '0' then
if (not v.am.rxfull or r.am.cfg.strict) = '1' then
v.am.cnt := unsigned(r.am.per);
end if;
if (not v.am.rxfull or (r.am.cfg.strict and not r.am.cfg.ovtb)) = '1' then
-- Start transfer. Initialize indexes and fifo counter
v.txdupd2 := '1'; tx_rd := '1';
v.am.cnt := unsigned(r.am.per);
v.rdli := (others => '0');
for i in 0 to aloop loop
if rstop2 = '0' then
if amask(i) = '0' then
v.rdli := v.rdli + 1;
else
rstop2 := '1';
end if;
end if;
end loop;
v.tfreecnt := FIFO_DEPTH;
v.am.rfreecnt := 0;
for i in 0 to aloop loop
if amask(i) = '1' then
v.am.rfreecnt := v.am.rfreecnt+1;
v.tfreecnt := v.tfreecnt-1;
end if;
end loop;
v.tdfi := (others => '0');
-- Check mask to see which word in the FIFO to start with.
for i in 0 to aloop loop
if amask(i) = '1' then
if tstop2 = '0' then
v.tdfi := conv_std_logic_vector(i, r.tdfi'length);
end if;
tstop2 := '1';
end if;
end loop;
-- Skip incoming data if receive FIFO is full and OVDB is '1'.
v.am.skipdata := v.am.rxfull and r.am.cfg.ovdb;
if v.am.skipdata = '0' then
-- Clear AM receive fifo if we will overwrite it.
v.am.rfreecnt := FIFO_DEPTH;
for i in 0 to aloop loop
if amask(i) = '0' then
v.am.rfreecnt := v.am.rfreecnt-1;
end if;
end loop;
v.am.rxfull := '0';
end if;
v.event.at := '1';
v.cstart := astart and r.am.cfg.erpt;
end if;
end if;
else
v.am.cnt := r.am.cnt - 1;
end if;
end if;
end if;
---------------------------------------------------------------------------
-- SCK filtering, only used in slave mode
---------------------------------------------------------------------------
fsck := r.psck;
if (r.mode.en and not r.mode.ms) = '1' then
if (r.spii(1).sck xor r.psck) = '0' then
reload := '1';
else
-- Detected SCK change
if r.divcnt = 0 then
v.psck := r.spii(1).sck;
fsck := r.spii(1).sck;
fsck_chg := '1';
reload := '1';
else
v.divcnt := r.divcnt - 1;
end if;
end if;
elsif r.mode.en = '1' then
v.psck := r.spii(1).sck;
end if;
---------------------------------------------------------------------------
-- SPI bus control
---------------------------------------------------------------------------
if (r.mode.en and not r.running) = '1' and (r.mode.ms = '0' or r.divcnt = 0) then
if r.mode.ms = '1' then
if r.divcnt = 0 then
v.spio.sck := r.mode.cpol;
end if;
v.spio.misooen := INPUT;
if TW_EN = 0 or r.mode.tw = '0' then
if OD_EN = 0 or r.mode.od = '0' then
v.spio.mosioen := OUTPUT;
end if;
else
v.spio.mosioen := INPUT;
end if;
v.spio.sckoen := OUTPUT;
if TW_EN = 1 then v.twdir := OUTPUT xor r.mode.tto; end if;
else
if (spisel or r.mode.tw) = '0' then
v.spio.misooen := OUTPUT;
else
v.spio.misooen := INPUT;
end if;
if (not spisel and r.mode.tw and r.mode.tto) = '0' then
v.spio.mosioen := INPUT;
else
v.spio.mosioen := OUTPUT;
end if;
v.spio.sckoen := INPUT;
if TW_EN = 1 then v.twdir := INPUT xor r.mode.tto; end if;
end if;
if ((((AM_EN = 0 or r.mode.amen = '0') or
(AM_EN = 1 and r.mode.amen = '1' and r.am.active = '1')) and
r.mode.ms = '1' and r.tfreecnt /= FIFO_DEPTH and r.txdupd = '0' and (AM_EN = 0 or r.txdupd2 = '0')) or
slv_start(spisel, r.mode.cpol, fsck, fsck_chg)) then
-- Slave underrun detection
if r.tfreecnt = FIFO_DEPTH then
v.uf := '1';
if (r.mask.un and not v.event.un) = '1' then
v.irq := '1';
end if;
v.event.un := '1';
end if;
v.running := '1';
if r.mode.ms = '1' then
if TW_EN = 0 or r.mode.tw = '0' then
v.spio.mosioen := OUTPUT;
else
v.spio.mosioen := OUTPUT xor r.mode.tto;
end if;
change := not r.mode.cpha;
-- Insert cycles when cpha = '0' to ensure proper setup
-- time for first MOSI value in master mode.
reload := not r.mode.cpha;
end if;
end if;
v.cgcnt := (others => '0');
v.rbitcnt := (others => '0'); v.tbitcnt := (others => '0');
if r.mode.ms = '0' then
update := not (r.mode.cpha or (fsck xor r.mode.cpol));
if r.mode.cpha = '0' then
-- Prepare first bit
v.tbitcnt := (others => '0'); v.tbitcnt(0) := '1';
if v.running = '1' and (TW_EN = 0 or r.mode.tw = '0' or r.twdir = OUTPUT) then
txshift := '1';
end if;
end if;
end if;
-- samp and chng should not be changed on b2b
if spisel /= '0' then
v.samp := not r.mode.cpha;
v.chng := r.mode.cpha;
v.psck := r.mode.cpol;
end if;
end if;
if AM_EN = 0 or r.mode.amen = '0' or r.am.cfg.ecgc = '0' then
v.cgcntblock := '0';
else
if r.cstart = '1' then
v.cgcntblock := '0';
end if;
end if;
---------------------------------------------------------------------------
-- Clock generation, only in master mode
---------------------------------------------------------------------------
if r.mode.ms = '1' and (r.running = '1' or r.divcnt /= 0) then
-- The frequency of the SPI clock relative to the system clock is
-- determined by the fact, div16 and pm register fields.
--
-- With fact = 0 the fields have the same meaning as in the MPC83xx
-- register interface. The clock is divided by 4*([PM]+1) and if div16
-- is set the clock is divided by 16*(4*([PM]+1)).
--
-- With fact = 1 the core's register i/f is no longer compatible with
-- the MPC83xx register interface. The clock is divided by 2*([PM]+1) and
-- if div16 is set the clock is divided by 16*(2*([PM]+1)).
--
-- The generated clock's duty cycle is always 50%.
if r.divcnt = 0 then
if ASEL_EN = 0 or r.aselcnt = 0 then
-- Toggle SCK unless we are in a clock gap
if (r.cgcnt = 0 and (AM_EN = 0 or r.cgcntblock = '0')) or
r.spiolb.sck /= r.mode.cpol then
v.spio.sck := not r.spiolb.sck;
v.toggle := r.running;
end if;
if r.cgcnt /= 0 and (AM_EN = 0 or r.cgcntblock = '0') then
v.cgcnt := r.cgcnt - 1;
if ASEL_EN /= 0 and r.cgcnt = 1 then
cgasel := r.mode.tac;
end if;
end if;
elsif ASEL_EN = 1 then
v.aselcnt := r.aselcnt - 1;
end if;
reload := '1';
else
v.divcnt := r.divcnt - 1;
end if;
elsif r.mode.ms = '1' then
v.divcnt := (others => '0');
end if;
if reload = '1' then
-- Reload clock scale counter
v.divcnt(4 downto 0) := unsigned('0' & r.mode.pm) + 1;
if (not r.mode.fact and r.mode.ms) = '1' then
if r.mode.div16 = '1' then
v.divcnt := shift_left(v.divcnt, 5) - 1;
else
v.divcnt := shift_left(v.divcnt, 1) - 1;
end if;
else
if (r.mode.div16 and r.mode.ms) = '1' then
v.divcnt := shift_left(v.divcnt, 4) - 1;
else
v.divcnt(9 downto 4) := (others => '0');
v.divcnt(3 downto 0) := unsigned(r.mode.pm);
end if;
end if;
end if;
---------------------------------------------------------------------------
-- Handle master operation.
---------------------------------------------------------------------------
if r.mode.ms = '1' then
-- Sample data
if r.toggle = '1' then
v.samp := not r.samp;
sample := r.samp;
end if;
-- Change data on the clock flank...
if v.toggle = '1' then
v.chng := not r.chng;
change := r.chng;
end if;
-- Detect multiple-master errors (mode-fault)
if spisel = '0' then
v.mode.en := '0';
v.mode.ms := '0';
v.event.mme := '1';
if (r.mask.mme and not r.event.mme) = '1' then
v.irq := '1';
end if;
v.running := '0';
v.event.tip := '0';
if AM_EN = 1 then
v.event.at := '0';
end if;
end if;
-- Select input data
if r.mode.loopb = '1' then
indata := r.spiolb.mosi;
elsif TW_EN = 1 and r.mode.tw = '1' then
indata := r.spii(1).mosi;
else
indata := r.spii(1).miso;
end if;
end if;
---------------------------------------------------------------------------
-- Handle slave operation
---------------------------------------------------------------------------
if (r.mode.en and not r.mode.ms) = '1' then
if spisel = '0' then
if fsck_chg = '1' then
sample := r.samp; v.samp := not r.samp;
change := r.chng; v.chng := not r.chng;
end if;
indata := r.spii(1).mosi;
end if;
end if;
---------------------------------------------------------------------------
-- Used in both master and slave operation
---------------------------------------------------------------------------
if sample = '1' then
-- Detect receive overflow
if ((AM_EN = 0 or r.mode.amen = '0' ) and (r.rfreecnt = 0 and r.rd_free = '0')) or
(AM_EN = 1 and r.mode.amen = '1' and r.am.rfreecnt = 0) or
r.ov = '1' then
if TW_EN = 0 or r.mode.tw = '0' or r.twdir = INPUT then
-- Overflow event and IRQ
v.ov := '1';
if r.ov = '0' then
if (r.mask.ov and not r.event.ov) = '1' then
v.irq := '1';
end if;
v.event.ov := '1';
end if;
end if;
sample := '0'; -- Prevent sample below
else
sample := not r.mode.ms or r.mode.loopb;
v.syncsamp(0) := not sample;
end if;
if r.rbitcnt = len(log2(wlen+1)-1 downto 0) then
v.rbitcnt := (others => '0');
if TW_EN = 1 then
v.twdir := r.twdir xor not r.mode.loopb;
end if;
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or
(r.mode.tw = '1' and r.twdir = INPUT)) then
v.incrdli := not r.ov;
end if;
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or
(TW_EN = 1 and r.mode.tw = '1' and
(((r.mode.ms xor r.mode.tto) = '1' and r.twdir = INPUT) or
((r.mode.ms xor r.mode.tto) = '0' and r.twdir = OUTPUT)))) then
if r.mode.cpha = '0' then
v.cgcnt := unsigned(r.mode.cg & '0');
if ASEL_EN /= 0 then v.cgasel := r.mode.tac; end if;
if AM_EN = 1 and r.mode.amen = '1' and r.am.cfg.ecgc = '1' then
v.cgcntblock := '1';
end if;
end if;
v.ov := '0';
if r.tfreecnt = FIFO_DEPTH then
v.running := '0';
-- When running with with SCK freq. at half the system freq. we are
-- past the last edge here and SCK has transitioned from CPOL.
-- Force controller into idle state, only applies to master mode.
if (r.toggle and v.toggle) = '1' then
v.toggle := '0';
v.spio.sck := r.mode.cpol;
v.chng := r.chng;
end if;
end if;
v.uf := '0';
end if;
else
v.rbitcnt := r.rbitcnt + 1;
end if;
end if;
-- Sample data line and put into shift register.
if (r.syncsamp(1) or sample) = '1' then
v.rxd := r.rxd(wlen-1 downto 0) & indata;
if ((r.syncsamp(1) and r.incrdli) or (sample and v.incrdli)) = '1' then
v.rxdone := '1'; v.rxdone2 := '1'; v.incrdli := '0';
end if;
end if;
-- Put data into receive queue
if ((AM_EN = 0 or (r.mode.amen and r.am.skipdata) = '0') and
r.rxdone = '1') then
if AM_EN = 1 and r.am.active = '1'then
if not ((ignore > 0) and (spii_ignore = '1')) then
-- Check mask, maybe we need to skip next word in fifo
v.rdli := r.rdli + 1;
v.am.rfreecnt := v.am.rfreecnt - 1;
if DISCONT_AM_MASK then
for i in 0 to aloop loop
if i > conv_integer(r.rdli) and rstop3 = '0' then
if amask(i) = '0' then
v.rdli := v.rdli + 1;
else
rstop3 := '1';
end if;
end if;
end loop;
end if;
end if;
else
v.rdli := r.rdli + 1;
v.rfreecnt := v.rfreecnt - 1;
rx_rd := v.rd_free;
end if;
if syncram = 0 then
if AM_EN = 1 and r.am.active = '1' then
v.am.rxfifo(conv_integer(r.rdli)) := r.rxd;
else
v.rxfifo(conv_integer(r.rdli)) := r.rxd;
end if;
else
rx_wr := '1';
end if;
if r.running = '0' then
if AM_EN = 1 then v.am.rxfull := r.am.active; end if;
end if;
end if;
if AM_EN = 1 and r.mode.amen = '1' then
if TW_EN = 0 or r.mode.tw = '0' or r.mode.tto = '0' then
if r.rxdone = '1' then
v.spio.aready := '1';
end if;
else
if r.twdir = '1' and r.twdir2 = '0' then
v.spio.aready := '1';
end if;
end if;
end if;
-- Special case to put data in receive queue for automatic
-- transfer while in three wire mode with tto = 1
if AM_EN = 1 and TW_EN = 1 and r.mode.amen = '1' and
r.mode.tw = '1' and r.running = '0' and r.rxdone2 = '1' and
r.mode.tto = '1' and r.twdir = INPUT and r.mode.ms = '1' then
v.am.rxfull := r.am.active;
end if;
-- Advance transmit queue
if change = '1' then
if TW_EN = 1 and r.mode.tw = '1' then
v.spio.mosioen := r.twdir;
end if;
if r.tbitcnt = len(log2(wlen+1)-1 downto 0) then
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or
(TW_EN = 1 and r.mode.tw = '1' and
(((r.mode.ms xor r.mode.tto) = '1' and r.twdir = INPUT) or
((r.mode.ms xor r.mode.tto) = '0' and r.twdir = OUTPUT)))) then
if r.mode.cpha = '1' then
v.cgcnt := unsigned(r.mode.cg & '0');
if ASEL_EN /= 0 then v.cgasel := r.mode.tac; end if;
if AM_EN = 1 and r.mode.amen = '1' and r.am.cfg.ecgc = '1' then
v.cgcntblock := '1';
end if;
end if;
end if;
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or r.twdir = OUTPUT) then
if r.uf = '0' then
if not ((ignore > 0) and (spii_ignore = '1')) then
v.tfreecnt := v.tfreecnt + 1;
end if;
end if;
v.txdupd := '1'; tx_rd := '1';
end if;
v.tbitcnt := (others => '0');
else
v.tbitcnt := r.tbitcnt + 1;
end if;
if v.uf = '0' and (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or r.twdir = OUTPUT) then
txshift := v.running;
end if;
end if;
if txshift = '1' then
v.txd := '1' & r.txd(wlen downto 1);
end if;
if AM_EN = 1 then
if r.txdupd2 = '1' then
tx_rd := '1';
v.txdupd := '1';
end if;
end if;
if r.txdupd = '1' then
tx_rd := '1';
if r.txdbyp = '0' then
if syncram = 0 then
if AM_EN = 1 and r.mode.amen = '1' then
v.txd := r.am.txfifo(conv_integer(r.tdfi));
else
v.txd := r.txfifo(conv_integer(r.tdfi));
end if;
else
-- The first FIFO is always used when using syncrams, even in AM mode
v.txd := tx_do(0);
end if;
end if;
-- Data written to TD, bypass
if v.txdbyp = '1' then
v.txd := ntxd;
end if;
if r.tfreecnt /= FIFO_DEPTH then
if AM_EN = 0 or r.mode.amen = '0' then
v.tdfi := v.tdfi + 1;
else
-- Check mask, might need to skip next word
if not (((ignore > 0) and (spii_ignore = '1'))) then
if DISCONT_AM_MASK then
for i in 0 to aloop loop
if tstop3 = '0' and i > conv_integer(v.tdfi) then
if amask(i) = '0' then
v.tdfi := v.tdfi + 1;
else
tstop3 := '1';
end if;
end if;
end loop;
end if;
v.tdfi := v.tdfi + 1;
end if;
end if;
elsif v.txdbyp = '0' then
-- Bus idle value
v.txd(0) := '1';
end if;
end if;
-- Transmit bit
if (change or update) = '1' then
if v.uf = '0' then
v.spio.miso := r.txd(0);
v.spio.mosi := r.txd(0);
if OD_EN = 1 and r.mode.od = '1' then
if (r.mode.ms or r.mode.tw) = '1' then
v.spio.mosioen := r.txd(0) xor OUTPUT;
else
v.spio.misooen := r.txd(0) xor OUTPUT;
end if;
end if;
else
v.spio.miso := '1';
v.spio.mosi := '1';
if OD_EN = 1 and r.mode.od = '1' then
v.spio.misooen := INPUT;
v.spio.mosioen := INPUT;
end if;
end if;
end if;
-- Transfer in progress interrupt generation
if (not r.running and (r.ov2 or (r.rxdone2 or (not r.mode.ms and r.mode.tw)))) = '1' then
if r.mode.ms = '0' or r.mode.cite = '0' or r.divcnt = 0 then
v.event.tip := '0'; v.rxdone2 := '0';
end if;
end if;
if v.running = '1' then v.event.tip := '1'; end if;
if (v.running and not r.event.tip and r.mask.tip and r.mode.en) = '1' then
v.irq := '1';
end if;
-- LST detection and interrupt generation
if v.running = '0' and v.tfreecnt = FIFO_DEPTH and r.lst = '1' then
v.event.lt := '1'; v.lst := '0';
if (r.mask.lt and not r.event.lt) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- Automatic slave select, only in master mode
---------------------------------------------------------------------------
if ASEL_EN /= 0 then
if (r.mode.ms and r.mode.asel) = '1' then
if ((not r.running and v.running) or -- Transfer start or
(r.event.tip and not v.event.tip) or -- transfer end or
(v.running and (cgasel or -- End or start of CG
(r.cgasel and not (r.spiolb.sck xor r.mode.cpol))))) = '1'
then
v.slvsel := r.aslvsel;
v.aslvsel := r.slvsel;
v.cgasel := '0';
end if;
-- May need to delay start of transfer
if ((not r.running and v.running) or cgasel) = '1' then -- Transfer start
v.aselcnt := unsigned(r.mode.aseldel);
end if;
else
v.cgasel := '0';
v.aselcnt := (others => '0');
end if;
end if;
-- Do not toggle outputs in loopback mode
if (r.mode.loopb = '1' or
(r.mode.tw = '1' and TW_EN = 1 and r.twdir = INPUT)) then
v.spio.mosioen := INPUT; v.spio.misooen := INPUT;
end if;
if r.mode.loopb = '1' then v.spio.sckoen := INPUT; end if;
-- When driving in OD mode, always drive low.
if OD_EN = 1 and (r.mode.od and not r.mode.loopb) = '1' then
v.spio.miso := v.spio.miso and not r.mode.od;
v.spio.mosi := v.spio.mosi and not r.mode.od;
end if;
-- Core is disabled
if ((not RESET_ALL) and rstn = '0') or (r.mode.en = '0') then
v.tfreecnt := FIFO_DEPTH;
v.rfreecnt := FIFO_DEPTH;
v.tdfi := RES.tdfi; v.rdfi := RES.rdfi;
v.tdli := RES.tdli; v.rdli := RES.rdli;
v.rd_free := RES.rd_free;
v.td_occ := RES.td_occ;
v.lst := RES.lst;
v.uf := RES.uf;
v.ov := RES.ov;
v.running := RES.running;
v.event.tip := RES.event.tip;
v.incrdli := RES.incrdli;
if TW_EN = 1 then
v.twdir := RES.twdir;
end if;
v.spio.miso := RES.spio.miso;
v.spio.mosi := RES.spio.mosi;
if syncrst = 1 or (r.mode.en = '0') then
v.spio.misooen := RES.spio.misooen;
v.spio.mosioen := RES.spio.mosioen;
v.spio.sckoen := RES.spio.sckoen;
end if;
if AM_EN = 1 then
v.event.at := RES.event.at;
end if;
-- Need to assign samp, chng and psck here if spisel is low when the
-- core is enabled
v.samp := not r.mode.cpha;
v.chng := r.mode.cpha;
v.psck := r.mode.cpol;
if AM_EN = 1 then
v.am.active := RES.am.active;
v.am.cfg.act := RES.am.cfg.act;
v.am.cfg.eact := RES.am.cfg.eact;
v.am.unread := RES.am.unread;
v.am.rxsel := RES.am.rxsel;
end if;
v.rxdone2 := '0';
v.divcnt := (others => '0');
end if;
-- Chip reset
if (not RESET_ALL) and (rstn = '0') then
v.mode := RES.mode;
v.event.tip := RES.event.tip;
v.event.lt := RES.event.lt;
v.event.ov := RES.event.ov;
v.event.un := RES.event.un;
v.event.mme := RES.event.mme;
v.event.ne := RES.event.ne;
v.event.nf := RES.event.nf;
v.mask := RES.mask;
if AM_EN = 1 then
v.event.at := RES.event.at;
if PROG_AM_MASK then
v.am.mask_shdw := RES.am.mask_shdw;
end if;
v.am.per := RES.am.per;
v.am.cfg := RES.am.cfg;
v.am.rxread := RES.am.rxread;
v.am.txwrite := RES.am.txwrite;
v.am.txread := RES.am.txread;
v.am.apbaddr := RES.am.apbaddr;
v.am.rxsel := RES.am.rxsel;
v.cgcntblock := RES.cgcntblock;
end if;
v.lst := RES.lst;
if syncrst = 1 then
v.slvsel := RES.slvsel;
end if;
v.cgcnt := RES.cgcnt;
v.rbitcnt := RES.rbitcnt; v.tbitcnt := RES.tbitcnt;
v.txd := RES.txd;
end if;
-- Drive unused bit if open drain mode is not supported
if OD_EN = 0 then v.mode.od := '0'; end if;
-- Drive unused bits if automode is not supported
if AM_EN = 0 then
v.mode.amen := '0';
--
v.am.cfg.seq := '0';
v.am.cfg.strict := '0';
v.am.cfg.ovtb := '0';
v.am.cfg.ovdb := '0';
v.am.cfg.act := '0';
v.am.cfg.eact := '0';
v.am.per := (others => '0');
v.am.active := '0';
v.am.lock := '0';
v.am.skipdata := '0';
v.am.rxfull := '0';
v.am.rfreecnt := 0;
v.event.at := '0';
v.am.unread := (others=>'0');
v.am.cfg.erpt := '0';
v.am.cfg.lock := '0';
v.am.cfg.ecgc := '0';
v.am.cnt := (others=>'0');
v.am.rxread := '0';
v.am.txwrite := '0';
v.am.txread := '0';
v.am.apbaddr := (others => '0');
v.am.rxsel := '0';
v.mask.at := '0';
v.cstart := '0';
end if;
if AM_EN = 0 or not PROG_AM_MASK then
v.am.mask := (others=>'0');
v.am.mask_shdw := (others=>'0');
end if;
-- Drive unused bits if automatic slave select is not enabled
if ASEL_EN = 0 then
v.mode.asel := '0';
v.aslvsel := (others => '0');
v.mode.aseldel := (others => '0');
v.mode.tac := '0';
v.aselcnt := (others => '0');
v.cgasel := '0';
end if;
-- Drive unused bits if three-wire mode is not enabled
if TW_EN = 0 then
v.mode.tw := '0';
v.mode.tto := '0';
v.twdir := INPUT;
end if;
if TW_EN = 0 or AM_EN = 0 then
v.twdir2 := INPUT;
end if;
if SLVSEL_EN = 0 then
v.slvsel := (others => '1');
end if;
-- Propagate core enable bit
v.spio.enable := r.mode.en;
-- Synchronize inputs coming from off-chip
v.spii(0) := (spii_miso, spii_mosi, spii_sck, spii_spisel);
v.spii(1) := r.spii(0);
-- Outputs to RAMs
if syncram = 0 then
rx_di <= (others => (others => '0'));
tx_di <= (others => (others => '0'));
rx_ra <= (others => (others => '0'));
rx_wa <= (others => (others => '0'));
tx_ra <= (others => (others => '0'));
tx_wa <= (others => (others => '0'));
rx_read <= (others => '0'); rx_write <= (others => '0');
tx_read <= (others => '0'); tx_write <= (others => '0');
else
-- TX RAM(s) write
-- TX RAM(s) are either written from TX register or AM TX area
for i in 0 to automode loop
tx_di(i) <= ntxd;
end loop;
for i in 0 to automode loop
tx_wa(i) <= r.tdli;
end loop;
tx_write(0) <= tx_wr;
if AM_EN /= 0 then
-- Auto mode present
-- Write from AM register interface writes both RAMs
-- Write from TXD register writes RAM 0
tx_write(automode) <= r.am.txwrite;
tx_write(0) <= tx_wr or r.am.txwrite;
if r.am.txwrite = '1' then
for i in 0 to automode loop
tx_wa(i) <= r.am.apbaddr;
end loop;
end if;
end if;
-- TX RAM(s) read
-- First RAM is read by bit shift logic
tx_read(0) <= tx_rd;
tx_ra(0) <= r.tdfi;
if AM_EN /= 0 then
-- Second RAM is read from register interface
tx_read(automode) <= v.am.txread or r.am.txread;
tx_ra(automode) <= v.am.apbaddr;
end if;
-- RX RAM(s) write
-- RX RAM(s) is always written from receive shift register
for i in 0 to automode loop
rx_di(i) <= r.rxd;
rx_wa(i) <= r.rdli;
end loop;
rx_write(0) <= rx_wr;
if AM_EN /= 0 then
rx_write(automode) <= '0';
end if;
if AM_EN /= 0 and r.mode.amen = '1' then
-- AM active
-- Handle writes from bit shift logic
if r.am.rxsel = '0' then
rx_write(0) <= rx_wr;
rx_write(automode) <= '0';
else
rx_write(0) <= '0';
rx_write(automode) <= rx_wr;
end if;
end if;
-- RX RAM(s) are read via register interface
for i in 0 to automode loop
rx_ra(i) <= r.rdfi;
rx_read(i) <= rx_rd;
end loop;
if AM_EN /= 0 and r.mode.amen = '1' then
if r.am.rxsel = '0' then
rx_read(0) <= '0';
rx_read(automode) <= v.am.rxread;
if v.am.rxread = '1' then
rx_ra(automode) <= v.am.apbaddr;
end if;
else
rx_read(0) <= v.am.rxread;
rx_read(automode) <= '0';
if v.am.rxread = '1' then
rx_ra(0) <= v.am.apbaddr;
end if;
end if;
end if;
if scantest = 1 and (apbi_scanen and apbi_testen) = '1' then
rx_read <= (others => '0'); rx_write <= (others => '0');
tx_read <= (others => '0'); tx_write <= (others => '0');
end if;
end if;
v.spiolb.mosi := v.spio.mosi;
v.spiolb.sck := v.spio.sck;
-- Update registers
rin <= v;
-- Update outputs
apbo_prdata <= apbout;
apbo_pirq <= r.irq;
slvsel <= r.slvsel;
spio_miso <= r.spio.miso;
spio_misooen <= r.spio.misooen;
spio_mosi <= r.spio.mosi;
spio_mosioen <= r.spio.mosioen;
spio_sck <= r.spio.sck;
spio_sckoen <= r.spio.sckoen;
spio_enable <= r.spio.enable;
spio_astart <= r.spio.astart;
spio_aready <= r.spio.aready;
if scantest = 1 and apbi_testen = '1' then
spio_misooen <= apbi_testoen;
spio_mosioen <= apbi_testoen;
spio_sckoen <= apbi_testoen;
end if;
end process comb;
-- FIFOs
fiforams : if syncram /= 0 generate
fifoloop : for i in 0 to automode generate
noft : if ft = 0 generate
rxfifo : syncram_2p
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1)
port map (
rclk => clk,
renable => rx_read(i),
raddress => rx_ra(i),
dataout => rx_do(i),
wclk => clk,
write => rx_write(i),
waddress => rx_wa(i),
datain => rx_di(i));
-- testin => testin);
txfifo : syncram_2p
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1)
port map (
rclk => clk,
renable => tx_read(i),
raddress => tx_ra(i),
dataout => tx_do(i),
wclk => clk,
write => tx_write(i),
waddress => tx_wa(i),
datain => tx_di(i));
-- testin => testin);
end generate noft;
ftfifos : if ft /= 0 generate
ftrxfifo : syncram_2pft
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1,
ft => ft)
port map (
rclk => clk,
renable => rx_read(i),
raddress => rx_ra(i),
dataout => rx_do(i),
wclk => clk,
write => rx_write(i),
waddress => rx_wa(i),
datain => rx_di(i),
error => open);
-- testin => testin);
fttxfifo : syncram_2pft
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1,
ft => ft)
port map (
rclk => clk,
renable => tx_read(i),
raddress => tx_ra(i),
dataout => tx_do(i),
wclk => clk,
write => tx_write(i),
waddress => tx_wa(i),
datain => tx_di(i),
error => open);
-- testin => testin);
end generate ftfifos;
end generate fifoloop;
end generate fiforams;
nofiforams : if syncram = 0 generate
rx_do <= (others => (others => '0'));
tx_do <= (others => (others => '0'));
end generate;
-- Registers
reg: process (clk, arstn)
begin -- process reg
if rising_edge(clk) then
r <= rin;
if rstn = '0' then
r.spio.sck <= RES.spio.sck;
r.rbitcnt <= RES.rbitcnt; r.tbitcnt <= RES.tbitcnt;
if RESET_ALL then
r <= RES;
-- Do not use synchronous reset for sync. registers
r.spii <= rin.spii;
end if;
end if;
end if;
if syncrst = 0 and arstn = '0' then
r.spio.misooen <= RES.spio.misooen;
r.spio.mosioen <= RES.spio.mosioen;
r.spio.sckoen <= RES.spio.sckoen;
if SLVSEL_EN /= 0 then
r.slvsel <= RES.slvsel;
end if;
end if;
end process reg;
end architecture rtl;
|
entity tb_iassoc04 is
end tb_iassoc04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_iassoc04 is
signal a, b : bit_vector (3 downto 0);
signal res : bit;
begin
dut: entity work.iassoc04
port map (a, b, res);
process
begin
a <= "0001";
b <= "0000";
wait for 1 ns;
assert res = '1' severity failure;
a <= "0000";
b <= "0000";
wait for 1 ns;
assert res = '0' severity failure;
wait;
end process;
end behav;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_8;
USE proc_sys_reset_v5_0_8.proc_sys_reset;
ENTITY design_SW_standalone_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_SW_standalone_rst_processing_system7_0_100M_0;
ARCHITECTURE design_SW_standalone_rst_processing_system7_0_100M_0_arch OF design_SW_standalone_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SW_standalone_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SW_standalone_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SW_standalone_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "design_SW_standalone_rst_processing_system7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SW_standalone_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "design_SW_standalone_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_SW_standalone_rst_processing_system7_0_100M_0_arch;
|
-----------------------------------------------------------------------------
-- Entity: grfpushwx
-- File: grfpushwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU (shared version) wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.leon3.all;
entity grfpushwx is
generic (mul : integer := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
fpvi : in grfpu_in_vector_type;
fpvo : out grfpu_out_vector_type
);
end;
architecture rtl of grfpushwx is
component grfpushw
generic (mul : integer range 0 to 3 := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
cpu0_start : in std_logic;
cpu0_nonstd : in std_logic;
cpu0_flop : in std_logic_vector(8 downto 0);
cpu0_op1 : in std_logic_vector(63 downto 0);
cpu0_op2 : in std_logic_vector(63 downto 0);
cpu0_opid : in std_logic_vector(7 downto 0);
cpu0_flush : in std_logic;
cpu0_flushid : in std_logic_vector(5 downto 0);
cpu0_rndmode : in std_logic_vector(1 downto 0);
cpu0_req : in std_logic_vector(2 downto 0);
cpu0_res : out std_logic_vector(63 downto 0);
cpu0_exc : out std_logic_vector(5 downto 0);
cpu0_allow : out std_logic_vector(2 downto 0);
cpu0_rdy : out std_logic;
cpu0_cc : out std_logic_vector(1 downto 0);
cpu0_idout : out std_logic_vector(7 downto 0);
cpu1_start : in std_logic;
cpu1_nonstd : in std_logic;
cpu1_flop : in std_logic_vector(8 downto 0);
cpu1_op1 : in std_logic_vector(63 downto 0);
cpu1_op2 : in std_logic_vector(63 downto 0);
cpu1_opid : in std_logic_vector(7 downto 0);
cpu1_flush : in std_logic;
cpu1_flushid : in std_logic_vector(5 downto 0);
cpu1_rndmode : in std_logic_vector(1 downto 0);
cpu1_req : in std_logic_vector(2 downto 0);
cpu1_res : out std_logic_vector(63 downto 0);
cpu1_exc : out std_logic_vector(5 downto 0);
cpu1_allow : out std_logic_vector(2 downto 0);
cpu1_rdy : out std_logic;
cpu1_cc : out std_logic_vector(1 downto 0);
cpu1_idout : out std_logic_vector(7 downto 0);
cpu2_start : in std_logic;
cpu2_nonstd : in std_logic;
cpu2_flop : in std_logic_vector(8 downto 0);
cpu2_op1 : in std_logic_vector(63 downto 0);
cpu2_op2 : in std_logic_vector(63 downto 0);
cpu2_opid : in std_logic_vector(7 downto 0);
cpu2_flush : in std_logic;
cpu2_flushid : in std_logic_vector(5 downto 0);
cpu2_rndmode : in std_logic_vector(1 downto 0);
cpu2_req : in std_logic_vector(2 downto 0);
cpu2_res : out std_logic_vector(63 downto 0);
cpu2_exc : out std_logic_vector(5 downto 0);
cpu2_allow : out std_logic_vector(2 downto 0);
cpu2_rdy : out std_logic;
cpu2_cc : out std_logic_vector(1 downto 0);
cpu2_idout : out std_logic_vector(7 downto 0);
cpu3_start : in std_logic;
cpu3_nonstd : in std_logic;
cpu3_flop : in std_logic_vector(8 downto 0);
cpu3_op1 : in std_logic_vector(63 downto 0);
cpu3_op2 : in std_logic_vector(63 downto 0);
cpu3_opid : in std_logic_vector(7 downto 0);
cpu3_flush : in std_logic;
cpu3_flushid : in std_logic_vector(5 downto 0);
cpu3_rndmode : in std_logic_vector(1 downto 0);
cpu3_req : in std_logic_vector(2 downto 0);
cpu3_res : out std_logic_vector(63 downto 0);
cpu3_exc : out std_logic_vector(5 downto 0);
cpu3_allow : out std_logic_vector(2 downto 0);
cpu3_rdy : out std_logic;
cpu3_cc : out std_logic_vector(1 downto 0);
cpu3_idout : out std_logic_vector(7 downto 0);
cpu4_start : in std_logic;
cpu4_nonstd : in std_logic;
cpu4_flop : in std_logic_vector(8 downto 0);
cpu4_op1 : in std_logic_vector(63 downto 0);
cpu4_op2 : in std_logic_vector(63 downto 0);
cpu4_opid : in std_logic_vector(7 downto 0);
cpu4_flush : in std_logic;
cpu4_flushid : in std_logic_vector(5 downto 0);
cpu4_rndmode : in std_logic_vector(1 downto 0);
cpu4_req : in std_logic_vector(2 downto 0);
cpu4_res : out std_logic_vector(63 downto 0);
cpu4_exc : out std_logic_vector(5 downto 0);
cpu4_allow : out std_logic_vector(2 downto 0);
cpu4_rdy : out std_logic;
cpu4_cc : out std_logic_vector(1 downto 0);
cpu4_idout : out std_logic_vector(7 downto 0);
cpu5_start : in std_logic;
cpu5_nonstd : in std_logic;
cpu5_flop : in std_logic_vector(8 downto 0);
cpu5_op1 : in std_logic_vector(63 downto 0);
cpu5_op2 : in std_logic_vector(63 downto 0);
cpu5_opid : in std_logic_vector(7 downto 0);
cpu5_flush : in std_logic;
cpu5_flushid : in std_logic_vector(5 downto 0);
cpu5_rndmode : in std_logic_vector(1 downto 0);
cpu5_req : in std_logic_vector(2 downto 0);
cpu5_res : out std_logic_vector(63 downto 0);
cpu5_exc : out std_logic_vector(5 downto 0);
cpu5_allow : out std_logic_vector(2 downto 0);
cpu5_rdy : out std_logic;
cpu5_cc : out std_logic_vector(1 downto 0);
cpu5_idout : out std_logic_vector(7 downto 0);
cpu6_start : in std_logic;
cpu6_nonstd : in std_logic;
cpu6_flop : in std_logic_vector(8 downto 0);
cpu6_op1 : in std_logic_vector(63 downto 0);
cpu6_op2 : in std_logic_vector(63 downto 0);
cpu6_opid : in std_logic_vector(7 downto 0);
cpu6_flush : in std_logic;
cpu6_flushid : in std_logic_vector(5 downto 0);
cpu6_rndmode : in std_logic_vector(1 downto 0);
cpu6_req : in std_logic_vector(2 downto 0);
cpu6_res : out std_logic_vector(63 downto 0);
cpu6_exc : out std_logic_vector(5 downto 0);
cpu6_allow : out std_logic_vector(2 downto 0);
cpu6_rdy : out std_logic;
cpu6_cc : out std_logic_vector(1 downto 0);
cpu6_idout : out std_logic_vector(7 downto 0);
cpu7_start : in std_logic;
cpu7_nonstd : in std_logic;
cpu7_flop : in std_logic_vector(8 downto 0);
cpu7_op1 : in std_logic_vector(63 downto 0);
cpu7_op2 : in std_logic_vector(63 downto 0);
cpu7_opid : in std_logic_vector(7 downto 0);
cpu7_flush : in std_logic;
cpu7_flushid : in std_logic_vector(5 downto 0);
cpu7_rndmode : in std_logic_vector(1 downto 0);
cpu7_req : in std_logic_vector(2 downto 0);
cpu7_res : out std_logic_vector(63 downto 0);
cpu7_exc : out std_logic_vector(5 downto 0);
cpu7_allow : out std_logic_vector(2 downto 0);
cpu7_rdy : out std_logic;
cpu7_cc : out std_logic_vector(1 downto 0);
cpu7_idout : out std_logic_vector(7 downto 0)
);
end component;
begin
x0 : grfpushw generic map ((mul mod 4), nshare, tech, arb)
port map (
clk ,
reset ,
fpvi(0).start ,
fpvi(0).nonstd ,
fpvi(0).flop ,
fpvi(0).op1 ,
fpvi(0).op2 ,
fpvi(0).opid ,
fpvi(0).flush ,
fpvi(0).flushid ,
fpvi(0).rndmode ,
fpvi(0).req ,
fpvo(0).res ,
fpvo(0).exc ,
fpvo(0).allow ,
fpvo(0).rdy ,
fpvo(0).cc ,
fpvo(0).idout ,
fpvi(1).start ,
fpvi(1).nonstd ,
fpvi(1).flop ,
fpvi(1).op1 ,
fpvi(1).op2 ,
fpvi(1).opid ,
fpvi(1).flush ,
fpvi(1).flushid ,
fpvi(1).rndmode ,
fpvi(1).req ,
fpvo(1).res ,
fpvo(1).exc ,
fpvo(1).allow ,
fpvo(1).rdy ,
fpvo(1).cc ,
fpvo(1).idout ,
fpvi(2).start ,
fpvi(2).nonstd ,
fpvi(2).flop ,
fpvi(2).op1 ,
fpvi(2).op2 ,
fpvi(2).opid ,
fpvi(2).flush ,
fpvi(2).flushid ,
fpvi(2).rndmode ,
fpvi(2).req ,
fpvo(2).res ,
fpvo(2).exc ,
fpvo(2).allow ,
fpvo(2).rdy ,
fpvo(2).cc ,
fpvo(2).idout ,
fpvi(3).start ,
fpvi(3).nonstd ,
fpvi(3).flop ,
fpvi(3).op1 ,
fpvi(3).op2 ,
fpvi(3).opid ,
fpvi(3).flush ,
fpvi(3).flushid ,
fpvi(3).rndmode ,
fpvi(3).req ,
fpvo(3).res ,
fpvo(3).exc ,
fpvo(3).allow ,
fpvo(3).rdy ,
fpvo(3).cc ,
fpvo(3).idout ,
fpvi(4).start ,
fpvi(4).nonstd ,
fpvi(4).flop ,
fpvi(4).op1 ,
fpvi(4).op2 ,
fpvi(4).opid ,
fpvi(4).flush ,
fpvi(4).flushid ,
fpvi(4).rndmode ,
fpvi(4).req ,
fpvo(4).res ,
fpvo(4).exc ,
fpvo(4).allow ,
fpvo(4).rdy ,
fpvo(4).cc ,
fpvo(4).idout ,
fpvi(5).start ,
fpvi(5).nonstd ,
fpvi(5).flop ,
fpvi(5).op1 ,
fpvi(5).op2 ,
fpvi(5).opid ,
fpvi(5).flush ,
fpvi(5).flushid ,
fpvi(5).rndmode ,
fpvi(5).req ,
fpvo(5).res ,
fpvo(5).exc ,
fpvo(5).allow ,
fpvo(5).rdy ,
fpvo(5).cc ,
fpvo(5).idout ,
fpvi(6).start ,
fpvi(6).nonstd ,
fpvi(6).flop ,
fpvi(6).op1 ,
fpvi(6).op2 ,
fpvi(6).opid ,
fpvi(6).flush ,
fpvi(6).flushid ,
fpvi(6).rndmode ,
fpvi(6).req ,
fpvo(6).res ,
fpvo(6).exc ,
fpvo(6).allow ,
fpvo(6).rdy ,
fpvo(6).cc ,
fpvo(6).idout ,
fpvi(7).start ,
fpvi(7).nonstd ,
fpvi(7).flop ,
fpvi(7).op1 ,
fpvi(7).op2 ,
fpvi(7).opid ,
fpvi(7).flush ,
fpvi(7).flushid ,
fpvi(7).rndmode ,
fpvi(7).req ,
fpvo(7).res ,
fpvo(7).exc ,
fpvo(7).allow ,
fpvo(7).rdy ,
fpvo(7).cc ,
fpvo(7).idout);
end;
|
-----------------------------------------------------------------------------
-- Entity: grfpushwx
-- File: grfpushwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU (shared version) wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.leon3.all;
entity grfpushwx is
generic (mul : integer := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
fpvi : in grfpu_in_vector_type;
fpvo : out grfpu_out_vector_type
);
end;
architecture rtl of grfpushwx is
component grfpushw
generic (mul : integer range 0 to 3 := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
cpu0_start : in std_logic;
cpu0_nonstd : in std_logic;
cpu0_flop : in std_logic_vector(8 downto 0);
cpu0_op1 : in std_logic_vector(63 downto 0);
cpu0_op2 : in std_logic_vector(63 downto 0);
cpu0_opid : in std_logic_vector(7 downto 0);
cpu0_flush : in std_logic;
cpu0_flushid : in std_logic_vector(5 downto 0);
cpu0_rndmode : in std_logic_vector(1 downto 0);
cpu0_req : in std_logic_vector(2 downto 0);
cpu0_res : out std_logic_vector(63 downto 0);
cpu0_exc : out std_logic_vector(5 downto 0);
cpu0_allow : out std_logic_vector(2 downto 0);
cpu0_rdy : out std_logic;
cpu0_cc : out std_logic_vector(1 downto 0);
cpu0_idout : out std_logic_vector(7 downto 0);
cpu1_start : in std_logic;
cpu1_nonstd : in std_logic;
cpu1_flop : in std_logic_vector(8 downto 0);
cpu1_op1 : in std_logic_vector(63 downto 0);
cpu1_op2 : in std_logic_vector(63 downto 0);
cpu1_opid : in std_logic_vector(7 downto 0);
cpu1_flush : in std_logic;
cpu1_flushid : in std_logic_vector(5 downto 0);
cpu1_rndmode : in std_logic_vector(1 downto 0);
cpu1_req : in std_logic_vector(2 downto 0);
cpu1_res : out std_logic_vector(63 downto 0);
cpu1_exc : out std_logic_vector(5 downto 0);
cpu1_allow : out std_logic_vector(2 downto 0);
cpu1_rdy : out std_logic;
cpu1_cc : out std_logic_vector(1 downto 0);
cpu1_idout : out std_logic_vector(7 downto 0);
cpu2_start : in std_logic;
cpu2_nonstd : in std_logic;
cpu2_flop : in std_logic_vector(8 downto 0);
cpu2_op1 : in std_logic_vector(63 downto 0);
cpu2_op2 : in std_logic_vector(63 downto 0);
cpu2_opid : in std_logic_vector(7 downto 0);
cpu2_flush : in std_logic;
cpu2_flushid : in std_logic_vector(5 downto 0);
cpu2_rndmode : in std_logic_vector(1 downto 0);
cpu2_req : in std_logic_vector(2 downto 0);
cpu2_res : out std_logic_vector(63 downto 0);
cpu2_exc : out std_logic_vector(5 downto 0);
cpu2_allow : out std_logic_vector(2 downto 0);
cpu2_rdy : out std_logic;
cpu2_cc : out std_logic_vector(1 downto 0);
cpu2_idout : out std_logic_vector(7 downto 0);
cpu3_start : in std_logic;
cpu3_nonstd : in std_logic;
cpu3_flop : in std_logic_vector(8 downto 0);
cpu3_op1 : in std_logic_vector(63 downto 0);
cpu3_op2 : in std_logic_vector(63 downto 0);
cpu3_opid : in std_logic_vector(7 downto 0);
cpu3_flush : in std_logic;
cpu3_flushid : in std_logic_vector(5 downto 0);
cpu3_rndmode : in std_logic_vector(1 downto 0);
cpu3_req : in std_logic_vector(2 downto 0);
cpu3_res : out std_logic_vector(63 downto 0);
cpu3_exc : out std_logic_vector(5 downto 0);
cpu3_allow : out std_logic_vector(2 downto 0);
cpu3_rdy : out std_logic;
cpu3_cc : out std_logic_vector(1 downto 0);
cpu3_idout : out std_logic_vector(7 downto 0);
cpu4_start : in std_logic;
cpu4_nonstd : in std_logic;
cpu4_flop : in std_logic_vector(8 downto 0);
cpu4_op1 : in std_logic_vector(63 downto 0);
cpu4_op2 : in std_logic_vector(63 downto 0);
cpu4_opid : in std_logic_vector(7 downto 0);
cpu4_flush : in std_logic;
cpu4_flushid : in std_logic_vector(5 downto 0);
cpu4_rndmode : in std_logic_vector(1 downto 0);
cpu4_req : in std_logic_vector(2 downto 0);
cpu4_res : out std_logic_vector(63 downto 0);
cpu4_exc : out std_logic_vector(5 downto 0);
cpu4_allow : out std_logic_vector(2 downto 0);
cpu4_rdy : out std_logic;
cpu4_cc : out std_logic_vector(1 downto 0);
cpu4_idout : out std_logic_vector(7 downto 0);
cpu5_start : in std_logic;
cpu5_nonstd : in std_logic;
cpu5_flop : in std_logic_vector(8 downto 0);
cpu5_op1 : in std_logic_vector(63 downto 0);
cpu5_op2 : in std_logic_vector(63 downto 0);
cpu5_opid : in std_logic_vector(7 downto 0);
cpu5_flush : in std_logic;
cpu5_flushid : in std_logic_vector(5 downto 0);
cpu5_rndmode : in std_logic_vector(1 downto 0);
cpu5_req : in std_logic_vector(2 downto 0);
cpu5_res : out std_logic_vector(63 downto 0);
cpu5_exc : out std_logic_vector(5 downto 0);
cpu5_allow : out std_logic_vector(2 downto 0);
cpu5_rdy : out std_logic;
cpu5_cc : out std_logic_vector(1 downto 0);
cpu5_idout : out std_logic_vector(7 downto 0);
cpu6_start : in std_logic;
cpu6_nonstd : in std_logic;
cpu6_flop : in std_logic_vector(8 downto 0);
cpu6_op1 : in std_logic_vector(63 downto 0);
cpu6_op2 : in std_logic_vector(63 downto 0);
cpu6_opid : in std_logic_vector(7 downto 0);
cpu6_flush : in std_logic;
cpu6_flushid : in std_logic_vector(5 downto 0);
cpu6_rndmode : in std_logic_vector(1 downto 0);
cpu6_req : in std_logic_vector(2 downto 0);
cpu6_res : out std_logic_vector(63 downto 0);
cpu6_exc : out std_logic_vector(5 downto 0);
cpu6_allow : out std_logic_vector(2 downto 0);
cpu6_rdy : out std_logic;
cpu6_cc : out std_logic_vector(1 downto 0);
cpu6_idout : out std_logic_vector(7 downto 0);
cpu7_start : in std_logic;
cpu7_nonstd : in std_logic;
cpu7_flop : in std_logic_vector(8 downto 0);
cpu7_op1 : in std_logic_vector(63 downto 0);
cpu7_op2 : in std_logic_vector(63 downto 0);
cpu7_opid : in std_logic_vector(7 downto 0);
cpu7_flush : in std_logic;
cpu7_flushid : in std_logic_vector(5 downto 0);
cpu7_rndmode : in std_logic_vector(1 downto 0);
cpu7_req : in std_logic_vector(2 downto 0);
cpu7_res : out std_logic_vector(63 downto 0);
cpu7_exc : out std_logic_vector(5 downto 0);
cpu7_allow : out std_logic_vector(2 downto 0);
cpu7_rdy : out std_logic;
cpu7_cc : out std_logic_vector(1 downto 0);
cpu7_idout : out std_logic_vector(7 downto 0)
);
end component;
begin
x0 : grfpushw generic map ((mul mod 4), nshare, tech, arb)
port map (
clk ,
reset ,
fpvi(0).start ,
fpvi(0).nonstd ,
fpvi(0).flop ,
fpvi(0).op1 ,
fpvi(0).op2 ,
fpvi(0).opid ,
fpvi(0).flush ,
fpvi(0).flushid ,
fpvi(0).rndmode ,
fpvi(0).req ,
fpvo(0).res ,
fpvo(0).exc ,
fpvo(0).allow ,
fpvo(0).rdy ,
fpvo(0).cc ,
fpvo(0).idout ,
fpvi(1).start ,
fpvi(1).nonstd ,
fpvi(1).flop ,
fpvi(1).op1 ,
fpvi(1).op2 ,
fpvi(1).opid ,
fpvi(1).flush ,
fpvi(1).flushid ,
fpvi(1).rndmode ,
fpvi(1).req ,
fpvo(1).res ,
fpvo(1).exc ,
fpvo(1).allow ,
fpvo(1).rdy ,
fpvo(1).cc ,
fpvo(1).idout ,
fpvi(2).start ,
fpvi(2).nonstd ,
fpvi(2).flop ,
fpvi(2).op1 ,
fpvi(2).op2 ,
fpvi(2).opid ,
fpvi(2).flush ,
fpvi(2).flushid ,
fpvi(2).rndmode ,
fpvi(2).req ,
fpvo(2).res ,
fpvo(2).exc ,
fpvo(2).allow ,
fpvo(2).rdy ,
fpvo(2).cc ,
fpvo(2).idout ,
fpvi(3).start ,
fpvi(3).nonstd ,
fpvi(3).flop ,
fpvi(3).op1 ,
fpvi(3).op2 ,
fpvi(3).opid ,
fpvi(3).flush ,
fpvi(3).flushid ,
fpvi(3).rndmode ,
fpvi(3).req ,
fpvo(3).res ,
fpvo(3).exc ,
fpvo(3).allow ,
fpvo(3).rdy ,
fpvo(3).cc ,
fpvo(3).idout ,
fpvi(4).start ,
fpvi(4).nonstd ,
fpvi(4).flop ,
fpvi(4).op1 ,
fpvi(4).op2 ,
fpvi(4).opid ,
fpvi(4).flush ,
fpvi(4).flushid ,
fpvi(4).rndmode ,
fpvi(4).req ,
fpvo(4).res ,
fpvo(4).exc ,
fpvo(4).allow ,
fpvo(4).rdy ,
fpvo(4).cc ,
fpvo(4).idout ,
fpvi(5).start ,
fpvi(5).nonstd ,
fpvi(5).flop ,
fpvi(5).op1 ,
fpvi(5).op2 ,
fpvi(5).opid ,
fpvi(5).flush ,
fpvi(5).flushid ,
fpvi(5).rndmode ,
fpvi(5).req ,
fpvo(5).res ,
fpvo(5).exc ,
fpvo(5).allow ,
fpvo(5).rdy ,
fpvo(5).cc ,
fpvo(5).idout ,
fpvi(6).start ,
fpvi(6).nonstd ,
fpvi(6).flop ,
fpvi(6).op1 ,
fpvi(6).op2 ,
fpvi(6).opid ,
fpvi(6).flush ,
fpvi(6).flushid ,
fpvi(6).rndmode ,
fpvi(6).req ,
fpvo(6).res ,
fpvo(6).exc ,
fpvo(6).allow ,
fpvo(6).rdy ,
fpvo(6).cc ,
fpvo(6).idout ,
fpvi(7).start ,
fpvi(7).nonstd ,
fpvi(7).flop ,
fpvi(7).op1 ,
fpvi(7).op2 ,
fpvi(7).opid ,
fpvi(7).flush ,
fpvi(7).flushid ,
fpvi(7).rndmode ,
fpvi(7).req ,
fpvo(7).res ,
fpvo(7).exc ,
fpvo(7).allow ,
fpvo(7).rdy ,
fpvo(7).cc ,
fpvo(7).idout);
end;
|
-----------------------------------------------------------------------------
-- Entity: grfpushwx
-- File: grfpushwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU (shared version) wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.leon3.all;
entity grfpushwx is
generic (mul : integer := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
fpvi : in grfpu_in_vector_type;
fpvo : out grfpu_out_vector_type
);
end;
architecture rtl of grfpushwx is
component grfpushw
generic (mul : integer range 0 to 3 := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
cpu0_start : in std_logic;
cpu0_nonstd : in std_logic;
cpu0_flop : in std_logic_vector(8 downto 0);
cpu0_op1 : in std_logic_vector(63 downto 0);
cpu0_op2 : in std_logic_vector(63 downto 0);
cpu0_opid : in std_logic_vector(7 downto 0);
cpu0_flush : in std_logic;
cpu0_flushid : in std_logic_vector(5 downto 0);
cpu0_rndmode : in std_logic_vector(1 downto 0);
cpu0_req : in std_logic_vector(2 downto 0);
cpu0_res : out std_logic_vector(63 downto 0);
cpu0_exc : out std_logic_vector(5 downto 0);
cpu0_allow : out std_logic_vector(2 downto 0);
cpu0_rdy : out std_logic;
cpu0_cc : out std_logic_vector(1 downto 0);
cpu0_idout : out std_logic_vector(7 downto 0);
cpu1_start : in std_logic;
cpu1_nonstd : in std_logic;
cpu1_flop : in std_logic_vector(8 downto 0);
cpu1_op1 : in std_logic_vector(63 downto 0);
cpu1_op2 : in std_logic_vector(63 downto 0);
cpu1_opid : in std_logic_vector(7 downto 0);
cpu1_flush : in std_logic;
cpu1_flushid : in std_logic_vector(5 downto 0);
cpu1_rndmode : in std_logic_vector(1 downto 0);
cpu1_req : in std_logic_vector(2 downto 0);
cpu1_res : out std_logic_vector(63 downto 0);
cpu1_exc : out std_logic_vector(5 downto 0);
cpu1_allow : out std_logic_vector(2 downto 0);
cpu1_rdy : out std_logic;
cpu1_cc : out std_logic_vector(1 downto 0);
cpu1_idout : out std_logic_vector(7 downto 0);
cpu2_start : in std_logic;
cpu2_nonstd : in std_logic;
cpu2_flop : in std_logic_vector(8 downto 0);
cpu2_op1 : in std_logic_vector(63 downto 0);
cpu2_op2 : in std_logic_vector(63 downto 0);
cpu2_opid : in std_logic_vector(7 downto 0);
cpu2_flush : in std_logic;
cpu2_flushid : in std_logic_vector(5 downto 0);
cpu2_rndmode : in std_logic_vector(1 downto 0);
cpu2_req : in std_logic_vector(2 downto 0);
cpu2_res : out std_logic_vector(63 downto 0);
cpu2_exc : out std_logic_vector(5 downto 0);
cpu2_allow : out std_logic_vector(2 downto 0);
cpu2_rdy : out std_logic;
cpu2_cc : out std_logic_vector(1 downto 0);
cpu2_idout : out std_logic_vector(7 downto 0);
cpu3_start : in std_logic;
cpu3_nonstd : in std_logic;
cpu3_flop : in std_logic_vector(8 downto 0);
cpu3_op1 : in std_logic_vector(63 downto 0);
cpu3_op2 : in std_logic_vector(63 downto 0);
cpu3_opid : in std_logic_vector(7 downto 0);
cpu3_flush : in std_logic;
cpu3_flushid : in std_logic_vector(5 downto 0);
cpu3_rndmode : in std_logic_vector(1 downto 0);
cpu3_req : in std_logic_vector(2 downto 0);
cpu3_res : out std_logic_vector(63 downto 0);
cpu3_exc : out std_logic_vector(5 downto 0);
cpu3_allow : out std_logic_vector(2 downto 0);
cpu3_rdy : out std_logic;
cpu3_cc : out std_logic_vector(1 downto 0);
cpu3_idout : out std_logic_vector(7 downto 0);
cpu4_start : in std_logic;
cpu4_nonstd : in std_logic;
cpu4_flop : in std_logic_vector(8 downto 0);
cpu4_op1 : in std_logic_vector(63 downto 0);
cpu4_op2 : in std_logic_vector(63 downto 0);
cpu4_opid : in std_logic_vector(7 downto 0);
cpu4_flush : in std_logic;
cpu4_flushid : in std_logic_vector(5 downto 0);
cpu4_rndmode : in std_logic_vector(1 downto 0);
cpu4_req : in std_logic_vector(2 downto 0);
cpu4_res : out std_logic_vector(63 downto 0);
cpu4_exc : out std_logic_vector(5 downto 0);
cpu4_allow : out std_logic_vector(2 downto 0);
cpu4_rdy : out std_logic;
cpu4_cc : out std_logic_vector(1 downto 0);
cpu4_idout : out std_logic_vector(7 downto 0);
cpu5_start : in std_logic;
cpu5_nonstd : in std_logic;
cpu5_flop : in std_logic_vector(8 downto 0);
cpu5_op1 : in std_logic_vector(63 downto 0);
cpu5_op2 : in std_logic_vector(63 downto 0);
cpu5_opid : in std_logic_vector(7 downto 0);
cpu5_flush : in std_logic;
cpu5_flushid : in std_logic_vector(5 downto 0);
cpu5_rndmode : in std_logic_vector(1 downto 0);
cpu5_req : in std_logic_vector(2 downto 0);
cpu5_res : out std_logic_vector(63 downto 0);
cpu5_exc : out std_logic_vector(5 downto 0);
cpu5_allow : out std_logic_vector(2 downto 0);
cpu5_rdy : out std_logic;
cpu5_cc : out std_logic_vector(1 downto 0);
cpu5_idout : out std_logic_vector(7 downto 0);
cpu6_start : in std_logic;
cpu6_nonstd : in std_logic;
cpu6_flop : in std_logic_vector(8 downto 0);
cpu6_op1 : in std_logic_vector(63 downto 0);
cpu6_op2 : in std_logic_vector(63 downto 0);
cpu6_opid : in std_logic_vector(7 downto 0);
cpu6_flush : in std_logic;
cpu6_flushid : in std_logic_vector(5 downto 0);
cpu6_rndmode : in std_logic_vector(1 downto 0);
cpu6_req : in std_logic_vector(2 downto 0);
cpu6_res : out std_logic_vector(63 downto 0);
cpu6_exc : out std_logic_vector(5 downto 0);
cpu6_allow : out std_logic_vector(2 downto 0);
cpu6_rdy : out std_logic;
cpu6_cc : out std_logic_vector(1 downto 0);
cpu6_idout : out std_logic_vector(7 downto 0);
cpu7_start : in std_logic;
cpu7_nonstd : in std_logic;
cpu7_flop : in std_logic_vector(8 downto 0);
cpu7_op1 : in std_logic_vector(63 downto 0);
cpu7_op2 : in std_logic_vector(63 downto 0);
cpu7_opid : in std_logic_vector(7 downto 0);
cpu7_flush : in std_logic;
cpu7_flushid : in std_logic_vector(5 downto 0);
cpu7_rndmode : in std_logic_vector(1 downto 0);
cpu7_req : in std_logic_vector(2 downto 0);
cpu7_res : out std_logic_vector(63 downto 0);
cpu7_exc : out std_logic_vector(5 downto 0);
cpu7_allow : out std_logic_vector(2 downto 0);
cpu7_rdy : out std_logic;
cpu7_cc : out std_logic_vector(1 downto 0);
cpu7_idout : out std_logic_vector(7 downto 0)
);
end component;
begin
x0 : grfpushw generic map ((mul mod 4), nshare, tech, arb)
port map (
clk ,
reset ,
fpvi(0).start ,
fpvi(0).nonstd ,
fpvi(0).flop ,
fpvi(0).op1 ,
fpvi(0).op2 ,
fpvi(0).opid ,
fpvi(0).flush ,
fpvi(0).flushid ,
fpvi(0).rndmode ,
fpvi(0).req ,
fpvo(0).res ,
fpvo(0).exc ,
fpvo(0).allow ,
fpvo(0).rdy ,
fpvo(0).cc ,
fpvo(0).idout ,
fpvi(1).start ,
fpvi(1).nonstd ,
fpvi(1).flop ,
fpvi(1).op1 ,
fpvi(1).op2 ,
fpvi(1).opid ,
fpvi(1).flush ,
fpvi(1).flushid ,
fpvi(1).rndmode ,
fpvi(1).req ,
fpvo(1).res ,
fpvo(1).exc ,
fpvo(1).allow ,
fpvo(1).rdy ,
fpvo(1).cc ,
fpvo(1).idout ,
fpvi(2).start ,
fpvi(2).nonstd ,
fpvi(2).flop ,
fpvi(2).op1 ,
fpvi(2).op2 ,
fpvi(2).opid ,
fpvi(2).flush ,
fpvi(2).flushid ,
fpvi(2).rndmode ,
fpvi(2).req ,
fpvo(2).res ,
fpvo(2).exc ,
fpvo(2).allow ,
fpvo(2).rdy ,
fpvo(2).cc ,
fpvo(2).idout ,
fpvi(3).start ,
fpvi(3).nonstd ,
fpvi(3).flop ,
fpvi(3).op1 ,
fpvi(3).op2 ,
fpvi(3).opid ,
fpvi(3).flush ,
fpvi(3).flushid ,
fpvi(3).rndmode ,
fpvi(3).req ,
fpvo(3).res ,
fpvo(3).exc ,
fpvo(3).allow ,
fpvo(3).rdy ,
fpvo(3).cc ,
fpvo(3).idout ,
fpvi(4).start ,
fpvi(4).nonstd ,
fpvi(4).flop ,
fpvi(4).op1 ,
fpvi(4).op2 ,
fpvi(4).opid ,
fpvi(4).flush ,
fpvi(4).flushid ,
fpvi(4).rndmode ,
fpvi(4).req ,
fpvo(4).res ,
fpvo(4).exc ,
fpvo(4).allow ,
fpvo(4).rdy ,
fpvo(4).cc ,
fpvo(4).idout ,
fpvi(5).start ,
fpvi(5).nonstd ,
fpvi(5).flop ,
fpvi(5).op1 ,
fpvi(5).op2 ,
fpvi(5).opid ,
fpvi(5).flush ,
fpvi(5).flushid ,
fpvi(5).rndmode ,
fpvi(5).req ,
fpvo(5).res ,
fpvo(5).exc ,
fpvo(5).allow ,
fpvo(5).rdy ,
fpvo(5).cc ,
fpvo(5).idout ,
fpvi(6).start ,
fpvi(6).nonstd ,
fpvi(6).flop ,
fpvi(6).op1 ,
fpvi(6).op2 ,
fpvi(6).opid ,
fpvi(6).flush ,
fpvi(6).flushid ,
fpvi(6).rndmode ,
fpvi(6).req ,
fpvo(6).res ,
fpvo(6).exc ,
fpvo(6).allow ,
fpvo(6).rdy ,
fpvo(6).cc ,
fpvo(6).idout ,
fpvi(7).start ,
fpvi(7).nonstd ,
fpvi(7).flop ,
fpvi(7).op1 ,
fpvi(7).op2 ,
fpvi(7).opid ,
fpvi(7).flush ,
fpvi(7).flushid ,
fpvi(7).rndmode ,
fpvi(7).req ,
fpvo(7).res ,
fpvo(7).exc ,
fpvo(7).allow ,
fpvo(7).rdy ,
fpvo(7).cc ,
fpvo(7).idout);
end;
|
-----------------------------------------------------------------------------
-- Entity: grfpushwx
-- File: grfpushwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU (shared version) wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library gaisler;
use gaisler.leon3.all;
entity grfpushwx is
generic (mul : integer := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
fpvi : in grfpu_in_vector_type;
fpvo : out grfpu_out_vector_type
);
end;
architecture rtl of grfpushwx is
component grfpushw
generic (mul : integer range 0 to 3 := 0;
nshare : integer range 0 to 8 := 0;
tech : integer;
arb : integer range 0 to 2 := 1);
port(
clk : in std_logic;
reset : in std_logic;
cpu0_start : in std_logic;
cpu0_nonstd : in std_logic;
cpu0_flop : in std_logic_vector(8 downto 0);
cpu0_op1 : in std_logic_vector(63 downto 0);
cpu0_op2 : in std_logic_vector(63 downto 0);
cpu0_opid : in std_logic_vector(7 downto 0);
cpu0_flush : in std_logic;
cpu0_flushid : in std_logic_vector(5 downto 0);
cpu0_rndmode : in std_logic_vector(1 downto 0);
cpu0_req : in std_logic_vector(2 downto 0);
cpu0_res : out std_logic_vector(63 downto 0);
cpu0_exc : out std_logic_vector(5 downto 0);
cpu0_allow : out std_logic_vector(2 downto 0);
cpu0_rdy : out std_logic;
cpu0_cc : out std_logic_vector(1 downto 0);
cpu0_idout : out std_logic_vector(7 downto 0);
cpu1_start : in std_logic;
cpu1_nonstd : in std_logic;
cpu1_flop : in std_logic_vector(8 downto 0);
cpu1_op1 : in std_logic_vector(63 downto 0);
cpu1_op2 : in std_logic_vector(63 downto 0);
cpu1_opid : in std_logic_vector(7 downto 0);
cpu1_flush : in std_logic;
cpu1_flushid : in std_logic_vector(5 downto 0);
cpu1_rndmode : in std_logic_vector(1 downto 0);
cpu1_req : in std_logic_vector(2 downto 0);
cpu1_res : out std_logic_vector(63 downto 0);
cpu1_exc : out std_logic_vector(5 downto 0);
cpu1_allow : out std_logic_vector(2 downto 0);
cpu1_rdy : out std_logic;
cpu1_cc : out std_logic_vector(1 downto 0);
cpu1_idout : out std_logic_vector(7 downto 0);
cpu2_start : in std_logic;
cpu2_nonstd : in std_logic;
cpu2_flop : in std_logic_vector(8 downto 0);
cpu2_op1 : in std_logic_vector(63 downto 0);
cpu2_op2 : in std_logic_vector(63 downto 0);
cpu2_opid : in std_logic_vector(7 downto 0);
cpu2_flush : in std_logic;
cpu2_flushid : in std_logic_vector(5 downto 0);
cpu2_rndmode : in std_logic_vector(1 downto 0);
cpu2_req : in std_logic_vector(2 downto 0);
cpu2_res : out std_logic_vector(63 downto 0);
cpu2_exc : out std_logic_vector(5 downto 0);
cpu2_allow : out std_logic_vector(2 downto 0);
cpu2_rdy : out std_logic;
cpu2_cc : out std_logic_vector(1 downto 0);
cpu2_idout : out std_logic_vector(7 downto 0);
cpu3_start : in std_logic;
cpu3_nonstd : in std_logic;
cpu3_flop : in std_logic_vector(8 downto 0);
cpu3_op1 : in std_logic_vector(63 downto 0);
cpu3_op2 : in std_logic_vector(63 downto 0);
cpu3_opid : in std_logic_vector(7 downto 0);
cpu3_flush : in std_logic;
cpu3_flushid : in std_logic_vector(5 downto 0);
cpu3_rndmode : in std_logic_vector(1 downto 0);
cpu3_req : in std_logic_vector(2 downto 0);
cpu3_res : out std_logic_vector(63 downto 0);
cpu3_exc : out std_logic_vector(5 downto 0);
cpu3_allow : out std_logic_vector(2 downto 0);
cpu3_rdy : out std_logic;
cpu3_cc : out std_logic_vector(1 downto 0);
cpu3_idout : out std_logic_vector(7 downto 0);
cpu4_start : in std_logic;
cpu4_nonstd : in std_logic;
cpu4_flop : in std_logic_vector(8 downto 0);
cpu4_op1 : in std_logic_vector(63 downto 0);
cpu4_op2 : in std_logic_vector(63 downto 0);
cpu4_opid : in std_logic_vector(7 downto 0);
cpu4_flush : in std_logic;
cpu4_flushid : in std_logic_vector(5 downto 0);
cpu4_rndmode : in std_logic_vector(1 downto 0);
cpu4_req : in std_logic_vector(2 downto 0);
cpu4_res : out std_logic_vector(63 downto 0);
cpu4_exc : out std_logic_vector(5 downto 0);
cpu4_allow : out std_logic_vector(2 downto 0);
cpu4_rdy : out std_logic;
cpu4_cc : out std_logic_vector(1 downto 0);
cpu4_idout : out std_logic_vector(7 downto 0);
cpu5_start : in std_logic;
cpu5_nonstd : in std_logic;
cpu5_flop : in std_logic_vector(8 downto 0);
cpu5_op1 : in std_logic_vector(63 downto 0);
cpu5_op2 : in std_logic_vector(63 downto 0);
cpu5_opid : in std_logic_vector(7 downto 0);
cpu5_flush : in std_logic;
cpu5_flushid : in std_logic_vector(5 downto 0);
cpu5_rndmode : in std_logic_vector(1 downto 0);
cpu5_req : in std_logic_vector(2 downto 0);
cpu5_res : out std_logic_vector(63 downto 0);
cpu5_exc : out std_logic_vector(5 downto 0);
cpu5_allow : out std_logic_vector(2 downto 0);
cpu5_rdy : out std_logic;
cpu5_cc : out std_logic_vector(1 downto 0);
cpu5_idout : out std_logic_vector(7 downto 0);
cpu6_start : in std_logic;
cpu6_nonstd : in std_logic;
cpu6_flop : in std_logic_vector(8 downto 0);
cpu6_op1 : in std_logic_vector(63 downto 0);
cpu6_op2 : in std_logic_vector(63 downto 0);
cpu6_opid : in std_logic_vector(7 downto 0);
cpu6_flush : in std_logic;
cpu6_flushid : in std_logic_vector(5 downto 0);
cpu6_rndmode : in std_logic_vector(1 downto 0);
cpu6_req : in std_logic_vector(2 downto 0);
cpu6_res : out std_logic_vector(63 downto 0);
cpu6_exc : out std_logic_vector(5 downto 0);
cpu6_allow : out std_logic_vector(2 downto 0);
cpu6_rdy : out std_logic;
cpu6_cc : out std_logic_vector(1 downto 0);
cpu6_idout : out std_logic_vector(7 downto 0);
cpu7_start : in std_logic;
cpu7_nonstd : in std_logic;
cpu7_flop : in std_logic_vector(8 downto 0);
cpu7_op1 : in std_logic_vector(63 downto 0);
cpu7_op2 : in std_logic_vector(63 downto 0);
cpu7_opid : in std_logic_vector(7 downto 0);
cpu7_flush : in std_logic;
cpu7_flushid : in std_logic_vector(5 downto 0);
cpu7_rndmode : in std_logic_vector(1 downto 0);
cpu7_req : in std_logic_vector(2 downto 0);
cpu7_res : out std_logic_vector(63 downto 0);
cpu7_exc : out std_logic_vector(5 downto 0);
cpu7_allow : out std_logic_vector(2 downto 0);
cpu7_rdy : out std_logic;
cpu7_cc : out std_logic_vector(1 downto 0);
cpu7_idout : out std_logic_vector(7 downto 0)
);
end component;
begin
x0 : grfpushw generic map ((mul mod 4), nshare, tech, arb)
port map (
clk ,
reset ,
fpvi(0).start ,
fpvi(0).nonstd ,
fpvi(0).flop ,
fpvi(0).op1 ,
fpvi(0).op2 ,
fpvi(0).opid ,
fpvi(0).flush ,
fpvi(0).flushid ,
fpvi(0).rndmode ,
fpvi(0).req ,
fpvo(0).res ,
fpvo(0).exc ,
fpvo(0).allow ,
fpvo(0).rdy ,
fpvo(0).cc ,
fpvo(0).idout ,
fpvi(1).start ,
fpvi(1).nonstd ,
fpvi(1).flop ,
fpvi(1).op1 ,
fpvi(1).op2 ,
fpvi(1).opid ,
fpvi(1).flush ,
fpvi(1).flushid ,
fpvi(1).rndmode ,
fpvi(1).req ,
fpvo(1).res ,
fpvo(1).exc ,
fpvo(1).allow ,
fpvo(1).rdy ,
fpvo(1).cc ,
fpvo(1).idout ,
fpvi(2).start ,
fpvi(2).nonstd ,
fpvi(2).flop ,
fpvi(2).op1 ,
fpvi(2).op2 ,
fpvi(2).opid ,
fpvi(2).flush ,
fpvi(2).flushid ,
fpvi(2).rndmode ,
fpvi(2).req ,
fpvo(2).res ,
fpvo(2).exc ,
fpvo(2).allow ,
fpvo(2).rdy ,
fpvo(2).cc ,
fpvo(2).idout ,
fpvi(3).start ,
fpvi(3).nonstd ,
fpvi(3).flop ,
fpvi(3).op1 ,
fpvi(3).op2 ,
fpvi(3).opid ,
fpvi(3).flush ,
fpvi(3).flushid ,
fpvi(3).rndmode ,
fpvi(3).req ,
fpvo(3).res ,
fpvo(3).exc ,
fpvo(3).allow ,
fpvo(3).rdy ,
fpvo(3).cc ,
fpvo(3).idout ,
fpvi(4).start ,
fpvi(4).nonstd ,
fpvi(4).flop ,
fpvi(4).op1 ,
fpvi(4).op2 ,
fpvi(4).opid ,
fpvi(4).flush ,
fpvi(4).flushid ,
fpvi(4).rndmode ,
fpvi(4).req ,
fpvo(4).res ,
fpvo(4).exc ,
fpvo(4).allow ,
fpvo(4).rdy ,
fpvo(4).cc ,
fpvo(4).idout ,
fpvi(5).start ,
fpvi(5).nonstd ,
fpvi(5).flop ,
fpvi(5).op1 ,
fpvi(5).op2 ,
fpvi(5).opid ,
fpvi(5).flush ,
fpvi(5).flushid ,
fpvi(5).rndmode ,
fpvi(5).req ,
fpvo(5).res ,
fpvo(5).exc ,
fpvo(5).allow ,
fpvo(5).rdy ,
fpvo(5).cc ,
fpvo(5).idout ,
fpvi(6).start ,
fpvi(6).nonstd ,
fpvi(6).flop ,
fpvi(6).op1 ,
fpvi(6).op2 ,
fpvi(6).opid ,
fpvi(6).flush ,
fpvi(6).flushid ,
fpvi(6).rndmode ,
fpvi(6).req ,
fpvo(6).res ,
fpvo(6).exc ,
fpvo(6).allow ,
fpvo(6).rdy ,
fpvo(6).cc ,
fpvo(6).idout ,
fpvi(7).start ,
fpvi(7).nonstd ,
fpvi(7).flop ,
fpvi(7).op1 ,
fpvi(7).op2 ,
fpvi(7).opid ,
fpvi(7).flush ,
fpvi(7).flushid ,
fpvi(7).rndmode ,
fpvi(7).req ,
fpvo(7).res ,
fpvo(7).exc ,
fpvo(7).allow ,
fpvo(7).rdy ,
fpvo(7).cc ,
fpvo(7).idout);
end;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_wishbone_pack.all ;
entity wishbone_intercon is
generic(memory_map : array_of_addr );
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone slave signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector(15 downto 0);
wbs_readdata : out std_logic_vector(15 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- Wishbone master signals
wbm_address : out array_of_slv16((memory_map'length-1) downto 0) ;
wbm_writedata : out array_of_slv16((memory_map'length-1) downto 0);
wbm_readdata : in array_of_slv16((memory_map'length-1) downto 0);
wbm_strobe : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_cycle : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_write : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_ack : in std_logic_vector((memory_map'length-1) downto 0)
);
end wishbone_intercon;
architecture Behavioral of wishbone_intercon is
signal cs_vector : std_logic_vector(0 to (memory_map'length-1));
signal ack_vector : std_logic_vector(0 to (memory_map'length-1));
begin
gen_cs : for i in 0 to (memory_map'length-1) generate
cs_vector(i) <= '1' when wbs_address(wbs_address'length-1 downto find_X(memory_map(i))) = memory_map(i)(wbs_address'length-1 downto find_X(memory_map(i))) else
'0' ;
ack_vector(i) <= wbm_ack(i) and cs_vector(i) ;
wbm_address(i)(wbs_address'length-1 downto find_X(memory_map(i))) <= (others => '0') ;
wbm_address(i)(find_X(memory_map(i))-1 downto 0) <= wbs_address(find_X(memory_map(i))-1 downto 0) ;
wbm_writedata(i) <= wbs_writedata ;
wbm_write(i) <= wbs_write and cs_vector(i) ;
wbm_strobe(i) <= wbs_strobe and cs_vector(i) ;
wbm_cycle(i) <= wbs_cycle and cs_vector(i) ;
wbs_readdata <= wbm_readdata(i) when cs_vector(i) = '1' else
(others => 'Z') ;
end generate ;
wbs_ack <= '1' when ack_vector /= 0 else
'0' ;
wbs_readdata <= wbs_address when cs_vector = 0 else
(others => 'Z') ;
end Behavioral;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_wishbone_pack.all ;
entity wishbone_intercon is
generic(memory_map : array_of_addr );
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone slave signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector(15 downto 0);
wbs_readdata : out std_logic_vector(15 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- Wishbone master signals
wbm_address : out array_of_slv16((memory_map'length-1) downto 0) ;
wbm_writedata : out array_of_slv16((memory_map'length-1) downto 0);
wbm_readdata : in array_of_slv16((memory_map'length-1) downto 0);
wbm_strobe : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_cycle : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_write : out std_logic_vector((memory_map'length-1) downto 0) ;
wbm_ack : in std_logic_vector((memory_map'length-1) downto 0)
);
end wishbone_intercon;
architecture Behavioral of wishbone_intercon is
signal cs_vector : std_logic_vector(0 to (memory_map'length-1));
signal ack_vector : std_logic_vector(0 to (memory_map'length-1));
begin
gen_cs : for i in 0 to (memory_map'length-1) generate
cs_vector(i) <= '1' when wbs_address(wbs_address'length-1 downto find_X(memory_map(i))) = memory_map(i)(wbs_address'length-1 downto find_X(memory_map(i))) else
'0' ;
ack_vector(i) <= wbm_ack(i) and cs_vector(i) ;
wbm_address(i)(wbs_address'length-1 downto find_X(memory_map(i))) <= (others => '0') ;
wbm_address(i)(find_X(memory_map(i))-1 downto 0) <= wbs_address(find_X(memory_map(i))-1 downto 0) ;
wbm_writedata(i) <= wbs_writedata ;
wbm_write(i) <= wbs_write and cs_vector(i) ;
wbm_strobe(i) <= wbs_strobe and cs_vector(i) ;
wbm_cycle(i) <= wbs_cycle and cs_vector(i) ;
wbs_readdata <= wbm_readdata(i) when cs_vector(i) = '1' else
(others => 'Z') ;
end generate ;
wbs_ack <= '1' when ack_vector /= 0 else
'0' ;
wbs_readdata <= wbs_address when cs_vector = 0 else
(others => 'Z') ;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2339.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02339ent IS
END c07s02b07x00p02n02i02339ent;
ARCHITECTURE c07s02b07x00p02n02i02339arch OF c07s02b07x00p02n02i02339ent IS
BEGIN
TESTING: PROCESS
type WORD is array(0 to 31) of BIT;
variable WORDV : WORD;
variable INTV : INTEGER;
BEGIN
INTV := WORDV ** 2;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02339 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02339arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2339.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02339ent IS
END c07s02b07x00p02n02i02339ent;
ARCHITECTURE c07s02b07x00p02n02i02339arch OF c07s02b07x00p02n02i02339ent IS
BEGIN
TESTING: PROCESS
type WORD is array(0 to 31) of BIT;
variable WORDV : WORD;
variable INTV : INTEGER;
BEGIN
INTV := WORDV ** 2;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02339 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02339arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2339.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02339ent IS
END c07s02b07x00p02n02i02339ent;
ARCHITECTURE c07s02b07x00p02n02i02339arch OF c07s02b07x00p02n02i02339ent IS
BEGIN
TESTING: PROCESS
type WORD is array(0 to 31) of BIT;
variable WORDV : WORD;
variable INTV : INTEGER;
BEGIN
INTV := WORDV ** 2;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02339 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02339arch;
|
----------------------------------------------------------------------------------
-- Company: NTU Athens - BNL
-- Engineer: Christos Bakalis ([email protected])
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 02.04.2017
-- Design Name: ICMP UDP MUX
-- Module Name: icmp_udp_mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions: Vivado 2016.2
-- Description: This module instantiates a multiplexer that selects between data
-- input from UDP_TX or ICMP_TX and forwards the data to the IP layer.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.axi.all;
use work.ipv4_types.all;
entity icmp_udp_mux is
Port(
sel_icmp : in std_logic;
ip_tx_start_icmp : in std_logic;
ip_tx_icmp : in ipv4_tx_type;
ip_tx_start_udp : in std_logic;
ip_tx_udp : in ipv4_tx_type;
ip_tx_start_IP : out std_logic;
ip_tx_IP : out ipv4_tx_type
);
end icmp_udp_mux;
architecture Behavioral of icmp_udp_mux is
begin
ICMPudpMUX_proc: process(sel_icmp, ip_tx_start_icmp, ip_tx_icmp, ip_tx_start_udp, ip_tx_udp)
begin
case sel_icmp is
when '0' =>
ip_tx_start_IP <= ip_tx_start_udp;
ip_tx_IP <= ip_tx_udp;
when '1' =>
ip_tx_start_IP <= ip_tx_start_icmp;
ip_tx_IP <= ip_tx_icmp;
when others =>
ip_tx_start_IP <= '0';
ip_tx_IP.hdr.protocol <= (others => '0');
ip_tx_IP.hdr.data_length <= (others => '0');
ip_tx_IP.hdr.dst_ip_addr <= (others => '0');
ip_tx_IP.data.data_out <= (others => '0');
ip_tx_IP.data.data_out_valid <= '0';
ip_tx_IP.data.data_out_last <= '0';
end case;
end process;
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adders_4 is
port(A,B : in std_logic_vector(7 downto 0);
CI : in std_logic;
SUM : out std_logic_vector(7 downto 0);
CO : out std_logic);
end adders_4;
architecture archi of adders_4 is
signal tmp: std_logic_vector(8 downto 0);
begin
tmp <= conv_std_logic_vector((conv_integer(A) + conv_integer(B) + conv_integer(CI)),9);
SUM <= tmp(7 downto 0);
CO <= tmp(8);
end archi;
|
-- unnamed.vhd
-- Generated using ACDS version 16.1 200
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity unnamed is
port (
inclk : in std_logic := '0'; -- altclkctrl_input.inclk
ena : in std_logic := '0'; -- .ena
outclk : out std_logic -- altclkctrl_output.outclk
);
end entity unnamed;
architecture rtl of unnamed is
component unnamed_altclkctrl_0 is
port (
inclk : in std_logic := 'X'; -- inclk
ena : in std_logic := 'X'; -- ena
outclk : out std_logic -- outclk
);
end component unnamed_altclkctrl_0;
begin
altclkctrl_0 : component unnamed_altclkctrl_0
port map (
inclk => inclk, -- altclkctrl_input.inclk
ena => ena, -- .ena
outclk => outclk -- altclkctrl_output.outclk
);
end architecture rtl; -- of unnamed
|
-- unnamed.vhd
-- Generated using ACDS version 16.1 200
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity unnamed is
port (
inclk : in std_logic := '0'; -- altclkctrl_input.inclk
ena : in std_logic := '0'; -- .ena
outclk : out std_logic -- altclkctrl_output.outclk
);
end entity unnamed;
architecture rtl of unnamed is
component unnamed_altclkctrl_0 is
port (
inclk : in std_logic := 'X'; -- inclk
ena : in std_logic := 'X'; -- ena
outclk : out std_logic -- outclk
);
end component unnamed_altclkctrl_0;
begin
altclkctrl_0 : component unnamed_altclkctrl_0
port map (
inclk => inclk, -- altclkctrl_input.inclk
ena => ena, -- .ena
outclk => outclk -- altclkctrl_output.outclk
);
end architecture rtl; -- of unnamed
|
-- unnamed.vhd
-- Generated using ACDS version 16.1 200
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity unnamed is
port (
inclk : in std_logic := '0'; -- altclkctrl_input.inclk
ena : in std_logic := '0'; -- .ena
outclk : out std_logic -- altclkctrl_output.outclk
);
end entity unnamed;
architecture rtl of unnamed is
component unnamed_altclkctrl_0 is
port (
inclk : in std_logic := 'X'; -- inclk
ena : in std_logic := 'X'; -- ena
outclk : out std_logic -- outclk
);
end component unnamed_altclkctrl_0;
begin
altclkctrl_0 : component unnamed_altclkctrl_0
port map (
inclk => inclk, -- altclkctrl_input.inclk
ena => ena, -- .ena
outclk => outclk -- altclkctrl_output.outclk
);
end architecture rtl; -- of unnamed
|
-- unnamed.vhd
-- Generated using ACDS version 16.1 200
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity unnamed is
port (
inclk : in std_logic := '0'; -- altclkctrl_input.inclk
ena : in std_logic := '0'; -- .ena
outclk : out std_logic -- altclkctrl_output.outclk
);
end entity unnamed;
architecture rtl of unnamed is
component unnamed_altclkctrl_0 is
port (
inclk : in std_logic := 'X'; -- inclk
ena : in std_logic := 'X'; -- ena
outclk : out std_logic -- outclk
);
end component unnamed_altclkctrl_0;
begin
altclkctrl_0 : component unnamed_altclkctrl_0
port map (
inclk => inclk, -- altclkctrl_input.inclk
ena => ena, -- .ena
outclk => outclk -- altclkctrl_output.outclk
);
end architecture rtl; -- of unnamed
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity StateMachine is
port (
clk : in std_logic;
nReset : in std_logic;
Dout : out std_logic_vector(7 downto 0); -- data read from ds1621
error : out std_logic; -- no correct ack received
SCL : inout std_logic;
SDA : inout std_logic
);
end entity StateMachine;
architecture structural of StateMachine is
---------------------------------------------------------------------------
YUVmachine: process (Hsync, Vsync, YUV_Cstate)
begin
case YUV_Cstate is
when "000" =>
YUV_Nstate <="001";
YUVclk<= '0';
Yclk<='0';
Uclk<='0';
Y1clk<='0';
Vclk<='0';
when "001" =>
YUV_Nstate <="010";
YUVclk<='1' ; --and Hsync;
Yclk<='1';
Uclk<='0';
Y1clk<='0';
Vclk<='0';
when "010" =>
YUV_Nstate <="011";
YUVclk<='0';
Yclk<='0';
Uclk<='1';
Y1clk<='0';
Vclk<='0';
when "011" =>
YUV_Nstate <="100";
YUVclk<='0';
Yclk<='0';
Uclk<='0';
Y1clk<='1';
Vclk<='0';
when "100" =>
YUV_Nstate <="001";
YUVclk<='0';
Yclk<='0';
Uclk<='0';
Y1clk<='0';
Vclk<='1';
when others =>
Yclk<='0';
Uclk<='0';
Y1clk<='0';
Vclk<='0';
YUV_Nstate <="001";
YUVclk<='0';
end case;
-- genregs
if (Hsync='0') then
YUV_Cstate <="000";
elsif (clk'event) and (clk = '0') then -- PC 04.08.06 was '1'
YUV_Cstate<=YUV_Nstate;
end if;
end process structural;
--------------------------------------------------------------------------- |
architecture RTL of FIFO is
begin
process
begin
loop
end loop;
-- Violations below
loop end
loop;
end process;
end;
|
architecture RTL of ENTITY1 is
signal sig1, sig2 : std_logic;
signal sig9 : std_logic;
signal sig3 : std_logic;
signal sig4 : std_logic;
signal sig5 : std_logic;
signal sig6 : std_logic;
signal sig7 : std_logic;
component COMP1 is
port (
SIG1 : in std_logic;
SIG2 : out std_logic;
SIG3 : in std_logic
);
end component COMP1;
begin
PROC_NAME : process (sig2) is
begin
sig1 <= '0';
if (sig2 = '0') then
sig1 <= '1';
elsif (sig2 = '1') then
sig1 <= '0';
end if;
end process PROC_NAME;
-- This is a component that is brought in by a component declaration in the same file
U_COMP1 : COMP1
port map (
SIG1 => sig1,
SIG2 => sig2,
SIG3 => sig3
);
-- This is a component that is brought in by a package
U_COMP2 : COMP2
port map (
SIG3 => sig3,
SIG4 => sig4,
SIG5 => sig5
);
-- This is a component that is directly instantiated
U_COMP3 : entity library.COMP3
port map (
SIG6 => sig6,
SIG7 => sig7
);
sig1 <= '0';
sig1 <= sig2 and sig3;
sig1 <= sig2 and sig3;
sig1 <= sig2 and
sig3;
sig1 <= sig2 and sig3;
sig1 <= sig1 or sig1;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCMSID0 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end DCMSID0;
architecture BEHAVIORAL of DCMSID0 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0,
CLKFX_DIVIDE => 16,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.344,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
library ieee;
use ieee.std_logic_1164.all;
entity fsm_6s is
port (clk : std_logic;
rst : std_logic;
d : std_logic;
done : out std_logic);
end fsm_6s;
architecture behav of fsm_6s is
type state_t is (S0_1, S1_0, S2_0, S3_1, S4_0, S5_1);
signal s : state_t;
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
s <= S0_1;
done <= '0';
else
-- Reset by default
s <= S0_1;
done <= '0';
case s is
when S0_1 =>
if d = '1' then
s <= S1_0;
end if;
when S1_0 =>
if d = '0' then
s <= S2_0;
end if;
when S2_0 =>
if d = '0' then
s <= S3_1;
end if;
when S3_1 =>
if d = '1' then
s <= S4_0;
end if;
when S4_0 =>
if d = '0' then
s <= S5_1;
end if;
when S5_1 =>
if d = '1' then
done <= '1';
end if;
end case;
end if;
end if;
end process;
end behav;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:28:10 07/01/2014
-- Design Name:
-- Module Name: i2c_master - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity i2c_master is
generic(i2c_freq_hz : positive := 100_000;
clk_freq_hz : positive := 100_000_000);
port(
clk : in std_logic;
reset : in std_logic;
slave_addr : in std_logic_vector(6 downto 0 );
data_in : in std_logic_vector(7 downto 0 );
i2c_read : in std_logic;
i2c_write : in std_logic;
scl : inout std_logic;
sda : inout std_logic;
data_out : out std_logic_vector(7 downto 0 );
new_data : out std_logic ;
ack, nack, busy : out std_logic
);
end i2c_master;
architecture Behavioral of i2c_master is
constant clk_div : positive := ((clk_freq_hz/i2c_freq_hz)/4)-1 ;
TYPE master_state IS (IDLE, I2C_START, TX_ADDR, ACK_ADDR, TX_BYTE, RX_BYTE, ACK_BYTE, HOLDING, I2C_STOP) ;
signal cur_state, next_state : master_state ;
signal modulo_counter : std_logic_vector(15 downto 0);
signal end_modulo : std_logic ;
signal cycle_counter : std_logic_vector(1 downto 0);
signal quarter, half, full : std_logic ;
signal transmit_buffer, receive_buffer, addr_buffer : std_logic_vector(7 downto 0);
signal bit_counter : std_logic_vector(2 downto 0);
signal write_mode : std_logic ;
signal sda_unbuf, sda_latched : std_logic ;
signal sda_shift_reg : std_logic_vector(5 downto 0);
signal is_acked : std_logic ;
begin
process(clk, reset)
begin
if reset = '1' then
modulo_counter <= std_logic_vector(to_unsigned(clk_div, 16));
cycle_counter <= (others => '0');
elsif clk'event and clk = '1' then
if cur_state = IDLE then
modulo_counter <= std_logic_vector(to_unsigned(clk_div, 16));
cycle_counter <= (others => '0');
elsif modulo_counter = 0 then
modulo_counter <= std_logic_vector(to_unsigned(clk_div, 16));
cycle_counter <= cycle_counter + 1;
else
modulo_counter <= modulo_counter - 1 ;
end if ;
end if ;
end process ;
end_modulo <= '1' when modulo_counter = 0 else
'0' ;
quarter <= '1' when cycle_counter = 1 else
'1' when cycle_counter = 3 else
'0' ;
half <= '1' when cycle_counter = 2 else
'0' ;
full <= '1' when cycle_counter = 3 and end_modulo = '1' else
'0' ;
process(clk, reset)
begin
if reset = '1' then
cur_state <= IDLE ;
elsif clk'event and clk = '1' then
cur_state <= next_state ;
end if ;
end process ;
process(cur_state, bit_counter, write_mode, cycle_counter, end_modulo, quarter, half, full, i2c_write, i2c_read, sda)
begin
next_state <= cur_state ;
case (cur_state) is
when IDLE =>
if i2c_write = '1' then
next_state <= I2C_START ;
elsif i2c_read = '1' then
next_state <= I2C_START ;
end if ;
when I2C_START =>
if full = '1' then
next_state <= TX_ADDR ;
end if ;
when TX_ADDR =>
if full = '1' and bit_counter = 7 then
next_state <= ACK_ADDR ;
end if ;
when ACK_ADDR =>
if full = '1' and is_acked = '1' and write_mode = '1' then
next_state <= TX_BYTE ;
elsif full = '1' and is_acked = '1' and write_mode = '0' then
next_state <= RX_BYTE ;
elsif full = '1' and is_acked = '0' then
next_state <= I2C_STOP ;
end if ;
when TX_BYTE =>
if full = '1' and bit_counter = 7 then
next_state <= ACK_BYTE ;
end if ;
when RX_BYTE =>
if full = '1' and bit_counter = 7 then
next_state <= ACK_BYTE ;
end if ;
when ACK_BYTE =>
if full = '1' and i2c_write = '1' and is_acked = '1' then --
next_state <= TX_BYTE ;
elsif full = '1' and i2c_read = '1' then
next_state <= RX_BYTE ;
elsif full = '1' then
next_state <= I2C_STOP ;
end if ;
when I2C_STOP =>
if full = '1' then
next_state <= IDLE ;
end if ;
when others =>
end case ;
end process ;
scl <= 'Z' when cur_state = I2C_START and cycle_counter < 2 else
'0' when cur_state = I2C_START and cycle_counter >= 2 else
'Z' when cur_state = IDLE else
'0' when cycle_counter < 2 else
'Z' ;
sda_unbuf <= '0' when cur_state = I2C_START else
'0' when cur_state = I2C_STOP and cycle_counter <= 2 else
'1' when cur_state = I2C_STOP and cycle_counter > 2 else -- need to make sure its enough ...
'1' when cur_state = IDLE else
'1' when cur_state = TX_ADDR and addr_buffer(7) = '1' else
'0' when cur_state = TX_ADDR and addr_buffer(7) = '0' else
'1' when cur_state = TX_BYTE and transmit_buffer(7) = '1' else
'0' when cur_state = TX_BYTE and transmit_buffer(7) = '0' else
'0' when cur_state = ACK_BYTE and write_mode = '0' and i2c_read = '1' else
'1' ;
process(clk, reset)
begin
if reset = '1' then
sda_shift_reg <= (others => '1');
elsif clk'event and clk = '1' then
sda_shift_reg(0) <= sda_unbuf ;
sda_shift_reg(sda_shift_reg'high downto 1) <= sda_shift_reg(sda_shift_reg'high-1 downto 0);
end if ;
end process ;
sda <= 'Z' when cur_state = ACK_BYTE and write_mode = '1' else
'0' when sda_shift_reg(sda_shift_reg'high) = '0' else
'Z' ;
process(clk, reset)
begin
if reset = '1' then
is_acked <= '0' ;
elsif clk'event and clk = '1' then
if (cur_state = ACK_BYTE or cur_state = ACK_ADDR ) and sda = '0' then
is_acked <= '1' ;
elsif cur_state /= ACK_BYTE then
is_acked <= '0' ;
end if ;
end if ;
end process ;
ack <= '1' when cur_state = ACK_BYTE and is_acked = '1' and full = '1' else
'1' when cur_state = ACK_BYTE and next_state = RX_BYTE else
'1' when cur_state = ACK_ADDR and is_acked = '1' and full = '1' else
'0' ;
nack <= '1' when cur_state = ACK_BYTE and write_mode = '1' and full='1' and is_acked = '0' else
'1' when cur_state = ACK_ADDR and full='1' and is_acked = '0' else
'0' ;
busy <= '0' when cur_state = IDLE else
'1' ;
new_data <= '1' when cur_state = ACK_BYTE and write_mode = '0' else
'0' ;
process(clk, reset)
begin
if reset = '1' then
transmit_buffer <= (others => '0') ;
receive_buffer <= (others => '0') ;
addr_buffer <= (others => '0') ;
bit_counter <= (others => '0') ;
elsif clk'event and clk = '1' then
if (cur_state = IDLE and i2c_write = '1') or i2c_read = '1' then
addr_buffer <= slave_addr & i2c_read ;
elsif cur_state = TX_ADDR and full = '1' then
addr_buffer(7 downto 1) <= addr_buffer(6 downto 0);
end if;
if cur_state = IDLE and i2c_write = '1' then
transmit_buffer <= data_in ;
elsif cur_state = TX_BYTE and full = '1' then
transmit_buffer(7 downto 1) <= transmit_buffer(6 downto 0);
transmit_buffer(0) <= '0' ;
elsif cur_state = ACK_BYTE and i2c_write = '1' and is_acked = '1' then
transmit_buffer <= data_in;
end if;
if cur_state = IDLE then
receive_buffer <= (others => '0') ;
elsif cur_state = RX_BYTE and half = '1' then
receive_buffer(7 downto 1) <= receive_buffer(6 downto 0);
receive_buffer(0) <= sda ;
end if;
if cur_state = IDLE or cur_state = ACK_BYTE or cur_state = ACK_ADDR then
bit_counter <= (others => '0') ;
elsif (cur_state = TX_ADDR or cur_state = TX_BYTE) and full = '1' then
bit_counter <= bit_counter + 1 ;
end if;
end if ;
end process ;
process(clk, reset)
begin
if reset = '1' then
write_mode <= '0' ;
elsif clk'event and clk = '1' then
if cur_state = IDLE and i2c_write = '1' then
write_mode <= '1' ;
elsif cur_state = I2C_STOP then
write_mode <= '0' ;
end if;
end if ;
end process ;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:28:10 07/01/2014
-- Design Name:
-- Module Name: i2c_master - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity i2c_master is
generic(i2c_freq_hz : positive := 100_000;
clk_freq_hz : positive := 100_000_000);
port(
clk : in std_logic;
reset : in std_logic;
slave_addr : in std_logic_vector(6 downto 0 );
data_in : in std_logic_vector(7 downto 0 );
i2c_read : in std_logic;
i2c_write : in std_logic;
scl : inout std_logic;
sda : inout std_logic;
data_out : out std_logic_vector(7 downto 0 );
new_data : out std_logic ;
ack, nack, busy : out std_logic
);
end i2c_master;
architecture Behavioral of i2c_master is
constant clk_div : positive := ((clk_freq_hz/i2c_freq_hz)/4)-1 ;
TYPE master_state IS (IDLE, I2C_START, TX_ADDR, ACK_ADDR, TX_BYTE, RX_BYTE, ACK_BYTE, HOLDING, I2C_STOP) ;
signal cur_state, next_state : master_state ;
signal modulo_counter : std_logic_vector(15 downto 0);
signal end_modulo : std_logic ;
signal cycle_counter : std_logic_vector(1 downto 0);
signal quarter, half, full : std_logic ;
signal transmit_buffer, receive_buffer, addr_buffer : std_logic_vector(7 downto 0);
signal bit_counter : std_logic_vector(2 downto 0);
signal write_mode : std_logic ;
signal sda_unbuf, sda_latched : std_logic ;
signal sda_shift_reg : std_logic_vector(5 downto 0);
signal is_acked : std_logic ;
begin
process(clk, reset)
begin
if reset = '1' then
modulo_counter <= std_logic_vector(to_unsigned(clk_div, 16));
cycle_counter <= (others => '0');
elsif clk'event and clk = '1' then
if cur_state = IDLE then
modulo_counter <= std_logic_vector(to_unsigned(clk_div, 16));
cycle_counter <= (others => '0');
elsif modulo_counter = 0 then
modulo_counter <= std_logic_vector(to_unsigned(clk_div, 16));
cycle_counter <= cycle_counter + 1;
else
modulo_counter <= modulo_counter - 1 ;
end if ;
end if ;
end process ;
end_modulo <= '1' when modulo_counter = 0 else
'0' ;
quarter <= '1' when cycle_counter = 1 else
'1' when cycle_counter = 3 else
'0' ;
half <= '1' when cycle_counter = 2 else
'0' ;
full <= '1' when cycle_counter = 3 and end_modulo = '1' else
'0' ;
process(clk, reset)
begin
if reset = '1' then
cur_state <= IDLE ;
elsif clk'event and clk = '1' then
cur_state <= next_state ;
end if ;
end process ;
process(cur_state, bit_counter, write_mode, cycle_counter, end_modulo, quarter, half, full, i2c_write, i2c_read, sda)
begin
next_state <= cur_state ;
case (cur_state) is
when IDLE =>
if i2c_write = '1' then
next_state <= I2C_START ;
elsif i2c_read = '1' then
next_state <= I2C_START ;
end if ;
when I2C_START =>
if full = '1' then
next_state <= TX_ADDR ;
end if ;
when TX_ADDR =>
if full = '1' and bit_counter = 7 then
next_state <= ACK_ADDR ;
end if ;
when ACK_ADDR =>
if full = '1' and is_acked = '1' and write_mode = '1' then
next_state <= TX_BYTE ;
elsif full = '1' and is_acked = '1' and write_mode = '0' then
next_state <= RX_BYTE ;
elsif full = '1' and is_acked = '0' then
next_state <= I2C_STOP ;
end if ;
when TX_BYTE =>
if full = '1' and bit_counter = 7 then
next_state <= ACK_BYTE ;
end if ;
when RX_BYTE =>
if full = '1' and bit_counter = 7 then
next_state <= ACK_BYTE ;
end if ;
when ACK_BYTE =>
if full = '1' and i2c_write = '1' and is_acked = '1' then --
next_state <= TX_BYTE ;
elsif full = '1' and i2c_read = '1' then
next_state <= RX_BYTE ;
elsif full = '1' then
next_state <= I2C_STOP ;
end if ;
when I2C_STOP =>
if full = '1' then
next_state <= IDLE ;
end if ;
when others =>
end case ;
end process ;
scl <= 'Z' when cur_state = I2C_START and cycle_counter < 2 else
'0' when cur_state = I2C_START and cycle_counter >= 2 else
'Z' when cur_state = IDLE else
'0' when cycle_counter < 2 else
'Z' ;
sda_unbuf <= '0' when cur_state = I2C_START else
'0' when cur_state = I2C_STOP and cycle_counter <= 2 else
'1' when cur_state = I2C_STOP and cycle_counter > 2 else -- need to make sure its enough ...
'1' when cur_state = IDLE else
'1' when cur_state = TX_ADDR and addr_buffer(7) = '1' else
'0' when cur_state = TX_ADDR and addr_buffer(7) = '0' else
'1' when cur_state = TX_BYTE and transmit_buffer(7) = '1' else
'0' when cur_state = TX_BYTE and transmit_buffer(7) = '0' else
'0' when cur_state = ACK_BYTE and write_mode = '0' and i2c_read = '1' else
'1' ;
process(clk, reset)
begin
if reset = '1' then
sda_shift_reg <= (others => '1');
elsif clk'event and clk = '1' then
sda_shift_reg(0) <= sda_unbuf ;
sda_shift_reg(sda_shift_reg'high downto 1) <= sda_shift_reg(sda_shift_reg'high-1 downto 0);
end if ;
end process ;
sda <= 'Z' when cur_state = ACK_BYTE and write_mode = '1' else
'0' when sda_shift_reg(sda_shift_reg'high) = '0' else
'Z' ;
process(clk, reset)
begin
if reset = '1' then
is_acked <= '0' ;
elsif clk'event and clk = '1' then
if (cur_state = ACK_BYTE or cur_state = ACK_ADDR ) and sda = '0' then
is_acked <= '1' ;
elsif cur_state /= ACK_BYTE then
is_acked <= '0' ;
end if ;
end if ;
end process ;
ack <= '1' when cur_state = ACK_BYTE and is_acked = '1' and full = '1' else
'1' when cur_state = ACK_BYTE and next_state = RX_BYTE else
'1' when cur_state = ACK_ADDR and is_acked = '1' and full = '1' else
'0' ;
nack <= '1' when cur_state = ACK_BYTE and write_mode = '1' and full='1' and is_acked = '0' else
'1' when cur_state = ACK_ADDR and full='1' and is_acked = '0' else
'0' ;
busy <= '0' when cur_state = IDLE else
'1' ;
new_data <= '1' when cur_state = ACK_BYTE and write_mode = '0' else
'0' ;
process(clk, reset)
begin
if reset = '1' then
transmit_buffer <= (others => '0') ;
receive_buffer <= (others => '0') ;
addr_buffer <= (others => '0') ;
bit_counter <= (others => '0') ;
elsif clk'event and clk = '1' then
if (cur_state = IDLE and i2c_write = '1') or i2c_read = '1' then
addr_buffer <= slave_addr & i2c_read ;
elsif cur_state = TX_ADDR and full = '1' then
addr_buffer(7 downto 1) <= addr_buffer(6 downto 0);
end if;
if cur_state = IDLE and i2c_write = '1' then
transmit_buffer <= data_in ;
elsif cur_state = TX_BYTE and full = '1' then
transmit_buffer(7 downto 1) <= transmit_buffer(6 downto 0);
transmit_buffer(0) <= '0' ;
elsif cur_state = ACK_BYTE and i2c_write = '1' and is_acked = '1' then
transmit_buffer <= data_in;
end if;
if cur_state = IDLE then
receive_buffer <= (others => '0') ;
elsif cur_state = RX_BYTE and half = '1' then
receive_buffer(7 downto 1) <= receive_buffer(6 downto 0);
receive_buffer(0) <= sda ;
end if;
if cur_state = IDLE or cur_state = ACK_BYTE or cur_state = ACK_ADDR then
bit_counter <= (others => '0') ;
elsif (cur_state = TX_ADDR or cur_state = TX_BYTE) and full = '1' then
bit_counter <= bit_counter + 1 ;
end if;
end if ;
end process ;
process(clk, reset)
begin
if reset = '1' then
write_mode <= '0' ;
elsif clk'event and clk = '1' then
if cur_state = IDLE and i2c_write = '1' then
write_mode <= '1' ;
elsif cur_state = I2C_STOP then
write_mode <= '0' ;
end if;
end if ;
end process ;
end Behavioral;
|
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from fp_mul
-- VHDL created on Thu Feb 15 13:10:22 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_mul is
port (
a : in std_logic_vector(31 downto 0); -- float32_m23
b : in std_logic_vector(31 downto 0); -- float32_m23
q : out std_logic_vector(31 downto 0); -- float32_m23
clk : in std_logic;
areset : in std_logic
);
end fp_mul;
architecture normal of fp_mul is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal expX_uid6_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal expY_uid7_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal signX_uid8_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal signY_uid9_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal cstAllOWE_uid10_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cstZeroWF_uid11_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal cstAllZWE_uid12_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal frac_x_uid14_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_x_uid15_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_x_uid15_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid16_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid16_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid17_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid17_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid18_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_x_uid19_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_x_uid20_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid21_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid22_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_x_uid23_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal frac_y_uid28_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excZ_y_uid29_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_y_uid29_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid30_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid30_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid31_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid31_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid32_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_y_uid33_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_y_uid34_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid35_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid36_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_y_uid37_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal ofracX_uid40_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal ofracY_uid43_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal expSum_uid44_fpMulTest_a : STD_LOGIC_VECTOR (8 downto 0);
signal expSum_uid44_fpMulTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal expSum_uid44_fpMulTest_o : STD_LOGIC_VECTOR (8 downto 0);
signal expSum_uid44_fpMulTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal biasInc_uid45_fpMulTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal expSumMBias_uid46_fpMulTest_a : STD_LOGIC_VECTOR (11 downto 0);
signal expSumMBias_uid46_fpMulTest_b : STD_LOGIC_VECTOR (11 downto 0);
signal expSumMBias_uid46_fpMulTest_o : STD_LOGIC_VECTOR (11 downto 0);
signal expSumMBias_uid46_fpMulTest_q : STD_LOGIC_VECTOR (10 downto 0);
signal signR_uid48_fpMulTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal signR_uid48_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal normalizeBit_uid49_fpMulTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPostNormHigh_uid51_fpMulTest_in : STD_LOGIC_VECTOR (25 downto 0);
signal fracRPostNormHigh_uid51_fpMulTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPostNormLow_uid52_fpMulTest_in : STD_LOGIC_VECTOR (24 downto 0);
signal fracRPostNormLow_uid52_fpMulTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPostNorm_uid53_fpMulTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal fracRPostNorm_uid53_fpMulTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal expFracPreRound_uid55_fpMulTest_q : STD_LOGIC_VECTOR (34 downto 0);
signal roundBitAndNormalizationOp_uid57_fpMulTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal expFracRPostRounding_uid58_fpMulTest_a : STD_LOGIC_VECTOR (36 downto 0);
signal expFracRPostRounding_uid58_fpMulTest_b : STD_LOGIC_VECTOR (36 downto 0);
signal expFracRPostRounding_uid58_fpMulTest_o : STD_LOGIC_VECTOR (36 downto 0);
signal expFracRPostRounding_uid58_fpMulTest_q : STD_LOGIC_VECTOR (35 downto 0);
signal fracRPreExc_uid59_fpMulTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPreExc_uid59_fpMulTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal expRPreExcExt_uid60_fpMulTest_b : STD_LOGIC_VECTOR (11 downto 0);
signal expRPreExc_uid61_fpMulTest_in : STD_LOGIC_VECTOR (7 downto 0);
signal expRPreExc_uid61_fpMulTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal expUdf_uid62_fpMulTest_a : STD_LOGIC_VECTOR (13 downto 0);
signal expUdf_uid62_fpMulTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal expUdf_uid62_fpMulTest_o : STD_LOGIC_VECTOR (13 downto 0);
signal expUdf_uid62_fpMulTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal expOvf_uid64_fpMulTest_a : STD_LOGIC_VECTOR (13 downto 0);
signal expOvf_uid64_fpMulTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal expOvf_uid64_fpMulTest_o : STD_LOGIC_VECTOR (13 downto 0);
signal expOvf_uid64_fpMulTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYZ_uid65_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYR_uid66_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excYZAndExcXR_uid67_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excZC3_uid68_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRZero_uid69_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXIAndExcYI_uid70_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXRAndExcYI_uid71_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excYRAndExcXI_uid72_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal ExcROvfAndInReg_uid73_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRInf_uid74_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excYZAndExcXI_uid75_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXZAndExcYI_uid76_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal ZeroTimesInf_uid77_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN_uid78_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal concExc_uid79_fpMulTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal excREnc_uid80_fpMulTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal oneFracRPostExc2_uid81_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal fracRPostExc_uid84_fpMulTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPostExc_uid84_fpMulTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPostExc_uid89_fpMulTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal expRPostExc_uid89_fpMulTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal invExcRNaN_uid90_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signRPostExc_uid91_fpMulTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal R_uid92_fpMulTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal topRangeX_uid102_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal topRangeY_uid103_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal aboveLeftX_uid108_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal aboveLeftY_bottomExtension_uid109_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_mergedSignalTM_uid111_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (5 downto 0);
signal rightBottomX_mergedSignalTM_uid115_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomY_uid117_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomX_uid121_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (14 downto 0);
signal rightBottomX_uid121_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal rightBottomY_uid122_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal rightBottomY_uid122_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal aboveLeftX_uid123_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftX_uid123_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal aboveLeftY_uid124_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (14 downto 0);
signal aboveLeftY_uid124_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal n0_uid130_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n1_uid131_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n0_uid132_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n1_uid133_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n0_uid138_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n1_uid139_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n0_uid140_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n1_uid141_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n0_uid146_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n1_uid147_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n0_uid148_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n1_uid149_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid160_prod_uid47_fpMulTest_a0 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid160_prod_uid47_fpMulTest_b0 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid160_prod_uid47_fpMulTest_s1 : STD_LOGIC_VECTOR (35 downto 0);
signal sm0_uid160_prod_uid47_fpMulTest_reset : std_logic;
signal sm0_uid160_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (35 downto 0);
signal sm0_uid161_prod_uid47_fpMulTest_a0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm0_uid161_prod_uid47_fpMulTest_b0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm0_uid161_prod_uid47_fpMulTest_s1 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid161_prod_uid47_fpMulTest_reset : std_logic;
signal sm0_uid161_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (17 downto 0);
signal sm1_uid162_prod_uid47_fpMulTest_a0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm1_uid162_prod_uid47_fpMulTest_b0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm1_uid162_prod_uid47_fpMulTest_s1 : STD_LOGIC_VECTOR (17 downto 0);
signal sm1_uid162_prod_uid47_fpMulTest_reset : std_logic;
signal sm1_uid162_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid163_prod_uid47_fpMulTest_a0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid163_prod_uid47_fpMulTest_b0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid163_prod_uid47_fpMulTest_s1 : STD_LOGIC_VECTOR (3 downto 0);
signal sm0_uid163_prod_uid47_fpMulTest_reset : std_logic;
signal sm0_uid163_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal sm1_uid164_prod_uid47_fpMulTest_a0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm1_uid164_prod_uid47_fpMulTest_b0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm1_uid164_prod_uid47_fpMulTest_s1 : STD_LOGIC_VECTOR (3 downto 0);
signal sm1_uid164_prod_uid47_fpMulTest_reset : std_logic;
signal sm1_uid164_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal lev1_a0_uid165_prod_uid47_fpMulTest_a : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid165_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid165_prod_uid47_fpMulTest_o : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid165_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a1high_uid168_prod_uid47_fpMulTest_a : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid168_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid168_prod_uid47_fpMulTest_o : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid168_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1_uid169_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (18 downto 0);
signal lev2_a0_uid170_prod_uid47_fpMulTest_a : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid170_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid170_prod_uid47_fpMulTest_o : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid170_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (37 downto 0);
signal lev3_a0high_uid173_prod_uid47_fpMulTest_a : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid173_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid173_prod_uid47_fpMulTest_o : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid173_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0_uid174_prod_uid47_fpMulTest_q : STD_LOGIC_VECTOR (38 downto 0);
signal osig_uid175_prod_uid47_fpMulTest_in : STD_LOGIC_VECTOR (35 downto 0);
signal osig_uid175_prod_uid47_fpMulTest_b : STD_LOGIC_VECTOR (26 downto 0);
signal lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_b : STD_LOGIC_VECTOR (4 downto 0);
signal lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_c : STD_LOGIC_VECTOR (12 downto 0);
signal lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_b : STD_LOGIC_VECTOR (4 downto 0);
signal lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_c : STD_LOGIC_VECTOR (32 downto 0);
signal redist0_signR_uid48_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist1_expSum_uid44_fpMulTest_q_2_q : STD_LOGIC_VECTOR (8 downto 0);
signal redist2_fracXIsZero_uid31_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist3_expXIsMax_uid30_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist4_excZ_y_uid29_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist5_fracXIsZero_uid17_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist6_expXIsMax_uid16_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist7_excZ_x_uid15_fpMulTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
begin
-- frac_x_uid14_fpMulTest(BITSELECT,13)@0
frac_x_uid14_fpMulTest_b <= a(22 downto 0);
-- cstZeroWF_uid11_fpMulTest(CONSTANT,10)
cstZeroWF_uid11_fpMulTest_q <= "00000000000000000000000";
-- fracXIsZero_uid17_fpMulTest(LOGICAL,16)@0 + 1
fracXIsZero_uid17_fpMulTest_qi <= "1" WHEN cstZeroWF_uid11_fpMulTest_q = frac_x_uid14_fpMulTest_b ELSE "0";
fracXIsZero_uid17_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_qi, xout => fracXIsZero_uid17_fpMulTest_q, clk => clk, aclr => areset );
-- redist5_fracXIsZero_uid17_fpMulTest_q_2(DELAY,183)
redist5_fracXIsZero_uid17_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid17_fpMulTest_q, xout => redist5_fracXIsZero_uid17_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- cstAllOWE_uid10_fpMulTest(CONSTANT,9)
cstAllOWE_uid10_fpMulTest_q <= "11111111";
-- expX_uid6_fpMulTest(BITSELECT,5)@0
expX_uid6_fpMulTest_b <= a(30 downto 23);
-- expXIsMax_uid16_fpMulTest(LOGICAL,15)@0 + 1
expXIsMax_uid16_fpMulTest_qi <= "1" WHEN expX_uid6_fpMulTest_b = cstAllOWE_uid10_fpMulTest_q ELSE "0";
expXIsMax_uid16_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid16_fpMulTest_qi, xout => expXIsMax_uid16_fpMulTest_q, clk => clk, aclr => areset );
-- redist6_expXIsMax_uid16_fpMulTest_q_2(DELAY,184)
redist6_expXIsMax_uid16_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid16_fpMulTest_q, xout => redist6_expXIsMax_uid16_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- excI_x_uid19_fpMulTest(LOGICAL,18)@2
excI_x_uid19_fpMulTest_q <= redist6_expXIsMax_uid16_fpMulTest_q_2_q and redist5_fracXIsZero_uid17_fpMulTest_q_2_q;
-- cstAllZWE_uid12_fpMulTest(CONSTANT,11)
cstAllZWE_uid12_fpMulTest_q <= "00000000";
-- expY_uid7_fpMulTest(BITSELECT,6)@0
expY_uid7_fpMulTest_b <= b(30 downto 23);
-- excZ_y_uid29_fpMulTest(LOGICAL,28)@0 + 1
excZ_y_uid29_fpMulTest_qi <= "1" WHEN expY_uid7_fpMulTest_b = cstAllZWE_uid12_fpMulTest_q ELSE "0";
excZ_y_uid29_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_y_uid29_fpMulTest_qi, xout => excZ_y_uid29_fpMulTest_q, clk => clk, aclr => areset );
-- redist4_excZ_y_uid29_fpMulTest_q_2(DELAY,182)
redist4_excZ_y_uid29_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_y_uid29_fpMulTest_q, xout => redist4_excZ_y_uid29_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- excYZAndExcXI_uid75_fpMulTest(LOGICAL,74)@2
excYZAndExcXI_uid75_fpMulTest_q <= redist4_excZ_y_uid29_fpMulTest_q_2_q and excI_x_uid19_fpMulTest_q;
-- frac_y_uid28_fpMulTest(BITSELECT,27)@0
frac_y_uid28_fpMulTest_b <= b(22 downto 0);
-- fracXIsZero_uid31_fpMulTest(LOGICAL,30)@0 + 1
fracXIsZero_uid31_fpMulTest_qi <= "1" WHEN cstZeroWF_uid11_fpMulTest_q = frac_y_uid28_fpMulTest_b ELSE "0";
fracXIsZero_uid31_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_qi, xout => fracXIsZero_uid31_fpMulTest_q, clk => clk, aclr => areset );
-- redist2_fracXIsZero_uid31_fpMulTest_q_2(DELAY,180)
redist2_fracXIsZero_uid31_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid31_fpMulTest_q, xout => redist2_fracXIsZero_uid31_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- expXIsMax_uid30_fpMulTest(LOGICAL,29)@0 + 1
expXIsMax_uid30_fpMulTest_qi <= "1" WHEN expY_uid7_fpMulTest_b = cstAllOWE_uid10_fpMulTest_q ELSE "0";
expXIsMax_uid30_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid30_fpMulTest_qi, xout => expXIsMax_uid30_fpMulTest_q, clk => clk, aclr => areset );
-- redist3_expXIsMax_uid30_fpMulTest_q_2(DELAY,181)
redist3_expXIsMax_uid30_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid30_fpMulTest_q, xout => redist3_expXIsMax_uid30_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- excI_y_uid33_fpMulTest(LOGICAL,32)@2
excI_y_uid33_fpMulTest_q <= redist3_expXIsMax_uid30_fpMulTest_q_2_q and redist2_fracXIsZero_uid31_fpMulTest_q_2_q;
-- excZ_x_uid15_fpMulTest(LOGICAL,14)@0 + 1
excZ_x_uid15_fpMulTest_qi <= "1" WHEN expX_uid6_fpMulTest_b = cstAllZWE_uid12_fpMulTest_q ELSE "0";
excZ_x_uid15_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_x_uid15_fpMulTest_qi, xout => excZ_x_uid15_fpMulTest_q, clk => clk, aclr => areset );
-- redist7_excZ_x_uid15_fpMulTest_q_2(DELAY,185)
redist7_excZ_x_uid15_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_x_uid15_fpMulTest_q, xout => redist7_excZ_x_uid15_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- excXZAndExcYI_uid76_fpMulTest(LOGICAL,75)@2
excXZAndExcYI_uid76_fpMulTest_q <= redist7_excZ_x_uid15_fpMulTest_q_2_q and excI_y_uid33_fpMulTest_q;
-- ZeroTimesInf_uid77_fpMulTest(LOGICAL,76)@2
ZeroTimesInf_uid77_fpMulTest_q <= excXZAndExcYI_uid76_fpMulTest_q or excYZAndExcXI_uid75_fpMulTest_q;
-- fracXIsNotZero_uid32_fpMulTest(LOGICAL,31)@2
fracXIsNotZero_uid32_fpMulTest_q <= not (redist2_fracXIsZero_uid31_fpMulTest_q_2_q);
-- excN_y_uid34_fpMulTest(LOGICAL,33)@2
excN_y_uid34_fpMulTest_q <= redist3_expXIsMax_uid30_fpMulTest_q_2_q and fracXIsNotZero_uid32_fpMulTest_q;
-- fracXIsNotZero_uid18_fpMulTest(LOGICAL,17)@2
fracXIsNotZero_uid18_fpMulTest_q <= not (redist5_fracXIsZero_uid17_fpMulTest_q_2_q);
-- excN_x_uid20_fpMulTest(LOGICAL,19)@2
excN_x_uid20_fpMulTest_q <= redist6_expXIsMax_uid16_fpMulTest_q_2_q and fracXIsNotZero_uid18_fpMulTest_q;
-- excRNaN_uid78_fpMulTest(LOGICAL,77)@2
excRNaN_uid78_fpMulTest_q <= excN_x_uid20_fpMulTest_q or excN_y_uid34_fpMulTest_q or ZeroTimesInf_uid77_fpMulTest_q;
-- invExcRNaN_uid90_fpMulTest(LOGICAL,89)@2
invExcRNaN_uid90_fpMulTest_q <= not (excRNaN_uid78_fpMulTest_q);
-- signY_uid9_fpMulTest(BITSELECT,8)@0
signY_uid9_fpMulTest_b <= STD_LOGIC_VECTOR(b(31 downto 31));
-- signX_uid8_fpMulTest(BITSELECT,7)@0
signX_uid8_fpMulTest_b <= STD_LOGIC_VECTOR(a(31 downto 31));
-- signR_uid48_fpMulTest(LOGICAL,47)@0 + 1
signR_uid48_fpMulTest_qi <= signX_uid8_fpMulTest_b xor signY_uid9_fpMulTest_b;
signR_uid48_fpMulTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => signR_uid48_fpMulTest_qi, xout => signR_uid48_fpMulTest_q, clk => clk, aclr => areset );
-- redist0_signR_uid48_fpMulTest_q_2(DELAY,178)
redist0_signR_uid48_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => signR_uid48_fpMulTest_q, xout => redist0_signR_uid48_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- signRPostExc_uid91_fpMulTest(LOGICAL,90)@2
signRPostExc_uid91_fpMulTest_q <= redist0_signR_uid48_fpMulTest_q_2_q and invExcRNaN_uid90_fpMulTest_q;
-- GND(CONSTANT,0)
GND_q <= "0";
-- ofracY_uid43_fpMulTest(BITJOIN,42)@0
ofracY_uid43_fpMulTest_q <= VCC_q & frac_y_uid28_fpMulTest_b;
-- aboveLeftY_uid124_prod_uid47_fpMulTest(BITSELECT,123)@0
aboveLeftY_uid124_prod_uid47_fpMulTest_in <= ofracY_uid43_fpMulTest_q(14 downto 0);
aboveLeftY_uid124_prod_uid47_fpMulTest_b <= aboveLeftY_uid124_prod_uid47_fpMulTest_in(14 downto 10);
-- n1_uid133_prod_uid47_fpMulTest(BITSELECT,132)@0
n1_uid133_prod_uid47_fpMulTest_b <= aboveLeftY_uid124_prod_uid47_fpMulTest_b(4 downto 1);
-- n1_uid141_prod_uid47_fpMulTest(BITSELECT,140)@0
n1_uid141_prod_uid47_fpMulTest_b <= n1_uid133_prod_uid47_fpMulTest_b(3 downto 1);
-- n1_uid149_prod_uid47_fpMulTest(BITSELECT,148)@0
n1_uid149_prod_uid47_fpMulTest_b <= n1_uid141_prod_uid47_fpMulTest_b(2 downto 1);
-- ofracX_uid40_fpMulTest(BITJOIN,39)@0
ofracX_uid40_fpMulTest_q <= VCC_q & frac_x_uid14_fpMulTest_b;
-- aboveLeftX_uid123_prod_uid47_fpMulTest(BITSELECT,122)@0
aboveLeftX_uid123_prod_uid47_fpMulTest_in <= ofracX_uid40_fpMulTest_q(5 downto 0);
aboveLeftX_uid123_prod_uid47_fpMulTest_b <= aboveLeftX_uid123_prod_uid47_fpMulTest_in(5 downto 1);
-- n0_uid132_prod_uid47_fpMulTest(BITSELECT,131)@0
n0_uid132_prod_uid47_fpMulTest_b <= aboveLeftX_uid123_prod_uid47_fpMulTest_b(4 downto 1);
-- n0_uid140_prod_uid47_fpMulTest(BITSELECT,139)@0
n0_uid140_prod_uid47_fpMulTest_b <= n0_uid132_prod_uid47_fpMulTest_b(3 downto 1);
-- n0_uid148_prod_uid47_fpMulTest(BITSELECT,147)@0
n0_uid148_prod_uid47_fpMulTest_b <= n0_uid140_prod_uid47_fpMulTest_b(2 downto 1);
-- sm1_uid164_prod_uid47_fpMulTest(MULT,163)@0 + 2
sm1_uid164_prod_uid47_fpMulTest_a0 <= n0_uid148_prod_uid47_fpMulTest_b;
sm1_uid164_prod_uid47_fpMulTest_b0 <= n1_uid149_prod_uid47_fpMulTest_b;
sm1_uid164_prod_uid47_fpMulTest_reset <= areset;
sm1_uid164_prod_uid47_fpMulTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 2,
lpm_widthb => 2,
lpm_widthp => 4,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm1_uid164_prod_uid47_fpMulTest_a0,
datab => sm1_uid164_prod_uid47_fpMulTest_b0,
clken => VCC_q(0),
aclr => sm1_uid164_prod_uid47_fpMulTest_reset,
clock => clk,
result => sm1_uid164_prod_uid47_fpMulTest_s1
);
sm1_uid164_prod_uid47_fpMulTest_q <= sm1_uid164_prod_uid47_fpMulTest_s1;
-- lev3_a0high_uid173_prod_uid47_fpMulTest(ADD,172)@2
lev3_a0high_uid173_prod_uid47_fpMulTest_a <= STD_LOGIC_VECTOR("0" & lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_c);
lev3_a0high_uid173_prod_uid47_fpMulTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000" & sm1_uid164_prod_uid47_fpMulTest_q);
lev3_a0high_uid173_prod_uid47_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev3_a0high_uid173_prod_uid47_fpMulTest_a) + UNSIGNED(lev3_a0high_uid173_prod_uid47_fpMulTest_b));
lev3_a0high_uid173_prod_uid47_fpMulTest_q <= lev3_a0high_uid173_prod_uid47_fpMulTest_o(33 downto 0);
-- rightBottomY_uid122_prod_uid47_fpMulTest(BITSELECT,121)@0
rightBottomY_uid122_prod_uid47_fpMulTest_in <= ofracY_uid43_fpMulTest_q(5 downto 0);
rightBottomY_uid122_prod_uid47_fpMulTest_b <= rightBottomY_uid122_prod_uid47_fpMulTest_in(5 downto 1);
-- n1_uid131_prod_uid47_fpMulTest(BITSELECT,130)@0
n1_uid131_prod_uid47_fpMulTest_b <= rightBottomY_uid122_prod_uid47_fpMulTest_b(4 downto 1);
-- n1_uid139_prod_uid47_fpMulTest(BITSELECT,138)@0
n1_uid139_prod_uid47_fpMulTest_b <= n1_uid131_prod_uid47_fpMulTest_b(3 downto 1);
-- n1_uid147_prod_uid47_fpMulTest(BITSELECT,146)@0
n1_uid147_prod_uid47_fpMulTest_b <= n1_uid139_prod_uid47_fpMulTest_b(2 downto 1);
-- rightBottomX_uid121_prod_uid47_fpMulTest(BITSELECT,120)@0
rightBottomX_uid121_prod_uid47_fpMulTest_in <= ofracX_uid40_fpMulTest_q(14 downto 0);
rightBottomX_uid121_prod_uid47_fpMulTest_b <= rightBottomX_uid121_prod_uid47_fpMulTest_in(14 downto 10);
-- n0_uid130_prod_uid47_fpMulTest(BITSELECT,129)@0
n0_uid130_prod_uid47_fpMulTest_b <= rightBottomX_uid121_prod_uid47_fpMulTest_b(4 downto 1);
-- n0_uid138_prod_uid47_fpMulTest(BITSELECT,137)@0
n0_uid138_prod_uid47_fpMulTest_b <= n0_uid130_prod_uid47_fpMulTest_b(3 downto 1);
-- n0_uid146_prod_uid47_fpMulTest(BITSELECT,145)@0
n0_uid146_prod_uid47_fpMulTest_b <= n0_uid138_prod_uid47_fpMulTest_b(2 downto 1);
-- sm0_uid163_prod_uid47_fpMulTest(MULT,162)@0 + 2
sm0_uid163_prod_uid47_fpMulTest_a0 <= n0_uid146_prod_uid47_fpMulTest_b;
sm0_uid163_prod_uid47_fpMulTest_b0 <= n1_uid147_prod_uid47_fpMulTest_b;
sm0_uid163_prod_uid47_fpMulTest_reset <= areset;
sm0_uid163_prod_uid47_fpMulTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 2,
lpm_widthb => 2,
lpm_widthp => 4,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid163_prod_uid47_fpMulTest_a0,
datab => sm0_uid163_prod_uid47_fpMulTest_b0,
clken => VCC_q(0),
aclr => sm0_uid163_prod_uid47_fpMulTest_reset,
clock => clk,
result => sm0_uid163_prod_uid47_fpMulTest_s1
);
sm0_uid163_prod_uid47_fpMulTest_q <= sm0_uid163_prod_uid47_fpMulTest_s1;
-- lev1_a1high_uid168_prod_uid47_fpMulTest(ADD,167)@2
lev1_a1high_uid168_prod_uid47_fpMulTest_a <= STD_LOGIC_VECTOR("0" & lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_c);
lev1_a1high_uid168_prod_uid47_fpMulTest_b <= STD_LOGIC_VECTOR("0000000000" & sm0_uid163_prod_uid47_fpMulTest_q);
lev1_a1high_uid168_prod_uid47_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a1high_uid168_prod_uid47_fpMulTest_a) + UNSIGNED(lev1_a1high_uid168_prod_uid47_fpMulTest_b));
lev1_a1high_uid168_prod_uid47_fpMulTest_q <= lev1_a1high_uid168_prod_uid47_fpMulTest_o(13 downto 0);
-- rightBottomY_uid117_prod_uid47_fpMulTest(BITSELECT,116)@0
rightBottomY_uid117_prod_uid47_fpMulTest_b <= ofracY_uid43_fpMulTest_q(23 downto 15);
-- rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest(BITSELECT,113)@0
rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_in <= ofracX_uid40_fpMulTest_q(5 downto 0);
rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_b <= rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_in(5 downto 0);
-- aboveLeftY_bottomExtension_uid109_prod_uid47_fpMulTest(CONSTANT,108)
aboveLeftY_bottomExtension_uid109_prod_uid47_fpMulTest_q <= "000";
-- rightBottomX_mergedSignalTM_uid115_prod_uid47_fpMulTest(BITJOIN,114)@0
rightBottomX_mergedSignalTM_uid115_prod_uid47_fpMulTest_q <= rightBottomX_bottomRange_uid114_prod_uid47_fpMulTest_b & aboveLeftY_bottomExtension_uid109_prod_uid47_fpMulTest_q;
-- sm1_uid162_prod_uid47_fpMulTest(MULT,161)@0 + 2
sm1_uid162_prod_uid47_fpMulTest_a0 <= rightBottomX_mergedSignalTM_uid115_prod_uid47_fpMulTest_q;
sm1_uid162_prod_uid47_fpMulTest_b0 <= rightBottomY_uid117_prod_uid47_fpMulTest_b;
sm1_uid162_prod_uid47_fpMulTest_reset <= areset;
sm1_uid162_prod_uid47_fpMulTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 9,
lpm_widthb => 9,
lpm_widthp => 18,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm1_uid162_prod_uid47_fpMulTest_a0,
datab => sm1_uid162_prod_uid47_fpMulTest_b0,
clken => VCC_q(0),
aclr => sm1_uid162_prod_uid47_fpMulTest_reset,
clock => clk,
result => sm1_uid162_prod_uid47_fpMulTest_s1
);
sm1_uid162_prod_uid47_fpMulTest_q <= sm1_uid162_prod_uid47_fpMulTest_s1;
-- lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select(BITSELECT,176)@2
lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_b <= sm1_uid162_prod_uid47_fpMulTest_q(4 downto 0);
lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_c <= sm1_uid162_prod_uid47_fpMulTest_q(17 downto 5);
-- lev1_a1_uid169_prod_uid47_fpMulTest(BITJOIN,168)@2
lev1_a1_uid169_prod_uid47_fpMulTest_q <= lev1_a1high_uid168_prod_uid47_fpMulTest_q & lowRangeA_uid166_prod_uid47_fpMulTest_merged_bit_select_b;
-- aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest(BITSELECT,109)@0
aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_in <= ofracY_uid43_fpMulTest_q(5 downto 0);
aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_b <= aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_in(5 downto 0);
-- aboveLeftY_mergedSignalTM_uid111_prod_uid47_fpMulTest(BITJOIN,110)@0
aboveLeftY_mergedSignalTM_uid111_prod_uid47_fpMulTest_q <= aboveLeftY_bottomRange_uid110_prod_uid47_fpMulTest_b & aboveLeftY_bottomExtension_uid109_prod_uid47_fpMulTest_q;
-- aboveLeftX_uid108_prod_uid47_fpMulTest(BITSELECT,107)@0
aboveLeftX_uid108_prod_uid47_fpMulTest_b <= ofracX_uid40_fpMulTest_q(23 downto 15);
-- sm0_uid161_prod_uid47_fpMulTest(MULT,160)@0 + 2
sm0_uid161_prod_uid47_fpMulTest_a0 <= aboveLeftX_uid108_prod_uid47_fpMulTest_b;
sm0_uid161_prod_uid47_fpMulTest_b0 <= aboveLeftY_mergedSignalTM_uid111_prod_uid47_fpMulTest_q;
sm0_uid161_prod_uid47_fpMulTest_reset <= areset;
sm0_uid161_prod_uid47_fpMulTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 9,
lpm_widthb => 9,
lpm_widthp => 18,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid161_prod_uid47_fpMulTest_a0,
datab => sm0_uid161_prod_uid47_fpMulTest_b0,
clken => VCC_q(0),
aclr => sm0_uid161_prod_uid47_fpMulTest_reset,
clock => clk,
result => sm0_uid161_prod_uid47_fpMulTest_s1
);
sm0_uid161_prod_uid47_fpMulTest_q <= sm0_uid161_prod_uid47_fpMulTest_s1;
-- topRangeY_uid103_prod_uid47_fpMulTest(BITSELECT,102)@0
topRangeY_uid103_prod_uid47_fpMulTest_b <= ofracY_uid43_fpMulTest_q(23 downto 6);
-- topRangeX_uid102_prod_uid47_fpMulTest(BITSELECT,101)@0
topRangeX_uid102_prod_uid47_fpMulTest_b <= ofracX_uid40_fpMulTest_q(23 downto 6);
-- sm0_uid160_prod_uid47_fpMulTest(MULT,159)@0 + 2
sm0_uid160_prod_uid47_fpMulTest_a0 <= topRangeX_uid102_prod_uid47_fpMulTest_b;
sm0_uid160_prod_uid47_fpMulTest_b0 <= topRangeY_uid103_prod_uid47_fpMulTest_b;
sm0_uid160_prod_uid47_fpMulTest_reset <= areset;
sm0_uid160_prod_uid47_fpMulTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 18,
lpm_widthb => 18,
lpm_widthp => 36,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid160_prod_uid47_fpMulTest_a0,
datab => sm0_uid160_prod_uid47_fpMulTest_b0,
clken => VCC_q(0),
aclr => sm0_uid160_prod_uid47_fpMulTest_reset,
clock => clk,
result => sm0_uid160_prod_uid47_fpMulTest_s1
);
sm0_uid160_prod_uid47_fpMulTest_q <= sm0_uid160_prod_uid47_fpMulTest_s1;
-- lev1_a0_uid165_prod_uid47_fpMulTest(ADD,164)@2
lev1_a0_uid165_prod_uid47_fpMulTest_a <= STD_LOGIC_VECTOR("0" & sm0_uid160_prod_uid47_fpMulTest_q);
lev1_a0_uid165_prod_uid47_fpMulTest_b <= STD_LOGIC_VECTOR("0000000000000000000" & sm0_uid161_prod_uid47_fpMulTest_q);
lev1_a0_uid165_prod_uid47_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a0_uid165_prod_uid47_fpMulTest_a) + UNSIGNED(lev1_a0_uid165_prod_uid47_fpMulTest_b));
lev1_a0_uid165_prod_uid47_fpMulTest_q <= lev1_a0_uid165_prod_uid47_fpMulTest_o(36 downto 0);
-- lev2_a0_uid170_prod_uid47_fpMulTest(ADD,169)@2
lev2_a0_uid170_prod_uid47_fpMulTest_a <= STD_LOGIC_VECTOR("0" & lev1_a0_uid165_prod_uid47_fpMulTest_q);
lev2_a0_uid170_prod_uid47_fpMulTest_b <= STD_LOGIC_VECTOR("0000000000000000000" & lev1_a1_uid169_prod_uid47_fpMulTest_q);
lev2_a0_uid170_prod_uid47_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev2_a0_uid170_prod_uid47_fpMulTest_a) + UNSIGNED(lev2_a0_uid170_prod_uid47_fpMulTest_b));
lev2_a0_uid170_prod_uid47_fpMulTest_q <= lev2_a0_uid170_prod_uid47_fpMulTest_o(37 downto 0);
-- lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select(BITSELECT,177)@2
lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_b <= lev2_a0_uid170_prod_uid47_fpMulTest_q(4 downto 0);
lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_c <= lev2_a0_uid170_prod_uid47_fpMulTest_q(37 downto 5);
-- lev3_a0_uid174_prod_uid47_fpMulTest(BITJOIN,173)@2
lev3_a0_uid174_prod_uid47_fpMulTest_q <= lev3_a0high_uid173_prod_uid47_fpMulTest_q & lowRangeA_uid171_prod_uid47_fpMulTest_merged_bit_select_b;
-- osig_uid175_prod_uid47_fpMulTest(BITSELECT,174)@2
osig_uid175_prod_uid47_fpMulTest_in <= lev3_a0_uid174_prod_uid47_fpMulTest_q(35 downto 0);
osig_uid175_prod_uid47_fpMulTest_b <= osig_uid175_prod_uid47_fpMulTest_in(35 downto 9);
-- normalizeBit_uid49_fpMulTest(BITSELECT,48)@2
normalizeBit_uid49_fpMulTest_b <= STD_LOGIC_VECTOR(osig_uid175_prod_uid47_fpMulTest_b(26 downto 26));
-- roundBitAndNormalizationOp_uid57_fpMulTest(BITJOIN,56)@2
roundBitAndNormalizationOp_uid57_fpMulTest_q <= GND_q & normalizeBit_uid49_fpMulTest_b & cstZeroWF_uid11_fpMulTest_q & VCC_q;
-- biasInc_uid45_fpMulTest(CONSTANT,44)
biasInc_uid45_fpMulTest_q <= "0001111111";
-- expSum_uid44_fpMulTest(ADD,43)@0 + 1
expSum_uid44_fpMulTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpMulTest_b);
expSum_uid44_fpMulTest_b <= STD_LOGIC_VECTOR("0" & expY_uid7_fpMulTest_b);
expSum_uid44_fpMulTest_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid44_fpMulTest_o <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
expSum_uid44_fpMulTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid44_fpMulTest_a) + UNSIGNED(expSum_uid44_fpMulTest_b));
END IF;
END PROCESS;
expSum_uid44_fpMulTest_q <= expSum_uid44_fpMulTest_o(8 downto 0);
-- redist1_expSum_uid44_fpMulTest_q_2(DELAY,179)
redist1_expSum_uid44_fpMulTest_q_2 : dspba_delay
GENERIC MAP ( width => 9, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expSum_uid44_fpMulTest_q, xout => redist1_expSum_uid44_fpMulTest_q_2_q, clk => clk, aclr => areset );
-- expSumMBias_uid46_fpMulTest(SUB,45)@2
expSumMBias_uid46_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "00" & redist1_expSum_uid44_fpMulTest_q_2_q));
expSumMBias_uid46_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid45_fpMulTest_q(9)) & biasInc_uid45_fpMulTest_q));
expSumMBias_uid46_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid46_fpMulTest_a) - SIGNED(expSumMBias_uid46_fpMulTest_b));
expSumMBias_uid46_fpMulTest_q <= expSumMBias_uid46_fpMulTest_o(10 downto 0);
-- fracRPostNormHigh_uid51_fpMulTest(BITSELECT,50)@2
fracRPostNormHigh_uid51_fpMulTest_in <= osig_uid175_prod_uid47_fpMulTest_b(25 downto 0);
fracRPostNormHigh_uid51_fpMulTest_b <= fracRPostNormHigh_uid51_fpMulTest_in(25 downto 2);
-- fracRPostNormLow_uid52_fpMulTest(BITSELECT,51)@2
fracRPostNormLow_uid52_fpMulTest_in <= osig_uid175_prod_uid47_fpMulTest_b(24 downto 0);
fracRPostNormLow_uid52_fpMulTest_b <= fracRPostNormLow_uid52_fpMulTest_in(24 downto 1);
-- fracRPostNorm_uid53_fpMulTest(MUX,52)@2
fracRPostNorm_uid53_fpMulTest_s <= normalizeBit_uid49_fpMulTest_b;
fracRPostNorm_uid53_fpMulTest_combproc: PROCESS (fracRPostNorm_uid53_fpMulTest_s, fracRPostNormLow_uid52_fpMulTest_b, fracRPostNormHigh_uid51_fpMulTest_b)
BEGIN
CASE (fracRPostNorm_uid53_fpMulTest_s) IS
WHEN "0" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormLow_uid52_fpMulTest_b;
WHEN "1" => fracRPostNorm_uid53_fpMulTest_q <= fracRPostNormHigh_uid51_fpMulTest_b;
WHEN OTHERS => fracRPostNorm_uid53_fpMulTest_q <= (others => '0');
END CASE;
END PROCESS;
-- expFracPreRound_uid55_fpMulTest(BITJOIN,54)@2
expFracPreRound_uid55_fpMulTest_q <= expSumMBias_uid46_fpMulTest_q & fracRPostNorm_uid53_fpMulTest_q;
-- expFracRPostRounding_uid58_fpMulTest(ADD,57)@2
expFracRPostRounding_uid58_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((36 downto 35 => expFracPreRound_uid55_fpMulTest_q(34)) & expFracPreRound_uid55_fpMulTest_q));
expFracRPostRounding_uid58_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "0000000000" & roundBitAndNormalizationOp_uid57_fpMulTest_q));
expFracRPostRounding_uid58_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid58_fpMulTest_a) + SIGNED(expFracRPostRounding_uid58_fpMulTest_b));
expFracRPostRounding_uid58_fpMulTest_q <= expFracRPostRounding_uid58_fpMulTest_o(35 downto 0);
-- expRPreExcExt_uid60_fpMulTest(BITSELECT,59)@2
expRPreExcExt_uid60_fpMulTest_b <= STD_LOGIC_VECTOR(expFracRPostRounding_uid58_fpMulTest_q(35 downto 24));
-- expRPreExc_uid61_fpMulTest(BITSELECT,60)@2
expRPreExc_uid61_fpMulTest_in <= expRPreExcExt_uid60_fpMulTest_b(7 downto 0);
expRPreExc_uid61_fpMulTest_b <= expRPreExc_uid61_fpMulTest_in(7 downto 0);
-- expOvf_uid64_fpMulTest(COMPARE,63)@2
expOvf_uid64_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 12 => expRPreExcExt_uid60_fpMulTest_b(11)) & expRPreExcExt_uid60_fpMulTest_b));
expOvf_uid64_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "00000" & cstAllOWE_uid10_fpMulTest_q));
expOvf_uid64_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid64_fpMulTest_a) - SIGNED(expOvf_uid64_fpMulTest_b));
expOvf_uid64_fpMulTest_n(0) <= not (expOvf_uid64_fpMulTest_o(13));
-- invExpXIsMax_uid35_fpMulTest(LOGICAL,34)@2
invExpXIsMax_uid35_fpMulTest_q <= not (redist3_expXIsMax_uid30_fpMulTest_q_2_q);
-- InvExpXIsZero_uid36_fpMulTest(LOGICAL,35)@2
InvExpXIsZero_uid36_fpMulTest_q <= not (redist4_excZ_y_uid29_fpMulTest_q_2_q);
-- excR_y_uid37_fpMulTest(LOGICAL,36)@2
excR_y_uid37_fpMulTest_q <= InvExpXIsZero_uid36_fpMulTest_q and invExpXIsMax_uid35_fpMulTest_q;
-- invExpXIsMax_uid21_fpMulTest(LOGICAL,20)@2
invExpXIsMax_uid21_fpMulTest_q <= not (redist6_expXIsMax_uid16_fpMulTest_q_2_q);
-- InvExpXIsZero_uid22_fpMulTest(LOGICAL,21)@2
InvExpXIsZero_uid22_fpMulTest_q <= not (redist7_excZ_x_uid15_fpMulTest_q_2_q);
-- excR_x_uid23_fpMulTest(LOGICAL,22)@2
excR_x_uid23_fpMulTest_q <= InvExpXIsZero_uid22_fpMulTest_q and invExpXIsMax_uid21_fpMulTest_q;
-- ExcROvfAndInReg_uid73_fpMulTest(LOGICAL,72)@2
ExcROvfAndInReg_uid73_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expOvf_uid64_fpMulTest_n;
-- excYRAndExcXI_uid72_fpMulTest(LOGICAL,71)@2
excYRAndExcXI_uid72_fpMulTest_q <= excR_y_uid37_fpMulTest_q and excI_x_uid19_fpMulTest_q;
-- excXRAndExcYI_uid71_fpMulTest(LOGICAL,70)@2
excXRAndExcYI_uid71_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excI_y_uid33_fpMulTest_q;
-- excXIAndExcYI_uid70_fpMulTest(LOGICAL,69)@2
excXIAndExcYI_uid70_fpMulTest_q <= excI_x_uid19_fpMulTest_q and excI_y_uid33_fpMulTest_q;
-- excRInf_uid74_fpMulTest(LOGICAL,73)@2
excRInf_uid74_fpMulTest_q <= excXIAndExcYI_uid70_fpMulTest_q or excXRAndExcYI_uid71_fpMulTest_q or excYRAndExcXI_uid72_fpMulTest_q or ExcROvfAndInReg_uid73_fpMulTest_q;
-- expUdf_uid62_fpMulTest(COMPARE,61)@2
expUdf_uid62_fpMulTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "000000000000" & GND_q));
expUdf_uid62_fpMulTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((13 downto 12 => expRPreExcExt_uid60_fpMulTest_b(11)) & expRPreExcExt_uid60_fpMulTest_b));
expUdf_uid62_fpMulTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid62_fpMulTest_a) - SIGNED(expUdf_uid62_fpMulTest_b));
expUdf_uid62_fpMulTest_n(0) <= not (expUdf_uid62_fpMulTest_o(13));
-- excZC3_uid68_fpMulTest(LOGICAL,67)@2
excZC3_uid68_fpMulTest_q <= excR_x_uid23_fpMulTest_q and excR_y_uid37_fpMulTest_q and expUdf_uid62_fpMulTest_n;
-- excYZAndExcXR_uid67_fpMulTest(LOGICAL,66)@2
excYZAndExcXR_uid67_fpMulTest_q <= redist4_excZ_y_uid29_fpMulTest_q_2_q and excR_x_uid23_fpMulTest_q;
-- excXZAndExcYR_uid66_fpMulTest(LOGICAL,65)@2
excXZAndExcYR_uid66_fpMulTest_q <= redist7_excZ_x_uid15_fpMulTest_q_2_q and excR_y_uid37_fpMulTest_q;
-- excXZAndExcYZ_uid65_fpMulTest(LOGICAL,64)@2
excXZAndExcYZ_uid65_fpMulTest_q <= redist7_excZ_x_uid15_fpMulTest_q_2_q and redist4_excZ_y_uid29_fpMulTest_q_2_q;
-- excRZero_uid69_fpMulTest(LOGICAL,68)@2
excRZero_uid69_fpMulTest_q <= excXZAndExcYZ_uid65_fpMulTest_q or excXZAndExcYR_uid66_fpMulTest_q or excYZAndExcXR_uid67_fpMulTest_q or excZC3_uid68_fpMulTest_q;
-- concExc_uid79_fpMulTest(BITJOIN,78)@2
concExc_uid79_fpMulTest_q <= excRNaN_uid78_fpMulTest_q & excRInf_uid74_fpMulTest_q & excRZero_uid69_fpMulTest_q;
-- excREnc_uid80_fpMulTest(LOOKUP,79)@2
excREnc_uid80_fpMulTest_combproc: PROCESS (concExc_uid79_fpMulTest_q)
BEGIN
-- Begin reserved scope level
CASE (concExc_uid79_fpMulTest_q) IS
WHEN "000" => excREnc_uid80_fpMulTest_q <= "01";
WHEN "001" => excREnc_uid80_fpMulTest_q <= "00";
WHEN "010" => excREnc_uid80_fpMulTest_q <= "10";
WHEN "011" => excREnc_uid80_fpMulTest_q <= "00";
WHEN "100" => excREnc_uid80_fpMulTest_q <= "11";
WHEN "101" => excREnc_uid80_fpMulTest_q <= "00";
WHEN "110" => excREnc_uid80_fpMulTest_q <= "00";
WHEN "111" => excREnc_uid80_fpMulTest_q <= "00";
WHEN OTHERS => -- unreachable
excREnc_uid80_fpMulTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- expRPostExc_uid89_fpMulTest(MUX,88)@2
expRPostExc_uid89_fpMulTest_s <= excREnc_uid80_fpMulTest_q;
expRPostExc_uid89_fpMulTest_combproc: PROCESS (expRPostExc_uid89_fpMulTest_s, cstAllZWE_uid12_fpMulTest_q, expRPreExc_uid61_fpMulTest_b, cstAllOWE_uid10_fpMulTest_q)
BEGIN
CASE (expRPostExc_uid89_fpMulTest_s) IS
WHEN "00" => expRPostExc_uid89_fpMulTest_q <= cstAllZWE_uid12_fpMulTest_q;
WHEN "01" => expRPostExc_uid89_fpMulTest_q <= expRPreExc_uid61_fpMulTest_b;
WHEN "10" => expRPostExc_uid89_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q;
WHEN "11" => expRPostExc_uid89_fpMulTest_q <= cstAllOWE_uid10_fpMulTest_q;
WHEN OTHERS => expRPostExc_uid89_fpMulTest_q <= (others => '0');
END CASE;
END PROCESS;
-- oneFracRPostExc2_uid81_fpMulTest(CONSTANT,80)
oneFracRPostExc2_uid81_fpMulTest_q <= "00000000000000000000001";
-- fracRPreExc_uid59_fpMulTest(BITSELECT,58)@2
fracRPreExc_uid59_fpMulTest_in <= expFracRPostRounding_uid58_fpMulTest_q(23 downto 0);
fracRPreExc_uid59_fpMulTest_b <= fracRPreExc_uid59_fpMulTest_in(23 downto 1);
-- fracRPostExc_uid84_fpMulTest(MUX,83)@2
fracRPostExc_uid84_fpMulTest_s <= excREnc_uid80_fpMulTest_q;
fracRPostExc_uid84_fpMulTest_combproc: PROCESS (fracRPostExc_uid84_fpMulTest_s, cstZeroWF_uid11_fpMulTest_q, fracRPreExc_uid59_fpMulTest_b, oneFracRPostExc2_uid81_fpMulTest_q)
BEGIN
CASE (fracRPostExc_uid84_fpMulTest_s) IS
WHEN "00" => fracRPostExc_uid84_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q;
WHEN "01" => fracRPostExc_uid84_fpMulTest_q <= fracRPreExc_uid59_fpMulTest_b;
WHEN "10" => fracRPostExc_uid84_fpMulTest_q <= cstZeroWF_uid11_fpMulTest_q;
WHEN "11" => fracRPostExc_uid84_fpMulTest_q <= oneFracRPostExc2_uid81_fpMulTest_q;
WHEN OTHERS => fracRPostExc_uid84_fpMulTest_q <= (others => '0');
END CASE;
END PROCESS;
-- R_uid92_fpMulTest(BITJOIN,91)@2
R_uid92_fpMulTest_q <= signRPostExc_uid91_fpMulTest_q & expRPostExc_uid89_fpMulTest_q & fracRPostExc_uid84_fpMulTest_q;
-- xOut(GPOUT,4)@2
q <= R_uid92_fpMulTest_q;
END normal;
|
architecture RTL of FIFO is
begin
LABEL_PROC : process
begin
end process LABEL_PROC;
-- Violations below
LABEL_PROCESS : process
begin
end process LABEL_PROCESS;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity rgb2ycbcr is
port
(
rgb : in std_logic_vector(23 downto 0);
de_in : in std_logic;
ycbcr : out std_logic_vector(23 downto 0);
de_out : out std_logic;
rst_n : in std_logic;
clk : in std_logic
);
end entity rgb2ycbcr;
architecture rtl of rgb2ycbcr is
signal Y_reg_1 : signed(23 downto 0):=(others=>'0');
signal Y_reg_2 : signed(23 downto 0):=(others=>'0');
signal Y_reg_3 : signed(23 downto 0):=(others=>'0');
signal Cb_reg_1 : signed(23 downto 0):=(others=>'0');
signal Cb_reg_2 : signed(23 downto 0):=(others=>'0');
signal Cb_reg_3 : signed(23 downto 0):=(others=>'0');
signal Cr_reg_1 : signed(23 downto 0):=(others=>'0');
signal Cr_reg_2 : signed(23 downto 0):=(others=>'0');
signal Cr_reg_3 : signed(23 downto 0):=(others=>'0');
signal Y_reg : signed(23 downto 0):=(others=>'0');
signal Cb_reg : signed(23 downto 0):=(others=>'0');
signal Cr_reg : signed(23 downto 0):=(others=>'0');
constant C_Y_1 : signed(14 downto 0) := to_signed(4899, 15);
constant C_Y_2 : signed(14 downto 0) := to_signed(9617, 15);
constant C_Y_3 : signed(14 downto 0) := to_signed(1868, 15);
constant C_Cb_1 : signed(14 downto 0) := to_signed(-2764, 15);
constant C_Cb_2 : signed(14 downto 0) := to_signed(-5428, 15);
constant C_Cb_3 : signed(14 downto 0) := to_signed(8192, 15);
constant C_Cr_1 : signed(14 downto 0) := to_signed(8192, 15);
constant C_Cr_2 : signed(14 downto 0) := to_signed(-6860, 15);
constant C_Cr_3 : signed(14 downto 0) := to_signed(-1332, 15);
signal R_s : signed(8 downto 0):=(others=>'0');
signal G_s : signed(8 downto 0):=(others=>'0');
signal B_s : signed(8 downto 0):=(others=>'0');
signal Y_8bit : unsigned(7 downto 0):=(others=>'0');
signal Cb_8bit : unsigned(7 downto 0):=(others=>'0');
signal Cr_8bit : unsigned(7 downto 0):=(others=>'0');
signal de_in_q : std_logic;
begin
process(CLK, rst_n)
begin
if rst_n = '0' then
Y_Reg_1 <= (others => '0');
Y_Reg_2 <= (others => '0');
Y_Reg_3 <= (others => '0');
Cb_Reg_1 <= (others => '0');
Cb_Reg_2 <= (others => '0');
Cb_Reg_3 <= (others => '0');
Cr_Reg_1 <= (others => '0');
Cr_Reg_2 <= (others => '0');
Cr_Reg_3 <= (others => '0');
Y_Reg <= (others => '0');
Cb_Reg <= (others => '0');
Cr_Reg <= (others => '0');
de_in_q <= '0';
de_out <= '0';
elsif rising_edge(clk) then
de_in_q <= de_in;
Y_Reg_1 <= R_s*C_Y_1;
Y_Reg_2 <= G_s*C_Y_2;
Y_Reg_3 <= B_s*C_Y_3;
Cb_Reg_1 <= R_s*C_Cb_1;
Cb_Reg_2 <= G_s*C_Cb_2;
Cb_Reg_3 <= B_s*C_Cb_3;
Cr_Reg_1 <= R_s*C_Cr_1;
Cr_Reg_2 <= G_s*C_Cr_2;
Cr_Reg_3 <= B_s*C_Cr_3;
de_out <= de_in_q;
Y_Reg <= Y_Reg_1 + Y_Reg_2 + Y_Reg_3;
Cb_Reg <= Cb_Reg_1 + Cb_Reg_2 + Cb_Reg_3 + to_signed(128*16384,Cb_Reg'length);
Cr_Reg <= Cr_Reg_1 + Cr_Reg_2 + Cr_Reg_3 + to_signed(128*16384,Cr_Reg'length);
end if;
end process;
R_s <= signed('0' & rgb(7 downto 0));
G_s <= signed('0' & rgb(15 downto 8));
B_s <= signed('0' & rgb(23 downto 16));
Y_8bit <= unsigned(Y_Reg(21 downto 14));
Cb_8bit <= unsigned(Cb_Reg(21 downto 14));
Cr_8bit <= unsigned(Cr_Reg(21 downto 14));
ycbcr(7 downto 0) <= std_logic_vector(Y_8bit);
ycbcr(15 downto 8) <= std_logic_vector(Cb_8bit);
ycbcr(23 downto 16) <= std_logic_vector(Cr_8bit);
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity rgb2ycbcr is
port
(
rgb : in std_logic_vector(23 downto 0);
de_in : in std_logic;
ycbcr : out std_logic_vector(23 downto 0);
de_out : out std_logic;
rst_n : in std_logic;
clk : in std_logic
);
end entity rgb2ycbcr;
architecture rtl of rgb2ycbcr is
signal Y_reg_1 : signed(23 downto 0):=(others=>'0');
signal Y_reg_2 : signed(23 downto 0):=(others=>'0');
signal Y_reg_3 : signed(23 downto 0):=(others=>'0');
signal Cb_reg_1 : signed(23 downto 0):=(others=>'0');
signal Cb_reg_2 : signed(23 downto 0):=(others=>'0');
signal Cb_reg_3 : signed(23 downto 0):=(others=>'0');
signal Cr_reg_1 : signed(23 downto 0):=(others=>'0');
signal Cr_reg_2 : signed(23 downto 0):=(others=>'0');
signal Cr_reg_3 : signed(23 downto 0):=(others=>'0');
signal Y_reg : signed(23 downto 0):=(others=>'0');
signal Cb_reg : signed(23 downto 0):=(others=>'0');
signal Cr_reg : signed(23 downto 0):=(others=>'0');
constant C_Y_1 : signed(14 downto 0) := to_signed(4899, 15);
constant C_Y_2 : signed(14 downto 0) := to_signed(9617, 15);
constant C_Y_3 : signed(14 downto 0) := to_signed(1868, 15);
constant C_Cb_1 : signed(14 downto 0) := to_signed(-2764, 15);
constant C_Cb_2 : signed(14 downto 0) := to_signed(-5428, 15);
constant C_Cb_3 : signed(14 downto 0) := to_signed(8192, 15);
constant C_Cr_1 : signed(14 downto 0) := to_signed(8192, 15);
constant C_Cr_2 : signed(14 downto 0) := to_signed(-6860, 15);
constant C_Cr_3 : signed(14 downto 0) := to_signed(-1332, 15);
signal R_s : signed(8 downto 0):=(others=>'0');
signal G_s : signed(8 downto 0):=(others=>'0');
signal B_s : signed(8 downto 0):=(others=>'0');
signal Y_8bit : unsigned(7 downto 0):=(others=>'0');
signal Cb_8bit : unsigned(7 downto 0):=(others=>'0');
signal Cr_8bit : unsigned(7 downto 0):=(others=>'0');
signal de_in_q : std_logic;
begin
process(CLK, rst_n)
begin
if rst_n = '0' then
Y_Reg_1 <= (others => '0');
Y_Reg_2 <= (others => '0');
Y_Reg_3 <= (others => '0');
Cb_Reg_1 <= (others => '0');
Cb_Reg_2 <= (others => '0');
Cb_Reg_3 <= (others => '0');
Cr_Reg_1 <= (others => '0');
Cr_Reg_2 <= (others => '0');
Cr_Reg_3 <= (others => '0');
Y_Reg <= (others => '0');
Cb_Reg <= (others => '0');
Cr_Reg <= (others => '0');
de_in_q <= '0';
de_out <= '0';
elsif rising_edge(clk) then
de_in_q <= de_in;
Y_Reg_1 <= R_s*C_Y_1;
Y_Reg_2 <= G_s*C_Y_2;
Y_Reg_3 <= B_s*C_Y_3;
Cb_Reg_1 <= R_s*C_Cb_1;
Cb_Reg_2 <= G_s*C_Cb_2;
Cb_Reg_3 <= B_s*C_Cb_3;
Cr_Reg_1 <= R_s*C_Cr_1;
Cr_Reg_2 <= G_s*C_Cr_2;
Cr_Reg_3 <= B_s*C_Cr_3;
de_out <= de_in_q;
Y_Reg <= Y_Reg_1 + Y_Reg_2 + Y_Reg_3;
Cb_Reg <= Cb_Reg_1 + Cb_Reg_2 + Cb_Reg_3 + to_signed(128*16384,Cb_Reg'length);
Cr_Reg <= Cr_Reg_1 + Cr_Reg_2 + Cr_Reg_3 + to_signed(128*16384,Cr_Reg'length);
end if;
end process;
R_s <= signed('0' & rgb(7 downto 0));
G_s <= signed('0' & rgb(15 downto 8));
B_s <= signed('0' & rgb(23 downto 16));
Y_8bit <= unsigned(Y_Reg(21 downto 14));
Cb_8bit <= unsigned(Cb_Reg(21 downto 14));
Cr_8bit <= unsigned(Cr_Reg(21 downto 14));
ycbcr(7 downto 0) <= std_logic_vector(Y_8bit);
ycbcr(15 downto 8) <= std_logic_vector(Cb_8bit);
ycbcr(23 downto 16) <= std_logic_vector(Cr_8bit);
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity rgb2ycbcr is
port
(
rgb : in std_logic_vector(23 downto 0);
de_in : in std_logic;
ycbcr : out std_logic_vector(23 downto 0);
de_out : out std_logic;
rst_n : in std_logic;
clk : in std_logic
);
end entity rgb2ycbcr;
architecture rtl of rgb2ycbcr is
signal Y_reg_1 : signed(23 downto 0):=(others=>'0');
signal Y_reg_2 : signed(23 downto 0):=(others=>'0');
signal Y_reg_3 : signed(23 downto 0):=(others=>'0');
signal Cb_reg_1 : signed(23 downto 0):=(others=>'0');
signal Cb_reg_2 : signed(23 downto 0):=(others=>'0');
signal Cb_reg_3 : signed(23 downto 0):=(others=>'0');
signal Cr_reg_1 : signed(23 downto 0):=(others=>'0');
signal Cr_reg_2 : signed(23 downto 0):=(others=>'0');
signal Cr_reg_3 : signed(23 downto 0):=(others=>'0');
signal Y_reg : signed(23 downto 0):=(others=>'0');
signal Cb_reg : signed(23 downto 0):=(others=>'0');
signal Cr_reg : signed(23 downto 0):=(others=>'0');
constant C_Y_1 : signed(14 downto 0) := to_signed(4899, 15);
constant C_Y_2 : signed(14 downto 0) := to_signed(9617, 15);
constant C_Y_3 : signed(14 downto 0) := to_signed(1868, 15);
constant C_Cb_1 : signed(14 downto 0) := to_signed(-2764, 15);
constant C_Cb_2 : signed(14 downto 0) := to_signed(-5428, 15);
constant C_Cb_3 : signed(14 downto 0) := to_signed(8192, 15);
constant C_Cr_1 : signed(14 downto 0) := to_signed(8192, 15);
constant C_Cr_2 : signed(14 downto 0) := to_signed(-6860, 15);
constant C_Cr_3 : signed(14 downto 0) := to_signed(-1332, 15);
signal R_s : signed(8 downto 0):=(others=>'0');
signal G_s : signed(8 downto 0):=(others=>'0');
signal B_s : signed(8 downto 0):=(others=>'0');
signal Y_8bit : unsigned(7 downto 0):=(others=>'0');
signal Cb_8bit : unsigned(7 downto 0):=(others=>'0');
signal Cr_8bit : unsigned(7 downto 0):=(others=>'0');
signal de_in_q : std_logic;
begin
process(CLK, rst_n)
begin
if rst_n = '0' then
Y_Reg_1 <= (others => '0');
Y_Reg_2 <= (others => '0');
Y_Reg_3 <= (others => '0');
Cb_Reg_1 <= (others => '0');
Cb_Reg_2 <= (others => '0');
Cb_Reg_3 <= (others => '0');
Cr_Reg_1 <= (others => '0');
Cr_Reg_2 <= (others => '0');
Cr_Reg_3 <= (others => '0');
Y_Reg <= (others => '0');
Cb_Reg <= (others => '0');
Cr_Reg <= (others => '0');
de_in_q <= '0';
de_out <= '0';
elsif rising_edge(clk) then
de_in_q <= de_in;
Y_Reg_1 <= R_s*C_Y_1;
Y_Reg_2 <= G_s*C_Y_2;
Y_Reg_3 <= B_s*C_Y_3;
Cb_Reg_1 <= R_s*C_Cb_1;
Cb_Reg_2 <= G_s*C_Cb_2;
Cb_Reg_3 <= B_s*C_Cb_3;
Cr_Reg_1 <= R_s*C_Cr_1;
Cr_Reg_2 <= G_s*C_Cr_2;
Cr_Reg_3 <= B_s*C_Cr_3;
de_out <= de_in_q;
Y_Reg <= Y_Reg_1 + Y_Reg_2 + Y_Reg_3;
Cb_Reg <= Cb_Reg_1 + Cb_Reg_2 + Cb_Reg_3 + to_signed(128*16384,Cb_Reg'length);
Cr_Reg <= Cr_Reg_1 + Cr_Reg_2 + Cr_Reg_3 + to_signed(128*16384,Cr_Reg'length);
end if;
end process;
R_s <= signed('0' & rgb(7 downto 0));
G_s <= signed('0' & rgb(15 downto 8));
B_s <= signed('0' & rgb(23 downto 16));
Y_8bit <= unsigned(Y_Reg(21 downto 14));
Cb_8bit <= unsigned(Cb_Reg(21 downto 14));
Cr_8bit <= unsigned(Cr_Reg(21 downto 14));
ycbcr(7 downto 0) <= std_logic_vector(Y_8bit);
ycbcr(15 downto 8) <= std_logic_vector(Cb_8bit);
ycbcr(23 downto 16) <= std_logic_vector(Cr_8bit);
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc961.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p02n01i00961ent IS
END c06s03b00x00p02n01i00961ent;
ARCHITECTURE c06s03b00x00p02n01i00961arch OF c06s03b00x00p02n01i00961ent IS
BEGIN
TESTING: PROCESS
type T1 is record
S1 : Bit ;
S2 : Integer;
end record;
type T2 is record
S11 : BIT ;
S12 : T1 ;
end record;
variable V1 : T2 ;
BEGIN
V1.S12 := 10 ; -- Failure_here
wait for 100 ns;
assert FALSE
report "***FAILED TEST: c06s03b00x00p02n01i00961 - Missing suffix."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p02n01i00961arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc961.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p02n01i00961ent IS
END c06s03b00x00p02n01i00961ent;
ARCHITECTURE c06s03b00x00p02n01i00961arch OF c06s03b00x00p02n01i00961ent IS
BEGIN
TESTING: PROCESS
type T1 is record
S1 : Bit ;
S2 : Integer;
end record;
type T2 is record
S11 : BIT ;
S12 : T1 ;
end record;
variable V1 : T2 ;
BEGIN
V1.S12 := 10 ; -- Failure_here
wait for 100 ns;
assert FALSE
report "***FAILED TEST: c06s03b00x00p02n01i00961 - Missing suffix."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p02n01i00961arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc961.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p02n01i00961ent IS
END c06s03b00x00p02n01i00961ent;
ARCHITECTURE c06s03b00x00p02n01i00961arch OF c06s03b00x00p02n01i00961ent IS
BEGIN
TESTING: PROCESS
type T1 is record
S1 : Bit ;
S2 : Integer;
end record;
type T2 is record
S11 : BIT ;
S12 : T1 ;
end record;
variable V1 : T2 ;
BEGIN
V1.S12 := 10 ; -- Failure_here
wait for 100 ns;
assert FALSE
report "***FAILED TEST: c06s03b00x00p02n01i00961 - Missing suffix."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p02n01i00961arch;
|
------------------------------------------------------------------------------
-- Testbench for cycledncntr.vhd
--
-- Project :
-- File : tb_cycledncntr.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/26
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_CycleDnCntr is
end tb_CycleDnCntr;
architecture arch of tb_CycleDnCntr is
constant CNTWIDTH : integer := 8; -- Counter width
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, load, countdown, done);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT I/O signals
signal LoadxE : std_logic;
signal CinxD : std_logic_vector(CNTWIDTH-1 downto 0);
signal OnxS : std_logic;
signal CoutxD : std_logic_vector(CNTWIDTH-1 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : CycleDnCntr
generic map (
CNTWIDTH => CNTWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
LoadxEI => LoadxE,
CinxDI => CinxD,
OnxSO => OnxS,
CoutxDO => CoutxD);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
LoadxE <= '0';
CinxD <= std_logic_vector(to_unsigned(0, CNTWIDTH));
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= load; -- load start value
LoadxE <= '1';
CinxD <= std_logic_vector(to_unsigned(9, CNTWIDTH));
wait for CLK_PERIOD;
tbStatus <= countdown; -- countdown
LoadxE <= '0';
CinxD <= std_logic_vector(to_unsigned(0, CNTWIDTH));
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= load; -- load start value
LoadxE <= '1'; -- (should *not* be loaded)
CinxD <= std_logic_vector(to_unsigned(9, CNTWIDTH));
wait for CLK_PERIOD;
tbStatus <= countdown; -- countdown
LoadxE <= '0';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= load; -- load start value
LoadxE <= '1';
CinxD <= std_logic_vector(to_unsigned(4, CNTWIDTH));
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
LoadxE <= '0';
tbStatus <= countdown; -- countdown
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= done; -- done
LoadxE <= '0';
CinxD <= std_logic_vector(to_unsigned(0, CNTWIDTH));
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
|
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_sync_reset.vhd
--!
--! @brief fpgaMSP430 Generic reset synchronizer
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
entity fmsp_sync_reset is
port (
--! INPUTs
clk : in std_logic; --! Receiving clock
rst_a : in std_logic; --! Asynchronous reset
--! OUTPUTs
rst_s : out std_logic --! Synchronized resett
);
end entity fmsp_sync_reset;
architecture RTL of fmsp_sync_reset is
signal data_sync : std_logic_vector(1 downto 0);
begin
--=============================================================================
--! 1) SYNCHRONIZER
--=============================================================================
DATA_SYNC_REG : process(clk,rst_a)
begin
if (rst_a = '1') then
data_sync <= "11";
elsif rising_edge(clk) then
data_sync <= data_sync(0) & '0';
end if;
end process DATA_SYNC_REG;
rst_s <= data_sync(1);
end RTL; --! fmsp_sync_reset
|
-------------------------------------------------------------------------------
-- Title : Testbench for one SPI frequency
-- Project :
-------------------------------------------------------------------------------
-- File : spi_single_test.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-11-01
-- Last update: 2014-11-03
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This module tests one SPI channel
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-11-01 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spi_single_test is
generic(
g_width : positive := 16
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
--master
spi_sck_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
spi_ssel_o : out std_logic;
--slave
spi_sck_i : in std_logic;
spi_mosi_i : in std_logic;
spi_miso_o : out std_logic;
spi_ssel_i : in std_logic;
chipscope_control : inout std_logic_vector(35 downto 0)
);
end entity spi_single_test;
architecture structural of spi_single_test is
constant c_cpol : std_logic := '0';
constant c_cpha : std_logic := '0';
constant c_prefetch : positive := 1;
constant c_spi_clk_div : positive := 1;
-- service signals
signal clock : std_logic;
signal enable : std_logic := '1';
-- master signals
signal master_req, master_wren : std_logic;
signal master_di : std_logic_vector(g_width-1 downto 0);
signal count_up : std_logic;
--slave signals
signal slave_valid : std_logic;
signal slave_do : std_logic_vector(g_width-1 downto 0);
signal slave_ok, slave_nok : std_logic;
-- output signals
signal ok_count, nok_count : std_logic_vector(g_width-1 downto 0);
component spi_master is
generic (
N : positive; -- width
CPOL : std_logic;
CPHA : std_logic;
PREFETCH : positive;
SPI_2X_CLK_DIV : positive);
port (
sclk_i : in std_logic := 'X';
pclk_i : in std_logic := 'X';
rst_i : in std_logic := 'X';
spi_ssel_o : out std_logic;
spi_sck_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := 'X';
di_req_o : out std_logic;
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X');
wren_i : in std_logic := 'X';
wr_ack_o : out std_logic;
do_valid_o : out std_logic;
do_o : out std_logic_vector (N-1 downto 0));
end component spi_master;
component spi_slave is
generic (
N : positive;
CPOL : std_logic;
CPHA : std_logic;
PREFETCH : positive);
port (
clk_i : in std_logic := 'X';
spi_ssel_i : in std_logic := 'X';
spi_sck_i : in std_logic := 'X';
spi_mosi_i : in std_logic := 'X';
spi_miso_o : out std_logic := 'X';
di_req_o : out std_logic;
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X');
wren_i : in std_logic := 'X';
wr_ack_o : out std_logic;
do_valid_o : out std_logic;
do_o : out std_logic_vector (N-1 downto 0));
end component spi_slave;
component simple_counter is
generic (
g_width : natural);
port (
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
data_o : out std_logic_vector(g_width-1 downto 0));
end component simple_counter;
component slave_checker is
generic (
g_width : natural);
port (
clk_i : in std_logic;
rst_i : in std_logic;
spi_valid_i : in std_logic;
data_i : in std_logic_vector(g_width-1 downto 0);
ok_o : out std_logic;
nok_o : out std_logic);
end component slave_checker;
component master_controller is
port (
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
spi_req_i : in std_logic;
spi_wen_o : out std_logic;
count_up_o : out std_logic);
end component master_controller;
component chipscope_ila is
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
DATA : in std_logic_vector(63 downto 0);
TRIG0 : in std_logic_vector(7 downto 0));
end component chipscope_ila;
begin
cmp_master_controller : master_controller
port map (
clk_i => clk_i,
en_i => enable,
rst_i => rst_i,
spi_req_i => master_req,
spi_wen_o => master_wren,
count_up_o => count_up);
cmp_count_gen : simple_counter
generic map (
g_width => g_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => count_up,
data_o => master_di);
cmp_master : spi_master
generic map (
N => g_width,
CPOL => c_cpol,
CPHA => c_cpha,
PREFETCH => c_prefetch,
SPI_2X_CLK_DIV => c_spi_clk_div)
port map (
sclk_i => clk_i,
pclk_i => clk_i,
rst_i => rst_i,
spi_ssel_o => spi_ssel_o,
spi_sck_o => spi_sck_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
di_req_o => master_req,
di_i => master_di,
wren_i => master_wren,
wr_ack_o => open,
do_valid_o => open,
do_o => open);
-----------------------------------------------------------------------------
-- slave section
cmp_spi_slave : spi_slave
generic map (
N => g_width,
CPOL => c_cpol,
CPHA => c_cpha,
PREFETCH => c_prefetch)
port map (
clk_i => clk_i,
spi_ssel_i => spi_ssel_i,
spi_sck_i => spi_sck_i,
spi_mosi_i => spi_mosi_i,
spi_miso_o => spi_miso_o,
di_req_o => open,
di_i => (others => '0'),
wren_i => '0',
wr_ack_o => open,
do_valid_o => slave_valid,
do_o => slave_do);
cmp_slave_checker : slave_checker
generic map (
g_width => g_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
spi_valid_i => slave_valid,
data_i => slave_do,
ok_o => slave_ok,
nok_o => slave_nok);
cmp_ok_counter : simple_counter
generic map (
g_width => g_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => slave_ok,
data_o => ok_count);
cmp_nok_counter : simple_counter
generic map (
g_width => g_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => slave_nok,
data_o => nok_count);
cmp_ila : chipscope_ila
port map (
CONTROL => chipscope_control,
CLK => clk_i,
DATA(63 downto 48) => master_di(15 downto 0),
DATA(47 downto 32) => ok_count(15 downto 0),
DATA(31 downto 16) => nok_count(15 downto 0),
DATA(15) => slave_valid,
DATA(14) => slave_ok,
DATA(13) => slave_nok,
DATA(12 downto 0) => slave_do(12 downto 0),
TRIG0(7) => slave_valid,
TRIG0(6 downto 2) => (others => '0'),
TRIG0(1) => slave_ok,
TRIG0(0) => master_req);
end architecture structural;
|
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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|
`protect begin_protected
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 67920)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 67920)
`protect data_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect data_block
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
entity arith1 is
end entity;
architecture test of arith1 is
begin
proc1: process is
variable x, y : integer;
begin
x := 3;
y := 12;
wait for 1 ns;
assert x + y = 15;
assert x - y = -9;
assert x * y = 36;
assert x / 12 = 0;
assert x = 3;
assert y = 12;
assert x /= y;
assert x < y;
assert y > x;
assert x <= y;
assert y >= x;
assert (- x) = -3;
assert x ** y = 531441;
x := -34;
assert abs x = 34;
assert abs y = 12;
assert 5 mod 3 = 2;
assert 5 rem 3 = 2;
assert (-5) rem 3 = -2;
assert (-5) mod 3 = 2;
assert x = +x;
wait;
end process;
end architecture;
|
entity arith1 is
end entity;
architecture test of arith1 is
begin
proc1: process is
variable x, y : integer;
begin
x := 3;
y := 12;
wait for 1 ns;
assert x + y = 15;
assert x - y = -9;
assert x * y = 36;
assert x / 12 = 0;
assert x = 3;
assert y = 12;
assert x /= y;
assert x < y;
assert y > x;
assert x <= y;
assert y >= x;
assert (- x) = -3;
assert x ** y = 531441;
x := -34;
assert abs x = 34;
assert abs y = 12;
assert 5 mod 3 = 2;
assert 5 rem 3 = 2;
assert (-5) rem 3 = -2;
assert (-5) mod 3 = 2;
assert x = +x;
wait;
end process;
end architecture;
|
entity arith1 is
end entity;
architecture test of arith1 is
begin
proc1: process is
variable x, y : integer;
begin
x := 3;
y := 12;
wait for 1 ns;
assert x + y = 15;
assert x - y = -9;
assert x * y = 36;
assert x / 12 = 0;
assert x = 3;
assert y = 12;
assert x /= y;
assert x < y;
assert y > x;
assert x <= y;
assert y >= x;
assert (- x) = -3;
assert x ** y = 531441;
x := -34;
assert abs x = 34;
assert abs y = 12;
assert 5 mod 3 = 2;
assert 5 rem 3 = 2;
assert (-5) rem 3 = -2;
assert (-5) mod 3 = 2;
assert x = +x;
wait;
end process;
end architecture;
|
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
|
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
|
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
|
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2;
constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS;
constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS;
constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS;
constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS;
constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#;
|
--!
--! \file thread.vhd
--!
--! Demo thread for partial reconfiguration (pr_msg_demo)
--!
--! \author Enno Luebbers <[email protected]>
--! \date 10.02.2011
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 10.02.2011 Enno Luebbers File created.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity thread is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_THREAD_NUM : integer := 0 -- equals position in chain
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end thread;
architecture Behavioral of thread is
-- OS synchronization state machine states
type t_state is (STATE_INIT, STATE_RECV, STATE_SETBIT, STATE_NOTIFY, STATE_SEND, STATE_EXIT);
signal state : t_state := STATE_INIT;
-- buffer for modifying messages
signal msg : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of repeat cycles
signal repeat_count : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- signature
signal sig : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
constant C_MB_IN : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_OUT : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_NOTIFY : std_logic_vector(0 to 31) := X"00000002";
begin
-- tie RAM signals low (we don't use them)
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWe <= '0';
o_RAMClk <= '0';
sig(C_THREAD_NUM) <= '1';
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable next_state : t_state := STATE_INIT;
begin
if reset = '1' then
reconos_reset_with_signature(o_osif, i_osif, sig);
state <= STATE_INIT;
next_state := STATE_INIT;
done := false;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- read number of repeats from init data
when STATE_INIT =>
reconos_get_init_data_s(done, o_osif, i_osif, repeat_count);
next_state := STATE_RECV;
-- read data in message box
when STATE_RECV =>
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_IN, msg);
next_state := STATE_SETBIT;
-- set message bit
when STATE_SETBIT =>
msg(C_THREAD_NUM) <= '1';
next_state := STATE_NOTIFY;
-- notify main()
when STATE_NOTIFY =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_NOTIFY, sig);
next_state := STATE_SEND;
-- send modified message to next message box
when STATE_SEND =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_OUT, msg);
if repeat_count = 0 then
next_state := STATE_EXIT;
else
repeat_count <= repeat_count - 1;
next_state := STATE_RECV;
end if;
-- terminate
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, C_RECONOS_SUCCESS);
when others =>
next_state := STATE_INIT;
end case;
if done then
state <= next_state;
end if;
end if;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:41:06 02/07/2014
-- Design Name:
-- Module Name: C:/SoundboxProject/Source/soundbox-vhdl/ISEProject/Soundbox/Source/AudioIO/ADSampler_tb.vhd
-- Project Name: Soundbox
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ADSampler
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ADSampler_tb IS
END ADSampler_tb;
ARCHITECTURE behavior OF ADSampler_tb IS
-- Component Declaration for the Unit Under Test (UUT)
--Inputs
signal DRP_output : std_logic_vector(15 downto 0) := (others => '0');
signal DRP_dataReady : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal DRP_input : std_logic_vector(15 downto 0);
signal DRP_address : std_logic_vector(6 downto 0);
signal DRP_enable : std_logic;
signal DRP_writeEnable : std_logic;
signal DRP_clk : std_logic;
signal XADC_reset : std_logic;
signal XADC_EOC : std_logic := '0';
signal XADC_busy : std_logic := '0';
signal output : std_logic_vector(11 downto 0);
-- Clock period definitions
constant DRP_clk_period : time := 10 ns;
constant XADC_convstclk_period : time := 10 ns;
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.ADSampler
port map(
DRP_output => DRP_output,
DRP_dataReady => DRP_dataReady,
DRP_input => DRP_input,
DRP_address => DRP_address,
DRP_enable => DRP_enable,
DRP_writeEnable => DRP_writeEnable,
DRP_clk => DRP_clk,
XADC_reset => XADC_reset,
XADC_EOC => XADC_EOC,
XADC_busy => XADC_busy,
output => output,
clk => clk,
reset => reset
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
XADC_busy <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*5;
XADC_busy <= '0';
wait for clk_period*10;
XADC_EOC <= '1';
wait for clk_period;
XADC_EOC <= '0';
wait for clk_period*5;
DRP_dataReady <= '1';
DRP_output <= (others => '1');
wait for clk_period;
DRP_dataReady <= '0';
-- insert stimulus here
wait;
end process;
END;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
-- Inspired by similar functionality in SystemVerilog/UVM and OSVVM.
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Local package
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package local_pkg is
function slv_to_string(
constant value : in std_logic_vector
) return string;
end package local_pkg;
package body local_pkg is
function slv_to_string(
constant value : in std_logic_vector
) return string is
begin
return to_string(value, HEX, KEEP_LEADING_0, INCL_RADIX);
end function;
end package body local_pkg;
------------------------------------------------------------------------------------------
--
-- slv_sb_pkg
--
-- Predefined scoreboard package for std_logic_vector. Vector length is defined by
-- the constant C_SB_SLV_WIDTH located under scoreboard adaptions in adaptions_pkg.
--
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use work.local_pkg.all;
-- WARNING! The slv_sb_pkg will be deprecated
package slv_sb_pkg is new work.generic_sb_pkg
generic map (t_element => std_logic_vector(C_SB_SLV_WIDTH-1 downto 0),
element_match => std_match,
to_string_element => slv_to_string);
------------------------------------------------------------------------------------------
--
-- slv8_sb_pkg
--
-- Predefined scoreboard package for std_logic_vector(7 downto 0).
--
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use work.local_pkg.all;
package slv8_sb_pkg is new work.generic_sb_pkg
generic map (t_element => std_logic_vector(7 downto 0),
element_match => std_match,
to_string_element => slv_to_string);
------------------------------------------------------------------------------------------
--
-- int_sb_pkg
--
-- Predefined scoreboard package for integer.
--
------------------------------------------------------------------------------------------
package int_sb_pkg is new work.generic_sb_pkg
generic map (t_element => integer,
element_match => "=",
to_string_element => to_string); |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: [email protected]
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 1, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
--------------------------------------------------------------------------
--
-- $RCSfile: dlx_types-body.vhdl,v $ $Revision: 2.1 $ $Date: 1993/10/31 20:37:38 $
--
--------------------------------------------------------------------------
--
-- Package body for types used in dlx model
--
package body dlx_types is
function resolve_dlx_word (values : in dlx_word_array) return dlx_word is
variable result : dlx_word := X"0000_0000";
begin
for i in values'range loop
result := result or values(i);
end loop;
return result;
end resolve_dlx_word;
end dlx_types;
|
-- Vhdl test bench created from schematic C:\Users\fafik\Dropbox\infa\git\ethernet\ethernet4b\CU_test1.sch - Mon Aug 25 21:35:04 2014
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY CU_test1_CU_test1_sch_tb IS
END CU_test1_CU_test1_sch_tb;
ARCHITECTURE behavioral OF CU_test1_CU_test1_sch_tb IS
COMPONENT CU_test1
PORT( clk : IN STD_LOGIC;
E_RX_D : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
E_RX_CLK : IN STD_LOGIC;
E_RX_DV : IN STD_LOGIC;
full : OUT STD_LOGIC;
test : OUT STD_LOGIC);
END COMPONENT;
SIGNAL clk : STD_LOGIC;
SIGNAL E_RX_D : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL E_RX_CLK : STD_LOGIC;
SIGNAL E_RX_DV : STD_LOGIC;
SIGNAL full : STD_LOGIC;
SIGNAL test : STD_LOGIC;
BEGIN
UUT: CU_test1 PORT MAP(
clk => clk,
E_RX_D => E_RX_D,
E_RX_CLK => E_RX_CLK,
E_RX_DV => E_RX_DV,
full => full,
test => test
);
process (clk)
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
process (E_RX_CLK)
begin
E_RX_CLK <= '0';
wait for 200 ns;
E_RX_CLK <= '1';
wait for 200 ns;
end process;
E_RX_D <= "0000", "0101" after 200 ns, "1101" after 600 ns, "0011" after 1000 ns, "0011" after 1400 ns;
E_RX_DV <= '0', '1' after 200 ns, '0' after 1800 ns;
END;
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_ch_08_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package ch_08_02 is
-- code from book
subtype word32 is bit_vector(31 downto 0);
procedure add ( a, b : in word32;
result : out word32; overflow : out boolean );
function "<" ( a, b : in word32 ) return boolean;
constant max_buffer_size : positive;
-- end code from book
end package ch_08_02;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_ch_08_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package ch_08_02 is
-- code from book
subtype word32 is bit_vector(31 downto 0);
procedure add ( a, b : in word32;
result : out word32; overflow : out boolean );
function "<" ( a, b : in word32 ) return boolean;
constant max_buffer_size : positive;
-- end code from book
end package ch_08_02;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_ch_08_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package ch_08_02 is
-- code from book
subtype word32 is bit_vector(31 downto 0);
procedure add ( a, b : in word32;
result : out word32; overflow : out boolean );
function "<" ( a, b : in word32 ) return boolean;
constant max_buffer_size : positive;
-- end code from book
end package ch_08_02;
|
entity issue467 is
end entity;
architecture test of issue467 is
type int_array is array (natural range <>) of integer_vector;
function sum_all (x : int_array) return integer is
variable result : integer := 0;
begin
for i in x'range loop
for j in x(i)'range loop
result := result + x(i)(j);
end loop;
end loop;
return result;
end function;
function get_slice (x : int_array; l, r : natural) return int_array is
begin
return x(l to r);
end function;
signal s1 : int_array(1 to 3)(1 to 2) := ( (1, 2), (3, 4), (5, 6) );
begin
p1: process is
begin
assert sum_all(s1) = 21;
assert get_slice(s1, 1, 2) = ( (1, 2), (3, 4) );
assert get_slice(s1, 3, 3) = ( 0 => (5, 6) );
assert get_slice(s1, 3, 0) = ( 1 to 0 => (1, 1) );
assert get_slice(s1, 1, 2)(2) = ( (3, 4) );
s1(2)(2) <= 10;
wait for 1 ns;
assert sum_all(s1) = 27;
wait;
end process;
end architecture;
|
-- NEED RESULT: ARCH00336.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P4: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P5: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P6: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P7: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P8: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P9: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P10: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P11: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P12: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P13: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P14: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P15: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P16: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336.P17: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00336: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P17: Transport transactions completed entirely passed
-- NEED RESULT: P16: Transport transactions completed entirely passed
-- NEED RESULT: P15: Transport transactions completed entirely passed
-- NEED RESULT: P14: Transport transactions completed entirely passed
-- NEED RESULT: P13: Transport transactions completed entirely passed
-- NEED RESULT: P12: Transport transactions completed entirely passed
-- NEED RESULT: P11: Transport transactions completed entirely passed
-- NEED RESULT: P10: Transport transactions completed entirely passed
-- NEED RESULT: P9: Transport transactions completed entirely passed
-- NEED RESULT: P8: Transport transactions completed entirely passed
-- NEED RESULT: P7: Transport transactions completed entirely passed
-- NEED RESULT: P6: Transport transactions completed entirely passed
-- NEED RESULT: P5: Transport transactions completed entirely passed
-- NEED RESULT: P4: Transport transactions completed entirely passed
-- NEED RESULT: P3: Transport transactions completed entirely passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00336
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00336(ARCH00336)
-- ENT00336_Test_Bench(ARCH00336_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00336 is
end ENT00336 ;
--
--
architecture ARCH00336 of ENT00336 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_boolean_savt : chk_time_type := 0 ns ;
signal s_bit_savt : chk_time_type := 0 ns ;
signal s_severity_level_savt : chk_time_type := 0 ns ;
signal s_character_savt : chk_time_type := 0 ns ;
signal s_st_enum1_savt : chk_time_type := 0 ns ;
signal s_integer_savt : chk_time_type := 0 ns ;
signal s_st_int1_savt : chk_time_type := 0 ns ;
signal s_time_savt : chk_time_type := 0 ns ;
signal s_st_phys1_savt : chk_time_type := 0 ns ;
signal s_real_savt : chk_time_type := 0 ns ;
signal s_st_real1_savt : chk_time_type := 0 ns ;
signal s_st_rec1_savt : chk_time_type := 0 ns ;
signal s_st_rec2_savt : chk_time_type := 0 ns ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
signal s_st_arr1_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
signal s_st_arr3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_boolean_cnt : chk_cnt_type := 0 ;
signal s_bit_cnt : chk_cnt_type := 0 ;
signal s_severity_level_cnt : chk_cnt_type := 0 ;
signal s_character_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_cnt : chk_cnt_type := 0 ;
signal s_integer_cnt : chk_cnt_type := 0 ;
signal s_st_int1_cnt : chk_cnt_type := 0 ;
signal s_time_cnt : chk_cnt_type := 0 ;
signal s_st_phys1_cnt : chk_cnt_type := 0 ;
signal s_real_cnt : chk_cnt_type := 0 ;
signal s_st_real1_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
signal s_st_arr1_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal boolean_select : select_type := 1 ;
signal bit_select : select_type := 1 ;
signal severity_level_select : select_type := 1 ;
signal character_select : select_type := 1 ;
signal st_enum1_select : select_type := 1 ;
signal integer_select : select_type := 1 ;
signal st_int1_select : select_type := 1 ;
signal time_select : select_type := 1 ;
signal st_phys1_select : select_type := 1 ;
signal real_select : select_type := 1 ;
signal st_real1_select : select_type := 1 ;
signal st_rec1_select : select_type := 1 ;
signal st_rec2_select : select_type := 1 ;
signal st_rec3_select : select_type := 1 ;
signal st_arr1_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
signal st_arr3_select : select_type := 1 ;
--
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
begin
CHG1 :
process ( s_boolean )
variable correct : boolean ;
begin
case s_boolean_cnt is
when 0
=> null ;
-- s_boolean <= transport
-- c_boolean_2 after 10 ns,
-- c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
boolean_select <= transport 2 ;
-- s_boolean <= transport
-- c_boolean_2 after 10 ns ,
-- c_boolean_1 after 20 ns ,
-- c_boolean_2 after 30 ns ,
-- c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean =
c_boolean_2 and
(s_boolean_savt + 10 ns) = Std.Standard.Now ;
boolean_select <= transport 3 ;
-- s_boolean <= transport
-- c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean =
c_boolean_1 and
(s_boolean_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_boolean_savt <= transport Std.Standard.Now ;
chk_boolean <= transport s_boolean_cnt
after (1 us - Std.Standard.Now) ;
s_boolean_cnt <= transport s_boolean_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_boolean = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with boolean_select select
s_boolean <= transport
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns
when 1,
--
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns
when 2,
--
c_boolean_1 after 5 ns when 3 ;
--
CHG2 :
process ( s_bit )
variable correct : boolean ;
begin
case s_bit_cnt is
when 0
=> null ;
-- s_bit <= transport
-- c_bit_2 after 10 ns,
-- c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
bit_select <= transport 2 ;
-- s_bit <= transport
-- c_bit_2 after 10 ns ,
-- c_bit_1 after 20 ns ,
-- c_bit_2 after 30 ns ,
-- c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit =
c_bit_2 and
(s_bit_savt + 10 ns) = Std.Standard.Now ;
bit_select <= transport 3 ;
-- s_bit <= transport
-- c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit =
c_bit_1 and
(s_bit_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_bit_savt <= transport Std.Standard.Now ;
chk_bit <= transport s_bit_cnt
after (1 us - Std.Standard.Now) ;
s_bit_cnt <= transport s_bit_cnt + 1 ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_bit = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with bit_select select
s_bit <= transport
c_bit_2 after 10 ns,
c_bit_1 after 20 ns
when 1,
--
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns
when 2,
--
c_bit_1 after 5 ns when 3 ;
--
CHG3 :
process ( s_severity_level )
variable correct : boolean ;
begin
case s_severity_level_cnt is
when 0
=> null ;
-- s_severity_level <= transport
-- c_severity_level_2 after 10 ns,
-- c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
severity_level_select <= transport 2 ;
-- s_severity_level <= transport
-- c_severity_level_2 after 10 ns ,
-- c_severity_level_1 after 20 ns ,
-- c_severity_level_2 after 30 ns ,
-- c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level =
c_severity_level_2 and
(s_severity_level_savt + 10 ns) = Std.Standard.Now ;
severity_level_select <= transport 3 ;
-- s_severity_level <= transport
-- c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level =
c_severity_level_1 and
(s_severity_level_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_severity_level_savt <= transport Std.Standard.Now ;
chk_severity_level <= transport s_severity_level_cnt
after (1 us - Std.Standard.Now) ;
s_severity_level_cnt <= transport s_severity_level_cnt + 1 ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_severity_level = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with severity_level_select select
s_severity_level <= transport
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns
when 1,
--
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns
when 2,
--
c_severity_level_1 after 5 ns when 3 ;
--
CHG4 :
process ( s_character )
variable correct : boolean ;
begin
case s_character_cnt is
when 0
=> null ;
-- s_character <= transport
-- c_character_2 after 10 ns,
-- c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P4" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
character_select <= transport 2 ;
-- s_character <= transport
-- c_character_2 after 10 ns ,
-- c_character_1 after 20 ns ,
-- c_character_2 after 30 ns ,
-- c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character =
c_character_2 and
(s_character_savt + 10 ns) = Std.Standard.Now ;
character_select <= transport 3 ;
-- s_character <= transport
-- c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character =
c_character_1 and
(s_character_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_character_savt <= transport Std.Standard.Now ;
chk_character <= transport s_character_cnt
after (1 us - Std.Standard.Now) ;
s_character_cnt <= transport s_character_cnt + 1 ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions completed entirely",
chk_character = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with character_select select
s_character <= transport
c_character_2 after 10 ns,
c_character_1 after 20 ns
when 1,
--
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns
when 2,
--
c_character_1 after 5 ns when 3 ;
--
CHG5 :
process ( s_st_enum1 )
variable correct : boolean ;
begin
case s_st_enum1_cnt is
when 0
=> null ;
-- s_st_enum1 <= transport
-- c_st_enum1_2 after 10 ns,
-- c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P5" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_select <= transport 2 ;
-- s_st_enum1 <= transport
-- c_st_enum1_2 after 10 ns ,
-- c_st_enum1_1 after 20 ns ,
-- c_st_enum1_2 after 30 ns ,
-- c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 =
c_st_enum1_2 and
(s_st_enum1_savt + 10 ns) = Std.Standard.Now ;
st_enum1_select <= transport 3 ;
-- s_st_enum1 <= transport
-- c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 =
c_st_enum1_1 and
(s_st_enum1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_enum1_savt <= transport Std.Standard.Now ;
chk_st_enum1 <= transport s_st_enum1_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions completed entirely",
chk_st_enum1 = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_enum1_select select
s_st_enum1 <= transport
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns
when 1,
--
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns
when 2,
--
c_st_enum1_1 after 5 ns when 3 ;
--
CHG6 :
process ( s_integer )
variable correct : boolean ;
begin
case s_integer_cnt is
when 0
=> null ;
-- s_integer <= transport
-- c_integer_2 after 10 ns,
-- c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P6" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
integer_select <= transport 2 ;
-- s_integer <= transport
-- c_integer_2 after 10 ns ,
-- c_integer_1 after 20 ns ,
-- c_integer_2 after 30 ns ,
-- c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer =
c_integer_2 and
(s_integer_savt + 10 ns) = Std.Standard.Now ;
integer_select <= transport 3 ;
-- s_integer <= transport
-- c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer =
c_integer_1 and
(s_integer_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_integer_savt <= transport Std.Standard.Now ;
chk_integer <= transport s_integer_cnt
after (1 us - Std.Standard.Now) ;
s_integer_cnt <= transport s_integer_cnt + 1 ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions completed entirely",
chk_integer = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with integer_select select
s_integer <= transport
c_integer_2 after 10 ns,
c_integer_1 after 20 ns
when 1,
--
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns
when 2,
--
c_integer_1 after 5 ns when 3 ;
--
CHG7 :
process ( s_st_int1 )
variable correct : boolean ;
begin
case s_st_int1_cnt is
when 0
=> null ;
-- s_st_int1 <= transport
-- c_st_int1_2 after 10 ns,
-- c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P7" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_int1_select <= transport 2 ;
-- s_st_int1 <= transport
-- c_st_int1_2 after 10 ns ,
-- c_st_int1_1 after 20 ns ,
-- c_st_int1_2 after 30 ns ,
-- c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 =
c_st_int1_2 and
(s_st_int1_savt + 10 ns) = Std.Standard.Now ;
st_int1_select <= transport 3 ;
-- s_st_int1 <= transport
-- c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 =
c_st_int1_1 and
(s_st_int1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_int1_savt <= transport Std.Standard.Now ;
chk_st_int1 <= transport s_st_int1_cnt
after (1 us - Std.Standard.Now) ;
s_st_int1_cnt <= transport s_st_int1_cnt + 1 ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions completed entirely",
chk_st_int1 = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_int1_select select
s_st_int1 <= transport
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns
when 1,
--
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns
when 2,
--
c_st_int1_1 after 5 ns when 3 ;
--
CHG8 :
process ( s_time )
variable correct : boolean ;
begin
case s_time_cnt is
when 0
=> null ;
-- s_time <= transport
-- c_time_2 after 10 ns,
-- c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P8" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
time_select <= transport 2 ;
-- s_time <= transport
-- c_time_2 after 10 ns ,
-- c_time_1 after 20 ns ,
-- c_time_2 after 30 ns ,
-- c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time =
c_time_2 and
(s_time_savt + 10 ns) = Std.Standard.Now ;
time_select <= transport 3 ;
-- s_time <= transport
-- c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time =
c_time_1 and
(s_time_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_time_savt <= transport Std.Standard.Now ;
chk_time <= transport s_time_cnt
after (1 us - Std.Standard.Now) ;
s_time_cnt <= transport s_time_cnt + 1 ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions completed entirely",
chk_time = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with time_select select
s_time <= transport
c_time_2 after 10 ns,
c_time_1 after 20 ns
when 1,
--
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns
when 2,
--
c_time_1 after 5 ns when 3 ;
--
CHG9 :
process ( s_st_phys1 )
variable correct : boolean ;
begin
case s_st_phys1_cnt is
when 0
=> null ;
-- s_st_phys1 <= transport
-- c_st_phys1_2 after 10 ns,
-- c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P9" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_phys1_select <= transport 2 ;
-- s_st_phys1 <= transport
-- c_st_phys1_2 after 10 ns ,
-- c_st_phys1_1 after 20 ns ,
-- c_st_phys1_2 after 30 ns ,
-- c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 =
c_st_phys1_2 and
(s_st_phys1_savt + 10 ns) = Std.Standard.Now ;
st_phys1_select <= transport 3 ;
-- s_st_phys1 <= transport
-- c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 =
c_st_phys1_1 and
(s_st_phys1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_phys1_savt <= transport Std.Standard.Now ;
chk_st_phys1 <= transport s_st_phys1_cnt
after (1 us - Std.Standard.Now) ;
s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions completed entirely",
chk_st_phys1 = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_phys1_select select
s_st_phys1 <= transport
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns
when 1,
--
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns
when 2,
--
c_st_phys1_1 after 5 ns when 3 ;
--
CHG10 :
process ( s_real )
variable correct : boolean ;
begin
case s_real_cnt is
when 0
=> null ;
-- s_real <= transport
-- c_real_2 after 10 ns,
-- c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P10" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
real_select <= transport 2 ;
-- s_real <= transport
-- c_real_2 after 10 ns ,
-- c_real_1 after 20 ns ,
-- c_real_2 after 30 ns ,
-- c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real =
c_real_2 and
(s_real_savt + 10 ns) = Std.Standard.Now ;
real_select <= transport 3 ;
-- s_real <= transport
-- c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real =
c_real_1 and
(s_real_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_real_savt <= transport Std.Standard.Now ;
chk_real <= transport s_real_cnt
after (1 us - Std.Standard.Now) ;
s_real_cnt <= transport s_real_cnt + 1 ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions completed entirely",
chk_real = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
with real_select select
s_real <= transport
c_real_2 after 10 ns,
c_real_1 after 20 ns
when 1,
--
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns
when 2,
--
c_real_1 after 5 ns when 3 ;
--
CHG11 :
process ( s_st_real1 )
variable correct : boolean ;
begin
case s_st_real1_cnt is
when 0
=> null ;
-- s_st_real1 <= transport
-- c_st_real1_2 after 10 ns,
-- c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P11" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real1_select <= transport 2 ;
-- s_st_real1 <= transport
-- c_st_real1_2 after 10 ns ,
-- c_st_real1_1 after 20 ns ,
-- c_st_real1_2 after 30 ns ,
-- c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 =
c_st_real1_2 and
(s_st_real1_savt + 10 ns) = Std.Standard.Now ;
st_real1_select <= transport 3 ;
-- s_st_real1 <= transport
-- c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 =
c_st_real1_1 and
(s_st_real1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_real1_savt <= transport Std.Standard.Now ;
chk_st_real1 <= transport s_st_real1_cnt
after (1 us - Std.Standard.Now) ;
s_st_real1_cnt <= transport s_st_real1_cnt + 1 ;
--
end process CHG11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions completed entirely",
chk_st_real1 = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
--
with st_real1_select select
s_st_real1 <= transport
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns
when 1,
--
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns
when 2,
--
c_st_real1_1 after 5 ns when 3 ;
--
CHG12 :
process ( s_st_rec1 )
variable correct : boolean ;
begin
case s_st_rec1_cnt is
when 0
=> null ;
-- s_st_rec1 <= transport
-- c_st_rec1_2 after 10 ns,
-- c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P12" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_select <= transport 2 ;
-- s_st_rec1 <= transport
-- c_st_rec1_2 after 10 ns ,
-- c_st_rec1_1 after 20 ns ,
-- c_st_rec1_2 after 30 ns ,
-- c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 =
c_st_rec1_2 and
(s_st_rec1_savt + 10 ns) = Std.Standard.Now ;
st_rec1_select <= transport 3 ;
-- s_st_rec1 <= transport
-- c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 =
c_st_rec1_1 and
(s_st_rec1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec1_savt <= transport Std.Standard.Now ;
chk_st_rec1 <= transport s_st_rec1_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ;
--
end process CHG12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions completed entirely",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
--
with st_rec1_select select
s_st_rec1 <= transport
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns
when 1,
--
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns
when 2,
--
c_st_rec1_1 after 5 ns when 3 ;
--
CHG13 :
process ( s_st_rec2 )
variable correct : boolean ;
begin
case s_st_rec2_cnt is
when 0
=> null ;
-- s_st_rec2 <= transport
-- c_st_rec2_2 after 10 ns,
-- c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P13" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_select <= transport 2 ;
-- s_st_rec2 <= transport
-- c_st_rec2_2 after 10 ns ,
-- c_st_rec2_1 after 20 ns ,
-- c_st_rec2_2 after 30 ns ,
-- c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 =
c_st_rec2_2 and
(s_st_rec2_savt + 10 ns) = Std.Standard.Now ;
st_rec2_select <= transport 3 ;
-- s_st_rec2 <= transport
-- c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 =
c_st_rec2_1 and
(s_st_rec2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec2_savt <= transport Std.Standard.Now ;
chk_st_rec2 <= transport s_st_rec2_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ;
--
end process CHG13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions completed entirely",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
--
with st_rec2_select select
s_st_rec2 <= transport
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns
when 1,
--
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns
when 2,
--
c_st_rec2_1 after 5 ns when 3 ;
--
CHG14 :
process ( s_st_rec3 )
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3 <= transport
-- c_st_rec3_2 after 10 ns,
-- c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P14" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3 <= transport
-- c_st_rec3_2 after 10 ns ,
-- c_st_rec3_1 after 20 ns ,
-- c_st_rec3_2 after 30 ns ,
-- c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 =
c_st_rec3_2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3 <= transport
-- c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 =
c_st_rec3_1 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
--
end process CHG14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
--
with st_rec3_select select
s_st_rec3 <= transport
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns
when 1,
--
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns
when 2,
--
c_st_rec3_1 after 5 ns when 3 ;
--
CHG15 :
process ( s_st_arr1 )
variable correct : boolean ;
begin
case s_st_arr1_cnt is
when 0
=> null ;
-- s_st_arr1 <= transport
-- c_st_arr1_2 after 10 ns,
-- c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P15" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr1_select <= transport 2 ;
-- s_st_arr1 <= transport
-- c_st_arr1_2 after 10 ns ,
-- c_st_arr1_1 after 20 ns ,
-- c_st_arr1_2 after 30 ns ,
-- c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 =
c_st_arr1_2 and
(s_st_arr1_savt + 10 ns) = Std.Standard.Now ;
st_arr1_select <= transport 3 ;
-- s_st_arr1 <= transport
-- c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 =
c_st_arr1_1 and
(s_st_arr1_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr1_savt <= transport Std.Standard.Now ;
chk_st_arr1 <= transport s_st_arr1_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ;
--
end process CHG15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions completed entirely",
chk_st_arr1 = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
--
with st_arr1_select select
s_st_arr1 <= transport
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns
when 1,
--
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns
when 2,
--
c_st_arr1_1 after 5 ns when 3 ;
--
CHG16 :
process ( s_st_arr2 )
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2 <= transport
-- c_st_arr2_2 after 10 ns,
-- c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P16" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2 <= transport
-- c_st_arr2_2 after 10 ns ,
-- c_st_arr2_1 after 20 ns ,
-- c_st_arr2_2 after 30 ns ,
-- c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 =
c_st_arr2_2 and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2 <= transport
-- c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 =
c_st_arr2_1 and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
--
end process CHG16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions completed entirely",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
--
with st_arr2_select select
s_st_arr2 <= transport
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns
when 1,
--
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns
when 2,
--
c_st_arr2_1 after 5 ns when 3 ;
--
CHG17 :
process ( s_st_arr3 )
variable correct : boolean ;
begin
case s_st_arr3_cnt is
when 0
=> null ;
-- s_st_arr3 <= transport
-- c_st_arr3_2 after 10 ns,
-- c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00336.P17" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_select <= transport 2 ;
-- s_st_arr3 <= transport
-- c_st_arr3_2 after 10 ns ,
-- c_st_arr3_1 after 20 ns ,
-- c_st_arr3_2 after 30 ns ,
-- c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 =
c_st_arr3_2 and
(s_st_arr3_savt + 10 ns) = Std.Standard.Now ;
st_arr3_select <= transport 3 ;
-- s_st_arr3 <= transport
-- c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 =
c_st_arr3_1 and
(s_st_arr3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00336" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00336" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr3_savt <= transport Std.Standard.Now ;
chk_st_arr3 <= transport s_st_arr3_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ;
--
end process CHG17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions completed entirely",
chk_st_arr3 = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
with st_arr3_select select
s_st_arr3 <= transport
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns
when 1,
--
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns
when 2,
--
c_st_arr3_1 after 5 ns when 3 ;
--
end ARCH00336 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00336_Test_Bench is
end ENT00336_Test_Bench ;
--
--
architecture ARCH00336_Test_Bench of ENT00336_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00336 ( ARCH00336 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00336_Test_Bench ;
|
--------------------------------------------------------------------------------
-- Company: KTH
--
-- File: WOLF_CONTROLLER.vhd
-- File history:
-- v0.1: 2017-04-15: Initial verision for drop test only
--
-- Description:
-- Controller for the REXUS - WOLF exeriment. Handles the statemachine and status communication.
--
-- Backup version:
-- 2017-05-28: D.R: 19:20: First version, light led at 5 sec, turn off led at 10 sec.
--
-- Targeted device: <Family::ProASIC3> <Die::A3P250> <Package::100 VQFP>
-- Author: David Rozenbeek
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity WOLF_CONTROLLER is
port (
---------------------------------------------------
-- Inputs --
---------------------------------------------------
clk_main : IN std_logic; -- Main clock
clk_1hz : IN std_logic; -- 1 Hz clock
reset : IN std_logic; -- Reset (when 1)
rocket_pin : IN std_logic; -- rocket pin if mounted in RMU = 1, ejected = 0
---------------------------------------------------
-- Outputs --
---------------------------------------------------
cutter_en: OUT std_logic -- Cutter Enable (0=Off, 1=On)
);
end WOLF_CONTROLLER;
architecture architecture_WOLF_CONTROLLER of WOLF_CONTROLLER is
--####################### Constants #####################################
constant sec_cutter_enable : integer := 10; -- Seconds cutter should be enabled
constant sec_to_cutter_enable : integer := 5; -- Seconds from ejection to enable cutter.
--####################### Signals #####################################
----------------------------------------------------------------------------------------------------------------------
-- Control signals |Comments --
----------------------------------------------------------------------------------------------------------------------
signal rocket_pin_old : std_logic; --
-----------------------------------------------------------------------------------------------------------------------
-- Mission counter |Comments --
-----------------------------------------------------------------------------------------------------------------------
signal sec_since_eject : unsigned(12 downto 0) := (others => '0'); -- Variable to keep track of seconds since ejection
-----------------------------------------------------------------------------------------------------------------------
-- State Machine Signals |Comments --
-----------------------------------------------------------------------------------------------------------------------
type state is (START, IDLE, EJECTED, CUTTER_ENABLE, CUTTER_DISABLE, SLEEP); -- State declaration
signal current_state : state; -- Current state value
signal next_state : state := START; -- Next clock cycle state value
--################# Architecture Body ###########################
begin
-----------------------------------------------------------------
-- Signal/Port mapping --
-----------------------------------------------------------------
-----------------------------------------------------------------
-- Mission counter --
-- Description: --
-- Keeps track of seconds since ejected, counts up to --
-- 2^12 = 4096 seconds (68,3 min) and then overflows back to 0.--
-----------------------------------------------------------------
mission_counter: process(clk_1hz, rocket_pin, reset)
begin
if ( reset = '1' ) then
sec_since_eject <= (others => '0');
else
if ( rising_edge(clk_1hz) ) then
sec_since_eject <= sec_since_eject + 1;
end if;
end if;
end process;
-----------------------------------------------------------------
-- Main State Machine --
-- Description: --
-- Makes transitions betweens states --
-----------------------------------------------------------------
main_state_machine : process(clk_main, reset, sec_since_eject, current_state, clk_1hz)
begin
rocket_pin_old <= rocket_pin;
if(reset = '1') then
rocket_pin_old <= '0';
cutter_en <= '0';
current_state <= START;
elsif(rising_edge(clk_main)) then
current_state <= next_state;
case current_state is
-- Starting state
when START =>
rocket_pin_old <= '0';
cutter_en <= '0';
next_state <= IDLE;
-- IDLE state
when IDLE =>
-- if ('1') then --rocket_pin = '0' AND rocket_pin_old = '0') then
next_state <= EJECTED;
--else
-- next_state <= current_state;
--end if;
when EJECTED =>
-- Enable cutter after "sec_to_cutter_enable" from reset
if (sec_since_eject >= To_unsigned(sec_to_cutter_enable, sec_since_eject'length)) then
next_state <= CUTTER_ENABLE;
else
next_state <= current_state;
end if;
-- Enable cutter
when CUTTER_ENABLE =>
cutter_en <= '1';
next_state <= CUTTER_DISABLE;
--Disable cutter
when CUTTER_DISABLE =>
-- Disable cutter after "sec_to_cutter_disable" from reset
if (sec_since_eject >= To_unsigned(sec_cutter_enable, sec_since_eject'length)) then
cutter_en <= '0';
next_state <= SLEEP;
else
next_state <= current_state;
end if;
-- SLEEP state, do nothing
when SLEEP =>
next_state <= current_state;
-- Default go back to start
when others =>
next_state <= START;
end case;
end if;
end process main_state_machine;
end architecture_WOLF_CONTROLLER;
|
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