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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1334.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n03i01334ent IS
END c08s04b01x00p04n03i01334ent;
ARCHITECTURE c08s04b01x00p04n03i01334arch OF c08s04b01x00p04n03i01334ent IS
signal S : Bit;
BEGIN
TESTING: PROCESS
BEGIN
S <= '0' after -5 ns;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p04n03i01334 - Time expression must be positive"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n03i01334arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1334.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p04n03i01334ent IS
END c08s04b01x00p04n03i01334ent;
ARCHITECTURE c08s04b01x00p04n03i01334arch OF c08s04b01x00p04n03i01334ent IS
signal S : Bit;
BEGIN
TESTING: PROCESS
BEGIN
S <= '0' after -5 ns;
wait for 1 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p04n03i01334 - Time expression must be positive"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p04n03i01334arch;
|
-------------------------------------------------------------------------------
-- Author: David Wolf, Leonhardt Schwarz
-- Project: FPGA Project
--
-- Copyright (C) 2014 David Wolf, Leonhardt Schwarz
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.numeric_std.all;
architecture Behavioral of ioctrl is
component debounce
generic (
WIDTH : natural;
DELAY : natural);
port (
clk50 : in std_logic;
keyin_i : in std_logic_vector(WIDTH-1 downto 0);
keyout_o : out std_logic_vector(WIDTH-1 downto 0));
end component;
component decoder
port (
clk50 : in std_logic; -- Takt
cntr_i : in std_logic_vector(3 downto 0); -- Counter
ss_o : out std_logic_vector(7 downto 0)); -- Display
end component;
signal s_ff_pbsync0 : std_logic_vector(1 downto 0):= (others => '0');
signal s_ff_pbsync1 : std_logic_vector(1 downto 0):= (others => '0'); -- read here
signal s_ff_swsync0 : std_logic_vector(9 downto 0):= (others => '0');
signal s_ff_swsync1 : std_logic_vector(9 downto 0):= (others => '0'); -- read here
signal s_swsync : std_logic_vector(9 downto 0):= (others => '0');
signal s_pbsync : std_logic_vector(1 downto 0):= (others => '0');
signal s_reset_occured : std_logic := '1';
signal s_cycle_counter : integer range 0 to 100 := 0;
signal s_initial_sw : std_logic_vector(9 downto 0) := (others => '0'); -- Intialzustand für Schalter
begin
-- Entprellt die Schalter
i_sw_debouncer : debounce
generic map (
WIDTH => s_ff_swsync1'length,
DELAY => 2500)
port map (
clk50 => clk50,
keyin_i => s_ff_swsync1,
keyout_o => s_swsync);
-- Entprellt die Buttons
i_pb_debouncer : debounce
generic map (
WIDTH => s_ff_pbsync1'length,
DELAY => 2500)
port map (
clk50 => clk50,
keyin_i => s_ff_pbsync1,
keyout_o => s_pbsync);
-- Dekodiert output 0
i_decoder0 : decoder
port map (
clk50 => clk50,
cntr_i => cntr0,
ss_o => ss0_o
);
-- Dekodiert output 1
i_decoder1 : decoder
port map (
clk50 => clk50,
cntr_i => cntr1,
ss_o => ss1_o
);
-- Dekodiert output 2
i_decoder2 : decoder
port map (
clk50 => clk50,
cntr_i => cntr2,
ss_o => ss2_o
);
-- Dekodiert output 3
i_decoder3 : decoder
port map (
clk50 => clk50,
cntr_i => cntr3,
ss_o => ss3_o
);
p_synchronize : process(clk50, reset_n)
begin
if(reset_n = '0') then
s_reset_occured <= '1';
pbsync_o <= (others => '1');
swsync_o <= (others => '0');
s_ff_pbsync0 <= (others => '0');
s_ff_pbsync1 <= (others => '0');
s_ff_swsync0 <= (others => '0');
s_ff_swsync1 <= (others => '0');
s_cycle_counter <= 0;
elsif rising_edge(clk50) then
if (s_reset_occured = '1' and s_cycle_counter < 1) then
s_cycle_counter <= s_cycle_counter + 1;
s_initial_sw <= sw_i; -- Nach Reset wird der Initialzustand gespeichert.
else
s_reset_occured <= '0';
s_ff_pbsync0 <= pb_i;
s_ff_pbsync1 <= s_ff_pbsync0;
s_ff_swsync0 <= sw_i;
s_ff_swsync1 <= s_ff_swsync0;
swsync_o <= s_swsync xor s_initial_sw;
pbsync_o <= s_pbsync;
end if;
end if;
end process;
end architecture Behavioral;
|
-------------------------------------------------------------------------------
-- axi_vdma_reset
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_reset.vhd
-- Description: This entity encompasses the reset logic (soft and hard) for
-- distribution to the axi_vdma core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
entity axi_vdma_reset is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_INCLUDE_SG : integer range 0 to 1 := 0
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
);
port (
-- Clock Sources
s_axi_lite_aclk : in std_logic ; --
m_axi_sg_aclk : in std_logic ; --
prmry_axi_aclk : in std_logic ; --
prmry_axis_aclk : in std_logic ; --
--
-- Hard Reset --
axi_resetn : in std_logic ; --
--
-- Soft Reset --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
--
--
run_stop : in std_logic ; --
all_idle : in std_logic ; --
stop : in std_logic ; --
halt : out std_logic := '0' ; --
halt_cmplt : in std_logic ; --
fsize_mismatch_err : in std_logic ; -- CR591965
hrd_axi_resetn : out std_logic ; --
--
-- MM2S or S2MM Main Primary Reset (Hard and Soft) --
prmry_resetn : out std_logic := '0' ; --
-- MM2S or S2MM Main Datamover Primary Reset (RAW) (Hard and Soft) --
dm_prmry_resetn : out std_logic := '1' ; --
-- AXI Stream Reset (Hard and Soft) --
axis_resetn : out std_logic := '1' ; --
-- AXI Stream Reset Out (Hard and Soft) --
axis_reset_out_n : out std_logic ; --
-- AXI Scatter/Gather Reset (Hard and Soft) --
axi_sg_resetn : out std_logic ; --
-- AXI Scatter/Gather Reset (RAW) (Hard and Soft) --
axi_dm_sg_resetn : out std_logic --
);
end axi_vdma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant ZERO_VALUE_VECT : std_logic_vector(128 downto 0) := (others => '0');
constant SEVEN_COUNT : std_logic_vector(2 downto 0) := (others => '1');
constant FIFTEEN_COUNT : std_logic_vector(3 downto 0) := (others => '1');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Soft Reset Support
signal s_soft_reset_i : std_logic := '0';
signal s_soft_reset_i_d1 : std_logic := '0';
signal s_soft_reset_i_re : std_logic := '0';
signal assert_sftrst_d1 : std_logic := '0';
signal min_assert_sftrst : std_logic := '0';
--signal min_assert_sftrst_d1 : std_logic := '0';
signal sft_rst_dly1 : std_logic := '0';
signal sft_rst_dly2 : std_logic := '0';
signal sft_rst_dly3 : std_logic := '0';
signal sft_rst_dly4 : std_logic := '0';
signal sft_rst_dly5 : std_logic := '0';
signal sft_rst_dly6 : std_logic := '0';
signal sft_rst_dly7 : std_logic := '0';
signal sft_rst_dly8 : std_logic := '0';
signal sft_rst_dly9 : std_logic := '0';
signal sft_rst_dly10 : std_logic := '0';
signal sft_rst_dly11 : std_logic := '0';
signal sft_rst_dly12 : std_logic := '0';
signal sft_rst_dly13 : std_logic := '0';
signal sft_rst_dly14 : std_logic := '0';
signal sft_rst_dly15 : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
-- Composite reset (hard and soft)
signal resetn_i : std_logic := '1';
-- Data Mover Halt
signal halt_i : std_logic := '0';
signal halt_reset : std_logic := '0';
signal run_stop_d1 : std_logic := '0'; -- CR581004
signal run_stop_fe : std_logic := '0'; -- CR581004
-- Reset outputs
signal axis_resetn_i : std_logic := '1';
signal prmry_resetn_i : std_logic := '1';
signal axi_sg_resetn_i : std_logic := '1';
signal hrd_axi_resetn_i : std_logic := '1';
signal sg_min_assert_sftrst : std_logic := '0';
signal sg_soft_reset_re : std_logic := '0';
signal sg_all_idle : std_logic := '0';
signal lite_min_assert_sftrst : std_logic := '0';
signal lite_soft_reset_re : std_logic := '0';
signal lite_all_idle : std_logic := '0';
signal axis_min_assert_sftrst : std_logic := '0';
signal axis_soft_reset_re : std_logic := '0';
signal axis_all_idle : std_logic := '0';
-- Soft reset support
signal prmry_min_assert_sftrst : std_logic := '0';
signal p_sg_min_assert_sftrst : std_logic := '0';
signal p_lite_min_assert_sftrst : std_logic := '0';
signal p_axis_min_assert_sftrst : std_logic := '0';
signal clear_sft_rst_hold : std_logic := '0';
signal sg_clear_sft_rst_hold : std_logic := '0';
signal lite_clear_sft_rst_hold : std_logic := '0';
signal axis_clear_sft_rst_hold : std_logic := '0';
signal prmry_min_count : std_logic_vector(3 downto 0) := (others => '0');
signal sg_min_count : std_logic_vector(3 downto 0) := (others => '0');
signal lite_min_count : std_logic_vector(3 downto 0) := (others => '0');
signal axis_min_count : std_logic_vector(3 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
hrd_axi_resetn <= hrd_axi_resetn_i;
-------------------------------------------------------------------------------
-- Internal Hard Reset
-- Generate reset on hardware reset or soft reset
-------------------------------------------------------------------------------
resetn_i <= '0' when s_soft_reset_i = '1'
or min_assert_sftrst = '1'
or hrd_axi_resetn_i = '0'
else '1';
-------------------------------------------------------------------------------
-- Minimum Reset Logic for Soft Reset
-------------------------------------------------------------------------------
-- Register to generate rising edge on soft reset and falling edge
-- on reset assertion.
REG_SFTRST_FOR_RE : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
s_soft_reset_i_d1 <= s_soft_reset_i;
assert_sftrst_d1 <= min_assert_sftrst;
-- Register soft reset from DMACR to create
-- rising edge pulse
soft_reset_d1 <= soft_reset;
end if;
end process REG_SFTRST_FOR_RE;
-- rising edge pulse on internal soft reset
s_soft_reset_i_re <= s_soft_reset_i and not s_soft_reset_i_d1;
-- rising edge pulse on DMACR soft reset
soft_reset_re <= soft_reset and not soft_reset_d1;
-- falling edge detection on min soft rst to clear soft reset
-- bit in register module
soft_reset_clr <= (not min_assert_sftrst and assert_sftrst_d1)
or (not hrd_axi_resetn_i);
-------------------------------------------------------------------------------
-- Run Stop turned off by user (i.e. not an error and not a soft reset)
-------------------------------------------------------------------------------
-- CR581004 - When AXI VDMA in asynchronous mode does not come out of intial soft reset
-- Generate falling edge pulse for run_stop de-assertion
-- indicating run_stop turned off.
-- Only assert if not soft_reset and not stop (i.e. error)
REG_RUN_STOP_FE : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(resetn_i = '0' or soft_reset = '1' or stop = '1')then
run_stop_d1 <= '0';
else
run_stop_d1 <= run_stop;
end if;
end if;
end process REG_RUN_STOP_FE;
run_stop_fe <= not run_stop and run_stop_d1;
---------------------------------------------------------------------------
-- Minimum soft reset in primary domain
---------------------------------------------------------------------------
GEN_MIN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
PRMRY_MIN_RESET_ASSERTION : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(clear_sft_rst_hold = '1')then
prmry_min_count <= (others => '0');
prmry_min_assert_sftrst <= '0';
elsif(s_soft_reset_i_re = '1')then
prmry_min_count <= (others => '0');
prmry_min_assert_sftrst <= '1';
elsif(prmry_min_assert_sftrst='1' and prmry_min_count = FIFTEEN_COUNT)then
prmry_min_count <= FIFTEEN_COUNT;
prmry_min_assert_sftrst <= '1';
elsif(prmry_min_assert_sftrst='1' and all_idle = '1')then
prmry_min_count <= std_logic_vector(unsigned(prmry_min_count) + 1);
prmry_min_assert_sftrst <= '1';
end if;
end if;
end process PRMRY_MIN_RESET_ASSERTION;
---------------------------------------------------------------------------
-- Minimum soft reset in lite domain
---------------------------------------------------------------------------
---- LITE_RESET_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => s_axi_lite_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => s_soft_reset_i_re ,
---- scndry_out => lite_soft_reset_re ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
LITE_RESET_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => s_soft_reset_i_re,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '1',
scndry_out => lite_soft_reset_re,
scndry_vect_out => open
);
---- LITE_IDLE_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => s_axi_lite_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => all_idle ,
---- scndry_out => lite_all_idle ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
LITE_IDLE_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '1',
scndry_out => lite_all_idle,
scndry_vect_out => open
);
LITE_MIN_RESET_ASSERTION : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(lite_clear_sft_rst_hold = '1')then
lite_min_count <= (others => '0');
lite_min_assert_sftrst <= '0';
elsif(lite_soft_reset_re = '1')then
lite_min_count <= (others => '0');
lite_min_assert_sftrst <= '1';
elsif(lite_min_assert_sftrst='1' and lite_min_count = FIFTEEN_COUNT)then
lite_min_count <= FIFTEEN_COUNT;
lite_min_assert_sftrst <= '1';
elsif(lite_min_assert_sftrst ='1' and lite_all_idle = '1')then
lite_min_count <= std_logic_vector(unsigned(lite_min_count) + 1);
lite_min_assert_sftrst <= '1';
end if;
end if;
end process LITE_MIN_RESET_ASSERTION;
-- Cross back to primary
---- LITE_MIN_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => s_axi_lite_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => lite_min_assert_sftrst ,
---- prmry_out => p_lite_min_assert_sftrst ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
LITE_MIN_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '1',
prmry_in => lite_min_assert_sftrst,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axi_aclk,
scndry_resetn => '1',
scndry_out => p_lite_min_assert_sftrst,
scndry_vect_out => open
);
---- LITE_CLR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => s_axi_lite_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => clear_sft_rst_hold ,
---- scndry_out => lite_clear_sft_rst_hold ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
LITE_CLR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => clear_sft_rst_hold,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '1',
scndry_out => lite_clear_sft_rst_hold,
scndry_vect_out => open
);
---------------------------------------------------------------------------
-- Minimum soft reset in axis domain
---------------------------------------------------------------------------
---- AXIS_RESET_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => prmry_axis_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => s_soft_reset_i_re ,
---- scndry_out => axis_soft_reset_re ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
AXIS_RESET_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => s_soft_reset_i_re,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axis_aclk,
scndry_resetn => '1',
scndry_out => axis_soft_reset_re,
scndry_vect_out => open
);
---- AXIS_IDLE_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => prmry_axis_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => all_idle ,
---- scndry_out => axis_all_idle ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
AXIS_IDLE_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axis_aclk,
scndry_resetn => '1',
scndry_out => axis_all_idle,
scndry_vect_out => open
);
AXIS_MIN_RESET_ASSERTION : process(prmry_axis_aclk)
begin
if(prmry_axis_aclk'EVENT and prmry_axis_aclk = '1')then
if(axis_clear_sft_rst_hold = '1')then
axis_min_count <= (others => '0');
axis_min_assert_sftrst <= '0';
elsif(axis_soft_reset_re = '1')then
axis_min_count <= (others => '0');
axis_min_assert_sftrst <= '1';
elsif(axis_min_assert_sftrst='1' and axis_min_count = FIFTEEN_COUNT)then
axis_min_count <= FIFTEEN_COUNT;
axis_min_assert_sftrst <= '1';
elsif(axis_min_assert_sftrst ='1' and axis_all_idle = '1')then
axis_min_count <= std_logic_vector(unsigned(axis_min_count) + 1);
axis_min_assert_sftrst <= '1';
end if;
end if;
end process AXIS_MIN_RESET_ASSERTION;
-- Cross back to primary
---- AXIS_MIN_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => prmry_axis_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => axis_min_assert_sftrst ,
---- prmry_out => p_axis_min_assert_sftrst ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
AXIS_MIN_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axis_aclk,
prmry_resetn => '1',
prmry_in => axis_min_assert_sftrst,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axi_aclk,
scndry_resetn => '1',
scndry_out => p_axis_min_assert_sftrst,
scndry_vect_out => open
);
---- AXIS_CLR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => prmry_axis_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => clear_sft_rst_hold ,
---- scndry_out => axis_clear_sft_rst_hold ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
AXIS_CLR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => clear_sft_rst_hold,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axis_aclk,
scndry_resetn => '1',
scndry_out => axis_clear_sft_rst_hold,
scndry_vect_out => open
);
---------------------------------------------------------------------------
-- Minimum soft reset in sg domain
---------------------------------------------------------------------------
GEN_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
---- SG_RESET_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => m_axi_sg_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => s_soft_reset_i_re ,
---- scndry_out => sg_soft_reset_re ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
SG_RESET_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => s_soft_reset_i_re,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '1',
scndry_out => sg_soft_reset_re,
scndry_vect_out => open
);
---- SG_IDLE_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => m_axi_sg_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => all_idle ,
---- scndry_out => sg_all_idle ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
SG_IDLE_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '1',
scndry_out => sg_all_idle,
scndry_vect_out => open
);
SG_MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_clear_sft_rst_hold = '1')then
sg_min_count <= (others => '0');
sg_min_assert_sftrst <= '0';
elsif(sg_soft_reset_re = '1')then
sg_min_count <= (others => '0');
sg_min_assert_sftrst <= '1';
elsif(sg_min_assert_sftrst='1' and sg_min_count = FIFTEEN_COUNT)then
sg_min_count <= FIFTEEN_COUNT;
sg_min_assert_sftrst <= '1';
elsif(sg_min_assert_sftrst ='1' and sg_all_idle = '1')then
sg_min_count <= std_logic_vector(unsigned(sg_min_count) + 1);
sg_min_assert_sftrst <= '1';
end if;
end if;
end process SG_MIN_RESET_ASSERTION;
-- Cross back to primary
---- SG_MIN_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => m_axi_sg_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => sg_min_assert_sftrst ,
---- prmry_out => p_sg_min_assert_sftrst ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
SG_MIN_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axi_sg_aclk,
prmry_resetn => '1',
prmry_in => sg_min_assert_sftrst,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axi_aclk,
scndry_resetn => '1',
scndry_out => p_sg_min_assert_sftrst,
scndry_vect_out => open
);
---- SG_CLR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => m_axi_sg_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => clear_sft_rst_hold ,
---- scndry_out => sg_clear_sft_rst_hold ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
SG_CLR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => clear_sft_rst_hold,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '1',
scndry_out => sg_clear_sft_rst_hold,
scndry_vect_out => open
);
clear_sft_rst_hold <= prmry_min_assert_sftrst
and p_sg_min_assert_sftrst
and p_lite_min_assert_sftrst
and p_axis_min_assert_sftrst;
-- Assert minimum soft reset.
REG_MIN_SFTRST : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(s_soft_reset_i_re='1')then
min_assert_sftrst <= '1';
elsif(min_assert_sftrst = '1'
and prmry_min_assert_sftrst = '0'
and p_sg_min_assert_sftrst = '0'
and p_lite_min_assert_sftrst = '0'
and p_axis_min_assert_sftrst = '0')then
min_assert_sftrst <= '0';
end if;
end if;
end process REG_MIN_SFTRST;
end generate GEN_FOR_SG;
-- No SG so do not look at sg_min_assert signal
GEN_FOR_NO_SG : if C_INCLUDE_SG = 0 generate
begin
clear_sft_rst_hold <= prmry_min_assert_sftrst
and p_lite_min_assert_sftrst
and p_axis_min_assert_sftrst;
-- Assert minimum soft reset.
REG_MIN_SFTRST : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(s_soft_reset_i_re='1')then
min_assert_sftrst <= '1';
elsif(min_assert_sftrst = '1'
and prmry_min_assert_sftrst = '0'
and p_lite_min_assert_sftrst = '0'
and p_axis_min_assert_sftrst = '0')then
min_assert_sftrst <= '0';
end if;
end if;
end process REG_MIN_SFTRST;
end generate GEN_FOR_NO_SG;
end generate GEN_MIN_FOR_ASYNC;
GEN_MIN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- On start of soft reset shift pulse through to assert
-- 15 clock later. Used to set minimum 16clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 16 clocks.
PRMRY_MIN_RESET_ASSERTION : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly15 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process PRMRY_MIN_RESET_ASSERTION;
end generate GEN_MIN_FOR_SYNC;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
-- On soft reset or error
-- mm2s dma controller will idle immediatly
-- sg fetch engine will complete current task and idle (desc's will flush)
-- sg update engine will update all completed descriptors then idle
REG_SOFT_RESET : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1' and (halt_cmplt = '1' or halt_reset = '1'))then
s_soft_reset_i <= '1';
else
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(resetn_i = '0')then
halt_i <= '0';
-- CR581004 - When AXI VDMA in asynchronous mode does not come out of intial soft reset
-- Soft reset or error or turned off therefore issue halt to datamover
--elsif(soft_reset_re = '1' or stop = '1' or run_stop = '0')then
--elsif(soft_reset_re = '1' or stop = '1' or run_stop_fe = '1')then
--
-- CR591965 need to halt and reset data mover on frame size mismatch inorder to correctly
-- flush out datamover and prep for starting up again on next frame sync. This is really
-- only needed for flush on frame sync mode. Signal is redundant in non-flush on frame sync mode
elsif(soft_reset_re = '1' or stop = '1' or run_stop_fe = '1' or fsize_mismatch_err = '1')then
halt_i <= '1';
-- If halt due to turn off then clear on halt reset else will
-- clear once resetn_i asserts for soft reset
--elsif(halt_reset = '1' and stop = '0' and run_stop = '1')then
elsif(halt_reset = '1' and stop = '0' and run_stop = '1')then
halt_i <= '0';
end if;
end if;
end process REG_DM_HALT;
-- Halt To DataMover
halt <= halt_i;
-- AXI Stream reset output
--REG_AXIS_RESET_OUT : process(prmry_axi_aclk)
-- begin
-- if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
-- axis_resetn_i <= resetn_i and not s_soft_reset_i;
-- end if;
-- end process REG_AXIS_RESET_OUT;
-- Registered primary and secondary resets out
REG_RESET_OUT : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
prmry_resetn_i <= resetn_i;
end if;
end process REG_RESET_OUT;
-- Issue hard reset to DM on halt completed
-- specifically for when run_stop is cleared in DMACR
-- Note: If soft_reset then do not issue halt_reset because this will
-- terminate the halt_cmplt too soon and it will not get captured
-- by soft_reset process above. Reset to dm will occur
-- based on resetn_i for the soft_reset case.
HRDRST_DM : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
--CR574564 - on hard reset p_halt de-asserted before halt_cmplt thus
-- halt_reset never asserted causing a system hang
--if(halt_cmplt = '1' and run_stop = '0' and soft_reset = '0')then
-- CR581004 - When AXI VDMA in asynchronous mode does not come out of intial soft reset
--if(halt_cmplt = '1' and halt_i = '1' and soft_reset = '0')then
if(halt_cmplt = '1' and halt_i = '1' and soft_reset = '0' and stop = '0')then
halt_reset <= '1';
elsif(halt_reset = '1' and run_stop = '1')then
halt_reset <= '0';
end if;
end if;
end process HRDRST_DM;
-- System is asynchronous therefore use CDC module to cross
-- resets to appropriate clock domain
GEN_RESET_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Cross top level hard reset in from axi_lite to primary (mm2s or s2mm)
---- HARD_RESET_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => s_axi_lite_aclk ,
---- prmry_resetn => '1' ,
----
---- scndry_aclk => prmry_axi_aclk ,
---- scndry_resetn => '1' ,
----
---- -- Secondary to Primary Clock Crossing
---- scndry_in => '0' ,
---- prmry_out => open ,
----
---- -- Primary to Secondary Clock Crossing
---- prmry_in => axi_resetn ,
---- scndry_out => hrd_axi_resetn_i ,
----
---- -- Secondary Vector to Primary Vector Clock Crossing
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
----
---- -- Primary Vector to Secondary Vector Clock Crossing
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
----
---- );
----
HARD_RESET_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '1',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axi_aclk,
scndry_resetn => '1',
scndry_out => hrd_axi_resetn_i,
scndry_vect_out => open
);
-- AXI DataMover Primary Reset (Raw) and primary logic reset
dm_prmry_resetn <= resetn_i and not halt_reset;
prmry_resetn <= prmry_resetn_i;
-- Scatter Gather Mode
GEN_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
-- AXI_SG_RESET_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
-- generic map(
-- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
-- C_VECTOR_WIDTH => 1
-- )
-- port map(
-- prmry_aclk => prmry_axi_aclk ,
-- prmry_resetn => '1' ,
--
-- scndry_aclk => m_axi_sg_aclk ,
-- scndry_resetn => '1' ,
--
-- -- Secondary to Primary Clock Crossing
-- scndry_in => '0' ,
-- prmry_out => open ,
--
-- -- Primary to Secondary Clock Crossing
-- prmry_in => resetn_i ,
-- scndry_out => axi_sg_resetn_i ,
--
-- -- Secondary Vector to Primary Vector Clock Crossing
-- scndry_vect_s_h => '0' ,
-- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
-- prmry_vect_out => open ,
--
-- -- Primary Vector to Secondary Vector Clock Crossing
-- prmry_vect_s_h => '0' ,
-- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
-- scndry_vect_out => open
--
-- );
--
AXI_SG_RESET_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => resetn_i,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '1',
scndry_out => axi_sg_resetn_i,
scndry_vect_out => open
);
-- Scatter Gather Datamover and Logic Reset
axi_dm_sg_resetn <= axi_sg_resetn_i;
axi_sg_resetn <= axi_sg_resetn_i;
end generate GEN_FOR_SG;
-- Register Direct Mode
GEN_FOR_NO_SG : if C_INCLUDE_SG = 0 generate
axi_dm_sg_resetn <= '1';
axi_sg_resetn <= '1';
end generate GEN_FOR_NO_SG;
---- AXIS_RESET_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
----
---- scndry_aclk => prmry_axis_aclk ,
---- scndry_resetn => '1' ,
----
---- -- Secondary to Primary Clock Crossing
---- scndry_in => '0' ,
---- prmry_out => open ,
----
---- -- Primary to Secondary Clock Crossing
---- prmry_in => resetn_i ,
---- scndry_out => axis_resetn_i ,
----
---- -- Secondary Vector to Primary Vector Clock Crossing
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
----
---- -- Primary Vector to Secondary Vector Clock Crossing
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
----
---- );
AXIS_RESET_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => resetn_i,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axis_aclk,
scndry_resetn => '1',
scndry_out => axis_resetn_i,
scndry_vect_out => open
);
-- AXIS (MM2S or S2MM) logic reset and reset out
axis_resetn <= axis_resetn_i;
axis_reset_out_n <= axis_resetn_i;
end generate GEN_RESET_FOR_ASYNC;
-- System is synchronous therefore map internal resets to all
-- reset outputs
GEN_RESET_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- Hard reset in
hrd_axi_resetn_i <= axi_resetn;
-- AXI DataMover Primary Reset (Raw) and primary logic reset
prmry_resetn <= prmry_resetn_i;
dm_prmry_resetn <= resetn_i and not halt_reset;
-- Scatter Gather Mode
GEN_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
-- Scatter Gather Engine Reset
axi_sg_resetn <= prmry_resetn_i;
axi_dm_sg_resetn <= resetn_i;
end generate GEN_FOR_SG;
-- Register Direct Mode
GEN_FOR_NO_SG : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather Engine Reset
axi_sg_resetn <= '1';
axi_dm_sg_resetn <= '1';
end generate GEN_FOR_NO_SG;
-- AXIS (MM2S or S2MM) logic reset and reset out
axis_resetn <= prmry_resetn_i;
axis_reset_out_n <= prmry_resetn_i;
end generate GEN_RESET_FOR_SYNC;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_reset
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_reset.vhd
-- Description: This entity encompasses the reset logic (soft and hard) for
-- distribution to the axi_vdma core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
entity axi_vdma_reset is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_INCLUDE_SG : integer range 0 to 1 := 0
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
);
port (
-- Clock Sources
s_axi_lite_aclk : in std_logic ; --
m_axi_sg_aclk : in std_logic ; --
prmry_axi_aclk : in std_logic ; --
prmry_axis_aclk : in std_logic ; --
--
-- Hard Reset --
axi_resetn : in std_logic ; --
--
-- Soft Reset --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
--
--
run_stop : in std_logic ; --
all_idle : in std_logic ; --
stop : in std_logic ; --
halt : out std_logic := '0' ; --
halt_cmplt : in std_logic ; --
fsize_mismatch_err : in std_logic ; -- CR591965
hrd_axi_resetn : out std_logic ; --
--
-- MM2S or S2MM Main Primary Reset (Hard and Soft) --
prmry_resetn : out std_logic := '0' ; --
-- MM2S or S2MM Main Datamover Primary Reset (RAW) (Hard and Soft) --
dm_prmry_resetn : out std_logic := '1' ; --
-- AXI Stream Reset (Hard and Soft) --
axis_resetn : out std_logic := '1' ; --
-- AXI Stream Reset Out (Hard and Soft) --
axis_reset_out_n : out std_logic ; --
-- AXI Scatter/Gather Reset (Hard and Soft) --
axi_sg_resetn : out std_logic ; --
-- AXI Scatter/Gather Reset (RAW) (Hard and Soft) --
axi_dm_sg_resetn : out std_logic --
);
end axi_vdma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant ZERO_VALUE_VECT : std_logic_vector(128 downto 0) := (others => '0');
constant SEVEN_COUNT : std_logic_vector(2 downto 0) := (others => '1');
constant FIFTEEN_COUNT : std_logic_vector(3 downto 0) := (others => '1');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Soft Reset Support
signal s_soft_reset_i : std_logic := '0';
signal s_soft_reset_i_d1 : std_logic := '0';
signal s_soft_reset_i_re : std_logic := '0';
signal assert_sftrst_d1 : std_logic := '0';
signal min_assert_sftrst : std_logic := '0';
--signal min_assert_sftrst_d1 : std_logic := '0';
signal sft_rst_dly1 : std_logic := '0';
signal sft_rst_dly2 : std_logic := '0';
signal sft_rst_dly3 : std_logic := '0';
signal sft_rst_dly4 : std_logic := '0';
signal sft_rst_dly5 : std_logic := '0';
signal sft_rst_dly6 : std_logic := '0';
signal sft_rst_dly7 : std_logic := '0';
signal sft_rst_dly8 : std_logic := '0';
signal sft_rst_dly9 : std_logic := '0';
signal sft_rst_dly10 : std_logic := '0';
signal sft_rst_dly11 : std_logic := '0';
signal sft_rst_dly12 : std_logic := '0';
signal sft_rst_dly13 : std_logic := '0';
signal sft_rst_dly14 : std_logic := '0';
signal sft_rst_dly15 : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
-- Composite reset (hard and soft)
signal resetn_i : std_logic := '1';
-- Data Mover Halt
signal halt_i : std_logic := '0';
signal halt_reset : std_logic := '0';
signal run_stop_d1 : std_logic := '0'; -- CR581004
signal run_stop_fe : std_logic := '0'; -- CR581004
-- Reset outputs
signal axis_resetn_i : std_logic := '1';
signal prmry_resetn_i : std_logic := '1';
signal axi_sg_resetn_i : std_logic := '1';
signal hrd_axi_resetn_i : std_logic := '1';
signal sg_min_assert_sftrst : std_logic := '0';
signal sg_soft_reset_re : std_logic := '0';
signal sg_all_idle : std_logic := '0';
signal lite_min_assert_sftrst : std_logic := '0';
signal lite_soft_reset_re : std_logic := '0';
signal lite_all_idle : std_logic := '0';
signal axis_min_assert_sftrst : std_logic := '0';
signal axis_soft_reset_re : std_logic := '0';
signal axis_all_idle : std_logic := '0';
-- Soft reset support
signal prmry_min_assert_sftrst : std_logic := '0';
signal p_sg_min_assert_sftrst : std_logic := '0';
signal p_lite_min_assert_sftrst : std_logic := '0';
signal p_axis_min_assert_sftrst : std_logic := '0';
signal clear_sft_rst_hold : std_logic := '0';
signal sg_clear_sft_rst_hold : std_logic := '0';
signal lite_clear_sft_rst_hold : std_logic := '0';
signal axis_clear_sft_rst_hold : std_logic := '0';
signal prmry_min_count : std_logic_vector(3 downto 0) := (others => '0');
signal sg_min_count : std_logic_vector(3 downto 0) := (others => '0');
signal lite_min_count : std_logic_vector(3 downto 0) := (others => '0');
signal axis_min_count : std_logic_vector(3 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
hrd_axi_resetn <= hrd_axi_resetn_i;
-------------------------------------------------------------------------------
-- Internal Hard Reset
-- Generate reset on hardware reset or soft reset
-------------------------------------------------------------------------------
resetn_i <= '0' when s_soft_reset_i = '1'
or min_assert_sftrst = '1'
or hrd_axi_resetn_i = '0'
else '1';
-------------------------------------------------------------------------------
-- Minimum Reset Logic for Soft Reset
-------------------------------------------------------------------------------
-- Register to generate rising edge on soft reset and falling edge
-- on reset assertion.
REG_SFTRST_FOR_RE : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
s_soft_reset_i_d1 <= s_soft_reset_i;
assert_sftrst_d1 <= min_assert_sftrst;
-- Register soft reset from DMACR to create
-- rising edge pulse
soft_reset_d1 <= soft_reset;
end if;
end process REG_SFTRST_FOR_RE;
-- rising edge pulse on internal soft reset
s_soft_reset_i_re <= s_soft_reset_i and not s_soft_reset_i_d1;
-- rising edge pulse on DMACR soft reset
soft_reset_re <= soft_reset and not soft_reset_d1;
-- falling edge detection on min soft rst to clear soft reset
-- bit in register module
soft_reset_clr <= (not min_assert_sftrst and assert_sftrst_d1)
or (not hrd_axi_resetn_i);
-------------------------------------------------------------------------------
-- Run Stop turned off by user (i.e. not an error and not a soft reset)
-------------------------------------------------------------------------------
-- CR581004 - When AXI VDMA in asynchronous mode does not come out of intial soft reset
-- Generate falling edge pulse for run_stop de-assertion
-- indicating run_stop turned off.
-- Only assert if not soft_reset and not stop (i.e. error)
REG_RUN_STOP_FE : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(resetn_i = '0' or soft_reset = '1' or stop = '1')then
run_stop_d1 <= '0';
else
run_stop_d1 <= run_stop;
end if;
end if;
end process REG_RUN_STOP_FE;
run_stop_fe <= not run_stop and run_stop_d1;
---------------------------------------------------------------------------
-- Minimum soft reset in primary domain
---------------------------------------------------------------------------
GEN_MIN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
PRMRY_MIN_RESET_ASSERTION : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(clear_sft_rst_hold = '1')then
prmry_min_count <= (others => '0');
prmry_min_assert_sftrst <= '0';
elsif(s_soft_reset_i_re = '1')then
prmry_min_count <= (others => '0');
prmry_min_assert_sftrst <= '1';
elsif(prmry_min_assert_sftrst='1' and prmry_min_count = FIFTEEN_COUNT)then
prmry_min_count <= FIFTEEN_COUNT;
prmry_min_assert_sftrst <= '1';
elsif(prmry_min_assert_sftrst='1' and all_idle = '1')then
prmry_min_count <= std_logic_vector(unsigned(prmry_min_count) + 1);
prmry_min_assert_sftrst <= '1';
end if;
end if;
end process PRMRY_MIN_RESET_ASSERTION;
---------------------------------------------------------------------------
-- Minimum soft reset in lite domain
---------------------------------------------------------------------------
---- LITE_RESET_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => s_axi_lite_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => s_soft_reset_i_re ,
---- scndry_out => lite_soft_reset_re ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
LITE_RESET_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => s_soft_reset_i_re,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '1',
scndry_out => lite_soft_reset_re,
scndry_vect_out => open
);
---- LITE_IDLE_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => s_axi_lite_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => all_idle ,
---- scndry_out => lite_all_idle ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
LITE_IDLE_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '1',
scndry_out => lite_all_idle,
scndry_vect_out => open
);
LITE_MIN_RESET_ASSERTION : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(lite_clear_sft_rst_hold = '1')then
lite_min_count <= (others => '0');
lite_min_assert_sftrst <= '0';
elsif(lite_soft_reset_re = '1')then
lite_min_count <= (others => '0');
lite_min_assert_sftrst <= '1';
elsif(lite_min_assert_sftrst='1' and lite_min_count = FIFTEEN_COUNT)then
lite_min_count <= FIFTEEN_COUNT;
lite_min_assert_sftrst <= '1';
elsif(lite_min_assert_sftrst ='1' and lite_all_idle = '1')then
lite_min_count <= std_logic_vector(unsigned(lite_min_count) + 1);
lite_min_assert_sftrst <= '1';
end if;
end if;
end process LITE_MIN_RESET_ASSERTION;
-- Cross back to primary
---- LITE_MIN_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => s_axi_lite_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => lite_min_assert_sftrst ,
---- prmry_out => p_lite_min_assert_sftrst ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
LITE_MIN_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '1',
prmry_in => lite_min_assert_sftrst,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axi_aclk,
scndry_resetn => '1',
scndry_out => p_lite_min_assert_sftrst,
scndry_vect_out => open
);
---- LITE_CLR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => s_axi_lite_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => clear_sft_rst_hold ,
---- scndry_out => lite_clear_sft_rst_hold ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
LITE_CLR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => clear_sft_rst_hold,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '1',
scndry_out => lite_clear_sft_rst_hold,
scndry_vect_out => open
);
---------------------------------------------------------------------------
-- Minimum soft reset in axis domain
---------------------------------------------------------------------------
---- AXIS_RESET_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => prmry_axis_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => s_soft_reset_i_re ,
---- scndry_out => axis_soft_reset_re ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
AXIS_RESET_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => s_soft_reset_i_re,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axis_aclk,
scndry_resetn => '1',
scndry_out => axis_soft_reset_re,
scndry_vect_out => open
);
---- AXIS_IDLE_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => prmry_axis_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => all_idle ,
---- scndry_out => axis_all_idle ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
AXIS_IDLE_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axis_aclk,
scndry_resetn => '1',
scndry_out => axis_all_idle,
scndry_vect_out => open
);
AXIS_MIN_RESET_ASSERTION : process(prmry_axis_aclk)
begin
if(prmry_axis_aclk'EVENT and prmry_axis_aclk = '1')then
if(axis_clear_sft_rst_hold = '1')then
axis_min_count <= (others => '0');
axis_min_assert_sftrst <= '0';
elsif(axis_soft_reset_re = '1')then
axis_min_count <= (others => '0');
axis_min_assert_sftrst <= '1';
elsif(axis_min_assert_sftrst='1' and axis_min_count = FIFTEEN_COUNT)then
axis_min_count <= FIFTEEN_COUNT;
axis_min_assert_sftrst <= '1';
elsif(axis_min_assert_sftrst ='1' and axis_all_idle = '1')then
axis_min_count <= std_logic_vector(unsigned(axis_min_count) + 1);
axis_min_assert_sftrst <= '1';
end if;
end if;
end process AXIS_MIN_RESET_ASSERTION;
-- Cross back to primary
---- AXIS_MIN_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => prmry_axis_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => axis_min_assert_sftrst ,
---- prmry_out => p_axis_min_assert_sftrst ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
AXIS_MIN_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axis_aclk,
prmry_resetn => '1',
prmry_in => axis_min_assert_sftrst,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axi_aclk,
scndry_resetn => '1',
scndry_out => p_axis_min_assert_sftrst,
scndry_vect_out => open
);
---- AXIS_CLR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => prmry_axis_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => clear_sft_rst_hold ,
---- scndry_out => axis_clear_sft_rst_hold ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
AXIS_CLR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => clear_sft_rst_hold,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axis_aclk,
scndry_resetn => '1',
scndry_out => axis_clear_sft_rst_hold,
scndry_vect_out => open
);
---------------------------------------------------------------------------
-- Minimum soft reset in sg domain
---------------------------------------------------------------------------
GEN_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
---- SG_RESET_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => m_axi_sg_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => s_soft_reset_i_re ,
---- scndry_out => sg_soft_reset_re ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
SG_RESET_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => s_soft_reset_i_re,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '1',
scndry_out => sg_soft_reset_re,
scndry_vect_out => open
);
---- SG_IDLE_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => m_axi_sg_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => all_idle ,
---- scndry_out => sg_all_idle ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
SG_IDLE_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '1',
scndry_out => sg_all_idle,
scndry_vect_out => open
);
SG_MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_clear_sft_rst_hold = '1')then
sg_min_count <= (others => '0');
sg_min_assert_sftrst <= '0';
elsif(sg_soft_reset_re = '1')then
sg_min_count <= (others => '0');
sg_min_assert_sftrst <= '1';
elsif(sg_min_assert_sftrst='1' and sg_min_count = FIFTEEN_COUNT)then
sg_min_count <= FIFTEEN_COUNT;
sg_min_assert_sftrst <= '1';
elsif(sg_min_assert_sftrst ='1' and sg_all_idle = '1')then
sg_min_count <= std_logic_vector(unsigned(sg_min_count) + 1);
sg_min_assert_sftrst <= '1';
end if;
end if;
end process SG_MIN_RESET_ASSERTION;
-- Cross back to primary
---- SG_MIN_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => m_axi_sg_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => sg_min_assert_sftrst ,
---- prmry_out => p_sg_min_assert_sftrst ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
SG_MIN_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axi_sg_aclk,
prmry_resetn => '1',
prmry_in => sg_min_assert_sftrst,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axi_aclk,
scndry_resetn => '1',
scndry_out => p_sg_min_assert_sftrst,
scndry_vect_out => open
);
---- SG_CLR_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
---- scndry_aclk => m_axi_sg_aclk ,
---- scndry_resetn => '1' ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => clear_sft_rst_hold ,
---- scndry_out => sg_clear_sft_rst_hold ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
SG_CLR_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => clear_sft_rst_hold,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '1',
scndry_out => sg_clear_sft_rst_hold,
scndry_vect_out => open
);
clear_sft_rst_hold <= prmry_min_assert_sftrst
and p_sg_min_assert_sftrst
and p_lite_min_assert_sftrst
and p_axis_min_assert_sftrst;
-- Assert minimum soft reset.
REG_MIN_SFTRST : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(s_soft_reset_i_re='1')then
min_assert_sftrst <= '1';
elsif(min_assert_sftrst = '1'
and prmry_min_assert_sftrst = '0'
and p_sg_min_assert_sftrst = '0'
and p_lite_min_assert_sftrst = '0'
and p_axis_min_assert_sftrst = '0')then
min_assert_sftrst <= '0';
end if;
end if;
end process REG_MIN_SFTRST;
end generate GEN_FOR_SG;
-- No SG so do not look at sg_min_assert signal
GEN_FOR_NO_SG : if C_INCLUDE_SG = 0 generate
begin
clear_sft_rst_hold <= prmry_min_assert_sftrst
and p_lite_min_assert_sftrst
and p_axis_min_assert_sftrst;
-- Assert minimum soft reset.
REG_MIN_SFTRST : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(s_soft_reset_i_re='1')then
min_assert_sftrst <= '1';
elsif(min_assert_sftrst = '1'
and prmry_min_assert_sftrst = '0'
and p_lite_min_assert_sftrst = '0'
and p_axis_min_assert_sftrst = '0')then
min_assert_sftrst <= '0';
end if;
end if;
end process REG_MIN_SFTRST;
end generate GEN_FOR_NO_SG;
end generate GEN_MIN_FOR_ASYNC;
GEN_MIN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- On start of soft reset shift pulse through to assert
-- 15 clock later. Used to set minimum 16clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 16 clocks.
PRMRY_MIN_RESET_ASSERTION : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly15 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process PRMRY_MIN_RESET_ASSERTION;
end generate GEN_MIN_FOR_SYNC;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
-- On soft reset or error
-- mm2s dma controller will idle immediatly
-- sg fetch engine will complete current task and idle (desc's will flush)
-- sg update engine will update all completed descriptors then idle
REG_SOFT_RESET : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1' and (halt_cmplt = '1' or halt_reset = '1'))then
s_soft_reset_i <= '1';
else
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
if(resetn_i = '0')then
halt_i <= '0';
-- CR581004 - When AXI VDMA in asynchronous mode does not come out of intial soft reset
-- Soft reset or error or turned off therefore issue halt to datamover
--elsif(soft_reset_re = '1' or stop = '1' or run_stop = '0')then
--elsif(soft_reset_re = '1' or stop = '1' or run_stop_fe = '1')then
--
-- CR591965 need to halt and reset data mover on frame size mismatch inorder to correctly
-- flush out datamover and prep for starting up again on next frame sync. This is really
-- only needed for flush on frame sync mode. Signal is redundant in non-flush on frame sync mode
elsif(soft_reset_re = '1' or stop = '1' or run_stop_fe = '1' or fsize_mismatch_err = '1')then
halt_i <= '1';
-- If halt due to turn off then clear on halt reset else will
-- clear once resetn_i asserts for soft reset
--elsif(halt_reset = '1' and stop = '0' and run_stop = '1')then
elsif(halt_reset = '1' and stop = '0' and run_stop = '1')then
halt_i <= '0';
end if;
end if;
end process REG_DM_HALT;
-- Halt To DataMover
halt <= halt_i;
-- AXI Stream reset output
--REG_AXIS_RESET_OUT : process(prmry_axi_aclk)
-- begin
-- if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
-- axis_resetn_i <= resetn_i and not s_soft_reset_i;
-- end if;
-- end process REG_AXIS_RESET_OUT;
-- Registered primary and secondary resets out
REG_RESET_OUT : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
prmry_resetn_i <= resetn_i;
end if;
end process REG_RESET_OUT;
-- Issue hard reset to DM on halt completed
-- specifically for when run_stop is cleared in DMACR
-- Note: If soft_reset then do not issue halt_reset because this will
-- terminate the halt_cmplt too soon and it will not get captured
-- by soft_reset process above. Reset to dm will occur
-- based on resetn_i for the soft_reset case.
HRDRST_DM : process(prmry_axi_aclk)
begin
if(prmry_axi_aclk'EVENT and prmry_axi_aclk = '1')then
--CR574564 - on hard reset p_halt de-asserted before halt_cmplt thus
-- halt_reset never asserted causing a system hang
--if(halt_cmplt = '1' and run_stop = '0' and soft_reset = '0')then
-- CR581004 - When AXI VDMA in asynchronous mode does not come out of intial soft reset
--if(halt_cmplt = '1' and halt_i = '1' and soft_reset = '0')then
if(halt_cmplt = '1' and halt_i = '1' and soft_reset = '0' and stop = '0')then
halt_reset <= '1';
elsif(halt_reset = '1' and run_stop = '1')then
halt_reset <= '0';
end if;
end if;
end process HRDRST_DM;
-- System is asynchronous therefore use CDC module to cross
-- resets to appropriate clock domain
GEN_RESET_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Cross top level hard reset in from axi_lite to primary (mm2s or s2mm)
---- HARD_RESET_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => s_axi_lite_aclk ,
---- prmry_resetn => '1' ,
----
---- scndry_aclk => prmry_axi_aclk ,
---- scndry_resetn => '1' ,
----
---- -- Secondary to Primary Clock Crossing
---- scndry_in => '0' ,
---- prmry_out => open ,
----
---- -- Primary to Secondary Clock Crossing
---- prmry_in => axi_resetn ,
---- scndry_out => hrd_axi_resetn_i ,
----
---- -- Secondary Vector to Primary Vector Clock Crossing
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
----
---- -- Primary Vector to Secondary Vector Clock Crossing
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
----
---- );
----
HARD_RESET_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '1',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axi_aclk,
scndry_resetn => '1',
scndry_out => hrd_axi_resetn_i,
scndry_vect_out => open
);
-- AXI DataMover Primary Reset (Raw) and primary logic reset
dm_prmry_resetn <= resetn_i and not halt_reset;
prmry_resetn <= prmry_resetn_i;
-- Scatter Gather Mode
GEN_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
-- AXI_SG_RESET_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
-- generic map(
-- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
-- C_VECTOR_WIDTH => 1
-- )
-- port map(
-- prmry_aclk => prmry_axi_aclk ,
-- prmry_resetn => '1' ,
--
-- scndry_aclk => m_axi_sg_aclk ,
-- scndry_resetn => '1' ,
--
-- -- Secondary to Primary Clock Crossing
-- scndry_in => '0' ,
-- prmry_out => open ,
--
-- -- Primary to Secondary Clock Crossing
-- prmry_in => resetn_i ,
-- scndry_out => axi_sg_resetn_i ,
--
-- -- Secondary Vector to Primary Vector Clock Crossing
-- scndry_vect_s_h => '0' ,
-- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
-- prmry_vect_out => open ,
--
-- -- Primary Vector to Secondary Vector Clock Crossing
-- prmry_vect_s_h => '0' ,
-- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
-- scndry_vect_out => open
--
-- );
--
AXI_SG_RESET_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => resetn_i,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '1',
scndry_out => axi_sg_resetn_i,
scndry_vect_out => open
);
-- Scatter Gather Datamover and Logic Reset
axi_dm_sg_resetn <= axi_sg_resetn_i;
axi_sg_resetn <= axi_sg_resetn_i;
end generate GEN_FOR_SG;
-- Register Direct Mode
GEN_FOR_NO_SG : if C_INCLUDE_SG = 0 generate
axi_dm_sg_resetn <= '1';
axi_sg_resetn <= '1';
end generate GEN_FOR_NO_SG;
---- AXIS_RESET_CDC_I : entity axi_vdma_v6_2.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S_NO_RST ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map(
---- prmry_aclk => prmry_axi_aclk ,
---- prmry_resetn => '1' ,
----
---- scndry_aclk => prmry_axis_aclk ,
---- scndry_resetn => '1' ,
----
---- -- Secondary to Primary Clock Crossing
---- scndry_in => '0' ,
---- prmry_out => open ,
----
---- -- Primary to Secondary Clock Crossing
---- prmry_in => resetn_i ,
---- scndry_out => axis_resetn_i ,
----
---- -- Secondary Vector to Primary Vector Clock Crossing
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- prmry_vect_out => open ,
----
---- -- Primary Vector to Secondary Vector Clock Crossing
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
----
---- );
AXIS_RESET_CDC_I : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => prmry_axi_aclk,
prmry_resetn => '1',
prmry_in => resetn_i,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => prmry_axis_aclk,
scndry_resetn => '1',
scndry_out => axis_resetn_i,
scndry_vect_out => open
);
-- AXIS (MM2S or S2MM) logic reset and reset out
axis_resetn <= axis_resetn_i;
axis_reset_out_n <= axis_resetn_i;
end generate GEN_RESET_FOR_ASYNC;
-- System is synchronous therefore map internal resets to all
-- reset outputs
GEN_RESET_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- Hard reset in
hrd_axi_resetn_i <= axi_resetn;
-- AXI DataMover Primary Reset (Raw) and primary logic reset
prmry_resetn <= prmry_resetn_i;
dm_prmry_resetn <= resetn_i and not halt_reset;
-- Scatter Gather Mode
GEN_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
-- Scatter Gather Engine Reset
axi_sg_resetn <= prmry_resetn_i;
axi_dm_sg_resetn <= resetn_i;
end generate GEN_FOR_SG;
-- Register Direct Mode
GEN_FOR_NO_SG : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather Engine Reset
axi_sg_resetn <= '1';
axi_dm_sg_resetn <= '1';
end generate GEN_FOR_NO_SG;
-- AXIS (MM2S or S2MM) logic reset and reset out
axis_resetn <= prmry_resetn_i;
axis_reset_out_n <= prmry_resetn_i;
end generate GEN_RESET_FOR_SYNC;
end implementation;
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Cadre : GEN1333 - Conception des circuits integrés --
-- : Projet de conception individuel 1 --
-- Par : Maxime Gauthier --
-- Date : 03 / 21 / 2015 --
-- Fichier : adder_n.vhd --
-- Description : VHDL pour une unité arithmétique logique générique (n bits) --
-- : basé sur du matériel de cours fourni par Ahmed Lakhsassi --
-- : et du code originellement écrit par Antoine Shaneen --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- librairie a inclure
library ieee;
use ieee.std_logic_1164.all;
-- déclaration de l'entité de l'additionneur générique (n bits) paramétrable
entity adder_n is
generic ( N : integer := 8);
port (
augend, addend : in std_logic_vector ( N downto 1 );
sum : out std_logic_vector ( N downto 1 );
carry_in : in std_logic;
carry_out : out std_logic
);
end adder_n;
-- architecture structurelle de l'additionneur générique (n bits).
architecture adder_n_impl of adder_n is
-- declare components
component adder
port(
augend, addend, carry_in : in std_logic;
sum, carry_out : out std_logic
);
end component;
-- declare signal
signal cs : std_logic_vector ( N downto 0 ); -- pour garder le carry
begin
cs(0) <= carry_in;
carry_out <= cs(N);
--instantiation de l'additionneur de 1 bit n fois
summator : for i in 1 to N generate
sum_n : adder
port map (
augend => augend(i),
addend => addend(i),
carry_in => cs(i-1),
sum => sum(i),
carry_out => cs(i)
);
end generate summator;
end adder_n_impl;
|
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_footer
---- Version: 1.0.0
---- Description:
---- TBD
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/02/28: initial release
---- 2016/10/21: rework
-------------------------------
--TODO: operationnal control field
--TODO: security trailer
--[OPT] SECURITY TRAILER
--[OPT] TRANSFER FRAME TRAILER (2 to 6 octets)
-- \ [OPT] OPERATIONAL CONTROL FIELD => 4 octets
-- \ [OPT] Frame error control field => 2 octets
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx footer inputs and outputs
--=============================================================================
entity ccsds_tx_footer is
generic(
constant CCSDS_TX_FOOTER_DATA_LENGTH: integer; -- in Bytes
constant CCSDS_TX_FOOTER_LENGTH: integer -- in Bytes
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_FOOTER_DATA_LENGTH*8-1 downto 0);
nxt_i: in std_logic;
rst_i: in std_logic;
-- outputs
bus_o: out std_logic;
dat_o: out std_logic_vector((CCSDS_TX_FOOTER_DATA_LENGTH+CCSDS_TX_FOOTER_LENGTH)*8-1 downto 0);
dat_val_o: out std_logic
);
end ccsds_tx_footer;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_footer is
component ccsds_rxtx_crc is
generic(
constant CCSDS_RXTX_CRC_LENGTH: integer;
constant CCSDS_RXTX_CRC_DATA_LENGTH: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
nxt_i: in std_logic;
pad_dat_i: in std_logic_vector(CCSDS_RXTX_CRC_LENGTH*8-1 downto 0);
pad_dat_val_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_RXTX_CRC_DATA_LENGTH*8-1 downto 0);
bus_o: out std_logic;
crc_o: out std_logic_vector(CCSDS_RXTX_CRC_LENGTH*8-1 downto 0);
dat_o: out std_logic_vector(CCSDS_RXTX_CRC_DATA_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end component;
-- internal variable signals
-- components instanciation and mapping
begin
tx_footer_crc_0: ccsds_rxtx_crc
generic map(
CCSDS_RXTX_CRC_DATA_LENGTH => CCSDS_TX_FOOTER_DATA_LENGTH,
CCSDS_RXTX_CRC_LENGTH => CCSDS_TX_FOOTER_LENGTH
)
port map(
clk_i => clk_i,
rst_i => rst_i,
nxt_i => nxt_i,
pad_dat_i => (others => '0'),
pad_dat_val_i => '0',
bus_o => bus_o,
dat_i => dat_i,
crc_o => dat_o(CCSDS_TX_FOOTER_LENGTH*8-1 downto 0),
dat_o => dat_o((CCSDS_TX_FOOTER_DATA_LENGTH+CCSDS_TX_FOOTER_LENGTH)*8-1 downto CCSDS_TX_FOOTER_LENGTH*8),
dat_val_o => dat_val_o
);
-- internal processing
end structure;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_09.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity computer_system is
end entity computer_system;
-- end not in book
architecture abstract of computer_system is
subtype word is bit_vector(31 downto 0);
signal address : natural;
signal read_data, write_data : word;
signal mem_read, mem_write : bit := '0';
signal mem_ready : bit := '0';
begin
cpu : process is
variable instr_reg : word;
variable PC : natural;
-- . . . -- other declarations
begin
loop
address <= PC;
mem_read <= '1';
wait until mem_ready = '1';
instr_reg := read_data;
mem_read <= '0';
wait until mem_ready = '0';
PC := PC + 4;
-- . . . -- execute the instruction
end loop;
end process cpu;
memory : process is
type memory_array is array (0 to 2**14 - 1) of word;
variable store : memory_array := (
-- . . .
-- not in book
0 => X"0000_0000",
1 => X"0000_0004",
2 => X"0000_0008",
3 => X"0000_000C",
4 => X"0000_0010",
5 => X"0000_0014",
others => X"0000_0000"
-- end not in book
);
begin
wait until mem_read = '1' or mem_write = '1';
if mem_read = '1' then
read_data <= store( address / 4 );
mem_ready <= '1';
wait until mem_read = '0';
mem_ready <= '0';
else
-- . . . -- perform write access
end if;
end process memory;
end architecture abstract;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_09.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity computer_system is
end entity computer_system;
-- end not in book
architecture abstract of computer_system is
subtype word is bit_vector(31 downto 0);
signal address : natural;
signal read_data, write_data : word;
signal mem_read, mem_write : bit := '0';
signal mem_ready : bit := '0';
begin
cpu : process is
variable instr_reg : word;
variable PC : natural;
-- . . . -- other declarations
begin
loop
address <= PC;
mem_read <= '1';
wait until mem_ready = '1';
instr_reg := read_data;
mem_read <= '0';
wait until mem_ready = '0';
PC := PC + 4;
-- . . . -- execute the instruction
end loop;
end process cpu;
memory : process is
type memory_array is array (0 to 2**14 - 1) of word;
variable store : memory_array := (
-- . . .
-- not in book
0 => X"0000_0000",
1 => X"0000_0004",
2 => X"0000_0008",
3 => X"0000_000C",
4 => X"0000_0010",
5 => X"0000_0014",
others => X"0000_0000"
-- end not in book
);
begin
wait until mem_read = '1' or mem_write = '1';
if mem_read = '1' then
read_data <= store( address / 4 );
mem_ready <= '1';
wait until mem_read = '0';
mem_ready <= '0';
else
-- . . . -- perform write access
end if;
end process memory;
end architecture abstract;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_fg_05_09.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity computer_system is
end entity computer_system;
-- end not in book
architecture abstract of computer_system is
subtype word is bit_vector(31 downto 0);
signal address : natural;
signal read_data, write_data : word;
signal mem_read, mem_write : bit := '0';
signal mem_ready : bit := '0';
begin
cpu : process is
variable instr_reg : word;
variable PC : natural;
-- . . . -- other declarations
begin
loop
address <= PC;
mem_read <= '1';
wait until mem_ready = '1';
instr_reg := read_data;
mem_read <= '0';
wait until mem_ready = '0';
PC := PC + 4;
-- . . . -- execute the instruction
end loop;
end process cpu;
memory : process is
type memory_array is array (0 to 2**14 - 1) of word;
variable store : memory_array := (
-- . . .
-- not in book
0 => X"0000_0000",
1 => X"0000_0004",
2 => X"0000_0008",
3 => X"0000_000C",
4 => X"0000_0010",
5 => X"0000_0014",
others => X"0000_0000"
-- end not in book
);
begin
wait until mem_read = '1' or mem_write = '1';
if mem_read = '1' then
read_data <= store( address / 4 );
mem_ready <= '1';
wait until mem_read = '0';
mem_ready <= '0';
else
-- . . . -- perform write access
end if;
end process memory;
end architecture abstract;
|
-- This system does nothing useful
-- It takes input X and this is registered internally
-- It computes x+1 and x+const independently
-- The output is computed as (x+const)-(x+1)=const-1
-- so the higher level modifies C and then C-1 is returned
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity Const_system is
generic (C: in integer := 500);
port (clk, reset: in std_logic;
x: in std_logic_vector (7 downto 0);
y: out std_logic_vector (10 downto 0) );
end Const_system;
library ieee;
use ieee.std_logic_1164.all;
entity Add is
generic (n: integer := 8);
port (a, b: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0);
cin: in std_logic );
end Add;
library ieee;
use ieee.std_logic_1164.all;
entity Inc is
generic (n: integer := 8);
port (a: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0)
);
end Inc;
library ieee;
use ieee.std_logic_1164.all;
entity Reg_N is
generic (n: integer := 4);
port (clk, reset: in std_logic;
a: in std_logic_vector (n-1 downto 0);
a_reg: out std_logic_vector (n-1 downto 0) );
end Reg_N;
architecture System_rtl of Const_system is
-- Register component
component Reg_N is
generic (n: integer := 4);
port (clk, reset: in std_logic;
a: in std_logic_vector (n-1 downto 0);
a_reg: out std_logic_vector (n-1 downto 0) );
end component;
-- incrementer component
component Inc is
generic (n: integer := 8);
port (a: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0)
);
end component;
-- adder component
component Add is
generic (n: integer := 8);
port (a, b: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0);
cin: in std_logic );
end component;
signal x_int: std_logic_vector (7 downto 0);
signal x_inc: std_logic_vector (7 downto 0);
signal x_sum: std_logic_vector (10 downto 0);
signal x_ext: std_logic_vector (10 downto 0);
signal x_inv: std_logic_vector (10 downto 0);
signal x_dif: std_logic_vector (10 downto 0);
signal zero, one: std_logic;
signal const: std_logic_vector (10 downto 0);
begin
const <= conv_std_logic_vector (C, 11);
-- connstant bit 0, 1
zero <= '0';
one <= '1';
-- registering input X
RegX: Reg_N generic map (n => 8)
port map ( clk => clk, reset => reset, a => x, a_reg => x_int);
-- Incrementing input x_int
incrementer: Inc generic map (n => 8)
port map (a => x_int, sum => x_inc); -- x + 1
-- forming 1's complement of x+1
x_inv <= "111" & not x_inc;
x_ext <= "000" & x_int;
-- adding constant to x_int
addition: Add generic map (n => 11)
port map (a => x_ext, b => const, cin => zero, sum => x_sum); -- x + 1000
-- this should get x+1000-(x+1) = 1000-1 = 999
subtraction: Add generic map (n => 11)
port map (a => x_sum, b => x_inv, cin => one, sum => x_dif);
-- registering output X
RegY: Reg_N generic map (n => 11)
port map ( clk => clk, reset => reset, a => x_dif, a_reg => y);
end System_rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
architecture Add_rtl of Add is
signal cx: std_logic_vector (n downto 0);
begin
cx <= ('0' & a) + ('0' & b) + cin;
sum <= cx (n-1 downto 0);
end Add_rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
architecture Inc_rtl of Inc is
signal cx: std_logic_vector (n downto 0);
begin
cx <= ('0' & a) + '1';
sum <= cx (n-1 downto 0);
end Inc_rtl;
library ieee;
use ieee.std_logic_1164.all;
architecture Reg_rtl of Reg_N is
begin
My_register: process (clk, reset)
begin
if (reset = '1') then
a_reg <= (others => '0');
elsif (clk'event and clk = '1') then
a_reg <= a;
end if;
end process;
end Reg_rtl;
|
-- This system does nothing useful
-- It takes input X and this is registered internally
-- It computes x+1 and x+const independently
-- The output is computed as (x+const)-(x+1)=const-1
-- so the higher level modifies C and then C-1 is returned
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity Const_system is
generic (C: in integer := 500);
port (clk, reset: in std_logic;
x: in std_logic_vector (7 downto 0);
y: out std_logic_vector (10 downto 0) );
end Const_system;
library ieee;
use ieee.std_logic_1164.all;
entity Add is
generic (n: integer := 8);
port (a, b: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0);
cin: in std_logic );
end Add;
library ieee;
use ieee.std_logic_1164.all;
entity Inc is
generic (n: integer := 8);
port (a: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0)
);
end Inc;
library ieee;
use ieee.std_logic_1164.all;
entity Reg_N is
generic (n: integer := 4);
port (clk, reset: in std_logic;
a: in std_logic_vector (n-1 downto 0);
a_reg: out std_logic_vector (n-1 downto 0) );
end Reg_N;
architecture System_rtl of Const_system is
-- Register component
component Reg_N is
generic (n: integer := 4);
port (clk, reset: in std_logic;
a: in std_logic_vector (n-1 downto 0);
a_reg: out std_logic_vector (n-1 downto 0) );
end component;
-- incrementer component
component Inc is
generic (n: integer := 8);
port (a: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0)
);
end component;
-- adder component
component Add is
generic (n: integer := 8);
port (a, b: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0);
cin: in std_logic );
end component;
signal x_int: std_logic_vector (7 downto 0);
signal x_inc: std_logic_vector (7 downto 0);
signal x_sum: std_logic_vector (10 downto 0);
signal x_ext: std_logic_vector (10 downto 0);
signal x_inv: std_logic_vector (10 downto 0);
signal x_dif: std_logic_vector (10 downto 0);
signal zero, one: std_logic;
signal const: std_logic_vector (10 downto 0);
begin
const <= conv_std_logic_vector (C, 11);
-- connstant bit 0, 1
zero <= '0';
one <= '1';
-- registering input X
RegX: Reg_N generic map (n => 8)
port map ( clk => clk, reset => reset, a => x, a_reg => x_int);
-- Incrementing input x_int
incrementer: Inc generic map (n => 8)
port map (a => x_int, sum => x_inc); -- x + 1
-- forming 1's complement of x+1
x_inv <= "111" & not x_inc;
x_ext <= "000" & x_int;
-- adding constant to x_int
addition: Add generic map (n => 11)
port map (a => x_ext, b => const, cin => zero, sum => x_sum); -- x + 1000
-- this should get x+1000-(x+1) = 1000-1 = 999
subtraction: Add generic map (n => 11)
port map (a => x_sum, b => x_inv, cin => one, sum => x_dif);
-- registering output X
RegY: Reg_N generic map (n => 11)
port map ( clk => clk, reset => reset, a => x_dif, a_reg => y);
end System_rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
architecture Add_rtl of Add is
signal cx: std_logic_vector (n downto 0);
begin
cx <= ('0' & a) + ('0' & b) + cin;
sum <= cx (n-1 downto 0);
end Add_rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
architecture Inc_rtl of Inc is
signal cx: std_logic_vector (n downto 0);
begin
cx <= ('0' & a) + '1';
sum <= cx (n-1 downto 0);
end Inc_rtl;
library ieee;
use ieee.std_logic_1164.all;
architecture Reg_rtl of Reg_N is
begin
My_register: process (clk, reset)
begin
if (reset = '1') then
a_reg <= (others => '0');
elsif (clk'event and clk = '1') then
a_reg <= a;
end if;
end process;
end Reg_rtl;
|
-- This system does nothing useful
-- It takes input X and this is registered internally
-- It computes x+1 and x+const independently
-- The output is computed as (x+const)-(x+1)=const-1
-- so the higher level modifies C and then C-1 is returned
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity Const_system is
generic (C: in integer := 500);
port (clk, reset: in std_logic;
x: in std_logic_vector (7 downto 0);
y: out std_logic_vector (10 downto 0) );
end Const_system;
library ieee;
use ieee.std_logic_1164.all;
entity Add is
generic (n: integer := 8);
port (a, b: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0);
cin: in std_logic );
end Add;
library ieee;
use ieee.std_logic_1164.all;
entity Inc is
generic (n: integer := 8);
port (a: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0)
);
end Inc;
library ieee;
use ieee.std_logic_1164.all;
entity Reg_N is
generic (n: integer := 4);
port (clk, reset: in std_logic;
a: in std_logic_vector (n-1 downto 0);
a_reg: out std_logic_vector (n-1 downto 0) );
end Reg_N;
architecture System_rtl of Const_system is
-- Register component
component Reg_N is
generic (n: integer := 4);
port (clk, reset: in std_logic;
a: in std_logic_vector (n-1 downto 0);
a_reg: out std_logic_vector (n-1 downto 0) );
end component;
-- incrementer component
component Inc is
generic (n: integer := 8);
port (a: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0)
);
end component;
-- adder component
component Add is
generic (n: integer := 8);
port (a, b: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0);
cin: in std_logic );
end component;
signal x_int: std_logic_vector (7 downto 0);
signal x_inc: std_logic_vector (7 downto 0);
signal x_sum: std_logic_vector (10 downto 0);
signal x_ext: std_logic_vector (10 downto 0);
signal x_inv: std_logic_vector (10 downto 0);
signal x_dif: std_logic_vector (10 downto 0);
signal zero, one: std_logic;
signal const: std_logic_vector (10 downto 0);
begin
const <= conv_std_logic_vector (C, 11);
-- connstant bit 0, 1
zero <= '0';
one <= '1';
-- registering input X
RegX: Reg_N generic map (n => 8)
port map ( clk => clk, reset => reset, a => x, a_reg => x_int);
-- Incrementing input x_int
incrementer: Inc generic map (n => 8)
port map (a => x_int, sum => x_inc); -- x + 1
-- forming 1's complement of x+1
x_inv <= "111" & not x_inc;
x_ext <= "000" & x_int;
-- adding constant to x_int
addition: Add generic map (n => 11)
port map (a => x_ext, b => const, cin => zero, sum => x_sum); -- x + 1000
-- this should get x+1000-(x+1) = 1000-1 = 999
subtraction: Add generic map (n => 11)
port map (a => x_sum, b => x_inv, cin => one, sum => x_dif);
-- registering output X
RegY: Reg_N generic map (n => 11)
port map ( clk => clk, reset => reset, a => x_dif, a_reg => y);
end System_rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
architecture Add_rtl of Add is
signal cx: std_logic_vector (n downto 0);
begin
cx <= ('0' & a) + ('0' & b) + cin;
sum <= cx (n-1 downto 0);
end Add_rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
architecture Inc_rtl of Inc is
signal cx: std_logic_vector (n downto 0);
begin
cx <= ('0' & a) + '1';
sum <= cx (n-1 downto 0);
end Inc_rtl;
library ieee;
use ieee.std_logic_1164.all;
architecture Reg_rtl of Reg_N is
begin
My_register: process (clk, reset)
begin
if (reset = '1') then
a_reg <= (others => '0');
elsif (clk'event and clk = '1') then
a_reg <= a;
end if;
end process;
end Reg_rtl;
|
-- This system does nothing useful
-- It takes input X and this is registered internally
-- It computes x+1 and x+const independently
-- The output is computed as (x+const)-(x+1)=const-1
-- so the higher level modifies C and then C-1 is returned
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity Const_system is
generic (C: in integer := 500);
port (clk, reset: in std_logic;
x: in std_logic_vector (7 downto 0);
y: out std_logic_vector (10 downto 0) );
end Const_system;
library ieee;
use ieee.std_logic_1164.all;
entity Add is
generic (n: integer := 8);
port (a, b: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0);
cin: in std_logic );
end Add;
library ieee;
use ieee.std_logic_1164.all;
entity Inc is
generic (n: integer := 8);
port (a: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0)
);
end Inc;
library ieee;
use ieee.std_logic_1164.all;
entity Reg_N is
generic (n: integer := 4);
port (clk, reset: in std_logic;
a: in std_logic_vector (n-1 downto 0);
a_reg: out std_logic_vector (n-1 downto 0) );
end Reg_N;
architecture System_rtl of Const_system is
-- Register component
component Reg_N is
generic (n: integer := 4);
port (clk, reset: in std_logic;
a: in std_logic_vector (n-1 downto 0);
a_reg: out std_logic_vector (n-1 downto 0) );
end component;
-- incrementer component
component Inc is
generic (n: integer := 8);
port (a: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0)
);
end component;
-- adder component
component Add is
generic (n: integer := 8);
port (a, b: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0);
cin: in std_logic );
end component;
signal x_int: std_logic_vector (7 downto 0);
signal x_inc: std_logic_vector (7 downto 0);
signal x_sum: std_logic_vector (10 downto 0);
signal x_ext: std_logic_vector (10 downto 0);
signal x_inv: std_logic_vector (10 downto 0);
signal x_dif: std_logic_vector (10 downto 0);
signal zero, one: std_logic;
signal const: std_logic_vector (10 downto 0);
begin
const <= conv_std_logic_vector (C, 11);
-- connstant bit 0, 1
zero <= '0';
one <= '1';
-- registering input X
RegX: Reg_N generic map (n => 8)
port map ( clk => clk, reset => reset, a => x, a_reg => x_int);
-- Incrementing input x_int
incrementer: Inc generic map (n => 8)
port map (a => x_int, sum => x_inc); -- x + 1
-- forming 1's complement of x+1
x_inv <= "111" & not x_inc;
x_ext <= "000" & x_int;
-- adding constant to x_int
addition: Add generic map (n => 11)
port map (a => x_ext, b => const, cin => zero, sum => x_sum); -- x + 1000
-- this should get x+1000-(x+1) = 1000-1 = 999
subtraction: Add generic map (n => 11)
port map (a => x_sum, b => x_inv, cin => one, sum => x_dif);
-- registering output X
RegY: Reg_N generic map (n => 11)
port map ( clk => clk, reset => reset, a => x_dif, a_reg => y);
end System_rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
architecture Add_rtl of Add is
signal cx: std_logic_vector (n downto 0);
begin
cx <= ('0' & a) + ('0' & b) + cin;
sum <= cx (n-1 downto 0);
end Add_rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
architecture Inc_rtl of Inc is
signal cx: std_logic_vector (n downto 0);
begin
cx <= ('0' & a) + '1';
sum <= cx (n-1 downto 0);
end Inc_rtl;
library ieee;
use ieee.std_logic_1164.all;
architecture Reg_rtl of Reg_N is
begin
My_register: process (clk, reset)
begin
if (reset = '1') then
a_reg <= (others => '0');
elsif (clk'event and clk = '1') then
a_reg <= a;
end if;
end process;
end Reg_rtl;
|
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Parity is
generic (
C_USE_LUT6 : boolean := true;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
library unisim;
use unisim.vcomponents.all;
architecture IMP of Parity is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_LUT6 : if (C_USE_LUT6) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MUXF7
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MUXF7
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MUXF7
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MUXF8
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_LUT6;
-- Fall-back implementation without LUT6
Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate
begin
Res <= ParityGen(InA);
end generate Not_Using_LUT6;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Parity is
generic (
C_USE_LUT6 : boolean := true;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
library unisim;
use unisim.vcomponents.all;
architecture IMP of Parity is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_LUT6 : if (C_USE_LUT6) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MUXF7
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MUXF7
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MUXF7
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MUXF8
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_LUT6;
-- Fall-back implementation without LUT6
Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate
begin
Res <= ParityGen(InA);
end generate Not_Using_LUT6;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Parity is
generic (
C_USE_LUT6 : boolean := true;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
library unisim;
use unisim.vcomponents.all;
architecture IMP of Parity is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_LUT6 : if (C_USE_LUT6) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MUXF7
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MUXF7
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MUXF7
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MUXF8
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_LUT6;
-- Fall-back implementation without LUT6
Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate
begin
Res <= ParityGen(InA);
end generate Not_Using_LUT6;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Parity is
generic (
C_USE_LUT6 : boolean := true;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
library unisim;
use unisim.vcomponents.all;
architecture IMP of Parity is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_LUT6 : if (C_USE_LUT6) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MUXF7
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MUXF7
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MUXF7
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MUXF8
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_LUT6;
-- Fall-back implementation without LUT6
Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate
begin
Res <= ParityGen(InA);
end generate Not_Using_LUT6;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Parity is
generic (
C_USE_LUT6 : boolean := true;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
library unisim;
use unisim.vcomponents.all;
architecture IMP of Parity is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_LUT6 : if (C_USE_LUT6) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MUXF7
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MUXF7
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MUXF7
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MUXF8
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_LUT6;
-- Fall-back implementation without LUT6
Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate
begin
Res <= ParityGen(InA);
end generate Not_Using_LUT6;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Parity is
generic (
C_USE_LUT6 : boolean := true;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
library unisim;
use unisim.vcomponents.all;
architecture IMP of Parity is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_LUT6 : if (C_USE_LUT6) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MUXF7
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MUXF7
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MUXF7
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MUXF8
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_LUT6;
-- Fall-back implementation without LUT6
Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate
begin
Res <= ParityGen(InA);
end generate Not_Using_LUT6;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- parity.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Parity is
generic (
C_USE_LUT6 : boolean := true;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
library unisim;
use unisim.vcomponents.all;
architecture IMP of Parity is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_LUT6 : if (C_USE_LUT6) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MUXF7
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MUXF7
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : LUT6
generic map(
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : LUT6
generic map(
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MUXF7
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MUXF8
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_LUT6;
-- Fall-back implementation without LUT6
Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate
begin
Res <= ParityGen(InA);
end generate Not_Using_LUT6;
end architecture IMP;
|
library ieee;
use ieee.std_logic_1164.all;
use work.rec05_pkg.all;
entity rec05 is
port (inp : std_logic;
o : out myrec);
end rec05;
architecture behav of rec05 is
begin
o.b <= not inp;
o.a <= "0101" when inp = '0' else "1010";
end behav;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY counter_tb IS
END counter_tb;
ARCHITECTURE behavior OF counter_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT counter
PORT(
CLK : IN std_logic;
OUTPUT : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
--Outputs
signal OUTPUT : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: counter PORT MAP (
CLK => CLK,
OUTPUT => OUTPUT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
-- insert stimulus here
wait;
end process;
END; |
entity foo is end;
architecture bar of foo is
signal S: STANDARD.BIT_VECTOR (1 to 10);
signal CLK1, CLK2: TIME;
signal CLK3: TIME register;
signal CLK4: TIME bus;
signal X: INTEGER := 42;
signal OUTPUT: WIRED_OR MULTI_VALUED_LOGIC;
begin end;
|
-------------------------------------------------------------------------------------------------
-- Company: CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version: V1
-- Version history :
-- V1 : 2015-04-02 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_01900_bad.vhd
-- File Creation date : 2015-04-02
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description: Handbook example: Indentation of source code: bad example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
--demonstrating good practices in VHDL and as such, its design is minimalistic.
--It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_01900_bad is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_01900_bad;
architecture Behavioral of STD_01900_bad is
signal Q : std_logic; -- D Flip-Flop output
begin
--CODE
-- D FlipFlop process
P_FlipFlop : process(i_Clock, i_Reset_n)
begin
if (i_Reset_n = '0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
Q <= i_D;
end if;
end process;
--CODE
o_Q <= Q;
end Behavioral;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
entity Arbiter_out_one_hot_pseudo is
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: out std_logic_vector (5 downto 0) -- 6 states for Arbiter's FSM
);
end Arbiter_out_one_hot_pseudo;
architecture behavior of Arbiter_out_one_hot_pseudo is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
begin
--process (clk, reset)begin
-- if reset = '0' then
-- state <= IDLE;
-- elsif clk'event and clk ='1'then
-- state <= state_in;
-- end if;
--end process;
-- anything below here is pure combinational
process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, credit)
begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
-- Arbiter_out's prioritization is N,E,W,S and L (N: highest priority)
case state is
when IDLE =>
if req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and req_X_N = '1' then
grant_Y_N <= '1';
end if;
if req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and req_X_E = '1' then
grant_Y_E <= '1';
end if;
if req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and req_X_W = '1' then
grant_Y_W <= '1';
end if;
if req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and req_X_S = '1' then
grant_Y_S <= '1';
end if;
if req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others => -- Includes Local state and invalid state(s)
if credit /= "00" and req_X_L = '1' then
grant_Y_L <= '1';
end if;
if req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
entity Arbiter_out_one_hot_pseudo is
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: out std_logic_vector (5 downto 0) -- 6 states for Arbiter's FSM
);
end Arbiter_out_one_hot_pseudo;
architecture behavior of Arbiter_out_one_hot_pseudo is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
begin
--process (clk, reset)begin
-- if reset = '0' then
-- state <= IDLE;
-- elsif clk'event and clk ='1'then
-- state <= state_in;
-- end if;
--end process;
-- anything below here is pure combinational
process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, credit)
begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
-- Arbiter_out's prioritization is N,E,W,S and L (N: highest priority)
case state is
when IDLE =>
if req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and req_X_N = '1' then
grant_Y_N <= '1';
end if;
if req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and req_X_E = '1' then
grant_Y_E <= '1';
end if;
if req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and req_X_W = '1' then
grant_Y_W <= '1';
end if;
if req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and req_X_S = '1' then
grant_Y_S <= '1';
end if;
if req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others => -- Includes Local state and invalid state(s)
if credit /= "00" and req_X_L = '1' then
grant_Y_L <= '1';
end if;
if req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
entity Arbiter_out_one_hot_pseudo is
port ( credit: in std_logic_vector(1 downto 0);
req_X_N, req_X_E, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: out std_logic_vector (5 downto 0) -- 6 states for Arbiter's FSM
);
end Arbiter_out_one_hot_pseudo;
architecture behavior of Arbiter_out_one_hot_pseudo is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
begin
--process (clk, reset)begin
-- if reset = '0' then
-- state <= IDLE;
-- elsif clk'event and clk ='1'then
-- state <= state_in;
-- end if;
--end process;
-- anything below here is pure combinational
process(state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, credit)
begin
grant_Y_N <= '0';
grant_Y_E <= '0';
grant_Y_W <= '0';
grant_Y_S <= '0';
grant_Y_L <= '0';
-- Arbiter_out's prioritization is N,E,W,S and L (N: highest priority)
case state is
when IDLE =>
if req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when North =>
if credit /= "00" and req_X_N = '1' then
grant_Y_N <= '1';
end if;
if req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
else
state_in <= IDLE;
end if;
when East =>
if credit /= "00" and req_X_E = '1' then
grant_Y_E <= '1';
end if;
if req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
else
state_in <= IDLE;
end if;
when West =>
if credit /= "00" and req_X_W = '1' then
grant_Y_W <= '1';
end if;
if req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
else
state_in <= IDLE;
end if;
when South =>
if credit /= "00" and req_X_S = '1' then
grant_Y_S <= '1';
end if;
if req_X_S = '1' then
state_in <= South;
elsif req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
else
state_in <= IDLE;
end if;
when others => -- Includes Local state and invalid state(s)
if credit /= "00" and req_X_L = '1' then
grant_Y_L <= '1';
end if;
if req_X_L = '1' then
state_in <= Local;
elsif req_X_N ='1' then
state_in <= North;
elsif req_X_E = '1' then
state_in <= East;
elsif req_X_W = '1' then
state_in <= West;
elsif req_X_S = '1' then
state_in <= South;
else
state_in <= IDLE;
end if;
end case;
end process;
end;
|
-------------------------------------------------------------------------------
-- system_microblaze_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library microblaze_v8_50_c;
use microblaze_v8_50_c.all;
entity system_microblaze_0_wrapper is
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to 7);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to 63);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to 63);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to 7);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to 63);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to 63);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector(0 downto 0);
M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector(0 downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector(0 downto 0);
M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector(0 downto 0);
M_AXI_IP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector(0 downto 0);
M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector(0 downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector(0 downto 0);
M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector(0 downto 0);
M_AXI_DP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector(0 downto 0);
M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_IC_BID : in std_logic_vector(0 downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_WACK : out std_logic;
M_AXI_IC_ARID : out std_logic_vector(0 downto 0);
M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_RID : in std_logic_vector(0 downto 0);
M_AXI_IC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_RACK : out std_logic;
M_AXI_IC_ACVALID : in std_logic;
M_AXI_IC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_IC_ACREADY : out std_logic;
M_AXI_IC_CRREADY : in std_logic;
M_AXI_IC_CRVALID : out std_logic;
M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_IC_CDVALID : out std_logic;
M_AXI_IC_CDREADY : in std_logic;
M_AXI_IC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_CDLAST : out std_logic;
M_AXI_DC_AWID : out std_logic_vector(0 downto 0);
M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_DC_BID : in std_logic_vector(0 downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_WACK : out std_logic;
M_AXI_DC_ARID : out std_logic_vector(0 downto 0);
M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_RID : in std_logic_vector(0 downto 0);
M_AXI_DC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_RACK : out std_logic;
M_AXI_DC_ACVALID : in std_logic;
M_AXI_DC_ACADDR : in std_logic_vector(31 downto 0);
M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_DC_ACREADY : out std_logic;
M_AXI_DC_CRREADY : in std_logic;
M_AXI_DC_CRVALID : out std_logic;
M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_DC_CDVALID : out std_logic;
M_AXI_DC_CDREADY : in std_logic;
M_AXI_DC_CDDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_CDLAST : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to 31);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to 31);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to 31);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to 31);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to 31);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to 31);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to 31);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to 31);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to 31);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to 31);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to 31);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to 31);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to 31);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to 31);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to 31);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to 31);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to 31);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to 31);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to 31);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to 31);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to 31);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to 31);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to 31);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to 31);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to 31);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to 31);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to 31);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to 31);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to 31);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to 31);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to 31);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to 31);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(31 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(31 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(31 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(31 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(31 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(31 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(31 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(31 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(31 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(31 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(31 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(31 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(31 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(31 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(31 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(31 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(31 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(31 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(31 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(31 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(31 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(31 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(31 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(31 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(31 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(31 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(31 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(31 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(31 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(31 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(31 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(31 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_microblaze_0_wrapper : entity is "microblaze_v8_50_c";
end system_microblaze_0_wrapper;
architecture STRUCTURE of system_microblaze_0_wrapper is
component microblaze is
generic (
C_SCO : integer;
C_FREQ : integer;
C_DATA_SIZE : integer;
C_DYNAMIC_BUS_SIZING : integer;
C_FAMILY : string;
C_INSTANCE : string;
C_AVOID_PRIMITIVES : integer;
C_FAULT_TOLERANT : integer;
C_ECC_USE_CE_EXCEPTION : integer;
C_LOCKSTEP_SLAVE : integer;
C_ENDIANNESS : integer;
C_AREA_OPTIMIZED : integer;
C_OPTIMIZATION : integer;
C_INTERCONNECT : integer;
C_STREAM_INTERCONNECT : integer;
C_BASE_VECTORS : std_logic_vector;
C_DPLB_DWIDTH : integer;
C_DPLB_NATIVE_DWIDTH : integer;
C_DPLB_BURST_EN : integer;
C_DPLB_P2P : integer;
C_IPLB_DWIDTH : integer;
C_IPLB_NATIVE_DWIDTH : integer;
C_IPLB_BURST_EN : integer;
C_IPLB_P2P : integer;
C_M_AXI_DP_THREAD_ID_WIDTH : integer;
C_M_AXI_DP_DATA_WIDTH : integer;
C_M_AXI_DP_ADDR_WIDTH : integer;
C_M_AXI_DP_EXCLUSIVE_ACCESS : integer;
C_M_AXI_IP_THREAD_ID_WIDTH : integer;
C_M_AXI_IP_DATA_WIDTH : integer;
C_M_AXI_IP_ADDR_WIDTH : integer;
C_D_AXI : integer;
C_D_PLB : integer;
C_D_LMB : integer;
C_I_AXI : integer;
C_I_PLB : integer;
C_I_LMB : integer;
C_USE_MSR_INSTR : integer;
C_USE_PCMP_INSTR : integer;
C_USE_BARREL : integer;
C_USE_DIV : integer;
C_USE_HW_MUL : integer;
C_USE_FPU : integer;
C_USE_REORDER_INSTR : integer;
C_UNALIGNED_EXCEPTIONS : integer;
C_ILL_OPCODE_EXCEPTION : integer;
C_M_AXI_I_BUS_EXCEPTION : integer;
C_M_AXI_D_BUS_EXCEPTION : integer;
C_IPLB_BUS_EXCEPTION : integer;
C_DPLB_BUS_EXCEPTION : integer;
C_DIV_ZERO_EXCEPTION : integer;
C_FPU_EXCEPTION : integer;
C_FSL_EXCEPTION : integer;
C_USE_STACK_PROTECTION : integer;
C_PVR : integer;
C_PVR_USER1 : std_logic_vector(0 to 7);
C_PVR_USER2 : std_logic_vector(0 to 31);
C_DEBUG_ENABLED : integer;
C_NUMBER_OF_PC_BRK : integer;
C_NUMBER_OF_RD_ADDR_BRK : integer;
C_NUMBER_OF_WR_ADDR_BRK : integer;
C_INTERRUPT_IS_EDGE : integer;
C_EDGE_IS_POSITIVE : integer;
C_RESET_MSR : std_logic_vector;
C_OPCODE_0x0_ILLEGAL : integer;
C_FSL_LINKS : integer;
C_FSL_DATA_SIZE : integer;
C_USE_EXTENDED_FSL_INSTR : integer;
C_M0_AXIS_DATA_WIDTH : integer;
C_S0_AXIS_DATA_WIDTH : integer;
C_M1_AXIS_DATA_WIDTH : integer;
C_S1_AXIS_DATA_WIDTH : integer;
C_M2_AXIS_DATA_WIDTH : integer;
C_S2_AXIS_DATA_WIDTH : integer;
C_M3_AXIS_DATA_WIDTH : integer;
C_S3_AXIS_DATA_WIDTH : integer;
C_M4_AXIS_DATA_WIDTH : integer;
C_S4_AXIS_DATA_WIDTH : integer;
C_M5_AXIS_DATA_WIDTH : integer;
C_S5_AXIS_DATA_WIDTH : integer;
C_M6_AXIS_DATA_WIDTH : integer;
C_S6_AXIS_DATA_WIDTH : integer;
C_M7_AXIS_DATA_WIDTH : integer;
C_S7_AXIS_DATA_WIDTH : integer;
C_M8_AXIS_DATA_WIDTH : integer;
C_S8_AXIS_DATA_WIDTH : integer;
C_M9_AXIS_DATA_WIDTH : integer;
C_S9_AXIS_DATA_WIDTH : integer;
C_M10_AXIS_DATA_WIDTH : integer;
C_S10_AXIS_DATA_WIDTH : integer;
C_M11_AXIS_DATA_WIDTH : integer;
C_S11_AXIS_DATA_WIDTH : integer;
C_M12_AXIS_DATA_WIDTH : integer;
C_S12_AXIS_DATA_WIDTH : integer;
C_M13_AXIS_DATA_WIDTH : integer;
C_S13_AXIS_DATA_WIDTH : integer;
C_M14_AXIS_DATA_WIDTH : integer;
C_S14_AXIS_DATA_WIDTH : integer;
C_M15_AXIS_DATA_WIDTH : integer;
C_S15_AXIS_DATA_WIDTH : integer;
C_ICACHE_BASEADDR : std_logic_vector;
C_ICACHE_HIGHADDR : std_logic_vector;
C_USE_ICACHE : integer;
C_ALLOW_ICACHE_WR : integer;
C_ADDR_TAG_BITS : integer;
C_CACHE_BYTE_SIZE : integer;
C_ICACHE_USE_FSL : integer;
C_ICACHE_LINE_LEN : integer;
C_ICACHE_ALWAYS_USED : integer;
C_ICACHE_INTERFACE : integer;
C_ICACHE_VICTIMS : integer;
C_ICACHE_STREAMS : integer;
C_ICACHE_FORCE_TAG_LUTRAM : integer;
C_ICACHE_DATA_WIDTH : integer;
C_M_AXI_IC_THREAD_ID_WIDTH : integer;
C_M_AXI_IC_DATA_WIDTH : integer;
C_M_AXI_IC_ADDR_WIDTH : integer;
C_M_AXI_IC_USER_VALUE : integer;
C_M_AXI_IC_AWUSER_WIDTH : integer;
C_M_AXI_IC_ARUSER_WIDTH : integer;
C_M_AXI_IC_WUSER_WIDTH : integer;
C_M_AXI_IC_RUSER_WIDTH : integer;
C_M_AXI_IC_BUSER_WIDTH : integer;
C_DCACHE_BASEADDR : std_logic_vector;
C_DCACHE_HIGHADDR : std_logic_vector;
C_USE_DCACHE : integer;
C_ALLOW_DCACHE_WR : integer;
C_DCACHE_ADDR_TAG : integer;
C_DCACHE_BYTE_SIZE : integer;
C_DCACHE_USE_FSL : integer;
C_DCACHE_LINE_LEN : integer;
C_DCACHE_ALWAYS_USED : integer;
C_DCACHE_INTERFACE : integer;
C_DCACHE_USE_WRITEBACK : integer;
C_DCACHE_VICTIMS : integer;
C_DCACHE_FORCE_TAG_LUTRAM : integer;
C_DCACHE_DATA_WIDTH : integer;
C_M_AXI_DC_THREAD_ID_WIDTH : integer;
C_M_AXI_DC_DATA_WIDTH : integer;
C_M_AXI_DC_ADDR_WIDTH : integer;
C_M_AXI_DC_EXCLUSIVE_ACCESS : integer;
C_M_AXI_DC_USER_VALUE : integer;
C_M_AXI_DC_AWUSER_WIDTH : integer;
C_M_AXI_DC_ARUSER_WIDTH : integer;
C_M_AXI_DC_WUSER_WIDTH : integer;
C_M_AXI_DC_RUSER_WIDTH : integer;
C_M_AXI_DC_BUSER_WIDTH : integer;
C_USE_MMU : integer;
C_MMU_DTLB_SIZE : integer;
C_MMU_ITLB_SIZE : integer;
C_MMU_TLB_ACCESS : integer;
C_MMU_ZONES : integer;
C_MMU_PRIVILEGED_INSTR : integer;
C_USE_INTERRUPT : integer;
C_USE_EXT_BRK : integer;
C_USE_EXT_NM_BRK : integer;
C_USE_BRANCH_TARGET_CACHE : integer;
C_BRANCH_TARGET_CACHE_SIZE : integer;
C_PC_WIDTH : integer
);
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to (C_IPLB_DWIDTH-1)/8);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to (C_DPLB_DWIDTH-1)/8);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_AWADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(((C_M_AXI_IP_DATA_WIDTH/8)-1) downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_ARADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_RDATA : in std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_AWADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(((C_M_AXI_DP_DATA_WIDTH/8)-1) downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_ARADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_RDATA : in std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_AWADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector((C_M_AXI_IC_AWUSER_WIDTH-1) downto 0);
M_AXI_IC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_WDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(((C_M_AXI_IC_DATA_WIDTH/8)-1) downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector((C_M_AXI_IC_WUSER_WIDTH-1) downto 0);
M_AXI_IC_BID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector((C_M_AXI_IC_BUSER_WIDTH-1) downto 0);
M_AXI_IC_WACK : out std_logic;
M_AXI_IC_ARID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_ARADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector((C_M_AXI_IC_ARUSER_WIDTH-1) downto 0);
M_AXI_IC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_IC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_IC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_IC_RID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_RDATA : in std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1+2*((C_INTERCONNECT-1)/2) downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector((C_M_AXI_IC_RUSER_WIDTH-1) downto 0);
M_AXI_IC_RACK : out std_logic;
M_AXI_IC_ACVALID : in std_logic;
M_AXI_IC_ACADDR : in std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_IC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_IC_ACREADY : out std_logic;
M_AXI_IC_CRREADY : in std_logic;
M_AXI_IC_CRVALID : out std_logic;
M_AXI_IC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_IC_CDVALID : out std_logic;
M_AXI_IC_CDREADY : in std_logic;
M_AXI_IC_CDDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_CDLAST : out std_logic;
M_AXI_DC_AWID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_AWADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector((C_M_AXI_DC_AWUSER_WIDTH-1) downto 0);
M_AXI_DC_AWDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_AWSNOOP : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_WDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(((C_M_AXI_DC_DATA_WIDTH/8)-1) downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector((C_M_AXI_DC_WUSER_WIDTH-1) downto 0);
M_AXI_DC_BID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector((C_M_AXI_DC_BUSER_WIDTH-1) downto 0);
M_AXI_DC_WACK : out std_logic;
M_AXI_DC_ARID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_ARADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector((C_M_AXI_DC_ARUSER_WIDTH-1) downto 0);
M_AXI_DC_ARDOMAIN : out std_logic_vector(1 downto 0);
M_AXI_DC_ARSNOOP : out std_logic_vector(3 downto 0);
M_AXI_DC_ARBAR : out std_logic_vector(1 downto 0);
M_AXI_DC_RID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_RDATA : in std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1+2*((C_INTERCONNECT-1)/2) downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector((C_M_AXI_DC_RUSER_WIDTH-1) downto 0);
M_AXI_DC_RACK : out std_logic;
M_AXI_DC_ACVALID : in std_logic;
M_AXI_DC_ACADDR : in std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ACSNOOP : in std_logic_vector(3 downto 0);
M_AXI_DC_ACPROT : in std_logic_vector(2 downto 0);
M_AXI_DC_ACREADY : out std_logic;
M_AXI_DC_CRREADY : in std_logic;
M_AXI_DC_CRVALID : out std_logic;
M_AXI_DC_CRRESP : out std_logic_vector(4 downto 0);
M_AXI_DC_CDVALID : out std_logic;
M_AXI_DC_CDREADY : in std_logic;
M_AXI_DC_CDDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_CDLAST : out std_logic;
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(C_M0_AXIS_DATA_WIDTH-1 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(C_S0_AXIS_DATA_WIDTH-1 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(C_M1_AXIS_DATA_WIDTH-1 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(C_S1_AXIS_DATA_WIDTH-1 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(C_M2_AXIS_DATA_WIDTH-1 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(C_S2_AXIS_DATA_WIDTH-1 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(C_M3_AXIS_DATA_WIDTH-1 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(C_S3_AXIS_DATA_WIDTH-1 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(C_M4_AXIS_DATA_WIDTH-1 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(C_S4_AXIS_DATA_WIDTH-1 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(C_M5_AXIS_DATA_WIDTH-1 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(C_S5_AXIS_DATA_WIDTH-1 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(C_M6_AXIS_DATA_WIDTH-1 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(C_S6_AXIS_DATA_WIDTH-1 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(C_M7_AXIS_DATA_WIDTH-1 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(C_S7_AXIS_DATA_WIDTH-1 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(C_M8_AXIS_DATA_WIDTH-1 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(C_S8_AXIS_DATA_WIDTH-1 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(C_M9_AXIS_DATA_WIDTH-1 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(C_S9_AXIS_DATA_WIDTH-1 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(C_M10_AXIS_DATA_WIDTH-1 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(C_S10_AXIS_DATA_WIDTH-1 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(C_M11_AXIS_DATA_WIDTH-1 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(C_S11_AXIS_DATA_WIDTH-1 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(C_M12_AXIS_DATA_WIDTH-1 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(C_S12_AXIS_DATA_WIDTH-1 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(C_M13_AXIS_DATA_WIDTH-1 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(C_S13_AXIS_DATA_WIDTH-1 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(C_M14_AXIS_DATA_WIDTH-1 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(C_S14_AXIS_DATA_WIDTH-1 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(C_M15_AXIS_DATA_WIDTH-1 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(C_S15_AXIS_DATA_WIDTH-1 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end component;
begin
microblaze_0 : microblaze
generic map (
C_SCO => 0,
C_FREQ => 50000000,
C_DATA_SIZE => 32,
C_DYNAMIC_BUS_SIZING => 1,
C_FAMILY => "virtex5",
C_INSTANCE => "microblaze_0",
C_AVOID_PRIMITIVES => 0,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_ENDIANNESS => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 1,
C_STREAM_INTERCONNECT => 0,
C_BASE_VECTORS => X"00000000",
C_DPLB_DWIDTH => 64,
C_DPLB_NATIVE_DWIDTH => 32,
C_DPLB_BURST_EN => 0,
C_DPLB_P2P => 0,
C_IPLB_DWIDTH => 64,
C_IPLB_NATIVE_DWIDTH => 32,
C_IPLB_BURST_EN => 0,
C_IPLB_P2P => 0,
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_D_AXI => 0,
C_D_PLB => 1,
C_D_LMB => 1,
C_I_AXI => 0,
C_I_PLB => 1,
C_I_LMB => 1,
C_USE_MSR_INSTR => 1,
C_USE_PCMP_INSTR => 1,
C_USE_BARREL => 1,
C_USE_DIV => 0,
C_USE_HW_MUL => 1,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_IPLB_BUS_EXCEPTION => 0,
C_DPLB_BUS_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_FSL_LINKS => 0,
C_FSL_DATA_SIZE => 32,
C_USE_EXTENDED_FSL_INSTR => 0,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"00000000",
C_ICACHE_HIGHADDR => X"3FFFFFFF",
C_USE_ICACHE => 0,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 0,
C_CACHE_BYTE_SIZE => 8192,
C_ICACHE_USE_FSL => 1,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 0,
C_ICACHE_INTERFACE => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_STREAMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 2#11111#,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"00000000",
C_DCACHE_HIGHADDR => X"3FFFFFFF",
C_USE_DCACHE => 0,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 0,
C_DCACHE_BYTE_SIZE => 8192,
C_DCACHE_USE_FSL => 1,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 0,
C_DCACHE_INTERFACE => 0,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 2#11111#,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_INTERRUPT => 0,
C_USE_EXT_BRK => 1,
C_USE_EXT_NM_BRK => 1,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32
)
port map (
CLK => CLK,
RESET => RESET,
MB_RESET => MB_RESET,
INTERRUPT => INTERRUPT,
INTERRUPT_ADDRESS => INTERRUPT_ADDRESS,
INTERRUPT_ACK => INTERRUPT_ACK,
EXT_BRK => EXT_BRK,
EXT_NM_BRK => EXT_NM_BRK,
DBG_STOP => DBG_STOP,
MB_Halted => MB_Halted,
MB_Error => MB_Error,
WAKEUP => WAKEUP,
SLEEP => SLEEP,
DBG_WAKEUP => DBG_WAKEUP,
LOCKSTEP_MASTER_OUT => LOCKSTEP_MASTER_OUT,
LOCKSTEP_SLAVE_IN => LOCKSTEP_SLAVE_IN,
LOCKSTEP_OUT => LOCKSTEP_OUT,
INSTR => INSTR,
IREADY => IREADY,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
INSTR_ADDR => INSTR_ADDR,
IFETCH => IFETCH,
I_AS => I_AS,
IPLB_M_ABort => IPLB_M_ABort,
IPLB_M_ABus => IPLB_M_ABus,
IPLB_M_UABus => IPLB_M_UABus,
IPLB_M_BE => IPLB_M_BE,
IPLB_M_busLock => IPLB_M_busLock,
IPLB_M_lockErr => IPLB_M_lockErr,
IPLB_M_MSize => IPLB_M_MSize,
IPLB_M_priority => IPLB_M_priority,
IPLB_M_rdBurst => IPLB_M_rdBurst,
IPLB_M_request => IPLB_M_request,
IPLB_M_RNW => IPLB_M_RNW,
IPLB_M_size => IPLB_M_size,
IPLB_M_TAttribute => IPLB_M_TAttribute,
IPLB_M_type => IPLB_M_type,
IPLB_M_wrBurst => IPLB_M_wrBurst,
IPLB_M_wrDBus => IPLB_M_wrDBus,
IPLB_MBusy => IPLB_MBusy,
IPLB_MRdErr => IPLB_MRdErr,
IPLB_MWrErr => IPLB_MWrErr,
IPLB_MIRQ => IPLB_MIRQ,
IPLB_MWrBTerm => IPLB_MWrBTerm,
IPLB_MWrDAck => IPLB_MWrDAck,
IPLB_MAddrAck => IPLB_MAddrAck,
IPLB_MRdBTerm => IPLB_MRdBTerm,
IPLB_MRdDAck => IPLB_MRdDAck,
IPLB_MRdDBus => IPLB_MRdDBus,
IPLB_MRdWdAddr => IPLB_MRdWdAddr,
IPLB_MRearbitrate => IPLB_MRearbitrate,
IPLB_MSSize => IPLB_MSSize,
IPLB_MTimeout => IPLB_MTimeout,
DATA_READ => DATA_READ,
DREADY => DREADY,
DWAIT => DWAIT,
DCE => DCE,
DUE => DUE,
DATA_WRITE => DATA_WRITE,
DATA_ADDR => DATA_ADDR,
D_AS => D_AS,
READ_STROBE => READ_STROBE,
WRITE_STROBE => WRITE_STROBE,
BYTE_ENABLE => BYTE_ENABLE,
DPLB_M_ABort => DPLB_M_ABort,
DPLB_M_ABus => DPLB_M_ABus,
DPLB_M_UABus => DPLB_M_UABus,
DPLB_M_BE => DPLB_M_BE,
DPLB_M_busLock => DPLB_M_busLock,
DPLB_M_lockErr => DPLB_M_lockErr,
DPLB_M_MSize => DPLB_M_MSize,
DPLB_M_priority => DPLB_M_priority,
DPLB_M_rdBurst => DPLB_M_rdBurst,
DPLB_M_request => DPLB_M_request,
DPLB_M_RNW => DPLB_M_RNW,
DPLB_M_size => DPLB_M_size,
DPLB_M_TAttribute => DPLB_M_TAttribute,
DPLB_M_type => DPLB_M_type,
DPLB_M_wrBurst => DPLB_M_wrBurst,
DPLB_M_wrDBus => DPLB_M_wrDBus,
DPLB_MBusy => DPLB_MBusy,
DPLB_MRdErr => DPLB_MRdErr,
DPLB_MWrErr => DPLB_MWrErr,
DPLB_MIRQ => DPLB_MIRQ,
DPLB_MWrBTerm => DPLB_MWrBTerm,
DPLB_MWrDAck => DPLB_MWrDAck,
DPLB_MAddrAck => DPLB_MAddrAck,
DPLB_MRdBTerm => DPLB_MRdBTerm,
DPLB_MRdDAck => DPLB_MRdDAck,
DPLB_MRdDBus => DPLB_MRdDBus,
DPLB_MRdWdAddr => DPLB_MRdWdAddr,
DPLB_MRearbitrate => DPLB_MRearbitrate,
DPLB_MSSize => DPLB_MSSize,
DPLB_MTimeout => DPLB_MTimeout,
M_AXI_IP_AWID => M_AXI_IP_AWID,
M_AXI_IP_AWADDR => M_AXI_IP_AWADDR,
M_AXI_IP_AWLEN => M_AXI_IP_AWLEN,
M_AXI_IP_AWSIZE => M_AXI_IP_AWSIZE,
M_AXI_IP_AWBURST => M_AXI_IP_AWBURST,
M_AXI_IP_AWLOCK => M_AXI_IP_AWLOCK,
M_AXI_IP_AWCACHE => M_AXI_IP_AWCACHE,
M_AXI_IP_AWPROT => M_AXI_IP_AWPROT,
M_AXI_IP_AWQOS => M_AXI_IP_AWQOS,
M_AXI_IP_AWVALID => M_AXI_IP_AWVALID,
M_AXI_IP_AWREADY => M_AXI_IP_AWREADY,
M_AXI_IP_WDATA => M_AXI_IP_WDATA,
M_AXI_IP_WSTRB => M_AXI_IP_WSTRB,
M_AXI_IP_WLAST => M_AXI_IP_WLAST,
M_AXI_IP_WVALID => M_AXI_IP_WVALID,
M_AXI_IP_WREADY => M_AXI_IP_WREADY,
M_AXI_IP_BID => M_AXI_IP_BID,
M_AXI_IP_BRESP => M_AXI_IP_BRESP,
M_AXI_IP_BVALID => M_AXI_IP_BVALID,
M_AXI_IP_BREADY => M_AXI_IP_BREADY,
M_AXI_IP_ARID => M_AXI_IP_ARID,
M_AXI_IP_ARADDR => M_AXI_IP_ARADDR,
M_AXI_IP_ARLEN => M_AXI_IP_ARLEN,
M_AXI_IP_ARSIZE => M_AXI_IP_ARSIZE,
M_AXI_IP_ARBURST => M_AXI_IP_ARBURST,
M_AXI_IP_ARLOCK => M_AXI_IP_ARLOCK,
M_AXI_IP_ARCACHE => M_AXI_IP_ARCACHE,
M_AXI_IP_ARPROT => M_AXI_IP_ARPROT,
M_AXI_IP_ARQOS => M_AXI_IP_ARQOS,
M_AXI_IP_ARVALID => M_AXI_IP_ARVALID,
M_AXI_IP_ARREADY => M_AXI_IP_ARREADY,
M_AXI_IP_RID => M_AXI_IP_RID,
M_AXI_IP_RDATA => M_AXI_IP_RDATA,
M_AXI_IP_RRESP => M_AXI_IP_RRESP,
M_AXI_IP_RLAST => M_AXI_IP_RLAST,
M_AXI_IP_RVALID => M_AXI_IP_RVALID,
M_AXI_IP_RREADY => M_AXI_IP_RREADY,
M_AXI_DP_AWID => M_AXI_DP_AWID,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWLEN => M_AXI_DP_AWLEN,
M_AXI_DP_AWSIZE => M_AXI_DP_AWSIZE,
M_AXI_DP_AWBURST => M_AXI_DP_AWBURST,
M_AXI_DP_AWLOCK => M_AXI_DP_AWLOCK,
M_AXI_DP_AWCACHE => M_AXI_DP_AWCACHE,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWQOS => M_AXI_DP_AWQOS,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WLAST => M_AXI_DP_WLAST,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => M_AXI_DP_BID,
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARID => M_AXI_DP_ARID,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARLEN => M_AXI_DP_ARLEN,
M_AXI_DP_ARSIZE => M_AXI_DP_ARSIZE,
M_AXI_DP_ARBURST => M_AXI_DP_ARBURST,
M_AXI_DP_ARLOCK => M_AXI_DP_ARLOCK,
M_AXI_DP_ARCACHE => M_AXI_DP_ARCACHE,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARQOS => M_AXI_DP_ARQOS,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => M_AXI_DP_RID,
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => M_AXI_DP_RLAST,
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_AWUSER => M_AXI_IC_AWUSER,
M_AXI_IC_AWDOMAIN => M_AXI_IC_AWDOMAIN,
M_AXI_IC_AWSNOOP => M_AXI_IC_AWSNOOP,
M_AXI_IC_AWBAR => M_AXI_IC_AWBAR,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_WUSER => M_AXI_IC_WUSER,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => M_AXI_IC_BUSER,
M_AXI_IC_WACK => M_AXI_IC_WACK,
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_ARUSER => M_AXI_IC_ARUSER,
M_AXI_IC_ARDOMAIN => M_AXI_IC_ARDOMAIN,
M_AXI_IC_ARSNOOP => M_AXI_IC_ARSNOOP,
M_AXI_IC_ARBAR => M_AXI_IC_ARBAR,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => M_AXI_IC_RUSER,
M_AXI_IC_RACK => M_AXI_IC_RACK,
M_AXI_IC_ACVALID => M_AXI_IC_ACVALID,
M_AXI_IC_ACADDR => M_AXI_IC_ACADDR,
M_AXI_IC_ACSNOOP => M_AXI_IC_ACSNOOP,
M_AXI_IC_ACPROT => M_AXI_IC_ACPROT,
M_AXI_IC_ACREADY => M_AXI_IC_ACREADY,
M_AXI_IC_CRREADY => M_AXI_IC_CRREADY,
M_AXI_IC_CRVALID => M_AXI_IC_CRVALID,
M_AXI_IC_CRRESP => M_AXI_IC_CRRESP,
M_AXI_IC_CDVALID => M_AXI_IC_CDVALID,
M_AXI_IC_CDREADY => M_AXI_IC_CDREADY,
M_AXI_IC_CDDATA => M_AXI_IC_CDDATA,
M_AXI_IC_CDLAST => M_AXI_IC_CDLAST,
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_AWUSER => M_AXI_DC_AWUSER,
M_AXI_DC_AWDOMAIN => M_AXI_DC_AWDOMAIN,
M_AXI_DC_AWSNOOP => M_AXI_DC_AWSNOOP,
M_AXI_DC_AWBAR => M_AXI_DC_AWBAR,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_WUSER => M_AXI_DC_WUSER,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => M_AXI_DC_BUSER,
M_AXI_DC_WACK => M_AXI_DC_WACK,
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_ARUSER => M_AXI_DC_ARUSER,
M_AXI_DC_ARDOMAIN => M_AXI_DC_ARDOMAIN,
M_AXI_DC_ARSNOOP => M_AXI_DC_ARSNOOP,
M_AXI_DC_ARBAR => M_AXI_DC_ARBAR,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => M_AXI_DC_RUSER,
M_AXI_DC_RACK => M_AXI_DC_RACK,
M_AXI_DC_ACVALID => M_AXI_DC_ACVALID,
M_AXI_DC_ACADDR => M_AXI_DC_ACADDR,
M_AXI_DC_ACSNOOP => M_AXI_DC_ACSNOOP,
M_AXI_DC_ACPROT => M_AXI_DC_ACPROT,
M_AXI_DC_ACREADY => M_AXI_DC_ACREADY,
M_AXI_DC_CRREADY => M_AXI_DC_CRREADY,
M_AXI_DC_CRVALID => M_AXI_DC_CRVALID,
M_AXI_DC_CRRESP => M_AXI_DC_CRRESP,
M_AXI_DC_CDVALID => M_AXI_DC_CDVALID,
M_AXI_DC_CDREADY => M_AXI_DC_CDREADY,
M_AXI_DC_CDDATA => M_AXI_DC_CDDATA,
M_AXI_DC_CDLAST => M_AXI_DC_CDLAST,
DBG_CLK => DBG_CLK,
DBG_TDI => DBG_TDI,
DBG_TDO => DBG_TDO,
DBG_REG_EN => DBG_REG_EN,
DBG_SHIFT => DBG_SHIFT,
DBG_CAPTURE => DBG_CAPTURE,
DBG_UPDATE => DBG_UPDATE,
DEBUG_RST => DEBUG_RST,
Trace_Instruction => Trace_Instruction,
Trace_Valid_Instr => Trace_Valid_Instr,
Trace_PC => Trace_PC,
Trace_Reg_Write => Trace_Reg_Write,
Trace_Reg_Addr => Trace_Reg_Addr,
Trace_MSR_Reg => Trace_MSR_Reg,
Trace_PID_Reg => Trace_PID_Reg,
Trace_New_Reg_Value => Trace_New_Reg_Value,
Trace_Exception_Taken => Trace_Exception_Taken,
Trace_Exception_Kind => Trace_Exception_Kind,
Trace_Jump_Taken => Trace_Jump_Taken,
Trace_Delay_Slot => Trace_Delay_Slot,
Trace_Data_Address => Trace_Data_Address,
Trace_Data_Access => Trace_Data_Access,
Trace_Data_Read => Trace_Data_Read,
Trace_Data_Write => Trace_Data_Write,
Trace_Data_Write_Value => Trace_Data_Write_Value,
Trace_Data_Byte_Enable => Trace_Data_Byte_Enable,
Trace_DCache_Req => Trace_DCache_Req,
Trace_DCache_Hit => Trace_DCache_Hit,
Trace_DCache_Rdy => Trace_DCache_Rdy,
Trace_DCache_Read => Trace_DCache_Read,
Trace_ICache_Req => Trace_ICache_Req,
Trace_ICache_Hit => Trace_ICache_Hit,
Trace_ICache_Rdy => Trace_ICache_Rdy,
Trace_OF_PipeRun => Trace_OF_PipeRun,
Trace_EX_PipeRun => Trace_EX_PipeRun,
Trace_MEM_PipeRun => Trace_MEM_PipeRun,
Trace_MB_Halted => Trace_MB_Halted,
Trace_Jump_Hit => Trace_Jump_Hit,
FSL0_S_CLK => FSL0_S_CLK,
FSL0_S_READ => FSL0_S_READ,
FSL0_S_DATA => FSL0_S_DATA,
FSL0_S_CONTROL => FSL0_S_CONTROL,
FSL0_S_EXISTS => FSL0_S_EXISTS,
FSL0_M_CLK => FSL0_M_CLK,
FSL0_M_WRITE => FSL0_M_WRITE,
FSL0_M_DATA => FSL0_M_DATA,
FSL0_M_CONTROL => FSL0_M_CONTROL,
FSL0_M_FULL => FSL0_M_FULL,
FSL1_S_CLK => FSL1_S_CLK,
FSL1_S_READ => FSL1_S_READ,
FSL1_S_DATA => FSL1_S_DATA,
FSL1_S_CONTROL => FSL1_S_CONTROL,
FSL1_S_EXISTS => FSL1_S_EXISTS,
FSL1_M_CLK => FSL1_M_CLK,
FSL1_M_WRITE => FSL1_M_WRITE,
FSL1_M_DATA => FSL1_M_DATA,
FSL1_M_CONTROL => FSL1_M_CONTROL,
FSL1_M_FULL => FSL1_M_FULL,
FSL2_S_CLK => FSL2_S_CLK,
FSL2_S_READ => FSL2_S_READ,
FSL2_S_DATA => FSL2_S_DATA,
FSL2_S_CONTROL => FSL2_S_CONTROL,
FSL2_S_EXISTS => FSL2_S_EXISTS,
FSL2_M_CLK => FSL2_M_CLK,
FSL2_M_WRITE => FSL2_M_WRITE,
FSL2_M_DATA => FSL2_M_DATA,
FSL2_M_CONTROL => FSL2_M_CONTROL,
FSL2_M_FULL => FSL2_M_FULL,
FSL3_S_CLK => FSL3_S_CLK,
FSL3_S_READ => FSL3_S_READ,
FSL3_S_DATA => FSL3_S_DATA,
FSL3_S_CONTROL => FSL3_S_CONTROL,
FSL3_S_EXISTS => FSL3_S_EXISTS,
FSL3_M_CLK => FSL3_M_CLK,
FSL3_M_WRITE => FSL3_M_WRITE,
FSL3_M_DATA => FSL3_M_DATA,
FSL3_M_CONTROL => FSL3_M_CONTROL,
FSL3_M_FULL => FSL3_M_FULL,
FSL4_S_CLK => FSL4_S_CLK,
FSL4_S_READ => FSL4_S_READ,
FSL4_S_DATA => FSL4_S_DATA,
FSL4_S_CONTROL => FSL4_S_CONTROL,
FSL4_S_EXISTS => FSL4_S_EXISTS,
FSL4_M_CLK => FSL4_M_CLK,
FSL4_M_WRITE => FSL4_M_WRITE,
FSL4_M_DATA => FSL4_M_DATA,
FSL4_M_CONTROL => FSL4_M_CONTROL,
FSL4_M_FULL => FSL4_M_FULL,
FSL5_S_CLK => FSL5_S_CLK,
FSL5_S_READ => FSL5_S_READ,
FSL5_S_DATA => FSL5_S_DATA,
FSL5_S_CONTROL => FSL5_S_CONTROL,
FSL5_S_EXISTS => FSL5_S_EXISTS,
FSL5_M_CLK => FSL5_M_CLK,
FSL5_M_WRITE => FSL5_M_WRITE,
FSL5_M_DATA => FSL5_M_DATA,
FSL5_M_CONTROL => FSL5_M_CONTROL,
FSL5_M_FULL => FSL5_M_FULL,
FSL6_S_CLK => FSL6_S_CLK,
FSL6_S_READ => FSL6_S_READ,
FSL6_S_DATA => FSL6_S_DATA,
FSL6_S_CONTROL => FSL6_S_CONTROL,
FSL6_S_EXISTS => FSL6_S_EXISTS,
FSL6_M_CLK => FSL6_M_CLK,
FSL6_M_WRITE => FSL6_M_WRITE,
FSL6_M_DATA => FSL6_M_DATA,
FSL6_M_CONTROL => FSL6_M_CONTROL,
FSL6_M_FULL => FSL6_M_FULL,
FSL7_S_CLK => FSL7_S_CLK,
FSL7_S_READ => FSL7_S_READ,
FSL7_S_DATA => FSL7_S_DATA,
FSL7_S_CONTROL => FSL7_S_CONTROL,
FSL7_S_EXISTS => FSL7_S_EXISTS,
FSL7_M_CLK => FSL7_M_CLK,
FSL7_M_WRITE => FSL7_M_WRITE,
FSL7_M_DATA => FSL7_M_DATA,
FSL7_M_CONTROL => FSL7_M_CONTROL,
FSL7_M_FULL => FSL7_M_FULL,
FSL8_S_CLK => FSL8_S_CLK,
FSL8_S_READ => FSL8_S_READ,
FSL8_S_DATA => FSL8_S_DATA,
FSL8_S_CONTROL => FSL8_S_CONTROL,
FSL8_S_EXISTS => FSL8_S_EXISTS,
FSL8_M_CLK => FSL8_M_CLK,
FSL8_M_WRITE => FSL8_M_WRITE,
FSL8_M_DATA => FSL8_M_DATA,
FSL8_M_CONTROL => FSL8_M_CONTROL,
FSL8_M_FULL => FSL8_M_FULL,
FSL9_S_CLK => FSL9_S_CLK,
FSL9_S_READ => FSL9_S_READ,
FSL9_S_DATA => FSL9_S_DATA,
FSL9_S_CONTROL => FSL9_S_CONTROL,
FSL9_S_EXISTS => FSL9_S_EXISTS,
FSL9_M_CLK => FSL9_M_CLK,
FSL9_M_WRITE => FSL9_M_WRITE,
FSL9_M_DATA => FSL9_M_DATA,
FSL9_M_CONTROL => FSL9_M_CONTROL,
FSL9_M_FULL => FSL9_M_FULL,
FSL10_S_CLK => FSL10_S_CLK,
FSL10_S_READ => FSL10_S_READ,
FSL10_S_DATA => FSL10_S_DATA,
FSL10_S_CONTROL => FSL10_S_CONTROL,
FSL10_S_EXISTS => FSL10_S_EXISTS,
FSL10_M_CLK => FSL10_M_CLK,
FSL10_M_WRITE => FSL10_M_WRITE,
FSL10_M_DATA => FSL10_M_DATA,
FSL10_M_CONTROL => FSL10_M_CONTROL,
FSL10_M_FULL => FSL10_M_FULL,
FSL11_S_CLK => FSL11_S_CLK,
FSL11_S_READ => FSL11_S_READ,
FSL11_S_DATA => FSL11_S_DATA,
FSL11_S_CONTROL => FSL11_S_CONTROL,
FSL11_S_EXISTS => FSL11_S_EXISTS,
FSL11_M_CLK => FSL11_M_CLK,
FSL11_M_WRITE => FSL11_M_WRITE,
FSL11_M_DATA => FSL11_M_DATA,
FSL11_M_CONTROL => FSL11_M_CONTROL,
FSL11_M_FULL => FSL11_M_FULL,
FSL12_S_CLK => FSL12_S_CLK,
FSL12_S_READ => FSL12_S_READ,
FSL12_S_DATA => FSL12_S_DATA,
FSL12_S_CONTROL => FSL12_S_CONTROL,
FSL12_S_EXISTS => FSL12_S_EXISTS,
FSL12_M_CLK => FSL12_M_CLK,
FSL12_M_WRITE => FSL12_M_WRITE,
FSL12_M_DATA => FSL12_M_DATA,
FSL12_M_CONTROL => FSL12_M_CONTROL,
FSL12_M_FULL => FSL12_M_FULL,
FSL13_S_CLK => FSL13_S_CLK,
FSL13_S_READ => FSL13_S_READ,
FSL13_S_DATA => FSL13_S_DATA,
FSL13_S_CONTROL => FSL13_S_CONTROL,
FSL13_S_EXISTS => FSL13_S_EXISTS,
FSL13_M_CLK => FSL13_M_CLK,
FSL13_M_WRITE => FSL13_M_WRITE,
FSL13_M_DATA => FSL13_M_DATA,
FSL13_M_CONTROL => FSL13_M_CONTROL,
FSL13_M_FULL => FSL13_M_FULL,
FSL14_S_CLK => FSL14_S_CLK,
FSL14_S_READ => FSL14_S_READ,
FSL14_S_DATA => FSL14_S_DATA,
FSL14_S_CONTROL => FSL14_S_CONTROL,
FSL14_S_EXISTS => FSL14_S_EXISTS,
FSL14_M_CLK => FSL14_M_CLK,
FSL14_M_WRITE => FSL14_M_WRITE,
FSL14_M_DATA => FSL14_M_DATA,
FSL14_M_CONTROL => FSL14_M_CONTROL,
FSL14_M_FULL => FSL14_M_FULL,
FSL15_S_CLK => FSL15_S_CLK,
FSL15_S_READ => FSL15_S_READ,
FSL15_S_DATA => FSL15_S_DATA,
FSL15_S_CONTROL => FSL15_S_CONTROL,
FSL15_S_EXISTS => FSL15_S_EXISTS,
FSL15_M_CLK => FSL15_M_CLK,
FSL15_M_WRITE => FSL15_M_WRITE,
FSL15_M_DATA => FSL15_M_DATA,
FSL15_M_CONTROL => FSL15_M_CONTROL,
FSL15_M_FULL => FSL15_M_FULL,
M0_AXIS_TLAST => M0_AXIS_TLAST,
M0_AXIS_TDATA => M0_AXIS_TDATA,
M0_AXIS_TVALID => M0_AXIS_TVALID,
M0_AXIS_TREADY => M0_AXIS_TREADY,
S0_AXIS_TLAST => S0_AXIS_TLAST,
S0_AXIS_TDATA => S0_AXIS_TDATA,
S0_AXIS_TVALID => S0_AXIS_TVALID,
S0_AXIS_TREADY => S0_AXIS_TREADY,
M1_AXIS_TLAST => M1_AXIS_TLAST,
M1_AXIS_TDATA => M1_AXIS_TDATA,
M1_AXIS_TVALID => M1_AXIS_TVALID,
M1_AXIS_TREADY => M1_AXIS_TREADY,
S1_AXIS_TLAST => S1_AXIS_TLAST,
S1_AXIS_TDATA => S1_AXIS_TDATA,
S1_AXIS_TVALID => S1_AXIS_TVALID,
S1_AXIS_TREADY => S1_AXIS_TREADY,
M2_AXIS_TLAST => M2_AXIS_TLAST,
M2_AXIS_TDATA => M2_AXIS_TDATA,
M2_AXIS_TVALID => M2_AXIS_TVALID,
M2_AXIS_TREADY => M2_AXIS_TREADY,
S2_AXIS_TLAST => S2_AXIS_TLAST,
S2_AXIS_TDATA => S2_AXIS_TDATA,
S2_AXIS_TVALID => S2_AXIS_TVALID,
S2_AXIS_TREADY => S2_AXIS_TREADY,
M3_AXIS_TLAST => M3_AXIS_TLAST,
M3_AXIS_TDATA => M3_AXIS_TDATA,
M3_AXIS_TVALID => M3_AXIS_TVALID,
M3_AXIS_TREADY => M3_AXIS_TREADY,
S3_AXIS_TLAST => S3_AXIS_TLAST,
S3_AXIS_TDATA => S3_AXIS_TDATA,
S3_AXIS_TVALID => S3_AXIS_TVALID,
S3_AXIS_TREADY => S3_AXIS_TREADY,
M4_AXIS_TLAST => M4_AXIS_TLAST,
M4_AXIS_TDATA => M4_AXIS_TDATA,
M4_AXIS_TVALID => M4_AXIS_TVALID,
M4_AXIS_TREADY => M4_AXIS_TREADY,
S4_AXIS_TLAST => S4_AXIS_TLAST,
S4_AXIS_TDATA => S4_AXIS_TDATA,
S4_AXIS_TVALID => S4_AXIS_TVALID,
S4_AXIS_TREADY => S4_AXIS_TREADY,
M5_AXIS_TLAST => M5_AXIS_TLAST,
M5_AXIS_TDATA => M5_AXIS_TDATA,
M5_AXIS_TVALID => M5_AXIS_TVALID,
M5_AXIS_TREADY => M5_AXIS_TREADY,
S5_AXIS_TLAST => S5_AXIS_TLAST,
S5_AXIS_TDATA => S5_AXIS_TDATA,
S5_AXIS_TVALID => S5_AXIS_TVALID,
S5_AXIS_TREADY => S5_AXIS_TREADY,
M6_AXIS_TLAST => M6_AXIS_TLAST,
M6_AXIS_TDATA => M6_AXIS_TDATA,
M6_AXIS_TVALID => M6_AXIS_TVALID,
M6_AXIS_TREADY => M6_AXIS_TREADY,
S6_AXIS_TLAST => S6_AXIS_TLAST,
S6_AXIS_TDATA => S6_AXIS_TDATA,
S6_AXIS_TVALID => S6_AXIS_TVALID,
S6_AXIS_TREADY => S6_AXIS_TREADY,
M7_AXIS_TLAST => M7_AXIS_TLAST,
M7_AXIS_TDATA => M7_AXIS_TDATA,
M7_AXIS_TVALID => M7_AXIS_TVALID,
M7_AXIS_TREADY => M7_AXIS_TREADY,
S7_AXIS_TLAST => S7_AXIS_TLAST,
S7_AXIS_TDATA => S7_AXIS_TDATA,
S7_AXIS_TVALID => S7_AXIS_TVALID,
S7_AXIS_TREADY => S7_AXIS_TREADY,
M8_AXIS_TLAST => M8_AXIS_TLAST,
M8_AXIS_TDATA => M8_AXIS_TDATA,
M8_AXIS_TVALID => M8_AXIS_TVALID,
M8_AXIS_TREADY => M8_AXIS_TREADY,
S8_AXIS_TLAST => S8_AXIS_TLAST,
S8_AXIS_TDATA => S8_AXIS_TDATA,
S8_AXIS_TVALID => S8_AXIS_TVALID,
S8_AXIS_TREADY => S8_AXIS_TREADY,
M9_AXIS_TLAST => M9_AXIS_TLAST,
M9_AXIS_TDATA => M9_AXIS_TDATA,
M9_AXIS_TVALID => M9_AXIS_TVALID,
M9_AXIS_TREADY => M9_AXIS_TREADY,
S9_AXIS_TLAST => S9_AXIS_TLAST,
S9_AXIS_TDATA => S9_AXIS_TDATA,
S9_AXIS_TVALID => S9_AXIS_TVALID,
S9_AXIS_TREADY => S9_AXIS_TREADY,
M10_AXIS_TLAST => M10_AXIS_TLAST,
M10_AXIS_TDATA => M10_AXIS_TDATA,
M10_AXIS_TVALID => M10_AXIS_TVALID,
M10_AXIS_TREADY => M10_AXIS_TREADY,
S10_AXIS_TLAST => S10_AXIS_TLAST,
S10_AXIS_TDATA => S10_AXIS_TDATA,
S10_AXIS_TVALID => S10_AXIS_TVALID,
S10_AXIS_TREADY => S10_AXIS_TREADY,
M11_AXIS_TLAST => M11_AXIS_TLAST,
M11_AXIS_TDATA => M11_AXIS_TDATA,
M11_AXIS_TVALID => M11_AXIS_TVALID,
M11_AXIS_TREADY => M11_AXIS_TREADY,
S11_AXIS_TLAST => S11_AXIS_TLAST,
S11_AXIS_TDATA => S11_AXIS_TDATA,
S11_AXIS_TVALID => S11_AXIS_TVALID,
S11_AXIS_TREADY => S11_AXIS_TREADY,
M12_AXIS_TLAST => M12_AXIS_TLAST,
M12_AXIS_TDATA => M12_AXIS_TDATA,
M12_AXIS_TVALID => M12_AXIS_TVALID,
M12_AXIS_TREADY => M12_AXIS_TREADY,
S12_AXIS_TLAST => S12_AXIS_TLAST,
S12_AXIS_TDATA => S12_AXIS_TDATA,
S12_AXIS_TVALID => S12_AXIS_TVALID,
S12_AXIS_TREADY => S12_AXIS_TREADY,
M13_AXIS_TLAST => M13_AXIS_TLAST,
M13_AXIS_TDATA => M13_AXIS_TDATA,
M13_AXIS_TVALID => M13_AXIS_TVALID,
M13_AXIS_TREADY => M13_AXIS_TREADY,
S13_AXIS_TLAST => S13_AXIS_TLAST,
S13_AXIS_TDATA => S13_AXIS_TDATA,
S13_AXIS_TVALID => S13_AXIS_TVALID,
S13_AXIS_TREADY => S13_AXIS_TREADY,
M14_AXIS_TLAST => M14_AXIS_TLAST,
M14_AXIS_TDATA => M14_AXIS_TDATA,
M14_AXIS_TVALID => M14_AXIS_TVALID,
M14_AXIS_TREADY => M14_AXIS_TREADY,
S14_AXIS_TLAST => S14_AXIS_TLAST,
S14_AXIS_TDATA => S14_AXIS_TDATA,
S14_AXIS_TVALID => S14_AXIS_TVALID,
S14_AXIS_TREADY => S14_AXIS_TREADY,
M15_AXIS_TLAST => M15_AXIS_TLAST,
M15_AXIS_TDATA => M15_AXIS_TDATA,
M15_AXIS_TVALID => M15_AXIS_TVALID,
M15_AXIS_TREADY => M15_AXIS_TREADY,
S15_AXIS_TLAST => S15_AXIS_TLAST,
S15_AXIS_TDATA => S15_AXIS_TDATA,
S15_AXIS_TVALID => S15_AXIS_TVALID,
S15_AXIS_TREADY => S15_AXIS_TREADY,
ICACHE_FSL_IN_CLK => ICACHE_FSL_IN_CLK,
ICACHE_FSL_IN_READ => ICACHE_FSL_IN_READ,
ICACHE_FSL_IN_DATA => ICACHE_FSL_IN_DATA,
ICACHE_FSL_IN_CONTROL => ICACHE_FSL_IN_CONTROL,
ICACHE_FSL_IN_EXISTS => ICACHE_FSL_IN_EXISTS,
ICACHE_FSL_OUT_CLK => ICACHE_FSL_OUT_CLK,
ICACHE_FSL_OUT_WRITE => ICACHE_FSL_OUT_WRITE,
ICACHE_FSL_OUT_DATA => ICACHE_FSL_OUT_DATA,
ICACHE_FSL_OUT_CONTROL => ICACHE_FSL_OUT_CONTROL,
ICACHE_FSL_OUT_FULL => ICACHE_FSL_OUT_FULL,
DCACHE_FSL_IN_CLK => DCACHE_FSL_IN_CLK,
DCACHE_FSL_IN_READ => DCACHE_FSL_IN_READ,
DCACHE_FSL_IN_DATA => DCACHE_FSL_IN_DATA,
DCACHE_FSL_IN_CONTROL => DCACHE_FSL_IN_CONTROL,
DCACHE_FSL_IN_EXISTS => DCACHE_FSL_IN_EXISTS,
DCACHE_FSL_OUT_CLK => DCACHE_FSL_OUT_CLK,
DCACHE_FSL_OUT_WRITE => DCACHE_FSL_OUT_WRITE,
DCACHE_FSL_OUT_DATA => DCACHE_FSL_OUT_DATA,
DCACHE_FSL_OUT_CONTROL => DCACHE_FSL_OUT_CONTROL,
DCACHE_FSL_OUT_FULL => DCACHE_FSL_OUT_FULL
);
end architecture STRUCTURE;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net8,
G => vbias4,
S => gnd
);
end simple;
|
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity nbit_encoder is
generic(
numInputs: integer:=4
);
port(
enable: in std_logic;
inputVector: in std_logic_vector(numInputs -1 downto 0);
outputVector: out std_logic_vector(integer(log2(Real(numInputs))) -1 downto 0)
);
end nbit_encoder;
architecture primary of nbit_encoder is
signal outputTemp: std_logic_vector(integer(log2(Real(numInputs))) -1 downto 0);
begin
process(enable,inputVector,outputTemp)
begin
if(enable = '1') then
outputTemp <= (others=>'0');
for num in 0 to numInputs-1 loop
if(inputVector(num) = '1') then
outputTemp <= std_logic_vector((to_unsigned(num, integer(log2(Real(numInputs))))));
end if;
end loop;
else
outputTemp <= (others=>'0');
end if
end process;
outputVector<=outputTemp;
end primary;
|
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_model.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_core.vhd
--
-- Description: Simple testbench for ac97_core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:34 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_ac97_core is
end TESTBENCH_ac97_core;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.TESTBENCH_ac97_package.all;
architecture behavioral of TESTBENCH_ac97_core is
component ac97_core
generic (
C_PLAYBACK : integer := 1;
C_RECORD : integer := 1;
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Data_Valid : out std_logic;
AC97_Reg_Read : in std_logic;
AC97_Reg_Write : in std_logic;
AC97_Reg_Ready : out std_logic;
PCM_Playback_Left: in std_logic_vector(0 to 15);
PCM_Playback_Right: in std_logic_vector(0 to 15);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Record_Left: out std_logic_vector(0 to 15);
PCM_Record_Right: out std_logic_vector(0 to 15);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
New_Frame : out std_logic;
CODEC_RDY : out std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal reset : std_logic;
signal ac97_reset : std_logic;
signal clk : std_logic;
signal sync : std_logic;
signal sdata_out : std_logic;
signal sdata_in : std_logic;
signal reg_addr : std_logic_vector(0 to 6);
signal reg_write_data : std_logic_vector(0 to 15);
signal reg_read_data : std_logic_vector(0 to 15);
signal reg_read_data_valid : std_logic;
signal reg_read : std_logic;
signal reg_write : std_logic;
signal reg_ready : std_logic;
signal PCM_Playback_Left: std_logic_vector(0 to 15);
signal PCM_Playback_Right: std_logic_vector(0 to 15);
signal PCM_Playback_Left_Valid: std_logic;
signal PCM_Playback_Right_Valid: std_logic;
signal PCM_Record_Left: std_logic_vector(0 to 15);
signal PCM_Record_Right: std_logic_vector(0 to 15);
signal PCM_Record_Left_Valid: std_logic;
signal PCM_Record_Right_Valid: std_logic;
signal New_Frame : std_logic;
signal CODEC_RDY : std_logic;
signal test_no : integer;
begin -- behavioral
ac97_reset <= not reset;
uut_1 : ac97_model
port map (
AC97Reset_n => ac97_reset,
Bit_Clk => clk,
Sync => sync,
SData_Out => sdata_out,
SData_In => sdata_in
);
uut: ac97_core
generic map (
C_PLAYBACK => 1,
C_RECORD => 1
)
port map (
Reset => reset,
-- signals attaching directly to AC97 codec
AC97_Bit_Clk => clk,
AC97_Sync => sync,
AC97_SData_Out => sdata_out,
AC97_SData_In => sdata_in,
AC97_Reg_Addr => reg_addr,
AC97_Reg_Write_Data => reg_write_data,
AC97_Reg_Read_Data => reg_read_data,
AC97_Reg_Read_Data_Valid => reg_read_data_valid,
AC97_Reg_Read => reg_read,
AC97_Reg_Write => reg_write,
AC97_Reg_Ready => reg_ready,
PCM_Playback_Left => PCM_Playback_Left,
PCM_Playback_Right => PCM_Playback_Right,
PCM_Playback_Left_Valid => PCM_Playback_Left_Valid,
PCM_Playback_Right_Valid => PCM_Playback_Right_Valid,
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => PCM_Record_Left_Valid,
PCM_Record_Right_Valid => PCM_Record_Right_Valid,
New_Frame => New_Frame,
CODEC_RDY => CODEC_RDY
);
-- simulate a reset
opb_rst_gen: process
begin
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process opb_rst_gen;
-- Test process
test_process: process
begin
test_no <= 0;
-- set default values
reg_addr <= (others => '0');
reg_write_data <= (others => '0');
reg_read <= '0';
reg_write <= '0';
PCM_Playback_Left <= (others => '0');
PCM_Playback_Right <= (others => '0');
PCM_Playback_Left_Valid <= '0';
PCM_Playback_Right_Valid <= '0';
-- 1. Wait until CODEC ready before doing anything
wait until CODEC_RDY='1' and clk'event and clk='1';
-- skip some time slots before performing a bus cycle
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
-- Start at first sync pulse
wait until Sync'event and Sync='1';
--wait until clk'event and clk='1';
wait until clk'event and clk='1';
test_no <= 1;
-- send some playback data
PCM_Playback_Left <= X"8001";
PCM_Playback_Right <= X"0180";
PCM_Playback_Left_Valid <= '1';
PCM_Playback_Right_Valid <= '1';
wait until New_Frame'event and New_Frame='0';
test_no <= 2;
PCM_Playback_Left <= X"4002";
PCM_Playback_Right <= X"0240";
wait until New_Frame'event and New_Frame='0';
test_no <= 3;
-- send a read command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_read <= '1';
wait until New_Frame'event and New_Frame='0';
reg_read <= '0';
wait;
-- send a write command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_write_data <= X"5A5A";
reg_write <= '1';
wait until New_Frame'event and New_Frame='0';
wait;
end process;
-- -- Recording Data
-- sdata_in_proc: process
-- variable slot0 : std_logic_vector(15 downto 0) := "1001100000000000";
-- -- Control address
-- variable slot1 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- Control data
-- variable slot2 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- PCM left (0x69696)
-- variable slot3 : std_logic_vector(19 downto 0) := "01101001011010010110";
-- -- PCM right (0x96969)
-- variable slot4 : std_logic_vector(19 downto 0) := "10010110100101101001";
-- begin
-- sdata_in <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- -- (1) record data
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (2) record data
-- slot3 := X"8001_0";
-- slot4 := X"1234_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (3) record data
-- slot3 := X"4002_0";
-- slot4 := X"2345_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (4) record data & some control data
-- slot3 := X"2004_0";
-- slot4 := X"3456_0";
-- slot0 := "1011100000000000";
-- slot2 := X"FEDC_B";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (5) record data
-- slot3 := X"1008_0";
-- slot4 := X"3456_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- wait;
-- end process;
-- -- Recording Data
-- control_proc: process
-- begin
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- skip 2 frames
-- for i in 1 downto 0 loop
-- wait until New_Frame'event and New_Frame='0';
-- end loop;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_write <= '0';
-- PCM_Playback_Left <= X"1008";
-- PCM_Playback_Right <= X"0810";
-- wait;
-- end process;
end behavioral;
|
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_model.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_core.vhd
--
-- Description: Simple testbench for ac97_core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:34 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_ac97_core is
end TESTBENCH_ac97_core;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.TESTBENCH_ac97_package.all;
architecture behavioral of TESTBENCH_ac97_core is
component ac97_core
generic (
C_PLAYBACK : integer := 1;
C_RECORD : integer := 1;
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Data_Valid : out std_logic;
AC97_Reg_Read : in std_logic;
AC97_Reg_Write : in std_logic;
AC97_Reg_Ready : out std_logic;
PCM_Playback_Left: in std_logic_vector(0 to 15);
PCM_Playback_Right: in std_logic_vector(0 to 15);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Record_Left: out std_logic_vector(0 to 15);
PCM_Record_Right: out std_logic_vector(0 to 15);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
New_Frame : out std_logic;
CODEC_RDY : out std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal reset : std_logic;
signal ac97_reset : std_logic;
signal clk : std_logic;
signal sync : std_logic;
signal sdata_out : std_logic;
signal sdata_in : std_logic;
signal reg_addr : std_logic_vector(0 to 6);
signal reg_write_data : std_logic_vector(0 to 15);
signal reg_read_data : std_logic_vector(0 to 15);
signal reg_read_data_valid : std_logic;
signal reg_read : std_logic;
signal reg_write : std_logic;
signal reg_ready : std_logic;
signal PCM_Playback_Left: std_logic_vector(0 to 15);
signal PCM_Playback_Right: std_logic_vector(0 to 15);
signal PCM_Playback_Left_Valid: std_logic;
signal PCM_Playback_Right_Valid: std_logic;
signal PCM_Record_Left: std_logic_vector(0 to 15);
signal PCM_Record_Right: std_logic_vector(0 to 15);
signal PCM_Record_Left_Valid: std_logic;
signal PCM_Record_Right_Valid: std_logic;
signal New_Frame : std_logic;
signal CODEC_RDY : std_logic;
signal test_no : integer;
begin -- behavioral
ac97_reset <= not reset;
uut_1 : ac97_model
port map (
AC97Reset_n => ac97_reset,
Bit_Clk => clk,
Sync => sync,
SData_Out => sdata_out,
SData_In => sdata_in
);
uut: ac97_core
generic map (
C_PLAYBACK => 1,
C_RECORD => 1
)
port map (
Reset => reset,
-- signals attaching directly to AC97 codec
AC97_Bit_Clk => clk,
AC97_Sync => sync,
AC97_SData_Out => sdata_out,
AC97_SData_In => sdata_in,
AC97_Reg_Addr => reg_addr,
AC97_Reg_Write_Data => reg_write_data,
AC97_Reg_Read_Data => reg_read_data,
AC97_Reg_Read_Data_Valid => reg_read_data_valid,
AC97_Reg_Read => reg_read,
AC97_Reg_Write => reg_write,
AC97_Reg_Ready => reg_ready,
PCM_Playback_Left => PCM_Playback_Left,
PCM_Playback_Right => PCM_Playback_Right,
PCM_Playback_Left_Valid => PCM_Playback_Left_Valid,
PCM_Playback_Right_Valid => PCM_Playback_Right_Valid,
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => PCM_Record_Left_Valid,
PCM_Record_Right_Valid => PCM_Record_Right_Valid,
New_Frame => New_Frame,
CODEC_RDY => CODEC_RDY
);
-- simulate a reset
opb_rst_gen: process
begin
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process opb_rst_gen;
-- Test process
test_process: process
begin
test_no <= 0;
-- set default values
reg_addr <= (others => '0');
reg_write_data <= (others => '0');
reg_read <= '0';
reg_write <= '0';
PCM_Playback_Left <= (others => '0');
PCM_Playback_Right <= (others => '0');
PCM_Playback_Left_Valid <= '0';
PCM_Playback_Right_Valid <= '0';
-- 1. Wait until CODEC ready before doing anything
wait until CODEC_RDY='1' and clk'event and clk='1';
-- skip some time slots before performing a bus cycle
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
-- Start at first sync pulse
wait until Sync'event and Sync='1';
--wait until clk'event and clk='1';
wait until clk'event and clk='1';
test_no <= 1;
-- send some playback data
PCM_Playback_Left <= X"8001";
PCM_Playback_Right <= X"0180";
PCM_Playback_Left_Valid <= '1';
PCM_Playback_Right_Valid <= '1';
wait until New_Frame'event and New_Frame='0';
test_no <= 2;
PCM_Playback_Left <= X"4002";
PCM_Playback_Right <= X"0240";
wait until New_Frame'event and New_Frame='0';
test_no <= 3;
-- send a read command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_read <= '1';
wait until New_Frame'event and New_Frame='0';
reg_read <= '0';
wait;
-- send a write command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_write_data <= X"5A5A";
reg_write <= '1';
wait until New_Frame'event and New_Frame='0';
wait;
end process;
-- -- Recording Data
-- sdata_in_proc: process
-- variable slot0 : std_logic_vector(15 downto 0) := "1001100000000000";
-- -- Control address
-- variable slot1 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- Control data
-- variable slot2 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- PCM left (0x69696)
-- variable slot3 : std_logic_vector(19 downto 0) := "01101001011010010110";
-- -- PCM right (0x96969)
-- variable slot4 : std_logic_vector(19 downto 0) := "10010110100101101001";
-- begin
-- sdata_in <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- -- (1) record data
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (2) record data
-- slot3 := X"8001_0";
-- slot4 := X"1234_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (3) record data
-- slot3 := X"4002_0";
-- slot4 := X"2345_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (4) record data & some control data
-- slot3 := X"2004_0";
-- slot4 := X"3456_0";
-- slot0 := "1011100000000000";
-- slot2 := X"FEDC_B";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (5) record data
-- slot3 := X"1008_0";
-- slot4 := X"3456_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- wait;
-- end process;
-- -- Recording Data
-- control_proc: process
-- begin
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- skip 2 frames
-- for i in 1 downto 0 loop
-- wait until New_Frame'event and New_Frame='0';
-- end loop;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_write <= '0';
-- PCM_Playback_Left <= X"1008";
-- PCM_Playback_Right <= X"0810";
-- wait;
-- end process;
end behavioral;
|
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_model.vhd,v 1.1 2005/02/17 20:29:34 crh Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_core.vhd
--
-- Description: Simple testbench for ac97_core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:34 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_ac97_core is
end TESTBENCH_ac97_core;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.TESTBENCH_ac97_package.all;
architecture behavioral of TESTBENCH_ac97_core is
component ac97_core
generic (
C_PLAYBACK : integer := 1;
C_RECORD : integer := 1;
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Data_Valid : out std_logic;
AC97_Reg_Read : in std_logic;
AC97_Reg_Write : in std_logic;
AC97_Reg_Ready : out std_logic;
PCM_Playback_Left: in std_logic_vector(0 to 15);
PCM_Playback_Right: in std_logic_vector(0 to 15);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Record_Left: out std_logic_vector(0 to 15);
PCM_Record_Right: out std_logic_vector(0 to 15);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
New_Frame : out std_logic;
CODEC_RDY : out std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal reset : std_logic;
signal ac97_reset : std_logic;
signal clk : std_logic;
signal sync : std_logic;
signal sdata_out : std_logic;
signal sdata_in : std_logic;
signal reg_addr : std_logic_vector(0 to 6);
signal reg_write_data : std_logic_vector(0 to 15);
signal reg_read_data : std_logic_vector(0 to 15);
signal reg_read_data_valid : std_logic;
signal reg_read : std_logic;
signal reg_write : std_logic;
signal reg_ready : std_logic;
signal PCM_Playback_Left: std_logic_vector(0 to 15);
signal PCM_Playback_Right: std_logic_vector(0 to 15);
signal PCM_Playback_Left_Valid: std_logic;
signal PCM_Playback_Right_Valid: std_logic;
signal PCM_Record_Left: std_logic_vector(0 to 15);
signal PCM_Record_Right: std_logic_vector(0 to 15);
signal PCM_Record_Left_Valid: std_logic;
signal PCM_Record_Right_Valid: std_logic;
signal New_Frame : std_logic;
signal CODEC_RDY : std_logic;
signal test_no : integer;
begin -- behavioral
ac97_reset <= not reset;
uut_1 : ac97_model
port map (
AC97Reset_n => ac97_reset,
Bit_Clk => clk,
Sync => sync,
SData_Out => sdata_out,
SData_In => sdata_in
);
uut: ac97_core
generic map (
C_PLAYBACK => 1,
C_RECORD => 1
)
port map (
Reset => reset,
-- signals attaching directly to AC97 codec
AC97_Bit_Clk => clk,
AC97_Sync => sync,
AC97_SData_Out => sdata_out,
AC97_SData_In => sdata_in,
AC97_Reg_Addr => reg_addr,
AC97_Reg_Write_Data => reg_write_data,
AC97_Reg_Read_Data => reg_read_data,
AC97_Reg_Read_Data_Valid => reg_read_data_valid,
AC97_Reg_Read => reg_read,
AC97_Reg_Write => reg_write,
AC97_Reg_Ready => reg_ready,
PCM_Playback_Left => PCM_Playback_Left,
PCM_Playback_Right => PCM_Playback_Right,
PCM_Playback_Left_Valid => PCM_Playback_Left_Valid,
PCM_Playback_Right_Valid => PCM_Playback_Right_Valid,
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => PCM_Record_Left_Valid,
PCM_Record_Right_Valid => PCM_Record_Right_Valid,
New_Frame => New_Frame,
CODEC_RDY => CODEC_RDY
);
-- simulate a reset
opb_rst_gen: process
begin
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process opb_rst_gen;
-- Test process
test_process: process
begin
test_no <= 0;
-- set default values
reg_addr <= (others => '0');
reg_write_data <= (others => '0');
reg_read <= '0';
reg_write <= '0';
PCM_Playback_Left <= (others => '0');
PCM_Playback_Right <= (others => '0');
PCM_Playback_Left_Valid <= '0';
PCM_Playback_Right_Valid <= '0';
-- 1. Wait until CODEC ready before doing anything
wait until CODEC_RDY='1' and clk'event and clk='1';
-- skip some time slots before performing a bus cycle
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
-- Start at first sync pulse
wait until Sync'event and Sync='1';
--wait until clk'event and clk='1';
wait until clk'event and clk='1';
test_no <= 1;
-- send some playback data
PCM_Playback_Left <= X"8001";
PCM_Playback_Right <= X"0180";
PCM_Playback_Left_Valid <= '1';
PCM_Playback_Right_Valid <= '1';
wait until New_Frame'event and New_Frame='0';
test_no <= 2;
PCM_Playback_Left <= X"4002";
PCM_Playback_Right <= X"0240";
wait until New_Frame'event and New_Frame='0';
test_no <= 3;
-- send a read command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_read <= '1';
wait until New_Frame'event and New_Frame='0';
reg_read <= '0';
wait;
-- send a write command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_write_data <= X"5A5A";
reg_write <= '1';
wait until New_Frame'event and New_Frame='0';
wait;
end process;
-- -- Recording Data
-- sdata_in_proc: process
-- variable slot0 : std_logic_vector(15 downto 0) := "1001100000000000";
-- -- Control address
-- variable slot1 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- Control data
-- variable slot2 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- PCM left (0x69696)
-- variable slot3 : std_logic_vector(19 downto 0) := "01101001011010010110";
-- -- PCM right (0x96969)
-- variable slot4 : std_logic_vector(19 downto 0) := "10010110100101101001";
-- begin
-- sdata_in <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- -- (1) record data
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (2) record data
-- slot3 := X"8001_0";
-- slot4 := X"1234_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (3) record data
-- slot3 := X"4002_0";
-- slot4 := X"2345_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (4) record data & some control data
-- slot3 := X"2004_0";
-- slot4 := X"3456_0";
-- slot0 := "1011100000000000";
-- slot2 := X"FEDC_B";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (5) record data
-- slot3 := X"1008_0";
-- slot4 := X"3456_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- wait;
-- end process;
-- -- Recording Data
-- control_proc: process
-- begin
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- skip 2 frames
-- for i in 1 downto 0 loop
-- wait until New_Frame'event and New_Frame='0';
-- end loop;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_write <= '0';
-- PCM_Playback_Left <= X"1008";
-- PCM_Playback_Right <= X"0810";
-- wait;
-- end process;
end behavioral;
|
---------------------------------------------------------------------------------------------------
--
-- Title : Shift Reg
-- Design : Common Module
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : shiftReg.vhd
-- Generated : 2013/9/4
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : shift reg
--
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--Library synplify;
entity ShiftReg is
generic(
width : integer;
depth : integer
);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector(width-1 downto 0);
Q : out std_logic_vector(width-1 downto 0) := ( others => '0' );
S : out std_logic_vector(width-1 downto 0)
);
end ShiftReg;
architecture behave of ShiftReg is
type ram_memtype is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal mem : ram_memtype := (others => (others => '0'));
-- attribute syn_srlstyle of mem : signal is "no_rw_check";
-- attribute syn_srlstyle of mem : signal is "select_srl";
-- synthesis syn_ramstyle = "no_rw_check";
begin
mem(0) <= D;
process(clk)
begin
if rising_edge(clk) then
if ce = '1' then
mem(depth downto 1) <= mem(depth-1 downto 0);
Q <= mem (depth-1);
end if;
end if;
end process;
S <= mem(depth);
end behave; |
---------------------------------------------------------------------------------------------------
--
-- Title : Shift Reg
-- Design : Common Module
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : shiftReg.vhd
-- Generated : 2013/9/4
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : shift reg
--
---------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--Library synplify;
entity ShiftReg is
generic(
width : integer;
depth : integer
);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector(width-1 downto 0);
Q : out std_logic_vector(width-1 downto 0) := ( others => '0' );
S : out std_logic_vector(width-1 downto 0)
);
end ShiftReg;
architecture behave of ShiftReg is
type ram_memtype is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal mem : ram_memtype := (others => (others => '0'));
-- attribute syn_srlstyle of mem : signal is "no_rw_check";
-- attribute syn_srlstyle of mem : signal is "select_srl";
-- synthesis syn_ramstyle = "no_rw_check";
begin
mem(0) <= D;
process(clk)
begin
if rising_edge(clk) then
if ce = '1' then
mem(depth downto 1) <= mem(depth-1 downto 0);
Q <= mem (depth-1);
end if;
end if;
end process;
S <= mem(depth);
end behave; |
library IEEE;
use IEEE.std_logic_1164.all;
architecture behavior of truth_table is
begin
O<= (not D and C) or (D and not C) or A or B ;
end behavior;
|
library IEEE;
use IEEE.std_logic_1164.all;
architecture behavior of truth_table is
begin
O<= (not D and C) or (D and not C) or A or B ;
end behavior;
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_19 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_19 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(8 downto 0);
variable rTemp2 : SIGNED(8 downto 0);
variable rTemp3 : SIGNED(8 downto 0);
variable rTemp4 : SIGNED(8 downto 0);
variable vTemp1 : std_logic_vector(7 downto 0);
variable vTemp2 : std_logic_vector(7 downto 0);
variable vTemp3 : std_logic_vector(7 downto 0);
variable vTemp4 : std_logic_vector(7 downto 0);
begin
rTemp1 := RESIZE( SIGNED(INPUT_1( 7 downto 0)), 9) + RESIZE( SIGNED(INPUT_2( 7 downto 0)), 9);
rTemp2 := RESIZE( SIGNED(INPUT_1(15 downto 8)), 9) + RESIZE( SIGNED(INPUT_2(15 downto 8)), 9);
rTemp3 := RESIZE( SIGNED(INPUT_1(23 downto 16)), 9) + RESIZE( SIGNED(INPUT_2(23 downto 16)), 9);
rTemp4 := RESIZE( SIGNED(INPUT_1(31 downto 24)), 9) + RESIZE( SIGNED(INPUT_2(31 downto 24)), 9);
if ( rTemp1 > TO_SIGNED(+127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp1 < TO_SIGNED(-127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp1 := STD_LOGIC_VECTOR(rTemp1(7 downto 0));
end if;
if ( rTemp2 > TO_SIGNED(+127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp2 < TO_SIGNED(-127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp2 := STD_LOGIC_VECTOR(rTemp2(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp3 := STD_LOGIC_VECTOR(rTemp3(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp4 := STD_LOGIC_VECTOR(rTemp4(7 downto 0));
end if;
OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1);
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_19 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_19 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(8 downto 0);
variable rTemp2 : SIGNED(8 downto 0);
variable rTemp3 : SIGNED(8 downto 0);
variable rTemp4 : SIGNED(8 downto 0);
variable vTemp1 : std_logic_vector(7 downto 0);
variable vTemp2 : std_logic_vector(7 downto 0);
variable vTemp3 : std_logic_vector(7 downto 0);
variable vTemp4 : std_logic_vector(7 downto 0);
begin
rTemp1 := RESIZE( SIGNED(INPUT_1( 7 downto 0)), 9) + RESIZE( SIGNED(INPUT_2( 7 downto 0)), 9);
rTemp2 := RESIZE( SIGNED(INPUT_1(15 downto 8)), 9) + RESIZE( SIGNED(INPUT_2(15 downto 8)), 9);
rTemp3 := RESIZE( SIGNED(INPUT_1(23 downto 16)), 9) + RESIZE( SIGNED(INPUT_2(23 downto 16)), 9);
rTemp4 := RESIZE( SIGNED(INPUT_1(31 downto 24)), 9) + RESIZE( SIGNED(INPUT_2(31 downto 24)), 9);
if ( rTemp1 > TO_SIGNED(+127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp1 < TO_SIGNED(-127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp1 := STD_LOGIC_VECTOR(rTemp1(7 downto 0));
end if;
if ( rTemp2 > TO_SIGNED(+127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp2 < TO_SIGNED(-127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp2 := STD_LOGIC_VECTOR(rTemp2(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp3 := STD_LOGIC_VECTOR(rTemp3(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp4 := STD_LOGIC_VECTOR(rTemp4(7 downto 0));
end if;
OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1);
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_19 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_19 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(8 downto 0);
variable rTemp2 : SIGNED(8 downto 0);
variable rTemp3 : SIGNED(8 downto 0);
variable rTemp4 : SIGNED(8 downto 0);
variable vTemp1 : std_logic_vector(7 downto 0);
variable vTemp2 : std_logic_vector(7 downto 0);
variable vTemp3 : std_logic_vector(7 downto 0);
variable vTemp4 : std_logic_vector(7 downto 0);
begin
rTemp1 := RESIZE( SIGNED(INPUT_1( 7 downto 0)), 9) + RESIZE( SIGNED(INPUT_2( 7 downto 0)), 9);
rTemp2 := RESIZE( SIGNED(INPUT_1(15 downto 8)), 9) + RESIZE( SIGNED(INPUT_2(15 downto 8)), 9);
rTemp3 := RESIZE( SIGNED(INPUT_1(23 downto 16)), 9) + RESIZE( SIGNED(INPUT_2(23 downto 16)), 9);
rTemp4 := RESIZE( SIGNED(INPUT_1(31 downto 24)), 9) + RESIZE( SIGNED(INPUT_2(31 downto 24)), 9);
if ( rTemp1 > TO_SIGNED(+127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp1 < TO_SIGNED(-127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp1 := STD_LOGIC_VECTOR(rTemp1(7 downto 0));
end if;
if ( rTemp2 > TO_SIGNED(+127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp2 < TO_SIGNED(-127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp2 := STD_LOGIC_VECTOR(rTemp2(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp3 := STD_LOGIC_VECTOR(rTemp3(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp4 := STD_LOGIC_VECTOR(rTemp4(7 downto 0));
end if;
OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1);
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_19 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_19 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(8 downto 0);
variable rTemp2 : SIGNED(8 downto 0);
variable rTemp3 : SIGNED(8 downto 0);
variable rTemp4 : SIGNED(8 downto 0);
variable vTemp1 : std_logic_vector(7 downto 0);
variable vTemp2 : std_logic_vector(7 downto 0);
variable vTemp3 : std_logic_vector(7 downto 0);
variable vTemp4 : std_logic_vector(7 downto 0);
begin
rTemp1 := RESIZE( SIGNED(INPUT_1( 7 downto 0)), 9) + RESIZE( SIGNED(INPUT_2( 7 downto 0)), 9);
rTemp2 := RESIZE( SIGNED(INPUT_1(15 downto 8)), 9) + RESIZE( SIGNED(INPUT_2(15 downto 8)), 9);
rTemp3 := RESIZE( SIGNED(INPUT_1(23 downto 16)), 9) + RESIZE( SIGNED(INPUT_2(23 downto 16)), 9);
rTemp4 := RESIZE( SIGNED(INPUT_1(31 downto 24)), 9) + RESIZE( SIGNED(INPUT_2(31 downto 24)), 9);
if ( rTemp1 > TO_SIGNED(+127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp1 < TO_SIGNED(-127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp1 := STD_LOGIC_VECTOR(rTemp1(7 downto 0));
end if;
if ( rTemp2 > TO_SIGNED(+127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp2 < TO_SIGNED(-127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp2 := STD_LOGIC_VECTOR(rTemp2(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp3 := STD_LOGIC_VECTOR(rTemp3(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp4 := STD_LOGIC_VECTOR(rTemp4(7 downto 0));
end if;
OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1);
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_19 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_19 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : SIGNED(8 downto 0);
variable rTemp2 : SIGNED(8 downto 0);
variable rTemp3 : SIGNED(8 downto 0);
variable rTemp4 : SIGNED(8 downto 0);
variable vTemp1 : std_logic_vector(7 downto 0);
variable vTemp2 : std_logic_vector(7 downto 0);
variable vTemp3 : std_logic_vector(7 downto 0);
variable vTemp4 : std_logic_vector(7 downto 0);
begin
rTemp1 := RESIZE( SIGNED(INPUT_1( 7 downto 0)), 9) + RESIZE( SIGNED(INPUT_2( 7 downto 0)), 9);
rTemp2 := RESIZE( SIGNED(INPUT_1(15 downto 8)), 9) + RESIZE( SIGNED(INPUT_2(15 downto 8)), 9);
rTemp3 := RESIZE( SIGNED(INPUT_1(23 downto 16)), 9) + RESIZE( SIGNED(INPUT_2(23 downto 16)), 9);
rTemp4 := RESIZE( SIGNED(INPUT_1(31 downto 24)), 9) + RESIZE( SIGNED(INPUT_2(31 downto 24)), 9);
if ( rTemp1 > TO_SIGNED(+127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp1 < TO_SIGNED(-127, 8) ) then vTemp1 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp1 := STD_LOGIC_VECTOR(rTemp1(7 downto 0));
end if;
if ( rTemp2 > TO_SIGNED(+127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp2 < TO_SIGNED(-127, 8) ) then vTemp2 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp2 := STD_LOGIC_VECTOR(rTemp2(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp3 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp3 := STD_LOGIC_VECTOR(rTemp3(7 downto 0));
end if;
if ( rTemp3 > TO_SIGNED(+127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(+127, 8) );
elsif ( rTemp3 < TO_SIGNED(-127, 8) ) then vTemp4 := STD_LOGIC_VECTOR( TO_SIGNED(-127, 8) );
else vTemp4 := STD_LOGIC_VECTOR(rTemp4(7 downto 0));
end if;
OUTPUT_1 <= (vTemp4 & vTemp3 & vTemp2 & vTemp1);
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of pads_westsouth
--
-- Generated
-- by: wig
-- on: Mon Mar 5 15:01:50 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl ../padio2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pads_westsouth-struct-a.vhd,v 1.6 2007/03/05 15:29:26 wig Exp $
-- $Date: 2007/03/05 15:29:26 $
-- $Log: pads_westsouth-struct-a.vhd,v $
-- Revision 1.6 2007/03/05 15:29:26 wig
-- Updated testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of pads_westsouth
--
architecture struct of pads_westsouth is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ioc
-- No Generated Generics
port (
-- Generated Port for Entity ioc
bypass : in std_ulogic_vector(1 downto 0);
clk : in std_ulogic_vector(1 downto 0);
clockdr_i : in std_ulogic;
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic_vector(1 downto 0);
en : in std_ulogic_vector(1 downto 0);
enq : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
iddq : in std_ulogic_vector(1 downto 0);
mode_1_i : in std_ulogic;
mode_2_i : in std_ulogic;
mode_3_i : in std_ulogic;
mux_sel_p : in std_ulogic_vector(1 downto 0);
oe : in std_ulogic_vector(1 downto 0);
pad : inout std_ulogic;
pd : in std_ulogic_vector(1 downto 0);
res_n : in std_ulogic;
scan_en_i : in std_ulogic;
scan_i : in std_ulogic;
scan_o : out std_ulogic;
serial_input_i : in std_ulogic;
serial_output_o : out std_ulogic;
shiftdr_i : in std_ulogic;
tck_i : in std_ulogic;
tenq : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
updatedr_i : in std_ulogic
-- End of Generated Port for Entity ioc
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic1_18 : std_ulogic;
signal mix_logic1_19 : std_ulogic;
signal mix_logic1_20 : std_ulogic;
signal mix_logic1_21 : std_ulogic;
signal mix_logic1_22 : std_ulogic;
signal mix_logic1_23 : std_ulogic;
signal mix_logic1_24 : std_ulogic;
signal mix_logic1_25 : std_ulogic;
signal mix_logic1_26 : std_ulogic;
signal mix_logic1_27 : std_ulogic;
signal mix_logic1_28 : std_ulogic;
signal mix_logic1_29 : std_ulogic;
signal mix_logic1_30 : std_ulogic;
signal mix_logic1_31 : std_ulogic;
signal mix_logic1_32 : std_ulogic;
signal mix_logic1_33 : std_ulogic;
signal mix_logic1_34 : std_ulogic;
signal mix_logic1_35 : std_ulogic;
signal mix_logic1_36 : std_ulogic;
signal mix_logic1_37 : std_ulogic;
signal mix_logic1_38 : std_ulogic;
signal mix_logic1_39 : std_ulogic;
signal mix_logic1_40 : std_ulogic;
signal mix_logic1_41 : std_ulogic;
signal mix_logic1_42 : std_ulogic;
signal mix_logic1_43 : std_ulogic;
signal mix_logic1_44 : std_ulogic;
signal mix_logic1_45 : std_ulogic;
signal mix_logic1_46 : std_ulogic;
signal mix_logic1_47 : std_ulogic;
signal mix_logic1_66 : std_ulogic;
signal mix_logic1_67 : std_ulogic;
signal mix_logic1_68 : std_ulogic;
signal mix_logic1_69 : std_ulogic;
signal mix_logic1_70 : std_ulogic;
signal mix_logic1_71 : std_ulogic;
signal mix_logic1_72 : std_ulogic;
signal mix_logic1_73 : std_ulogic;
signal mix_logic1_74 : std_ulogic;
signal mix_logic1_75 : std_ulogic;
signal mix_logic1_76 : std_ulogic;
signal mix_logic1_77 : std_ulogic;
signal mix_logic1_78 : std_ulogic;
signal mix_logic1_79 : std_ulogic;
signal mix_logic1_80 : std_ulogic;
signal mix_logic1_81 : std_ulogic;
signal mix_logic1_82 : std_ulogic;
signal mix_logic1_83 : std_ulogic;
signal mix_logic1_84 : std_ulogic;
signal mix_logic1_85 : std_ulogic;
signal mix_logic1_86 : std_ulogic;
signal mix_logic1_87 : std_ulogic;
signal mix_logic1_88 : std_ulogic;
signal mix_logic1_89 : std_ulogic;
signal mix_logic1_90 : std_ulogic;
signal mix_logic1_91 : std_ulogic;
signal mix_logic1_92 : std_ulogic;
signal mix_logic1_93 : std_ulogic;
signal mix_logic1_94 : std_ulogic;
signal mix_logic1_95 : std_ulogic;
signal mix_logic0_10 : std_ulogic;
signal mix_logic0_11 : std_ulogic;
signal mix_logic0_12 : std_ulogic;
signal mix_logic0_13 : std_ulogic;
signal mix_logic0_14 : std_ulogic;
signal mix_logic0_15 : std_ulogic;
signal mix_logic0_22 : std_ulogic;
signal mix_logic0_23 : std_ulogic;
signal mix_logic0_24 : std_ulogic;
signal mix_logic0_25 : std_ulogic;
signal mix_logic0_26 : std_ulogic;
signal mix_logic0_27 : std_ulogic;
signal mix_logic0_28 : std_ulogic;
signal mix_logic0_29 : std_ulogic;
signal mix_logic0_30 : std_ulogic;
signal mix_logic0_31 : std_ulogic;
signal mix_logic0_33 : std_ulogic;
signal mix_logic0_36 : std_ulogic;
signal mix_logic0_38 : std_ulogic;
signal mix_logic0_40 : std_ulogic;
signal mix_logic0_42 : std_ulogic;
signal mix_logic0_44 : std_ulogic;
signal mix_logic0_46 : std_ulogic;
signal mix_logic0_47 : std_ulogic;
signal mix_logic0_48 : std_ulogic;
signal mix_logic0_49 : std_ulogic;
signal mix_logic0_51 : std_ulogic;
signal mix_logic0_52 : std_ulogic;
signal mix_logic0_54 : std_ulogic;
signal mix_logic0_57 : std_ulogic;
signal mix_logic0_58 : std_ulogic;
signal mix_logic0_59 : std_ulogic;
signal mix_logic0_6 : std_ulogic;
signal mix_logic0_60 : std_ulogic;
signal mix_logic0_62 : std_ulogic;
signal mix_logic0_64 : std_ulogic;
signal mix_logic0_65 : std_ulogic;
signal mix_logic0_7 : std_ulogic;
signal mix_logic0_8 : std_ulogic;
signal mix_logic0_9 : std_ulogic;
signal clkf81 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal clockdr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal dbo_o : std_ulogic_vector(15 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal default : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_1_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_2_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_3_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pmux_sel_por : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal res_f81_n : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal rgbout_byp_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal rgbout_iddq_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal rgbout_sio_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_in_db2o_0 : std_ulogic;
signal s_in_db2o_1 : std_ulogic;
signal s_in_db2o_2 : std_ulogic;
signal s_in_db2o_3 : std_ulogic;
signal s_in_db2o_4 : std_ulogic;
signal s_in_db2o_5 : std_ulogic;
signal s_in_db2o_6 : std_ulogic;
signal s_in_db2o_7 : std_ulogic;
signal s_in_db2o_8 : std_ulogic;
signal s_in_db2o_9 : std_ulogic;
signal s_in_dbo_0 : std_ulogic;
signal s_in_dbo_1 : std_ulogic;
signal s_in_dbo_2 : std_ulogic;
signal s_in_dbo_3 : std_ulogic;
signal s_in_dbo_4 : std_ulogic;
signal s_in_dbo_5 : std_ulogic;
signal s_in_dbo_6 : std_ulogic;
signal s_in_dbo_7 : std_ulogic;
signal s_in_dbo_8 : std_ulogic;
signal s_in_dbo_9 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_0 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_1 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_2 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_3 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_4 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_5 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_6 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_7 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_8 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_9 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_0 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_1 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_2 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_3 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_4 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_5 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_6 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_7 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_8 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_9 : std_ulogic;
signal scan_en_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal shiftdr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal tck_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal updatedr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal varclk_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic1_18 <= '1';
mix_logic1_19 <= '1';
mix_logic1_20 <= '1';
mix_logic1_21 <= '1';
mix_logic1_22 <= '1';
mix_logic1_23 <= '1';
mix_logic1_24 <= '1';
mix_logic1_25 <= '1';
mix_logic1_26 <= '1';
mix_logic1_27 <= '1';
mix_logic1_28 <= '1';
mix_logic1_29 <= '1';
mix_logic1_30 <= '1';
mix_logic1_31 <= '1';
mix_logic1_32 <= '1';
mix_logic1_33 <= '1';
mix_logic1_34 <= '1';
mix_logic1_35 <= '1';
mix_logic1_36 <= '1';
mix_logic1_37 <= '1';
mix_logic1_38 <= '1';
mix_logic1_39 <= '1';
mix_logic1_40 <= '1';
mix_logic1_41 <= '1';
mix_logic1_42 <= '1';
mix_logic1_43 <= '1';
mix_logic1_44 <= '1';
mix_logic1_45 <= '1';
mix_logic1_46 <= '1';
mix_logic1_47 <= '1';
mix_logic1_66 <= '1';
mix_logic1_67 <= '1';
mix_logic1_68 <= '1';
mix_logic1_69 <= '1';
mix_logic1_70 <= '1';
mix_logic1_71 <= '1';
mix_logic1_72 <= '1';
mix_logic1_73 <= '1';
mix_logic1_74 <= '1';
mix_logic1_75 <= '1';
mix_logic1_76 <= '1';
mix_logic1_77 <= '1';
mix_logic1_78 <= '1';
mix_logic1_79 <= '1';
mix_logic1_80 <= '1';
mix_logic1_81 <= '1';
mix_logic1_82 <= '1';
mix_logic1_83 <= '1';
mix_logic1_84 <= '1';
mix_logic1_85 <= '1';
mix_logic1_86 <= '1';
mix_logic1_87 <= '1';
mix_logic1_88 <= '1';
mix_logic1_89 <= '1';
mix_logic1_90 <= '1';
mix_logic1_91 <= '1';
mix_logic1_92 <= '1';
mix_logic1_93 <= '1';
mix_logic1_94 <= '1';
mix_logic1_95 <= '1';
mix_logic0_10 <= '0';
mix_logic0_11 <= '0';
mix_logic0_12 <= '0';
mix_logic0_13 <= '0';
mix_logic0_14 <= '0';
mix_logic0_15 <= '0';
mix_logic0_22 <= '0';
mix_logic0_23 <= '0';
mix_logic0_24 <= '0';
mix_logic0_25 <= '0';
mix_logic0_26 <= '0';
mix_logic0_27 <= '0';
mix_logic0_28 <= '0';
mix_logic0_29 <= '0';
mix_logic0_30 <= '0';
mix_logic0_31 <= '0';
mix_logic0_33 <= '0';
mix_logic0_36 <= '0';
mix_logic0_38 <= '0';
mix_logic0_40 <= '0';
mix_logic0_42 <= '0';
mix_logic0_44 <= '0';
mix_logic0_46 <= '0';
mix_logic0_47 <= '0';
mix_logic0_48 <= '0';
mix_logic0_49 <= '0';
mix_logic0_51 <= '0';
mix_logic0_52 <= '0';
mix_logic0_54 <= '0';
mix_logic0_57 <= '0';
mix_logic0_58 <= '0';
mix_logic0_59 <= '0';
mix_logic0_6 <= '0';
mix_logic0_60 <= '0';
mix_logic0_62 <= '0';
mix_logic0_64 <= '0';
mix_logic0_65 <= '0';
mix_logic0_7 <= '0';
mix_logic0_8 <= '0';
mix_logic0_9 <= '0';
clkf81 <= clkf81_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
clockdr_i <= clockdr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
dbo_o_9_0_go(9 downto 0) <= dbo_o(9 downto 0); -- __I_O_SLICE_PORT
default <= default_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_1_i <= mode_1_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_2_i <= mode_2_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_3_i <= mode_3_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
pmux_sel_por <= pmux_sel_por_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
res_f81_n <= res_f81_n_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
rgbout_byp_i <= rgbout_byp_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
rgbout_iddq_i <= rgbout_iddq_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
rgbout_sio_i <= rgbout_sio_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
scan_en_i <= scan_en_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
shiftdr_i <= shiftdr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
tck_i <= tck_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
updatedr_i <= updatedr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
varclk_i <= varclk_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for ioc_db2o_0
ioc_db2o_0: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_68, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(0), -- padout (X2)
do(0) => db2o_i(0), -- padin (X2)
do(1) => mix_logic1_66, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_22, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_67, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_0, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_36,
scan_o => open,
serial_input_i => s_in_db2o_0,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_0
-- Generated Instance Port Map for ioc_db2o_1
ioc_db2o_1: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_71, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(1), -- padout (X2)
do(0) => db2o_i(1), -- padin (X2)
do(1) => mix_logic1_69, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_23, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_70, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_1, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_62,
scan_o => open,
serial_input_i => s_in_db2o_1,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_1
-- Generated Instance Port Map for ioc_db2o_2
ioc_db2o_2: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_74, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(2), -- padout (X2)
do(0) => db2o_i(2), -- padin (X2)
do(1) => mix_logic1_72, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_24, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_73, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_2, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_47,
scan_o => open,
serial_input_i => s_in_db2o_2,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_2
-- Generated Instance Port Map for ioc_db2o_3
ioc_db2o_3: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_77, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(3), -- padout (X2)
do(0) => db2o_i(3), -- padin (X2)
do(1) => mix_logic1_75, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_25, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_76, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_3, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_42,
scan_o => open,
serial_input_i => s_in_db2o_3,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_3
-- Generated Instance Port Map for ioc_db2o_4
ioc_db2o_4: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_80, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(4), -- padout (X2)
do(0) => db2o_i(4), -- padin (X2)
do(1) => mix_logic1_78, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_26, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_79, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_4, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_51,
scan_o => open,
serial_input_i => s_in_db2o_4,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_4
-- Generated Instance Port Map for ioc_db2o_5
ioc_db2o_5: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_83, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(5), -- padout (X2)
do(0) => db2o_i(5), -- padin (X2)
do(1) => mix_logic1_81, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_27, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_82, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_5, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_65,
scan_o => open,
serial_input_i => s_in_db2o_5,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_5
-- Generated Instance Port Map for ioc_db2o_6
ioc_db2o_6: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_86, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(6), -- padout (X2)
do(0) => db2o_i(6), -- padin (X2)
do(1) => mix_logic1_84, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_28, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_85, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_6, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_52,
scan_o => open,
serial_input_i => s_in_db2o_6,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_6
-- Generated Instance Port Map for ioc_db2o_7
ioc_db2o_7: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_89, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(7), -- padout (X2)
do(0) => db2o_i(7), -- padin (X2)
do(1) => mix_logic1_87, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_29, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_88, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_7, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_49,
scan_o => open,
serial_input_i => s_in_db2o_7,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_7
-- Generated Instance Port Map for ioc_db2o_8
ioc_db2o_8: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_92, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(8), -- padout (X2)
do(0) => db2o_i(8), -- padin (X2)
do(1) => mix_logic1_90, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_30, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_91, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_8, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_58,
scan_o => open,
serial_input_i => s_in_db2o_8,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_8
-- Generated Instance Port Map for ioc_db2o_9
ioc_db2o_9: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_95, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(9), -- padout (X2)
do(0) => db2o_i(9), -- padin (X2)
do(1) => mix_logic1_93, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_31, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_94, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_9, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_59,
scan_o => open,
serial_input_i => s_in_db2o_9,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_9
-- Generated Instance Port Map for ioc_dbo_0
ioc_dbo_0: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_20, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(0), -- padout
do(0) => dbo_i(0), -- padin (X2)
do(1) => mix_logic1_18, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_6, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_19, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_0, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_54,
scan_o => open,
serial_input_i => s_in_dbo_0,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_0
-- Generated Instance Port Map for ioc_dbo_1
ioc_dbo_1: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_23, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(1), -- padout
do(0) => dbo_i(1), -- padin (X2)
do(1) => mix_logic1_21, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_7, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_22, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_1, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_60,
scan_o => open,
serial_input_i => s_in_dbo_1,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_1
-- Generated Instance Port Map for ioc_dbo_2
ioc_dbo_2: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_26, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(2), -- padout
do(0) => dbo_i(2), -- padin (X2)
do(1) => mix_logic1_24, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_8, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_25, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_2, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_33,
scan_o => open,
serial_input_i => s_in_dbo_2,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_2
-- Generated Instance Port Map for ioc_dbo_3
ioc_dbo_3: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_29, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(3), -- padout
do(0) => dbo_i(3), -- padin (X2)
do(1) => mix_logic1_27, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_9, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_28, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_3, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_44,
scan_o => open,
serial_input_i => s_in_dbo_3,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_3
-- Generated Instance Port Map for ioc_dbo_4
ioc_dbo_4: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_32, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(4), -- padout
do(0) => dbo_i(4), -- padin (X2)
do(1) => mix_logic1_30, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_10, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_31, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_4, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_57,
scan_o => open,
serial_input_i => s_in_dbo_4,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_4
-- Generated Instance Port Map for ioc_dbo_5
ioc_dbo_5: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_35, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(5), -- padout
do(0) => dbo_i(5), -- padin (X2)
do(1) => mix_logic1_33, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_11, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_34, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_5, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_40,
scan_o => open,
serial_input_i => s_in_dbo_5,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_5
-- Generated Instance Port Map for ioc_dbo_6
ioc_dbo_6: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_38, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(6), -- padout
do(0) => dbo_i(6), -- padin (X2)
do(1) => mix_logic1_36, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_12, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_37, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_6, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_46,
scan_o => open,
serial_input_i => s_in_dbo_6,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_6
-- Generated Instance Port Map for ioc_dbo_7
ioc_dbo_7: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_41, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(7), -- padout
do(0) => dbo_i(7), -- padin (X2)
do(1) => mix_logic1_39, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_13, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_40, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_7, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_64,
scan_o => open,
serial_input_i => s_in_dbo_7,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_7
-- Generated Instance Port Map for ioc_dbo_8
ioc_dbo_8: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_44, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(8), -- padout
do(0) => dbo_i(8), -- padin (X2)
do(1) => mix_logic1_42, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_14, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_43, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_8, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_48,
scan_o => open,
serial_input_i => s_in_dbo_8,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_8
-- Generated Instance Port Map for ioc_dbo_9
ioc_dbo_9: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_47, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(9), -- padout
do(0) => dbo_i(9), -- padin (X2)
do(1) => mix_logic1_45, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_15, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_46, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_9, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_38,
scan_o => open,
serial_input_i => s_in_dbo_9,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_9
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
--
-- File Name: OsvvmGlobalPkg.vhd
-- Design Unit Name: OsvvmGlobalPkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
--
-- Description:
-- Global Settings for OSVVM packages
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 01/2014: 2015.01 Initial revision
--
--
-- Copyright (c) 2015 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
library ieee ;
use std.textio.all ;
use work.NamePkg.all ;
package OsvvmGlobalPkg is
-- FILE IO Global File Identifier -- Open using AlertLogPkg.TranscriptOpen
-- file TranscriptFile : text ;
-- Shared Options Type used in OSVVM
type OsvvmOptionsType is (OPT_INIT_PARM_DETECT, OPT_USE_DEFAULT, DISABLED, FALSE, ENABLED, TRUE) ;
function IsEnabled (A : OsvvmOptionsType) return boolean ; -- Requires that TRUE is last and ENABLED is 2nd to last
function to_OsvvmOptionsType (A : boolean) return OsvvmOptionsType ;
-- Defaults for String values
constant OSVVM_DEFAULT_ALERT_PREFIX : string := "%% Alert" ;
constant OSVVM_DEFAULT_LOG_PREFIX : string := "%% Log " ;
constant OSVVM_DEFAULT_WRITE_PREFIX : string := "%% " ;
constant OSVVM_DEFAULT_DONE_NAME : string := "DONE" ;
constant OSVVM_DEFAULT_PASS_NAME : string := "PASSED" ;
constant OSVVM_DEFAULT_FAIL_NAME : string := "FAILED" ;
constant OSVVM_STRING_INIT_PARM_DETECT : string := NUL & NUL & NUL ;
constant OSVVM_STRING_USE_DEFAULT : string := NUL & "" ;
-- Coverage Settings
constant OSVVM_DEFAULT_WRITE_PASS_FAIL : OsvvmOptionsType := FALSE ;
constant OSVVM_DEFAULT_WRITE_BIN_INFO : OsvvmOptionsType := TRUE ;
constant OSVVM_DEFAULT_WRITE_COUNT : OsvvmOptionsType := TRUE ;
constant OSVVM_DEFAULT_WRITE_ANY_ILLEGAL : OsvvmOptionsType := FALSE ;
------------------------------------------------------------
procedure SetOsvvmGlobalOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
------------------------------------------------------------
-- Accessor Functions
function ResolveOsvvmOption(A, B, C : OsvvmOptionsType) return OsvvmOptionsType ;
function ResolveOsvvmOption(A, B, C, D : OsvvmOptionsType) return OsvvmOptionsType ;
function IsOsvvmStringSet (A : string) return boolean ;
function ResolveOsvvmOption(A, B : string) return string ;
function ResolveOsvvmOption(A, B, C : string) return string ;
function ResolveOsvvmOption(A, B, C, D : string) return string ;
impure function ResolveOsvvmWritePrefix(A : String) return string ;
impure function ResolveOsvvmWritePrefix(A, B : String) return string ;
impure function ResolveOsvvmDoneName(A : String) return string ;
impure function ResolveOsvvmDoneName(A, B : String) return string ;
impure function ResolveOsvvmPassName(A : String) return string ;
impure function ResolveOsvvmPassName(A, B : String) return string ;
impure function ResolveOsvvmFailName(A : String) return string ;
impure function ResolveOsvvmFailName(A, B : String) return string ;
impure function ResolveCovWritePassFail(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteBinInfo(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteCount(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteAnyIllegal(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
procedure OsvvmDeallocate ;
type OptionsPType is protected
procedure Set (A: OsvvmOptionsType) ;
impure function get return OsvvmOptionsType ;
end protected OptionsPType ;
end OsvvmGlobalPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body OsvvmGlobalPkg is
type OptionsPType is protected body
variable GlobalVar : OsvvmOptionsType ;
procedure Set (A : OsvvmOptionsType) is
begin
GlobalVar := A ;
end procedure Set ;
impure function get return OsvvmOptionsType is
begin
return GlobalVar ;
end function get ;
end protected body OptionsPType ;
shared variable WritePrefixVar : NamePType ;
shared variable DoneNameVar : NamePType ;
shared variable PassNameVar : NamePType ;
shared variable FailNameVar : NamePType ;
shared variable WritePassFailVar : OptionsPType ; -- := FALSE ;
shared variable WriteBinInfoVar : OptionsPType ; -- := TRUE ;
shared variable WriteCountVar : OptionsPType ; -- := TRUE ;
shared variable WriteAnyIllegalVar : OptionsPType ; -- := FALSE ;
function IsEnabled (A : OsvvmOptionsType) return boolean is
begin
return A >= ENABLED ;
end function IsEnabled ;
function to_OsvvmOptionsType (A : boolean) return OsvvmOptionsType is
begin
if A then
return TRUE ;
else
return FALSE ;
end if ;
end function to_OsvvmOptionsType ;
------------------------------------------------------------
procedure SetOsvvmGlobalOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
if WritePassFail /= OPT_INIT_PARM_DETECT then
WritePassFailVar.Set(WritePassFail) ;
end if ;
if WriteBinInfo /= OPT_INIT_PARM_DETECT then
WriteBinInfoVar.Set(WriteBinInfo) ;
end if ;
if WriteCount /= OPT_INIT_PARM_DETECT then
WriteCountVar.Set(WriteCount) ;
end if ;
if WriteAnyIllegal /= OPT_INIT_PARM_DETECT then
WriteAnyIllegalVar.Set(WriteAnyIllegal) ;
end if ;
if WritePrefix /= OSVVM_STRING_INIT_PARM_DETECT then
WritePrefixVar.Set(WritePrefix) ;
end if ;
if DoneName /= OSVVM_STRING_INIT_PARM_DETECT then
DoneNameVar.Set(DoneName) ;
end if ;
if PassName /= OSVVM_STRING_INIT_PARM_DETECT then
PassNameVar.Set(PassName) ;
end if ;
if FailName /= OSVVM_STRING_INIT_PARM_DETECT then
FailNameVar.Set(FailName) ;
end if ;
end procedure SetOsvvmGlobalOptions ;
------------------------------------------------------------
-- Accessor Functions
-- Local Function
function IsOsvvmOptionSet (A : OsvvmOptionsType) return boolean is
begin
return A > OPT_USE_DEFAULT ;
end function IsOsvvmOptionSet ;
function ResolveOsvvmOption(A, B, C : OsvvmOptionsType) return OsvvmOptionsType is
begin
if IsOsvvmOptionSet(A) then
return A ;
elsif IsOsvvmOptionSet(B) then
return B ;
else
return C ;
end if ;
end function ResolveOsvvmOption ;
function ResolveOsvvmOption(A, B, C, D : OsvvmOptionsType) return OsvvmOptionsType is
begin
if IsOsvvmOptionSet(A) then
return A ;
elsif IsOsvvmOptionSet(B) then
return B ;
elsif IsOsvvmOptionSet(C) then
return C ;
else
return D ;
end if ;
end function ResolveOsvvmOption ;
-- Local Function
function IsOsvvmStringSet (A : string) return boolean is
begin
if A'length = 0 then -- Null strings permitted
return TRUE ;
else
return A(A'left) /= NUL ;
end if;
end function IsOsvvmStringSet ;
function ResolveOsvvmOption(A, B : string) return string is
begin
if IsOsvvmStringSet(A) then
return A ;
else
return B ;
end if ;
end function ResolveOsvvmOption ;
function ResolveOsvvmOption(A, B, C : string) return string is
begin
if IsOsvvmStringSet(A) then
return A ;
elsif IsOsvvmStringSet(B) then
return B ;
else
return C ;
end if ;
end function ResolveOsvvmOption ;
function ResolveOsvvmOption(A, B, C, D : string) return string is
begin
if IsOsvvmStringSet(A) then
return A ;
elsif IsOsvvmStringSet(B) then
return B ;
elsif IsOsvvmStringSet(C) then
return C ;
else
return D ;
end if ;
end function ResolveOsvvmOption ;
impure function ResolveOsvvmWritePrefix(A : String) return string is
begin
return ResolveOsvvmOption(A, WritePrefixVar.GetOpt, OSVVM_DEFAULT_WRITE_PREFIX) ;
end function ResolveOsvvmWritePrefix ;
impure function ResolveOsvvmWritePrefix(A, B : String) return string is
begin
return ResolveOsvvmOption(A, B, WritePrefixVar.GetOpt, OSVVM_DEFAULT_WRITE_PREFIX) ;
end function ResolveOsvvmWritePrefix ;
impure function ResolveOsvvmDoneName(A : String) return string is
begin
return ResolveOsvvmOption(A, DoneNameVar.GetOpt, OSVVM_DEFAULT_DONE_NAME) ;
end function ResolveOsvvmDoneName ;
impure function ResolveOsvvmDoneName(A, B : String) return string is
begin
return ResolveOsvvmOption(A, DoneNameVar.GetOpt, OSVVM_DEFAULT_DONE_NAME) ;
end function ResolveOsvvmDoneName ;
impure function ResolveOsvvmPassName(A : String) return string is
begin
return ResolveOsvvmOption(A, PassNameVar.GetOpt, OSVVM_DEFAULT_PASS_NAME) ;
end function ResolveOsvvmPassName ;
impure function ResolveOsvvmPassName(A, B : String) return string is
begin
return ResolveOsvvmOption(A, B, PassNameVar.GetOpt, OSVVM_DEFAULT_PASS_NAME) ;
end function ResolveOsvvmPassName ;
impure function ResolveOsvvmFailName(A : String) return string is
begin
return ResolveOsvvmOption(A, FailNameVar.GetOpt, OSVVM_DEFAULT_FAIL_NAME) ;
end function ResolveOsvvmFailName ;
impure function ResolveOsvvmFailName(A, B : String) return string is
begin
return ResolveOsvvmOption(A, B, FailNameVar.GetOpt, OSVVM_DEFAULT_FAIL_NAME) ;
end function ResolveOsvvmFailName ;
impure function ResolveCovWritePassFail(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WritePassFailVar.Get, OSVVM_DEFAULT_WRITE_PASS_FAIL) ;
end function ResolveCovWritePassFail ; -- Cov
impure function ResolveCovWriteBinInfo(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WriteBinInfoVar.Get, OSVVM_DEFAULT_WRITE_BIN_INFO) ;
end function ResolveCovWriteBinInfo ; -- Cov
impure function ResolveCovWriteCount(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WriteCountVar.Get, OSVVM_DEFAULT_WRITE_COUNT) ;
end function ResolveCovWriteCount ; -- Cov
impure function ResolveCovWriteAnyIllegal(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WriteAnyIllegalVar.Get, OSVVM_DEFAULT_WRITE_ANY_ILLEGAL) ;
end function ResolveCovWriteAnyIllegal ; -- Cov
procedure OsvvmDeallocate is
begin
-- Free up space used by NamePType within OsvvmGlobalPkg
WritePrefixVar.Deallocate ;
DoneNameVar.Deallocate ;
PassNameVar.Deallocate ;
FailNameVar.Deallocate ;
WritePassFailVar.Set(FALSE) ; -- := FALSE ;
WriteBinInfoVar.Set(TRUE ) ; -- := TRUE ;
WriteCountVar.Set(TRUE ) ; -- := TRUE ;
WriteAnyIllegalVar.Set(FALSE) ; -- := FALSE ;
end procedure OsvvmDeallocate ;
end package body OsvvmGlobalPkg ; |
--
-- File Name: OsvvmGlobalPkg.vhd
-- Design Unit Name: OsvvmGlobalPkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
--
-- Description:
-- Global Settings for OSVVM packages
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 01/2014: 2015.01 Initial revision
--
--
-- Copyright (c) 2015 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
library ieee ;
use std.textio.all ;
use work.NamePkg.all ;
package OsvvmGlobalPkg is
-- FILE IO Global File Identifier -- Open using AlertLogPkg.TranscriptOpen
-- file TranscriptFile : text ;
-- Shared Options Type used in OSVVM
type OsvvmOptionsType is (OPT_INIT_PARM_DETECT, OPT_USE_DEFAULT, DISABLED, FALSE, ENABLED, TRUE) ;
function IsEnabled (A : OsvvmOptionsType) return boolean ; -- Requires that TRUE is last and ENABLED is 2nd to last
function to_OsvvmOptionsType (A : boolean) return OsvvmOptionsType ;
-- Defaults for String values
constant OSVVM_DEFAULT_ALERT_PREFIX : string := "%% Alert" ;
constant OSVVM_DEFAULT_LOG_PREFIX : string := "%% Log " ;
constant OSVVM_DEFAULT_WRITE_PREFIX : string := "%% " ;
constant OSVVM_DEFAULT_DONE_NAME : string := "DONE" ;
constant OSVVM_DEFAULT_PASS_NAME : string := "PASSED" ;
constant OSVVM_DEFAULT_FAIL_NAME : string := "FAILED" ;
constant OSVVM_STRING_INIT_PARM_DETECT : string := NUL & NUL & NUL ;
constant OSVVM_STRING_USE_DEFAULT : string := NUL & "" ;
-- Coverage Settings
constant OSVVM_DEFAULT_WRITE_PASS_FAIL : OsvvmOptionsType := FALSE ;
constant OSVVM_DEFAULT_WRITE_BIN_INFO : OsvvmOptionsType := TRUE ;
constant OSVVM_DEFAULT_WRITE_COUNT : OsvvmOptionsType := TRUE ;
constant OSVVM_DEFAULT_WRITE_ANY_ILLEGAL : OsvvmOptionsType := FALSE ;
------------------------------------------------------------
procedure SetOsvvmGlobalOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
------------------------------------------------------------
-- Accessor Functions
function ResolveOsvvmOption(A, B, C : OsvvmOptionsType) return OsvvmOptionsType ;
function ResolveOsvvmOption(A, B, C, D : OsvvmOptionsType) return OsvvmOptionsType ;
function IsOsvvmStringSet (A : string) return boolean ;
function ResolveOsvvmOption(A, B : string) return string ;
function ResolveOsvvmOption(A, B, C : string) return string ;
function ResolveOsvvmOption(A, B, C, D : string) return string ;
impure function ResolveOsvvmWritePrefix(A : String) return string ;
impure function ResolveOsvvmWritePrefix(A, B : String) return string ;
impure function ResolveOsvvmDoneName(A : String) return string ;
impure function ResolveOsvvmDoneName(A, B : String) return string ;
impure function ResolveOsvvmPassName(A : String) return string ;
impure function ResolveOsvvmPassName(A, B : String) return string ;
impure function ResolveOsvvmFailName(A : String) return string ;
impure function ResolveOsvvmFailName(A, B : String) return string ;
impure function ResolveCovWritePassFail(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteBinInfo(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteCount(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteAnyIllegal(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
procedure OsvvmDeallocate ;
type OptionsPType is protected
procedure Set (A: OsvvmOptionsType) ;
impure function get return OsvvmOptionsType ;
end protected OptionsPType ;
end OsvvmGlobalPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body OsvvmGlobalPkg is
type OptionsPType is protected body
variable GlobalVar : OsvvmOptionsType ;
procedure Set (A : OsvvmOptionsType) is
begin
GlobalVar := A ;
end procedure Set ;
impure function get return OsvvmOptionsType is
begin
return GlobalVar ;
end function get ;
end protected body OptionsPType ;
shared variable WritePrefixVar : NamePType ;
shared variable DoneNameVar : NamePType ;
shared variable PassNameVar : NamePType ;
shared variable FailNameVar : NamePType ;
shared variable WritePassFailVar : OptionsPType ; -- := FALSE ;
shared variable WriteBinInfoVar : OptionsPType ; -- := TRUE ;
shared variable WriteCountVar : OptionsPType ; -- := TRUE ;
shared variable WriteAnyIllegalVar : OptionsPType ; -- := FALSE ;
function IsEnabled (A : OsvvmOptionsType) return boolean is
begin
return A >= ENABLED ;
end function IsEnabled ;
function to_OsvvmOptionsType (A : boolean) return OsvvmOptionsType is
begin
if A then
return TRUE ;
else
return FALSE ;
end if ;
end function to_OsvvmOptionsType ;
------------------------------------------------------------
procedure SetOsvvmGlobalOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
if WritePassFail /= OPT_INIT_PARM_DETECT then
WritePassFailVar.Set(WritePassFail) ;
end if ;
if WriteBinInfo /= OPT_INIT_PARM_DETECT then
WriteBinInfoVar.Set(WriteBinInfo) ;
end if ;
if WriteCount /= OPT_INIT_PARM_DETECT then
WriteCountVar.Set(WriteCount) ;
end if ;
if WriteAnyIllegal /= OPT_INIT_PARM_DETECT then
WriteAnyIllegalVar.Set(WriteAnyIllegal) ;
end if ;
if WritePrefix /= OSVVM_STRING_INIT_PARM_DETECT then
WritePrefixVar.Set(WritePrefix) ;
end if ;
if DoneName /= OSVVM_STRING_INIT_PARM_DETECT then
DoneNameVar.Set(DoneName) ;
end if ;
if PassName /= OSVVM_STRING_INIT_PARM_DETECT then
PassNameVar.Set(PassName) ;
end if ;
if FailName /= OSVVM_STRING_INIT_PARM_DETECT then
FailNameVar.Set(FailName) ;
end if ;
end procedure SetOsvvmGlobalOptions ;
------------------------------------------------------------
-- Accessor Functions
-- Local Function
function IsOsvvmOptionSet (A : OsvvmOptionsType) return boolean is
begin
return A > OPT_USE_DEFAULT ;
end function IsOsvvmOptionSet ;
function ResolveOsvvmOption(A, B, C : OsvvmOptionsType) return OsvvmOptionsType is
begin
if IsOsvvmOptionSet(A) then
return A ;
elsif IsOsvvmOptionSet(B) then
return B ;
else
return C ;
end if ;
end function ResolveOsvvmOption ;
function ResolveOsvvmOption(A, B, C, D : OsvvmOptionsType) return OsvvmOptionsType is
begin
if IsOsvvmOptionSet(A) then
return A ;
elsif IsOsvvmOptionSet(B) then
return B ;
elsif IsOsvvmOptionSet(C) then
return C ;
else
return D ;
end if ;
end function ResolveOsvvmOption ;
-- Local Function
function IsOsvvmStringSet (A : string) return boolean is
begin
if A'length = 0 then -- Null strings permitted
return TRUE ;
else
return A(A'left) /= NUL ;
end if;
end function IsOsvvmStringSet ;
function ResolveOsvvmOption(A, B : string) return string is
begin
if IsOsvvmStringSet(A) then
return A ;
else
return B ;
end if ;
end function ResolveOsvvmOption ;
function ResolveOsvvmOption(A, B, C : string) return string is
begin
if IsOsvvmStringSet(A) then
return A ;
elsif IsOsvvmStringSet(B) then
return B ;
else
return C ;
end if ;
end function ResolveOsvvmOption ;
function ResolveOsvvmOption(A, B, C, D : string) return string is
begin
if IsOsvvmStringSet(A) then
return A ;
elsif IsOsvvmStringSet(B) then
return B ;
elsif IsOsvvmStringSet(C) then
return C ;
else
return D ;
end if ;
end function ResolveOsvvmOption ;
impure function ResolveOsvvmWritePrefix(A : String) return string is
begin
return ResolveOsvvmOption(A, WritePrefixVar.GetOpt, OSVVM_DEFAULT_WRITE_PREFIX) ;
end function ResolveOsvvmWritePrefix ;
impure function ResolveOsvvmWritePrefix(A, B : String) return string is
begin
return ResolveOsvvmOption(A, B, WritePrefixVar.GetOpt, OSVVM_DEFAULT_WRITE_PREFIX) ;
end function ResolveOsvvmWritePrefix ;
impure function ResolveOsvvmDoneName(A : String) return string is
begin
return ResolveOsvvmOption(A, DoneNameVar.GetOpt, OSVVM_DEFAULT_DONE_NAME) ;
end function ResolveOsvvmDoneName ;
impure function ResolveOsvvmDoneName(A, B : String) return string is
begin
return ResolveOsvvmOption(A, DoneNameVar.GetOpt, OSVVM_DEFAULT_DONE_NAME) ;
end function ResolveOsvvmDoneName ;
impure function ResolveOsvvmPassName(A : String) return string is
begin
return ResolveOsvvmOption(A, PassNameVar.GetOpt, OSVVM_DEFAULT_PASS_NAME) ;
end function ResolveOsvvmPassName ;
impure function ResolveOsvvmPassName(A, B : String) return string is
begin
return ResolveOsvvmOption(A, B, PassNameVar.GetOpt, OSVVM_DEFAULT_PASS_NAME) ;
end function ResolveOsvvmPassName ;
impure function ResolveOsvvmFailName(A : String) return string is
begin
return ResolveOsvvmOption(A, FailNameVar.GetOpt, OSVVM_DEFAULT_FAIL_NAME) ;
end function ResolveOsvvmFailName ;
impure function ResolveOsvvmFailName(A, B : String) return string is
begin
return ResolveOsvvmOption(A, B, FailNameVar.GetOpt, OSVVM_DEFAULT_FAIL_NAME) ;
end function ResolveOsvvmFailName ;
impure function ResolveCovWritePassFail(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WritePassFailVar.Get, OSVVM_DEFAULT_WRITE_PASS_FAIL) ;
end function ResolveCovWritePassFail ; -- Cov
impure function ResolveCovWriteBinInfo(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WriteBinInfoVar.Get, OSVVM_DEFAULT_WRITE_BIN_INFO) ;
end function ResolveCovWriteBinInfo ; -- Cov
impure function ResolveCovWriteCount(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WriteCountVar.Get, OSVVM_DEFAULT_WRITE_COUNT) ;
end function ResolveCovWriteCount ; -- Cov
impure function ResolveCovWriteAnyIllegal(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WriteAnyIllegalVar.Get, OSVVM_DEFAULT_WRITE_ANY_ILLEGAL) ;
end function ResolveCovWriteAnyIllegal ; -- Cov
procedure OsvvmDeallocate is
begin
-- Free up space used by NamePType within OsvvmGlobalPkg
WritePrefixVar.Deallocate ;
DoneNameVar.Deallocate ;
PassNameVar.Deallocate ;
FailNameVar.Deallocate ;
WritePassFailVar.Set(FALSE) ; -- := FALSE ;
WriteBinInfoVar.Set(TRUE ) ; -- := TRUE ;
WriteCountVar.Set(TRUE ) ; -- := TRUE ;
WriteAnyIllegalVar.Set(FALSE) ; -- := FALSE ;
end procedure OsvvmDeallocate ;
end package body OsvvmGlobalPkg ; |
--
-- File Name: OsvvmGlobalPkg.vhd
-- Design Unit Name: OsvvmGlobalPkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
--
-- Description:
-- Global Settings for OSVVM packages
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 01/2014: 2015.01 Initial revision
--
--
-- Copyright (c) 2015 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http://www.perlfoundation.org/artistic_license_2_0
--
library ieee ;
use std.textio.all ;
use work.NamePkg.all ;
package OsvvmGlobalPkg is
-- FILE IO Global File Identifier -- Open using AlertLogPkg.TranscriptOpen
-- file TranscriptFile : text ;
-- Shared Options Type used in OSVVM
type OsvvmOptionsType is (OPT_INIT_PARM_DETECT, OPT_USE_DEFAULT, DISABLED, FALSE, ENABLED, TRUE) ;
function IsEnabled (A : OsvvmOptionsType) return boolean ; -- Requires that TRUE is last and ENABLED is 2nd to last
function to_OsvvmOptionsType (A : boolean) return OsvvmOptionsType ;
-- Defaults for String values
constant OSVVM_DEFAULT_ALERT_PREFIX : string := "%% Alert" ;
constant OSVVM_DEFAULT_LOG_PREFIX : string := "%% Log " ;
constant OSVVM_DEFAULT_WRITE_PREFIX : string := "%% " ;
constant OSVVM_DEFAULT_DONE_NAME : string := "DONE" ;
constant OSVVM_DEFAULT_PASS_NAME : string := "PASSED" ;
constant OSVVM_DEFAULT_FAIL_NAME : string := "FAILED" ;
constant OSVVM_STRING_INIT_PARM_DETECT : string := NUL & NUL & NUL ;
constant OSVVM_STRING_USE_DEFAULT : string := NUL & "" ;
-- Coverage Settings
constant OSVVM_DEFAULT_WRITE_PASS_FAIL : OsvvmOptionsType := FALSE ;
constant OSVVM_DEFAULT_WRITE_BIN_INFO : OsvvmOptionsType := TRUE ;
constant OSVVM_DEFAULT_WRITE_COUNT : OsvvmOptionsType := TRUE ;
constant OSVVM_DEFAULT_WRITE_ANY_ILLEGAL : OsvvmOptionsType := FALSE ;
------------------------------------------------------------
procedure SetOsvvmGlobalOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
------------------------------------------------------------
-- Accessor Functions
function ResolveOsvvmOption(A, B, C : OsvvmOptionsType) return OsvvmOptionsType ;
function ResolveOsvvmOption(A, B, C, D : OsvvmOptionsType) return OsvvmOptionsType ;
function IsOsvvmStringSet (A : string) return boolean ;
function ResolveOsvvmOption(A, B : string) return string ;
function ResolveOsvvmOption(A, B, C : string) return string ;
function ResolveOsvvmOption(A, B, C, D : string) return string ;
impure function ResolveOsvvmWritePrefix(A : String) return string ;
impure function ResolveOsvvmWritePrefix(A, B : String) return string ;
impure function ResolveOsvvmDoneName(A : String) return string ;
impure function ResolveOsvvmDoneName(A, B : String) return string ;
impure function ResolveOsvvmPassName(A : String) return string ;
impure function ResolveOsvvmPassName(A, B : String) return string ;
impure function ResolveOsvvmFailName(A : String) return string ;
impure function ResolveOsvvmFailName(A, B : String) return string ;
impure function ResolveCovWritePassFail(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteBinInfo(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteCount(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteAnyIllegal(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
procedure OsvvmDeallocate ;
type OptionsPType is protected
procedure Set (A: OsvvmOptionsType) ;
impure function get return OsvvmOptionsType ;
end protected OptionsPType ;
end OsvvmGlobalPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body OsvvmGlobalPkg is
type OptionsPType is protected body
variable GlobalVar : OsvvmOptionsType ;
procedure Set (A : OsvvmOptionsType) is
begin
GlobalVar := A ;
end procedure Set ;
impure function get return OsvvmOptionsType is
begin
return GlobalVar ;
end function get ;
end protected body OptionsPType ;
shared variable WritePrefixVar : NamePType ;
shared variable DoneNameVar : NamePType ;
shared variable PassNameVar : NamePType ;
shared variable FailNameVar : NamePType ;
shared variable WritePassFailVar : OptionsPType ; -- := FALSE ;
shared variable WriteBinInfoVar : OptionsPType ; -- := TRUE ;
shared variable WriteCountVar : OptionsPType ; -- := TRUE ;
shared variable WriteAnyIllegalVar : OptionsPType ; -- := FALSE ;
function IsEnabled (A : OsvvmOptionsType) return boolean is
begin
return A >= ENABLED ;
end function IsEnabled ;
function to_OsvvmOptionsType (A : boolean) return OsvvmOptionsType is
begin
if A then
return TRUE ;
else
return FALSE ;
end if ;
end function to_OsvvmOptionsType ;
------------------------------------------------------------
procedure SetOsvvmGlobalOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
if WritePassFail /= OPT_INIT_PARM_DETECT then
WritePassFailVar.Set(WritePassFail) ;
end if ;
if WriteBinInfo /= OPT_INIT_PARM_DETECT then
WriteBinInfoVar.Set(WriteBinInfo) ;
end if ;
if WriteCount /= OPT_INIT_PARM_DETECT then
WriteCountVar.Set(WriteCount) ;
end if ;
if WriteAnyIllegal /= OPT_INIT_PARM_DETECT then
WriteAnyIllegalVar.Set(WriteAnyIllegal) ;
end if ;
if WritePrefix /= OSVVM_STRING_INIT_PARM_DETECT then
WritePrefixVar.Set(WritePrefix) ;
end if ;
if DoneName /= OSVVM_STRING_INIT_PARM_DETECT then
DoneNameVar.Set(DoneName) ;
end if ;
if PassName /= OSVVM_STRING_INIT_PARM_DETECT then
PassNameVar.Set(PassName) ;
end if ;
if FailName /= OSVVM_STRING_INIT_PARM_DETECT then
FailNameVar.Set(FailName) ;
end if ;
end procedure SetOsvvmGlobalOptions ;
------------------------------------------------------------
-- Accessor Functions
-- Local Function
function IsOsvvmOptionSet (A : OsvvmOptionsType) return boolean is
begin
return A > OPT_USE_DEFAULT ;
end function IsOsvvmOptionSet ;
function ResolveOsvvmOption(A, B, C : OsvvmOptionsType) return OsvvmOptionsType is
begin
if IsOsvvmOptionSet(A) then
return A ;
elsif IsOsvvmOptionSet(B) then
return B ;
else
return C ;
end if ;
end function ResolveOsvvmOption ;
function ResolveOsvvmOption(A, B, C, D : OsvvmOptionsType) return OsvvmOptionsType is
begin
if IsOsvvmOptionSet(A) then
return A ;
elsif IsOsvvmOptionSet(B) then
return B ;
elsif IsOsvvmOptionSet(C) then
return C ;
else
return D ;
end if ;
end function ResolveOsvvmOption ;
-- Local Function
function IsOsvvmStringSet (A : string) return boolean is
begin
if A'length = 0 then -- Null strings permitted
return TRUE ;
else
return A(A'left) /= NUL ;
end if;
end function IsOsvvmStringSet ;
function ResolveOsvvmOption(A, B : string) return string is
begin
if IsOsvvmStringSet(A) then
return A ;
else
return B ;
end if ;
end function ResolveOsvvmOption ;
function ResolveOsvvmOption(A, B, C : string) return string is
begin
if IsOsvvmStringSet(A) then
return A ;
elsif IsOsvvmStringSet(B) then
return B ;
else
return C ;
end if ;
end function ResolveOsvvmOption ;
function ResolveOsvvmOption(A, B, C, D : string) return string is
begin
if IsOsvvmStringSet(A) then
return A ;
elsif IsOsvvmStringSet(B) then
return B ;
elsif IsOsvvmStringSet(C) then
return C ;
else
return D ;
end if ;
end function ResolveOsvvmOption ;
impure function ResolveOsvvmWritePrefix(A : String) return string is
begin
return ResolveOsvvmOption(A, WritePrefixVar.GetOpt, OSVVM_DEFAULT_WRITE_PREFIX) ;
end function ResolveOsvvmWritePrefix ;
impure function ResolveOsvvmWritePrefix(A, B : String) return string is
begin
return ResolveOsvvmOption(A, B, WritePrefixVar.GetOpt, OSVVM_DEFAULT_WRITE_PREFIX) ;
end function ResolveOsvvmWritePrefix ;
impure function ResolveOsvvmDoneName(A : String) return string is
begin
return ResolveOsvvmOption(A, DoneNameVar.GetOpt, OSVVM_DEFAULT_DONE_NAME) ;
end function ResolveOsvvmDoneName ;
impure function ResolveOsvvmDoneName(A, B : String) return string is
begin
return ResolveOsvvmOption(A, DoneNameVar.GetOpt, OSVVM_DEFAULT_DONE_NAME) ;
end function ResolveOsvvmDoneName ;
impure function ResolveOsvvmPassName(A : String) return string is
begin
return ResolveOsvvmOption(A, PassNameVar.GetOpt, OSVVM_DEFAULT_PASS_NAME) ;
end function ResolveOsvvmPassName ;
impure function ResolveOsvvmPassName(A, B : String) return string is
begin
return ResolveOsvvmOption(A, B, PassNameVar.GetOpt, OSVVM_DEFAULT_PASS_NAME) ;
end function ResolveOsvvmPassName ;
impure function ResolveOsvvmFailName(A : String) return string is
begin
return ResolveOsvvmOption(A, FailNameVar.GetOpt, OSVVM_DEFAULT_FAIL_NAME) ;
end function ResolveOsvvmFailName ;
impure function ResolveOsvvmFailName(A, B : String) return string is
begin
return ResolveOsvvmOption(A, B, FailNameVar.GetOpt, OSVVM_DEFAULT_FAIL_NAME) ;
end function ResolveOsvvmFailName ;
impure function ResolveCovWritePassFail(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WritePassFailVar.Get, OSVVM_DEFAULT_WRITE_PASS_FAIL) ;
end function ResolveCovWritePassFail ; -- Cov
impure function ResolveCovWriteBinInfo(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WriteBinInfoVar.Get, OSVVM_DEFAULT_WRITE_BIN_INFO) ;
end function ResolveCovWriteBinInfo ; -- Cov
impure function ResolveCovWriteCount(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WriteCountVar.Get, OSVVM_DEFAULT_WRITE_COUNT) ;
end function ResolveCovWriteCount ; -- Cov
impure function ResolveCovWriteAnyIllegal(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WriteAnyIllegalVar.Get, OSVVM_DEFAULT_WRITE_ANY_ILLEGAL) ;
end function ResolveCovWriteAnyIllegal ; -- Cov
procedure OsvvmDeallocate is
begin
-- Free up space used by NamePType within OsvvmGlobalPkg
WritePrefixVar.Deallocate ;
DoneNameVar.Deallocate ;
PassNameVar.Deallocate ;
FailNameVar.Deallocate ;
WritePassFailVar.Set(FALSE) ; -- := FALSE ;
WriteBinInfoVar.Set(TRUE ) ; -- := TRUE ;
WriteCountVar.Set(TRUE ) ; -- := TRUE ;
WriteAnyIllegalVar.Set(FALSE) ; -- := FALSE ;
end procedure OsvvmDeallocate ;
end package body OsvvmGlobalPkg ; |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net6,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net1,
G => net5,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net6,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net1,
G => vbias2,
S => net3
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net4,
G => net1,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net4
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
|
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for I2C WB Arbiter
---------------------------------------------------------------------------------------
-- File : i2c_arb_wb.vhd
-- Author : auto-generated by wbgen2 from i2c_arbiter_wb.wb
-- Created : Tue Jun 9 11:32:14 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE i2c_arbiter_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.i2c_arb_wbgen2_pkg.all;
entity wb_i2c_arb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_o : out t_i2c_arb_out_registers
);
end wb_i2c_arb_slave;
architecture syn of wb_i2c_arb_slave is
signal i2c_arb_cr_bypass_mode_int : std_logic ;
signal i2c_arb_cr_bypass_src_int : std_logic_vector(4 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(0 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
i2c_arb_cr_bypass_mode_int <= '0';
i2c_arb_cr_bypass_src_int <= "00000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
if (wb_we_i = '1') then
i2c_arb_cr_bypass_mode_int <= wrdata_reg(0);
i2c_arb_cr_bypass_src_int <= wrdata_reg(5 downto 1);
end if;
rddata_reg(0) <= i2c_arb_cr_bypass_mode_int;
rddata_reg(5 downto 1) <= i2c_arb_cr_bypass_src_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Bypass Mode
regs_o.cr_bypass_mode_o <= i2c_arb_cr_bypass_mode_int;
-- Bypass Input (Source)
regs_o.cr_bypass_src_o <= i2c_arb_cr_bypass_src_int;
rwaddr_reg <= (others => '0');
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
|
-------------------------------------------------------------------------------
--! @file nf_pkg.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-11
--! @brief NanoFIP package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--! @brief Package declaration of nf_pkg
--! @details
--! This provides types and constants for the NanoFIP component.
package nf_pkg is
---------------------------------------------------------------------------
-- Types and Constants
---------------------------------------------------------------------------
type nf_in_t is record
--! @brief Signals from NanoFIP
--! @param cmd_0 NF received FGClite CMD 0
--! @param tx_rdy NF transmitter ready
--! @param r_fcser NanoFIP status byte - bit 5
--! @param r_tler NanoFIP status byte - bit 4
--! @param u_cacer NanoFIP status byte - bit 2
--! @param u_pacer NanoFIP status byte - bit 3
--! @param rx_frame NF serial frame
--! @param rx_bit_en NF serial bit enable
--! @param rx NF serial data
cmd_0 : std_ulogic;
tx_rdy : std_ulogic;
r_fcser : std_ulogic;
r_tler : std_ulogic;
u_cacer : std_ulogic;
u_pacer : std_ulogic;
rx_frame : std_ulogic;
rx_bit_en : std_ulogic;
rx : std_ulogic;
end record nf_in_t;
type nf_out_t is record
--! @brief Signals to NanoFIP
--! @param tx_frame NF serial frame
--! @param tx_bit_en NF serial bit enable
--! @param tx NF serial data
tx_frame : std_ulogic;
tx_bit_en : std_ulogic;
tx : std_ulogic;
end record nf_out_t;
type nf_command_t is record
--! @brief Commands received from gateway
-- Command 0
sefi_test_vs_m0 : std_ulogic_vector(1 downto 0);
sefi_test_vs_m1 : std_ulogic_vector(1 downto 0);
sefi_test_ia_m0 : std_ulogic_vector(1 downto 0);
sefi_test_ia_m1 : std_ulogic_vector(1 downto 0);
sefi_test_ib_m0 : std_ulogic_vector(1 downto 0);
sefi_test_ib_m1 : std_ulogic_vector(1 downto 0);
ms_period : std_ulogic_vector(15 downto 0);
-- Command 1
serial_data : std_ulogic_vector(31 downto 0);
serial_data_en : std_ulogic;
-- Command 2
index : std_ulogic_vector(14 downto 0);
index_type : std_ulogic_vector(2 downto 0);
adc_log_freeze : std_ulogic;
dim_log_freeze : std_ulogic;
dim_reset : std_ulogic;
ow_scan : std_ulogic;
ow_bus_select : std_ulogic_vector(2 downto 0);
-- Command 3
v_ref : std_ulogic_vector(15 downto 0);
cal_source : std_ulogic_vector(1 downto 0);
cal_vs_en : std_ulogic;
cal_ia_en : std_ulogic;
cal_ib_en : std_ulogic;
adc_vs_reset_n : std_ulogic;
adc_ia_reset_n : std_ulogic;
adc_ib_reset_n : std_ulogic;
vs_cmd : std_ulogic_vector(7 downto 0);
end record nf_command_t;
type nf_status_t is record
--! @brief Status transmitted to gateway
adc_acc_vs_0 : std_ulogic_vector(31 downto 0);
adc_acc_vs_0_en : std_ulogic;
adc_acc_vs_1 : std_ulogic_vector(31 downto 0);
adc_acc_vs_1_en : std_ulogic;
adc_acc_ia_0 : std_ulogic_vector(31 downto 0);
adc_acc_ia_0_en : std_ulogic;
adc_acc_ia_1 : std_ulogic_vector(31 downto 0);
adc_acc_ia_1_en : std_ulogic;
adc_acc_ib_0 : std_ulogic_vector(31 downto 0);
adc_acc_ib_0_en : std_ulogic;
adc_acc_ib_1 : std_ulogic_vector(31 downto 0);
adc_acc_ib_1_en : std_ulogic;
dim_a_trig_lat : std_ulogic_vector(15 downto 0);
dim_a_trig_lat_en : std_ulogic;
dim_a_trig_unl : std_ulogic_vector(15 downto 0);
dim_a_trig_unl_en : std_ulogic;
dim_a1_ana_0 : std_ulogic_vector(15 downto 0);
dim_a1_ana_0_en : std_ulogic;
dim_a1_ana_1 : std_ulogic_vector(15 downto 0);
dim_a1_ana_1_en : std_ulogic;
dim_a1_ana_2 : std_ulogic_vector(15 downto 0);
dim_a1_ana_2_en : std_ulogic;
dim_a1_ana_3 : std_ulogic_vector(15 downto 0);
dim_a1_ana_3_en : std_ulogic;
cycle_period : std_ulogic_vector(31 downto 0);
cycle_period_en : std_ulogic;
version_cfnf : std_ulogic_vector(7 downto 0);
version_cfnf_en : std_ulogic;
version_xfpf : std_ulogic_vector(7 downto 0);
version_xfpf_en : std_ulogic;
adc_log_idx : std_ulogic_vector(15 downto 0);
adc_log_idx_en : std_ulogic;
dim_log_idx : std_ulogic_vector(15 downto 0);
dim_log_idx_en : std_ulogic;
vs_dig_in : std_ulogic_vector(15 downto 0);
vs_dig_in_en : std_ulogic;
vs_dig_out : std_ulogic_vector(7 downto 0);
vs_dig_out_en : std_ulogic;
seu_count : std_ulogic_vector(7 downto 0);
seu_count_en : std_ulogic;
fgc_status : std_ulogic_vector(15 downto 0);
fgc_status_en : std_ulogic;
backplane : std_ulogic_vector(7 downto 0);
backplane_en : std_ulogic;
serial_data : std_ulogic_vector(7 downto 0);
serial_num : std_ulogic_vector(3 downto 0);
serial_data_en : std_ulogic;
end record nf_status_t;
end package nf_pkg;
|
-- megafunction wizard: %ALTFP_EXP%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTFP_EXP
-- ============================================================
-- File Name: fp_exp.vhd
-- Megafunction Name(s):
-- ALTFP_EXP
--
-- Simulation Library Files(s):
--
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_exp CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=17 ROUNDING="TO_NEAREST" WIDTH_EXP=8 WIDTH_MAN=23 aclr clk_en clock data result
--VERSION_BEGIN 9.1SP2 cbx_altfp_exp 2010:03:24:20:34:20:SJ cbx_altmult_opt 2010:03:24:20:34:20:SJ cbx_cycloneii 2010:03:24:20:34:20:SJ cbx_lpm_add_sub 2010:03:24:20:34:20:SJ cbx_lpm_clshift 2010:03:24:20:34:20:SJ cbx_lpm_compare 2010:03:24:20:34:20:SJ cbx_lpm_mult 2010:03:24:20:34:20:SJ cbx_lpm_mux 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ cbx_padd 2010:03:24:20:34:20:SJ cbx_stratix 2010:03:24:20:34:20:SJ cbx_stratixii 2010:03:24:20:34:20:SJ cbx_util_mgl 2010:03:24:20:34:20:SJ VERSION_END
LIBRARY lpm;
USE lpm.lpm_components.all;
--synthesis_resources = lpm_add_sub 9 lpm_clshift 1 lpm_compare 3 lpm_mult 5 lpm_mux 3 mux21 124 reg 745
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_exp_altfp_exp_fkd IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_altfp_exp_fkd;
ARCHITECTURE RTL OF fp_exp_altfp_exp_fkd IS
SIGNAL barrel_shifter_underflow_dffe2_15_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_0 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_10 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_6 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_7 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_8 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_9 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_dffe1 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_extra_ln2_dffe_5_w_lg_q157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL fraction_dffe1 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_overflow_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_prod_dffe14 : STD_LOGIC_VECTOR(61 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_round_dffe15 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL result_pipe_dffe16 : STD_LOGIC_VECTOR(30 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL round_up_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_sign_dffe_w_lg_q448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_sign_dffe_w_lg_q434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tbl1_compare_dffe11_4_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL tbl1_compare_dffe11_4_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL tbl1_compare_dffe11_4_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL tbl1_compare_dffe11_4_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL tbl1_tbl2_prod_dffe12 : STD_LOGIC_VECTOR(30 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL tbl3_taylor_prod_dffe12 : STD_LOGIC_VECTOR(30 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_fixed_dffe_0 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_fixed_dffe_1 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_fixed_dffe_2 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_fixed_dffe_3 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_fixed_dffe_4 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL xf_pre_2_dffe10 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL xf_pre_dffe9 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL xi_exp_value_dffe4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL xi_ln2_prod_dffe7 : STD_LOGIC_VECTOR(45 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL xi_prod_dffe3 : STD_LOGIC_VECTOR(20 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_exp_minus_bias_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_minus_bias_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_minus_bias_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_add_bias_w_lg_w_result_range445w446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_value_add_bias_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_add_bias_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_add_bias_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_add_bias_w_result_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_value_man_over_w_lg_w_lg_w_result_range435w436w437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_value_man_over_w_lg_w_result_range435w436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_value_man_over_w_lg_w_lg_w_lg_w_result_range435w436w437w438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_value_man_over_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_man_over_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_man_over_w_result_range435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_invert_exp_value_dataa : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_invert_exp_value_result : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_invert_exp_value_w_result_range130w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_man_round_datab : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_man_round_result : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_one_minus_xf_dataa : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_one_minus_xf_result : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_x_fixed_minus_xiln2_datab : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL wire_x_fixed_minus_xiln2_result : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL wire_xf_minus_ln2_datab : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_xf_minus_ln2_result : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_xi_add_one_datab : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_xi_add_one_result : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_rbarrel_shift_result : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL wire_distance_overflow_comp_agb : STD_LOGIC;
SIGNAL wire_tbl1_compare_ageb : STD_LOGIC;
SIGNAL wire_underflow_compare_agb : STD_LOGIC;
SIGNAL wire_man_prod_result : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL wire_tbl1_tbl2_prod_result : STD_LOGIC_VECTOR (63 DOWNTO 0);
SIGNAL wire_tbl3_taylor_prod_datab : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL wire_tbl3_taylor_prod_result : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL wire_xi_ln2_prod_result : STD_LOGIC_VECTOR (45 DOWNTO 0);
SIGNAL wire_xi_prod_result : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL wire_table_one_data_2d : STD_LOGIC_2D(31 DOWNTO 0, 31 DOWNTO 0);
SIGNAL wire_table_one_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_table_three_data_2d : STD_LOGIC_2D(31 DOWNTO 0, 20 DOWNTO 0);
SIGNAL wire_table_three_result : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL wire_table_two_data_2d : STD_LOGIC_2D(31 DOWNTO 0, 25 DOWNTO 0);
SIGNAL wire_table_two_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_cin_to_bias_dataout : STD_LOGIC;
SIGNAL wire_exp_result_mux_prea_dataout : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_exp_result_mux_prea_w_lg_dataout557w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_exp_value_b4_biasa_dataout : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_exp_value_selecta_dataout : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL wire_exp_value_to_compare_muxa_dataout : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_exp_value_to_ln2a_dataout : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_extra_ln2_muxa_dataout : STD_LOGIC_VECTOR(30 DOWNTO 0);
SIGNAL wire_man_result_muxa_dataout : STD_LOGIC_VECTOR(22 DOWNTO 0);
SIGNAL wire_xf_muxa_dataout : STD_LOGIC_VECTOR(30 DOWNTO 0);
SIGNAL wire_w_lg_man_prod_shifted408w : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL wire_w_lg_man_prod_wire407w : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL wire_w_lg_underflow_w554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range10w34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range13w36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range16w38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range19w40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range22w42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range25w44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range28w46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_data_all_one_w_range47w119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range563w564w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range568w569w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range573w574w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range578w579w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range583w584w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range588w589w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range593w594w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range492w493w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range495w496w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range498w499w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range501w502w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range504w505w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range507w508w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range510w511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range513w514w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range516w517w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range519w520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range465w466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range522w523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range525w526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range528w529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range468w469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range471w472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range474w475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range477w478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range480w481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range483w484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range486w487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range489w490w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_underflow_w554w555w556w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_barrel_shifter_underflow553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_is_infinity_wo443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_is_nan_wo442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_is_zero_wo444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_underflow_w454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_data_not_zero_w_range116w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_prod_wo_range402w406w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_underflow_w554w555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_overflow_w536w537w538w539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_overflow_w536w537w538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_barrel_shifter_underflow549w550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_overflow_w542w543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_overflow_w536w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_barrel_shifter_underflow549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_distance_overflow447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_distance_overflow456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_overflow_w542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_overflow_w536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range78w79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range81w82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range84w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range51w52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range10w11w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range13w14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range16w17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range19w20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range22w23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range25w26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range54w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range28w29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range63w64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range66w67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range69w70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range72w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range75w76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range563w566w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range568w571w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range573w576w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range578w581w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range583w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range588w591w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range593w595w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_prod_result_range424w425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_prod_result_range421w422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_prod_result_range418w419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_prod_result_range415w416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL addr_val_more_than_one : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL barrel_shifter_data : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL barrel_shifter_distance : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL barrel_shifter_underflow : STD_LOGIC;
SIGNAL barrel_shifter_underflow_wi : STD_LOGIC;
SIGNAL distance_overflow : STD_LOGIC;
SIGNAL distance_overflow_val_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL distance_overflow_wi : STD_LOGIC;
SIGNAL exp_bias : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_bias_all_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_data_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_data_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_invert : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_one : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_result_out : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_result_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_value : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL extra_ln2 : STD_LOGIC;
SIGNAL fraction : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL fraction_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL fraction_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL gnd_w : STD_LOGIC;
SIGNAL guard_bit : STD_LOGIC;
SIGNAL input_is_infinity_wi : STD_LOGIC;
SIGNAL input_is_infinity_wo : STD_LOGIC;
SIGNAL input_is_nan_wi : STD_LOGIC;
SIGNAL input_is_nan_wo : STD_LOGIC;
SIGNAL input_is_zero_wi : STD_LOGIC;
SIGNAL input_is_zero_wo : STD_LOGIC;
SIGNAL ln2_w : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL man_data_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_overflow : STD_LOGIC;
SIGNAL man_overflow_wi : STD_LOGIC;
SIGNAL man_overflow_wo : STD_LOGIC;
SIGNAL man_prod_result : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL man_prod_shifted : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL man_prod_wi : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL man_prod_wire : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL man_prod_wo : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL man_result_all_ones : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_result_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_round_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_round_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL nan_w : STD_LOGIC;
SIGNAL negative_infinity : STD_LOGIC;
SIGNAL one_over_ln2_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL overflow_w : STD_LOGIC;
SIGNAL positive_infinity : STD_LOGIC;
SIGNAL result_pipe_wi : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL result_pipe_wo : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL result_underflow_w : STD_LOGIC;
SIGNAL round_bit : STD_LOGIC;
SIGNAL round_up : STD_LOGIC;
SIGNAL round_up_wi : STD_LOGIC;
SIGNAL round_up_wo : STD_LOGIC;
SIGNAL shifted_value : STD_LOGIC;
SIGNAL sign_w : STD_LOGIC;
SIGNAL sticky_bits : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL table_one_data : STD_LOGIC_VECTOR (1023 DOWNTO 0);
SIGNAL table_one_out : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL table_three_data : STD_LOGIC_VECTOR (671 DOWNTO 0);
SIGNAL table_three_out : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL table_three_out_tmp : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL table_two_data : STD_LOGIC_VECTOR (831 DOWNTO 0);
SIGNAL table_two_out : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL table_two_out_tmp : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL tbl1_compare_wi : STD_LOGIC;
SIGNAL tbl1_compare_wo : STD_LOGIC;
SIGNAL tbl1_tbl2_prod_wi : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL tbl1_tbl2_prod_wo : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL tbl3_taylor_prod_wi : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL tbl3_taylor_prod_wo : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL underflow_compare_val_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL underflow_w : STD_LOGIC;
SIGNAL x_fixed : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xf : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL xf_pre : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xf_pre_2_wi : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xf_pre_2_wo : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xf_pre_wi : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xf_pre_wo : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xi_exp_value : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL xi_exp_value_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL xi_exp_value_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL xi_ln2_prod_wi : STD_LOGIC_VECTOR (45 DOWNTO 0);
SIGNAL xi_ln2_prod_wo : STD_LOGIC_VECTOR (45 DOWNTO 0);
SIGNAL xi_prod_wi : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL xi_prod_wo : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL wire_w_data_range78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range10w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range16w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range8w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range559w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range565w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range570w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range575w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range590w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range567w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range572w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range577w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range582w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range587w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range592w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range563w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range568w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range573w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range578w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range583w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range588w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range593w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_value_wo_range129w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_w_exp_value_wo_range132w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_value_wo_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_prod_result_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_prod_result_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_prod_result_range418w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_prod_result_range415w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_prod_wo_range402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range494w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range497w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range500w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range506w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range509w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range512w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range515w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range492w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range495w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range498w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range501w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range507w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range510w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range513w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bits_range413w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bits_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bits_range420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bits_range423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_xf_pre_2_wo_range183w : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_w_xf_pre_wo_range177w : STD_LOGIC_VECTOR (30 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_clshift
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_SHIFTTYPE : STRING := "LOGICAL";
LPM_WIDTH : NATURAL;
LPM_WIDTHDIST : NATURAL;
lpm_type : STRING := "lpm_clshift"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
direction : IN STD_LOGIC := '0';
distance : IN STD_LOGIC_VECTOR(LPM_WIDTHDIST-1 DOWNTO 0);
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
underflow : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT lpm_mult
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTHA : NATURAL;
LPM_WIDTHB : NATURAL;
LPM_WIDTHP : NATURAL;
LPM_WIDTHS : NATURAL := 1;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_mult"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTHA-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR(LPM_WIDTHB-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(LPM_WIDTHP-1 DOWNTO 0);
sum : IN STD_LOGIC_VECTOR(LPM_WIDTHS-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
loop0 : FOR i IN 0 TO 61 GENERATE
wire_w_lg_man_prod_shifted408w(i) <= man_prod_shifted(i) AND wire_w_man_prod_wo_range402w(0);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 61 GENERATE
wire_w_lg_man_prod_wire407w(i) <= man_prod_wire(i) AND wire_w_lg_w_man_prod_wo_range402w406w(0);
END GENERATE loop1;
wire_w_lg_underflow_w554w(0) <= underflow_w AND wire_w_lg_barrel_shifter_underflow553w(0);
wire_w_lg_w_data_range10w34w(0) <= wire_w_data_range10w(0) AND wire_w_exp_data_all_one_w_range32w(0);
wire_w_lg_w_data_range13w36w(0) <= wire_w_data_range13w(0) AND wire_w_exp_data_all_one_w_range35w(0);
wire_w_lg_w_data_range16w38w(0) <= wire_w_data_range16w(0) AND wire_w_exp_data_all_one_w_range37w(0);
wire_w_lg_w_data_range19w40w(0) <= wire_w_data_range19w(0) AND wire_w_exp_data_all_one_w_range39w(0);
wire_w_lg_w_data_range22w42w(0) <= wire_w_data_range22w(0) AND wire_w_exp_data_all_one_w_range41w(0);
wire_w_lg_w_data_range25w44w(0) <= wire_w_data_range25w(0) AND wire_w_exp_data_all_one_w_range43w(0);
wire_w_lg_w_data_range28w46w(0) <= wire_w_data_range28w(0) AND wire_w_exp_data_all_one_w_range45w(0);
wire_w_lg_w_exp_data_all_one_w_range47w119w(0) <= wire_w_exp_data_all_one_w_range47w(0) AND wire_w_lg_w_man_data_not_zero_w_range116w118w(0);
wire_w_lg_w_exp_result_w_range563w564w(0) <= wire_w_exp_result_w_range563w(0) AND wire_w_exp_out_all_one_w_range559w(0);
wire_w_lg_w_exp_result_w_range568w569w(0) <= wire_w_exp_result_w_range568w(0) AND wire_w_exp_out_all_one_w_range565w(0);
wire_w_lg_w_exp_result_w_range573w574w(0) <= wire_w_exp_result_w_range573w(0) AND wire_w_exp_out_all_one_w_range570w(0);
wire_w_lg_w_exp_result_w_range578w579w(0) <= wire_w_exp_result_w_range578w(0) AND wire_w_exp_out_all_one_w_range575w(0);
wire_w_lg_w_exp_result_w_range583w584w(0) <= wire_w_exp_result_w_range583w(0) AND wire_w_exp_out_all_one_w_range580w(0);
wire_w_lg_w_exp_result_w_range588w589w(0) <= wire_w_exp_result_w_range588w(0) AND wire_w_exp_out_all_one_w_range585w(0);
wire_w_lg_w_exp_result_w_range593w594w(0) <= wire_w_exp_result_w_range593w(0) AND wire_w_exp_out_all_one_w_range590w(0);
wire_w_lg_w_man_round_wi_range492w493w(0) <= wire_w_man_round_wi_range492w(0) AND wire_w_man_result_all_ones_range491w(0);
wire_w_lg_w_man_round_wi_range495w496w(0) <= wire_w_man_round_wi_range495w(0) AND wire_w_man_result_all_ones_range494w(0);
wire_w_lg_w_man_round_wi_range498w499w(0) <= wire_w_man_round_wi_range498w(0) AND wire_w_man_result_all_ones_range497w(0);
wire_w_lg_w_man_round_wi_range501w502w(0) <= wire_w_man_round_wi_range501w(0) AND wire_w_man_result_all_ones_range500w(0);
wire_w_lg_w_man_round_wi_range504w505w(0) <= wire_w_man_round_wi_range504w(0) AND wire_w_man_result_all_ones_range503w(0);
wire_w_lg_w_man_round_wi_range507w508w(0) <= wire_w_man_round_wi_range507w(0) AND wire_w_man_result_all_ones_range506w(0);
wire_w_lg_w_man_round_wi_range510w511w(0) <= wire_w_man_round_wi_range510w(0) AND wire_w_man_result_all_ones_range509w(0);
wire_w_lg_w_man_round_wi_range513w514w(0) <= wire_w_man_round_wi_range513w(0) AND wire_w_man_result_all_ones_range512w(0);
wire_w_lg_w_man_round_wi_range516w517w(0) <= wire_w_man_round_wi_range516w(0) AND wire_w_man_result_all_ones_range515w(0);
wire_w_lg_w_man_round_wi_range519w520w(0) <= wire_w_man_round_wi_range519w(0) AND wire_w_man_result_all_ones_range518w(0);
wire_w_lg_w_man_round_wi_range465w466w(0) <= wire_w_man_round_wi_range465w(0) AND wire_w_man_result_all_ones_range463w(0);
wire_w_lg_w_man_round_wi_range522w523w(0) <= wire_w_man_round_wi_range522w(0) AND wire_w_man_result_all_ones_range521w(0);
wire_w_lg_w_man_round_wi_range525w526w(0) <= wire_w_man_round_wi_range525w(0) AND wire_w_man_result_all_ones_range524w(0);
wire_w_lg_w_man_round_wi_range528w529w(0) <= wire_w_man_round_wi_range528w(0) AND wire_w_man_result_all_ones_range527w(0);
wire_w_lg_w_man_round_wi_range468w469w(0) <= wire_w_man_round_wi_range468w(0) AND wire_w_man_result_all_ones_range467w(0);
wire_w_lg_w_man_round_wi_range471w472w(0) <= wire_w_man_round_wi_range471w(0) AND wire_w_man_result_all_ones_range470w(0);
wire_w_lg_w_man_round_wi_range474w475w(0) <= wire_w_man_round_wi_range474w(0) AND wire_w_man_result_all_ones_range473w(0);
wire_w_lg_w_man_round_wi_range477w478w(0) <= wire_w_man_round_wi_range477w(0) AND wire_w_man_result_all_ones_range476w(0);
wire_w_lg_w_man_round_wi_range480w481w(0) <= wire_w_man_round_wi_range480w(0) AND wire_w_man_result_all_ones_range479w(0);
wire_w_lg_w_man_round_wi_range483w484w(0) <= wire_w_man_round_wi_range483w(0) AND wire_w_man_result_all_ones_range482w(0);
wire_w_lg_w_man_round_wi_range486w487w(0) <= wire_w_man_round_wi_range486w(0) AND wire_w_man_result_all_ones_range485w(0);
wire_w_lg_w_man_round_wi_range489w490w(0) <= wire_w_man_round_wi_range489w(0) AND wire_w_man_result_all_ones_range488w(0);
wire_w_lg_w_lg_w_lg_underflow_w554w555w556w(0) <= NOT wire_w_lg_w_lg_underflow_w554w555w(0);
wire_w_lg_barrel_shifter_underflow553w(0) <= NOT barrel_shifter_underflow;
wire_w_lg_input_is_infinity_wo443w(0) <= NOT input_is_infinity_wo;
wire_w_lg_input_is_nan_wo442w(0) <= NOT input_is_nan_wo;
wire_w_lg_input_is_zero_wo444w(0) <= NOT input_is_zero_wo;
wire_w_lg_underflow_w454w(0) <= NOT underflow_w;
wire_w_lg_w_man_data_not_zero_w_range116w118w(0) <= NOT wire_w_man_data_not_zero_w_range116w(0);
wire_w_lg_w_man_prod_wo_range402w406w(0) <= NOT wire_w_man_prod_wo_range402w(0);
wire_w_lg_w_lg_underflow_w554w555w(0) <= wire_w_lg_underflow_w554w(0) OR negative_infinity;
wire_w_lg_w551w552w(0) <= wire_w551w(0) OR positive_infinity;
wire_w_lg_w_lg_w_lg_w_lg_overflow_w536w537w538w539w(0) <= wire_w_lg_w_lg_w_lg_overflow_w536w537w538w(0) OR input_is_infinity_wo;
wire_w551w(0) <= wire_w_lg_w_lg_barrel_shifter_underflow549w550w(0) OR nan_w;
wire_w_lg_w_lg_w_lg_overflow_w536w537w538w(0) <= wire_w_lg_w_lg_overflow_w536w537w(0) OR input_is_zero_wo;
wire_w_lg_w_lg_barrel_shifter_underflow549w550w(0) <= wire_w_lg_barrel_shifter_underflow549w(0) OR input_is_zero_wo;
wire_w_lg_w_lg_overflow_w542w543w(0) <= wire_w_lg_overflow_w542w(0) OR positive_infinity;
wire_w_lg_w_lg_overflow_w536w537w(0) <= wire_w_lg_overflow_w536w(0) OR nan_w;
wire_w_lg_barrel_shifter_underflow549w(0) <= barrel_shifter_underflow OR overflow_w;
wire_w_lg_distance_overflow447w(0) <= distance_overflow OR wire_exp_value_add_bias_w_lg_w_result_range445w446w(0);
wire_w_lg_distance_overflow456w(0) <= distance_overflow OR wire_exp_value_add_bias_w_result_range445w(0);
wire_w_lg_overflow_w542w(0) <= overflow_w OR nan_w;
wire_w_lg_overflow_w536w(0) <= overflow_w OR underflow_w;
wire_w_lg_w_data_range78w79w(0) <= wire_w_data_range78w(0) OR wire_w_man_data_not_zero_w_range77w(0);
wire_w_lg_w_data_range81w82w(0) <= wire_w_data_range81w(0) OR wire_w_man_data_not_zero_w_range80w(0);
wire_w_lg_w_data_range84w85w(0) <= wire_w_data_range84w(0) OR wire_w_man_data_not_zero_w_range83w(0);
wire_w_lg_w_data_range87w88w(0) <= wire_w_data_range87w(0) OR wire_w_man_data_not_zero_w_range86w(0);
wire_w_lg_w_data_range90w91w(0) <= wire_w_data_range90w(0) OR wire_w_man_data_not_zero_w_range89w(0);
wire_w_lg_w_data_range93w94w(0) <= wire_w_data_range93w(0) OR wire_w_man_data_not_zero_w_range92w(0);
wire_w_lg_w_data_range96w97w(0) <= wire_w_data_range96w(0) OR wire_w_man_data_not_zero_w_range95w(0);
wire_w_lg_w_data_range99w100w(0) <= wire_w_data_range99w(0) OR wire_w_man_data_not_zero_w_range98w(0);
wire_w_lg_w_data_range102w103w(0) <= wire_w_data_range102w(0) OR wire_w_man_data_not_zero_w_range101w(0);
wire_w_lg_w_data_range105w106w(0) <= wire_w_data_range105w(0) OR wire_w_man_data_not_zero_w_range104w(0);
wire_w_lg_w_data_range51w52w(0) <= wire_w_data_range51w(0) OR wire_w_man_data_not_zero_w_range49w(0);
wire_w_lg_w_data_range108w109w(0) <= wire_w_data_range108w(0) OR wire_w_man_data_not_zero_w_range107w(0);
wire_w_lg_w_data_range111w112w(0) <= wire_w_data_range111w(0) OR wire_w_man_data_not_zero_w_range110w(0);
wire_w_lg_w_data_range114w115w(0) <= wire_w_data_range114w(0) OR wire_w_man_data_not_zero_w_range113w(0);
wire_w_lg_w_data_range10w11w(0) <= wire_w_data_range10w(0) OR wire_w_exp_data_not_zero_w_range8w(0);
wire_w_lg_w_data_range13w14w(0) <= wire_w_data_range13w(0) OR wire_w_exp_data_not_zero_w_range12w(0);
wire_w_lg_w_data_range16w17w(0) <= wire_w_data_range16w(0) OR wire_w_exp_data_not_zero_w_range15w(0);
wire_w_lg_w_data_range19w20w(0) <= wire_w_data_range19w(0) OR wire_w_exp_data_not_zero_w_range18w(0);
wire_w_lg_w_data_range22w23w(0) <= wire_w_data_range22w(0) OR wire_w_exp_data_not_zero_w_range21w(0);
wire_w_lg_w_data_range25w26w(0) <= wire_w_data_range25w(0) OR wire_w_exp_data_not_zero_w_range24w(0);
wire_w_lg_w_data_range54w55w(0) <= wire_w_data_range54w(0) OR wire_w_man_data_not_zero_w_range53w(0);
wire_w_lg_w_data_range28w29w(0) <= wire_w_data_range28w(0) OR wire_w_exp_data_not_zero_w_range27w(0);
wire_w_lg_w_data_range57w58w(0) <= wire_w_data_range57w(0) OR wire_w_man_data_not_zero_w_range56w(0);
wire_w_lg_w_data_range60w61w(0) <= wire_w_data_range60w(0) OR wire_w_man_data_not_zero_w_range59w(0);
wire_w_lg_w_data_range63w64w(0) <= wire_w_data_range63w(0) OR wire_w_man_data_not_zero_w_range62w(0);
wire_w_lg_w_data_range66w67w(0) <= wire_w_data_range66w(0) OR wire_w_man_data_not_zero_w_range65w(0);
wire_w_lg_w_data_range69w70w(0) <= wire_w_data_range69w(0) OR wire_w_man_data_not_zero_w_range68w(0);
wire_w_lg_w_data_range72w73w(0) <= wire_w_data_range72w(0) OR wire_w_man_data_not_zero_w_range71w(0);
wire_w_lg_w_data_range75w76w(0) <= wire_w_data_range75w(0) OR wire_w_man_data_not_zero_w_range74w(0);
wire_w_lg_w_exp_result_w_range563w566w(0) <= wire_w_exp_result_w_range563w(0) OR wire_w_exp_out_not_zero_w_range561w(0);
wire_w_lg_w_exp_result_w_range568w571w(0) <= wire_w_exp_result_w_range568w(0) OR wire_w_exp_out_not_zero_w_range567w(0);
wire_w_lg_w_exp_result_w_range573w576w(0) <= wire_w_exp_result_w_range573w(0) OR wire_w_exp_out_not_zero_w_range572w(0);
wire_w_lg_w_exp_result_w_range578w581w(0) <= wire_w_exp_result_w_range578w(0) OR wire_w_exp_out_not_zero_w_range577w(0);
wire_w_lg_w_exp_result_w_range583w586w(0) <= wire_w_exp_result_w_range583w(0) OR wire_w_exp_out_not_zero_w_range582w(0);
wire_w_lg_w_exp_result_w_range588w591w(0) <= wire_w_exp_result_w_range588w(0) OR wire_w_exp_out_not_zero_w_range587w(0);
wire_w_lg_w_exp_result_w_range593w595w(0) <= wire_w_exp_result_w_range593w(0) OR wire_w_exp_out_not_zero_w_range592w(0);
wire_w_lg_w_man_prod_result_range424w425w(0) <= wire_w_man_prod_result_range424w(0) OR wire_w_sticky_bits_range423w(0);
wire_w_lg_w_man_prod_result_range421w422w(0) <= wire_w_man_prod_result_range421w(0) OR wire_w_sticky_bits_range420w(0);
wire_w_lg_w_man_prod_result_range418w419w(0) <= wire_w_man_prod_result_range418w(0) OR wire_w_sticky_bits_range417w(0);
wire_w_lg_w_man_prod_result_range415w416w(0) <= wire_w_man_prod_result_range415w(0) OR wire_w_sticky_bits_range413w(0);
addr_val_more_than_one <= "10111";
barrel_shifter_data <= ( "00000000" & "1" & fraction_wo & "000000");
barrel_shifter_distance <= wire_exp_value_selecta_dataout;
barrel_shifter_underflow <= barrel_shifter_underflow_dffe2_15_pipes14;
barrel_shifter_underflow_wi <= (wire_underflow_compare_agb AND exp_value_wo(8));
distance_overflow <= distance_overflow_dffe2_15_pipes14;
distance_overflow_val_w <= "00000110";
distance_overflow_wi <= (wire_distance_overflow_comp_agb AND (NOT exp_value_wo(8)));
exp_bias <= "01111111";
exp_bias_all_ones_w <= (OTHERS => '1');
exp_data_all_one_w <= ( wire_w_lg_w_data_range28w46w & wire_w_lg_w_data_range25w44w & wire_w_lg_w_data_range22w42w & wire_w_lg_w_data_range19w40w & wire_w_lg_w_data_range16w38w & wire_w_lg_w_data_range13w36w & wire_w_lg_w_data_range10w34w & data(23));
exp_data_not_zero_w <= ( wire_w_lg_w_data_range28w29w & wire_w_lg_w_data_range25w26w & wire_w_lg_w_data_range22w23w & wire_w_lg_w_data_range19w20w & wire_w_lg_w_data_range16w17w & wire_w_lg_w_data_range13w14w & wire_w_lg_w_data_range10w11w & data(23));
exp_invert <= (xi_exp_value XOR exp_bias_all_ones_w);
exp_one <= ( wire_w_lg_w_lg_overflow_w542w543w & "1111111");
exp_out_all_one_w <= ( wire_w_lg_w_exp_result_w_range593w594w & wire_w_lg_w_exp_result_w_range588w589w & wire_w_lg_w_exp_result_w_range583w584w & wire_w_lg_w_exp_result_w_range578w579w & wire_w_lg_w_exp_result_w_range573w574w & wire_w_lg_w_exp_result_w_range568w569w & wire_w_lg_w_exp_result_w_range563w564w & exp_result_w(0));
exp_out_not_zero_w <= ( wire_w_lg_w_exp_result_w_range593w595w & wire_w_lg_w_exp_result_w_range588w591w & wire_w_lg_w_exp_result_w_range583w586w & wire_w_lg_w_exp_result_w_range578w581w & wire_w_lg_w_exp_result_w_range573w576w & wire_w_lg_w_exp_result_w_range568w571w & wire_w_lg_w_exp_result_w_range563w566w & exp_result_w(0));
exp_result_out <= wire_exp_result_mux_prea_w_lg_dataout557w;
exp_result_w <= wire_exp_value_man_over_result(7 DOWNTO 0);
exp_value <= wire_exp_minus_bias_result;
exp_value_wi <= exp_value;
exp_value_wo <= exp_value_dffe1;
exp_w <= data(30 DOWNTO 23);
extra_ln2 <= ((NOT xf_pre(37)) AND sign_dffe8);
fraction <= ( data(22 DOWNTO 0));
fraction_wi <= fraction;
fraction_wo <= fraction_dffe1;
gnd_w <= '0';
guard_bit <= man_prod_result(35);
input_is_infinity_wi <= wire_w_lg_w_exp_data_all_one_w_range47w119w(0);
input_is_infinity_wo <= input_is_infinity_16_pipes15;
input_is_nan_wi <= (exp_data_all_one_w(7) AND man_data_not_zero_w(22));
input_is_nan_wo <= input_is_nan_16_pipes15;
input_is_zero_wi <= (NOT exp_data_not_zero_w(7));
input_is_zero_wo <= input_is_zero_16_pipes15;
ln2_w <= "10110001011100100001011111110111110100";
man_data_not_zero_w <= ( wire_w_lg_w_data_range114w115w & wire_w_lg_w_data_range111w112w & wire_w_lg_w_data_range108w109w & wire_w_lg_w_data_range105w106w & wire_w_lg_w_data_range102w103w & wire_w_lg_w_data_range99w100w & wire_w_lg_w_data_range96w97w & wire_w_lg_w_data_range93w94w & wire_w_lg_w_data_range90w91w & wire_w_lg_w_data_range87w88w & wire_w_lg_w_data_range84w85w & wire_w_lg_w_data_range81w82w & wire_w_lg_w_data_range78w79w & wire_w_lg_w_data_range75w76w & wire_w_lg_w_data_range72w73w & wire_w_lg_w_data_range69w70w & wire_w_lg_w_data_range66w67w & wire_w_lg_w_data_range63w64w & wire_w_lg_w_data_range60w61w & wire_w_lg_w_data_range57w58w & wire_w_lg_w_data_range54w55w & wire_w_lg_w_data_range51w52w & data(0));
man_overflow <= (round_up AND man_result_all_ones(22));
man_overflow_wi <= man_overflow;
man_overflow_wo <= man_overflow_dffe15;
man_prod_result <= (wire_w_lg_man_prod_shifted408w OR wire_w_lg_man_prod_wire407w);
man_prod_shifted <= ( gnd_w & man_prod_wo(61 DOWNTO 1));
man_prod_wi <= wire_man_prod_result;
man_prod_wire <= man_prod_wo;
man_prod_wo <= man_prod_dffe14;
man_result_all_ones <= ( wire_w_lg_w_man_round_wi_range528w529w & wire_w_lg_w_man_round_wi_range525w526w & wire_w_lg_w_man_round_wi_range522w523w & wire_w_lg_w_man_round_wi_range519w520w & wire_w_lg_w_man_round_wi_range516w517w & wire_w_lg_w_man_round_wi_range513w514w & wire_w_lg_w_man_round_wi_range510w511w & wire_w_lg_w_man_round_wi_range507w508w & wire_w_lg_w_man_round_wi_range504w505w & wire_w_lg_w_man_round_wi_range501w502w & wire_w_lg_w_man_round_wi_range498w499w & wire_w_lg_w_man_round_wi_range495w496w & wire_w_lg_w_man_round_wi_range492w493w & wire_w_lg_w_man_round_wi_range489w490w & wire_w_lg_w_man_round_wi_range486w487w & wire_w_lg_w_man_round_wi_range483w484w & wire_w_lg_w_man_round_wi_range480w481w & wire_w_lg_w_man_round_wi_range477w478w & wire_w_lg_w_man_round_wi_range474w475w & wire_w_lg_w_man_round_wi_range471w472w & wire_w_lg_w_man_round_wi_range468w469w & wire_w_lg_w_man_round_wi_range465w466w & man_round_wi(0));
man_result_w <= wire_man_result_muxa_dataout;
man_round_wi <= man_prod_result(57 DOWNTO 35);
man_round_wo <= man_round_dffe15;
nan_w <= input_is_nan_wo;
negative_infinity <= (sign_dffe15 AND input_is_infinity_wo);
one_over_ln2_w <= "101110001";
overflow_w <= (((wire_sign_dffe_w_lg_q434w(0) AND ((wire_w_lg_distance_overflow456w(0) OR exp_out_all_one_w(7)) OR wire_exp_value_man_over_result(8))) AND wire_w_lg_underflow_w454w(0)) AND wire_w_lg_input_is_nan_wo442w(0));
positive_infinity <= (wire_sign_dffe_w_lg_q434w(0) AND input_is_infinity_wo);
result <= ( "0" & result_pipe_wo);
result_pipe_wi <= ( exp_result_out & man_result_w);
result_pipe_wo <= result_pipe_dffe16;
result_underflow_w <= ((NOT exp_out_not_zero_w(7)) AND wire_exp_value_man_over_w_lg_w_lg_w_lg_w_result_range435w436w437w438w(0));
round_bit <= man_prod_result(34);
round_up <= (round_bit AND (guard_bit OR sticky_bits(4)));
round_up_wi <= round_up;
round_up_wo <= round_up_dffe15;
shifted_value <= (tbl1_compare_wo OR man_prod_wo(59));
sign_w <= data(31);
sticky_bits <= ( wire_w_lg_w_man_prod_result_range424w425w & wire_w_lg_w_man_prod_result_range421w422w & wire_w_lg_w_man_prod_result_range418w419w & wire_w_lg_w_man_prod_result_range415w416w & man_prod_result(33));
table_one_data <= ( "10101000100111100001011100110110" & "10100011011011100000001001111010" & "10011110011001101100101000011001" & "10011001100001110010110000111101" & "10010100110011011111000011111001" & "10010000001110011110100111111000" & "10001011110010011111001000110010" & "10000111011111001110110110100011" & "10000011010100011100100100000011" & "11111110100011101111001100001100" & "11110110101110011111100100100000" & "11101111001000101010111011111100" & "11100111110001110010111011000010" & "11100000101001011010000110001001" & "11011001101111000011111011100100" & "11010011000010010100110001110000" & "11001100100010110001110101101010" & "11000110010000000001001000111011" & "11000000001001101001100000011010" & "10111010001111010010100010011110" & "10110100100000100100100101100101" & "10101110111101001000101110110000" & "10101001100100101000110000000110" & "10100100010110101111000111100001" & "10011111010011000110111101010101" & "10011010011001011100000010111000" & "10010101101001011010110001011001" & "10010001000010110000001000101101" & "10001100100101001001101110000011" & "10001000010000010101101010111011" & "10000100000100000010101100000000" & "10000000000000000000000000000000");
table_one_out <= wire_table_one_result;
table_three_data <= ( "111110000001111000001" & "111100000001110000100" & "111010000001101001001" & "111000000001100010000" & "110110000001011011001" & "110100000001010100100" & "110010000001001110001" & "110000000001001000000" & "101110000001000010001" & "101100000000111100100" & "101010000000110111001" & "101000000000110010000" & "100110000000101101001" & "100100000000101000100" & "100010000000100100001" & "100000000000100000000" & "011110000000011100001" & "011100000000011000100" & "011010000000010101001" & "011000000000010010000" & "010110000000001111001" & "010100000000001100100" & "010010000000001010001" & "010000000000001000000" & "001110000000000110001" & "001100000000000100100" & "001010000000000011001" & "001000000000000010000" & "000110000000000001001" & "000100000000000000100" & "000010000000000000001" & "000000000000000000000");
table_three_out <= ( "1" & "0000000000" & table_three_out_tmp);
table_three_out_tmp <= wire_table_three_result;
table_two_data <= ( "11111011110010101100010101" & "11110011100011001101101010" & "11101011010100001111111011" & "11100011000101110011000111" & "11011010110111110111001100" & "11010010101010011100001000" & "11001010011101100001111000" & "11000010010001001000011011" & "10111010000101001111101110" & "10110001111001110111110000" & "10101001101111000000011110" & "10100001100100101001110111" & "10011001011010110011111000" & "10010001010001011110100000" & "10001001001000101001101100" & "10000001000000010101011010" & "01111000111000100001101001" & "01110000110001001110010101" & "01101000101010011011011110" & "01100000100100001001000001" & "01011000011110010110111100" & "01010000011001000101001110" & "01001000010100010011110011" & "01000000010000000010101011" & "00111000001100010001110010" & "00110000001001000001001000" & "00101000000110010000101001" & "00100000000100000000010101" & "00011000000010010000001001" & "00010000000001000000000010" & "00001000000000010000000000" & "00000000000000000000000000");
table_two_out <= ( "1" & "00000" & table_two_out_tmp);
table_two_out_tmp <= wire_table_two_result;
tbl1_compare_wi <= wire_tbl1_compare_ageb;
tbl1_compare_wo <= tbl1_compare_dffe11_4_pipes3;
tbl1_tbl2_prod_wi <= wire_tbl1_tbl2_prod_result(63 DOWNTO 33);
tbl1_tbl2_prod_wo <= tbl1_tbl2_prod_dffe12;
tbl3_taylor_prod_wi <= wire_tbl3_taylor_prod_result(61 DOWNTO 31);
tbl3_taylor_prod_wo <= tbl3_taylor_prod_dffe12;
underflow_compare_val_w <= "00011101";
underflow_w <= (((((result_underflow_w OR barrel_shifter_underflow) OR wire_sign_dffe_w_lg_q448w(0)) AND wire_w_lg_input_is_zero_wo444w(0)) AND wire_w_lg_input_is_infinity_wo443w(0)) AND wire_w_lg_input_is_nan_wo442w(0));
x_fixed <= wire_rbarrel_shift_result;
xf <= wire_xf_muxa_dataout;
xf_pre <= wire_x_fixed_minus_xiln2_result;
xf_pre_2_wi <= xf_pre_wo;
xf_pre_2_wo <= xf_pre_2_dffe10;
xf_pre_wi <= xf_pre;
xf_pre_wo <= xf_pre_dffe9;
xi_exp_value <= xi_prod_wo(18 DOWNTO 11);
xi_exp_value_wi <= xi_exp_value;
xi_exp_value_wo <= xi_exp_value_dffe4;
xi_ln2_prod_wi <= wire_xi_ln2_prod_result;
xi_ln2_prod_wo <= xi_ln2_prod_dffe7;
xi_prod_wi <= wire_xi_prod_result;
xi_prod_wo <= xi_prod_dffe3;
wire_w_data_range78w(0) <= data(10);
wire_w_data_range81w(0) <= data(11);
wire_w_data_range84w(0) <= data(12);
wire_w_data_range87w(0) <= data(13);
wire_w_data_range90w(0) <= data(14);
wire_w_data_range93w(0) <= data(15);
wire_w_data_range96w(0) <= data(16);
wire_w_data_range99w(0) <= data(17);
wire_w_data_range102w(0) <= data(18);
wire_w_data_range105w(0) <= data(19);
wire_w_data_range51w(0) <= data(1);
wire_w_data_range108w(0) <= data(20);
wire_w_data_range111w(0) <= data(21);
wire_w_data_range114w(0) <= data(22);
wire_w_data_range10w(0) <= data(24);
wire_w_data_range13w(0) <= data(25);
wire_w_data_range16w(0) <= data(26);
wire_w_data_range19w(0) <= data(27);
wire_w_data_range22w(0) <= data(28);
wire_w_data_range25w(0) <= data(29);
wire_w_data_range54w(0) <= data(2);
wire_w_data_range28w(0) <= data(30);
wire_w_data_range57w(0) <= data(3);
wire_w_data_range60w(0) <= data(4);
wire_w_data_range63w(0) <= data(5);
wire_w_data_range66w(0) <= data(6);
wire_w_data_range69w(0) <= data(7);
wire_w_data_range72w(0) <= data(8);
wire_w_data_range75w(0) <= data(9);
wire_w_exp_data_all_one_w_range32w(0) <= exp_data_all_one_w(0);
wire_w_exp_data_all_one_w_range35w(0) <= exp_data_all_one_w(1);
wire_w_exp_data_all_one_w_range37w(0) <= exp_data_all_one_w(2);
wire_w_exp_data_all_one_w_range39w(0) <= exp_data_all_one_w(3);
wire_w_exp_data_all_one_w_range41w(0) <= exp_data_all_one_w(4);
wire_w_exp_data_all_one_w_range43w(0) <= exp_data_all_one_w(5);
wire_w_exp_data_all_one_w_range45w(0) <= exp_data_all_one_w(6);
wire_w_exp_data_all_one_w_range47w(0) <= exp_data_all_one_w(7);
wire_w_exp_data_not_zero_w_range8w(0) <= exp_data_not_zero_w(0);
wire_w_exp_data_not_zero_w_range12w(0) <= exp_data_not_zero_w(1);
wire_w_exp_data_not_zero_w_range15w(0) <= exp_data_not_zero_w(2);
wire_w_exp_data_not_zero_w_range18w(0) <= exp_data_not_zero_w(3);
wire_w_exp_data_not_zero_w_range21w(0) <= exp_data_not_zero_w(4);
wire_w_exp_data_not_zero_w_range24w(0) <= exp_data_not_zero_w(5);
wire_w_exp_data_not_zero_w_range27w(0) <= exp_data_not_zero_w(6);
wire_w_exp_out_all_one_w_range559w(0) <= exp_out_all_one_w(0);
wire_w_exp_out_all_one_w_range565w(0) <= exp_out_all_one_w(1);
wire_w_exp_out_all_one_w_range570w(0) <= exp_out_all_one_w(2);
wire_w_exp_out_all_one_w_range575w(0) <= exp_out_all_one_w(3);
wire_w_exp_out_all_one_w_range580w(0) <= exp_out_all_one_w(4);
wire_w_exp_out_all_one_w_range585w(0) <= exp_out_all_one_w(5);
wire_w_exp_out_all_one_w_range590w(0) <= exp_out_all_one_w(6);
wire_w_exp_out_not_zero_w_range561w(0) <= exp_out_not_zero_w(0);
wire_w_exp_out_not_zero_w_range567w(0) <= exp_out_not_zero_w(1);
wire_w_exp_out_not_zero_w_range572w(0) <= exp_out_not_zero_w(2);
wire_w_exp_out_not_zero_w_range577w(0) <= exp_out_not_zero_w(3);
wire_w_exp_out_not_zero_w_range582w(0) <= exp_out_not_zero_w(4);
wire_w_exp_out_not_zero_w_range587w(0) <= exp_out_not_zero_w(5);
wire_w_exp_out_not_zero_w_range592w(0) <= exp_out_not_zero_w(6);
wire_w_exp_result_w_range563w(0) <= exp_result_w(1);
wire_w_exp_result_w_range568w(0) <= exp_result_w(2);
wire_w_exp_result_w_range573w(0) <= exp_result_w(3);
wire_w_exp_result_w_range578w(0) <= exp_result_w(4);
wire_w_exp_result_w_range583w(0) <= exp_result_w(5);
wire_w_exp_result_w_range588w(0) <= exp_result_w(6);
wire_w_exp_result_w_range593w(0) <= exp_result_w(7);
wire_w_exp_value_wo_range129w <= exp_value_wo(5 DOWNTO 0);
wire_w_exp_value_wo_range132w <= exp_value_wo(7 DOWNTO 0);
wire_w_exp_value_wo_range131w(0) <= exp_value_wo(8);
wire_w_man_data_not_zero_w_range49w(0) <= man_data_not_zero_w(0);
wire_w_man_data_not_zero_w_range80w(0) <= man_data_not_zero_w(10);
wire_w_man_data_not_zero_w_range83w(0) <= man_data_not_zero_w(11);
wire_w_man_data_not_zero_w_range86w(0) <= man_data_not_zero_w(12);
wire_w_man_data_not_zero_w_range89w(0) <= man_data_not_zero_w(13);
wire_w_man_data_not_zero_w_range92w(0) <= man_data_not_zero_w(14);
wire_w_man_data_not_zero_w_range95w(0) <= man_data_not_zero_w(15);
wire_w_man_data_not_zero_w_range98w(0) <= man_data_not_zero_w(16);
wire_w_man_data_not_zero_w_range101w(0) <= man_data_not_zero_w(17);
wire_w_man_data_not_zero_w_range104w(0) <= man_data_not_zero_w(18);
wire_w_man_data_not_zero_w_range107w(0) <= man_data_not_zero_w(19);
wire_w_man_data_not_zero_w_range53w(0) <= man_data_not_zero_w(1);
wire_w_man_data_not_zero_w_range110w(0) <= man_data_not_zero_w(20);
wire_w_man_data_not_zero_w_range113w(0) <= man_data_not_zero_w(21);
wire_w_man_data_not_zero_w_range116w(0) <= man_data_not_zero_w(22);
wire_w_man_data_not_zero_w_range56w(0) <= man_data_not_zero_w(2);
wire_w_man_data_not_zero_w_range59w(0) <= man_data_not_zero_w(3);
wire_w_man_data_not_zero_w_range62w(0) <= man_data_not_zero_w(4);
wire_w_man_data_not_zero_w_range65w(0) <= man_data_not_zero_w(5);
wire_w_man_data_not_zero_w_range68w(0) <= man_data_not_zero_w(6);
wire_w_man_data_not_zero_w_range71w(0) <= man_data_not_zero_w(7);
wire_w_man_data_not_zero_w_range74w(0) <= man_data_not_zero_w(8);
wire_w_man_data_not_zero_w_range77w(0) <= man_data_not_zero_w(9);
wire_w_man_prod_result_range424w(0) <= man_prod_result(29);
wire_w_man_prod_result_range421w(0) <= man_prod_result(30);
wire_w_man_prod_result_range418w(0) <= man_prod_result(31);
wire_w_man_prod_result_range415w(0) <= man_prod_result(32);
wire_w_man_prod_wo_range402w(0) <= man_prod_wo(59);
wire_w_man_result_all_ones_range463w(0) <= man_result_all_ones(0);
wire_w_man_result_all_ones_range494w(0) <= man_result_all_ones(10);
wire_w_man_result_all_ones_range497w(0) <= man_result_all_ones(11);
wire_w_man_result_all_ones_range500w(0) <= man_result_all_ones(12);
wire_w_man_result_all_ones_range503w(0) <= man_result_all_ones(13);
wire_w_man_result_all_ones_range506w(0) <= man_result_all_ones(14);
wire_w_man_result_all_ones_range509w(0) <= man_result_all_ones(15);
wire_w_man_result_all_ones_range512w(0) <= man_result_all_ones(16);
wire_w_man_result_all_ones_range515w(0) <= man_result_all_ones(17);
wire_w_man_result_all_ones_range518w(0) <= man_result_all_ones(18);
wire_w_man_result_all_ones_range521w(0) <= man_result_all_ones(19);
wire_w_man_result_all_ones_range467w(0) <= man_result_all_ones(1);
wire_w_man_result_all_ones_range524w(0) <= man_result_all_ones(20);
wire_w_man_result_all_ones_range527w(0) <= man_result_all_ones(21);
wire_w_man_result_all_ones_range470w(0) <= man_result_all_ones(2);
wire_w_man_result_all_ones_range473w(0) <= man_result_all_ones(3);
wire_w_man_result_all_ones_range476w(0) <= man_result_all_ones(4);
wire_w_man_result_all_ones_range479w(0) <= man_result_all_ones(5);
wire_w_man_result_all_ones_range482w(0) <= man_result_all_ones(6);
wire_w_man_result_all_ones_range485w(0) <= man_result_all_ones(7);
wire_w_man_result_all_ones_range488w(0) <= man_result_all_ones(8);
wire_w_man_result_all_ones_range491w(0) <= man_result_all_ones(9);
wire_w_man_round_wi_range492w(0) <= man_round_wi(10);
wire_w_man_round_wi_range495w(0) <= man_round_wi(11);
wire_w_man_round_wi_range498w(0) <= man_round_wi(12);
wire_w_man_round_wi_range501w(0) <= man_round_wi(13);
wire_w_man_round_wi_range504w(0) <= man_round_wi(14);
wire_w_man_round_wi_range507w(0) <= man_round_wi(15);
wire_w_man_round_wi_range510w(0) <= man_round_wi(16);
wire_w_man_round_wi_range513w(0) <= man_round_wi(17);
wire_w_man_round_wi_range516w(0) <= man_round_wi(18);
wire_w_man_round_wi_range519w(0) <= man_round_wi(19);
wire_w_man_round_wi_range465w(0) <= man_round_wi(1);
wire_w_man_round_wi_range522w(0) <= man_round_wi(20);
wire_w_man_round_wi_range525w(0) <= man_round_wi(21);
wire_w_man_round_wi_range528w(0) <= man_round_wi(22);
wire_w_man_round_wi_range468w(0) <= man_round_wi(2);
wire_w_man_round_wi_range471w(0) <= man_round_wi(3);
wire_w_man_round_wi_range474w(0) <= man_round_wi(4);
wire_w_man_round_wi_range477w(0) <= man_round_wi(5);
wire_w_man_round_wi_range480w(0) <= man_round_wi(6);
wire_w_man_round_wi_range483w(0) <= man_round_wi(7);
wire_w_man_round_wi_range486w(0) <= man_round_wi(8);
wire_w_man_round_wi_range489w(0) <= man_round_wi(9);
wire_w_sticky_bits_range413w(0) <= sticky_bits(0);
wire_w_sticky_bits_range417w(0) <= sticky_bits(1);
wire_w_sticky_bits_range420w(0) <= sticky_bits(2);
wire_w_sticky_bits_range423w(0) <= sticky_bits(3);
wire_w_xf_pre_2_wo_range183w <= xf_pre_2_wo(30 DOWNTO 0);
wire_w_xf_pre_wo_range177w <= xf_pre_wo(30 DOWNTO 0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes0 <= barrel_shifter_underflow_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes1 <= barrel_shifter_underflow_dffe2_15_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes2 <= barrel_shifter_underflow_dffe2_15_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes3 <= barrel_shifter_underflow_dffe2_15_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes4 <= barrel_shifter_underflow_dffe2_15_pipes3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes5 <= barrel_shifter_underflow_dffe2_15_pipes4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes6 <= barrel_shifter_underflow_dffe2_15_pipes5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes7 <= barrel_shifter_underflow_dffe2_15_pipes6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes8 <= barrel_shifter_underflow_dffe2_15_pipes7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes9 <= barrel_shifter_underflow_dffe2_15_pipes8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes10 <= barrel_shifter_underflow_dffe2_15_pipes9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes11 <= barrel_shifter_underflow_dffe2_15_pipes10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes12 <= barrel_shifter_underflow_dffe2_15_pipes11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes13 <= barrel_shifter_underflow_dffe2_15_pipes12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes14 <= barrel_shifter_underflow_dffe2_15_pipes13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes0 <= distance_overflow_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes1 <= distance_overflow_dffe2_15_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes2 <= distance_overflow_dffe2_15_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes3 <= distance_overflow_dffe2_15_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes4 <= distance_overflow_dffe2_15_pipes3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes5 <= distance_overflow_dffe2_15_pipes4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes6 <= distance_overflow_dffe2_15_pipes5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes7 <= distance_overflow_dffe2_15_pipes6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes8 <= distance_overflow_dffe2_15_pipes7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes9 <= distance_overflow_dffe2_15_pipes8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes10 <= distance_overflow_dffe2_15_pipes9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes11 <= distance_overflow_dffe2_15_pipes10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes12 <= distance_overflow_dffe2_15_pipes11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes13 <= distance_overflow_dffe2_15_pipes12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes14 <= distance_overflow_dffe2_15_pipes13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_0 <= wire_exp_value_b4_biasa_dataout;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_1 <= exp_value_b4_bias_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_10 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_10 <= exp_value_b4_bias_dffe_9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_2 <= exp_value_b4_bias_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_3 <= exp_value_b4_bias_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_4 <= exp_value_b4_bias_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_5 <= exp_value_b4_bias_dffe_4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_6 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_6 <= exp_value_b4_bias_dffe_5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_7 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_7 <= exp_value_b4_bias_dffe_6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_8 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_8 <= exp_value_b4_bias_dffe_7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_9 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_9 <= exp_value_b4_bias_dffe_8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_dffe1 <= exp_value_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_0 <= extra_ln2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_1 <= extra_ln2_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_2 <= extra_ln2_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_3 <= extra_ln2_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_4 <= extra_ln2_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_5 <= extra_ln2_dffe_4;
END IF;
END IF;
END PROCESS;
wire_extra_ln2_dffe_5_w_lg_q157w(0) <= NOT extra_ln2_dffe_5;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN fraction_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN fraction_dffe1 <= fraction_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes0 <= input_is_infinity_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes1 <= input_is_infinity_16_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes2 <= input_is_infinity_16_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes3 <= input_is_infinity_16_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes4 <= input_is_infinity_16_pipes3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes5 <= input_is_infinity_16_pipes4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes6 <= input_is_infinity_16_pipes5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes7 <= input_is_infinity_16_pipes6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes8 <= input_is_infinity_16_pipes7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes9 <= input_is_infinity_16_pipes8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes10 <= input_is_infinity_16_pipes9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes11 <= input_is_infinity_16_pipes10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes12 <= input_is_infinity_16_pipes11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes13 <= input_is_infinity_16_pipes12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes14 <= input_is_infinity_16_pipes13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes15 <= input_is_infinity_16_pipes14;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes0 <= input_is_nan_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes1 <= input_is_nan_16_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes2 <= input_is_nan_16_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes3 <= input_is_nan_16_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes4 <= input_is_nan_16_pipes3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes5 <= input_is_nan_16_pipes4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes6 <= input_is_nan_16_pipes5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes7 <= input_is_nan_16_pipes6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes8 <= input_is_nan_16_pipes7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes9 <= input_is_nan_16_pipes8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes10 <= input_is_nan_16_pipes9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes11 <= input_is_nan_16_pipes10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes12 <= input_is_nan_16_pipes11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes13 <= input_is_nan_16_pipes12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes14 <= input_is_nan_16_pipes13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes15 <= input_is_nan_16_pipes14;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes0 <= input_is_zero_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes1 <= input_is_zero_16_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes2 <= input_is_zero_16_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes3 <= input_is_zero_16_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes4 <= input_is_zero_16_pipes3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes5 <= input_is_zero_16_pipes4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes6 <= input_is_zero_16_pipes5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes7 <= input_is_zero_16_pipes6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes8 <= input_is_zero_16_pipes7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes9 <= input_is_zero_16_pipes8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes10 <= input_is_zero_16_pipes9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes11 <= input_is_zero_16_pipes10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes12 <= input_is_zero_16_pipes11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes13 <= input_is_zero_16_pipes12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes14 <= input_is_zero_16_pipes13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes15 <= input_is_zero_16_pipes14;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_overflow_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_overflow_dffe15 <= man_overflow_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_prod_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_prod_dffe14 <= man_prod_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_dffe15 <= man_round_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN result_pipe_dffe16 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN result_pipe_dffe16 <= result_pipe_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_up_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_up_dffe15 <= round_up_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe0 <= sign_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe1 <= sign_dffe0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe2 <= sign_dffe1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe3 <= sign_dffe2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe4 <= sign_dffe3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe5 <= sign_dffe4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe6 <= sign_dffe5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe7 <= sign_dffe6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe8 <= sign_dffe7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe9 <= sign_dffe8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe10 <= sign_dffe9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe11 <= sign_dffe10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe12 <= sign_dffe11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe13 <= sign_dffe12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe14 <= sign_dffe13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe15 <= sign_dffe14;
END IF;
END IF;
END PROCESS;
wire_sign_dffe_w_lg_q448w(0) <= sign_dffe15 AND wire_w_lg_distance_overflow447w(0);
wire_sign_dffe_w_lg_q434w(0) <= NOT sign_dffe15;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl1_compare_dffe11_4_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl1_compare_dffe11_4_pipes0 <= tbl1_compare_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl1_compare_dffe11_4_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl1_compare_dffe11_4_pipes1 <= tbl1_compare_dffe11_4_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl1_compare_dffe11_4_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl1_compare_dffe11_4_pipes2 <= tbl1_compare_dffe11_4_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl1_compare_dffe11_4_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl1_compare_dffe11_4_pipes3 <= tbl1_compare_dffe11_4_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl1_tbl2_prod_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl1_tbl2_prod_dffe12 <= tbl1_tbl2_prod_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl3_taylor_prod_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl3_taylor_prod_dffe12 <= tbl3_taylor_prod_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_fixed_dffe_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_fixed_dffe_0 <= x_fixed;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_fixed_dffe_1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_fixed_dffe_1 <= x_fixed_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_fixed_dffe_2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_fixed_dffe_2 <= x_fixed_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_fixed_dffe_3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_fixed_dffe_3 <= x_fixed_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_fixed_dffe_4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_fixed_dffe_4 <= x_fixed_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN xf_pre_2_dffe10 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN xf_pre_2_dffe10 <= xf_pre_2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN xf_pre_dffe9 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN xf_pre_dffe9 <= xf_pre_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN xi_exp_value_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN xi_exp_value_dffe4 <= xi_exp_value_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN xi_ln2_prod_dffe7 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN xi_ln2_prod_dffe7 <= xi_ln2_prod_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN xi_prod_dffe3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN xi_prod_dffe3 <= xi_prod_wi;
END IF;
END IF;
END PROCESS;
wire_exp_minus_bias_dataa <= ( "0" & exp_w);
wire_exp_minus_bias_datab <= ( "0" & exp_bias);
exp_minus_bias : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => wire_exp_minus_bias_dataa,
datab => wire_exp_minus_bias_datab,
result => wire_exp_minus_bias_result
);
wire_exp_value_add_bias_w_lg_w_result_range445w446w(0) <= NOT wire_exp_value_add_bias_w_result_range445w(0);
wire_exp_value_add_bias_dataa <= ( "0" & exp_value_b4_bias_dffe_10);
wire_exp_value_add_bias_datab <= ( "0" & exp_bias(7 DOWNTO 1) & wire_extra_ln2_dffe_5_w_lg_q157w);
wire_exp_value_add_bias_w_result_range445w(0) <= wire_exp_value_add_bias_result(8);
exp_value_add_bias : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
cin => wire_cin_to_bias_dataout,
clken => clk_en,
clock => clock,
dataa => wire_exp_value_add_bias_dataa,
datab => wire_exp_value_add_bias_datab,
result => wire_exp_value_add_bias_result
);
wire_exp_value_man_over_w_lg_w_lg_w_result_range435w436w437w(0) <= wire_exp_value_man_over_w_lg_w_result_range435w436w(0) AND wire_sign_dffe_w_lg_q434w(0);
wire_exp_value_man_over_w_lg_w_result_range435w436w(0) <= NOT wire_exp_value_man_over_w_result_range435w(0);
wire_exp_value_man_over_w_lg_w_lg_w_lg_w_result_range435w436w437w438w(0) <= wire_exp_value_man_over_w_lg_w_lg_w_result_range435w436w437w(0) OR sign_dffe15;
wire_exp_value_man_over_datab <= ( "00000000" & man_overflow_wo);
wire_exp_value_man_over_w_result_range435w(0) <= wire_exp_value_man_over_result(8);
exp_value_man_over : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => wire_exp_value_add_bias_result,
datab => wire_exp_value_man_over_datab,
result => wire_exp_value_man_over_result
);
wire_invert_exp_value_dataa <= (OTHERS => '0');
wire_invert_exp_value_w_result_range130w <= wire_invert_exp_value_result(5 DOWNTO 0);
invert_exp_value : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 8
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_invert_exp_value_dataa,
datab => exp_value(7 DOWNTO 0),
result => wire_invert_exp_value_result
);
wire_man_round_datab <= ( "0000000000000000000000" & round_up_wo);
man_round : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 23
)
PORT MAP (
dataa => man_round_wo,
datab => wire_man_round_datab,
result => wire_man_round_result
);
wire_one_minus_xf_dataa <= ( "1" & "000000000000000000000000000000");
one_minus_xf : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 31
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_one_minus_xf_dataa,
datab => wire_extra_ln2_muxa_dataout,
result => wire_one_minus_xf_result
);
wire_x_fixed_minus_xiln2_datab <= ( "0" & xi_ln2_prod_wo(45 DOWNTO 9));
x_fixed_minus_xiln2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 38
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => x_fixed_dffe_4,
datab => wire_x_fixed_minus_xiln2_datab,
result => wire_x_fixed_minus_xiln2_result
);
wire_xf_minus_ln2_datab <= ( "00" & ln2_w(37 DOWNTO 9));
xf_minus_ln2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 31
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => xf_pre(30 DOWNTO 0),
datab => wire_xf_minus_ln2_datab,
result => wire_xf_minus_ln2_result
);
wire_xi_add_one_datab <= "00000001";
xi_add_one : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 8
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => xi_exp_value,
datab => wire_xi_add_one_datab,
result => wire_xi_add_one_result
);
rbarrel_shift : lpm_clshift
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_SHIFTTYPE => "LOGICAL",
LPM_WIDTH => 38,
LPM_WIDTHDIST => 6
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
data => barrel_shifter_data,
direction => exp_value_wo(8),
distance => barrel_shifter_distance,
result => wire_rbarrel_shift_result
);
distance_overflow_comp : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 8
)
PORT MAP (
agb => wire_distance_overflow_comp_agb,
dataa => wire_exp_value_to_compare_muxa_dataout,
datab => distance_overflow_val_w
);
tbl1_compare : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 5
)
PORT MAP (
ageb => wire_tbl1_compare_ageb,
dataa => xf(28 DOWNTO 24),
datab => addr_val_more_than_one
);
underflow_compare : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 8
)
PORT MAP (
agb => wire_underflow_compare_agb,
dataa => wire_exp_value_to_compare_muxa_dataout,
datab => underflow_compare_val_w
);
man_prod : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 31,
LPM_WIDTHB => 31,
LPM_WIDTHP => 62,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => tbl1_tbl2_prod_wo,
datab => tbl3_taylor_prod_wo,
result => wire_man_prod_result
);
tbl1_tbl2_prod : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 32,
LPM_WIDTHB => 32,
LPM_WIDTHP => 64,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => table_one_out,
datab => table_two_out,
result => wire_tbl1_tbl2_prod_result
);
wire_tbl3_taylor_prod_datab <= ( "1" & "000000000000000" & xf(13 DOWNTO 0));
tbl3_taylor_prod : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 32,
LPM_WIDTHB => 30,
LPM_WIDTHP => 62,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => table_three_out,
datab => wire_tbl3_taylor_prod_datab,
result => wire_tbl3_taylor_prod_result
);
xi_ln2_prod : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 8,
LPM_WIDTHB => 38,
LPM_WIDTHP => 46,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_exp_value_to_ln2a_dataout,
datab => ln2_w,
result => wire_xi_ln2_prod_result
);
xi_prod : lpm_mult
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 12,
LPM_WIDTHB => 9,
LPM_WIDTHP => 21,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
dataa => x_fixed(37 DOWNTO 26),
datab => one_over_ln2_w,
result => wire_xi_prod_result
);
loop2 : FOR i IN 0 TO 31 GENERATE
loop3 : FOR j IN 0 TO 31 GENERATE
wire_table_one_data_2d(i, j) <= table_one_data(i*32+j);
END GENERATE loop3;
END GENERATE loop2;
table_one : lpm_mux
GENERIC MAP (
LPM_SIZE => 32,
LPM_WIDTH => 32,
LPM_WIDTHS => 5
)
PORT MAP (
data => wire_table_one_data_2d,
result => wire_table_one_result,
sel => xf(28 DOWNTO 24)
);
loop4 : FOR i IN 0 TO 31 GENERATE
loop5 : FOR j IN 0 TO 20 GENERATE
wire_table_three_data_2d(i, j) <= table_three_data(i*21+j);
END GENERATE loop5;
END GENERATE loop4;
table_three : lpm_mux
GENERIC MAP (
LPM_SIZE => 32,
LPM_WIDTH => 21,
LPM_WIDTHS => 5
)
PORT MAP (
data => wire_table_three_data_2d,
result => wire_table_three_result,
sel => xf(18 DOWNTO 14)
);
loop6 : FOR i IN 0 TO 31 GENERATE
loop7 : FOR j IN 0 TO 25 GENERATE
wire_table_two_data_2d(i, j) <= table_two_data(i*26+j);
END GENERATE loop7;
END GENERATE loop6;
table_two : lpm_mux
GENERIC MAP (
LPM_SIZE => 32,
LPM_WIDTH => 26,
LPM_WIDTHS => 5
)
PORT MAP (
data => wire_table_two_data_2d,
result => wire_table_two_result,
sel => xf(23 DOWNTO 19)
);
wire_cin_to_bias_dataout <= shifted_value;
wire_exp_result_mux_prea_dataout <= exp_one WHEN wire_w_lg_w551w552w(0) = '1' ELSE exp_result_w;
loop8 : FOR i IN 0 TO 7 GENERATE
wire_exp_result_mux_prea_w_lg_dataout557w(i) <= wire_exp_result_mux_prea_dataout(i) AND wire_w_lg_w_lg_w_lg_underflow_w554w555w556w(0);
END GENERATE loop8;
wire_exp_value_b4_biasa_dataout <= exp_invert WHEN sign_dffe3 = '1' ELSE xi_exp_value;
wire_exp_value_selecta_dataout <= wire_invert_exp_value_result(5 DOWNTO 0) WHEN exp_value_wo(8) = '1' ELSE exp_value_wo(5 DOWNTO 0);
wire_exp_value_to_compare_muxa_dataout <= wire_invert_exp_value_result WHEN exp_value_wo(8) = '1' ELSE exp_value_wo(7 DOWNTO 0);
wire_exp_value_to_ln2a_dataout <= wire_xi_add_one_result WHEN sign_dffe4 = '1' ELSE xi_exp_value_wo;
wire_extra_ln2_muxa_dataout <= wire_xf_minus_ln2_result WHEN extra_ln2_dffe_0 = '1' ELSE xf_pre_wo(30 DOWNTO 0);
wire_man_result_muxa_dataout <= ( nan_w & "0000000000000000000000") WHEN wire_w_lg_w_lg_w_lg_w_lg_overflow_w536w537w538w539w(0) = '1' ELSE wire_man_round_result;
wire_xf_muxa_dataout <= wire_one_minus_xf_result WHEN sign_dffe10 = '1' ELSE xf_pre_2_wo(30 DOWNTO 0);
END RTL; --fp_exp_altfp_exp_fkd
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_exp IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp;
ARCHITECTURE RTL OF fp_exp IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT fp_exp_altfp_exp_fkd
PORT (
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
fp_exp_altfp_exp_fkd_component : fp_exp_altfp_exp_fkd
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => data,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_exp"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "17"
-- Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.bsf FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp_inst.vhd FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.inc FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_exp.cmp TRUE TRUE
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: TWI_SlaveCtl.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module is a two-wire (I2C compatible) slave controller responding
-- to the address defined in SLAVE_ADDRESS. It samples the bus and
-- deserializes data. The module needs to be controlled in turn by a
-- high-level controller.
-- Status signals:
-- DONE_O active-high pulsed when the slave is addressed by a master,
-- or when a data byte is either sent or received
-- END_O active-high pulsed when the master ended the transfer
-- RD_WRN_O high when transfer is read, low when write
-- Control signals:
-- STB_I needs to be held high when the current byte needs to be
-- acknowledged; this is the case for the device address, as
-- well as every byte written to-slave
-- D_I data needs to be provided on this bus when read transaction
-- occurs; needs to be held until DONE_O
-- D_O data will appear on D_O when a write transaction occurs;
-- valid on DONE_O
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity TWI_SlaveCtl is
generic (
SLAVE_ADDRESS : std_logic_vector(7 downto 0) := x"A0"; -- TWI Slave address
kSampleClkFreqInMHz : natural := 100
);
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
D_O : out STD_LOGIC_VECTOR (7 downto 0);
RD_WRN_O : out STD_LOGIC;
END_O : out STD_LOGIC;
DONE_O : out STD_LOGIC;
STB_I : in STD_LOGIC;
SampleClk : in STD_LOGIC;
SRST : in STD_LOGIC;
--two-wire bus
SDA_I : in STD_LOGIC;
SDA_O : out STD_LOGIC;
SDA_T : out STD_LOGIC;
SCL_I : in STD_LOGIC;
SCL_O : out STD_LOGIC;
SCL_T : out STD_LOGIC
);
end TWI_SlaveCtl;
architecture Behavioral of TWI_SlaveCtl is
constant kGlitchDurationInNs : natural := 50; --tSP in I2C specs
constant kNoOfPeriodsToFilter : natural := natural(ceil(real(kGlitchDurationInNs * kSampleClkFreqInMHz) / 1000.0));
attribute fsm_encoding: string;
type state_type is (stIdle, stAddress, stRead, stWrite, stSAck, stMAck, stTurnAround);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal dSda, ddSda, dScl, ddScl : std_logic;
signal fStart, fStop, fSCLFalling, fSCLRising : std_logic;
signal dataByte : std_logic_vector(7 downto 0); --shift register and parallel load
signal iEnd, iDone, latchData, dataBitOut, shiftBitIn, shiftBitOut : std_logic;
signal rd_wrn, drive : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal sSda, sScl, sSdaFtr, sSclFtr : std_logic;
begin
-- Synchronize SDA and SCL inputs
SyncSDA: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SDA_I,
OutClk => SampleClk,
oOut => sSda);
SyncSCL: entity work.SyncAsync
generic map (
kResetTo => '1',
kStages => 2)
port map (
aReset => '0',
aIn => SCL_I,
OutClk => SampleClk,
oOut => sScl);
-- Glitch filter as required by I2C Fast-mode specs
GlitchF_SDA: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sSda,
sOut => sSdaFtr,
sRst => SRST);
GlitchF_SCL: entity work.GlitchFilter
Generic map (kNoOfPeriodsToFilter)
Port map (
SampleClk => SampleClk,
sIn => sScl,
sOut => sSclFtr,
sRst => SRST);
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
EdgeDetect: process(SampleClk)
begin
if Rising_Edge(SampleClk) then
dSda <= sSdaFtr;
ddSda <= dSda;
dScl <= sSclFtr;
ddScl <= dScl;
end if;
end process;
fStart <= dSCL and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dSCL and dSda and not ddSda; --if SCL high while SDA rising, stop condition
fSCLFalling <= ddSCL and not dScl; -- SCL falling
fSCLRising <= not ddSCL and dScl; -- SCL rising
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA_T <= '1' when dataBitOut = '1' or drive = '0' else -- high-Z
'0'; --drive
SDA_O <= '0';
SCL_T <= '1'; -- input 4eva
SCL_O <= '0';
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if ((latchData = '1' and fSCLFalling = '1') or state = stIdle or fStart = '1') then
dataByte <= D_I; --latch data
bitCount <= 7;
elsif (shiftBitOut = '1' and fSCLFalling = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
elsif (shiftBitIn = '1' and fSCLRising = '1') then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
dataBitOut <= '0' when state = stSAck else
dataByte(dataByte'high);
D_O <= dataByte;
RD_WRN_O <= rd_wrn;
RDWRN_BIT_REG: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (state = stAddress and bitCount = 0 and fSCLRising = '1') then
rd_wrn <= dSDA;
end if;
end if;
end process;
SYNC_PROC: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
state <= nstate;
END_O <= iEnd;
DONE_O <= iDone;
end if;
end process;
OUTPUT_DECODE: process (nstate, state, fSCLRising, fSCLFalling, ddSDA, bitCount, rd_wrn, dataByte, fStop, fStart)
begin
iDone <= '0';
iEnd <= '0';
shiftBitIn <= '0';
shiftBitOut <= '0';
latchData <= '0';
drive <= '0';
if (state = stRead or state = stSAck) then
drive <= '1';
end if;
if (state = stAddress or state = stWrite) then
shiftBitIn <= '1';
end if;
if (state = stRead) then
shiftBitOut <= '1';
end if;
if ((state = stSAck and rd_wrn = '1') or
(state = stMAck and ddSda = '0')) then --get the data byte for the next read
latchData <= '1';
end if;
if ((state = stAddress and bitCount = 0 and fSCLRising = '1' and dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) or
(state = stWrite and bitCount = 0 and fSCLRising = '1') or
(state = stRead and bitCount = 0 and fSCLFalling = '1')) then
iDone <= '1';
end if;
if (fStop = '1' or fStart = '1' or
(state = stMAck and fSCLRising = '1' and ddSDA = '1')) then
iEnd <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, fStart, STB_I, fSCLRising, fSCLFalling, bitCount, ddSDA, rd_wrn, dataByte, fStop)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (fStart = '1') then -- start condition received
nstate <= stAddress;
end if;
when stAddress =>
if (fStop = '1') then
nstate <= stIdle;
elsif (bitCount = 0 and fSCLRising = '1') then
if (dataByte(6 downto 0) = SLAVE_ADDRESS(7 downto 1)) then
nstate <= stTurnAround;
else
nstate <= stIdle;
end if;
end if;
when stTurnAround =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (STB_I = '1') then
nstate <= stSAck; --we acknowledge and continue
else
nstate <= stIdle; --don't ack and stop
end if;
end if;
when stSAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif fSCLFalling = '1' then
if (rd_wrn = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLRising = '1') then
nstate <= stTurnAround;
end if;
when stMAck =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (fSCLFalling = '1') then
if (ddSDA = '1') then
nstate <= stIdle;
else
nstate <= stRead;
end if;
end if;
when stRead =>
if (fStop = '1') then
nstate <= stIdle;
elsif (fStart = '1') then
nstate <= stAddress;
elsif (bitCount = 0 and fSCLFalling = '1') then
nstate <= stMAck;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
end Behavioral;
|
library ieee;
library ieee, lib2, lib3;
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
clk : in std_logic;
enable : in std_logic;
i : in std_logic;
o : out std_logic
);
end;
architecture a of ent is
begin
process(clk)
begin
-- works:
--if rising_edge(clk) and enable = '1' then
if enable = '1' and rising_edge(clk) then
o <= i;
end if;
end process;
end;
|
architecture RTL of FIFO is
attribute max_delay : time;
-- Violations below
attribute max_delay : time;
attribute max_delay : time;
begin
end architecture RTL;
|
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been added to the file as a new module
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DP";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
port (
RDCLOCK : in std_logic := '0';
RDCLKEN : in std_logic := '1';
RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
RDEN : in std_logic := '1';
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
WREN : in std_logic;
WRCLOCK : in std_logic := '0';
WRCLKEN : in std_logic := '1';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"0000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
-- For Xilinx Virtex-5
component RAM32X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"00000000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
DPRA4 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component cache
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset : in std_logic;
address_next : in std_logic_vector(31 downto 2);
byte_we_next : in std_logic_vector(3 downto 0);
cpu_address : in std_logic_vector(31 downto 2);
mem_busy : in std_logic;
cache_access : out std_logic; --access 4KB cache
cache_checking : out std_logic; --checking if cache hit
cache_miss : out std_logic); --cache miss
end component; --cache
component ram
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component NI
generic(current_address : integer := 10; -- the current node's address
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the memory mapped I/O
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"); -- reserved address for the counter
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
--NI_read_flag : out std_logic;
--NI_write_flag : out std_logic;
irq_out : out std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end component; --network interface
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 10;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
end; --package mlite_pack
package body mlite_pack is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable carry_in : std_logic;
variable bb : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length downto 0);
begin
if do_add = '1' then
bb := b;
carry_in := '0';
else
bb := not b;
carry_in := '1';
end if;
for index in 0 to a'length-1 loop
result(index) := a(index) xor bb(index) xor carry_in;
carry_in := (carry_in and (a(index) or bb(index))) or
(a(index) and bb(index));
end loop;
result(a'length) := carry_in xnor do_add;
return result;
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
|
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been added to the file as a new module
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DP";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
port (
RDCLOCK : in std_logic := '0';
RDCLKEN : in std_logic := '1';
RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
RDEN : in std_logic := '1';
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
WREN : in std_logic;
WRCLOCK : in std_logic := '0';
WRCLKEN : in std_logic := '1';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"0000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
-- For Xilinx Virtex-5
component RAM32X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"00000000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
DPRA4 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component cache
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset : in std_logic;
address_next : in std_logic_vector(31 downto 2);
byte_we_next : in std_logic_vector(3 downto 0);
cpu_address : in std_logic_vector(31 downto 2);
mem_busy : in std_logic;
cache_access : out std_logic; --access 4KB cache
cache_checking : out std_logic; --checking if cache hit
cache_miss : out std_logic); --cache miss
end component; --cache
component ram
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component NI
generic(current_address : integer := 10; -- the current node's address
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the memory mapped I/O
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"); -- reserved address for the counter
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
--NI_read_flag : out std_logic;
--NI_write_flag : out std_logic;
irq_out : out std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end component; --network interface
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 10;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
end; --package mlite_pack
package body mlite_pack is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable carry_in : std_logic;
variable bb : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length downto 0);
begin
if do_add = '1' then
bb := b;
carry_in := '0';
else
bb := not b;
carry_in := '1';
end if;
for index in 0 to a'length-1 loop
result(index) := a(index) xor bb(index) xor carry_in;
carry_in := (carry_in and (a(index) or bb(index))) or
(a(index) and bb(index));
end loop;
result(a'length) := carry_in xnor do_add;
return result;
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
|
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been added to the file as a new module
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DP";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
port (
RDCLOCK : in std_logic := '0';
RDCLKEN : in std_logic := '1';
RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
RDEN : in std_logic := '1';
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
WREN : in std_logic;
WRCLOCK : in std_logic := '0';
WRCLKEN : in std_logic := '1';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"0000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
-- For Xilinx Virtex-5
component RAM32X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"00000000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
DPRA4 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component cache
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset : in std_logic;
address_next : in std_logic_vector(31 downto 2);
byte_we_next : in std_logic_vector(3 downto 0);
cpu_address : in std_logic_vector(31 downto 2);
mem_busy : in std_logic;
cache_access : out std_logic; --access 4KB cache
cache_checking : out std_logic; --checking if cache hit
cache_miss : out std_logic); --cache miss
end component; --cache
component ram
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component NI
generic(current_address : integer := 10; -- the current node's address
reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000"; -- reserved address for the memory mapped I/O
counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001"); -- reserved address for the counter
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
--NI_read_flag : out std_logic;
--NI_write_flag : out std_logic;
irq_out : out std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end component; --network interface
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 10;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
end; --package mlite_pack
package body mlite_pack is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable carry_in : std_logic;
variable bb : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length downto 0);
begin
if do_add = '1' then
bb := b;
carry_in := '0';
else
bb := not b;
carry_in := '1';
end if;
for index in 0 to a'length-1 loop
result(index) := a(index) xor bb(index) xor carry_in;
carry_in := (carry_in and (a(index) or bb(index))) or
(a(index) and bb(index));
end loop;
result(a'length) := carry_in xnor do_add;
return result;
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
|
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Primitive library for post synthesis simulation --
-- These models are not intended for efficient synthesis --
-- --
-----------------------------------------------------------------------------
--pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
entity prim_counter is
generic (w : integer := 8);
port (
q : buffer std_logic_vector(w - 1 downto 0);
cout : out std_logic;
d : in std_logic_vector(w - 1 downto 0);
cin : in std_logic;
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
en : in std_logic;
updn : in std_logic
);
end prim_counter;
architecture beh of prim_counter is
signal nextq : std_logic_vector(w - 1 downto 0);
begin
nxt: process (q, cin, updn)
variable i : integer;
variable nextc, c : std_logic;
begin
nextc := cin;
for i in 0 to w - 1 loop
c := nextc;
nextq(i) <= c xor (not updn) xor q(i);
nextc := (c and (not updn)) or
(c and q(i)) or
((not updn) and q(i));
end loop;
cout <= nextc;
end process;
ff : process (clk, rst)
begin
if rst = '1' then
q <= (others => '0');
elsif rising_edge(clk) then
q <= nextq;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity prim_dff is
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_dff;
architecture beh of prim_dff is
begin
ff : process (clk, r, s)
begin
if r = '1' then
q <= '0';
elsif s = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
entity prim_sdff is
port (q : out std_logic;
d : in std_logic;
c : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_sdff;
architecture beh of prim_sdff is
begin
ff : process(c)
begin
if rising_edge(c) then
if r = '1' then
q <= '0';
elsif s = '1' then
q <= '1';
else
q <= d;
end if;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity prim_latch is
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_latch;
architecture beh of prim_latch is
begin
q <= '0' when r = '1' else
'1' when s = '1' else
d when clk = '1';
end beh;
----------------------------------------------------------------------------
-- Zero ohm resistors: Hardi's solution to connect two inout ports.
----------------------------------------------------------------------------
-- Copyright (c) 1995, Ben Cohen. All rights reserved.
-- This model can be used in conjunction with the Kluwer Academic book
-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
-- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic
-- which discusses guidelines and testbench design issues.
--
-- This source file for the ZERO Ohm resistor model may be used and
-- distributed without restriction provided that this copyright
-- statement is not removed from the file and that any derivative work
-- contains this copyright notice.
-- File name : Zohm_ea.vhd
-- Description: This package, entity, and architecture provide
-- the definition of a zero ohm component (A, B).
--
-- The applications of this component include:
-- . Normal operation of a jumper wire (data flowing in both directions)
--
-- The component consists of 2 ports:
-- . Port A: One side of the pass-through switch
-- . Port B: The other side of the pass-through switch
-- The model is sensitive to transactions on all ports. Once a
-- transaction is detected, all other transactions are ignored
-- for that simulation time (i.e. further transactions in that
-- delta time are ignored).
--
-- The width of the pass-through switch is defined through the
-- generic "width_g". The pass-through control and operation
-- is defined on a per bit basis (i.e. one process per bit).
--
-- Model Limitations and Restrictions:
-- Signals asserted on the ports of the error injector should not have
-- transactions occuring in multiple delta times because the model
-- is sensitive to transactions on port A, B ONLY ONCE during
-- a simulation time. Thus, once fired, a process will
-- not refire if there are multiple transactions occuring in delta times.
-- This condition may occur in gate level simulations with
-- ZERO delays because transactions may occur in multiple delta times.
--
--
-- Acknowledgement: The author thanks Steve Schoessow and Johan Sandstrom
-- for their contributions and discussions in the enhancement and
-- verification of this model.
--
--=================================================================
-- Revisions:
-- Date Author Revision Comment
-- 07-13-95 Ben Cohen Rev A Creation
-- [email protected]
-------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
entity ZeroOhm1 is
port
(A : inout Std_Logic;
B : inout Std_Logic
);
end ZeroOhm1;
architecture ZeroOhm1_a of ZeroOhm1 is
-- attribute syn_black_box : boolean;
-- attribute syn_feedthrough : boolean;
-- attribute syn_black_box of all : architecture is true;
-- attribute syn_feedthrough of all : architecture is true;
begin
ABC0_Lbl: process
variable ThenTime_v : time;
begin
wait on A'transaction, B'transaction
until ThenTime_v /= now;
-- Break
ThenTime_v := now;
A <= 'Z';
B <= 'Z';
wait for 0 ns;
-- Make
A <= B;
B <= A;
end process ABC0_Lbl;
end ZeroOhm1_a;
-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity prim_ramd is
generic (
data_width : integer := 4;
addr_width : integer := 5);
port (
dout : out std_logic_vector(data_width-1 downto 0);
aout : in std_logic_vector(addr_width-1 downto 0);
din : in std_logic_vector(data_width-1 downto 0);
ain : in std_logic_vector(addr_width-1 downto 0);
we : in std_logic;
clk : in std_logic);
end prim_ramd;
architecture beh of prim_ramd is
constant depth : integer := 2** addr_width;
type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
signal mem: mem_type;
begin
dout <= mem(conv_integer(aout));
process (clk)
begin
if rising_edge(clk) then
if (we = '1') then
mem(conv_integer(ain)) <= din;
end if;
end if;
end process;
end beh ;
library ieee;
use ieee.std_logic_1164.all;
package components is
component prim_counter
generic (w : integer);
port (
q : buffer std_logic_vector(w - 1 downto 0);
cout : out std_logic;
d : in std_logic_vector(w - 1 downto 0);
cin : in std_logic;
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
en : in std_logic;
updn : in std_logic
);
end component;
component prim_dff
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_sdff
port(q : out std_logic;
d : in std_logic;
c : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_latch
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_ramd is
generic (
data_width : integer := 4;
addr_width : integer := 5);
port (
dout : out std_logic_vector(data_width-1 downto 0);
aout : in std_logic_vector(addr_width-1 downto 0);
din : in std_logic_vector(data_width-1 downto 0);
ain : in std_logic_vector(addr_width-1 downto 0);
we : in std_logic;
clk : in std_logic);
end component;
end components;
-- pragma translate_on
|
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Primitive library for post synthesis simulation --
-- These models are not intended for efficient synthesis --
-- --
-----------------------------------------------------------------------------
--pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
entity prim_counter is
generic (w : integer := 8);
port (
q : buffer std_logic_vector(w - 1 downto 0);
cout : out std_logic;
d : in std_logic_vector(w - 1 downto 0);
cin : in std_logic;
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
en : in std_logic;
updn : in std_logic
);
end prim_counter;
architecture beh of prim_counter is
signal nextq : std_logic_vector(w - 1 downto 0);
begin
nxt: process (q, cin, updn)
variable i : integer;
variable nextc, c : std_logic;
begin
nextc := cin;
for i in 0 to w - 1 loop
c := nextc;
nextq(i) <= c xor (not updn) xor q(i);
nextc := (c and (not updn)) or
(c and q(i)) or
((not updn) and q(i));
end loop;
cout <= nextc;
end process;
ff : process (clk, rst)
begin
if rst = '1' then
q <= (others => '0');
elsif rising_edge(clk) then
q <= nextq;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity prim_dff is
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_dff;
architecture beh of prim_dff is
begin
ff : process (clk, r, s)
begin
if r = '1' then
q <= '0';
elsif s = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
entity prim_sdff is
port (q : out std_logic;
d : in std_logic;
c : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_sdff;
architecture beh of prim_sdff is
begin
ff : process(c)
begin
if rising_edge(c) then
if r = '1' then
q <= '0';
elsif s = '1' then
q <= '1';
else
q <= d;
end if;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity prim_latch is
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_latch;
architecture beh of prim_latch is
begin
q <= '0' when r = '1' else
'1' when s = '1' else
d when clk = '1';
end beh;
----------------------------------------------------------------------------
-- Zero ohm resistors: Hardi's solution to connect two inout ports.
----------------------------------------------------------------------------
-- Copyright (c) 1995, Ben Cohen. All rights reserved.
-- This model can be used in conjunction with the Kluwer Academic book
-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
-- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic
-- which discusses guidelines and testbench design issues.
--
-- This source file for the ZERO Ohm resistor model may be used and
-- distributed without restriction provided that this copyright
-- statement is not removed from the file and that any derivative work
-- contains this copyright notice.
-- File name : Zohm_ea.vhd
-- Description: This package, entity, and architecture provide
-- the definition of a zero ohm component (A, B).
--
-- The applications of this component include:
-- . Normal operation of a jumper wire (data flowing in both directions)
--
-- The component consists of 2 ports:
-- . Port A: One side of the pass-through switch
-- . Port B: The other side of the pass-through switch
-- The model is sensitive to transactions on all ports. Once a
-- transaction is detected, all other transactions are ignored
-- for that simulation time (i.e. further transactions in that
-- delta time are ignored).
--
-- The width of the pass-through switch is defined through the
-- generic "width_g". The pass-through control and operation
-- is defined on a per bit basis (i.e. one process per bit).
--
-- Model Limitations and Restrictions:
-- Signals asserted on the ports of the error injector should not have
-- transactions occuring in multiple delta times because the model
-- is sensitive to transactions on port A, B ONLY ONCE during
-- a simulation time. Thus, once fired, a process will
-- not refire if there are multiple transactions occuring in delta times.
-- This condition may occur in gate level simulations with
-- ZERO delays because transactions may occur in multiple delta times.
--
--
-- Acknowledgement: The author thanks Steve Schoessow and Johan Sandstrom
-- for their contributions and discussions in the enhancement and
-- verification of this model.
--
--=================================================================
-- Revisions:
-- Date Author Revision Comment
-- 07-13-95 Ben Cohen Rev A Creation
-- [email protected]
-------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
entity ZeroOhm1 is
port
(A : inout Std_Logic;
B : inout Std_Logic
);
end ZeroOhm1;
architecture ZeroOhm1_a of ZeroOhm1 is
-- attribute syn_black_box : boolean;
-- attribute syn_feedthrough : boolean;
-- attribute syn_black_box of all : architecture is true;
-- attribute syn_feedthrough of all : architecture is true;
begin
ABC0_Lbl: process
variable ThenTime_v : time;
begin
wait on A'transaction, B'transaction
until ThenTime_v /= now;
-- Break
ThenTime_v := now;
A <= 'Z';
B <= 'Z';
wait for 0 ns;
-- Make
A <= B;
B <= A;
end process ABC0_Lbl;
end ZeroOhm1_a;
-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity prim_ramd is
generic (
data_width : integer := 4;
addr_width : integer := 5);
port (
dout : out std_logic_vector(data_width-1 downto 0);
aout : in std_logic_vector(addr_width-1 downto 0);
din : in std_logic_vector(data_width-1 downto 0);
ain : in std_logic_vector(addr_width-1 downto 0);
we : in std_logic;
clk : in std_logic);
end prim_ramd;
architecture beh of prim_ramd is
constant depth : integer := 2** addr_width;
type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
signal mem: mem_type;
begin
dout <= mem(conv_integer(aout));
process (clk)
begin
if rising_edge(clk) then
if (we = '1') then
mem(conv_integer(ain)) <= din;
end if;
end if;
end process;
end beh ;
library ieee;
use ieee.std_logic_1164.all;
package components is
component prim_counter
generic (w : integer);
port (
q : buffer std_logic_vector(w - 1 downto 0);
cout : out std_logic;
d : in std_logic_vector(w - 1 downto 0);
cin : in std_logic;
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
en : in std_logic;
updn : in std_logic
);
end component;
component prim_dff
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_sdff
port(q : out std_logic;
d : in std_logic;
c : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_latch
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_ramd is
generic (
data_width : integer := 4;
addr_width : integer := 5);
port (
dout : out std_logic_vector(data_width-1 downto 0);
aout : in std_logic_vector(addr_width-1 downto 0);
din : in std_logic_vector(data_width-1 downto 0);
ain : in std_logic_vector(addr_width-1 downto 0);
we : in std_logic;
clk : in std_logic);
end component;
end components;
-- pragma translate_on
|
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Primitive library for post synthesis simulation --
-- These models are not intended for efficient synthesis --
-- --
-----------------------------------------------------------------------------
--pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
entity prim_counter is
generic (w : integer := 8);
port (
q : buffer std_logic_vector(w - 1 downto 0);
cout : out std_logic;
d : in std_logic_vector(w - 1 downto 0);
cin : in std_logic;
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
en : in std_logic;
updn : in std_logic
);
end prim_counter;
architecture beh of prim_counter is
signal nextq : std_logic_vector(w - 1 downto 0);
begin
nxt: process (q, cin, updn)
variable i : integer;
variable nextc, c : std_logic;
begin
nextc := cin;
for i in 0 to w - 1 loop
c := nextc;
nextq(i) <= c xor (not updn) xor q(i);
nextc := (c and (not updn)) or
(c and q(i)) or
((not updn) and q(i));
end loop;
cout <= nextc;
end process;
ff : process (clk, rst)
begin
if rst = '1' then
q <= (others => '0');
elsif rising_edge(clk) then
q <= nextq;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity prim_dff is
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_dff;
architecture beh of prim_dff is
begin
ff : process (clk, r, s)
begin
if r = '1' then
q <= '0';
elsif s = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
entity prim_sdff is
port (q : out std_logic;
d : in std_logic;
c : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_sdff;
architecture beh of prim_sdff is
begin
ff : process(c)
begin
if rising_edge(c) then
if r = '1' then
q <= '0';
elsif s = '1' then
q <= '1';
else
q <= d;
end if;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity prim_latch is
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_latch;
architecture beh of prim_latch is
begin
q <= '0' when r = '1' else
'1' when s = '1' else
d when clk = '1';
end beh;
----------------------------------------------------------------------------
-- Zero ohm resistors: Hardi's solution to connect two inout ports.
----------------------------------------------------------------------------
-- Copyright (c) 1995, Ben Cohen. All rights reserved.
-- This model can be used in conjunction with the Kluwer Academic book
-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
-- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic
-- which discusses guidelines and testbench design issues.
--
-- This source file for the ZERO Ohm resistor model may be used and
-- distributed without restriction provided that this copyright
-- statement is not removed from the file and that any derivative work
-- contains this copyright notice.
-- File name : Zohm_ea.vhd
-- Description: This package, entity, and architecture provide
-- the definition of a zero ohm component (A, B).
--
-- The applications of this component include:
-- . Normal operation of a jumper wire (data flowing in both directions)
--
-- The component consists of 2 ports:
-- . Port A: One side of the pass-through switch
-- . Port B: The other side of the pass-through switch
-- The model is sensitive to transactions on all ports. Once a
-- transaction is detected, all other transactions are ignored
-- for that simulation time (i.e. further transactions in that
-- delta time are ignored).
--
-- The width of the pass-through switch is defined through the
-- generic "width_g". The pass-through control and operation
-- is defined on a per bit basis (i.e. one process per bit).
--
-- Model Limitations and Restrictions:
-- Signals asserted on the ports of the error injector should not have
-- transactions occuring in multiple delta times because the model
-- is sensitive to transactions on port A, B ONLY ONCE during
-- a simulation time. Thus, once fired, a process will
-- not refire if there are multiple transactions occuring in delta times.
-- This condition may occur in gate level simulations with
-- ZERO delays because transactions may occur in multiple delta times.
--
--
-- Acknowledgement: The author thanks Steve Schoessow and Johan Sandstrom
-- for their contributions and discussions in the enhancement and
-- verification of this model.
--
--=================================================================
-- Revisions:
-- Date Author Revision Comment
-- 07-13-95 Ben Cohen Rev A Creation
-- [email protected]
-------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
entity ZeroOhm1 is
port
(A : inout Std_Logic;
B : inout Std_Logic
);
end ZeroOhm1;
architecture ZeroOhm1_a of ZeroOhm1 is
-- attribute syn_black_box : boolean;
-- attribute syn_feedthrough : boolean;
-- attribute syn_black_box of all : architecture is true;
-- attribute syn_feedthrough of all : architecture is true;
begin
ABC0_Lbl: process
variable ThenTime_v : time;
begin
wait on A'transaction, B'transaction
until ThenTime_v /= now;
-- Break
ThenTime_v := now;
A <= 'Z';
B <= 'Z';
wait for 0 ns;
-- Make
A <= B;
B <= A;
end process ABC0_Lbl;
end ZeroOhm1_a;
-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity prim_ramd is
generic (
data_width : integer := 4;
addr_width : integer := 5);
port (
dout : out std_logic_vector(data_width-1 downto 0);
aout : in std_logic_vector(addr_width-1 downto 0);
din : in std_logic_vector(data_width-1 downto 0);
ain : in std_logic_vector(addr_width-1 downto 0);
we : in std_logic;
clk : in std_logic);
end prim_ramd;
architecture beh of prim_ramd is
constant depth : integer := 2** addr_width;
type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
signal mem: mem_type;
begin
dout <= mem(conv_integer(aout));
process (clk)
begin
if rising_edge(clk) then
if (we = '1') then
mem(conv_integer(ain)) <= din;
end if;
end if;
end process;
end beh ;
library ieee;
use ieee.std_logic_1164.all;
package components is
component prim_counter
generic (w : integer);
port (
q : buffer std_logic_vector(w - 1 downto 0);
cout : out std_logic;
d : in std_logic_vector(w - 1 downto 0);
cin : in std_logic;
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
en : in std_logic;
updn : in std_logic
);
end component;
component prim_dff
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_sdff
port(q : out std_logic;
d : in std_logic;
c : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_latch
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_ramd is
generic (
data_width : integer := 4;
addr_width : integer := 5);
port (
dout : out std_logic_vector(data_width-1 downto 0);
aout : in std_logic_vector(addr_width-1 downto 0);
din : in std_logic_vector(data_width-1 downto 0);
ain : in std_logic_vector(addr_width-1 downto 0);
we : in std_logic;
clk : in std_logic);
end component;
end components;
-- pragma translate_on
|
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Primitive library for post synthesis simulation --
-- These models are not intended for efficient synthesis --
-- --
-----------------------------------------------------------------------------
--pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
entity prim_counter is
generic (w : integer := 8);
port (
q : buffer std_logic_vector(w - 1 downto 0);
cout : out std_logic;
d : in std_logic_vector(w - 1 downto 0);
cin : in std_logic;
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
en : in std_logic;
updn : in std_logic
);
end prim_counter;
architecture beh of prim_counter is
signal nextq : std_logic_vector(w - 1 downto 0);
begin
nxt: process (q, cin, updn)
variable i : integer;
variable nextc, c : std_logic;
begin
nextc := cin;
for i in 0 to w - 1 loop
c := nextc;
nextq(i) <= c xor (not updn) xor q(i);
nextc := (c and (not updn)) or
(c and q(i)) or
((not updn) and q(i));
end loop;
cout <= nextc;
end process;
ff : process (clk, rst)
begin
if rst = '1' then
q <= (others => '0');
elsif rising_edge(clk) then
q <= nextq;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity prim_dff is
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_dff;
architecture beh of prim_dff is
begin
ff : process (clk, r, s)
begin
if r = '1' then
q <= '0';
elsif s = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
entity prim_sdff is
port (q : out std_logic;
d : in std_logic;
c : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_sdff;
architecture beh of prim_sdff is
begin
ff : process(c)
begin
if rising_edge(c) then
if r = '1' then
q <= '0';
elsif s = '1' then
q <= '1';
else
q <= d;
end if;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity prim_latch is
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_latch;
architecture beh of prim_latch is
begin
q <= '0' when r = '1' else
'1' when s = '1' else
d when clk = '1';
end beh;
----------------------------------------------------------------------------
-- Zero ohm resistors: Hardi's solution to connect two inout ports.
----------------------------------------------------------------------------
-- Copyright (c) 1995, Ben Cohen. All rights reserved.
-- This model can be used in conjunction with the Kluwer Academic book
-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
-- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic
-- which discusses guidelines and testbench design issues.
--
-- This source file for the ZERO Ohm resistor model may be used and
-- distributed without restriction provided that this copyright
-- statement is not removed from the file and that any derivative work
-- contains this copyright notice.
-- File name : Zohm_ea.vhd
-- Description: This package, entity, and architecture provide
-- the definition of a zero ohm component (A, B).
--
-- The applications of this component include:
-- . Normal operation of a jumper wire (data flowing in both directions)
--
-- The component consists of 2 ports:
-- . Port A: One side of the pass-through switch
-- . Port B: The other side of the pass-through switch
-- The model is sensitive to transactions on all ports. Once a
-- transaction is detected, all other transactions are ignored
-- for that simulation time (i.e. further transactions in that
-- delta time are ignored).
--
-- The width of the pass-through switch is defined through the
-- generic "width_g". The pass-through control and operation
-- is defined on a per bit basis (i.e. one process per bit).
--
-- Model Limitations and Restrictions:
-- Signals asserted on the ports of the error injector should not have
-- transactions occuring in multiple delta times because the model
-- is sensitive to transactions on port A, B ONLY ONCE during
-- a simulation time. Thus, once fired, a process will
-- not refire if there are multiple transactions occuring in delta times.
-- This condition may occur in gate level simulations with
-- ZERO delays because transactions may occur in multiple delta times.
--
--
-- Acknowledgement: The author thanks Steve Schoessow and Johan Sandstrom
-- for their contributions and discussions in the enhancement and
-- verification of this model.
--
--=================================================================
-- Revisions:
-- Date Author Revision Comment
-- 07-13-95 Ben Cohen Rev A Creation
-- [email protected]
-------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
entity ZeroOhm1 is
port
(A : inout Std_Logic;
B : inout Std_Logic
);
end ZeroOhm1;
architecture ZeroOhm1_a of ZeroOhm1 is
-- attribute syn_black_box : boolean;
-- attribute syn_feedthrough : boolean;
-- attribute syn_black_box of all : architecture is true;
-- attribute syn_feedthrough of all : architecture is true;
begin
ABC0_Lbl: process
variable ThenTime_v : time;
begin
wait on A'transaction, B'transaction
until ThenTime_v /= now;
-- Break
ThenTime_v := now;
A <= 'Z';
B <= 'Z';
wait for 0 ns;
-- Make
A <= B;
B <= A;
end process ABC0_Lbl;
end ZeroOhm1_a;
-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity prim_ramd is
generic (
data_width : integer := 4;
addr_width : integer := 5);
port (
dout : out std_logic_vector(data_width-1 downto 0);
aout : in std_logic_vector(addr_width-1 downto 0);
din : in std_logic_vector(data_width-1 downto 0);
ain : in std_logic_vector(addr_width-1 downto 0);
we : in std_logic;
clk : in std_logic);
end prim_ramd;
architecture beh of prim_ramd is
constant depth : integer := 2** addr_width;
type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
signal mem: mem_type;
begin
dout <= mem(conv_integer(aout));
process (clk)
begin
if rising_edge(clk) then
if (we = '1') then
mem(conv_integer(ain)) <= din;
end if;
end if;
end process;
end beh ;
library ieee;
use ieee.std_logic_1164.all;
package components is
component prim_counter
generic (w : integer);
port (
q : buffer std_logic_vector(w - 1 downto 0);
cout : out std_logic;
d : in std_logic_vector(w - 1 downto 0);
cin : in std_logic;
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
en : in std_logic;
updn : in std_logic
);
end component;
component prim_dff
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_sdff
port(q : out std_logic;
d : in std_logic;
c : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_latch
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_ramd is
generic (
data_width : integer := 4;
addr_width : integer := 5);
port (
dout : out std_logic_vector(data_width-1 downto 0);
aout : in std_logic_vector(addr_width-1 downto 0);
din : in std_logic_vector(data_width-1 downto 0);
ain : in std_logic_vector(addr_width-1 downto 0);
we : in std_logic;
clk : in std_logic);
end component;
end components;
-- pragma translate_on
|
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Primitive library for post synthesis simulation --
-- These models are not intended for efficient synthesis --
-- --
-----------------------------------------------------------------------------
--pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
entity prim_counter is
generic (w : integer := 8);
port (
q : buffer std_logic_vector(w - 1 downto 0);
cout : out std_logic;
d : in std_logic_vector(w - 1 downto 0);
cin : in std_logic;
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
en : in std_logic;
updn : in std_logic
);
end prim_counter;
architecture beh of prim_counter is
signal nextq : std_logic_vector(w - 1 downto 0);
begin
nxt: process (q, cin, updn)
variable i : integer;
variable nextc, c : std_logic;
begin
nextc := cin;
for i in 0 to w - 1 loop
c := nextc;
nextq(i) <= c xor (not updn) xor q(i);
nextc := (c and (not updn)) or
(c and q(i)) or
((not updn) and q(i));
end loop;
cout <= nextc;
end process;
ff : process (clk, rst)
begin
if rst = '1' then
q <= (others => '0');
elsif rising_edge(clk) then
q <= nextq;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity prim_dff is
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_dff;
architecture beh of prim_dff is
begin
ff : process (clk, r, s)
begin
if r = '1' then
q <= '0';
elsif s = '1' then
q <= '1';
elsif rising_edge(clk) then
q <= d;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
entity prim_sdff is
port (q : out std_logic;
d : in std_logic;
c : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_sdff;
architecture beh of prim_sdff is
begin
ff : process(c)
begin
if rising_edge(c) then
if r = '1' then
q <= '0';
elsif s = '1' then
q <= '1';
else
q <= d;
end if;
end if;
end process ff;
end beh;
library ieee;
use ieee.std_logic_1164.all;
entity prim_latch is
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end prim_latch;
architecture beh of prim_latch is
begin
q <= '0' when r = '1' else
'1' when s = '1' else
d when clk = '1';
end beh;
----------------------------------------------------------------------------
-- Zero ohm resistors: Hardi's solution to connect two inout ports.
----------------------------------------------------------------------------
-- Copyright (c) 1995, Ben Cohen. All rights reserved.
-- This model can be used in conjunction with the Kluwer Academic book
-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
-- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic
-- which discusses guidelines and testbench design issues.
--
-- This source file for the ZERO Ohm resistor model may be used and
-- distributed without restriction provided that this copyright
-- statement is not removed from the file and that any derivative work
-- contains this copyright notice.
-- File name : Zohm_ea.vhd
-- Description: This package, entity, and architecture provide
-- the definition of a zero ohm component (A, B).
--
-- The applications of this component include:
-- . Normal operation of a jumper wire (data flowing in both directions)
--
-- The component consists of 2 ports:
-- . Port A: One side of the pass-through switch
-- . Port B: The other side of the pass-through switch
-- The model is sensitive to transactions on all ports. Once a
-- transaction is detected, all other transactions are ignored
-- for that simulation time (i.e. further transactions in that
-- delta time are ignored).
--
-- The width of the pass-through switch is defined through the
-- generic "width_g". The pass-through control and operation
-- is defined on a per bit basis (i.e. one process per bit).
--
-- Model Limitations and Restrictions:
-- Signals asserted on the ports of the error injector should not have
-- transactions occuring in multiple delta times because the model
-- is sensitive to transactions on port A, B ONLY ONCE during
-- a simulation time. Thus, once fired, a process will
-- not refire if there are multiple transactions occuring in delta times.
-- This condition may occur in gate level simulations with
-- ZERO delays because transactions may occur in multiple delta times.
--
--
-- Acknowledgement: The author thanks Steve Schoessow and Johan Sandstrom
-- for their contributions and discussions in the enhancement and
-- verification of this model.
--
--=================================================================
-- Revisions:
-- Date Author Revision Comment
-- 07-13-95 Ben Cohen Rev A Creation
-- [email protected]
-------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
entity ZeroOhm1 is
port
(A : inout Std_Logic;
B : inout Std_Logic
);
end ZeroOhm1;
architecture ZeroOhm1_a of ZeroOhm1 is
-- attribute syn_black_box : boolean;
-- attribute syn_feedthrough : boolean;
-- attribute syn_black_box of all : architecture is true;
-- attribute syn_feedthrough of all : architecture is true;
begin
ABC0_Lbl: process
variable ThenTime_v : time;
begin
wait on A'transaction, B'transaction
until ThenTime_v /= now;
-- Break
ThenTime_v := now;
A <= 'Z';
B <= 'Z';
wait for 0 ns;
-- Make
A <= B;
B <= A;
end process ABC0_Lbl;
end ZeroOhm1_a;
-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity prim_ramd is
generic (
data_width : integer := 4;
addr_width : integer := 5);
port (
dout : out std_logic_vector(data_width-1 downto 0);
aout : in std_logic_vector(addr_width-1 downto 0);
din : in std_logic_vector(data_width-1 downto 0);
ain : in std_logic_vector(addr_width-1 downto 0);
we : in std_logic;
clk : in std_logic);
end prim_ramd;
architecture beh of prim_ramd is
constant depth : integer := 2** addr_width;
type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);
signal mem: mem_type;
begin
dout <= mem(conv_integer(aout));
process (clk)
begin
if rising_edge(clk) then
if (we = '1') then
mem(conv_integer(ain)) <= din;
end if;
end if;
end process;
end beh ;
library ieee;
use ieee.std_logic_1164.all;
package components is
component prim_counter
generic (w : integer);
port (
q : buffer std_logic_vector(w - 1 downto 0);
cout : out std_logic;
d : in std_logic_vector(w - 1 downto 0);
cin : in std_logic;
clk : in std_logic;
rst : in std_logic;
load : in std_logic;
en : in std_logic;
updn : in std_logic
);
end component;
component prim_dff
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_sdff
port(q : out std_logic;
d : in std_logic;
c : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_latch
port (q : out std_logic;
d : in std_logic;
clk : in std_logic;
r : in std_logic := '0';
s : in std_logic := '0');
end component;
component prim_ramd is
generic (
data_width : integer := 4;
addr_width : integer := 5);
port (
dout : out std_logic_vector(data_width-1 downto 0);
aout : in std_logic_vector(addr_width-1 downto 0);
din : in std_logic_vector(data_width-1 downto 0);
ain : in std_logic_vector(addr_width-1 downto 0);
we : in std_logic;
clk : in std_logic);
end component;
end components;
-- pragma translate_on
|
------------------------------------------------------------------------------
-- Controller of context select register
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/contextselctrl.vhd $
-- Authos : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003-10-17
-- $Id: contextselctrl.vhd 241 2005-04-07 08:50:55Z plessl $
------------------------------------------------------------------------------
-- arbitrates between host interface decoder and the context
-- scheduler.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ContextSelCtrl is
port (
DecEnxEI : in std_logic;
SchedEnxEI : in std_logic;
SchedBusyxSI : in std_logic;
CSREnxEO : out std_logic;
CSRMuxSO : out std_logic);
end ContextSelCtrl;
architecture simple of ContextSelCtrl is
begin -- simple
-- CSR mux
CSRMuxSO <= SchedBusyxSI;
-- CSR enable
CSRenable: process (DecEnxEI, SchedEnxEI, SchedBusyxSI)
begin -- process CSRenable
if SchedBusyxSI = '0' then
CSREnxEO <= DecEnxEI;
else
CSREnxEO <= SchedEnxEI;
end if;
end process CSRenable;
end simple;
|
library verilog;
use verilog.vl_types.all;
entity Controller is
port(
Rb : in vl_logic;
Reset : in vl_logic;
Eq : in vl_logic;
D7 : in vl_logic;
D711 : in vl_logic;
D2312 : in vl_logic;
CLK : in vl_logic;
State_debug : out vl_logic_vector(1 downto 0);
Sp : out vl_logic;
Roll : out vl_logic;
Win : out vl_logic;
Lose : out vl_logic;
Clear : out vl_logic
);
end Controller;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port (
obus: out STD_LOGIC_VECTOR (31 downto 0);
ibus: in STD_LOGIC_VECTOR (31 downto 0);
quada: in STD_LOGIC;
quadb: in STD_LOGIC;
index: in STD_LOGIC;
ccrloadcmd: in STD_LOGIC;
ccrreadcmd: in STD_LOGIC;
countoutreadcmd: in STD_LOGIC;
countlatchcmd: in STD_LOGIC;
countclearcmd: in STD_LOGIC;
countenable: in STD_LOGIC;
indexmask: in STD_LOGIC;
nads: in STD_LOGIC;
clk: in STD_LOGIC
);
end counter;
architecture behavioral of counter is
signal count: STD_LOGIC_VECTOR (31 downto 0);
signal up: STD_LOGIC;
signal down: STD_LOGIC;
signal countoutlatch: STD_LOGIC_VECTOR (31 downto 0);
signal outlatchdel1: STD_LOGIC;
signal outlatchdel2: STD_LOGIC;
signal quada1: STD_LOGIC;
signal quada2: STD_LOGIC;
signal quadacnt: STD_LOGIC_VECTOR (3 downto 0);
signal quadafilt: STD_LOGIC;
signal quadb1: STD_LOGIC;
signal quadb2: STD_LOGIC;
signal quadbcnt: STD_LOGIC_VECTOR (3 downto 0);
signal quadbfilt: STD_LOGIC;
signal index1: STD_LOGIC;
signal index2: STD_LOGIC;
signal indexcnt: STD_LOGIC_VECTOR (3 downto 0);
signal indexfilt: STD_LOGIC;
signal qcountup: STD_LOGIC;
signal qcountdown: STD_LOGIC;
signal udcountup: STD_LOGIC;
signal udcountdown: STD_LOGIC;
signal autocount: STD_LOGIC;
signal doclear: STD_LOGIC;
signal clearonindex: STD_LOGIC; -- ccr register bits...
signal clearonce: STD_LOGIC;
signal indexgate: STD_LOGIC;
signal indexsrc: STD_LOGIC;
signal latchonread: STD_LOGIC;
signal quadfilter: STD_LOGIC;
signal countermode: STD_LOGIC;
signal indexpol: STD_LOGIC;
signal ccrloadcmd1: STD_LOGIC;
signal ccrloadcmd2: STD_LOGIC;
signal localhold: STD_LOGIC;
signal localclear: STD_LOGIC;
signal indexmaskenable: STD_LOGIC;
signal indexmaskpol: STD_LOGIC;
signal fixedindexmask: STD_LOGIC;
signal latchonce: STD_LOGIC;
signal latchonindex: STD_LOGIC;
signal flimit: STD_LOGIC_VECTOR (3 downto 0);
begin
acounter: process (clk, countoutlatch)
begin
if clk'event and clk = '1' then
outlatchdel1 <= countlatchcmd;
outlatchdel2 <= outlatchdel1;
if indexgate = '0' then
indexsrc <= index;
else
if indexpol = '1' then
indexsrc <= not quada and not quadb and index;
else
indexsrc <= (quada or quadb) and index;
end if;
end if;
if indexmaskpol = '1' then
fixedindexmask <= indexmask;
else
fixedindexmask <= not indexmask;
end if;
if quadfilter = '1' then
flimit <= "1111";
else
flimit <= "0011";
end if;
quada1 <= quadafilt;
quada2 <= quada1;
quadb1 <= quadbfilt;
quadb2 <= quadb1;
index1 <= indexfilt;
index2 <= index1;
-- deadended counter for A input filter --
if (quada = '1') and (quadacnt < flimit) then
quadacnt <= quadacnt + 1;
end if;
if (quada = '0') and (quadacnt /= 0) then
quadacnt <= quadacnt -1;
end if;
if quadacnt >= flimit then
quadafilt<= '1';
end if;
if quadacnt = 0 then
quadafilt<= '0';
end if;
-- deadended counter for B input filter --
if (quadb = '1') and (quadbcnt < flimit ) then
quadbcnt <= quadbcnt + 1;
end if;
if (quadb = '0') and (quadbcnt /= 0) then
quadbcnt <= quadbcnt -1;
end if;
if quadbcnt >= flimit then
quadbfilt<= '1';
end if;
if quadbcnt = 0 then
quadbfilt <= '0';
end if;
-- deadended counter for index input filter --
if (indexsrc = '1') and (indexcnt < flimit ) then
indexcnt <= indexcnt + 1;
end if;
if (indexsrc = '0') and (indexcnt /= 0) then
indexcnt <= indexcnt -1;
end if;
if indexcnt >= flimit then
indexfilt<= '1';
end if;
if indexcnt = 0 then
indexfilt<= '0';
end if;
if (countclearcmd = '1') or (localclear = '1') or
((clearonindex = '1') and (index1 = '1') and (index2 = '0') and (indexpol = '1') and (indexmaskenable = '0')) or -- rising edge of index
((clearonindex = '1') and (index1 = '0') and (index2 = '1') and (indexpol = '0') and (indexmaskenable = '0')) or -- falling edge of index
((clearonindex = '1') and (index1 = '1') and (index2 = '0') and (indexpol = '1') and (indexmaskenable = '1') and (fixedindexmask = '1')) or -- rising edge of index when masked
((clearonindex = '1') and (index1 = '0') and (index2 = '1') and (indexpol = '0') and (indexmaskenable = '1') and (fixedindexmask = '1')) then -- falling edge of index when masked
doclear <= '1';
if clearonce = '1' then
clearonindex <= '0';
end if;
else
doclear <= '0';
end if;
if ((latchonread = '1') and (nads = '0')) or -- (let the synthesizer factor this out...)
((outlatchdel2 = '0') and (outlatchdel1 = '1') and (latchonindex = '0')) or
((latchonindex = '1') and (index1 = '1') and (index2 = '0') and (indexpol = '1') and (indexmaskenable = '0')) or -- rising edge of index
((latchonindex = '1') and (index1 = '0') and (index2 = '1') and (indexpol = '0') and (indexmaskenable = '0')) or -- falling edge of index
((latchonindex = '1') and (index1 = '1') and (index2 = '0') and (indexpol = '1') and (indexmaskenable = '1') and (fixedindexmask = '1')) or -- rising edge of index when masked
((latchonindex = '1') and (index1 = '0') and (index2 = '1') and (indexpol = '0') and (indexmaskenable = '1') and (fixedindexmask = '1')) then -- falling edge of index when masked
countoutlatch <= count;
if latchonce = '1' then
latchonindex <= '0';
end if;
end if;
if countermode = '0' and countenable = '1' and localhold ='0' and doclear = '0' and (
(quada2 = '0' and quada1 = '1' and quadb2 = '0' and quadb1 = '0') or
(quada2 = '0' and quada1 = '0' and quadb2 = '1' and quadb1 = '0') or
(quada2 = '1' and quada1 = '1' and quadb2 = '0' and quadb1 = '1') or
(quada2 = '1' and quada1 = '0' and quadb2 = '1' and quadb1 = '1')) then
qcountup <= '1';
else
qcountup <= '0';
end if;
if (countermode = '1' and countenable = '1' and localhold ='0' and doclear = '0' and
quadb2 = '1' and quada2 = '0' and quada1 = '1') then
udcountup <= '1';
else
udcountup <= '0';
end if;
if countermode = '0' and countenable = '1' and localhold ='0' and doclear = '0' and (
(quada2 = '0' and quada1 = '0' and quadb2 = '0' and quadb1 = '1') or
(quada2 = '0' and quada1 = '1' and quadb2 = '1' and quadb1 = '1') or
(quada2 = '1' and quada1 = '0' and quadb2 = '0' and quadb1 = '0') or
(quada2 = '1' and quada1 = '1' and quadb2 = '1' and quadb1 = '0')) then
qcountdown <= '1';
else
qcountdown <= '0';
end if;
if (countermode = '1' and countenable = '1' and localhold ='0' and doclear = '0' and
quadb2 = '0' and quada2 = '0' and quada1 = '1') then
udcountdown <= '1';
else
udcountdown <= '0';
end if;
if up /= down then
if up = '1' then
count <= count + 1;
else
count <= count - 1;
end if;
end if;
if doclear = '1' then
count <= x"00000000";
end if;
if ccrloadcmd = '1' then -- load ccr
indexmaskpol <= ibus(15);
indexmaskenable <= ibus(14);
latchonce <= ibus(13);
latchonindex <= ibus(12);
autocount <= ibus(11);
countermode <= ibus(10);
quadfilter <= ibus(9);
localhold <= ibus(8);
indexgate <= ibus(7);
clearonce <= ibus(6);
clearonindex <= ibus(5);
indexpol <= ibus(4);
latchonread <= ibus(3);
localclear <= ibus(2);
end if;
if localclear = '1' then -- once were done clearing,, dont stick around
localclear <= '0';
end if;
end if; --(clock edge)
if (qcountup = '1' or udcountup = '1' or Autocount = '1') and localhold= '0' and doclear = '0' then
up <= '1';
else
up <= '0';
end if;
if (qcountdown = '1' or udcountdown = '1' ) and Autocount = '0' and localhold ='0' and doclear = '0' then
down <= '1';
else
down <= '0';
end if;
obus <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
if (countoutreadcmd = '1') and (ccrreadcmd = '0') then
obus <= countoutlatch;
end if;
if (ccrreadcmd = '1') and (countoutreadcmd = '0') then
obus(15) <= indexmaskpol;
obus(14) <= indexmask;
obus(13) <= latchonce;
obus(12) <= latchonindex;
obus(11) <= autocount;
obus(10) <= countermode;
obus(9) <= quadfilter;
obus(8) <= localhold;
obus(7) <= indexgate;
obus(6) <= clearonce;
obus(5) <= clearonindex;
obus(4) <= indexpol;
obus(3) <= latchonread;
obus(2) <= index1;
obus(1) <= quadb1;
obus(0) <= quada1;
end if;
end process;
end behavioral;
|
--------------------------------------------------------------------------------
-- Title : Data Unit of VME-Bridge
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_du.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 13/01/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- This unit handles the data path.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- vme_ctrl
-- vme_du
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.8 $
--
-- $Log: vme_du.vhd,v $
-- Revision 1.8 2015/09/16 09:20:05 mwawrik
-- Added generic USE_LONGADD
--
-- Revision 1.7 2014/04/17 07:35:25 MMiehling
-- added generic LONGADD_SIZE
--
-- Revision 1.6 2013/09/12 08:45:23 mmiehling
-- support of address modifier supervisory, non-privileged data/program for A16, A24 and A32
--
-- Revision 1.5 2012/11/15 09:43:53 MMiehling
-- connected each interrupt source to interface in order to support edge triggered msi
--
-- Revision 1.4 2012/11/12 08:13:10 MMiehling
-- bugfix locmon: improved handling of adr(4:3) for stable results
--
-- Revision 1.3 2012/09/25 11:21:43 MMiehling
-- added wbm_err signal for error signalling from pcie to vme
--
-- Revision 1.2 2012/08/27 12:57:13 MMiehling
-- general rework of d64 slave access handling
-- rework of reset handling
--
-- Revision 1.1 2012/03/29 10:14:39 MMiehling
-- Initial Revision
--
-- Revision 1.11 2006/06/02 15:48:59 MMiehling
-- changed default of arbitration => now not fair is default
--
-- Revision 1.10 2005/02/04 13:44:17 mmiehling
-- added combinations of addr3+4
--
-- Revision 1.9 2004/11/02 11:29:58 mmiehling
-- improved timing and area
-- moved dma_reg to vme_du
--
-- Revision 1.8 2004/07/27 17:15:42 mmiehling
-- changed pci-core to 16z014
-- changed wishbone bus to wb_bus.vhd
-- added clk_trans_wb2wb.vhd
-- improved dma
--
-- Revision 1.7 2003/12/17 15:51:48 MMiehling
-- byte swapping in "not swapped" mode was wrong
--
-- Revision 1.6 2003/12/01 10:03:55 MMiehling
-- added d64
--
-- Revision 1.5 2003/07/14 08:38:10 MMiehling
-- changed mail_irq; added lwordn
--
-- Revision 1.4 2003/06/24 13:47:10 MMiehling
-- added rst_aonly; changed vme_data_in_reg sampling (lwordn)
--
-- Revision 1.3 2003/06/13 10:06:38 MMiehling
-- added address bits 3+4 for locmon; changed locsta register
--
-- Revision 1.2 2003/04/22 11:03:02 MMiehling
-- changed irq and address map for locmon
--
-- Revision 1.1 2003/04/01 13:04:43 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY vme_du IS
GENERIC (
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
-- If TRUE, number of bits allocated to vme_adr_out depends on GENERIC LONGADD_SIZE
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
startup_rst : IN std_logic; -- powerup reset
vme_irq : OUT std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
berr_irq : OUT std_logic; -- signal berrn interrupt request
locmon_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
mailbox_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
-- dma
dma_sta : OUT std_logic_vector(9 DOWNTO 0);
clr_dma_en : IN std_logic;
set_dma_err : IN std_logic;
dma_act_bd : IN std_logic_vector(7 DOWNTO 4);
-- arbiter
sel_reg_data_in : IN std_logic; -- mux select signal for wbb/vme register access
sel_loc_data_out : IN std_logic_vector(1 DOWNTO 0); -- mux select signal for 0=reg, 1=vme data_out
en_wbm_dat_o : IN std_logic; -- enable for wbm_dat_o
-- requester
brl : OUT std_logic_vector(1 DOWNTO 0); -- bus request leve
-- vme_au
int_adr : IN std_logic_vector(18 DOWNTO 0); -- internal adress for reg
int_be : IN std_logic_vector(3 DOWNTO 0); -- internal byte enables
vme_adr_out : IN std_logic_vector(31 DOWNTO 0); -- vme adress lines
byte_routing : IN std_logic; -- mux select for byte routing
vme_adr_in : OUT std_logic_vector(31 DOWNTO 0); -- vme adress input lines
my_iack : IN std_logic;
d64 : IN std_logic; -- indicates d64 mblt
vam_reg : IN std_logic_vector(5 DOWNTO 0); -- registered vam_in for location monitoring and berr_adr (registered with en_vme_adr_in)
vme_adr_in_reg : IN std_logic_vector(31 DOWNTO 2); -- vme adress for location monitoring and berr_adr (registered with en_vme_adr_in)
sl_writen_reg : IN std_logic; -- vme read/wrtie signal (registered with en_vme_adr_in)
iackn_in_reg : IN std_logic; -- iack signal (registered with en_vme_adr_in)
-- sys_arbiter
lwordn : IN std_logic; -- stored for vme slave access
-- ctrl_mux
write_flag : IN std_logic; -- write flag for register write access
-- master
oe_vd : IN std_logic; -- output enable for vme data
oe_va : IN std_logic; -- output enable for vme adress
second_word : IN std_logic; -- indicates data phase of d64
-- slave
sel_vme_data_out : IN std_logic_vector(1 DOWNTO 0); -- mux select for vme data out
en_vme_data_out_reg : IN std_logic; -- register enable for vme data out
en_vme_data_out_reg_high: IN std_logic; -- register enable for vme data out high long
en_vme_data_in_reg : IN std_logic; -- register enable for vme data in
en_vme_data_in_reg_high : IN std_logic; -- register enable for vme data in high long
clr_intreq : IN std_logic; -- clear interrupt request (intr(3) <= '0'
-- wbb_slave
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0); -- indicates dma(1) or normal(0) access
swap : IN std_logic; -- swapps bytes when enabled
-- wbb_master
wbm_ack_i : IN std_logic;
wbm_err_i : IN std_logic;
wbm_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dat_i : IN std_logic_vector(31 DOWNTO 0);
sel_wbm_dat_o : IN std_logic; -- selects between low and high d32
-- register out
longadd : OUT std_logic_vector(7 DOWNTO 0); -- upper 3 address bits for A32 mode or dependent on LONGADD_SIZE
mstr_reg : OUT std_logic_vector(13 DOWNTO 0); -- master register (aonly, postwr, iberr, berr, req, rmw, A16_MODE, A24_MODE, A32_MODE)
sysc_reg : OUT std_logic_vector(2 DOWNTO 0); -- system control register (ato, sysr, sysc)
slv16_reg : OUT std_logic_vector(4 DOWNTO 0); -- slave A16 base address register
slv24_reg : OUT std_logic_vector(15 DOWNTO 0); -- slave A24 base address register
slv32_reg : OUT std_logic_vector(23 DOWNTO 0); -- slave A32 base address register
slv24_pci_q : OUT std_logic_vector(15 DOWNTO 0); -- slave A24 base address register for PCI
slv32_pci_q : OUT std_logic_vector(23 DOWNTO 0); -- slave A32 base address register for PCI
intr_reg : OUT std_logic_vector(3 DOWNTO 0); -- interrupt request register
pci_offset_q : OUT std_logic_vector(31 DOWNTO 2); -- pci offset address for vme to pci access
-- register bits
set_berr : IN std_logic; -- if bit is set => berr bit will be set
rst_rmw : IN std_logic; -- if bit is set => rmw bit will be cleared
set_sysc : IN std_logic; -- if bit is set => sysc bit will be set
set_ato : IN std_logic; -- if bit is set => ato bit will be set
clr_sysr : IN std_logic; -- if bit is set => sysr bit will be cleared
mail_irq : IN std_logic_vector(7 DOWNTO 0); -- mailbox interrupt flags
loc_am_0 : OUT std_logic_vector(1 DOWNTO 0); -- loc-monitor #0 - adress modus "00"-A32, "10"-A16, "11"-A24
loc_am_1 : OUT std_logic_vector(1 DOWNTO 0); -- loc-monitor #1 - adress modus "00"-A32, "10"-A16, "11"-A24
loc_irq_0 : IN std_logic; -- loc-monitor #0 - irq
loc_irq_1 : IN std_logic; -- loc-monitor #1 - irq
loc_rw_0 : OUT std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
loc_rw_1 : OUT std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
loc_adr_0 : OUT std_logic_vector(31 DOWNTO 0); -- location monitor #0 adress
loc_adr_1 : OUT std_logic_vector(31 DOWNTO 0); -- location monitor #1 adress
loc_sel : IN std_logic_vector(1 DOWNTO 0); -- these bits are loaded with combinations of address bits [4:3] if locmon hit address
rst_aonly : IN std_logic; -- resets aonly bit
clr_locmon : OUT std_logic_vector(1 DOWNTO 0); -- clear address combination bits when clear status bit
-- irq pins
irq_i_n : IN std_logic_vector(7 DOWNTO 1);
irq_o_n : OUT std_logic_vector(7 DOWNTO 1);
acfailn : IN std_logic; -- ACFAIL# input from Power Supply
--vme
ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
gap : IN std_logic; -- geographical addresses parity
vd : INOUT std_logic_vector(31 DOWNTO 0);
va : INOUT std_logic_vector(31 DOWNTO 0)
);
END vme_du;
ARCHITECTURE vme_du_arch OF vme_du IS
CONSTANT null_vec : std_logic_vector(23 DOWNTO 0):="000000000000000000000000";
SIGNAL reg_data_in : std_logic_vector(31 DOWNTO 0);
SIGNAL reg_data_out : std_logic_vector(31 DOWNTO 0);
SIGNAL vme_data_in_reg_mux : std_logic_vector(31 DOWNTO 0);
SIGNAL vme_data_in_reg : std_logic_vector(63 DOWNTO 0);
SIGNAL vme_data_out_reg : std_logic_vector(63 DOWNTO 0);
SIGNAL vd_in : std_logic_vector(31 DOWNTO 0);
SIGNAL vd_in_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL vd_in_reg_int : std_logic_vector(31 DOWNTO 0);
SIGNAL vd_out_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL va_in : std_logic_vector(31 DOWNTO 0);
SIGNAL va_in_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL va_out_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL wbs_dat_o_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL mstr_int : std_logic_vector(13 DOWNTO 0);
SIGNAL longadd_int : std_logic_vector(7 DOWNTO 0);
SIGNAL intr_int : std_logic_vector(3 DOWNTO 0);
SIGNAL intid_int : std_logic_vector(7 DOWNTO 0);
SIGNAL istat : std_logic_vector(7 DOWNTO 0);
SIGNAL imask : std_logic_vector(7 DOWNTO 0);
SIGNAL sysc_reg_int : std_logic_vector(2 DOWNTO 0);
SIGNAL mail_irqe : std_logic_vector(7 DOWNTO 0);
SIGNAL mail_irq_reg : std_logic_vector(7 DOWNTO 0);
SIGNAL locsta_0 : std_logic_vector(5 DOWNTO 0);
SIGNAL locsta_1 : std_logic_vector(5 DOWNTO 0);
SIGNAL loc_adr_0_int : std_logic_vector(31 DOWNTO 0);
SIGNAL loc_adr_1_int : std_logic_vector(31 DOWNTO 0);
SIGNAL slv16_reg_int : std_logic_vector(4 DOWNTO 0);
SIGNAL slv24_reg_int : std_logic_vector(15 DOWNTO 0);
SIGNAL slv32_reg_int : std_logic_vector(23 DOWNTO 0);
SIGNAL slv24_pci_q_int : std_logic_vector(15 DOWNTO 0);
SIGNAL slv32_pci_q_int : std_logic_vector(23 DOWNTO 0);
SIGNAL pci_offset_int : std_logic_vector(31 DOWNTO 12);
SIGNAL acfailn_regd : std_logic;
SIGNAL irqregd : std_logic_vector(7 DOWNTO 1);
SIGNAL acfst : std_logic;
SIGNAL wbm_dat_i_reg : std_logic_vector(31 DOWNTO 0);
SIGNAL dma_sta_int : std_logic_vector(9 DOWNTO 0);
SIGNAL test : std_logic_vector(20 DOWNTO 0):="000000000000000000000";
SIGNAL swap_byte_routing : std_logic_vector(1 DOWNTO 0);
SIGNAL vad_sel : std_logic_vector(2 DOWNTO 0);
SIGNAL loc_irq_0_q : std_logic; -- loc-monitor #0 - irq
SIGNAL loc_irq_1_q : std_logic; -- loc-monitor #1 - irq
SIGNAL loc_sel_0_int : std_logic_vector(1 DOWNTO 0);
SIGNAL loc_sel_1_int : std_logic_vector(1 DOWNTO 0);
SIGNAL set_dma_err_q : std_logic;
SIGNAL ga_q : std_logic_vector(5 DOWNTO 0); -- geographical addresses and parity
SIGNAL slot_nr : std_logic_vector(4 DOWNTO 0); -- slot number
SIGNAL brl_int : std_logic_vector(1 DOWNTO 0); -- bus request level
SIGNAL berr_vam : std_logic_vector(5 downto 0);
SIGNAL berr_adr : std_logic_vector(31 downto 0);
SIGNAL berr_rw : std_logic;
SIGNAL berr_iack : std_logic;
BEGIN
vme_adr_in <= va_in_reg;
longadd <= longadd_int WHEN USE_LONGADD ELSE longadd_int(2 DOWNTO 0)&"00000";
pci_offset_q <= pci_offset_int & "0000000000";
vme_irq <= istat;
vd_proc : PROCESS(vd_out_reg, vd, oe_vd)
BEGIN
IF oe_vd = '1' THEN
vd <= vd_out_reg;
vd_in <= vd;
ELSE
vd <= (OTHERS => 'Z');
vd_in <= vd;
END IF;
END PROCESS vd_proc;
va_proc : PROCESS(va_out_reg, va, oe_va)
BEGIN
IF oe_va = '1' THEN
va <= va_out_reg;
va_in <= va;
ELSE
va <= (OTHERS => 'Z');
va_in <= va;
END IF;
END PROCESS va_proc;
-- swap = 1, byte_routing = 1 => 3210
-- swap = 1, byte_routing = 0 => 1032
-- byte_routing = 1 => 2301
-- byte_routing = 0 => 0123
swap_byte_routing <= swap & byte_routing;
PROCESS (vd_in_reg_int, swap_byte_routing)
BEGIN
CASE swap_byte_routing IS
WHEN "01" => vme_data_in_reg_mux <= vd_in_reg_int(31 DOWNTO 0);
WHEN "00" => vme_data_in_reg_mux <= vd_in_reg_int(15 DOWNTO 0) & vd_in_reg_int(31 DOWNTO 16);
WHEN "11" => vme_data_in_reg_mux <= vd_in_reg_int(23 DOWNTO 16) & vd_in_reg_int(31 DOWNTO 24) & vd_in_reg_int(7 DOWNTO 0) & vd_in_reg_int(15 DOWNTO 8);
WHEN "10" => vme_data_in_reg_mux <= vd_in_reg_int(7 DOWNTO 0) & vd_in_reg_int(15 DOWNTO 8) & vd_in_reg_int(23 DOWNTO 16) & vd_in_reg_int(31 DOWNTO 24);
WHEN OTHERS => vme_data_in_reg_mux <= vd_in_reg_int(7 DOWNTO 0) & vd_in_reg_int(15 DOWNTO 8) & vd_in_reg_int(23 DOWNTO 16) & vd_in_reg_int(31 DOWNTO 24);
END CASE;
END PROCESS;
reg_data_in <= wbs_dat_i WHEN sel_reg_data_in = '1' ELSE vme_data_in_reg(31 DOWNTO 0);
wbs_dat_o <= wbs_dat_o_reg;
vd_in_reg_int <= va_in_reg WHEN d64 = '1' AND en_vme_data_in_reg_high = '1' ELSE vd_in_reg;
reg : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
vd_in_reg <= (OTHERS => '0');
vd_out_reg <= (OTHERS => '0');
vme_data_in_reg <= (OTHERS => '0');
vme_data_out_reg <= (OTHERS => '0');
va_out_reg <= (OTHERS => '0');
va_in_reg <= (OTHERS => '0');
wbs_dat_o_reg <= (OTHERS => '0');
wbm_dat_o <= (OTHERS => '0');
wbm_dat_i_reg <= (OTHERS => '0');
ga_q <= (OTHERS => '0');
slot_nr <= (OTHERS => '0');
ELSIF clk'EVENT and clk = '1' THEN
-- synchronization registers
ga_q <= gap & ga;
CASE ga_q IS
WHEN "111110" => slot_nr <= conv_std_logic_vector(1 ,5);
WHEN "111101" => slot_nr <= conv_std_logic_vector(2 ,5);
WHEN "011100" => slot_nr <= conv_std_logic_vector(3 ,5);
WHEN "111011" => slot_nr <= conv_std_logic_vector(4 ,5);
WHEN "011010" => slot_nr <= conv_std_logic_vector(5 ,5);
WHEN "011001" => slot_nr <= conv_std_logic_vector(6 ,5);
WHEN "111000" => slot_nr <= conv_std_logic_vector(7 ,5);
WHEN "110111" => slot_nr <= conv_std_logic_vector(8 ,5);
WHEN "010110" => slot_nr <= conv_std_logic_vector(9 ,5);
WHEN "010101" => slot_nr <= conv_std_logic_vector(10,5);
WHEN "110100" => slot_nr <= conv_std_logic_vector(11,5);
WHEN "010011" => slot_nr <= conv_std_logic_vector(12,5);
WHEN "110010" => slot_nr <= conv_std_logic_vector(13,5);
WHEN "110001" => slot_nr <= conv_std_logic_vector(14,5);
WHEN "010000" => slot_nr <= conv_std_logic_vector(15,5);
WHEN "101111" => slot_nr <= conv_std_logic_vector(16,5);
WHEN "001110" => slot_nr <= conv_std_logic_vector(17,5);
WHEN "001101" => slot_nr <= conv_std_logic_vector(18,5);
WHEN "101100" => slot_nr <= conv_std_logic_vector(19,5);
WHEN "001011" => slot_nr <= conv_std_logic_vector(20,5);
WHEN "101010" => slot_nr <= conv_std_logic_vector(21,5);
WHEN OTHERS => slot_nr <= conv_std_logic_vector(30,5); -- amnesia address
END CASE;
IF wbm_ack_i = '1' THEN
wbm_dat_i_reg <= wbm_dat_i;
ELSIF wbm_err_i = '1' THEN
wbm_dat_i_reg <= x"eeee_eeee"; -- should indicate 'error'
END IF;
IF en_wbm_dat_o = '1' AND sel_wbm_dat_o = '0' THEN -- low long
wbm_dat_o <= vme_data_in_reg(31 DOWNTO 0);
ELSIF en_wbm_dat_o = '1' AND sel_wbm_dat_o = '1' THEN -- high long
wbm_dat_o <= vme_data_in_reg(63 DOWNTO 32);
END IF;
vd_in_reg <= vd_in;
IF swap = '1' AND d64 = '1' THEN
-- swapping for d64: high and low 4 byte are swapped
IF en_vme_data_in_reg_high = '1' THEN
vme_data_in_reg(31 DOWNTO 0) <= va_in_reg(7 DOWNTO 0) & va_in_reg(15 DOWNTO 8) & va_in_reg(23 DOWNTO 16) & va_in_reg(31 DOWNTO 24);
END IF;
IF en_vme_data_in_reg = '1' THEN
vme_data_in_reg(63 DOWNTO 32) <= vd_in_reg(7 DOWNTO 0) & vd_in_reg(15 DOWNTO 8) & vd_in_reg(23 DOWNTO 16) & vd_in_reg(31 DOWNTO 24);
END IF;
ELSE
IF en_vme_data_in_reg = '1' AND (lwordn = '0' OR (lwordn = '1' AND byte_routing = '0')) THEN
vme_data_in_reg(31 DOWNTO 16) <= vme_data_in_reg_mux(31 DOWNTO 16);
END IF;
IF en_vme_data_in_reg = '1' AND (lwordn = '0' OR (lwordn = '1' AND byte_routing = '1')) THEN
vme_data_in_reg(15 DOWNTO 0) <= vme_data_in_reg_mux(15 DOWNTO 0);
END IF;
IF en_vme_data_in_reg_high = '1' THEN
vme_data_in_reg(63 DOWNTO 32) <= vme_data_in_reg_mux(31 DOWNTO 0);
END IF;
END IF;
-- DATA output
IF swap = '1' THEN
IF d64 = '1' THEN -- data phase for d64 mblt 7654
vd_out_reg <= vme_data_out_reg(39 DOWNTO 32) & vme_data_out_reg(47 DOWNTO 40) & vme_data_out_reg(55 DOWNTO 48) & vme_data_out_reg(63 DOWNTO 56);
ELSIF byte_routing = '1' THEN -- data phase with byte routing 0123
vd_out_reg <= vme_data_out_reg(23 DOWNTO 16) & vme_data_out_reg(31 DOWNTO 24) & vme_data_out_reg(7 DOWNTO 0) & vme_data_out_reg(15 DOWNTO 8);
ELSE -- data phase with byte routing 2301
vd_out_reg <= vme_data_out_reg(7 DOWNTO 0) & vme_data_out_reg(15 DOWNTO 8) & vme_data_out_reg(23 DOWNTO 16) & vme_data_out_reg(31 DOWNTO 24);
END IF;
ELSE
IF byte_routing = '1' THEN
vd_out_reg <= vme_data_out_reg(31 DOWNTO 0);-- data phase with byte routing 3210
ELSE
vd_out_reg <= vme_data_out_reg(15 DOWNTO 0) & vme_data_out_reg(31 DOWNTO 16);-- data phase with byte routing 1032
END IF;
END IF;
-- ADDRESS output
IF swap = '1' THEN
IF second_word = '1' AND d64 = '1' THEN -- master d64 data phases
va_out_reg <= vme_data_out_reg(7 DOWNTO 0) & vme_data_out_reg(15 DOWNTO 8) & vme_data_out_reg(23 DOWNTO 16) & vme_data_out_reg(31 DOWNTO 24);
ELSE -- master address phase
va_out_reg <= vme_adr_out;
END IF;
ELSE
IF second_word = '1' AND d64 = '1' THEN -- master d64 data phases
va_out_reg <= vme_data_out_reg(63 DOWNTO 32);
ELSE -- master address phase
va_out_reg <= vme_adr_out;
END IF;
END IF;
va_in_reg <= va_in;
IF en_vme_data_out_reg = '1' THEN
IF my_iack = '1' THEN -- vme slave iack read access
vme_data_out_reg(31 DOWNTO 0) <= intid_int & intid_int & intid_int & intid_int;
ELSIF sel_vme_data_out = "10" THEN -- vme slave read access from registers
vme_data_out_reg(31 DOWNTO 0) <= reg_data_out;
ELSIF sel_vme_data_out = "01" THEN -- vme master write access
vme_data_out_reg(31 DOWNTO 0) <= wbs_dat_i;
ELSE -- vme slave read access
vme_data_out_reg(31 DOWNTO 0) <= wbm_dat_i_reg;
END IF;
END IF;
IF en_vme_data_out_reg_high = '1' THEN
IF sel_vme_data_out = "01" THEN
vme_data_out_reg(63 DOWNTO 32) <= wbs_dat_i; -- vme master 64-bit write access
ELSE
vme_data_out_reg(63 DOWNTO 32) <= wbm_dat_i_reg; -- vme slave 64-bit read access
END IF;
END IF;
IF sel_loc_data_out(0) = '0' THEN
wbs_dat_o_reg <= reg_data_out;
ELSIF sel_loc_data_out(1) = '0' THEN
wbs_dat_o_reg <= vme_data_in_reg(31 DOWNTO 0);
ELSE
wbs_dat_o_reg <= vme_data_in_reg(63 DOWNTO 32);
END IF;
END IF;
END PROCESS reg;
----------------------------------------------------------------------------------------------
-- Registers
----------------------------------------------------------------------------------------------
reg_out : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
reg_data_out <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
CASE int_adr(6 DOWNTO 2) IS
WHEN "00000" => reg_data_out <= x"000000" & "0000" & intr_int; -- 0x000
WHEN "00001" => reg_data_out <= x"000000" & intid_int; -- 0x004
WHEN "00010" => reg_data_out <= x"000000" & istat; -- 0x008
WHEN "00011" => reg_data_out <= x"000000" & imask; -- 0x00c
WHEN "00100" => reg_data_out <= x"0000" & "00" & mstr_int; -- 0x010
WHEN "00101" => reg_data_out <= x"0000" & slv24_reg_int(15 DOWNTO 8) & "000" & slv24_reg_int(4 DOWNTO 0); -- 0x014
WHEN "00110" => reg_data_out <= x"000000" & "00000" & sysc_reg_int; -- 0x018
WHEN "00111" => reg_data_out <= x"000000" & longadd_int; -- 0x01c
WHEN "01000" => reg_data_out <= x"000000" & mail_irqe; -- 0x020
WHEN "01001" => reg_data_out <= x"000000" & mail_irq_reg; -- 0x024
WHEN "01010" => reg_data_out <= pci_offset_int(31 DOWNTO 12) & x"000"; -- 0x028
WHEN "01011" => reg_data_out <= x"000000" & dma_sta_int(7 DOWNTO 0); -- 0x02c
WHEN "01100" => reg_data_out <= x"000000" & "000" & slv16_reg_int; -- 0x030
WHEN "01101" => reg_data_out <= x"00" & slv32_reg_int(23 DOWNTO 8) & "000" & slv32_reg_int(4 DOWNTO 0); -- 0x034
WHEN "01110" => reg_data_out <= x"000000" & loc_sel_0_int & locsta_0; -- 0x038
WHEN "01111" => reg_data_out <= x"000000" & loc_sel_1_int & locsta_1; -- 0x03c
WHEN "10000" => reg_data_out <= loc_adr_0_int(31 DOWNTO 0); -- 0x040
WHEN "10001" => reg_data_out <= loc_adr_1_int(31 DOWNTO 0); -- 0x044
WHEN "10010" => reg_data_out <= x"0000" & slv24_pci_q_int(15 DOWNTO 8) & "000" & slv24_pci_q_int(4 DOWNTO 0); -- 0x048
WHEN "10011" => reg_data_out <= x"00" & slv32_pci_q_int(23 DOWNTO 8) & "000" & slv32_pci_q_int(4 DOWNTO 0); -- 0x04c
WHEN "10100" => reg_data_out <= x"0000" & "000" & slot_nr & "00" & ga_q; -- 0x050
WHEN "10101" => reg_data_out <= x"0000_000" & "00" & brl_int; -- 0x054
WHEN "10110" => reg_data_out <= berr_adr; -- 0x058
WHEN "10111" => reg_data_out <= x"0000_00" & berr_iack & berr_rw & berr_vam; -- 0x05c
WHEN OTHERS => reg_data_out <= (OTHERS => '0');
END CASE;
END IF;
END PROCESS reg_out;
-------------------------------------------------------------------------------
-- dma_sta_int register 0x2c
sta :PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
dma_sta_int(3 DOWNTO 0) <= (OTHERS => '0');
dma_sta_int(9 DOWNTO 8) <= (OTHERS => '0');
set_dma_err_q <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
set_dma_err_q <= set_dma_err;
IF clr_dma_en = '1' THEN
dma_sta_int(0) <= '0';
dma_sta_int(8) <= '0';
ELSIF write_flag = '1' AND int_be(0) = '1' AND int_adr(6 DOWNTO 2) = "01011" THEN
dma_sta_int(0) <= reg_data_in(0);
dma_sta_int(8) <= reg_data_in(0);
ELSE
dma_sta_int(8) <= '0';
END IF;
IF write_flag = '1' AND int_be(0) = '1' AND int_adr(6 DOWNTO 2) = "01011" THEN
dma_sta_int(1) <= reg_data_in(1);
END IF;
IF clr_dma_en = '1' AND dma_sta_int(1) = '1' THEN
dma_sta_int(2) <= '1';
ELSIF write_flag = '1' AND int_be(0) = '1' AND int_adr(6 DOWNTO 2) = "01011" AND reg_data_in(2) = '1' THEN
dma_sta_int(2) <= '0';
END IF;
IF set_dma_err = '1' AND set_dma_err_q = '0' THEN
dma_sta_int(3) <= '1';
dma_sta_int(9) <= '0';
ELSIF write_flag = '1' AND int_be(0) = '1' AND int_adr(6 DOWNTO 2) = "01011" AND reg_data_in(3) = '1' THEN
dma_sta_int(3) <= '0';
dma_sta_int(9) <= '1';
ELSE
dma_sta_int(9) <= '0';
END IF;
END IF;
END PROCESS sta;
dma_sta_int(7 DOWNTO 4) <= dma_act_bd;
dma_sta <= dma_sta_int;
-------------------------------------------------------------------------------
int_id : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
intid_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00001" AND int_be(0) = '1' THEN
intid_int(7 DOWNTO 0) <= reg_data_in(7 DOWNTO 0);
END IF;
END IF;
END PROCESS int_id;
-------------------------------------------------------------------------------
-- PCI-offset register
-------------------------------------------------------------------------------
pci_o : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
pci_offset_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01010" AND int_be(1) = '1' THEN
pci_offset_int(15 DOWNTO 12) <= reg_data_in(15 DOWNTO 12);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01010" AND int_be(2) = '1' THEN
pci_offset_int(23 DOWNTO 16) <= reg_data_in(23 DOWNTO 16);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01010" AND int_be(3) = '1' THEN
pci_offset_int(31 DOWNTO 24) <= reg_data_in(31 DOWNTO 24);
END IF;
END IF;
END PROCESS pci_o;
-------------------------------------------------------------------------------
-- Slave A24 Base address for PCI
-------------------------------------------------------------------------------
sl24_pci : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
slv24_pci_q_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10010" AND int_be(0) = '1' THEN
slv24_pci_q_int(4 DOWNTO 0) <= reg_data_in(4 DOWNTO 0);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10010" AND int_be(1) = '1' THEN
slv24_pci_q_int(15 DOWNTO 8) <= reg_data_in(15 DOWNTO 8);
END IF;
slv24_pci_q_int(7 DOWNTO 5) <= (OTHERS => '0');
END IF;
END PROCESS sl24_pci;
slv24_pci_q <= slv24_pci_q_int(15 DOWNTO 8) & "000" & slv24_pci_q_int(4 DOWNTO 0) ;
-------------------------------------------------------------------------------
-- Slave A32 Base address for PCI
-------------------------------------------------------------------------------
sl32_pci : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
slv32_pci_q_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10011" AND int_be(0) = '1' THEN
slv32_pci_q_int(4 DOWNTO 0) <= reg_data_in(4 DOWNTO 0);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10011" AND int_be(1) = '1' THEN
slv32_pci_q_int(15 DOWNTO 8) <= reg_data_in(15 DOWNTO 8);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10011" AND int_be(2) = '1' THEN
slv32_pci_q_int(23 DOWNTO 16) <= reg_data_in(23 DOWNTO 16);
END IF;
slv32_pci_q_int(7 DOWNTO 5) <= (OTHERS => '0');
END IF;
END PROCESS sl32_pci;
slv32_pci_q <= slv32_pci_q_int(23 DOWNTO 8) & "000" & slv32_pci_q_int(4 DOWNTO 0);
-------------------------------------------------------------------------------
-- Here is the Interrupt Request Register:
-- Consists of (INTEN, IL2-0)
-------------------------------------------------------------------------------
int_r : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
intr_int <= (OTHERS => '0');
irq_o_n <= "1111111";
ELSIF clk'EVENT AND clk = '1' THEN
IF clr_intreq = '1' THEN
intr_int(3) <= '0';
intr_int(2 DOWNTO 0) <= intr_int(2 DOWNTO 0);
ELSIF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00000" AND int_be(0) = '1' THEN
intr_int(3 DOWNTO 0) <= reg_data_in(3 DOWNTO 0);
END IF;
IF intr_int(3) = '1' THEN
CASE intr_int(2 DOWNTO 0) IS
WHEN "001" => irq_o_n <= "1111110";
WHEN "010" => irq_o_n <= "1111101";
WHEN "011" => irq_o_n <= "1111011";
WHEN "100" => irq_o_n <= "1110111";
WHEN "101" => irq_o_n <= "1101111";
WHEN "110" => irq_o_n <= "1011111";
WHEN "111" => irq_o_n <= "0111111";
WHEN OTHERS => irq_o_n <= "1111111";
END CASE;
ELSE
irq_o_n <= "1111111";
END IF;
END IF;
END PROCESS int_r;
intr_reg <= intr_int;
-------------------------------------------------------------------------------
-- The IMASK Register. '0' means interrupt is masked, '1' means it is enabled.
-------------------------------------------------------------------------------
i_mask : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
imask <= (OTHERS => '0');
istat <= (OTHERS => '0');
berr_irq <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00011" AND int_be(0) = '1' THEN
imask <= reg_data_in(7 DOWNTO 0);
END IF;
istat <= (irqregd & acfst) AND imask;
IF mstr_int(3) = '1' AND mstr_int(2) = '1' THEN
berr_irq <= '1';
ELSE
berr_irq <= '0';
END IF;
END IF;
END PROCESS i_mask;
-------------------------------------------------------------------------------
-- Here is the Interrupt Status Register:
-- Consists of (IRQ7-1, ACFST )
-------------------------------------------------------------------------------
regirq : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
irqregd <= (OTHERS => '0');
acfailn_regd <= '1';
acfst <= '0';
ELSIF clk'event AND clk = '1' THEN
irqregd <= NOT irq_i_n;
acfailn_regd <= acfailn;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00010" AND int_be(0) = '1' THEN
acfst <= '0';
ELSIF (acfailn_regd = '0') THEN
acfst <= '1';
END IF;
END IF;
END PROCESS regirq;
-------------------------------------------------------------------------------
-- Here is the Master Register:
-- Consists of (AONLY-bit, POSTWR-bit, IBERR-bit, BERR-bit, REQ-bit, RMW-bit
-- A16_MODE, A24_MODE, A32_MODE)
-------------------------------------------------------------------------------
mstr_int(7) <= '0'; -- unused
-- RMW-bit:
rmwena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(0) <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(0) = '1' THEN
mstr_int(0) <= reg_data_in(0);
ELSIF rst_rmw = '1' THEN
mstr_int(0) <= '0';
END IF;
END IF;
END PROCESS rmwena;
-- REQ-bit:
rwdena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(1) <= '0'; -- default is ROR
ELSIF clk'event AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(0) = '1' THEN
mstr_int(1) <= reg_data_in(1);
END IF;
END IF;
END PROCESS rwdena;
-- BERR-bit and BERR_ADR/BERR_ACC
berrena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(2) <= '0';
berr_vam <= (OTHERS => '0');
berr_adr <= (OTHERS => '0');
berr_rw <= '0';
berr_iack <= '0';
ELSIF (clk'event AND clk = '1') THEN
-- set bus error bit/irq for single and DMA accesses which causes an vme bus error
IF set_berr = '1' THEN
mstr_int(2) <= '1';
ELSIF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND reg_data_in(2) = '1' AND int_be(0) = '1' THEN -- write '1' to berr bit
mstr_int(2) <= '0';
END IF;
IF set_berr = '1' THEN
berr_vam <= vam_reg;
berr_adr <= vme_adr_in_reg & "00";
berr_rw <= sl_writen_reg;
berr_iack <= NOT iackn_in_reg;
ELSIF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND reg_data_in(2) = '1' AND int_be(0) = '1' THEN -- write '1' to berr bit
berr_vam <= (OTHERS => '0');
berr_adr <= (OTHERS => '0');
berr_rw <= '0';
berr_iack <= '0';
END IF;
END IF;
END PROCESS berrena;
-- IBERR-bit:
iberrena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(3) <= '0';
ELSIF (clk'event AND clk = '1') THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(0) = '1' THEN
mstr_int(3) <= reg_data_in(3);
END IF;
END IF;
END PROCESS iberrena;
-- POSTWR-bit:
postwrena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(4) <= '0';
ELSIF (clk'event AND clk = '1') THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(0) = '1' THEN
mstr_int(4) <= reg_data_in(4);
END IF;
END IF;
END PROCESS postwrena;
-- AONLY-bit:
aonlyena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(5) <= '0';
ELSIF (clk'event AND clk = '1') THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(0) = '1' THEN
mstr_int(5) <= reg_data_in(5);
ELSIF rst_aonly = '1' THEN
mstr_int(5) <= '0';
END IF;
END IF;
END PROCESS aonlyena;
-- Fair_requester-bit:
fair : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(6) <= '0'; -- default not fair
ELSIF (clk'event AND clk = '1') THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(0) = '1' THEN
mstr_int(6) <= reg_data_in(6);
END IF;
END IF;
END PROCESS fair;
-- A16_MODE-bit:
a16 : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(9 DOWNTO 8) <= "00"; -- default = non-privileged (AM=0x29)
ELSIF (clk'event AND clk = '1') THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(1) = '1' THEN
mstr_int(9 DOWNTO 8) <= reg_data_in(9 DOWNTO 8);
END IF;
END IF;
END PROCESS a16;
-- A24_MODE-bit:
a24 : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(11 DOWNTO 10) <= "00"; -- default = non-privileged (AM=0x39)
ELSIF (clk'event AND clk = '1') THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(1) = '1' THEN
mstr_int(11 DOWNTO 10) <= reg_data_in(11 DOWNTO 10);
END IF;
END IF;
END PROCESS a24;
-- A32_MODE-bit:
a32 : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mstr_int(13 DOWNTO 12) <= "00"; -- default = non-privileged (AM=0x09)
ELSIF (clk'event AND clk = '1') THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00100" AND int_be(1) = '1' THEN
mstr_int(13 DOWNTO 12) <= reg_data_in(13 DOWNTO 12);
END IF;
END IF;
END PROCESS a32;
mstr_reg <= mstr_int;
-------------------------------------------------------------------------------
-- Here is the System Control Register:
-- Consists of (ATO-bit, SYSR-bit, SYSC-bit)
-------------------------------------------------------------------------------
-- ato-bit
atoena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
sysc_reg_int(2) <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00110" AND reg_data_in(2) = '1' AND int_be(0) = '1' THEN
sysc_reg_int(2) <= '0';
ELSIF set_ato = '1' THEN
sysc_reg_int(2) <= '1';
END IF;
END IF;
END PROCESS atoena;
-- sysr-bit
sysrena : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
sysc_reg_int(1) <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00110" AND int_be(0) = '1' THEN
sysc_reg_int(1) <= reg_data_in(1);
ELSIF clr_sysr = '1' THEN
sysc_reg_int(1) <= '0';
END IF;
END IF;
END PROCESS sysrena;
-- sysc-bit
syscena : PROCESS (clk, startup_rst)
BEGIN
IF startup_rst = '1' THEN
sysc_reg_int(0) <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF set_sysc = '1' THEN
sysc_reg_int(0) <= '1';
ELSIF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00110" AND int_be(0) = '1' THEN
sysc_reg_int(0) <= reg_data_in(0);
END IF;
END IF;
END PROCESS syscena;
sysc_reg <= sysc_reg_int;
---------------------------------------------------------------------------
-- slave base address register
slv24_r : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
slv24_reg_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00101" AND int_be(0) = '1' THEN
slv24_reg_int(4 DOWNTO 0) <= reg_data_in(4 DOWNTO 0);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00101" AND int_be(1) = '1' THEN
slv24_reg_int(15 DOWNTO 8) <= reg_data_in(15 DOWNTO 8);
END IF;
slv24_reg_int(7 DOWNTO 5) <= (OTHERS => '0');
END IF;
END PROCESS slv24_r;
slv24_reg <= slv24_reg_int(15 DOWNTO 8) & "000" & slv24_reg_int(4 DOWNTO 0);
slv16_r : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
slv16_reg_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01100" AND int_be(0) = '1' THEN
slv16_reg_int <= reg_data_in(4 DOWNTO 0);
END IF;
END IF;
END PROCESS slv16_r;
slv16_reg <= slv16_reg_int;
slv32_r : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
slv32_reg_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01101" AND int_be(0) = '1' THEN
slv32_reg_int(4 DOWNTO 0) <= reg_data_in(4 DOWNTO 0);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01101" AND int_be(1) = '1' THEN
slv32_reg_int(15 DOWNTO 8) <= reg_data_in(15 DOWNTO 8);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01101" AND int_be(2) = '1' THEN
slv32_reg_int(23 DOWNTO 16) <= reg_data_in(23 DOWNTO 16);
END IF;
slv32_reg_int(7 DOWNTO 5) <= (OTHERS => '0');
END IF;
END PROCESS slv32_r;
slv32_reg <= slv32_reg_int(23 DOWNTO 8) & "000" & slv32_reg_int(4 DOWNTO 0);
long_add : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
longadd_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "00111" AND int_be(0) = '1' THEN
longadd_int <= reg_data_in(7 DOWNTO 0);
END IF;
END IF;
END PROCESS long_add;
mail_ie : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
mail_irqe <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01000" AND int_be(0) = '1' THEN
mail_irqe <= reg_data_in(7 DOWNTO 0);
END IF;
END IF;
END PROCESS mail_ie;
mail_ir : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
mail_irq_reg <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01001" AND int_be(0) = '1' THEN
IF reg_data_in(0) = '1' THEN
mail_irq_reg(0) <= '0';
END IF;
IF reg_data_in(1) = '1' THEN
mail_irq_reg(1) <= '0';
END IF;
IF reg_data_in(2) = '1' THEN
mail_irq_reg(2) <= '0';
END IF;
IF reg_data_in(3) = '1' THEN
mail_irq_reg(3) <= '0';
END IF;
IF reg_data_in(4) = '1' THEN
mail_irq_reg(4) <= '0';
END IF;
IF reg_data_in(5) = '1' THEN
mail_irq_reg(5) <= '0';
END IF;
IF reg_data_in(6) = '1' THEN
mail_irq_reg(6) <= '0';
END IF;
IF reg_data_in(7) = '1' THEN
mail_irq_reg(7) <= '0';
END IF;
ELSE
IF mail_irqe(0)= '1' AND mail_irq(0)= '1' THEN
mail_irq_reg(0) <= '1';
END IF;
IF mail_irqe(1)= '1' AND mail_irq(1)= '1' THEN
mail_irq_reg(1) <= '1';
END IF;
IF mail_irqe(2)= '1' AND mail_irq(2)= '1' THEN
mail_irq_reg(2) <= '1';
END IF;
IF mail_irqe(3)= '1' AND mail_irq(3)= '1' THEN
mail_irq_reg(3) <= '1';
END IF;
IF mail_irqe(4)= '1' AND mail_irq(4)= '1' THEN
mail_irq_reg(4) <= '1';
END IF;
IF mail_irqe(5)= '1' AND mail_irq(5)= '1' THEN
mail_irq_reg(5) <= '1';
END IF;
IF mail_irqe(6)= '1' AND mail_irq(6)= '1' THEN
mail_irq_reg(6) <= '1';
END IF;
IF mail_irqe(7)= '1' AND mail_irq(7)= '1' THEN
mail_irq_reg(7) <= '1';
END IF;
END IF;
END IF;
END PROCESS mail_ir;
mailbox_irq(0) <= '1' WHEN mail_irq_reg(0) = '1' OR mail_irq_reg(1) = '1' OR mail_irq_reg(2) = '1' OR mail_irq_reg(3) = '1' ELSE '0';
mailbox_irq(1) <= '1' WHEN mail_irq_reg(4) = '1' OR mail_irq_reg(5) = '1' OR mail_irq_reg(6) = '1' OR mail_irq_reg(7) = '1' ELSE '0';
-- clear address combination bits when clear status bit
clr_locmon(0) <= '1' WHEN write_flag = '1' AND int_adr(6 DOWNTO 2) = "01110" AND int_be(0) = '1' AND reg_data_in(3) = '1' ELSE '0';
clr_locmon(1) <= '1' WHEN write_flag = '1' AND int_adr(6 DOWNTO 2) = "01111" AND int_be(0) = '1' AND reg_data_in(3) = '1' ELSE '0';
loc_sta0 : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
locsta_0 <= (OTHERS => '0');
locmon_irq(0) <= '0';
loc_irq_0_q <= '0';
loc_sel_0_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
loc_irq_0_q <= loc_irq_0;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01110" AND int_be(0) = '1' THEN
locsta_0(5 DOWNTO 4) <= reg_data_in(5 DOWNTO 4);
locsta_0(2 DOWNTO 0) <= reg_data_in(2 DOWNTO 0);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01110" AND int_be(0) = '1' AND reg_data_in(3) = '1' THEN
locsta_0(3) <= '0';
loc_sel_0_int <= (OTHERS => '0');
ELSIF loc_irq_0 = '1' AND loc_irq_0_q = '0' THEN
locsta_0(3) <= '1';
loc_sel_0_int <= loc_sel;
END IF;
IF locsta_0(0) = '1' AND locsta_0(3) = '1' THEN
locmon_irq(0) <= '1';
ELSE
locmon_irq(0) <= '0';
END IF;
END IF;
END PROCESS loc_sta0;
loc_rw_0 <= locsta_0(5 DOWNTO 4);
loc_am_0 <= locsta_0(2 DOWNTO 1);
loc_sta1 : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
locsta_1 <= (OTHERS => '0');
locmon_irq(1) <= '0';
loc_irq_1_q <= '0';
loc_sel_1_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
loc_irq_1_q <= loc_irq_1;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01111" AND int_be(0) = '1' THEN
locsta_1(5 DOWNTO 4) <= reg_data_in(5 DOWNTO 4);
locsta_1(2 DOWNTO 0) <= reg_data_in(2 DOWNTO 0);
END IF;
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "01111" AND int_be(0) = '1' AND reg_data_in(3) = '1' THEN
locsta_1(3) <= '0';
loc_sel_1_int <= (OTHERS => '0');
ELSIF loc_irq_1 = '1' AND loc_irq_1_q = '0' THEN
locsta_1(3) <= '1';
loc_sel_1_int <= loc_sel;
END IF;
IF locsta_1(0) = '1' AND locsta_1(3) = '1' THEN
locmon_irq(1) <= '1';
ELSE
locmon_irq(1) <= '0';
END IF;
END IF;
END PROCESS loc_sta1;
loc_rw_1 <= locsta_1(5 DOWNTO 4);
loc_am_1 <= locsta_1(2 DOWNTO 1);
loc_adr0 : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
loc_adr_0_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10000" THEN
IF int_be(0) = '1' THEN
loc_adr_0_int(7 DOWNTO 0) <= reg_data_in(7 DOWNTO 0);
END IF;
IF int_be(1) = '1' THEN
loc_adr_0_int(15 DOWNTO 8) <= reg_data_in(15 DOWNTO 8);
END IF;
IF int_be(2) = '1' THEN
loc_adr_0_int(23 DOWNTO 16) <= reg_data_in(23 DOWNTO 16);
END IF;
IF int_be(3) = '1' THEN
loc_adr_0_int(31 DOWNTO 24) <= reg_data_in(31 DOWNTO 24);
END IF;
END IF;
END IF;
END PROCESS loc_adr0;
-- loc_adr_0 <= loc_adr_0_int(7 DOWNTO 0) & loc_adr_0_int(15 DOWNTO 8) & loc_adr_0_int(23 DOWNTO 16) & loc_adr_0_int(31 DOWNTO 24);
loc_adr_0 <= loc_adr_0_int;
loc_adr1 : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
loc_adr_1_int <= (OTHERS => '0');
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10001" THEN
IF int_be(0) = '1' THEN
loc_adr_1_int(7 DOWNTO 0) <= reg_data_in(7 DOWNTO 0);
END IF;
IF int_be(1) = '1' THEN
loc_adr_1_int(15 DOWNTO 8) <= reg_data_in(15 DOWNTO 8);
END IF;
IF int_be(2) = '1' THEN
loc_adr_1_int(23 DOWNTO 16) <= reg_data_in(23 DOWNTO 16);
END IF;
IF int_be(3) = '1' THEN
loc_adr_1_int(31 DOWNTO 24) <= reg_data_in(31 DOWNTO 24);
END IF;
END IF;
END IF;
END PROCESS loc_adr1;
-- loc_adr_1 <= loc_adr_1_int(7 DOWNTO 0) & loc_adr_1_int(15 DOWNTO 8) & loc_adr_1_int(23 DOWNTO 16) & loc_adr_1_int(31 DOWNTO 24);
loc_adr_1 <= loc_adr_1_int;
brl_pr : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
brl_int <= (OTHERS => '1'); -- default request level is 3 to be compatible to old implementations
ELSIF clk'EVENT AND clk = '1' THEN
IF write_flag = '1' AND int_adr(6 DOWNTO 2) = "10101" THEN
IF int_be(0) = '1' THEN
brl_int <= reg_data_in(1 DOWNTO 0);
END IF;
END IF;
END IF;
END PROCESS brl_pr;
brl <= brl_int;
END vme_du_arch;
|
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT_UNSIGNED package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type BIT_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the BIT_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package NUMERIC_BIT_UNSIGNED is
constant CopyRightNotice : STRING :=
"Copyright 2008 IEEE. All rights reserved.";
-- Id: A.3
function "+" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit bit_vector
-- Id: A.3L
function "+"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Id: A.39
function find_leftmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function "?>" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function "?>" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function "?>" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function "?<" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function "?<" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function "?<" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function "?<=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function "?<=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function "?<=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function "?>=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function "?>=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function "?>=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function "?=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function "?=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function "?=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function "?/=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function "?/=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function "?/=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : BIT_VECTOR; NEW_SIZE : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
function RESIZE (ARG, SIZE_RES : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : BIT_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.3
function To_BitVector (ARG, SIZE : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
function To_BitVector (ARG : NATURAL; SIZE_RES : BIT_VECTOR)
return BIT_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- begin LCS-2006-130
alias To_Bit_Vector is
To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
alias To_BV is
To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
alias To_Bit_Vector is
To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
alias To_BV is
To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
end package NUMERIC_BIT_UNSIGNED;
|
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT_UNSIGNED package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type BIT_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the BIT_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package NUMERIC_BIT_UNSIGNED is
constant CopyRightNotice : STRING :=
"Copyright 2008 IEEE. All rights reserved.";
-- Id: A.3
function "+" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit bit_vector
-- Id: A.3L
function "+"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Id: A.39
function find_leftmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function "?>" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function "?>" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function "?>" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function "?<" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function "?<" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function "?<" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function "?<=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function "?<=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function "?<=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function "?>=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function "?>=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function "?>=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function "?=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function "?=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function "?=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function "?/=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function "?/=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function "?/=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : BIT_VECTOR; NEW_SIZE : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
function RESIZE (ARG, SIZE_RES : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : BIT_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.3
function To_BitVector (ARG, SIZE : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
function To_BitVector (ARG : NATURAL; SIZE_RES : BIT_VECTOR)
return BIT_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- begin LCS-2006-130
alias To_Bit_Vector is
To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
alias To_BV is
To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
alias To_Bit_Vector is
To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
alias To_BV is
To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
end package NUMERIC_BIT_UNSIGNED;
|
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT_UNSIGNED package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type BIT_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the BIT_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package NUMERIC_BIT_UNSIGNED is
constant CopyRightNotice : STRING :=
"Copyright 2008 IEEE. All rights reserved.";
-- Id: A.3
function "+" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit bit_vector
-- Id: A.3L
function "+"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Id: A.39
function find_leftmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function "?>" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function "?>" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function "?>" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function "?<" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function "?<" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function "?<" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function "?<=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function "?<=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function "?<=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function "?>=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function "?>=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function "?>=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function "?=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function "?=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function "?=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function "?/=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function "?/=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function "?/=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : BIT_VECTOR; NEW_SIZE : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
function RESIZE (ARG, SIZE_RES : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : BIT_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.3
function To_BitVector (ARG, SIZE : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
function To_BitVector (ARG : NATURAL; SIZE_RES : BIT_VECTOR)
return BIT_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- begin LCS-2006-130
alias To_Bit_Vector is
To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
alias To_BV is
To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
alias To_Bit_Vector is
To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
alias To_BV is
To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
end package NUMERIC_BIT_UNSIGNED;
|
-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. This source file may not be
-- copied, sold, or included with software that is sold without written
-- permission from the IEEE Standards Department. This source file may be
-- copied for individual use between licensed users. This source file is
-- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR
-- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE
-- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify
-- and hold IEEE harmless from any damages or liability arising out of the
-- use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT_UNSIGNED package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type BIT_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the BIT_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package NUMERIC_BIT_UNSIGNED is
constant CopyRightNotice : STRING :=
"Copyright 2008 IEEE. All rights reserved.";
-- Id: A.3
function "+" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit bit_vector
-- Id: A.3L
function "+"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Id: A.39
function find_leftmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function "?>" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function "?>" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function "?>" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function "?<" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function "?<" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function "?<" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function "?<=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function "?<=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function "?<=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function "?>=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function "?>=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function "?>=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function "?=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function "?=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function "?=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function "?/=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function "?/=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function "?/=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : BIT_VECTOR; NEW_SIZE : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
function RESIZE (ARG, SIZE_RES : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : BIT_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.3
function To_BitVector (ARG, SIZE : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
function To_BitVector (ARG : NATURAL; SIZE_RES : BIT_VECTOR)
return BIT_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- begin LCS-2006-130
alias To_Bit_Vector is
To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
alias To_BV is
To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
alias To_Bit_Vector is
To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
alias To_BV is
To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
end package NUMERIC_BIT_UNSIGNED;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:29:38 11/03/2016
-- Design Name:
-- Module Name: /home/student1/Documents/Omega/CPU/Hardware/Omega/MemoryController_TB.vhd
-- Project Name: Omega
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MemoryController
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MemoryController_TB IS
END MemoryController_TB;
ARCHITECTURE behavior OF MemoryController_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MemoryController
PORT(
CLK : IN std_logic;
Address : IN std_logic_vector(31 downto 0);
Enable : IN std_logic;
ToWrite : IN std_logic_vector(31 downto 0);
FromRead : OUT std_logic_vector(31 downto 0);
Instruction : IN std_logic_vector(31 downto 0);
Reset : IN std_logic;
Done : OUT std_logic;
SRAM_addr : OUT std_logic_vector(20 downto 0);
SRAM_OE : OUT std_logic;
SRAM_CE : OUT std_logic;
SRAM_WE : OUT std_logic;
SRAM_data : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal Address : std_logic_vector(31 downto 0) := (others => '0');
signal Enable : std_logic := '0';
signal ToWrite : std_logic_vector(31 downto 0) := (others => '0');
signal Instruction : std_logic_vector(31 downto 0) := (others => '0');
signal Reset : std_logic := '0';
--BiDirs
signal SRAM_data : std_logic_vector(7 downto 0);
--Outputs
signal FromRead : std_logic_vector(31 downto 0);
signal Done : std_logic;
signal SRAM_addr : std_logic_vector(20 downto 0);
signal SRAM_OE : std_logic;
signal SRAM_CE : std_logic;
signal SRAM_WE : std_logic;
-- Clock period definitions
constant CLK_period : time := 31.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MemoryController PORT MAP (
CLK => CLK,
Address => Address,
Enable => Enable,
ToWrite => ToWrite,
FromRead => FromRead,
Instruction => Instruction,
Reset => Reset,
Done => Done,
SRAM_addr => SRAM_addr,
SRAM_OE => SRAM_OE,
SRAM_CE => SRAM_CE,
SRAM_WE => SRAM_WE,
SRAM_data => SRAM_data
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
data_proc: process
begin
sram_data <= (others => 'Z');
wait until falling_edge(SRAM_oe);
sram_data <= "00000000";
wait for 9 ns;
sram_data <= "01011010";
wait until SRAM_oe = '1';
end process data_proc;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait until SRAM_we = '1';
wait for CLK_period*10;
enable <= '1';
instruction <= "00010000000000000000000000000000";
address <= "00000000000000000000000000000100";
wait until done = '1';
enable <= '0';
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: mips_vram_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY mips_vram_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE mips_vram_synth_ARCH OF mips_vram_synth IS
COMPONENT mips_vram_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL WEB: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEB_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB: STD_LOGIC_VECTOR( 15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_R: STD_LOGIC_VECTOR( 15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_ENB_R : STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECK_DATA_TDP(0) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => CHECKER_ENB_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(1)
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(RSTB='1') THEN
CHECKER_ENB_R <= '0';
ELSE
CHECKER_ENB_R <= CHECK_DATA_TDP(1) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => CLKA,
CLKB => CLKB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
CHECK_DATA => CHECK_DATA_TDP
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
WEB_R <= (OTHERS=>'0') AFTER 50 ns;
DINB_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
WEB_R <= WEB AFTER 50 ns;
DINB_R <= DINB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: mips_vram_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB_R,
ADDRB => ADDRB_R,
DINB => DINB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
-- Title : tx_ctrl
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : tx_ctrl.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 09.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- this module controls all actions within the TxModule, including power
-- messages and information given by the init module
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- * tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.src_utils_pkg.all;
entity tx_ctrl is
port(
clk : in std_logic;
rst : in std_logic;
-- IP core
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
pme_to_cr : out std_logic;
-- FIFO
tx_c_head_empty : in std_logic;
tx_wr_head_empty : in std_logic;
tx_c_data_empty : in std_logic;
tx_wr_data_empty : in std_logic;
tx_c_head_enable : out std_logic;
tx_wr_head_enable : out std_logic;
tx_c_data_enable : out std_logic;
tx_wr_data_enable : out std_logic;
-- tx_put_data
aligned : in std_logic;
data_len : in std_logic_vector(9 downto 0);
wr_rd : in std_logic; -- 0: write, 1: read
posted : in std_logic; -- 0: non-posted, 1: posted
byte_count : in std_logic_vector(11 downto 0);
io_write : in std_logic; -- 0: no I/O write, 1: I/O write thus completion without data
orig_addr : in std_logic_vector(31 downto 0);
tx_tag_nbr : out std_logic_vector(7 downto 0);
get_header : out std_logic;
get_next_header : out std_logic;
make_header : out std_logic;
data_enable : out std_logic;
c_wrrd : out std_logic; -- =0: completion, =1: write or read
completer_id : out std_logic_vector(15 downto 0);
own_id : out std_logic_vector(15 downto 0);
abort_compl : out std_logic;
send_len : out std_logic_vector(9 downto 0); -- length of actual packet, stored to header
send_addr : out std_logic_vector(31 downto 0); -- address of actual packet, stored to header
payload_loop : out std_logic; -- =0: no loop, =1: loop
first_last_full : out std_logic_vector(1 downto 0); -- 00: unused, 01: first packet of payload_loop, 01: last
-- packet of payload_loop, 11: all enabled
-- tx_compl_timeout
start : out std_logic;
start_tag_nbr : out std_logic_vector(4 downto 0);
-- error
compl_abort : out std_logic;
-- init
bus_dev_func : in std_logic_vector(15 downto 0);
max_payload : in std_logic_vector(2 downto 0)
);
end entity tx_ctrl;
-- ****************************************************************************
architecture tx_ctrl_arch of tx_ctrl is
-- FSM state encoding ---------------------------------------------------------
type fsm_state is (
PREP_HEADER, IDLE, PREP_TRANS, START_TRANS, TRANSMIT, PME_OFF, TAG_START, ABORT, IO_WR
);
signal state : fsm_state;
-------------------------------------------------------------------------------
-- constants ------------------------------------------------------------------
constant ADDR_INCR : std_logic_vector(31 downto 0) := x"00000008";
-------------------------------------------------------------------------------
-- internal signals -----------------------------------------------------------
signal data_from_fifo : std_logic_vector(10 downto 0);
signal desired_len : std_logic_vector(10 downto 0);
signal data_to_ava : std_logic_vector(11 downto 0);
signal ready_q : std_logic;
signal wait_clk : integer range 3 downto 0 := 0;
signal pme_off_int : std_logic;
signal c_wr_int : std_logic;
signal tag_nbr_cntr : std_logic_vector(4 downto 0);
signal data_enable_int : std_logic;
signal fifo_enable_int : std_logic;
signal own_id_int : std_logic_vector(15 downto 0);
signal abort_compl_int : std_logic;
signal max_payload_len : std_logic_vector(9 downto 0);
signal payload_loop_en : std_logic;
signal addr_int : std_logic_vector(31 downto 0);
signal addr_offset : std_logic_vector(31 downto 0);
signal eop_int : std_logic;
signal get_last_packet : std_logic;
signal tx_st_valid0_int : std_logic;
signal send_len_int : std_logic_vector(9 downto 0);
signal arbit_access : std_logic_vector(1 downto 0); -- 00: invalid, 01: cpl, 10: wr/rd
-------------------------------------------------------------------------------
begin
-- unused signal, set to zero
tx_st_err0 <= '0';
-- decode max_payload
with max_payload select
max_payload_len <= "0001000000" when "001",
"0010000000" when "010",
"0100000000" when "011",
"1000000000" when "100",
"0000000000" when "101",
"0000100000" when others;
data_enable <= data_enable_int;
c_wrrd <= c_wr_int;
abort_compl <= abort_compl_int;
tx_st_valid0 <= tx_st_valid0_int;
send_len <= send_len_int;
-------------------------------------------------------------------------------
fsm_trans : process(rst, clk)
begin
if(rst = '1') then
state <= IDLE;
elsif(clk'event and clk = '1') then
case state is
when IDLE =>
if(arbit_access /= "00") then
state <= PREP_TRANS;
elsif(pme_off_int = '1') then
state <= PME_OFF;
else
state <= IDLE;
end if;
when PREP_HEADER =>
if(wait_clk = 3) then
state <= START_TRANS;
else
state <= PREP_HEADER;
end if;
when PREP_TRANS =>
if(wait_clk = 1 and c_wr_int = '1') then
state <= PREP_HEADER;
elsif(wait_clk = 2 and c_wr_int = '0') then
state <= PREP_HEADER;
else
state <= PREP_TRANS;
end if;
when START_TRANS =>
if(ready_q = '1') then
state <= TRANSMIT;
else
state <= START_TRANS;
end if;
when TRANSMIT =>
if(io_write = '1') then
state <= IO_WR;
elsif(data_to_ava <= TWO_12B and c_wr_int = '1' and wr_rd = '1') then
state <= TAG_START;
elsif(data_to_ava <= TWO_12B and c_wr_int = '0' and abort_compl_int = '1') then
state <= ABORT;
-- no loop on completion as read requests with length > max_payload_len are rejected
-- if looped write is finished (payload_loop_en = 0) go to IDLE as well
elsif(ready_q = '1' and (c_wr_int = '0' or (c_wr_int = '1' and wr_rd = '0' and payload_loop_en = '0')) and
((data_to_ava <= TWO_12B and ((aligned = '1' and send_len_int(0) = '0') or (aligned = '0' and send_len_int(0) = '1'))) or
(data_to_ava <= ONE_12B and ((aligned = '1' and send_len_int(0) = '1') or (aligned = '0' and send_len_int(0) = '0')))) ) then
state <= IDLE;
elsif(data_to_ava <= TWO_12B and c_wr_int = '1' and wr_rd = '0' and payload_loop_en = '1' and tx_st_valid0_int = '1') then
state <= PREP_HEADER;
else
state <= TRANSMIT;
end if;
when PME_OFF =>
state <= IDLE;
when TAG_START =>
-- transmission is done so process received power off request now
if(pme_off_int = '1' or pme_to_sr = '1') then
state <= PME_OFF;
elsif(payload_loop_en = '1') then
state <= PREP_HEADER;
else
state <= IDLE;
end if;
when ABORT =>
-- transmission is done so process received power off request now
if(pme_off_int = '1' or pme_to_sr = '1') then
state <= PME_OFF;
elsif(data_from_fifo <= TWO_11B) then
state <= IDLE;
else
state <= ABORT;
end if;
when IO_WR =>
-- transmission is done so process received power off request now
if(pme_off_int = '1' or pme_to_sr = '1') then
state <= PME_OFF;
else
state <= IDLE;
end if;
-- coverage off
when others =>
-- synthesis translate_off
report "undecoded state in ctrl_fsm" severity error;
-- synthesis translate_on
-- coverage on
end case;
end if;
end process fsm_trans;
-------------------------------------------------------------------------------
fsm_out : process(rst, clk)
begin
if(rst = '1') then
tx_st_valid0_int <= '0';
tx_st_sop0 <= '0';
tx_st_eop0 <= '0';
pme_to_cr <= '0';
tx_c_head_enable <= '0';
tx_wr_head_enable <= '0';
tx_c_data_enable <= '0';
tx_wr_data_enable <= '0';
tx_tag_nbr <= (others => '0');
get_header <= '0';
get_next_header <= '0';
make_header <= '0';
data_enable_int <= '0';
c_wr_int <= '0';
completer_id <= (others => '0');
own_id <= (others => '0');
abort_compl_int <= '0';
send_len_int <= (others => '0');
send_addr <= (others => '0');
payload_loop <= '0';
first_last_full <= (others => '0');
start <= '0';
start_tag_nbr <= (others => '0');
compl_abort <= '0';
data_from_fifo <= (others => '0');
desired_len <= (others => '0');
data_to_ava <= (others => '0');
ready_q <= '0';
wait_clk <= 0;
pme_off_int <= '0';
tag_nbr_cntr <= (others => '0');
fifo_enable_int <= '0';
own_id_int <= (others => '0');
payload_loop_en <= '0';
addr_int <= (others => '0');
addr_offset <= (others => '0');
eop_int <= '0';
get_last_packet <= '0';
arbit_access <= (others => '0');
elsif(clk'event and clk = '1') then
if(state = IDLE and tx_c_head_empty = '0') then
arbit_access <= "01";
elsif(state = IDLE and tx_wr_head_empty = '0') then
arbit_access <= "10";
elsif(state /= IDLE) then
arbit_access <= (others => '0');
end if;
if(state = TRANSMIT and tx_st_ready0 = '0' and data_from_fifo <= FOUR_12B and data_from_fifo > ZERO_12B and get_last_packet = '0') then
get_last_packet <= '1';
elsif(state = IDLE or (state = TRANSMIT and tx_st_ready0 = '1' and get_last_packet = '1')) then
get_last_packet <= '0';
end if;
if(state = TRANSMIT and data_to_ava >= THREE_12B and ready_q = '0') then
eop_int <= '1';
elsif(state = IDLE or state = PREP_HEADER or state = ABORT or state = TAG_START or state = IO_WR
or (state = TRANSMIT and tx_st_ready0 = '1' and ready_q = '1')
) then
eop_int <= '0';
end if;
-- release transfer when there is no more data to send
if(state = IDLE or state = PREP_HEADER or state = ABORT or state = IO_WR or state = TAG_START or
(state = TRANSMIT and ((data_to_ava <= TWO_12B and eop_int = '0') or ready_q = '0')) or
(state = START_TRANS and ready_q = '0')) then
tx_st_valid0_int <= '0';
-- assert tx_st_valid0 after correct ReadyLatency, in this case ReadyLatency = 2
elsif((state = START_TRANS and ready_q = '1') or (state = TRANSMIT and ready_q = '1')
) then
tx_st_valid0_int <= '1';
end if;
-- assert tx_st_sop0 after correct ReadyLatency, in this case ReadyLatency = 2
if(state = START_TRANS and ready_q = '1') then
tx_st_sop0 <= '1';
elsif((state = START_TRANS and ready_q = '0') or state = TRANSMIT) then
tx_st_sop0 <= '0';
end if;
if(state = IDLE or state = PREP_HEADER or state = TAG_START or state = ABORT or state = IO_WR or (state = TRANSMIT and
(data_to_ava > FOUR_12B or (data_to_ava <= TWO_12B and eop_int = '0')) and io_write = '0')) then
tx_st_eop0 <= '0';
-- set end of packet according to actual transfer length
elsif(state = TRANSMIT and ready_q = '1' and ((wr_rd = '1' and data_to_ava = THREE_12B) or
(data_to_ava = FOUR_12B and eop_int = '0' and ((aligned = '1' and send_len_int(0) = '0') or (aligned = '0' and send_len_int(0) = '1'))) or
(data_to_ava = THREE_12B and eop_int = '0' and ((aligned = '1' and send_len_int(0) = '1') or (aligned = '0' and send_len_int(0) = '0'))) or
io_write = '1' or (eop_int = '1' and data_to_ava <= TWO_12B) or (abort_compl_int = '1' and data_to_ava <= FOUR_12B))) then
tx_st_eop0 <= '1';
end if;
-- enable FIFO for corresponding type of transaction chosen before
if((state = IDLE and tx_c_head_empty = '0' and arbit_access = "01") or (state = PREP_TRANS and wait_clk = 1 and tx_c_head_empty = '0' and c_wr_int = '0')) then
tx_c_head_enable <= '1';
elsif(state = PREP_TRANS and (wait_clk /= 1 or tx_c_head_empty = '1' or c_wr_int = '1')) then
tx_c_head_enable <= '0';
end if;
-- enable FIFO for corresponding type of transaction chosen before
if(state = IDLE and tx_wr_head_empty = '0' and arbit_access = "10") then
tx_wr_head_enable <= '1';
-- enable correct header FIFO
elsif(state = PREP_TRANS and (wait_clk /= 1 or tx_c_head_empty = '1' or c_wr_int = '1')) then
tx_wr_head_enable <= '0';
end if;
-- enable appropriate FIFO
if((state = PREP_HEADER and wait_clk = 0 and c_wr_int = '0' and abort_compl_int = '0') or
(state = START_TRANS and tx_st_ready0 = '1' and c_wr_int = '0' and data_from_fifo > ZERO_11B and abort_compl_int = '0') or
(state = ABORT and data_from_fifo > TWO_11B) or
(state = TRANSMIT and tx_st_ready0 = '1' and c_wr_int = '0' and ((data_from_fifo > TWO_11B and data_to_ava > THREE_12B) or (get_last_packet = '1' and data_from_fifo > ZERO_12B)))
) then
tx_c_data_enable <= '1';
elsif((state = PREP_HEADER and wait_clk = 1 and c_wr_int = '0' and abort_compl_int = '0') or
(state = START_TRANS and c_wr_int = '0' and ((tx_st_ready0 = '0' and data_from_fifo = ONE_11B) or
(ready_q = '1' and data_from_fifo <= ONE_11B))) or
(state = TRANSMIT and ((data_from_fifo <= TWO_11B and c_wr_int = '0') or (tx_st_ready0 = '0'))) or -- reset FIFO enable when hard IP
-- core isn't able to receive data
(state = ABORT and data_from_fifo <= TWO_11B) -- disble data retrieval from FIFO due to end of transmission
) then
tx_c_data_enable <= '0';
end if;
if((state = PREP_HEADER and wait_clk = 1 and c_wr_int = '1' and wr_rd = '0') or
(state = START_TRANS and tx_st_ready0 = '1' and c_wr_int = '1' and wr_rd = '0' and data_from_fifo > ZERO_11B and fifo_enable_int = '0') or
(state = TRANSMIT and tx_st_ready0 = '1' and c_wr_int = '1' and wr_rd = '0' and ((data_from_fifo > TWO_11B and data_to_ava > THREE_12B) or (get_last_packet = '1' and data_from_fifo > ZERO_12B)))
) then
tx_wr_data_enable <= '1';
elsif((state = PREP_HEADER and wait_clk = 2 and c_wr_int = '1' and wr_rd = '0') or
(state = START_TRANS and c_wr_int = '1' and ((fifo_enable_int = '1' and ((send_len_int(0) = '1' and data_from_fifo = ONE_11B) or
(send_len_int(0) = '0' and data_from_fifo = TWO_11B))) or (tx_st_ready0 = '0' and data_from_fifo = ONE_11B))) or
(state = TRANSMIT and ((data_from_fifo <= TWO_11B and c_wr_int = '1') or (tx_st_ready0 = '0'))) -- reset FIFO enable when hard IP
-- core isn't able to receive data
) then
tx_wr_data_enable <= '0';
end if;
-- calculate tag ID
if(state = PREP_HEADER and c_wr_int = '1' and (wr_rd = '1' or (wr_rd = '0' and posted = '0'))) then
tx_tag_nbr <= "000" & tag_nbr_cntr;
elsif(state = PREP_HEADER and c_wr_int = '1' and wr_rd = '0' and posted = '1') then
tx_tag_nbr <= "00100000";
end if;
-- tell tx_put_data module to process header information
if(state = PREP_TRANS and wait_clk = 0) then
get_header <= '1';
elsif(state = PREP_HEADER or (state = PREP_TRANS and wait_clk = 1)) then
get_header <= '0';
end if;
-- completion information is stored to the FIFO using more than one header packet, thus get next header too
if(state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0') then
get_next_header <= '1';
elsif(state = PREP_HEADER) then
get_next_header <= '0';
end if;
-- advise tx_put_data module to process header information and to route that onto Avalon ST data bus
if(state = PREP_HEADER and ((c_wr_int = '0' and wait_clk = 0) or (c_wr_int = '1' and wait_clk = 1))) then
make_header <= '1';
elsif(state = PREP_HEADER and ((c_wr_int = '0' and wait_clk = 1) or (c_wr_int = '1' and wait_clk = 2))) then
make_header <= '0';
end if;
if((state = IDLE or state = ABORT or (state = START_TRANS and ready_q = '0')) or
(state = TRANSMIT and (ready_q = '0' or data_to_ava <= ZERO_12B)) or
(state = PREP_HEADER and (wait_clk = 0 or (wait_clk = 2 and c_wr_int = '0') or (wait_clk = 3 and c_wr_int = '1')))
) then
data_enable_int <= '0';
elsif((state = PREP_HEADER and ((wait_clk = 1 and c_wr_int = '0') or (wait_clk = 2 and c_wr_int = '1'))) or
(state = START_TRANS and ready_q = '1') or -- enable data processing when hard IP is ready to process data
(state = TRANSMIT and ready_q = '1' and data_to_ava > ZERO_12B) -- enable data processing as long as the data length counter isn't 0
) then
data_enable_int <= '1';
end if;
-- start transaction with priority on completions, don't change in any other state except IDLE
if(state = IDLE and arbit_access = "01") then
c_wr_int <= '0';
elsif(state = IDLE and arbit_access = "10") then
c_wr_int <= '1';
end if;
-- give actual own bus/dev/func number (=own_id_int) to tx_put_data module either for completion transmission
if(state = PREP_TRANS and c_wr_int = '0') then
completer_id <= own_id_int;
end if;
-- give actual own bus/dev/func number (=own_id_int) to tx_put_data module either for write/read transmission
if(state = PREP_TRANS and c_wr_int = '1') then
own_id <= own_id_int;
end if;
if(state = IDLE or state = ABORT) then
abort_compl_int <= '0';
-- if byte_count is greater than allowed (greater than max_payload) reject transmission, send completion without data
-- with completer abort status and signal error to error module which will signal error to hard IP by asserting cpl_err(2)
-- for 1 clock cycle
elsif(state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and tx_c_head_empty = '0' and ((data_len = ZERO_10B and
max_payload_len /= ZERO_10B) or (data_len /= ZERO_10B and data_len > max_payload_len))) then
abort_compl_int <= '1';
end if;
if(state = IDLE) then
send_len_int <= (others => '0');
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0') or (state = PREP_HEADER and wait_clk = 1 and c_wr_int = '1' and
wr_rd = '1')) then
send_len_int <= data_len;
-- store transmission length
elsif(state = PREP_HEADER and wait_clk = 1 and c_wr_int = '1' and wr_rd = '0') then
send_len_int <= data_from_fifo(9 downto 0);
end if;
if(state = IDLE) then
send_addr <= (others => '0');
-- show right address to tx_put_data module
elsif(state = PREP_HEADER and wait_clk = 1) then
send_addr <= addr_int;
end if;
if(state = IDLE) then
payload_loop <= '0';
-- if packet length is greater than allowed payload size, set payload_loop_en = 1 and do internal loop until desired
-- packet length is sent using multiple TLPs; don't forget to adapt packet address after each loop
elsif(state = PREP_HEADER and desired_len = ZERO_11B and c_wr_int = '1' and wr_rd = '0' and wait_clk = 0 and
((data_len = ZERO_10B and data_len /= max_payload_len) or (data_len /= ZERO_10B and data_len > max_payload_len))) then
payload_loop <= '1';
end if;
if(state = IDLE) then
first_last_full <= (others => '0');
-- advise tx_put_data module how to process first/last byte enables
elsif(state = PREP_HEADER and desired_len = ZERO_11B and c_wr_int = '1' and wr_rd = '0' and wait_clk = 0 and
((data_len = ZERO_10B and data_len /= max_payload_len) or (data_len /= ZERO_10B and data_len > max_payload_len))) then
first_last_full <= "01";
elsif(state = PREP_HEADER and c_wr_int = '1' and wr_rd = '0' and wait_clk = 1 and desired_len <= data_from_fifo) then
first_last_full <= "10";
elsif(state = START_TRANS) then
first_last_full <= "11";
end if;
if(state = IDLE or state = ABORT) then
compl_abort <= '0';
-- assert completion abort indicator
elsif(state = TRANSMIT and data_to_ava <= TWO_12B and c_wr_int = '0' and abort_compl_int = '1') then
compl_abort <= '1';
end if;
-- calculate length counter for data that has to be taken from appropriate FIFO
if((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and data_len = ZERO_10B) or
(state = PREP_HEADER and wait_clk = 0 and data_len = ZERO_10B and ((desired_len /= ZERO_11B and c_wr_int = '0') or (desired_len = ZERO_11B and
(c_wr_int = '0' or (c_wr_int = '1' and data_len = max_payload_len)))))
) then
data_from_fifo <= '1' & data_len;
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and data_len > ZERO_10B) or
(state = PREP_HEADER and wait_clk = 0 and data_len /= ZERO_10B and ((desired_len /= ZERO_11B and c_wr_int = '0') or (desired_len = ZERO_11B
and (c_wr_int = '0' or (c_wr_int = '1' and (max_payload_len = ZERO_10B or data_len <= max_payload_len))))))
) then
data_from_fifo <= '0' & data_len;
elsif(state = PREP_HEADER and wait_clk = 0 and c_wr_int = '1' and ((desired_len = ZERO_11B and ((data_len = ZERO_10B and data_len /= max_payload_len) or
(data_len /= ZERO_10B and data_len > max_payload_len))) or (desired_len /= ZERO_11B and ((desired_len = X_400_11B and
desired_len(9 downto 0) /= max_payload_len) or (desired_len < X_400_11B and desired_len(9 downto 0) > max_payload_len))))
)then
data_from_fifo <= '0' & max_payload_len;
elsif(state = PREP_HEADER and desired_len /= ZERO_11B and wait_clk = 0 and c_wr_int = '1' and desired_len = X_400_11B and desired_len(9 downto 0) = max_payload_len) then
data_from_fifo <= desired_len;
elsif(state = PREP_HEADER and desired_len /= ZERO_11B and wait_clk = 0 and c_wr_int = '1' and ((desired_len < X_400_11B and max_payload_len = ZERO_10B) or (desired_len < X_400_11B
and desired_len(9 downto 0) <= max_payload_len)))then
data_from_fifo <= '0' & desired_len(9 downto 0);
elsif((state = PREP_HEADER and ((wait_clk = 1 and c_wr_int = '0' and abort_compl_int = '0' and data_from_fifo > ONE_11B) or
(wait_clk = 2 and c_wr_int = '1' and wr_rd = '0' and data_from_fifo > ONE_11B))) or
(fifo_enable_int = '1' and ((state = TRANSMIT and data_from_fifo > ONE_11B and abort_compl_int = '0') or (state = ABORT and abort_compl_int = '0') or (state = START_TRANS and data_from_fifo > ONE_11B)))
)then
data_from_fifo <= data_from_fifo - TWO_11B;
elsif((state = PREP_HEADER and data_from_fifo <= ONE_11B and ((wait_clk = 1 and c_wr_int = '0' and abort_compl_int = '0') or
(wait_clk = 2 and c_wr_int = '1' and wr_rd = '0'))) or
(state = START_TRANS and fifo_enable_int = '1' and data_from_fifo = ONE_11B) or
(fifo_enable_int = '1' and state = TRANSMIT and data_from_fifo <= ONE_11B)
)then
data_from_fifo <= (others => '0');
end if;
-- as this is a loop, change desired_len only when entering this state for the very first time
-- on other entry times only subtract data_from_fifo value
-- new value for data_from_fifo is valid when wait_clk = 1
if(state = PREP_HEADER and desired_len = ZERO_11B and c_wr_int = '1' and wr_rd = '0' and wait_clk = 0 and data_len = ZERO_10B) then
desired_len <= '1' & data_len;
elsif(state = PREP_HEADER and desired_len = ZERO_11B and c_wr_int = '1' and wr_rd = '0' and wait_clk = 0 and data_len /= ZERO_10B) then
desired_len <= '0' & data_len;
elsif(state = PREP_HEADER and c_wr_int = '1' and wr_rd = '0' and wait_clk = 1 and desired_len >= data_from_fifo) then
desired_len <= desired_len - data_from_fifo;
elsif(state = PREP_HEADER and c_wr_int = '1' and (wr_rd = '1' or (wr_rd = '0' and wait_clk = 1 and desired_len < data_from_fifo))) then
desired_len <= (others => '0');
end if;
-- in actual design, completion data is returned using one completion only
-- reads that request more data than max_payload_size (max_read ignored by PCIe requester) are rejected thus use original data length here
-- check bit 2 for address alignment (=0: aligned, =1: not aligned) thus wait until addr_int is set (wait_clk = 1)
-- decrement length counters for amount of data taken from FIFO and amount of data sent to hard IP core
if((state = PREP_TRANS and wait_clk = 2 and ((c_wr_int = '0' and abort_compl_int = '1') or (c_wr_int = '1' and wr_rd = '1'))) or
(state = PREP_HEADER and ((c_wr_int = '1' and wait_clk = 1 and wr_rd = '1') or (abort_compl_int = '1' and wait_clk < 2)))) then
data_to_ava <= THREE_12B;
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and abort_compl_int = '0' and aligned = '1' and data_len = ZERO_10B) or
(state = PREP_HEADER and c_wr_int = '0' and wait_clk = 0 and aligned = '1' and data_len = ZERO_10B)) then
data_to_ava <= ("01" & data_len) + FOUR_12B;
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and abort_compl_int = '0' and aligned = '0' and data_len = ZERO_10B) or
(state = PREP_HEADER and c_wr_int = '0' and wait_clk = 0 and aligned = '0' and data_len = ZERO_10B)) then
data_to_ava <= ("01" & data_len) + THREE_12B;
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and abort_compl_int = '0' and aligned = '1' and data_len /= ZERO_10B) or
(state = PREP_HEADER and c_wr_int = '0' and wait_clk = 0 and aligned = '1' and data_len /= ZERO_10B)) then
data_to_ava <= ("00" & data_len) + FOUR_12B;
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and abort_compl_int = '0' and aligned = '0' and data_len /= ZERO_10B) or
(state = PREP_HEADER and c_wr_int = '0' and wait_clk = 0 and aligned = '0' and data_len /= ZERO_10B)) then
data_to_ava <= ("00" & data_len) + THREE_12B;
elsif(state = PREP_HEADER and c_wr_int = '1' and wait_clk = 1 and addr_int(2) = '0') then
data_to_ava <= ('0' & data_from_fifo) + FOUR_12B;
elsif(state = PREP_HEADER and c_wr_int = '1' and wait_clk = 1 and addr_int(2) = '1') then
data_to_ava <= ('0' & data_from_fifo) + THREE_12B;
elsif(state = TRANSMIT and data_to_ava > ONE_12B and tx_st_valid0_int = '1') then
data_to_ava <= data_to_ava - "10";
elsif((state = START_TRANS and data_enable_int = '1' and data_to_ava = 1) or (state = TRANSMIT and data_enable_int = '1' and data_to_ava <= ONE_12B)) then
data_to_ava <= (others => '0');
end if;
if(state = IDLE or state = PREP_HEADER or (tx_st_ready0 = '0' and (state = TRANSMIT or state = START_TRANS))) then
ready_q <= '0';
elsif(tx_st_ready0 = '1' and (state = TRANSMIT or state = START_TRANS)) then
ready_q <= '1';
end if;
-- use wait_clk to enable processing at the right point of time
if(state = IDLE or (state = PREP_TRANS and ((wait_clk = 2 and c_wr_int = '0') or (wait_clk = 1 and c_wr_int = '1'))) or
(state = PREP_HEADER and wait_clk = 3)) then
wait_clk <= 0;
elsif((state = PREP_TRANS and (c_wr_int = '1' or (c_wr_int = '0' and tx_c_head_empty = '0'))) or
(state = PREP_HEADER and wait_clk /= 3)) then
wait_clk <= wait_clk + 1;
end if;
-- if power off request occured, save it for later processing
if(pme_to_sr = '1' and (state = IDLE or state = PREP_TRANS or state = PREP_HEADER or state = START_TRANS or state = TRANSMIT
or state = TAG_START or state = ABORT)) then
pme_off_int <= '1';
elsif(state = PME_OFF or (state = IDLE and pme_to_sr = '0')) then
pme_off_int <= '0';
end if;
-- disable or enable data retrieval from FIFO
if(state = IDLE or
(state = ABORT and data_from_fifo <= 2) or
(state = PREP_HEADER and ((wait_clk = 1 and c_wr_int = '0' and abort_compl_int = '0') or (wait_clk = 2 and c_wr_int = '1' and
wr_rd = '0'))) or
(state = START_TRANS and ((tx_st_ready0 = '0' and data_from_fifo = ONE_11B) or
(ready_q = '1' and c_wr_int = '0' and data_from_fifo <= 1) or
(c_wr_int = '1' and fifo_enable_int = '1' and ((data_len(0) = '1' and data_from_fifo = ONE_11B) or (data_len(0) = '0' and
data_from_fifo = TWO_11B))))) or
(state = TRANSMIT and (tx_st_ready0 = '0' or (data_from_fifo <= TWO_11B and get_last_packet = '0')))) then
fifo_enable_int <= '0';
elsif((state = START_TRANS and tx_st_ready0 = '1' and data_from_fifo > ZERO_11B and (c_wr_int = '1' or (c_wr_int = '0' and
abort_compl_int = '0'))) or (state = ABORT and data_from_fifo > TWO_11B) or
(state = PREP_HEADER and ((wait_clk = 0 and c_wr_int = '0' and abort_compl_int = '0') or (wait_clk = 1 and c_wr_int = '1' and
wr_rd = '0'))) or
(state = TRANSMIT and tx_st_ready0 = '1') ) then
fifo_enable_int <= '1';
end if;
-- if packet length is greater than allowed payload size, set payload_loop_en = 1 and do internal loop until desired
-- packet length is sent using multiple TLPs
-- don't forget to adapt packet address after each loop
if(state = IDLE or
(state = PREP_HEADER and c_wr_int = '1' and wr_rd = '0' and desired_len > 0 and wait_clk = 1 and desired_len <= data_from_fifo)) then
payload_loop_en <= '0';
elsif(state = PREP_HEADER and desired_len = 0 and c_wr_int = '1' and wr_rd = '0' and wait_clk = 0 and
((data_len = ZERO_10B and data_len /= max_payload_len) or (data_len /= ZERO_10B and data_len > max_payload_len))) then
payload_loop_en <= '1';
end if;
if(state = IDLE) then
addr_int <= (others => '0');
-- calculate internal address used if transaction must be split into more parts
elsif(state = PREP_HEADER and wait_clk = 0) then
addr_int <= orig_addr + addr_offset;
end if;
-- calculate address offset for internal address calculation
if(state = IDLE) then
addr_offset <= (others => '0');
elsif((state = PREP_HEADER and wait_clk = 2 and c_wr_int = '1' and wr_rd = '0') or
(state = START_TRANS and fifo_enable_int = '1' and c_wr_int = '1') or
(state = TRANSMIT and fifo_enable_int = '1' and c_wr_int = '1' and data_from_fifo > ZERO_12B)) then
addr_offset <= addr_offset + ADDR_INCR;
end if;
case state is
when IDLE =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
own_id_int <= bus_dev_func;
when PREP_HEADER =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
when PREP_TRANS =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
when START_TRANS =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
when TRANSMIT =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
when PME_OFF =>
pme_to_cr <= '1';
start <= '0';
start_tag_nbr <= (others => '0');
when TAG_START =>
pme_to_cr <= '0';
start <= '1';
start_tag_nbr <= tag_nbr_cntr;
tag_nbr_cntr <= tag_nbr_cntr + '1';
when ABORT =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
when others =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
end case;
end if;
end process fsm_out;
-------------------------------------------------------------------------------
end architecture tx_ctrl_arch;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity madd_seq_inferred is
generic (
latency : positive := 1;
src1_bits : natural := 32;
src2_bits : natural := 32
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
en : in std_ulogic;
unsgnd : in std_ulogic;
sub : in std_ulogic;
acc : in std_ulogic_vector(src1_bits+src2_bits-1 downto 0);
src1 : in std_ulogic_vector(src1_bits-1 downto 0);
src2 : in std_ulogic_vector(src1_bits-1 downto 0);
valid : out std_ulogic;
result : out std_ulogic_vector(src1_bits+src2_bits-1 downto 0);
overflow : out std_ulogic
);
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
package Display_Management_pkg is --============================================================================
constant nbits_pixel : natural := 12;
type format_type is record
--------------------------------------------------------------
-- Based from VESA Monitor Timing Standard version 1 Rev. 13
--------------------------------------------------------------
Hor_Pixels : natural; -- Pixels
Ver_Pixels : natural; -- Lines
Hor_Frequency : natural; -- kHz
Ver_Frequency : natural; -- Hz
Pixel_Clock : natural; -- MHz
Character_Width : natural; -- Pixels
Scan_Type : boolean;
Hor_Sync_Polarity : boolean;
Ver_Sync_Polarity : boolean;
Hor_Total_Time : natural; -- Pixels
Hor_Addr_Time : natural; -- Pixels
Hor_Blank_Start : natural; -- Pixels
Hor_Blank_Time : natural; -- Pixels
Hor_Sync_Start : natural; -- Pixels
-- Pixels
H_Right_Border : natural; -- Pixels
H_Front_Porch : natural; -- Pixels
H_Sync_Time : natural; -- Pixels
H_Back_Porch : natural; -- Pixels
H_Left_Border : natural; -- Pixels
Ver_Total_Time : natural; -- Lines
Ver_Addr_Time : natural; -- Lines
Ver_Blank_Start : natural; -- Lines
Ver_Blank_Time : natural; -- Lines
Ver_Sync_Start : natural; -- Lines
-- Lines
V_Bottom_Border : natural; -- Lines
V_Front_Porch : natural; -- Lines
V_Sync_Time : natural; -- Lines
V_Back_Porch : natural; -- Lines
V_Top_Border : natural; -- Lines
end record;
type timing_type is record
Hsync_Start : unsigned((nbits_pixel-1) downto 0); -- Pixels
Hsync_End : unsigned((nbits_pixel-1) downto 0); -- Pixels
H_Active_Video_Start : unsigned((nbits_pixel-1) downto 0); -- Pixels
H_Addressable_Video_Start : unsigned((nbits_pixel-1) downto 0); -- Pixels
H_Addressable_Video_End : unsigned((nbits_pixel-1) downto 0); -- Pixels
H_Active_Video_End : unsigned((nbits_pixel-1) downto 0); -- Pixels
Vsync_Start : unsigned((nbits_pixel-1) downto 0); -- Lines
Vsync_End : unsigned((nbits_pixel-1) downto 0); -- Lines
V_Active_Video_Start : unsigned((nbits_pixel-1) downto 0); -- Lines
V_Addressable_Video_Start : unsigned((nbits_pixel-1) downto 0); -- Lines
V_Addressable_Video_End : unsigned((nbits_pixel-1) downto 0); -- Lines
V_Active_Video_End : unsigned((nbits_pixel-1) downto 0); -- Lines
end record;
type pixel_type is record
x : unsigned((nbits_pixel-1) downto 0);
y : unsigned((nbits_pixel-1) downto 0);
end record;
type area_type is record
addressable_area : std_logic;
H_Active_Video : std_logic;
H_Addressable_Video : std_logic;
V_Active_Video : std_logic;
V_Addressable_Video : std_logic;
end record;
type color_type is record
red : std_logic_vector(3 downto 0);
green : std_logic_vector(3 downto 0);
blue : std_logic_vector(3 downto 0);
end record;
type vga_type is record
red : std_logic_vector(3 downto 0);
green : std_logic_vector(3 downto 0);
blue : std_logic_vector(3 downto 0);
H_sync : std_logic;
V_sync : std_logic;
end record;
type internal_video_type is record
red : std_logic_vector(3 downto 0);
green : std_logic_vector(3 downto 0);
blue : std_logic_vector(3 downto 0);
H_sync : std_logic;
V_sync : std_logic;
addressable_area : std_logic;
end record;
type full_video_type is record
format : format_type;
color : color_type;
pixel : pixel_type;
area : area_type;
vga : vga_type;
end record;
-- Deferred Constant
---- internal
constant SYNC_POSITIVE : boolean;
constant SYNC_NEGATIVE : boolean;
constant NONINTERLACED : boolean;
constant INTERLACED : boolean;
---- For video
constant timing_1920x1080x60Hz : format_type;
constant timing_1920x1080x60Hz_debug : format_type;
constant timing_1600x900x60Hz : format_type;
constant timing_1600x900x60Hz_debug : format_type;
-- Type definitions
function init_constant(Condition: boolean; Enable_Debug,Disable_Debug : natural) return natural;
function init_video_type(Condition: boolean; format_video : string) return format_type;
function init_timing_type(input_format_video : format_type) return timing_type;
end package Display_Management_pkg; --==================================================================================
package body Display_Management_pkg is --=====================================================
--============= Deferred Constant ===============================
constant SYNC_POSITIVE : boolean := true;
constant SYNC_NEGATIVE : boolean := false;
constant NONINTERLACED : boolean := false;
constant INTERLACED : boolean := true;
constant timing_1920x1080x60Hz : format_type :=(
--------------------------------------------------------------
-- Based from VESA Monitor Timing Standard version 1 Rev. 13
--------------------------------------------------------------
Hor_Pixels =>1920, -- Pixels
Ver_Pixels =>1080, -- Lines
Hor_Frequency =>67, -- kHz
Ver_Frequency =>60, -- Hz
Pixel_Clock =>148, -- MHz
Character_Width =>4, -- Pixels
Scan_Type =>NONINTERLACED,
Hor_Sync_Polarity =>SYNC_POSITIVE,
Ver_Sync_Polarity =>SYNC_POSITIVE,
Hor_Total_Time =>2200, -- Pixels
Hor_Addr_Time =>1920, -- Pixels
Hor_Blank_Start =>1920, -- Pixels
Hor_Blank_Time =>280, -- Pixels
Hor_Sync_Start =>2008, -- Pixels
H_Right_Border =>0, -- Pixels
H_Front_Porch =>88, -- Pixels
H_Sync_Time =>44, -- Pixels
H_Back_Porch =>148, -- Pixels
H_Left_Border =>0, -- Pixels
Ver_Total_Time =>1125, -- Lines
Ver_Addr_Time =>1080, -- Lines
Ver_Blank_Start =>1080, -- Lines
Ver_Blank_Time =>45, -- Lines
Ver_Sync_Start =>1084, -- Lines
V_Bottom_Border =>0, -- Lines
V_Front_Porch =>4, -- Lines
V_Sync_Time =>5, -- Lines
V_Back_Porch =>36, -- Lines
V_Top_Border =>0 -- Lines
--------------------------------------------------------------
);
constant timing_1920x1080x60Hz_debug : format_type :=(
--------------------------------------------------------------
-- Based from VESA Monitor Timing Standard version 1 Rev. 13
--------------------------------------------------------------
Hor_Pixels =>25, -- Pixels
Ver_Pixels =>32, -- Lines
Hor_Frequency =>0, -- kHz
Ver_Frequency =>0, -- Hz
Pixel_Clock =>0, -- MHz
Character_Width =>4, -- Pixels
Scan_Type =>NONINTERLACED,
Hor_Sync_Polarity =>SYNC_POSITIVE,
Ver_Sync_Polarity =>SYNC_POSITIVE,
Hor_Total_Time =>30, -- Pixels
Hor_Addr_Time =>20, -- Pixels
Hor_Blank_Start =>20, -- Pixels
Hor_Blank_Time =>10, -- Pixels
Hor_Sync_Start =>23, -- Pixels
H_Right_Border =>0, -- Pixels
H_Front_Porch =>3, -- Pixels
H_Sync_Time =>2, -- Pixels
H_Back_Porch =>5, -- Pixels
H_Left_Border =>0, -- Pixels
Ver_Total_Time =>40, -- Lines
Ver_Addr_Time =>32, -- Lines
Ver_Blank_Start =>32, -- Lines
Ver_Blank_Time =>10, -- Lines
Ver_Sync_Start =>18, -- Lines
V_Bottom_Border =>0, -- Lines
V_Front_Porch =>3, -- Lines
V_Sync_Time =>2, -- Lines
V_Back_Porch =>5, -- Lines
V_Top_Border =>0 -- Lines
);
constant timing_1600x900x60Hz : format_type :=(
--------------------------------------------------------------
-- Based from VESA Monitor Timing Standard version 1 Rev. 13
--------------------------------------------------------------
Hor_Pixels =>1600, -- Pixels
Ver_Pixels =>900, -- Lines
Hor_Frequency =>60, -- kHz
Ver_Frequency =>60, -- Hz
Pixel_Clock =>108, -- MHz
Character_Width =>8, -- Pixels
Scan_Type =>NONINTERLACED,
Hor_Sync_Polarity =>SYNC_POSITIVE,
Ver_Sync_Polarity =>SYNC_POSITIVE,
Hor_Total_Time =>1800, -- Pixels
Hor_Addr_Time =>1600, -- Pixels
Hor_Blank_Start =>1600, -- Pixels
Hor_Blank_Time =>200, -- Pixels
Hor_Sync_Start =>1624, -- Pixels
H_Right_Border =>0, -- Pixels
H_Front_Porch =>24, -- Pixels
H_Sync_Time =>80, -- Pixels
H_Back_Porch =>96, -- Pixels
H_Left_Border =>0, -- Pixels
Ver_Total_Time =>1000, -- Lines
Ver_Addr_Time =>900, -- Lines
Ver_Blank_Start =>900, -- Lines
Ver_Blank_Time =>100, -- Lines
Ver_Sync_Start =>901, -- Lines
V_Bottom_Border =>0, -- Lines
V_Front_Porch =>1, -- Lines
V_Sync_Time =>3, -- Lines
V_Back_Porch =>96, -- Lines
V_Top_Border =>0 -- Lines
--------------------------------------------------------------
);
constant timing_1600x900x60Hz_debug : format_type :=(
--------------------------------------------------------------
-- Based from VESA Monitor Timing Standard version 1 Rev. 13
--------------------------------------------------------------
Hor_Pixels =>25, -- Pixels
Ver_Pixels =>32, -- Lines
Hor_Frequency =>0, -- kHz
Ver_Frequency =>0, -- Hz
Pixel_Clock =>0, -- MHz
Character_Width =>4, -- Pixels
Scan_Type =>NONINTERLACED,
Hor_Sync_Polarity =>SYNC_POSITIVE,
Ver_Sync_Polarity =>SYNC_POSITIVE,
Hor_Total_Time =>30, -- Pixels
Hor_Addr_Time =>20, -- Pixels
Hor_Blank_Start =>20, -- Pixels
Hor_Blank_Time =>10, -- Pixels
Hor_Sync_Start =>23, -- Pixels
H_Right_Border =>0, -- Pixels
H_Front_Porch =>3, -- Pixels
H_Sync_Time =>2, -- Pixels
H_Back_Porch =>5, -- Pixels
H_Left_Border =>0, -- Pixels
Ver_Total_Time =>40, -- Lines
Ver_Addr_Time =>32, -- Lines
Ver_Blank_Start =>32, -- Lines
Ver_Blank_Time =>10, -- Lines
Ver_Sync_Start =>18, -- Lines
V_Bottom_Border =>0, -- Lines
V_Front_Porch =>3, -- Lines
V_Sync_Time =>2, -- Lines
V_Back_Porch =>5, -- Lines
V_Top_Border =>0 -- Lines
);
--============= Deferred Functions ===============================
----------------------------------------------------------------
-- Functions to select simulation or synthesis parameter based
-- Use for init constant in function if we are in debug mode or not
-- in order to avoid long time of simulation...
-- 0 : Synthetesis mode
-- 1 : Simulation mode
-- init_constant( simul_mode, simul_parameter, synth_prameter)
----------------------------------------------------------------
function init_constant(Condition: boolean; Enable_Debug,Disable_Debug : natural) return natural is
begin
if (Condition = true) then
return(Enable_Debug);
else
return(Disable_Debug);
end if;
end function init_constant;
----------------------------------------------------------------
-- Functions to select simulation or synthesis parameter based
-- Use for init constant in function if we are in debug mode or not
-- in order to avoid long time of simulation...
-- false : Synthetesis mode
-- true : Simulation mode
----------------------------------------------------------------
--------------------------------------------------------------
-- Init format type
--------------------------------------------------------------
function init_video_type(Condition: boolean; format_video : string) return format_type is
begin
-- Debug Mode
if (Condition = true) then
if (format_video = "1920x1080@60Hz") then
return(timing_1920x1080x60Hz_debug);
elsif (format_video = "1600x900@60Hz") then
return(timing_1600x900x60Hz_debug);
else
assert false
report "(1)Display_Management_pkg : No way to find the format_type wanted : " & format_video
severity failure;
end if;
-- Normal Mode
else
if (format_video = "1920x1080@60Hz") then
return(timing_1920x1080x60Hz);
elsif (format_video = "1600x900@60Hz") then
return(timing_1600x900x60Hz);
else
assert false
report "(2)Display_Management_pkg : No way to find the format_type wanted : " & format_video
severity failure;
end if;
end if;
assert false
report "(3)Display_Management_pkg : No way to find the format_type wanted : " & format_video
severity failure;
return(timing_1920x1080x60Hz);
end function init_video_type;
--------------------------------------------------------------
-- Init pulse type
--------------------------------------------------------------
function init_timing_type(input_format_video : format_type) return timing_type is
variable temp_timing : timing_type;
begin
temp_timing.Hsync_Start :=to_unsigned( input_format_video.Hor_Total_Time -2, nbits_pixel);
temp_timing.Hsync_End :=to_unsigned( input_format_video.H_Sync_Time -1,nbits_pixel);
------------------------------------------------------------------------------------------------------------------------------
temp_timing.H_Active_Video_Start :=to_unsigned( input_format_video.H_Sync_Time + input_format_video.H_Back_Porch -1,nbits_pixel);
------------------------------------------------------------------------------------------------------------------------------
temp_timing.H_Addressable_Video_Start :=to_unsigned( input_format_video.H_Sync_Time + input_format_video.H_Back_Porch
+ input_format_video.H_Left_Border -1,nbits_pixel);
------------------------------------------------------------------------------------------------------------------------------
temp_timing.H_Addressable_Video_End :=to_unsigned( input_format_video.H_Sync_Time + input_format_video.H_Back_Porch
+ input_format_video.H_Left_Border + input_format_video.Hor_Addr_Time -1,nbits_pixel);
------------------------------------------------------------------------------------------------------------------------------
temp_timing.H_Active_Video_End :=to_unsigned( input_format_video.H_Sync_Time + input_format_video.H_Back_Porch
+ input_format_video.H_Left_Border + input_format_video.Hor_Addr_Time
+ input_format_video.H_Right_Border -1,nbits_pixel);
--============================================================================================================================
temp_timing.Vsync_Start :=to_unsigned( input_format_video.Ver_Total_Time -1,nbits_pixel);
temp_timing.Vsync_End :=to_unsigned( input_format_video.V_Sync_Time -1,nbits_pixel);
------------------------------------------------------------------------------------------------------------------------------
temp_timing.V_Active_Video_Start :=to_unsigned( input_format_video.V_Sync_Time + input_format_video.V_Back_Porch -2,nbits_pixel);
------------------------------------------------------------------------------------------------------------------------------
temp_timing.V_Addressable_Video_Start :=to_unsigned(input_format_video.V_Sync_Time + input_format_video.V_Back_Porch
+ input_format_video.V_Top_Border ,nbits_pixel);
------------------------------------------------------------------------------------------------------------------------------
temp_timing.V_Addressable_Video_End :=to_unsigned(input_format_video.V_Sync_Time + input_format_video.V_Back_Porch
+ input_format_video.V_Top_Border + input_format_video.Ver_Addr_Time ,nbits_pixel);
------------------------------------------------------------------------------------------------------------------------------
temp_timing.V_Active_Video_End :=to_unsigned(input_format_video.V_Sync_Time + input_format_video.V_Back_Porch
+ input_format_video.V_Top_Border + input_format_video.Ver_Addr_Time
+ input_format_video.V_Bottom_Border ,nbits_pixel);
return temp_timing;
end function init_timing_type;
end package body Display_Management_pkg;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: inpad_ds
-- File: inpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: input pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity inpad_ds is
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of inpad_ds is
signal gnd : std_ulogic;
begin
gnd <= '0';
gen0 : if has_ds_pads(tech) = 0 generate
o <= to_X01(padp)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (tech = virtex2) or (tech = spartan3) generate
u0 : unisim_inpad_ds generic map (level, voltage, term) port map (padp, padn, o);
end generate;
xc4v : if (tech = virtex4) or (tech = spartan3e) or (tech = virtex5) or (tech = spartan6)
or (tech = virtex6) or (tech = virtex7) or (tech = kintex7) or (tech =artix7) or (tech =zynq7000) generate
u0 : virtex4_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_inpad_ds generic map (level) port map (padp, padn, o);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad_ds port map (padp, padn, o, gnd);
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_inpad_ds generic map (level, voltage) port map (padp, padn, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity inpad_dsv is
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1);
port (
padp : in std_logic_vector(width-1 downto 0);
padn : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of inpad_dsv is
begin
v : for i in width-1 downto 0 generate
u0 : inpad_ds generic map (tech, level, voltage) port map (padp(i), padn(i), o(i));
end generate;
end;
|
--
-- True Dual-Port RAM
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.MEMS.all;
entity TrueDualPortRAM is
generic (
AWIDTH : positive:=8; -- Address width
DWIDTH : positive:=8; -- Data width
DEPTH : natural:=0; -- Memory depth
SYNCMODE : syncmode_t:=WRITE_FIRST; -- Synchronization Mode
OUTREG : boolean :=FALSE -- Optional Output Register
);
port (
clk1_i : in std_logic;
clk2_i : in std_logic;
wen1_i : in std_logic;
wen2_i : in std_logic;
addr1_i : in std_logic_vector(AWIDTH-1 downto 0);
addr2_i : in std_logic_vector(AWIDTH-1 downto 0);
data1_i : in std_logic_vector(DWIDTH-1 downto 0);
data2_i : in std_logic_vector(DWIDTH-1 downto 0);
data1_o : out std_logic_vector(DWIDTH-1 downto 0);
data2_o : out std_logic_vector(DWIDTH-1 downto 0)
);
end entity TrueDualPortRAM;
architecture RTL of TrueDualPortRAM is
constant SIZE : positive:=getMemorySize(DEPTH,AWIDTH);
type ram_type is array(SIZE-1 downto 0) of std_logic_vector (DWIDTH-1 downto 0);
shared variable ram : ram_type;
signal data1, data2 : std_logic_vector(DWIDTH-1 downto 0);
begin
ram1_p:
process (clk1_i)
begin
if rising_edge(clk1_i) then
case SYNCMODE is
when READ_FIRST =>
if OUTREG then
data1 <= ram(to_integer(unsigned(addr1_i)));
data1_o <= data1;
else
data1_o <= ram(to_integer(unsigned(addr1_i)));
end if;
if wen1_i='1' then
ram(to_integer(unsigned(addr1_i))) := data1_i;
end if;
when WRITE_FIRST =>
if wen1_i='1' then
ram(to_integer(unsigned(addr1_i))) := data1_i;
if OUTREG then
data1 <= data1_i;
data1_o <= data1;
else
data1_o <= data1_i;
end if;
else
if OUTREG then
data1 <= ram(to_integer(unsigned(addr1_i)));
data1_o <= data1;
else
data1_o <= ram(to_integer(unsigned(addr1_i)));
end if;
end if;
when NO_CHANGE =>
if wen1_i='1' then
ram(to_integer(unsigned(addr1_i))) := data1_i;
else
if OUTREG then
data1 <= ram(to_integer(unsigned(addr1_i)));
data1_o <= data1;
else
data1_o <= ram(to_integer(unsigned(addr1_i)));
end if;
end if;
end case;
end if;
end process ram1_p;
ram2_p:
process (clk2_i)
begin
if rising_edge(clk2_i) then
case SYNCMODE is
when READ_FIRST =>
if OUTREG then
data2 <= ram(to_integer(unsigned(addr2_i)));
data2_o <= data2;
else
data2_o <= ram(to_integer(unsigned(addr2_i)));
end if;
if wen2_i='1' then
ram(to_integer(unsigned(addr2_i))) := data2_i;
end if;
when WRITE_FIRST =>
if wen2_i='1' then
ram(to_integer(unsigned(addr2_i))) := data2_i;
if OUTREG then
data2 <= data2_i;
data2_o <= data2;
else
data2_o <= data2_i;
end if;
else
if OUTREG then
data2 <= ram(to_integer(unsigned(addr2_i)));
data2_o <= data2;
else
data2_o <= ram(to_integer(unsigned(addr2_i)));
end if;
end if;
when NO_CHANGE =>
if wen2_i='1' then
ram(to_integer(unsigned(addr2_i))) := data2_i;
else
if OUTREG then
data2 <= ram(to_integer(unsigned(addr2_i)));
data2_o <= data2;
else
data2_o <= ram(to_integer(unsigned(addr2_i)));
end if;
end if;
end case;
end if;
end process ram2_p;
end architecture RTL;
|
library accum;
use accum.OneHotAccum.all;
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity mrom_tb is
end mrom_tb;
architecture TB_ARCHITECTURE of mrom_tb is
-- Component declaration of the tested unit
component mrom
port(
RE : in STD_LOGIC;
ADDR : in mem_addr;
DOUT : out command );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal RE : STD_LOGIC;
signal ADDR : mem_addr;
-- Observed signals - signals mapped to the output ports of tested entity
signal DOUT : command;
-- Add your code here ...
constant WAIT_period: time := 10 ns;
begin
-- Unit Under Test port map
UUT : mrom
port map (
RE => RE,
ADDR => ADDR,
DOUT => DOUT
);
-- Add your stimulus here ...
main: process
begin
re <= '0';
addr <= "00010";
wait for 1 * WAIT_period;
re <= '1';
wait for 1 * WAIT_period;
addr <= "00000";
re <= '1';
wait for 1 * WAIT_period;
re <= '0';
wait for 100 * WAIT_period;
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_mrom of mrom_tb is
for TB_ARCHITECTURE
for UUT : mrom
use entity work.mrom(beh);
end for;
end for;
end TESTBENCH_FOR_mrom;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace_mb
-- File: ahbtrace_mb.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB trace unit that can have registers on a separate bus
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
entity ahbtrace_mb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
ahbfilt : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmi : in ahb_mst_in_type; -- Trace
tahbsi : in ahb_slv_in_type
);
end;
architecture rtl of ahbtrace_mb is
signal tahbmiv : ahb_mst_in_vector_type(0 to 0);
signal tahbsiv : ahb_slv_in_vector_type(0 to 0);
begin
tahbmiv(0) <= tahbmi;
tahbsiv(0) <= tahbsi;
ahbt0 : ahbtrace_mmb
generic map (
hindex => hindex,
ioaddr => ioaddr,
iomask => iomask,
tech => tech,
irq => irq,
kbytes => kbytes,
ahbfilt => ahbfilt,
ntrace => 1)
port map(
rst => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
tahbmiv => tahbmiv,
tahbsiv => tahbsiv);
end;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mact-bb.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture bench_behavioral of mac_test is
signal clk, clr, ovf : std_ulogic := '0';
signal x_real, x_imag,
y_real, y_imag,
s_real, s_imag : std_ulogic_vector(15 downto 0);
type complex is record
re, im : real;
end record;
signal x, y, s : complex := (0.0, 0.0);
constant Tpw_clk : time := 50 ns;
begin
x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
dut : entity work.mac(behavioral)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag, s_real, s_imag,
ovf );
s_real_converter : entity work.to_fp(behavioral) port map (s_real, s.re);
s_imag_converter : entity work.to_fp(behavioral) port map (s_imag, s.im);
clock_gen : process is
begin
clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
wait for 2 * Tpw_clk;
end process clock_gen;
stimulus : process is
begin
-- first sequence
clr <= '1'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (+0.2, +0.2); y <= (+0.2, +0.2); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
-- should be (0.4, 0.58) when it falls out the other end
clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (-0.5, +0.5); y <= (-0.5, +0.5); clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '1'; wait until clk = '0';
wait;
end process stimulus;
end architecture bench_behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mact-bb.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture bench_behavioral of mac_test is
signal clk, clr, ovf : std_ulogic := '0';
signal x_real, x_imag,
y_real, y_imag,
s_real, s_imag : std_ulogic_vector(15 downto 0);
type complex is record
re, im : real;
end record;
signal x, y, s : complex := (0.0, 0.0);
constant Tpw_clk : time := 50 ns;
begin
x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
dut : entity work.mac(behavioral)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag, s_real, s_imag,
ovf );
s_real_converter : entity work.to_fp(behavioral) port map (s_real, s.re);
s_imag_converter : entity work.to_fp(behavioral) port map (s_imag, s.im);
clock_gen : process is
begin
clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
wait for 2 * Tpw_clk;
end process clock_gen;
stimulus : process is
begin
-- first sequence
clr <= '1'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (+0.2, +0.2); y <= (+0.2, +0.2); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
-- should be (0.4, 0.58) when it falls out the other end
clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (-0.5, +0.5); y <= (-0.5, +0.5); clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '1'; wait until clk = '0';
wait;
end process stimulus;
end architecture bench_behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mact-bb.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture bench_behavioral of mac_test is
signal clk, clr, ovf : std_ulogic := '0';
signal x_real, x_imag,
y_real, y_imag,
s_real, s_imag : std_ulogic_vector(15 downto 0);
type complex is record
re, im : real;
end record;
signal x, y, s : complex := (0.0, 0.0);
constant Tpw_clk : time := 50 ns;
begin
x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
dut : entity work.mac(behavioral)
port map ( clk, clr,
x_real, x_imag, y_real, y_imag, s_real, s_imag,
ovf );
s_real_converter : entity work.to_fp(behavioral) port map (s_real, s.re);
s_imag_converter : entity work.to_fp(behavioral) port map (s_imag, s.im);
clock_gen : process is
begin
clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
wait for 2 * Tpw_clk;
end process clock_gen;
stimulus : process is
begin
-- first sequence
clr <= '1'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (+0.2, +0.2); y <= (+0.2, +0.2); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '1'; wait until clk = '0';
x <= (+0.1, -0.1); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
-- should be (0.4, 0.58) when it falls out the other end
clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.1, +0.1); clr <= '0'; wait until clk = '0';
x <= (+0.5, +0.5); y <= (+0.5, +0.5); clr <= '1'; wait until clk = '0';
x <= (-0.5, +0.5); y <= (-0.5, +0.5); clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '0'; wait until clk = '0';
clr <= '1'; wait until clk = '0';
wait;
end process stimulus;
end architecture bench_behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2275.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02275ent IS
END c07s02b06x00p14n01i02275ent;
ARCHITECTURE c07s02b06x00p14n01i02275arch OF c07s02b06x00p14n01i02275ent IS
BEGIN
TESTING: PROCESS
type ENUMERATION_TYPE is (ONE,TWO,THREE,FOUR);
variable T : TIME := 1 sec;
BEGIN
T := ONE * 1 MIN; -- Failure_here
-- SEMANTIC ERROR: if one operand is physical, then the other must
-- an integer or floating point type.
assert FALSE
report "***FAILED TEST: c07s02b06x00p14n01i02275 - If one operand is of type physical, the other has to be of type integer or real."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02275arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2275.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02275ent IS
END c07s02b06x00p14n01i02275ent;
ARCHITECTURE c07s02b06x00p14n01i02275arch OF c07s02b06x00p14n01i02275ent IS
BEGIN
TESTING: PROCESS
type ENUMERATION_TYPE is (ONE,TWO,THREE,FOUR);
variable T : TIME := 1 sec;
BEGIN
T := ONE * 1 MIN; -- Failure_here
-- SEMANTIC ERROR: if one operand is physical, then the other must
-- an integer or floating point type.
assert FALSE
report "***FAILED TEST: c07s02b06x00p14n01i02275 - If one operand is of type physical, the other has to be of type integer or real."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02275arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2275.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02275ent IS
END c07s02b06x00p14n01i02275ent;
ARCHITECTURE c07s02b06x00p14n01i02275arch OF c07s02b06x00p14n01i02275ent IS
BEGIN
TESTING: PROCESS
type ENUMERATION_TYPE is (ONE,TWO,THREE,FOUR);
variable T : TIME := 1 sec;
BEGIN
T := ONE * 1 MIN; -- Failure_here
-- SEMANTIC ERROR: if one operand is physical, then the other must
-- an integer or floating point type.
assert FALSE
report "***FAILED TEST: c07s02b06x00p14n01i02275 - If one operand is of type physical, the other has to be of type integer or real."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02275arch;
|
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