rtl-llm/vhdl_github · Datasets at Hugging Face

content stringlengths 1 1.04M ⌀
constant SPIFSMLength : integer := 1295; constant SPIFSMCfg : std_logic_vector(SPIFSMLength-1 downto 0) := "00001001110000100110010000010000000000000111000000001010101000000100101000000110000110000010010000100011100100000010011000100000000000010001000000000001110000000000000000100100011000000100100000000010000000010100010000000010100001000100000000110010000000010010000010001100000010100001100000000100000000011000000100101001000010001000000010000000000011001010000010010100000100100000000110001000001000010000001010000000100100001000010001000000010100000001010010100000000010000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000";
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block ncUawuo3vR1ZycZF8xtqqfVI6gCrdI+PWd72xdzgvbKVjiUqedCWSUEBFuuQDLCwTlT4hYrqtcoA k+jkF6hUqA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block N3KVU8m7dp9m/o5klJahn6JrAp4dPvJ5px8Qjfdd/9teg+MgeqRSyR4a+nedbYovR1iG1M+OV4GZ eedyUHeQwlftb33WHTgiSQcQOeDYQHOhB1q+SjuhN26SLFWK3YFERu3kL1tM5w3W0nuFqj+bXHZu R4gQdtVWH/+OjyCytQw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ZuxsHcVs7eB3t+mMECRU+c4tWaV00xKC1y8JMSw6ZK4lGIrGd9iKbAKZ3Blwh1vsVCQb3NTC7N3r Y605Rnu1VKPlFpM556/vIzoPVRgcSvlo0qBj3oTSzlA5eJk5FVF3mP4v0RD6iY8xceU38ESPNbz9 tslYUbhOJVSsY7yCjCM7p+456bByCG6ed5+0nGONoXPAT0zF3Hxdnq8qgQDMjEIvOsaFSADZUSxL WwjD6WPmcry72t5+zgCtiIUOoGhbFWqTndKP66O5YJAWE6dVlP4zMLQZZAfmdfQyazOsgs1uciSH +eAOcN/r5BkNmFBVWZOF8biq4mt3PmniNwcfbg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block ygy9fvZbqToh8lhxP+oGEoqQi72mLbOonZqXDBQOfdz3oQWE3Hi1Zc2hfB1uR17TPoqAq2eJIm6k q8c0om7asQ06vgODSHayDyQ+hyxq53TnIlLVx1AtJPfm0kI21kep00Mfc/Dwi7Qyt/ia2tlS/tQw 4OktcMlj77AyGCR8zdc= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mcqNli4YixoMqmYwzxOZ0byTQYAQvCZuCaZ7iJ4keY79GxqKVx5edvY5HqwqCRXfHCDzwy4qGKcN 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block ncUawuo3vR1ZycZF8xtqqfVI6gCrdI+PWd72xdzgvbKVjiUqedCWSUEBFuuQDLCwTlT4hYrqtcoA k+jkF6hUqA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block N3KVU8m7dp9m/o5klJahn6JrAp4dPvJ5px8Qjfdd/9teg+MgeqRSyR4a+nedbYovR1iG1M+OV4GZ eedyUHeQwlftb33WHTgiSQcQOeDYQHOhB1q+SjuhN26SLFWK3YFERu3kL1tM5w3W0nuFqj+bXHZu R4gQdtVWH/+OjyCytQw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_2 Core - Top File for the Example Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- Filename: ram_16x1k_sp_tb.vhd -- Description: -- Testbench Top -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.ALL; ENTITY ram_16x1k_sp_tb IS END ENTITY; ARCHITECTURE ram_16x1k_sp_tb_ARCH OF ram_16x1k_sp_tb IS SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL CLK : STD_LOGIC := '1'; SIGNAL RESET : STD_LOGIC; BEGIN CLK_GEN: PROCESS BEGIN CLK <= NOT CLK; WAIT FOR 100 NS; CLK <= NOT CLK; WAIT FOR 100 NS; END PROCESS; RST_GEN: PROCESS BEGIN RESET <= '1'; WAIT FOR 1000 NS; RESET <= '0'; WAIT; END PROCESS; --STOP_SIM: PROCESS BEGIN -- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS -- ASSERT FALSE -- REPORT "END SIMULATION TIME REACHED" -- SEVERITY FAILURE; --END PROCESS; -- PROCESS BEGIN WAIT UNTIL STATUS(8)='1'; IF( STATUS(7 downto 0)/="0") THEN ASSERT false REPORT "Simulation Failed" SEVERITY FAILURE; ELSE ASSERT false REPORT "Test Completed Successfully" SEVERITY FAILURE; END IF; END PROCESS; ram_16x1k_sp_synth_inst:ENTITY work.ram_16x1k_sp_synth PORT MAP( CLK_IN => CLK, RESET_IN => RESET, STATUS => STATUS ); END ARCHITECTURE;
architecture RTL of FIFO is shared variable shar_var1 : integer; begin process variable var1 : integer; begin end process; end architecture RTL; -- Violations below architecture RTL of FIFO is shared variable shar_var1 : integer; begin process variable var1 : integer; begin end process; end architecture RTL;
architecture RTL of FIFO is shared variable shar_var1 : integer; begin process variable var1 : integer; begin end process; end architecture RTL; -- Violations below architecture RTL of FIFO is shared variable shar_var1 : integer; begin process variable var1 : integer; begin end process; end architecture RTL;
architecture rtl of fifo is begin process begin my_signal := '1' when input = "00" else my_signal2 or my_sig3 when input = "01" else my_sig4 and my_sig5 when input = "10" else '0'; my_signal := '1' when input = "0000" else my_signal2 or my_sig3 when input = "0100" and input = "1100" else my_sig4 when input = "0010" else '0'; my_signal := '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else '0' when input(3 downto 0) = "0010" else 'Z'; my_signal := '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else '0' when input(3 downto 0) = "0010" else 'Z'; my_signal := '1' when a = "0000" and func1(345) or b = "1000" and func2(567) and c = "00" else sig1 when a = "1000" and func2(560) and b = "0010" else '0'; my_signal := '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; -- Testing no code after assignment my_signal := '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; my_signal := (others => '0') when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; end process; end architecture rtl;
-- DDR2 memory interface -- Andrew Read, March 2016 -- This project is based on a working DDR2 interface very kindly donated by a friend LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_textio.all; entity SDRAM_CTRL is port ( CLK : in std_logic; -- 125MHz clock CLK_130 : in std_logic; -- 125MHz clock 130 degree phase shift reset : in std_logic; wrrd_ba_add : in std_logic_vector(2 downto 0); -- bank address wrrd_ras_add : in std_logic_vector(12 downto 0); -- row address wrrd_cas_add : in std_logic_vector(8 downto 0); -- column address -- this is technically a 16-bit word address but SDRAM_PHY ignores the least significant bit of the column address -- so the address space is effectively 32-bit word addressable wr_we : in std_logic_vector(3 downto 0); wr_add : in std_logic_vector(25 downto 0); -- not used wr_dat : in std_logic_vector(31 downto 0); wr_ack : out std_logic; rd_re : in std_logic; rd_add : in std_logic_vector(25 downto 0); -- not used rd_dat : out std_logic_vector(31 downto 0); rd_ack : out std_logic; rd_valid : out std_logic; SDRAM_A : out std_logic_vector(13 downto 0); SDRAM_BA : out std_logic_vector(2 downto 0); SDRAM_CKE : out std_logic; SDRAM_CK : out std_logic; SDRAM_nCK : out std_logic; SDRAM_DQ : inout std_logic_vector(15 downto 0); SDRAM_DQS : inout std_logic_vector(1 downto 0); --SDRAM_nDQS : inout std_logic_vector(1 downto 0); SDRAM_DM : out std_logic_vector(1 downto 0); SDRAM_nCAS : out std_logic; SDRAM_nCS : out std_logic; SDRAM_nRAS : out std_logic; SDRAM_nWE : out std_logic); end SDRAM_CTRL; architecture Struct of SDRAM_CTRL is component SDRAM_PHYIO is port ( CLK : in std_logic; CLK_130 : in std_logic; reset : in std_logic; wrrd_ba_add : in std_logic_vector(2 downto 0); wrrd_ras_add : in std_logic_vector(12 downto 0); wrrd_cas_add : in std_logic_vector(8 downto 0); wr_we : in std_logic_vector(3 downto 0); wr_add : in std_logic_vector(25 downto 0); wr_dat : in std_logic_vector(31 downto 0); wr_ack : out std_logic; rd_re : in std_logic; rd_add : in std_logic_vector(25 downto 0); rd_dat : out std_logic_vector(31 downto 0); rd_ack : out std_logic; rd_valid : out std_logic; refresh : in std_logic; ref_ack : out std_logic; SDRAM_A : out std_logic_vector(13 downto 0); SDRAM_BA : out std_logic_vector(2 downto 0); SDRAM_CKE : out std_logic; SDRAM_CK : out std_logic; SDRAM_nCK : out std_logic; SDRAM_DQ : inout std_logic_vector(15 downto 0); SDRAM_DQS : inout std_logic_vector(1 downto 0); --SDRAM_nDQS : inout std_logic_vector(1 downto 0); SDRAM_DM : out std_logic_vector(1 downto 0); SDRAM_nCAS : out std_logic; SDRAM_nCS : out std_logic; SDRAM_nRAS : out std_logic; SDRAM_nWE : out std_logic); end component; ---------------------------------------------------- -- Refresh parameters ---------------------------------------------------- -- This module, SDRAM_CTRL, raises a refresh request each refreshInterval clock cycles -- SDRAM_PHY issues refreshCount consecutive REFRESH commands in response to each refresh request -- Each REFRESH command takes at least tRFC = 127.5 ns -- The refresh period of the MT47H64M16HR-25E is 64ms, thus to comply with the specification -- refreshInterval * ( refreshCount [defined in SDRAM_PHYIO.vhd] + 1 ) * clock_period <= 64ms -- Example refresh strategies at 125MHz (based on a 7.2us clock period including allowance) -- 1. Refresh the entire SDRAM once each 64ms, blocking the device for 1ms each time -- constant refreshInterval : integer range 0 to 16777215 := 8888888; -- constant refreshCount : integer range 0 to 8191 := 8191; -- -- 2. Refresh the entire SDRAM once each 0.75ms, blocking the device for 12.5us each time -- constant refreshInterval : integer range 0 to 16777215 := 54000; -- constant refreshCount : integer range 0 to 8191 := 95; -- -- 3. Refresh the SRDRAM once each 62.5us, blocking the device for 1us each time -- constant refreshInterval : integer range 0 to 16777215 := 4500; -- constant refreshCount : integer range 0 to 8191 := 7; constant refreshInterval : integer range 0 to 16777215 := 4500; -- number of clock cycles between each refresh request signal refresh_time_cnt : integer range 0 to 16777215; signal refresh : std_logic; signal ref_ack : std_logic; begin ----------------------------------------------------- -- Refresh Mechanism ----------------------------------------------------- refresh_gen : process (CLK, reset) begin if (reset='1') then refresh_time_cnt <= 0; refresh <= '0'; elsif (CLK'event and CLK='1') then -- free running timer/counter if (refresh_time_cnt = refreshInterval) then refresh_time_cnt <= 0; else refresh_time_cnt <= refresh_time_cnt + 1; end if; -- refresh request signal if (refresh_time_cnt = refreshInterval) then refresh <= '1'; elsif (ref_ack = '1') then refresh <= '0'; end if; end if; end process; -- instantiate SDRAM_PHYIO SDRAM_PHYIOi : SDRAM_PHYIO port map ( CLK => CLK, CLK_130 => CLK_130, reset => reset, wrrd_ba_add => wrrd_ba_add, wrrd_ras_add => wrrd_ras_add, wrrd_cas_add => wrrd_cas_add, wr_we => wr_we, wr_add => wr_add, wr_dat => wr_dat, wr_ack => wr_ack, rd_re => rd_re, rd_add => rd_add, rd_dat => rd_dat, rd_ack => rd_ack, rd_valid => rd_valid, refresh => refresh, ref_ack => ref_ack, SDRAM_A => SDRAM_A, SDRAM_BA => SDRAM_BA, SDRAM_CKE => SDRAM_CKE, SDRAM_CK => SDRAM_CK, SDRAM_nCK => SDRAM_nCK, SDRAM_DQ => SDRAM_DQ, SDRAM_DQS => SDRAM_DQS, --SDRAM_nDQS => SDRAM_nDQS, SDRAM_DM => SDRAM_DM, SDRAM_nCAS => SDRAM_nCAS, SDRAM_nCS => SDRAM_nCS, SDRAM_nRAS => SDRAM_nRAS, SDRAM_nWE => SDRAM_nWE); end Struct;
library ieee; use ieee.std_logic_1164.all; package memory_types is type memory_16b is array (15 downto 0) of std_logic_vector(7 downto 0); end package memory_types;
library ieee; use ieee.std_logic_1164.all; package memory_types is type memory_16b is array (15 downto 0) of std_logic_vector(7 downto 0); end package memory_types;
-- ------------------------------------------------------------- -- -- Entity Declaration for inst_ac_e -- -- Generated -- by: wig -- on: Sat Mar 3 17:08:41 2007 -- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_ac_e-e.vhd,v 1.2 2007/03/03 17:24:06 wig Exp $ -- $Date: 2007/03/03 17:24:06 $ -- $Log: inst_ac_e-e.vhd,v $ -- Revision 1.2 2007/03/03 17:24:06 wig -- Updated testcase for case matches. Added filename serialization. -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.47 , [email protected] -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_ac_e -- entity inst_ac_e is -- Generics: -- No Generated Generics for Entity inst_ac_e -- Generated Port Declaration: -- No Generated Port for Entity inst_ac_e end inst_ac_e; -- -- End of Generated Entity inst_ac_e -- -- --!End of Entity/ies -- --------------------------------------------------------------
------------------------------------------------------------------------------ -- LEON3 Demonstration design -- Copyright (C) 2006 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015 - 2016, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; library techmap; use techmap.gencomp.all; use techmap.allclkgen.all; library gaisler; use gaisler.memctrl.all; use gaisler.ddrpkg.all; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; use gaisler.net.all; use gaisler.jtag.all; library esa; use esa.memoryctrl.all; use work.config.all; entity leon3mp is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; ddrfreq : integer := 100000 -- frequency of ddr clock in kHz ); port ( resetn : in std_ulogic; resoutn : out std_logic; clk_100mhz : in std_ulogic; errorn : out std_ulogic; -- prom interface address : out std_logic_vector(21 downto 0); data : inout std_logic_vector(15 downto 0); romsn : out std_ulogic; oen : out std_ulogic; writen : out std_ulogic; romrstn : out std_ulogic; -- pragma translate_off iosn : out std_ulogic; testdata : inout std_logic_vector(15 downto 0); -- pragma translate_on -- ddr memory ddr_clk0 : out std_logic; ddr_clk0b : out std_logic; ddr_clk_fb_out : out std_logic; ddr_clk_fb : in std_logic; ddr_cke0 : out std_logic; ddr_cs0b : out std_logic; ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs ddr_ad : out std_logic_vector (12 downto 0); -- ddr address ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data -- debug support unit dsuen : in std_ulogic; dsubre : in std_ulogic; dsuact : out std_ulogic; -- UART for serial DCL/console I/O serrx : in std_ulogic; sertx : out std_ulogic; rtsn : out std_ulogic; ctsn : in std_ulogic; led_rx : out std_ulogic; led_tx : out std_ulogic; -- ethernet signals emdio : inout std_logic; -- ethernet PHY interface etx_clk : in std_ulogic; erx_clk : in std_ulogic; erxd : in std_logic_vector(3 downto 0); erx_dv : in std_ulogic; erx_er : in std_ulogic; erx_col : in std_ulogic; erx_crs : in std_ulogic; etxd : out std_logic_vector(3 downto 0); etx_en : out std_ulogic; etx_er : out std_ulogic; emdc : out std_ulogic; erstn : out std_ulogic; -- OLED display signals disp_dcn : out std_ulogic; disp_csn : out std_ulogic; disp_rdn : out std_ulogic; disp_wrn : out std_ulogic; disp_d : inout std_logic_vector(7 downto 0) ); end; architecture rtl of leon3mp is constant blength : integer := 12; constant fifodepth : integer := 8; signal vcc, gnd : std_logic_vector(4 downto 0); signal memi : memory_in_type; signal memo : memory_out_type; signal wpo : wprot_out_type; signal sdi : sdctrl_in_type; signal sdo : sdctrl_out_type; signal gpioi : gpio_in_type; signal gpioo : gpio_out_type; signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); signal lclk : std_ulogic; signal ddrclk, ddrrst, ddrclkfb : std_ulogic; signal clkm, rstn, clkml, clk2x : std_ulogic; signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; signal u1i, dui : uart_in_type; signal u1o, duo : uart_out_type; signal irqi : irq_in_vector(0 to CFG_NCPU-1); signal irqo : irq_out_vector(0 to CFG_NCPU-1); signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); signal dsui : dsu_in_type; signal dsuo : dsu_out_type; signal ethi, ethi1, ethi2 : eth_in_type; signal etho, etho1, etho2 : eth_out_type; signal gpti : gptimer_in_type; signal tck, tms, tdi, tdo : std_ulogic; -- signal dsubre : std_logic; signal duart, ldsuen : std_logic; signal rsertx, rserrx, rdsuen : std_logic; signal rstraw : std_logic; signal rstneg : std_logic; signal rxd1 : std_logic; signal txd1 : std_logic; signal lock : std_logic; signal ddr_clk : std_logic_vector(2 downto 0); signal ddr_clkb : std_logic_vector(2 downto 0); signal ddr_cke : std_logic_vector(1 downto 0); signal ddr_csb : std_logic_vector(1 downto 0); signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address attribute keep : boolean; attribute syn_keep : boolean; attribute syn_preserve : boolean; attribute syn_keep of lock : signal is true; attribute syn_keep of clkml : signal is true; attribute syn_preserve of clkml : signal is true; attribute keep of lock : signal is true; attribute keep of clkml : signal is true; attribute keep of clkm : signal is true; constant BOARD_FREQ : integer := 100000; -- input frequency in KHz constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz begin romrstn <= rstn; ---------------------------------------------------------------------- --- Reset and Clock generation ------------------------------------- ---------------------------------------------------------------------- vcc <= (others => '1'); gnd <= (others => '0'); cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; rstneg <= not resetn; rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw); clk_pad : clkpad generic map (tech => padtech) port map (clk_100mhz, lclk); clkgen0 : clkgen -- clock generator generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, 0, 1, 0, 0, 0, BOARD_FREQ, 0) port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo); ---------------------------------------------------------------------- --- AHB CONTROLLER -------------------------------------------------- ---------------------------------------------------------------------- ahb0 : ahbctrl -- AHB arbiter/multiplexer generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1, nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1, nahbs => 8) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- --- LEON3 processor and DSU ----------------------------------------- ---------------------------------------------------------------------- leon3gen : if CFG_LEON3 = 1 generate cpu : for i in 0 to CFG_NCPU-1 generate u0 : leon3s -- LEON3 processor generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); end generate; error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error); dsugen : if CFG_DSU = 1 generate dsu0 : dsu3 -- LEON3 Debug Support Unit generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); dsui.enable <= '1'; dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); end generate; end generate; nodsu : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; end generate; dcomgen : if CFG_AHB_UART = 1 generate dcom0 : ahbuart -- Debug UART generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7) port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU)); end generate; nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate; ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART) port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART), open, open, open, open, open, open, open, gnd(0)); end generate; ---------------------------------------------------------------------- --- Memory controllers ---------------------------------------------- ---------------------------------------------------------------------- mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 ) port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open); end generate; memi.brdyn <= '1'; memi.bexcn <= '1'; memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01"; mg0 : if (CFG_MCTRL_LEON2 = 0) generate apbo(0) <= apb_none; ahbso(0) <= ahbs_none; roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0)); end generate; mgpads : if (CFG_MCTRL_LEON2 /= 0) generate addr_pad : outpadv generic map (width => 22, tech => padtech) port map (address, memo.address(22 downto 1)); roms_pad : outpad generic map (tech => padtech) port map (romsn, memo.romsn(0)); oen_pad : outpad generic map (tech => padtech) port map (oen, memo.oen); wri_pad : outpad generic map (tech => padtech) port map (writen, memo.writen); -- pragma translate_off iosn_pad : outpad generic map (tech => padtech) port map (iosn, memo.iosn); tbdr : for i in 0 to 1 generate data_pad : iopadv generic map (tech => padtech, width => 8) port map (testdata(15-i8 downto 8-i8), memo.data(15-i8 downto 8-i8), memo.bdrive(i+2), memi.data(15-i8 downto 8-i8)); end generate; -- pragma translate_on bdr : for i in 0 to 1 generate data_pad : iopadv generic map (tech => padtech, width => 8) port map (data(15-i8 downto 8-i8), memo.data(31-i8 downto 24-i8), memo.bdrive(i), memi.data(31-i8 downto 24-i8)); end generate; end generate; ---------------------------------------------------------------------- --- DDR memory controller ------------------------------------------- ---------------------------------------------------------------------- ddrsp0 : if (CFG_DDRSP /= 0) generate ddrc : ddrspa generic map ( fabtech => virtex4, memtech => memtech, hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1, pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => -95 -- pragma translate_off * 0 -- disable clock skew during simulation -- pragma translate_on , clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16) port map ( rstneg, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(4), ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq); ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0); ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0); ddr_ad <= ddr_adl(12 downto 0); end generate; noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate; ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- ---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge generic map (hindex => 1, haddr => CFG_APBADDR) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); ua1 : if CFG_UART1_ENABLE /= 0 generate uart1 : apbuart -- UART 1 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO) port map (rstn, clkm, apbi, apbo(1), u1i, u1o); u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd; end generate; noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; irqctrl : if CFG_IRQ3_ENABLE /= 0 generate irqctrl0 : irqmp -- interrupt controller generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) port map (rstn, clkm, apbi, apbo(2), irqo, irqi); end generate; irq3 : if CFG_IRQ3_ENABLE = 0 generate x : for i in 0 to CFG_NCPU-1 generate irqi(i).irl <= "0000"; end generate; apbo(2) <= apb_none; end generate; gpt : if CFG_GPT_ENABLE /= 0 generate timer0 : gptimer -- timer unit generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW) port map (rstn, clkm, apbi, apbo(3), gpti, open); gpti <= gpti_dhalt_drive(dsuo.tstop); end generate; notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit grgpio0: grgpio generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12 --CFG_GRGPIO_WIDTH ) port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); disp_csn_pad : outpad generic map (tech => padtech) port map (disp_csn, gpioo.dout(8)); disp_dcn_pad : outpad generic map (tech => padtech) port map (disp_dcn, gpioo.dout(9)); disp_rdn_pad : outpad generic map (tech => padtech) port map (disp_rdn, gpioo.dout(10)); disp_wrn_pad : outpad generic map (tech => padtech) port map (disp_wrn, gpioo.dout(11)); disp_d_pads : for i in 0 to 7 generate pio_pad : iopad generic map (tech => padtech) port map (disp_d(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); end generate; end generate; ----------------------------------------------------------------------- --- ETHERNET --------------------------------------------------------- ----------------------------------------------------------------------- eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, pindex => 15, paddr => 15, pirq => 12, memtech => memtech, mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO, nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, phyrstadr => 3, giga => CFG_GRETH1G) port map( rst => rstn, clk => clkm, ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho); emdio_pad : iopad generic map (tech => padtech) port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i); etxc_pad : inpad generic map (tech => padtech) port map (etx_clk, ethi.tx_clk); erxc_pad : inpad generic map (tech => padtech) port map (erx_clk, ethi.rx_clk); erxd_pad : inpadv generic map (tech => padtech, width => 4) port map (erxd, ethi.rxd(3 downto 0)); erxdv_pad : inpad generic map (tech => padtech) port map (erx_dv, ethi.rx_dv); erxer_pad : inpad generic map (tech => padtech) port map (erx_er, ethi.rx_er); erxco_pad : inpad generic map (tech => padtech) port map (erx_col, ethi.rx_col); erxcr_pad : inpad generic map (tech => padtech) port map (erx_crs, ethi.rx_crs); etxd_pad : outpadv generic map (tech => padtech, width => 4) port map (etxd, etho.txd(3 downto 0)); etxen_pad : outpad generic map (tech => padtech) port map (etx_en, etho.tx_en); etxer_pad : outpad generic map (tech => padtech) port map (etx_er, etho.tx_er); emdc_pad : outpad generic map (tech => padtech) port map (emdc, etho.mdc); erstn_pad : outpad generic map (tech => padtech) port map (erstn, rstn); end generate; ----------------------------------------------------------------------- --- AHB DMA ---------------------------------------------------------- ----------------------------------------------------------------------- -- dma0 : ahbdma -- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH, -- pindex => 12, paddr => 12, dbuf => 32) -- port map (rstn, clkm, apbi, apbo(12), ahbmi, -- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH)); -- -- at0 : ahbtrace -- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#, -- tech => memtech, irq => 0, kbytes => 8) -- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7)); ----------------------------------------------------------------------- --- AHB ROM ---------------------------------------------------------- ----------------------------------------------------------------------- bpromgen : if CFG_AHBROMEN /= 0 generate brom : entity work.ahbrom generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP) port map ( rstn, clkm, ahbsi, ahbso(6)); end generate; nobpromgen : if CFG_AHBROMEN = 0 generate ahbso(6) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- AHB RAM ---------------------------------------------------------- ----------------------------------------------------------------------- ahbramgen : if CFG_AHBRAMEN = 1 generate ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ) port map (rstn, clkm, ahbsi, ahbso(3)); end generate; nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- Drive unused bus elements --------------------------------------- ----------------------------------------------------------------------- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate ahbmo(i) <= ahbm_none; end generate; -- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate; -- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate; resoutn <= rstn; ----------------------------------------------------------------------- --- Boot message ---------------------------------------------------- ----------------------------------------------------------------------- -- pragma translate_off x : report_design generic map ( msg1 => "LEON3 MP Demonstration design for Avnet Virtex4 Eval board", fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1 ); -- pragma translate_on -- use switch 1 to multiplex DSU UART and UART1 dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, ldsuen); duart <= rdsuen when CFG_AHB_UART /= 0 else '0'; rxd1 <= txd1 when duart = '1' else rserrx; rsertx <= duo.txd when duart = '1' else txd1; dui.rxd <= rserrx when duart = '1' else '1'; led_rx <= not rserrx; p1 : process(clkm) begin if rising_edge(clkm) then sertx <= rsertx; rserrx <= serrx; rdsuen <= ldsuen; rtsn <= '0'; led_tx <= not rsertx; end if; end process; end rtl;
-- VHDL Entity R6502_TC.Core.symbol -- -- Created: -- by - eda.UNKNOWN (ENTW1) -- at - 14:13:52 08.03.2010 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY Core IS PORT( clk_clk_i : IN std_logic; d_i : IN std_logic_vector (7 DOWNTO 0); irq_n_i : IN std_logic; nmi_n_i : IN std_logic; rdy_i : IN std_logic; rst_rst_n_i : IN std_logic; so_n_i : IN std_logic; a_o : OUT std_logic_vector (15 DOWNTO 0); d_o : OUT std_logic_vector (7 DOWNTO 0); rd_o : OUT std_logic; sync_o : OUT std_logic; wr_n_o : OUT std_logic; wr_o : OUT std_logic ); -- Declarations END Core ; -- Jens-D. Gutschmidt Project: R6502_TC -- [email protected] -- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG -- -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version -- 3 of the License, or any later version. -- -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A -- PARTICULAR PURPOSE. See the GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- CVS Revisins History -- -- $Log: struct.bd,v $ -- <<-- more -->> -- Title: Core -- Path: R6502_TC/Core/struct -- Edited: by eda on 08 Feb 2010 -- -- VHDL Architecture R6502_TC.Core.struct -- -- Created: -- by - eda.UNKNOWN (ENTW1) -- at - 14:13:53 08.03.2010 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; LIBRARY R6502_TC; ARCHITECTURE struct OF Core IS -- Architecture declarations -- Internal signal declarations SIGNAL adr_nxt_pc_o_i : std_logic_vector(15 DOWNTO 0); SIGNAL adr_o_i : std_logic_vector(15 DOWNTO 0); SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0); SIGNAL adr_sp_o_i : std_logic_vector(15 DOWNTO 0); SIGNAL ch_a_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL ch_b_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL d_alu_n_o_i : std_logic; SIGNAL d_alu_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL d_alu_or_o_i : std_logic; SIGNAL d_regs_in_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL d_regs_out_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL ld_o_i : std_logic_vector(1 DOWNTO 0); SIGNAL ld_pc_o_i : std_logic; SIGNAL ld_sp_o_i : std_logic; SIGNAL load_regs_o_i : std_logic; SIGNAL nmi_o_i : std_logic; SIGNAL offset_o_i : std_logic_vector(15 DOWNTO 0); SIGNAL q_a_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL q_x_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL q_y_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL reg_0flag_o_i : std_logic; SIGNAL reg_1flag_o_i : std_logic; SIGNAL reg_7flag_o_i : std_logic; SIGNAL rst_nmi_o_i : std_logic; SIGNAL sel_pc_in_o_i : std_logic; SIGNAL sel_pc_val_o_i : std_logic_vector(1 DOWNTO 0); SIGNAL sel_rb_in_o_i : std_logic_vector(1 DOWNTO 0); SIGNAL sel_rb_out_o_i : std_logic_vector(1 DOWNTO 0); SIGNAL sel_reg_o_i : std_logic_vector(1 DOWNTO 0); SIGNAL sel_sp_as_o_i : std_logic; SIGNAL sel_sp_in_o_i : std_logic; -- Component Declarations COMPONENT FSM_Execution_Unit PORT ( adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0); adr_pc_i : IN std_logic_vector (15 DOWNTO 0); adr_sp_i : IN std_logic_vector (15 DOWNTO 0); clk_clk_i : IN std_logic ; d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 ); d_i : IN std_logic_vector ( 7 DOWNTO 0 ); d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 ); irq_n_i : IN std_logic ; nmi_i : IN std_logic ; q_a_i : IN std_logic_vector ( 7 DOWNTO 0 ); q_x_i : IN std_logic_vector ( 7 DOWNTO 0 ); q_y_i : IN std_logic_vector ( 7 DOWNTO 0 ); rdy_i : IN std_logic ; reg_0flag_i : IN std_logic ; reg_1flag_i : IN std_logic ; reg_7flag_i : IN std_logic ; rst_rst_n_i : IN std_logic ; so_n_i : IN std_logic ; a_o : OUT std_logic_vector (15 DOWNTO 0); adr_o : OUT std_logic_vector (15 DOWNTO 0); ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 ); ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 ); d_o : OUT std_logic_vector ( 7 DOWNTO 0 ); d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 ); ld_o : OUT std_logic_vector ( 1 DOWNTO 0 ); ld_pc_o : OUT std_logic ; ld_sp_o : OUT std_logic ; load_regs_o : OUT std_logic ; offset_o : OUT std_logic_vector ( 15 DOWNTO 0 ); rd_o : OUT std_logic ; rst_nmi_o : OUT std_logic ; sel_pc_in_o : OUT std_logic ; sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_sp_as_o : OUT std_logic ; sel_sp_in_o : OUT std_logic ; sync_o : OUT std_logic ; wr_n_o : OUT std_logic ; wr_o : OUT std_logic ); END COMPONENT; COMPONENT FSM_NMI PORT ( clk_clk_i : IN std_logic ; nmi_n_i : IN std_logic ; rst_nmi_i : IN std_logic ; rst_rst_n_i : IN std_logic ; nmi_o : OUT std_logic ); END COMPONENT; COMPONENT RegBank_AXY PORT ( clk_clk_i : IN std_logic ; d_regs_in_i : IN std_logic_vector (7 DOWNTO 0); load_regs_i : IN std_logic ; rst_rst_n_i : IN std_logic ; sel_rb_in_i : IN std_logic_vector (1 DOWNTO 0); sel_rb_out_i : IN std_logic_vector (1 DOWNTO 0); sel_reg_i : IN std_logic_vector (1 DOWNTO 0); d_regs_out_o : OUT std_logic_vector (7 DOWNTO 0); q_a_o : OUT std_logic_vector (7 DOWNTO 0); q_x_o : OUT std_logic_vector (7 DOWNTO 0); q_y_o : OUT std_logic_vector (7 DOWNTO 0) ); END COMPONENT; COMPONENT Reg_PC PORT ( adr_i : IN std_logic_vector (15 DOWNTO 0); clk_clk_i : IN std_logic ; ld_i : IN std_logic_vector (1 DOWNTO 0); ld_pc_i : IN std_logic ; offset_i : IN std_logic_vector (15 DOWNTO 0); rst_rst_n_i : IN std_logic ; sel_pc_in_i : IN std_logic ; sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0); adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0); adr_pc_o : OUT std_logic_vector (15 DOWNTO 0) ); END COMPONENT; COMPONENT Reg_SP PORT ( adr_low_i : IN std_logic_vector (7 DOWNTO 0); clk_clk_i : IN std_logic ; ld_low_i : IN std_logic ; ld_sp_i : IN std_logic ; rst_rst_n_i : IN std_logic ; sel_sp_as_i : IN std_logic ; sel_sp_in_i : IN std_logic ; adr_sp_o : OUT std_logic_vector (15 DOWNTO 0) ); END COMPONENT; -- Optional embedded configurations -- pragma synthesis_off FOR ALL : FSM_Execution_Unit USE ENTITY R6502_TC.FSM_Execution_Unit; FOR ALL : FSM_NMI USE ENTITY R6502_TC.FSM_NMI; FOR ALL : RegBank_AXY USE ENTITY R6502_TC.RegBank_AXY; FOR ALL : Reg_PC USE ENTITY R6502_TC.Reg_PC; FOR ALL : Reg_SP USE ENTITY R6502_TC.Reg_SP; -- pragma synthesis_on BEGIN -- ModuleWare code(v1.9) for instance 'U_11' of 'add' u_11combo_proc: PROCESS (ch_a_o_i, ch_b_o_i) VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0); VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0); VARIABLE temp_sum : unsigned(8 DOWNTO 0); VARIABLE temp_carry : std_logic; BEGIN temp_din0 := '0' & ch_a_o_i; temp_din1 := '0' & ch_b_o_i; temp_carry := '0'; temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; d_alu_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8); reg_0flag_o_i <= temp_sum(8) ; END PROCESS u_11combo_proc; -- ModuleWare code(v1.9) for instance 'U_8' of 'inv' reg_1flag_o_i <= NOT(d_alu_or_o_i); -- ModuleWare code(v1.9) for instance 'U_9' of 'inv' reg_7flag_o_i <= NOT(d_alu_n_o_i); -- ModuleWare code(v1.9) for instance 'U_10' of 'inv' d_alu_n_o_i <= NOT(d_alu_o_i(7)); -- ModuleWare code(v1.9) for instance 'U_7' of 'por' d_alu_or_o_i <= d_alu_o_i(0) OR d_alu_o_i(1) OR d_alu_o_i(2) OR d_alu_o_i(3) OR d_alu_o_i(4) OR d_alu_o_i(5) OR d_alu_o_i(6) OR d_alu_o_i(7); -- Instance port mappings. U_4 : FSM_Execution_Unit PORT MAP ( adr_nxt_pc_i => adr_nxt_pc_o_i, adr_pc_i => adr_pc_o_i, adr_sp_i => adr_sp_o_i, clk_clk_i => clk_clk_i, d_alu_i => d_alu_o_i, d_i => d_i, d_regs_out_i => d_regs_out_o_i, irq_n_i => irq_n_i, nmi_i => nmi_o_i, q_a_i => q_a_o_i, q_x_i => q_x_o_i, q_y_i => q_y_o_i, rdy_i => rdy_i, reg_0flag_i => reg_0flag_o_i, reg_1flag_i => reg_1flag_o_i, reg_7flag_i => reg_7flag_o_i, rst_rst_n_i => rst_rst_n_i, so_n_i => so_n_i, a_o => a_o, adr_o => adr_o_i, ch_a_o => ch_a_o_i, ch_b_o => ch_b_o_i, d_o => d_o, d_regs_in_o => d_regs_in_o_i, ld_o => ld_o_i, ld_pc_o => ld_pc_o_i, ld_sp_o => ld_sp_o_i, load_regs_o => load_regs_o_i, offset_o => offset_o_i, rd_o => rd_o, rst_nmi_o => rst_nmi_o_i, sel_pc_in_o => sel_pc_in_o_i, sel_pc_val_o => sel_pc_val_o_i, sel_rb_in_o => sel_rb_in_o_i, sel_rb_out_o => sel_rb_out_o_i, sel_reg_o => sel_reg_o_i, sel_sp_as_o => sel_sp_as_o_i, sel_sp_in_o => sel_sp_in_o_i, sync_o => sync_o, wr_n_o => wr_n_o, wr_o => wr_o ); U_6 : FSM_NMI PORT MAP ( clk_clk_i => clk_clk_i, nmi_n_i => nmi_n_i, rst_nmi_i => rst_nmi_o_i, rst_rst_n_i => rst_rst_n_i, nmi_o => nmi_o_i ); U_2 : RegBank_AXY PORT MAP ( clk_clk_i => clk_clk_i, d_regs_in_i => d_regs_in_o_i, load_regs_i => load_regs_o_i, rst_rst_n_i => rst_rst_n_i, sel_rb_in_i => sel_rb_in_o_i, sel_rb_out_i => sel_rb_out_o_i, sel_reg_i => sel_reg_o_i, d_regs_out_o => d_regs_out_o_i, q_a_o => q_a_o_i, q_x_o => q_x_o_i, q_y_o => q_y_o_i ); U_0 : Reg_PC PORT MAP ( adr_i => adr_o_i, clk_clk_i => clk_clk_i, ld_i => ld_o_i, ld_pc_i => ld_pc_o_i, offset_i => offset_o_i, rst_rst_n_i => rst_rst_n_i, sel_pc_in_i => sel_pc_in_o_i, sel_pc_val_i => sel_pc_val_o_i, adr_nxt_pc_o => adr_nxt_pc_o_i, adr_pc_o => adr_pc_o_i ); U_1 : Reg_SP PORT MAP ( adr_low_i => adr_o_i(7 DOWNTO 0), clk_clk_i => clk_clk_i, ld_low_i => ld_o_i(0), ld_sp_i => ld_sp_o_i, rst_rst_n_i => rst_rst_n_i, sel_sp_as_i => sel_sp_as_o_i, sel_sp_in_i => sel_sp_in_o_i, adr_sp_o => adr_sp_o_i ); END struct;
component soc_design is port ( clock_clk : in std_logic := 'X'; -- clk fpga_reset_n : in std_logic := 'X' -- reset_n ); end component soc_design; u0 : component soc_design port map ( clock_clk => CONNECTED_TO_clock_clk, -- clock.clk fpga_reset_n => CONNECTED_TO_fpga_reset_n -- fpga.reset_n );
---------------------------------------------------------------------------------------------------- -- ENTITY - GF(2^M) Binary polynomial divider -- Computes the g/h mod f IN GF(2**m) -- -- Ports: -- clk_i - Clock -- rst_i - Reset flag -- enable_i - Enable computation -- g_i - First input value -- h_i - Seccond input value -- z_o - Output value -- ready_o - Ready flag after computation -- -- Example: -- 1100101 / 1101 = 1001 -- -- BIT-SHIFT and XOR: -- 1100101 / 1101 = 1001 -- 1101 -- 0011 -- 0000 -- 0110 -- 0000 -- 1101 -- 1101 -- 0 Remainder -- -- Based on: -- http://arithmetic-circuits.org/finite-field/vhdl_Models/chapter10_codes/VHDL/K-163/binary_algorithm_polynomials.vhd -- -- Autor: Lennart Bublies (inf100434) -- Date: 22.06.2017 ---------------------------------------------------------------------------------------------------- ------------------------------------------------------------ -- GF(2^M) binary polynomial divider ------------------------------------------------------------ LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_unsigned.all; USE work.tld_ecdsa_package.all; ENTITY e_gf2m_divider IS GENERIC ( MODULO : std_logic_vector(M DOWNTO 0) := ONE ); PORT( -- Clock, reset and enable clk_i: IN std_logic; rst_i: IN std_logic; enable_i: IN std_logic; -- Input signals g_i: IN std_logic_vector(M-1 DOWNTO 0); h_i: IN std_logic_vector(M-1 DOWNTO 0); -- Output signals z_o: OUT std_logic_vector(M-1 DOWNTO 0); ready_o: OUT std_logic ); END e_gf2m_divider; ARCHITECTURE rtl of e_gf2m_divider IS -- Internal signals SIGNAL a : std_logic_vector(M DOWNTO 0); SIGNAL b, c, d, next_b, next_d: std_logic_vector(M-1 DOWNTO 0); SIGNAL alpha, beta, next_beta, dec_input: std_logic_vector(logM-1 DOWNTO 0); SIGNAL ce_ac, ce_bd, load, beta_non_negative, alpha_gt_beta, b_zero: std_logic; -- Define all available states type states IS RANGE 0 TO 4; SIGNAL current_state: states; BEGIN -- Load arguments for next computation registers_ac: PROCESS(clk_i) BEGIN IF clk_i'event and clk_i = '1' THEN -- First computation (global arguments) IF load = '1' THEN a <= MODULO; c <= (OTHERS => '0'); -- Seccond computation ELSIF ce_ac = '1' THEN a <= '0'&b; c <= d; END IF; END IF; END PROCESS registers_ac; registers_bd: PROCESS(clk_i) BEGIN IF clk_i'event and clk_i = '1' THEN -- First computation (input arguments) IF load = '1' THEN b <= h_i; d <= g_i; -- Seccond computation ELSIF ce_bd = '1' THEN b <= next_b; d <= next_d; END IF; END IF; END PROCESS registers_bd; register_alpha: PROCESS(clk_i) BEGIN IF clk_i'event and clk_i = '1' THEN -- First computation (input arguments) IF load = '1' THEN alpha <= conv_std_logic_vector(M, logM); -- Seccond computation ELSIF ce_ac = '1' THEN alpha <= beta; END IF; END IF; END PROCESS register_alpha; register_beta: PROCESS(clk_i) BEGIN IF clk_i'event and clk_i = '1' THEN -- First computation (input arguments) IF load = '1' THEN beta <= conv_std_logic_vector(M-1, logM); -- Seccond computation ELSIF ce_bd = '1' THEN beta <= next_beta; END IF; END IF; END PROCESS register_beta; -- Shift and Add -- IF b(0)=0 THEN -- next_b(i) = b(i+1) -- ELSIF b(0)=1 THEN -- next_b(i) = b(i+1) + a(i+1) -- ENDIF first_iteration: FOR i IN 0 TO M-2 GENERATE next_b(i) <= (b(0) and (b(i+1) xor a(i+1))) or (not(b(0)) and b(i+1)); END GENERATE; next_b(M-1) <= b(0) and a(M); -- Shift and Add -- IF b(0)=0 THEN -- next_d(i) = (MODULO(i+1)&next_d(M-1)) + d(i+1) ????? (MODULO(i+1)&next_d(M-1)) ????? -- ELSIF b(0)=1 THEN -- next_d(i) = (MODULO(i+1)&next_d(M-1)) + d(i+1) + c(i+1) ????? (MODULO(i+1)&next_d(M-1)) ????? -- ENDIF second_iteration: FOR i IN 0 TO M-2 GENERATE next_d(i) <= (MODULO(i+1) and next_d(M-1)) xor ((b(0) and (d(i+1) xor c(i+1))) or (not(b(0)) and d(i+1))); END GENERATE; next_d(M-1) <= (b(0) and (d(0) xor c(0))) or (not(b(0)) and d(0)); WITH ce_ac SELECT dec_input <= beta WHEN '0', alpha WHEN OTHERS; next_beta <= dec_input - 1; beta_non_negative <= '1' WHEN beta(logM-1) = '0' ELSE '0'; alpha_gt_beta <= '1' WHEN alpha > beta ELSE '0'; b_zero <= '1' WHEN b(0) = '0' ELSE '0'; -- Set output z_o <= c; -- State machine control_unit: PROCESS(clk_i, rst_i, current_state, beta_non_negative, alpha_gt_beta, b_zero) BEGIN -- Handle current state -- 0,1 : Default state -- 2 : Load input arguments -- 3,4 : Calculation... CASE current_state IS WHEN 0 TO 1 => ce_ac <= '0'; ce_bd <='0'; load <= '0'; ready_o <= '1'; WHEN 2 => ce_ac <= '0'; ce_bd <= '0'; load <= '1'; ready_o <= '0'; WHEN 3 => IF beta_non_negative = '0' THEN ce_ac <= '0'; ce_bd <= '0'; ELSIF b_zero = '1' THEN ce_ac <= '0'; ce_bd <= '1'; ELSIF alpha_gt_beta = '1' THEN ce_ac <= '1'; ce_bd <= '1'; ELSE ce_ac <= '0'; ce_bd <= '1'; END IF; load <= '0'; ready_o <='0'; WHEN 4 => ce_ac <= '0'; ce_bd <='0'; load <= '0'; ready_o <= '0'; END CASE; IF rst_i = '1' THEN -- Reset state if reset is high current_state <= 0; ELSIF clk_i'event and clk_i = '1' THEN -- Set next state CASE current_state IS WHEN 0 => IF enable_i = '0' THEN current_state <= 1; END IF; WHEN 1 => IF enable_i = '1' THEN current_state <= 2; END IF; WHEN 2 => current_state <= 3; WHEN 3 => IF beta_non_negative = '0' THEN current_state <= 4; END IF; WHEN 4 => current_state <= 0; END CASE; END IF; END PROCESS control_unit; END rtl;
------------------------------------------------------------------------------- --! @file asyncFifo-syn-a.vhd -- --! @brief The asynchronous Fifo architecture for Altera -- --! @details This is a dual clock fifo generated in Megawizard! -- ------------------------------------------------------------------------------- -- -- (c) B&R Industrial Automation GmbH, 2014 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --! use altera_mf library library altera_mf; use altera_mf.altera_mf_components.all; architecture syn of asyncFifo is begin theAlteraDcFifo : dcfifo generic map ( intended_device_family => "Cyclone IV E", lpm_width => gDataWidth, lpm_widthu => logDualis(gWordSize), lpm_numwords => gWordSize, lpm_showahead => "OFF", lpm_type => "DCFIFO", overflow_checking => "ON", underflow_checking => "ON", delay_rdusedw => 1, delay_wrusedw => 1, add_usedw_msb_bit => "OFF", rdsync_delaypipe => gSyncStages+2, wrsync_delaypipe => gSyncStages+2, use_eab => gMemRes, write_aclr_synch => "ON", read_aclr_synch => "ON", clocks_are_synchronized => "FALSE", add_ram_output_register => "ON" ) port map ( aclr => iAclr, data => iWrData, q => oRdData, rdclk => iRdClk, rdempty => oRdEmpty, rdfull => oRdFull, rdreq => iRdReq, rdusedw => oRdUsedw, wrclk => iWrClk, wrempty => oWrEmpty, wrfull => oWrFull, wrreq => iWrReq, wrusedw => oWrUsedw ); end architecture syn;
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 21:28:33 10/18/2017 -- Design Name: -- Module Name: C:/Users/Kalugy/Documents/xilinx/secondooooooooo/Tbfirstpartnew.vhd -- Project Name: secondooooooooo -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: firstrpart -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY Tbfirstpartnew IS END Tbfirstpartnew; ARCHITECTURE behavior OF Tbfirstpartnew IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT firstrpart PORT( Resetext : IN std_logic; Clkinext : IN std_logic; Adressext : OUT std_logic_vector(31 downto 0) ); END COMPONENT; --Inputs signal Resetext : std_logic := '0'; signal Clkinext : std_logic := '0'; --Outputs signal Adressext : std_logic_vector(31 downto 0); -- Clock period definitions constant Clkinext_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: firstrpart PORT MAP ( Resetext => Resetext, Clkinext => Clkinext, Adressext => Adressext ); -- Clock process definitions Clkinext_process :process begin Clkinext <= '0'; wait for Clkinext_period/2; Clkinext <= '1'; wait for Clkinext_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. Resetext <= '0'; wait for 100 ns; Resetext <= '1'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; -- insert stimulus here -- insert stimulus here wait; end process; END;
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 21:28:33 10/18/2017 -- Design Name: -- Module Name: C:/Users/Kalugy/Documents/xilinx/secondooooooooo/Tbfirstpartnew.vhd -- Project Name: secondooooooooo -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: firstrpart -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY Tbfirstpartnew IS END Tbfirstpartnew; ARCHITECTURE behavior OF Tbfirstpartnew IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT firstrpart PORT( Resetext : IN std_logic; Clkinext : IN std_logic; Adressext : OUT std_logic_vector(31 downto 0) ); END COMPONENT; --Inputs signal Resetext : std_logic := '0'; signal Clkinext : std_logic := '0'; --Outputs signal Adressext : std_logic_vector(31 downto 0); -- Clock period definitions constant Clkinext_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: firstrpart PORT MAP ( Resetext => Resetext, Clkinext => Clkinext, Adressext => Adressext ); -- Clock process definitions Clkinext_process :process begin Clkinext <= '0'; wait for Clkinext_period/2; Clkinext <= '1'; wait for Clkinext_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. Resetext <= '0'; wait for 100 ns; Resetext <= '1'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; -- insert stimulus here -- insert stimulus here wait; end process; END;
-- ------------------------------------------------------------- -- -- Entity Declaration for inst_bug_e -- -- Generated -- by: wig -- on: Thu Oct 6 12:55:50 2005 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_bug_e-e.vhd,v 1.1 2005/10/06 13:36:57 wig Exp $ -- $Date: 2005/10/06 13:36:57 $ -- $Log: inst_bug_e-e.vhd,v $ -- Revision 1.1 2005/10/06 13:36:57 wig -- New testcase or generics -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.37 , [email protected] -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_bug_e -- entity inst_bug_e is -- Generics: generic( -- Generated Generics for Entity inst_bug_e CHROMA_GROUP_DELAY2_G : integer := 1; CHROMA_GROUP_DELAY_G : integer := 12; CHROMA_LINE_DELAY2_G : integer := 3; CHROMA_LINE_DELAY_G : integer := 0; CHROMA_PIPE_DELAY2_G : integer := 2; CHROMA_PIPE_DELAY_G : integer := 1 -- End of Generated Generics for Entity inst_bug_e ); -- Generated Port Declaration: -- No Generated Port for Entity inst_bug_e end inst_bug_e; -- -- End of Generated Entity inst_bug_e -- -- --!End of Entity/ies -- --------------------------------------------------------------
entity tb_ret03 is end tb_ret03; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_ret03 is signal d : std_logic_vector (7 downto 0); signal r : integer; begin dut: entity work.ret03 port map (d, r); process begin d <= x"01"; wait for 1 ns; assert r = 0 severity failure; d <= x"1f"; wait for 1 ns; assert r = 4 severity failure; d <= x"e2"; wait for 1 ns; assert r = 7 severity failure; d <= x"00"; wait for 1 ns; assert r = -1 severity failure; wait; end process; end behav;
-- Company: ZPU4 generic memory interface CPU -- Engineer: Øyvind Harboe library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_arith.ALL; library work; use work.zpu_config.all; use work.zpupkg.all; entity zpu_core is Port ( clk : in std_logic; areset : in std_logic; enable : in std_logic; mem_req : out std_logic; mem_we : out std_logic; mem_ack : in std_logic; mem_read : in std_logic_vector(wordSize-1 downto 0); mem_write : out std_logic_vector(wordSize-1 downto 0); out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); interrupt : in std_logic; break : out std_logic; zpu_status : out std_logic_vector(63 downto 0)); end zpu_core; architecture behave of zpu_core is type InsnType is ( State_AddTop, State_Dup, State_DupStackB, State_Pop, State_Popdown, State_Add, State_Or, State_And, State_Store, State_AddSP, State_Shift, State_Nop, State_Im, State_LoadSP, State_StoreSP, State_Emulate, State_Load, State_PushPC, State_PushSP, State_PopPC, State_PopPCRel, State_Not, State_Flip, State_PopSP, State_Neqbranch, State_Eq, State_Loadb, State_Mult, State_Lessthan, State_Lessthanorequal, State_Ulessthanorequal, State_Ulessthan, State_Pushspadd, State_Call, State_Callpcrel, State_Sub, State_Break, State_Storeb, State_Interrupt, State_InsnFetch ); type StateType is ( State_Idle, -- using first state first on the list out of paranoia State_Load2, State_Popped, State_LoadSP2, State_LoadSP3, State_AddSP2, State_Fetch, State_Execute, State_Decode, State_Decode2, State_Resync, State_StoreSP2, State_Resync2, State_Resync3, State_Loadb2, State_Storeb2, State_Mult2, State_Mult3, State_Mult5, State_Mult6, State_Mult4, State_BinaryOpResult ); signal pc : std_logic_vector(maxAddrBitIncIO downto 0); signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal stackA : std_logic_vector(wordSize-1 downto 0); signal binaryOpResult : std_logic_vector(wordSize-1 downto 0); signal multResult2 : std_logic_vector(wordSize-1 downto 0); signal multResult3 : std_logic_vector(wordSize-1 downto 0); signal multResult : std_logic_vector(wordSize-1 downto 0); signal multA : std_logic_vector(wordSize-1 downto 0); signal multB : std_logic_vector(wordSize-1 downto 0); signal stackB : std_logic_vector(wordSize-1 downto 0); signal idim_flag : std_logic; signal busy : std_logic; signal mem_readEnable : std_logic; signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal mem_delayReadEnable : std_logic; signal mem_busy : std_logic; signal decodeWord : std_logic_vector(wordSize-1 downto 0); signal state : StateType; signal insn : InsnType; type InsnArray is array(0 to wordBytes-1) of InsnType; signal decodedOpcode : InsnArray; type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); signal opcode : OpcodeArray; signal begin_inst : std_logic; signal trace_opcode : std_logic_vector(7 downto 0); signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); signal out_mem_req : std_logic; signal inInterrupt : std_logic; -- state machine. begin zpu_status(maxAddrBitIncIO downto 0) <= trace_pc; zpu_status(31) <= '1'; zpu_status(39 downto 32) <= trace_opcode; zpu_status(40) <= '1' when (state = State_Idle) else '0'; zpu_status(62) <= '1'; traceFileGenerate: if Generate_Trace generate trace_file: trace port map ( clk => clk, begin_inst => begin_inst, pc => trace_pc, opcode => trace_opcode, sp => trace_sp, memA => trace_topOfStack, memB => trace_topOfStackB, busy => busy, intsp => (others => 'U') ); end generate; -- the memory subsystem will tell us one cycle later whether or -- not it is busy out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); mem_req <= out_mem_req; incSp <= sp + 1; incIncSp <= sp + 2; decSp <= sp - 1; mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy opcodeControl: process(clk, areset) variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); variable spOffset : std_logic_vector(4 downto 0); variable tSpOffset : std_logic_vector(4 downto 0); variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0); variable tNextState : InsnType; variable tDecodedOpcode : InsnArray; variable tMultResult : std_logic_vector(wordSize2-1 downto 0); begin if areset = '1' then state <= State_Idle; break <= '0'; sp <= spStart(maxAddrBitIncIO downto minAddrBit); pc <= (others => '0'); idim_flag <= '0'; begin_inst <= '0'; mem_we <= '0'; multA <= (others => '0'); multB <= (others => '0'); mem_writeMask <= (others => '1'); out_mem_req <= '0'; mem_addr <= (others => DontCareValue); mem_write <= (others => DontCareValue); inInterrupt <= '0'; elsif (clk'event and clk = '1') then -- we must multiply unconditionally to get pipelined multiplication tMultResult := multA multB; multResult3 <= multResult2; multResult2 <= multResult; multResult <= tMultResult(wordSize-1 downto 0); spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4); spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0); nextPC := pc + 1; -- prepare trace snapshot trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0))); trace_pc <= pc; trace_sp <= sp; trace_topOfStack <= stackA; trace_topOfStackB <= stackB; begin_inst <= '0'; -- we terminate the requeset as soon as we get acknowledge if mem_ack = '1' then out_mem_req <= '0'; mem_we <= '0'; end if; if interrupt='0' then inInterrupt <= '0'; -- no longer in an interrupt end if; case state is when State_Idle => if enable='1' then state <= State_Resync; end if; -- Initial state of ZPU, fetch top of stack + first instruction when State_Resync => if mem_busy='0' then mem_addr <= sp; out_mem_req <= '1'; state <= State_Resync2; end if; when State_Resync2 => if mem_busy='0' then stackA <= mem_read; mem_addr <= incSp; out_mem_req <= '1'; state <= State_Resync3; end if; when State_Resync3 => if mem_busy='0' then stackB <= mem_read; mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); out_mem_req <= '1'; state <= State_Decode; end if; when State_Decode => if mem_busy='0' then decodeWord <= mem_read; state <= State_Decode2; end if; when State_Decode2 => -- decode 4 instructions in parallel for i in 0 to wordBytes-1 loop tOpcode := decodeWord((wordBytes-1-i+1)8-1 downto (wordBytes-1-i)8); tSpOffset(4):=not tOpcode(4); tSpOffset(3 downto 0):=tOpcode(3 downto 0); opcode(i) <= tOpcode; if (tOpcode(7 downto 7)=OpCode_Im) then tNextState:=State_Im; elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then if tSpOffset = 0 then tNextState := State_Pop; elsif tSpOffset=1 then tNextState := State_PopDown; else tNextState :=State_StoreSP; end if; elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then if tSpOffset = 0 then tNextState :=State_Dup; elsif tSpOffset = 1 then tNextState :=State_DupStackB; else tNextState :=State_LoadSP; end if; elsif (tOpcode(7 downto 5)=OpCode_Emulate) then tNextState :=State_Emulate; if tOpcode(5 downto 0)=OpCode_Neqbranch then tNextState :=State_Neqbranch; elsif tOpcode(5 downto 0)=OpCode_Eq then tNextState :=State_Eq; elsif tOpcode(5 downto 0)=OpCode_Lessthan then tNextState :=State_Lessthan; elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then --tNextState :=State_Lessthanorequal; elsif tOpcode(5 downto 0)=OpCode_Ulessthan then tNextState :=State_Ulessthan; elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then --tNextState :=State_Ulessthanorequal; elsif tOpcode(5 downto 0)=OpCode_Loadb then tNextState :=State_Loadb; elsif tOpcode(5 downto 0)=OpCode_Mult then tNextState :=State_Mult; elsif tOpcode(5 downto 0)=OpCode_Storeb then tNextState :=State_Storeb; elsif tOpcode(5 downto 0)=OpCode_Pushspadd then tNextState :=State_Pushspadd; elsif tOpcode(5 downto 0)=OpCode_Callpcrel then tNextState :=State_Callpcrel; elsif tOpcode(5 downto 0)=OpCode_Call then --tNextState :=State_Call; elsif tOpcode(5 downto 0)=OpCode_Sub then tNextState :=State_Sub; elsif tOpcode(5 downto 0)=OpCode_PopPCRel then --tNextState :=State_PopPCRel; end if; elsif (tOpcode(7 downto 4)=OpCode_AddSP) then if tSpOffset = 0 then tNextState := State_Shift; elsif tSpOffset = 1 then tNextState := State_AddTop; else tNextState :=State_AddSP; end if; else case tOpcode(3 downto 0) is when OpCode_Nop => tNextState :=State_Nop; when OpCode_PushSP => tNextState :=State_PushSP; when OpCode_PopPC => tNextState :=State_PopPC; when OpCode_Add => tNextState :=State_Add; when OpCode_Or => tNextState :=State_Or; when OpCode_And => tNextState :=State_And; when OpCode_Load => tNextState :=State_Load; when OpCode_Not => tNextState :=State_Not; when OpCode_Flip => tNextState :=State_Flip; when OpCode_Store => tNextState :=State_Store; when OpCode_PopSP => tNextState :=State_PopSP; when others => tNextState := State_Break; end case; end if; tDecodedOpcode(i) := tNextState; end loop; insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0))); -- once we wrap, we need to fetch tDecodedOpcode(0) := State_InsnFetch; decodedOpcode <= tDecodedOpcode; state <= State_Execute; -- Each instruction must: -- -- 1. set idim_flag -- 2. increase pc if applicable -- 3. set next state if appliable -- 4. do it's operation when State_Execute => insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0))); case insn is when State_InsnFetch => state <= State_Fetch; when State_Im => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '1'; pc <= pc + 1; if idim_flag='1' then stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); else out_mem_req <= '1'; mem_we <= '1'; mem_addr <= incSp; mem_write <= stackB; stackB <= stackA; sp <= decSp; for i in wordSize-1 downto 7 loop stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6); end loop; stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); end if; else insn <= insn; end if; when State_StoreSP => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; state <= State_StoreSP2; out_mem_req <= '1'; mem_we <= '1'; mem_addr <= sp+spOffset; mem_write <= stackA; stackA <= stackB; sp <= incSp; else insn <= insn; end if; when State_LoadSP => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; state <= State_LoadSP2; sp <= decSp; out_mem_req <= '1'; mem_we <= '1'; mem_addr <= incSp; mem_write <= stackB; else insn <= insn; end if; when State_Emulate => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; sp <= decSp; out_mem_req <= '1'; mem_we <= '1'; mem_addr <= incSp; mem_write <= stackB; stackA <= (others => DontCareValue); stackA(maxAddrBitIncIO downto 0) <= pc + 1; stackB <= stackA; -- The emulate address is: -- 98 7654 3210 -- 0000 00aa aaa0 0000 pc <= (others => '0'); pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0); state <= State_Fetch; else insn <= insn; end if; when State_Callpcrel => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; stackA <= (others => DontCareValue); stackA(maxAddrBitIncIO downto 0) <= pc + 1; pc <= pc + stackA(maxAddrBitIncIO downto 0); state <= State_Fetch; else insn <= insn; end if; when State_Call => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; stackA <= (others => DontCareValue); stackA(maxAddrBitIncIO downto 0) <= pc + 1; pc <= stackA(maxAddrBitIncIO downto 0); state <= State_Fetch; else insn <= insn; end if; when State_AddSP => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; state <= State_AddSP2; out_mem_req <= '1'; mem_addr <= sp+spOffset; else insn <= insn; end if; when State_PushSP => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; sp <= decSp; stackA <= (others => '0'); stackA(maxAddrBitIncIO downto minAddrBit) <= sp; stackB <= stackA; out_mem_req <= '1'; mem_we <= '1'; mem_addr <= incSp; mem_write <= stackB; else insn <= insn; end if; when State_PopPC => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; pc <= stackA(maxAddrBitIncIO downto 0); sp <= incSp; out_mem_req <= '1'; mem_we <= '1'; mem_addr <= incSp; mem_write <= stackB; state <= State_Resync; else insn <= insn; end if; when State_PopPCRel => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; pc <= stackA(maxAddrBitIncIO downto 0) + pc; sp <= incSp; out_mem_req <= '1'; mem_we <= '1'; mem_addr <= incSp; mem_write <= stackB; state <= State_Resync; else insn <= insn; end if; when State_Add => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; stackA <= stackA + stackB; out_mem_req <= '1'; mem_addr <= incIncSp; sp <= incSp; state <= State_Popped; else insn <= insn; end if; when State_Sub => begin_inst <= '1'; idim_flag <= '0'; binaryOpResult <= stackB - stackA; state <= State_BinaryOpResult; when State_Pop => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; mem_addr <= incIncSp; out_mem_req <= '1'; sp <= incSp; stackA <= stackB; state <= State_Popped; else insn <= insn; end if; when State_PopDown => if mem_busy='0' then -- PopDown leaves top of stack unchanged begin_inst <= '1'; idim_flag <= '0'; mem_addr <= incIncSp; out_mem_req <= '1'; sp <= incSp; state <= State_Popped; else insn <= insn; end if; when State_Or => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; stackA <= stackA or stackB; out_mem_req <= '1'; mem_addr <= incIncSp; sp <= incSp; state <= State_Popped; else insn <= insn; end if; when State_And => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; stackA <= stackA and stackB; out_mem_req <= '1'; mem_addr <= incIncSp; sp <= incSp; state <= State_Popped; else insn <= insn; end if; when State_Eq => begin_inst <= '1'; idim_flag <= '0'; binaryOpResult <= (others => '0'); if (stackA=stackB) then binaryOpResult(0) <= '1'; end if; state <= State_BinaryOpResult; when State_Ulessthan => begin_inst <= '1'; idim_flag <= '0'; binaryOpResult <= (others => '0'); if (stackA<stackB) then binaryOpResult(0) <= '1'; end if; state <= State_BinaryOpResult; when State_Ulessthanorequal => begin_inst <= '1'; idim_flag <= '0'; binaryOpResult <= (others => '0'); if (stackA<=stackB) then binaryOpResult(0) <= '1'; end if; state <= State_BinaryOpResult; when State_Lessthan => begin_inst <= '1'; idim_flag <= '0'; binaryOpResult <= (others => '0'); if (signed(stackA)<signed(stackB)) then binaryOpResult(0) <= '1'; end if; state <= State_BinaryOpResult; when State_Lessthanorequal => begin_inst <= '1'; idim_flag <= '0'; binaryOpResult <= (others => '0'); if (signed(stackA)<=signed(stackB)) then binaryOpResult(0) <= '1'; end if; state <= State_BinaryOpResult; when State_Load => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; state <= State_Load2; mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); out_mem_req <= '1'; else insn <= insn; end if; when State_Dup => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; sp <= decSp; stackB <= stackA; mem_write <= stackB; mem_addr <= incSp; out_mem_req <= '1'; mem_we <= '1'; else insn <= insn; end if; when State_DupStackB => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; sp <= decSp; stackA <= stackB; stackB <= stackA; mem_write <= stackB; mem_addr <= incSp; out_mem_req <= '1'; mem_we <= '1'; else insn <= insn; end if; when State_Store => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); mem_write <= stackB; out_mem_req <= '1'; mem_we <= '1'; sp <= incIncSp; state <= State_Resync; else insn <= insn; end if; when State_PopSP => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; mem_write <= stackB; mem_addr <= incSp; out_mem_req <= '1'; mem_we <= '1'; sp <= stackA(maxAddrBitIncIO downto minAddrBit); state <= State_Resync; else insn <= insn; end if; when State_Nop => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; when State_Not => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; stackA <= not stackA; when State_Flip => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; for i in 0 to wordSize-1 loop stackA(i) <= stackA(wordSize-1-i); end loop; when State_AddTop => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; stackA <= stackA + stackB; when State_Shift => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); stackA(0) <= '0'; when State_Pushspadd => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; stackA <= (others => '0'); stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; when State_Neqbranch => -- branches are almost always taken as they form loops begin_inst <= '1'; idim_flag <= '0'; sp <= incIncSp; if (stackB/=0) then pc <= stackA(maxAddrBitIncIO downto 0) + pc; else pc <= pc + 1; end if; -- need to fetch stack again. state <= State_Resync; when State_Mult => begin_inst <= '1'; idim_flag <= '0'; multA <= stackA; multB <= stackB; state <= State_Mult2; when State_Break => report "Break instruction encountered" severity failure; break <= '1'; when State_Loadb => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; state <= State_Loadb2; mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); out_mem_req <= '1'; else insn <= insn; end if; when State_Storeb => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; state <= State_Storeb2; mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); out_mem_req <= '1'; else insn <= insn; end if; when others => -- sp <= (others => DontCareValue); report "Illegal instruction" severity failure; break <= '1'; end case; when State_StoreSP2 => if mem_busy='0' then mem_addr <= incSp; out_mem_req <= '1'; state <= State_Popped; end if; when State_LoadSP2 => if mem_busy='0' then state <= State_LoadSP3; out_mem_req <= '1'; mem_addr <= sp+spOffset+1; end if; when State_LoadSP3 => if mem_busy='0' then pc <= pc + 1; state <= State_Execute; stackB <= stackA; stackA <= mem_read; end if; when State_AddSP2 => if mem_busy='0' then pc <= pc + 1; state <= State_Execute; stackA <= stackA + mem_read; end if; when State_Load2 => if mem_busy='0' then stackA <= mem_read; pc <= pc + 1; state <= State_Execute; end if; when State_Loadb2 => if mem_busy='0' then stackA <= (others => '0'); stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))8); pc <= pc + 1; state <= State_Execute; end if; when State_Storeb2 => if mem_busy='0' then mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); mem_write <= mem_read; mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))8) <= stackB(7 downto 0) ; out_mem_req <= '1'; mem_we <= '1'; pc <= pc + 1; sp <= incIncSp; state <= State_Resync; end if; when State_Fetch => if mem_busy='0' then if interrupt='1' and inInterrupt='0' and idim_flag='0' then -- We got an interrupt inInterrupt <= '1'; sp <= decSp; out_mem_req <= '1'; mem_we <= '1'; mem_addr <= incSp; mem_write <= stackB; stackA <= (others => DontCareValue); stackA(maxAddrBitIncIO downto 0) <= pc; stackB <= stackA; pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address report "ZPU jumped to interrupt!" severity note; else mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); out_mem_req <= '1'; state <= State_Decode; end if; end if; when State_Mult2 => state <= State_Mult3; when State_Mult3 => state <= State_Mult4; when State_Mult4 => state <= State_Mult5; when State_Mult5 => stackA <= multResult3; state <= State_Mult6; when State_Mult6 => if mem_busy='0' then out_mem_req <= '1'; mem_addr <= incIncSp; sp <= incSp; state <= State_Popped; end if; when State_BinaryOpResult => if mem_busy='0' then -- NB!!!! we know that the memory isn't busy at this point!!!! out_mem_req <= '1'; mem_addr <= incIncSp; sp <= incSp; stackA <= binaryOpResult; state <= State_Popped; end if; when State_Popped => if mem_busy='0' then pc <= pc + 1; stackB <= mem_read; state <= State_Execute; end if; when others => -- sp <= (others => DontCareValue); report "Illegal state" severity failure; break <= '1'; end case; end if; end process; end behave;
-- EMACS settings: -- tab-width: 2; indent-tabs-mode: t -- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Martin Zabel -- Patrick Lehmann -- -- Module: Instantiate single-port memory on Altera FPGAs. -- -- Description: -- ------------------------------------ -- Quartus synthesis does not infer this RAM type correctly. -- Instead, altsyncram is instantiated directly. -- -- For further documentation see module "ocram_sp" -- (src/mem/ocram/ocram_sp.vhdl). -- -- License: -- ============================================================================ -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library altera_mf; use altera_mf.all; library PoC; use PoC.utils.all; use PoC.strings.all; entity ocram_sp_altera is generic ( A_BITS : positive; D_BITS : positive; FILENAME : STRING := "" ); port ( clk : in std_logic; ce : in std_logic; we : in std_logic; a : in unsigned(A_BITS-1 downto 0); d : in std_logic_vector(D_BITS-1 downto 0); q : out std_logic_vector(D_BITS-1 downto 0) ); end entity; architecture rtl of ocram_sp_altera is component altsyncram generic ( address_aclr_a : STRING; indata_aclr_a : STRING; init_file : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL; wrcontrol_aclr_a : STRING ); port ( clocken0 : in STD_LOGIC; wren_a : in STD_LOGIC; clock0 : in STD_LOGIC; address_a : in STD_LOGIC_VECTOR(widthad_a-1 downto 0); q_a : out STD_LOGIC_VECTOR(width_a-1 downto 0); data_a : in STD_LOGIC_VECTOR(width_a-1 downto 0) ); end component; constant DEPTH : positive := 2**A_BITS; constant INIT_FILE : STRING := ite((str_length(FILENAME) = 0), "UNUSED", FILENAME); signal a_sl : std_logic_vector(A_BITS-1 downto 0); begin a_sl <= std_logic_vector(a); mem : altsyncram generic map ( address_aclr_a => "NONE", indata_aclr_a => "NONE", init_file => INIT_FILE, intended_device_family => "Stratix", lpm_hint => "ENABLE_RUNTIME_MOD = NO", lpm_type => "altsyncram", numwords_a => DEPTH, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "UNREGISTERED", power_up_uninitialized => "FALSE", widthad_a => A_BITS, width_a => D_BITS, width_byteena_a => 1, wrcontrol_aclr_a => "NONE" ) port map ( clocken0 => ce, wren_a => we, clock0 => clk, address_a => a_sl, data_a => d, q_a => q ); end architecture;
-- EMACS settings: -- tab-width: 2; indent-tabs-mode: t -- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Martin Zabel -- Patrick Lehmann -- -- Module: Instantiate single-port memory on Altera FPGAs. -- -- Description: -- ------------------------------------ -- Quartus synthesis does not infer this RAM type correctly. -- Instead, altsyncram is instantiated directly. -- -- For further documentation see module "ocram_sp" -- (src/mem/ocram/ocram_sp.vhdl). -- -- License: -- ============================================================================ -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library altera_mf; use altera_mf.all; library PoC; use PoC.utils.all; use PoC.strings.all; entity ocram_sp_altera is generic ( A_BITS : positive; D_BITS : positive; FILENAME : STRING := "" ); port ( clk : in std_logic; ce : in std_logic; we : in std_logic; a : in unsigned(A_BITS-1 downto 0); d : in std_logic_vector(D_BITS-1 downto 0); q : out std_logic_vector(D_BITS-1 downto 0) ); end entity; architecture rtl of ocram_sp_altera is component altsyncram generic ( address_aclr_a : STRING; indata_aclr_a : STRING; init_file : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL; wrcontrol_aclr_a : STRING ); port ( clocken0 : in STD_LOGIC; wren_a : in STD_LOGIC; clock0 : in STD_LOGIC; address_a : in STD_LOGIC_VECTOR(widthad_a-1 downto 0); q_a : out STD_LOGIC_VECTOR(width_a-1 downto 0); data_a : in STD_LOGIC_VECTOR(width_a-1 downto 0) ); end component; constant DEPTH : positive := 2**A_BITS; constant INIT_FILE : STRING := ite((str_length(FILENAME) = 0), "UNUSED", FILENAME); signal a_sl : std_logic_vector(A_BITS-1 downto 0); begin a_sl <= std_logic_vector(a); mem : altsyncram generic map ( address_aclr_a => "NONE", indata_aclr_a => "NONE", init_file => INIT_FILE, intended_device_family => "Stratix", lpm_hint => "ENABLE_RUNTIME_MOD = NO", lpm_type => "altsyncram", numwords_a => DEPTH, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "UNREGISTERED", power_up_uninitialized => "FALSE", widthad_a => A_BITS, width_a => D_BITS, width_byteena_a => 1, wrcontrol_aclr_a => "NONE" ) port map ( clocken0 => ce, wren_a => we, clock0 => clk, address_a => a_sl, data_a => d, q_a => q ); end architecture;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; library work; use work.Display_Management_pkg.all; entity OSD_border is --=========================================================================== generic( enable_debug : boolean := true; resolution : string := "1920x1080@60Hz" ); port( ------globally routed signals------- pixel_Clock : in std_logic; Reset_n : in std_logic; --=========== Inputs ============== --------------- VGA ---------------- vga_in : in internal_video_type; --=========== Outputs ============== --------------- VGA ---------------- vga_out : out internal_video_type ); end OSD_border; architecture arch_OSD_border of OSD_border is --============================================ -- ============================= Parameters ====================================================== ------------ General Parameters ---------------- constant format : format_type := init_video_type(enable_debug, resolution); constant timing : timing_type := init_timing_type(format); constant shifted_border : natural := 0; -- ============================= End of the Parameters =========================================== signal visible_pixel : pixel_type; signal phase_adjust : internal_video_type; signal border_detected : boolean; signal on_border : boolean; begin --========================================================================================== -------------------------------------------------------------- -- Counter horizontal visible_pixel -------------------------------------------------------------- process (pixel_Clock) is begin if rising_edge(pixel_Clock) then if (Reset_n = '0') then visible_pixel.x <= to_unsigned(0, nbits_pixel); --Need for force the first sync signal and for not lose the first frame elsif (vga_in.H_sync = '1') then visible_pixel.x <= to_unsigned(0, nbits_pixel); elsif(vga_in.addressable_area = '1') then visible_pixel.x <= visible_pixel.x + to_unsigned(1, nbits_pixel); end if; end if; end process; -------------------------------------------------------------- -- Counter vertical visible_pixel -------------------------------------------------------------- process (pixel_Clock) is begin if rising_edge(pixel_Clock) then if (Reset_n = '0') then visible_pixel.y <= to_unsigned(0, nbits_pixel); --Need for force the first sync signal and for not lose the first frame elsif (vga_in.V_sync = '1') then visible_pixel.y <= to_unsigned(0, nbits_pixel); elsif (visible_pixel.x = (format.Hor_Addr_Time-1) ) then visible_pixel.y <= visible_pixel.y + to_unsigned(1, nbits_pixel); end if; end if; end process; -------------------------------------------------------------- -- Phase adjust -------------------------------------------------------------- --Writing Shortcut because All the signal are synchrone of the pixel_Clock ! on_border <= ( (visible_pixel.y = to_unsigned(0 + shifted_border, nbits_pixel)) or (visible_pixel.y = (format.Ver_Addr_Time-to_unsigned(1 + shifted_border, nbits_pixel)) ) -- horizontal border or (visible_pixel.x = to_unsigned(0 + shifted_border, nbits_pixel)) or (visible_pixel.x = (format.Hor_Addr_Time-to_unsigned(1 + shifted_border, nbits_pixel)) ) -- vertical border ); process (pixel_Clock) is begin if rising_edge(pixel_Clock) then phase_adjust <= vga_in; border_detected <= (on_border = true) and (vga_in.addressable_area = '1'); end if; end process; -------------------------------------------------------------- -- Color management while the Active Video periode -------------------------------------------------------------- process (pixel_Clock) is begin if rising_edge(pixel_Clock) then --When we are on the border if (border_detected = true) then vga_out.red <= (others => '0'); vga_out.green <= (others => '1'); vga_out.blue <= (others => '0'); vga_out.H_sync <= phase_adjust.H_sync; vga_out.V_sync <= phase_adjust.V_sync; vga_out.addressable_area <= phase_adjust.addressable_area; --otherwise do nothing else vga_out <= phase_adjust; end if; end if; end process; end arch_OSD_border;
-- ------------------------------------------------------------- -- -- Generated Configuration for ddrv4 -- -- Generated -- by: wig -- on: Mon Jul 18 15:56:34 2005 -- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: ddrv4-rtl-conf-c.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $ -- $Date: 2005/07/19 07:13:11 $ -- $Log: ddrv4-rtl-conf-c.vhd,v $ -- Revision 1.3 2005/07/19 07:13:11 wig -- Update testcases. Added highlow/nolowbus -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.36 , [email protected] -- (C) 2003 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/conf -- -- Start of Generated Configuration ddrv4_rtl_conf / ddrv4 -- configuration ddrv4_rtl_conf of ddrv4 is for rtl -- Generated Configuration for d_ls_hr : ddrv use configuration work.d_ls_hr_RTL_CONF; end for; for d_ls_min : ddrv use configuration work.d_ls_min_RTL_CONF; end for; for d_ms_hr : ddrv use configuration work.d_ms_hr_RTL_CONF; end for; for d_ms_min : ddrv use configuration work.d_ms_min_RTL_CONF; end for; for u_and_f : and_f use configuration work.u_and_f_RTL_CONF; end for; end for; end ddrv4_rtl_conf; -- -- End of Generated Configuration ddrv4_rtl_conf -- -- --!End of Configuration/ies -- --------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity cmp01 is port (l : std_logic_vector(3 downto 0); r : std_logic_vector(3 downto 0); eq : out std_logic; ne : out std_logic; lt : out std_logic; le : out std_logic; ge : out std_logic; gt : out std_logic); end cmp01; architecture behav of cmp01 is begin eq <= '1' when unsigned(l) = unsigned(r) else '0'; ne <= '1' when unsigned(l) /= unsigned(r) else '0'; lt <= '1' when unsigned(l) < unsigned(r) else '0'; le <= '1' when unsigned(l) <= unsigned(r) else '0'; gt <= '1' when unsigned(l) > unsigned(r) else '0'; ge <= '1' when unsigned(l) >= unsigned(r) else '0'; end behav;
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.0 -- IP Revision: 7 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_0; USE floating_point_v7_0.floating_point_v7_0; ENTITY HLS_accel_ap_dmul_4_max_dsp_64 IS PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ); END HLS_accel_ap_dmul_4_max_dsp_64; ARCHITECTURE HLS_accel_ap_dmul_4_max_dsp_64_arch OF HLS_accel_ap_dmul_4_max_dsp_64 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF HLS_accel_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_0 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF HLS_accel_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2014.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF HLS_accel_ap_dmul_4_max_dsp_64_arch : ARCHITECTURE IS "HLS_accel_ap_dmul_4_max_dsp_64,floating_point_v7_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF HLS_accel_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "HLS_accel_ap_dmul_4_max_dsp_64,floating_point_v7_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=4,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_0 GENERIC MAP ( C_XDEVICEFAMILY => "virtex7", C_HAS_ADD => 0, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 1, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 64, C_A_FRACTION_WIDTH => 53, C_B_WIDTH => 64, C_B_FRACTION_WIDTH => 53, C_C_WIDTH => 64, C_C_FRACTION_WIDTH => 53, C_RESULT_WIDTH => 64, C_RESULT_FRACTION_WIDTH => 53, C_COMPARE_OPERATION => 8, C_LATENCY => 4, C_OPTIMIZATION => 1, C_MULT_USAGE => 3, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 1, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 1, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 64, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 64, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 64, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 64, C_RESULT_TUSER_WIDTH => 1 ) PORT MAP ( aclk => aclk, aclken => aclken, aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => s_axis_b_tvalid, s_axis_b_tdata => s_axis_b_tdata, s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END HLS_accel_ap_dmul_4_max_dsp_64_arch;
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.0 -- IP Revision: 7 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_0; USE floating_point_v7_0.floating_point_v7_0; ENTITY HLS_accel_ap_dmul_4_max_dsp_64 IS PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ); END HLS_accel_ap_dmul_4_max_dsp_64; ARCHITECTURE HLS_accel_ap_dmul_4_max_dsp_64_arch OF HLS_accel_ap_dmul_4_max_dsp_64 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF HLS_accel_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_0 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF HLS_accel_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2014.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF HLS_accel_ap_dmul_4_max_dsp_64_arch : ARCHITECTURE IS "HLS_accel_ap_dmul_4_max_dsp_64,floating_point_v7_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF HLS_accel_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "HLS_accel_ap_dmul_4_max_dsp_64,floating_point_v7_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=4,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_0 GENERIC MAP ( C_XDEVICEFAMILY => "virtex7", C_HAS_ADD => 0, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 1, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 64, C_A_FRACTION_WIDTH => 53, C_B_WIDTH => 64, C_B_FRACTION_WIDTH => 53, C_C_WIDTH => 64, C_C_FRACTION_WIDTH => 53, C_RESULT_WIDTH => 64, C_RESULT_FRACTION_WIDTH => 53, C_COMPARE_OPERATION => 8, C_LATENCY => 4, C_OPTIMIZATION => 1, C_MULT_USAGE => 3, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 1, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 1, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 64, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 64, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 64, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 64, C_RESULT_TUSER_WIDTH => 1 ) PORT MAP ( aclk => aclk, aclken => aclken, aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => s_axis_b_tvalid, s_axis_b_tdata => s_axis_b_tdata, s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END HLS_accel_ap_dmul_4_max_dsp_64_arch;
---------------------------------------------------------------------------------- -- Engineer: Mike Field <[email protected]> -- -- Module Name: scrambler_all_channels - Behavioral -- Description: A x^16+x^5+x^4+x^3+1 LFSR scxrambler for DisplayPort -- -- Scrambler LFSR is reset when a K.28.0 passes through it, -- as per the DisplayPort spec. -- -- Verified against the table in Apprndix C of the "PCI Express Base -- Specification 2.1" which uses the same polynomial. -- -- Here are the first 32 output words when data values of "00" are scrambled: -- -- \| 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F -- ---+------------------------------------------------ -- 00 \| FF 17 C0 14 B2 E7 02 82 72 6E 28 A6 BE 6D BF 8D -- 10 \| BE 40 A7 E6 2C D3 E2 B2 07 02 77 2A CD 34 BE E0 -- ---------------------------------------------------------------------------------- -- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort ------------------------------------------------------------------------------------ -- The MIT License (MIT) -- -- Copyright (c) 2015 Michael Alan Field <[email protected]> -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. ------------------------------------------------------------------------------------ ----- Want to say thanks? ---------------------------------------------------------- ------------------------------------------------------------------------------------ -- -- This design has taken many hours - 3 months of work. I'm more than happy -- to share it if you can make use of it. It is released under the MIT license, -- so you are not under any onus to say thanks, but.... -- -- If you what to say thanks for this design either drop me an email, or how about -- trying PayPal to my email ([email protected])? -- -- Educational use - Enough for a beer -- Hobbyist use - Enough for a pizza -- Research use - Enough to take the family out to dinner -- Commercial use - A weeks pay for an engineer (I wish!) -------------------------------------------------------------------------------------- -- Ver \| Date \| Change --------+------------+--------------------------------------------------------------- -- 0.1 \| 2015-10-17 \| Initial Version ------------------------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity scrambler_all_channels is Port ( clk : in STD_LOGIC; bypass0 : in STD_LOGIC; bypass1 : in STD_LOGIC; in_data : in STD_LOGIC_VECTOR (71 downto 0); out_data : out STD_LOGIC_VECTOR (71 downto 0) := (others => '0')); end scrambler_all_channels; architecture Behavioral of scrambler_all_channels is type a_delay_line is array(0 to 7) of STD_LOGIC_VECTOR (17 downto 0); signal lfsr_state : STD_LOGIC_VECTOR (15 downto 0) := (others => '1'); constant SR : STD_LOGIC_VECTOR ( 8 downto 0) := "100011100"; -- K28.0 ia used to reset the scrambler signal scramble_delay : a_delay_line := (others => (others => '0')); begin process(clk) variable s0 : STD_LOGIC_VECTOR (15 downto 0); variable s1 : STD_LOGIC_VECTOR (15 downto 0); variable flipping : STD_LOGIC_VECTOR (17 downto 0); begin if rising_edge(clk) then s0 := lfsr_state; -- generate intermediate scrambler state if in_data(8 downto 0) = SR then s1 := x"FFFF"; else s1(0) := s0(8); s1(1) := s0(9); s1(2) := s0(10); s1(3) := s0(11) xor s0(8); s1(4) := s0(12) xor s0(8) xor s0(9); s1(5) := s0(13) xor s0(8) xor s0(9) xor s0(10); s1(6) := s0(14) xor s0(9) xor s0(10) xor s0(11); s1(7) := s0(15) xor s0(10) xor s0(11) xor s0(12); s1(8) := s0(0) xor s0(11) xor s0(12) xor s0(13); s1(9) := s0(1) xor s0(12) xor s0(13) xor s0(14); s1(10) := s0(2) xor s0(13) xor s0(14) xor s0(15); s1(11) := s0(3) xor s0(14) xor s0(15); s1(12) := s0(4) xor s0(15); s1(13) := s0(5); s1(14) := s0(6); s1(15) := s0(7); end if; -- Update scrambler state if in_data(17 downto 9) = SR then lfsr_state <= x"FFFF"; else lfsr_state(0) <= s1(8); lfsr_state(1) <= s1(9); lfsr_state(2) <= s1(10); lfsr_state(3) <= s1(11) xor s1(8); lfsr_state(4) <= s1(12) xor s1(8) xor s1(9); lfsr_state(5) <= s1(13) xor s1(8) xor s1(9) xor s1(10); lfsr_state(6) <= s1(14) xor s1(9) xor s1(10) xor s1(11); lfsr_state(7) <= s1(15) xor s1(10) xor s1(11) xor s1(12); lfsr_state(8) <= s1(0) xor s1(11) xor s1(12) xor s1(13); lfsr_state(9) <= s1(1) xor s1(12) xor s1(13) xor s1(14); lfsr_state(10) <= s1(2) xor s1(13) xor s1(14) xor s1(15); lfsr_state(11) <= s1(3) xor s1(14) xor s1(15); lfsr_state(12) <= s1(4) xor s1(15); lfsr_state(13) <= s1(5); lfsr_state(14) <= s1(6); lfsr_state(15) <= s1(7); end if; -------------------------------------------- -- Calculate a vector of bits to be flipped -------------------------------------------- if in_data(8) = '0' and bypass0 = '0' then flipping(8 downto 0) := '0' & s0(8) & s0(9) & s0(10) & s0(11) & s0(12) & s0(13) & s0(14) & s0(15); else flipping(8 downto 0) := (others => '0'); end if; if in_data(17) = '0' and bypass1 = '0' then flipping(17 downto 9) := '0' & s1(8) & s1(9) & s1(10) & s1(11) & s1(12) & s1(13) & s1(14) & s1(15); else flipping(17 downto 9) := (others => '0'); end if; -------------------------------------------- -- Apply vector to channel 0 -------------------------------------------- out_data <= in_data xor (flipping & flipping & flipping & flipping ); end if; end process; end Behavioral;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity sub_586 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(31 downto 0) ); end sub_586; architecture augh of sub_586 is signal carry_inA : std_logic_vector(33 downto 0); signal carry_inB : std_logic_vector(33 downto 0); signal carry_res : std_logic_vector(33 downto 0); begin -- To handle the CI input, the operation is '0' - CI -- If CI is not present, the operation is '0' - '0' carry_inA <= '0' & in_a & '0'; carry_inB <= '0' & in_b & '0'; -- Compute the result carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); -- Set the outputs result <= carry_res(32 downto 1); end architecture;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity sub_586 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(31 downto 0) ); end sub_586; architecture augh of sub_586 is signal carry_inA : std_logic_vector(33 downto 0); signal carry_inB : std_logic_vector(33 downto 0); signal carry_res : std_logic_vector(33 downto 0); begin -- To handle the CI input, the operation is '0' - CI -- If CI is not present, the operation is '0' - '0' carry_inA <= '0' & in_a & '0'; carry_inB <= '0' & in_b & '0'; -- Compute the result carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); -- Set the outputs result <= carry_res(32 downto 1); end architecture;
library ieee; use ieee.std_logic_1164.all; entity bshift is port ( left: in std_logic; -- '1' for left, '0' for right logical: in std_logic; -- '1' for logical, '0' for arithmetic shift: in std_logic_vector(4 downto 0); -- shift count input: in std_logic_vector (31 downto 0); output: out std_logic_vector (31 downto 0) ); end entity bshift; architecture logic of bshift is signal shift1l, shift2l, shift4l, shift8l, shift16l : std_logic_vector(31 downto 0); signal shift1r, shift2r, shift4r, shift8r, shift16r : std_logic_vector(31 downto 0); signal fill : std_logic_vector(31 downto 16); begin fill <= (others => input(31)) when logical = '0' else x"0000"; shift1l <= input(30 downto 0) & '0' when shift(0) = '1' else input; shift2l <= shift1l(29 downto 0) & "00" when shift(1) = '1' else shift1l; shift4l <= shift2l(27 downto 0) & x"0" when shift(2) = '1' else shift2l; shift8l <= shift4l(23 downto 0) & x"00" when shift(3) = '1' else shift4l; shift16l <= shift8l(15 downto 0) & x"0000" when shift(4) = '1' else shift8l; shift1r <= fill(31) & input(31 downto 1) when shift(0) = '1' else input; shift2r <= fill(31 downto 30) & shift1r(31 downto 2) when shift(1) = '1' else shift1r; shift4r <= fill(31 downto 28) & shift2r(31 downto 4) when shift(2) = '1' else shift2r; shift8r <= fill(31 downto 24) & shift4r(31 downto 8) when shift(3) = '1' else shift4r; shift16r <= fill(31 downto 16) & shift8r(31 downto 16) when shift(4) = '1' else shift8r; output <= shift16r when left = '0' else shift16l; end;
library ieee; use ieee.std_logic_1164.all; entity bshift is port ( left: in std_logic; -- '1' for left, '0' for right logical: in std_logic; -- '1' for logical, '0' for arithmetic shift: in std_logic_vector(4 downto 0); -- shift count input: in std_logic_vector (31 downto 0); output: out std_logic_vector (31 downto 0) ); end entity bshift; architecture logic of bshift is signal shift1l, shift2l, shift4l, shift8l, shift16l : std_logic_vector(31 downto 0); signal shift1r, shift2r, shift4r, shift8r, shift16r : std_logic_vector(31 downto 0); signal fill : std_logic_vector(31 downto 16); begin fill <= (others => input(31)) when logical = '0' else x"0000"; shift1l <= input(30 downto 0) & '0' when shift(0) = '1' else input; shift2l <= shift1l(29 downto 0) & "00" when shift(1) = '1' else shift1l; shift4l <= shift2l(27 downto 0) & x"0" when shift(2) = '1' else shift2l; shift8l <= shift4l(23 downto 0) & x"00" when shift(3) = '1' else shift4l; shift16l <= shift8l(15 downto 0) & x"0000" when shift(4) = '1' else shift8l; shift1r <= fill(31) & input(31 downto 1) when shift(0) = '1' else input; shift2r <= fill(31 downto 30) & shift1r(31 downto 2) when shift(1) = '1' else shift1r; shift4r <= fill(31 downto 28) & shift2r(31 downto 4) when shift(2) = '1' else shift2r; shift8r <= fill(31 downto 24) & shift4r(31 downto 8) when shift(3) = '1' else shift4r; shift16r <= fill(31 downto 16) & shift8r(31 downto 16) when shift(4) = '1' else shift8r; output <= shift16r when left = '0' else shift16l; end;
library ieee; use ieee.std_logic_1164.all; entity bshift is port ( left: in std_logic; -- '1' for left, '0' for right logical: in std_logic; -- '1' for logical, '0' for arithmetic shift: in std_logic_vector(4 downto 0); -- shift count input: in std_logic_vector (31 downto 0); output: out std_logic_vector (31 downto 0) ); end entity bshift; architecture logic of bshift is signal shift1l, shift2l, shift4l, shift8l, shift16l : std_logic_vector(31 downto 0); signal shift1r, shift2r, shift4r, shift8r, shift16r : std_logic_vector(31 downto 0); signal fill : std_logic_vector(31 downto 16); begin fill <= (others => input(31)) when logical = '0' else x"0000"; shift1l <= input(30 downto 0) & '0' when shift(0) = '1' else input; shift2l <= shift1l(29 downto 0) & "00" when shift(1) = '1' else shift1l; shift4l <= shift2l(27 downto 0) & x"0" when shift(2) = '1' else shift2l; shift8l <= shift4l(23 downto 0) & x"00" when shift(3) = '1' else shift4l; shift16l <= shift8l(15 downto 0) & x"0000" when shift(4) = '1' else shift8l; shift1r <= fill(31) & input(31 downto 1) when shift(0) = '1' else input; shift2r <= fill(31 downto 30) & shift1r(31 downto 2) when shift(1) = '1' else shift1r; shift4r <= fill(31 downto 28) & shift2r(31 downto 4) when shift(2) = '1' else shift2r; shift8r <= fill(31 downto 24) & shift4r(31 downto 8) when shift(3) = '1' else shift4r; shift16r <= fill(31 downto 16) & shift8r(31 downto 16) when shift(4) = '1' else shift8r; output <= shift16r when left = '0' else shift16l; end;
library ieee; use ieee.std_logic_1164.all; entity bshift is port ( left: in std_logic; -- '1' for left, '0' for right logical: in std_logic; -- '1' for logical, '0' for arithmetic shift: in std_logic_vector(4 downto 0); -- shift count input: in std_logic_vector (31 downto 0); output: out std_logic_vector (31 downto 0) ); end entity bshift; architecture logic of bshift is signal shift1l, shift2l, shift4l, shift8l, shift16l : std_logic_vector(31 downto 0); signal shift1r, shift2r, shift4r, shift8r, shift16r : std_logic_vector(31 downto 0); signal fill : std_logic_vector(31 downto 16); begin fill <= (others => input(31)) when logical = '0' else x"0000"; shift1l <= input(30 downto 0) & '0' when shift(0) = '1' else input; shift2l <= shift1l(29 downto 0) & "00" when shift(1) = '1' else shift1l; shift4l <= shift2l(27 downto 0) & x"0" when shift(2) = '1' else shift2l; shift8l <= shift4l(23 downto 0) & x"00" when shift(3) = '1' else shift4l; shift16l <= shift8l(15 downto 0) & x"0000" when shift(4) = '1' else shift8l; shift1r <= fill(31) & input(31 downto 1) when shift(0) = '1' else input; shift2r <= fill(31 downto 30) & shift1r(31 downto 2) when shift(1) = '1' else shift1r; shift4r <= fill(31 downto 28) & shift2r(31 downto 4) when shift(2) = '1' else shift2r; shift8r <= fill(31 downto 24) & shift4r(31 downto 8) when shift(3) = '1' else shift4r; shift16r <= fill(31 downto 16) & shift8r(31 downto 16) when shift(4) = '1' else shift8r; output <= shift16r when left = '0' else shift16l; end;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc871.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c01s03b01x00p12n01i00871pkg is constant low_number : integer := 0; constant hi_number : integer := 3; subtype hi_to_low_range is integer range low_number to hi_number; type boolean_vector is array (natural range <>) of boolean; type severity_level_vector is array (natural range <>) of severity_level; type integer_vector is array (natural range <>) of integer; type real_vector is array (natural range <>) of real; type time_vector is array (natural range <>) of time; type natural_vector is array (natural range <>) of natural; type positive_vector is array (natural range <>) of positive; type record_std_package is record a: boolean; b: bit; c:character; d:severity_level; e:integer; f:real; g:time; h:natural; i:positive; end record; type array_rec_std is array (natural range <>) of record_std_package; type four_value is ('Z','0','1','X'); --enumerated type constant C1 : boolean := true; constant C2 : bit := '1'; constant C3 : character := 's'; constant C4 : severity_level := note; constant C5 : integer := 3; constant C6 : real := 3.0; constant C7 : time := 3 ns; constant C8 : natural := 1; constant C9 : positive := 1; signal Sin1 : bit_vector(0 to 5) ; signal Sin2 : boolean_vector(0 to 5) ; signal Sin4 : severity_level_vector(0 to 5) ; signal Sin5 : integer_vector(0 to 5) ; signal Sin6 : real_vector(0 to 5) ; signal Sin7 : time_vector(0 to 5) ; signal Sin8 : natural_vector(0 to 5) ; signal Sin9 : positive_vector(0 to 5) ; signal Sin10: array_rec_std(0 to 5) ; end c01s03b01x00p12n01i00871pkg; use work.c01s03b01x00p12n01i00871pkg.all; entity test is port( sigin1 : in boolean ; sigout1 : out boolean ; sigin2 : in bit ; sigout2 : out bit ; sigin4 : in severity_level ; sigout4 : out severity_level ; sigin5 : in integer ; sigout5 : out integer ; sigin6 : in real ; sigout6 : out real ; sigin7 : in time ; sigout7 : out time ; sigin8 : in natural ; sigout8 : out natural ; sigin9 : in positive ; sigout9 : out positive ; sigin10 : in record_std_package ; sigout10 : out record_std_package ); end; architecture test of test is begin sigout1 <= sigin1; sigout2 <= sigin2; sigout4 <= sigin4; sigout5 <= sigin5; sigout6 <= sigin6; sigout7 <= sigin7; sigout8 <= sigin8; sigout9 <= sigin9; sigout10 <= sigin10; end; configuration testbench of test is for test end for; end; use work.c01s03b01x00p12n01i00871pkg.all; entity test1 is port( sigin1 : in boolean ; sigout1 : out boolean ; sigin2 : in bit ; sigout2 : out bit ; sigin4 : in severity_level ; sigout4 : out severity_level ; sigin5 : in integer ; sigout5 : out integer ; sigin6 : in real ; sigout6 : out real ; sigin7 : in time ; sigout7 : out time ; sigin8 : in natural ; sigout8 : out natural ; sigin9 : in positive ; sigout9 : out positive ; sigin10 : in record_std_package ; sigout10 : out record_std_package ); end; architecture test1 of test1 is begin sigout1 <= false; sigout2 <= '0'; sigout4 <= error; sigout5 <= 6; sigout6 <= 6.0; sigout7 <= 6 ns; sigout8 <= 6; sigout9 <= 6; sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6); end; configuration test1bench of test1 is for test1 end for; end; use work.c01s03b01x00p12n01i00871pkg.all; ENTITY c01s03b01x00p12n01i00871ent IS generic( zero : integer := 0; one : integer := 1; two : integer := 2; three: integer := 3; four : integer := 4; five : integer := 5; six : integer := 6; seven: integer := 7; eight: integer := 8; nine : integer := 9; fifteen:integer:= 15); port( dumy : inout bit_vector(zero to three)); END c01s03b01x00p12n01i00871ent; ARCHITECTURE c01s03b01x00p12n01i00871arch OF c01s03b01x00p12n01i00871ent IS component test port( sigin1 : in boolean ; sigout1 : out boolean ; sigin2 : in bit ; sigout2 : out bit ; sigin4 : in severity_level ; sigout4 : out severity_level ; sigin5 : in integer ; sigout5 : out integer ; sigin6 : in real ; sigout6 : out real ; sigin7 : in time ; sigout7 : out time ; sigin8 : in natural ; sigout8 : out natural ; sigin9 : in positive ; sigout9 : out positive ; sigin10 : in record_std_package ; sigout10 : out record_std_package ); end component; begin Sin1(zero) <='1'; Sin2(zero) <= true; Sin4(zero) <= note; Sin5(zero) <= 3; Sin6(zero) <= 3.0; Sin7(zero) <= 3 ns; Sin8(zero) <= 1; Sin9(zero) <= 1; Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9); K:block BEGIN T5 : test port map ( Sin2(4),Sin2(5), Sin1(4),Sin1(5), Sin4(4),Sin4(5), Sin5(4),Sin5(5), Sin6(4),Sin6(5), Sin7(4),Sin7(5), Sin8(4),Sin8(5), Sin9(4),Sin9(5), Sin10(4),Sin10(5) ); G: for i in zero to three generate T1:test port map ( Sin2(i),Sin2(i+1), Sin1(i),Sin1(i+1), Sin4(i),Sin4(i+1), Sin5(i),Sin5(i+1), Sin6(i),Sin6(i+1), Sin7(i),Sin7(i+1), Sin8(i),Sin8(i+1), Sin9(i),Sin9(i+1), Sin10(i),Sin10(i+1) ); end generate; end block; TESTING: PROCESS variable dumb : bit_vector(zero to three); BEGIN wait for 1 ns; assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure; assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure; assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure; assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure; assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure; assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure; assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure; assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure; assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure; assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure; assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure; assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure; assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure; assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure; assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure; assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure; assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure; assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure; assert NOT( Sin1(0) = sin1(4) and Sin2(0) = Sin2(4) and Sin4(0) = Sin4(4) and Sin5(0) = Sin5(4) and Sin6(0) = Sin6(4) and Sin7(0) = Sin7(4) and Sin8(0) = Sin8(4) and Sin9(0) = Sin9(4) and Sin10(0)= Sin10(4) and Sin1(5) = '0' and Sin2(5) = FALSE and Sin4(5) = error and Sin5(5) = 6 and Sin6(5) = 6.0 and Sin7(5) = 6 ns and Sin8(5) = 6 and Sin9(5) = 6 and Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6)) report "*PASSED TEST: c01s03b01x00p12n01i00871" severity NOTE; assert ( Sin1(0) = sin1(4) and Sin2(0) = Sin2(4) and Sin4(0) = Sin4(4) and Sin5(0) = Sin5(4) and Sin6(0) = Sin6(4) and Sin7(0) = Sin7(4) and Sin8(0) = Sin8(4) and Sin9(0) = Sin9(4) and Sin10(0)= Sin10(4) and Sin1(5) = '0' and Sin2(5) = FALSE and Sin4(5) = error and Sin5(5) = 6 and Sin6(5) = 6.0 and Sin7(5) = 6 ns and Sin8(5) = 6 and Sin9(5) = 6 and Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6)) report "*FAILED TEST: c01s03b01x00p12n01i00871 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index." severity ERROR; wait; END PROCESS TESTING; END c01s03b01x00p12n01i00871arch; configuration c01s03b01x00p12n01i00871cfg of c01s03b01x00p12n01i00871ent is for c01s03b01x00p12n01i00871arch for K for all:test use configuration work.test1bench; end for; for G(0 to 3) for T1 :test use configuration work.testbench; end for; end for; end for; end for; end;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc871.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c01s03b01x00p12n01i00871pkg is constant low_number : integer := 0; constant hi_number : integer := 3; subtype hi_to_low_range is integer range low_number to hi_number; type boolean_vector is array (natural range <>) of boolean; type severity_level_vector is array (natural range <>) of severity_level; type integer_vector is array (natural range <>) of integer; type real_vector is array (natural range <>) of real; type time_vector is array (natural range <>) of time; type natural_vector is array (natural range <>) of natural; type positive_vector is array (natural range <>) of positive; type record_std_package is record a: boolean; b: bit; c:character; d:severity_level; e:integer; f:real; g:time; h:natural; i:positive; end record; type array_rec_std is array (natural range <>) of record_std_package; type four_value is ('Z','0','1','X'); --enumerated type constant C1 : boolean := true; constant C2 : bit := '1'; constant C3 : character := 's'; constant C4 : severity_level := note; constant C5 : integer := 3; constant C6 : real := 3.0; constant C7 : time := 3 ns; constant C8 : natural := 1; constant C9 : positive := 1; signal Sin1 : bit_vector(0 to 5) ; signal Sin2 : boolean_vector(0 to 5) ; signal Sin4 : severity_level_vector(0 to 5) ; signal Sin5 : integer_vector(0 to 5) ; signal Sin6 : real_vector(0 to 5) ; signal Sin7 : time_vector(0 to 5) ; signal Sin8 : natural_vector(0 to 5) ; signal Sin9 : positive_vector(0 to 5) ; signal Sin10: array_rec_std(0 to 5) ; end c01s03b01x00p12n01i00871pkg; use work.c01s03b01x00p12n01i00871pkg.all; entity test is port( sigin1 : in boolean ; sigout1 : out boolean ; sigin2 : in bit ; sigout2 : out bit ; sigin4 : in severity_level ; sigout4 : out severity_level ; sigin5 : in integer ; sigout5 : out integer ; sigin6 : in real ; sigout6 : out real ; sigin7 : in time ; sigout7 : out time ; sigin8 : in natural ; sigout8 : out natural ; sigin9 : in positive ; sigout9 : out positive ; sigin10 : in record_std_package ; sigout10 : out record_std_package ); end; architecture test of test is begin sigout1 <= sigin1; sigout2 <= sigin2; sigout4 <= sigin4; sigout5 <= sigin5; sigout6 <= sigin6; sigout7 <= sigin7; sigout8 <= sigin8; sigout9 <= sigin9; sigout10 <= sigin10; end; configuration testbench of test is for test end for; end; use work.c01s03b01x00p12n01i00871pkg.all; entity test1 is port( sigin1 : in boolean ; sigout1 : out boolean ; sigin2 : in bit ; sigout2 : out bit ; sigin4 : in severity_level ; sigout4 : out severity_level ; sigin5 : in integer ; sigout5 : out integer ; sigin6 : in real ; sigout6 : out real ; sigin7 : in time ; sigout7 : out time ; sigin8 : in natural ; sigout8 : out natural ; sigin9 : in positive ; sigout9 : out positive ; sigin10 : in record_std_package ; sigout10 : out record_std_package ); end; architecture test1 of test1 is begin sigout1 <= false; sigout2 <= '0'; sigout4 <= error; sigout5 <= 6; sigout6 <= 6.0; sigout7 <= 6 ns; sigout8 <= 6; sigout9 <= 6; sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6); end; configuration test1bench of test1 is for test1 end for; end; use work.c01s03b01x00p12n01i00871pkg.all; ENTITY c01s03b01x00p12n01i00871ent IS generic( zero : integer := 0; one : integer := 1; two : integer := 2; three: integer := 3; four : integer := 4; five : integer := 5; six : integer := 6; seven: integer := 7; eight: integer := 8; nine : integer := 9; fifteen:integer:= 15); port( dumy : inout bit_vector(zero to three)); END c01s03b01x00p12n01i00871ent; ARCHITECTURE c01s03b01x00p12n01i00871arch OF c01s03b01x00p12n01i00871ent IS component test port( sigin1 : in boolean ; sigout1 : out boolean ; sigin2 : in bit ; sigout2 : out bit ; sigin4 : in severity_level ; sigout4 : out severity_level ; sigin5 : in integer ; sigout5 : out integer ; sigin6 : in real ; sigout6 : out real ; sigin7 : in time ; sigout7 : out time ; sigin8 : in natural ; sigout8 : out natural ; sigin9 : in positive ; sigout9 : out positive ; sigin10 : in record_std_package ; sigout10 : out record_std_package ); end component; begin Sin1(zero) <='1'; Sin2(zero) <= true; Sin4(zero) <= note; Sin5(zero) <= 3; Sin6(zero) <= 3.0; Sin7(zero) <= 3 ns; Sin8(zero) <= 1; Sin9(zero) <= 1; Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9); K:block BEGIN T5 : test port map ( Sin2(4),Sin2(5), Sin1(4),Sin1(5), Sin4(4),Sin4(5), Sin5(4),Sin5(5), Sin6(4),Sin6(5), Sin7(4),Sin7(5), Sin8(4),Sin8(5), Sin9(4),Sin9(5), Sin10(4),Sin10(5) ); G: for i in zero to three generate T1:test port map ( Sin2(i),Sin2(i+1), Sin1(i),Sin1(i+1), Sin4(i),Sin4(i+1), Sin5(i),Sin5(i+1), Sin6(i),Sin6(i+1), Sin7(i),Sin7(i+1), Sin8(i),Sin8(i+1), Sin9(i),Sin9(i+1), Sin10(i),Sin10(i+1) ); end generate; end block; TESTING: PROCESS variable dumb : bit_vector(zero to three); BEGIN wait for 1 ns; assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure; assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure; assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure; assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure; assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure; assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure; assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure; assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure; assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure; assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure; assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure; assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure; assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure; assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure; assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure; assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure; assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure; assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure; assert NOT( Sin1(0) = sin1(4) and Sin2(0) = Sin2(4) and Sin4(0) = Sin4(4) and Sin5(0) = Sin5(4) and Sin6(0) = Sin6(4) and Sin7(0) = Sin7(4) and Sin8(0) = Sin8(4) and Sin9(0) = Sin9(4) and Sin10(0)= Sin10(4) and Sin1(5) = '0' and Sin2(5) = FALSE and Sin4(5) = error and Sin5(5) = 6 and Sin6(5) = 6.0 and Sin7(5) = 6 ns and Sin8(5) = 6 and Sin9(5) = 6 and Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6)) report "*PASSED TEST: c01s03b01x00p12n01i00871" severity NOTE; assert ( Sin1(0) = sin1(4) and Sin2(0) = Sin2(4) and Sin4(0) = Sin4(4) and Sin5(0) = Sin5(4) and Sin6(0) = Sin6(4) and Sin7(0) = Sin7(4) and Sin8(0) = Sin8(4) and Sin9(0) = Sin9(4) and Sin10(0)= Sin10(4) and Sin1(5) = '0' and Sin2(5) = FALSE and Sin4(5) = error and Sin5(5) = 6 and Sin6(5) = 6.0 and Sin7(5) = 6 ns and Sin8(5) = 6 and Sin9(5) = 6 and Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6)) report "*FAILED TEST: c01s03b01x00p12n01i00871 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index." severity ERROR; wait; END PROCESS TESTING; END c01s03b01x00p12n01i00871arch; configuration c01s03b01x00p12n01i00871cfg of c01s03b01x00p12n01i00871ent is for c01s03b01x00p12n01i00871arch for K for all:test use configuration work.test1bench; end for; for G(0 to 3) for T1 :test use configuration work.testbench; end for; end for; end for; end for; end;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO64x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO64x64WC; ARCHITECTURE DPBSCFIFO64x64WC_arch OF DPBSCFIFO64x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF DPBSCFIFO64x64WC_arch : ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 64, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 64, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO64x64WC_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO64x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO64x64WC; ARCHITECTURE DPBSCFIFO64x64WC_arch OF DPBSCFIFO64x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF DPBSCFIFO64x64WC_arch : ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 64, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 64, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO64x64WC_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO64x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO64x64WC; ARCHITECTURE DPBSCFIFO64x64WC_arch OF DPBSCFIFO64x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF DPBSCFIFO64x64WC_arch : ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 64, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 64, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO64x64WC_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO64x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO64x64WC; ARCHITECTURE DPBSCFIFO64x64WC_arch OF DPBSCFIFO64x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF DPBSCFIFO64x64WC_arch : ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 64, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 64, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO64x64WC_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO64x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO64x64WC; ARCHITECTURE DPBSCFIFO64x64WC_arch OF DPBSCFIFO64x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF DPBSCFIFO64x64WC_arch : ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 64, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 64, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO64x64WC_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO64x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO64x64WC; ARCHITECTURE DPBSCFIFO64x64WC_arch OF DPBSCFIFO64x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF DPBSCFIFO64x64WC_arch : ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 64, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 64, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO64x64WC_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO64x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO64x64WC; ARCHITECTURE DPBSCFIFO64x64WC_arch OF DPBSCFIFO64x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF DPBSCFIFO64x64WC_arch : ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 64, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 64, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO64x64WC_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO64x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO64x64WC; ARCHITECTURE DPBSCFIFO64x64WC_arch OF DPBSCFIFO64x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF DPBSCFIFO64x64WC_arch : ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 64, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 64, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO64x64WC_arch;
-------------------------------------------------------------------------------- -- -- Title : ctrl_game_block.vhd -- Design : Example -- Author : Kapitanov -- Company : InSys -- -- Version : 1.0 -------------------------------------------------------------------------------- -- -- Description : Main game block for minesweeper -- -- -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.ctrl_types_pkg.key_data; use work.ctrl_types_pkg.data8x8; use work.ctrl_types_pkg.data3x8; use work.ctrl_types_pkg.array8x8; use work.ctrl_comp_pkg.all; entity ctrl_game_block is generic( constant yend : std_logic_vector(4 downto 0); --! Y end area constant ystart : std_logic_vector(4 downto 0); --! Y start area constant xend : std_logic_vector(6 downto 0); --! X end area constant xstart : std_logic_vector(6 downto 0) --! X start area ); port( -- system signals: clk : in std_logic; --! clock reset : in std_logic; --! system reset -- keyboard: push_keys : in key_data; --! ps/2 keys -- vga XoY coordinates: display : in std_logic; --! display enable x_char : in std_logic_vector(9 downto 0); --! X line: 0:79 y_char : in std_logic_vector(8 downto 0); --! Y line: 0:29 -- out color scheme: rgb : out std_logic_vector(2 downto 0); --! RGB data leds : out std_logic_vector(8 downto 1) --! 8 LEDs ); end ctrl_game_block; architecture ctrl_game_block of ctrl_game_block is function conv8x8to64 (data_in : array8x8) return std_logic_vector is variable vector64 : std_logic_vector(63 downto 0); begin x_loop8: for jj in 0 to 7 loop y_loop8 :for ii in 0 to 7 loop vector64(ii+jj*8) := data_in(jj)(ii); end loop; end loop; return vector64; end conv8x8to64; component ctrl_8x16_rom is port( clk : in std_logic; -- clock addr : in std_logic_vector(10 downto 0); -- ROM address 2^11 data : out std_logic_vector(7 downto 0) -- ROM data 1 byte ); end component; type game_fsm is (WAIT_START, PLAY, CHECK, GAME_OVER, RST); signal game_status : game_fsm; signal addr_rnd : std_logic_vector(4 downto 0):="00000"; signal show_field, show_bad_msg, display_text: std_logic; signal x_in : std_logic_vector(6 downto 0); signal y_in : std_logic_vector(4 downto 0); signal x_inz : std_logic_vector(6 downto 0); signal x_inzz : std_logic_vector(6 downto 0); signal y_inz : std_logic_vector(4 downto 0); signal y_inzz : std_logic_vector(4 downto 0); signal cnt_yy : std_logic_vector(2 downto 0); signal cnt_xx : std_logic_vector(2 downto 0); signal comp_yy : std_logic_vector(6 downto 0); signal comp_xx : std_logic_vector(4 downto 0); signal rgb1 : std_logic_vector(2 downto 0):="000"; signal rgb2 : std_logic_vector(2 downto 0):="000"; signal rgb3 : std_logic_vector(2 downto 0):="000"; signal rgb4 : std_logic_vector(2 downto 0):="000"; signal rgb5 : std_logic_vector(2 downto 0):="000"; signal kw, ks, ka, kd : std_logic; signal kenter : std_logic; signal kspace : std_logic; signal ky, kn : std_logic; signal kesc : std_logic; signal data_box : std_logic_vector(7 downto 0); signal cnt_mines : std_logic_vector(6 downto 0); signal show_disp : array8x8; signal show_dispz : std_logic_vector(63 downto 0); signal win, lose, game : std_logic; signal cntg : std_logic; signal cnt_flash : std_logic_vector(23 downto 0); begin ---------------- SUMMARY RGB ON DISPLAY ---------------- rgb <= rgb1 or rgb2 or rgb3 or rgb4 or rgb5; ---------------- KEYBOARD ---------------- kw <= push_keys.WSAD(3) after 1 ns when rising_edge(clk); ks <= push_keys.WSAD(2) after 1 ns when rising_edge(clk); ka <= push_keys.WSAD(0) after 1 ns when rising_edge(clk); kd <= push_keys.WSAD(1) after 1 ns when rising_edge(clk); ky <= push_keys.ky after 1 ns when rising_edge(clk); kn <= push_keys.kn after 1 ns when rising_edge(clk); kspace <= push_keys.Space after 1 ns when rising_edge(clk); kenter <= push_keys.Enter after 1 ns when rising_edge(clk); kesc <= push_keys.Esc after 1 ns when rising_edge(clk); ---------------- LEDS ON DISPLAY ---------------- leds(1) <= kenter; leds(2) <= kw or ks or ka or kd; leds(3) <= ky or kn; leds(4) <= show_field; leds(5) <= display; leds(6) <= cnt_flash(23); ---------------- MOVING COUNTERS ---------------- pr_start: process(reset, clk) is begin if reset = '0' then cnt_xx <= "000"; cnt_yy <= "000"; elsif rising_edge(clk) then case game_status is when PLAY => if kw = '1' then cnt_yy <= cnt_yy - 1; elsif ks = '1' then cnt_yy <= cnt_yy + 1; else null; end if; if ka = '1' then cnt_xx <= cnt_xx + 1; elsif kd = '1' then cnt_xx <= cnt_xx - 1; else null; end if; when RST \| GAME_OVER \| WAIT_START => cnt_xx <= "000"; cnt_yy <= "000"; when others => null; end case; end if; end process; comp_yy <= "0000" & cnt_yy; comp_xx <= "00" & cnt_xx; ---------------- XoY COORDINATES ---------------- x_in <= x_char(9 downto 3); y_in <= y_char(8 downto 4); x_inz <= x_in after 1 ns when rising_edge(clk); y_inz <= y_in after 1 ns when rising_edge(clk); x_inzz <= x_inz after 1 ns when rising_edge(clk); y_inzz <= y_inz after 1 ns when rising_edge(clk); ---------------- GLOABAL FSM ---------------- pr_game_status: process(clk, reset) is begin if reset = '0' then game_status <= WAIT_START; show_field <= '0'; show_bad_msg <= '0'; addr_rnd <= (others => '0'); display_text <= '0'; win <= '0'; lose <= '0'; game <= '0'; cntg <= '0'; cnt_flash <= (others => '0'); elsif rising_edge(clk) then case game_status is when WAIT_START => display_text <= '1'; show_bad_msg <= '0'; win <= '0'; game <= '0'; lose <= '0'; cntg <= '0'; addr_rnd <= addr_rnd + '1'; -- UNCOMMENT LATER!! if kspace = '1' then game_status <= PLAY; show_field <= '1'; end if; when PLAY => cntg <= '1'; if kesc = '1' then game_status <= WAIT_START; else if cnt_mines = "111000" then show_bad_msg <= '0'; game_status <= GAME_OVER; else if kenter = '1' then game_status <= CHECK; else null; end if; end if; end if; when CHECK => if (x_inzz = (xstart + comp_xx)) and (y_inzz = (ystart + comp_yy)) then if data_box = x"0F" then show_bad_msg <= '1'; game_status <= GAME_OVER; else game_status <= PLAY; end if; end if; when GAME_OVER => cnt_flash <= cnt_flash + '1'; if show_bad_msg = '1' then win <= '0'; lose <= '1'; else win <= '1'; lose <= '0'; end if; game <= '1'; if ky = '1' then game_status <= WAIT_START; elsif kn = '1' then game_status <= RST; else null; end if; when RST => cntg <= '0'; game <= '0'; win <= '0'; lose <= '0'; show_field <= '0'; display_text <= '0'; show_bad_msg <= '0'; cnt_flash <= (others => '0'); addr_rnd <= (others => '0'); when others => null; end case; end if; end process; pr_display8x8: process(clk, reset) is begin if reset = '0' then show_disp <= (others=>(others=>'0')); cnt_mines <= (others => '0'); show_dispz <= (others => '0'); elsif rising_edge(clk) then case game_status is when PLAY => if kenter = '1' then show_disp(conv_integer(cnt_xx))(conv_integer(cnt_yy)) <= '1'; else null; end if; -- x_loop: for ii in 0 to 62 loop -- show_dispz(ii+1) <= show_dispz(ii); -- end loop; -- show_dispz(0) <= '0'; show_dispz(63 downto 0) <= show_dispz(62 downto 0) & '0'; if show_dispz(63) = '1' then cnt_mines <= cnt_mines + '1'; else null; end if; when CHECK => show_dispz <= conv8x8to64(show_disp); cnt_mines <= (others => '0'); when RST \| GAME_OVER \| WAIT_START => show_dispz <= (others => '0'); show_disp <= (others=>(others=>'0')); cnt_mines <= (others => '0'); when others => null; end case; end if; end process; ---------------- COMPONENTS MAPPING ---------------- x_check: cl_check generic map( yend => yend, ystart => ystart, xend => xend, xstart => xstart ) port map( clk => clk, reset => reset, cnt_yy => cnt_yy, cnt_xx => cnt_xx, display => show_field, x_char => x_char, y_char => y_char, rgb => rgb1 ); x_mines: cl_mines generic map( yend => yend, ystart => ystart, xend => xend, xstart => xstart ) port map( clk => clk, reset => reset, addr_rnd => addr_rnd, show_disp => show_disp, display => show_field, x_char => x_char, y_char => y_char, data_out => data_box, rgb => rgb2 ); x_square: cl_square generic map( yend => yend, ystart => ystart, xend => xend, xstart => xstart ) port map( clk => clk, reset => reset, show_disp => show_disp, display => show_field, x_char => x_char, y_char => y_char, rgb => rgb3 ); x_borders: cl_borders generic map( yend => yend, ystart => ystart, xend => xend, xstart => xstart ) port map( clk => clk, reset => reset, display => show_field, x_char => x_char, y_char => y_char, rgb => rgb4 ); x_text: cl_text generic map( yend => yend, ystart => ystart, xend => xend, xstart => xstart ) port map( clk => clk, reset => reset, addr_rnd => addr_rnd, display => display_text, cntgames => cntg, win => win, lose => lose, game => game, flash => cnt_flash(23 downto 21), x_char => x_char, y_char => y_char, rgb => rgb5 ); end ctrl_game_block;
-- ------------------------------------------------------------- -- -- Generated Architecture Declaration for rtl of inst_a_e -- -- Generated -- by: wig -- on: Wed Jul 19 05:28:20 2006 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../logic.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_a_e-rtl-a.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $ -- $Date: 2006/07/19 07:35:16 $ -- $Log: inst_a_e-rtl-a.vhd,v $ -- Revision 1.4 2006/07/19 07:35:16 wig -- Updated testcases. -- -- -- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp -- -- Generator: mix_0.pl Revision: 1.46 , [email protected] -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/arch -- -- -- Start of Generated Architecture rtl of inst_a_e -- architecture rtl of inst_a_e is -- -- Generated Constant Declarations -- -- -- Generated Components -- --__I_SIMPLE_LOGIC__ inst_a_and --__I_SIMPLE_LOGIC__ inst_a_or --__I_SIMPLE_LOGIC__ inst_a_wire component inst_aa_e -- the aa instance -- No Generated Generics port ( -- Generated Port for Entity inst_aa_e and_i1_1 : out std_ulogic; and_i2_1 : out std_ulogic_vector(15 downto 0); or_i1_1 : out std_ulogic; or_i2_1 : out std_ulogic_vector(15 downto 0) -- End of Generated Port for Entity inst_aa_e ); end component; -- --------- component inst_ab_e -- the ab instance -- No Generated Generics port ( -- Generated Port for Entity inst_ab_e and_i1_2 : out std_ulogic; and_i1_3_p : out std_ulogic; and_i2_2 : out std_ulogic_vector(15 downto 0); and_i2_3_p : out std_ulogic_vector(15 downto 0); or_i1_2 : out std_ulogic; or_i1_3_p : out std_ulogic; or_i2_2 : out std_ulogic_vector(15 downto 0); or_i2_3_p : out std_ulogic_vector(15 downto 0) -- End of Generated Port for Entity inst_ab_e ); end component; -- --------- -- -- Generated Signal List -- signal and_i1_1 : std_ulogic; signal and_i1_2 : std_ulogic; signal and_i1_3 : std_ulogic; signal and_i2_1 : std_ulogic_vector(15 downto 0); signal and_i2_2 : std_ulogic_vector(15 downto 0); signal and_i3_3 : std_ulogic_vector(15 downto 0); signal or_i1_1 : std_ulogic; signal or_i1_2 : std_ulogic; signal or_i1_3 : std_ulogic; signal or_i2_1 : std_ulogic_vector(15 downto 0); signal or_i2_2 : std_ulogic_vector(15 downto 0); signal or_i3_3 : std_ulogic_vector(15 downto 0); signal wire_bus_si : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ signal wire_bus_so : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ signal wire_si : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ signal wire_so : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ -- -- End of Generated Signal List -- begin -- -- Generated Concurrent Statements -- -- -- Generated Signal Assignments -- wire_bus_si <= wire_bus_i; -- __I_I_BUS_PORT wire_bus_o <= wire_bus_so; -- __I_O_BUS_PORT wire_si <= wire_i; -- __I_I_BIT_PORT wire_o <= wire_so; -- __I_O_BIT_PORT -- -- Generated Instances and Port Mappings -- -- Generated Logic for inst_a_and and_o1 <= and_i1_2 AND and_i1_1 AND and_i1_3; -- End of Generated Logic for inst_a_and -- Generated Logic for inst_a_and_1 and_o2 <= and_i2_2 AND and_i2_1 AND and_i3_3; -- End of Generated Logic for inst_a_and_1 -- Generated Logic for inst_a_or or_o1 <= or_i1_2 OR or_i1_3 OR or_i1_1; -- End of Generated Logic for inst_a_or -- Generated Logic for inst_a_or_1 or_o2 <= or_i2_2 OR or_i2_1 OR or_i3_3; -- End of Generated Logic for inst_a_or_1 -- Generated Logic for inst_a_wire wire_so <= wire_si; -- End of Generated Logic for inst_a_wire -- Generated Logic for inst_a_wire_1 wire_bus_so <= wire_bus_si; -- End of Generated Logic for inst_a_wire_1 -- Generated Instance Port Map for inst_aa_i inst_aa_i: inst_aa_e -- the aa instance port map ( and_i1_1 => and_i1_1, and_i2_1 => and_i2_1, or_i1_1 => or_i1_1, or_i2_1 => or_i2_1 ); -- End of Generated Instance Port Map for inst_aa_i -- Generated Instance Port Map for inst_ab_i inst_ab_i: inst_ab_e -- the ab instance port map ( and_i1_2 => and_i1_2, and_i1_3_p => and_i1_3, and_i2_2 => and_i2_2, and_i2_3_p => and_i3_3, or_i1_2 => or_i1_2, or_i1_3_p => or_i1_3, or_i2_2 => or_i2_2, or_i2_3_p => or_i3_3 ); -- End of Generated Instance Port Map for inst_ab_i end rtl; -- --!End of Architecture/s -- --------------------------------------------------------------
-- -- my_fpga_test_gates.vhdl -- library ieee; use ieee.std_logic_1164.all; use work.tbmsgs.all; entity my_fpga_test_gates is end entity; architecture sim of my_fpga_test_gates is signal clk : std_logic := '0'; signal n_rst : std_logic := '0'; signal up : std_logic := '0'; signal dn : std_logic := '0'; signal cnt : std_logic_vector(31 downto 0); signal cnt_1k : std_logic_vector(3 downto 0); signal in1 : std_logic := '0'; signal in2 : std_logic := '0'; signal out1 : std_logic; signal out2 : std_logic; begin uut : entity work.my_fpga port map ( clk => clk, n_rst => n_rst, up => up, dn => dn, cnt => cnt, cnt_1k => cnt_1k, in1 => in1, in2 => in2, out1 => out1, out2 => out2 ); test : process begin testcase("my_fpga gates", 4); wait for 1 us; check(out1 = '0', "out1 should be '0'"); check(out2 = '0', "out2 should be '0'"); tested("inputs set to 00"); in1 <= '1'; wait for 1 us; check(out1 = '1', "out1 should be '1'"); check(out2 = '0', "out2 should be '0'"); tested("inputs set to 01"); in2 <= '1'; wait for 1 us; check(out1 = '1', "out1 should be '1'"); check(out2 = '1', "out2 should be '1'"); tested("inputs set to 11"); in1 <= '0'; wait for 1 us; check(out1 = '1', "out1 should be '1'"); check(out2 = '0', "out2 should be '0'"); tested("inputs set to 10"); testcase_complete; wait; end process; end;
library IEEE; use IEEE.std_logic_1164.all; entity compara_zero_8bits is generic (N: integer := 10); port ( in_0,in_1: in std_logic_vector((N - 1) downto 0); out_0: out std_logic ); end entity; architecture circuito of compara_zero_8bits is begin compara_zero_8bits <= ( (in_0(0) xnor in_1(0)) and (in_0(1) xnor in_1(1)) and (in_0(2) xnor in_1(2)) and (in_0(3) xnor in_1(3)) and (in_0(4) xnor in_1(4)) and (in_0(5) xnor in_1(5)) and (in_0(6) xnor in_1(6)) and (in_0(7) xnor in_1(7)) ); end architecture;
----------------------------------------------------------------------------- --! @file --! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved. --! @author Sergey Khabarov --! @brief Network on Chip design top level. --! @details RISC-V "Rocket Core" based system with the AMBA AXI4 (NASTI) --! system bus and integrated peripheries. ------------------------------------------------------------------------------ --! Standard library library IEEE; use IEEE.STD_LOGIC_1164.ALL; --! Data transformation and math functions library library commonlib; use commonlib.types_common.all; --! Technology definition library. library techmap; --! Technology constants definition. use techmap.gencomp.all; --! "Virtual" PLL declaration. use techmap.types_pll.all; --! "Virtual" buffers declaration. use techmap.types_buf.all; --! AMBA system bus specific library library ambalib; --! AXI4 configuration constants. use ambalib.types_amba4.all; --! Rocket-chip specific library library rocketlib; --! SOC top-level component declaration. use rocketlib.types_rocket.all; --! Ethernet related declarations. use rocketlib.grethpkg.all; --! GNSS Sensor Ltd proprietary library library gnsslib; use gnsslib.types_gnss.all; --! Top-level implementaion library library work; --! Target dependable configuration: RTL, FPGA or ASIC. use work.config_target.all; --! Target independable configuration. use work.config_common.all; --! @brief SOC Top-level entity declaration. --! @details This module implements full SOC functionality and all IO signals --! are available on FPGA/ASIC IO pins. entity rocket_soc is port ( --! Input reset. Active High. Usually assigned to button "Center". i_rst : in std_logic; --! @name Clocks: --! @{ --! Differential clock (LVDS) positive signal. i_sclk_p : in std_logic; --! Differential clock (LVDS) negative signal. i_sclk_n : in std_logic; --! External ADC clock (default 26 MHz). i_clk_adc : in std_logic; --! @} --! @name User's IOs: --! @{ --! DIP switch. i_int_clkrf : in std_logic; i_dip : in std_logic_vector(3 downto 1); --! LEDs. o_led : out std_logic_vector(7 downto 0); --! @} --! @name UART1 signals: --! @{ i_uart1_ctsn : in std_logic; i_uart1_rd : in std_logic; o_uart1_td : out std_logic; o_uart1_rtsn : out std_logic; --! @} --! @name ADC channel A inputs (1575.4 GHz): --! @{ i_gps_I : in std_logic_vector(1 downto 0); i_gps_Q : in std_logic_vector(1 downto 0); --! @} --! @name ADC channel B inputs (1602 GHz): --! @{ i_glo_I : in std_logic_vector(1 downto 0); i_glo_Q : in std_logic_vector(1 downto 0); --! @} --! @name MAX2769 SPIs and antenna controls signals: --! @{ i_gps_ld : in std_logic; i_glo_ld : in std_logic; o_max_sclk : out std_logic; o_max_sdata : out std_logic; o_max_ncs : out std_logic_vector(1 downto 0); i_antext_stat : in std_logic; i_antext_detect : in std_logic; o_antext_ena : out std_logic; o_antint_contr : out std_logic; --! @} --! Ethernet MAC PHY interface signals --! @{ i_gmiiclk_p : in std_ulogic; i_gmiiclk_n : in std_ulogic; o_egtx_clk : out std_ulogic; i_etx_clk : in std_ulogic; i_erx_clk : in std_ulogic; i_erxd : in std_logic_vector(3 downto 0); i_erx_dv : in std_ulogic; i_erx_er : in std_ulogic; i_erx_col : in std_ulogic; i_erx_crs : in std_ulogic; i_emdint : in std_ulogic; o_etxd : out std_logic_vector(3 downto 0); o_etx_en : out std_ulogic; o_etx_er : out std_ulogic; o_emdc : out std_ulogic; io_emdio : inout std_logic; o_erstn : out std_ulogic ); --! @} end rocket_soc; --! @brief SOC top-level architecture declaration. architecture arch_rocket_soc of rocket_soc is --! @name Buffered in/out signals. --! @details All signals that are connected with in/out pads must be passed --! through the dedicated buffere modules. For FPGA they are implemented --! as an empty devices but ASIC couldn't be made without buffering. --! @{ signal ib_rst : std_logic; signal ib_sclk_p : std_logic; signal ib_sclk_n : std_logic; signal ib_clk_adc : std_logic; signal ib_dip : std_logic_vector(3 downto 0); signal ib_gmiiclk : std_logic; --! @} signal wSysReset : std_ulogic; -- Internal system reset. MUST NOT USED BY DEVICES. signal wReset : std_ulogic; -- Global reset active HIGH signal wNReset : std_ulogic; -- Global reset active LOW signal soft_rst : std_logic; -- reset from exteranl debugger signal bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW signal wClkBus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6) signal wClkAdc : std_ulogic; -- 26 MHz from the internal PLL signal wPllLocked : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked. signal uart1i : uart_in_type; signal uart1o : uart_out_type; --! Arbiter is switching only slaves output signal, data from noc --! is connected to all slaves and to the arbiter itself. signal aximi : nasti_master_in_type; signal aximo : nasti_master_out_type; signal axisi : nasti_slave_in_type; signal axiso : nasti_slave_out_type; signal slv_cfg : nasti_slave_cfg_vector; signal mst_cfg : nasti_master_cfg_vector; signal eth_i : eth_in_type; signal eth_o : eth_out_type; signal irq_pins : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0); begin --! PAD buffers: irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst); iclkp0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_p, i_sclk_p); iclkn0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_n, i_sclk_n); iclk1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_clk_adc, i_clk_adc); idip0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(0), i_int_clkrf); dipx : for i in 1 to 3 generate idipz : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(i), i_dip(i)); end generate; igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map ( i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk); --! @todo all other in/out signals via buffers: ------------------------------------ -- @brief Internal PLL device instance. pll0 : SysPLL_tech generic map ( tech => CFG_FABTECH, tmode_always_ena => CFG_TESTMODE_ON ) port map ( i_reset => ib_rst, i_int_clkrf => ib_dip(0), i_clkp => ib_sclk_p, i_clkn => ib_sclk_n, i_clk_adc => ib_clk_adc, o_clk_bus => wClkBus, o_clk_adc => wClkAdc, o_locked => wPllLocked ); wSysReset <= ib_rst or not wPllLocked; ------------------------------------ --! @brief System Reset device instance. rst0 : reset_global port map ( inSysReset => wSysReset, inSysClk => wClkBus, inPllLock => wPllLocked, outReset => wReset ); wNReset <= not wReset; bus_nrst <= not (wReset or soft_rst); aximi.grant <= "1"; aximi.aw_ready <= axiso.aw_ready; aximi.w_ready <= axiso.w_ready; aximi.b_valid <= axiso.b_valid; aximi.b_resp <= axiso.b_resp; aximi.b_id <= axiso.b_id; aximi.b_user <= axiso.b_user; aximi.ar_ready <= axiso.ar_ready; aximi.r_valid <= axiso.r_valid; aximi.r_resp <= axiso.r_resp; aximi.r_data <= axiso.r_data; aximi.r_last <= axiso.r_last; aximi.r_id <= axiso.r_id; aximi.r_user <= axiso.r_user; axisi.aw_valid <= aximo.aw_valid; axisi.aw_bits <= aximo.aw_bits; axisi.aw_id <= aximo.aw_id; axisi.aw_user <= aximo.aw_user; axisi.w_valid <= aximo.w_valid; axisi.w_data <= aximo.w_data; axisi.w_last <= aximo.w_last; axisi.w_strb <= aximo.w_strb; axisi.w_user <= aximo.w_user; axisi.b_ready <= aximo.b_ready; axisi.ar_valid <= aximo.ar_valid; axisi.ar_bits <= aximo.ar_bits; axisi.ar_id <= aximo.ar_id; axisi.ar_user <= aximo.ar_user; axisi.r_ready <= aximo.r_ready; ------------------------------------ --! @brief Controller of the LEDs, DIPs and GPIO with the AXI4 interface. --! @details Map address: --! 0x80000000..0x80000fff (4 KB total) gpio0 : nasti_gpio generic map ( xindex => CFG_NASTI_SLAVE_GPIO, xaddr => 16#80000#, xmask => 16#fffff# ) port map ( clk => wClkBus, nrst => wNReset, cfg => slv_cfg(CFG_NASTI_SLAVE_GPIO), i => axisi, o => axiso, i_dip => ib_dip, o_led => o_led ); --! Gigabit clock phase rotator with buffers clkrot90 : clkp90_tech generic map ( tech => CFG_FABTECH, freq => 125000 -- KHz = 125 MHz ) port map ( i_rst => wReset, i_clk => ib_gmiiclk, o_clk => eth_i.gtx_clk, o_clkp90 => eth_i.tx_clk_90, o_clk2x => open, -- used in gbe 'io_ref' o_lock => open ); --! @brief Ethernet MAC with the AXI4 interface. --! @details Map address: --! 0x80040000..0x8007ffff (256 KB total) --! EDCL IP: 192.168.0.51 = C0.A8.00.33 eth_i.tx_clk <= i_etx_clk; eth_i.rx_clk <= i_erx_clk; eth_i.rxd <= i_erxd; eth_i.rx_dv <= i_erx_dv; eth_i.rx_er <= i_erx_er; eth_i.rx_col <= i_erx_col; eth_i.rx_crs <= i_erx_crs; eth_i.mdint <= i_emdint; mac0 : grethaxi generic map ( xslvindex => CFG_NASTI_SLAVE_ETHMAC, xmstindex => CFG_NASTI_MASTER_ETHMAC, xaddr => 16#80040#, xmask => 16#FFFC0#, xirq => CFG_IRQ_ETHMAC, memtech => CFG_MEMTECH, mdcscaler => 60, --! System Bus clock in MHz enable_mdio => 1, fifosize => 16, nsync => 1, edcl => 1, edclbufsz => 16, macaddrh => 16#20789#, macaddrl => 16#123#, ipaddrh => 16#C0A8#, ipaddrl => 16#0033#, phyrstadr => 7, enable_mdint => 1, maxsize => 1518 ) port map ( rst => wNReset, clk => wClkBus, msti => aximi, msto => aximo, mstcfg => mst_cfg(CFG_NASTI_MASTER_ETHMAC), msto2 => open, -- EDCL separate access is disabled mstcfg2 => open, -- EDCL separate access is disabled slvi => axisi, slvo => open, slvcfg => slv_cfg(CFG_NASTI_SLAVE_ETHMAC), ethi => eth_i, etho => eth_o, irq => irq_pins(CFG_IRQ_ETHMAC) ); emdio_pad : iobuf_tech generic map( CFG_PADTECH ) port map ( o => eth_i.mdio_i, io => io_emdio, i => eth_o.mdio_o, t => eth_o.mdio_oe ); o_egtx_clk <= eth_i.gtx_clk;--eth_i.tx_clk_90; o_etxd <= eth_o.txd; o_etx_en <= eth_o.tx_en; o_etx_er <= eth_o.tx_er; o_emdc <= eth_o.mdc; o_erstn <= wNReset; end arch_rocket_soc;
----------------------------------------------------------------------------- --! @file --! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved. --! @author Sergey Khabarov --! @brief Network on Chip design top level. --! @details RISC-V "Rocket Core" based system with the AMBA AXI4 (NASTI) --! system bus and integrated peripheries. ------------------------------------------------------------------------------ --! Standard library library IEEE; use IEEE.STD_LOGIC_1164.ALL; --! Data transformation and math functions library library commonlib; use commonlib.types_common.all; --! Technology definition library. library techmap; --! Technology constants definition. use techmap.gencomp.all; --! "Virtual" PLL declaration. use techmap.types_pll.all; --! "Virtual" buffers declaration. use techmap.types_buf.all; --! AMBA system bus specific library library ambalib; --! AXI4 configuration constants. use ambalib.types_amba4.all; --! Rocket-chip specific library library rocketlib; --! SOC top-level component declaration. use rocketlib.types_rocket.all; --! Ethernet related declarations. use rocketlib.grethpkg.all; --! GNSS Sensor Ltd proprietary library library gnsslib; use gnsslib.types_gnss.all; --! Top-level implementaion library library work; --! Target dependable configuration: RTL, FPGA or ASIC. use work.config_target.all; --! Target independable configuration. use work.config_common.all; --! @brief SOC Top-level entity declaration. --! @details This module implements full SOC functionality and all IO signals --! are available on FPGA/ASIC IO pins. entity rocket_soc is port ( --! Input reset. Active High. Usually assigned to button "Center". i_rst : in std_logic; --! @name Clocks: --! @{ --! Differential clock (LVDS) positive signal. i_sclk_p : in std_logic; --! Differential clock (LVDS) negative signal. i_sclk_n : in std_logic; --! External ADC clock (default 26 MHz). i_clk_adc : in std_logic; --! @} --! @name User's IOs: --! @{ --! DIP switch. i_int_clkrf : in std_logic; i_dip : in std_logic_vector(3 downto 1); --! LEDs. o_led : out std_logic_vector(7 downto 0); --! @} --! @name UART1 signals: --! @{ i_uart1_ctsn : in std_logic; i_uart1_rd : in std_logic; o_uart1_td : out std_logic; o_uart1_rtsn : out std_logic; --! @} --! @name ADC channel A inputs (1575.4 GHz): --! @{ i_gps_I : in std_logic_vector(1 downto 0); i_gps_Q : in std_logic_vector(1 downto 0); --! @} --! @name ADC channel B inputs (1602 GHz): --! @{ i_glo_I : in std_logic_vector(1 downto 0); i_glo_Q : in std_logic_vector(1 downto 0); --! @} --! @name MAX2769 SPIs and antenna controls signals: --! @{ i_gps_ld : in std_logic; i_glo_ld : in std_logic; o_max_sclk : out std_logic; o_max_sdata : out std_logic; o_max_ncs : out std_logic_vector(1 downto 0); i_antext_stat : in std_logic; i_antext_detect : in std_logic; o_antext_ena : out std_logic; o_antint_contr : out std_logic; --! @} --! Ethernet MAC PHY interface signals --! @{ i_gmiiclk_p : in std_ulogic; i_gmiiclk_n : in std_ulogic; o_egtx_clk : out std_ulogic; i_etx_clk : in std_ulogic; i_erx_clk : in std_ulogic; i_erxd : in std_logic_vector(3 downto 0); i_erx_dv : in std_ulogic; i_erx_er : in std_ulogic; i_erx_col : in std_ulogic; i_erx_crs : in std_ulogic; i_emdint : in std_ulogic; o_etxd : out std_logic_vector(3 downto 0); o_etx_en : out std_ulogic; o_etx_er : out std_ulogic; o_emdc : out std_ulogic; io_emdio : inout std_logic; o_erstn : out std_ulogic ); --! @} end rocket_soc; --! @brief SOC top-level architecture declaration. architecture arch_rocket_soc of rocket_soc is --! @name Buffered in/out signals. --! @details All signals that are connected with in/out pads must be passed --! through the dedicated buffere modules. For FPGA they are implemented --! as an empty devices but ASIC couldn't be made without buffering. --! @{ signal ib_rst : std_logic; signal ib_sclk_p : std_logic; signal ib_sclk_n : std_logic; signal ib_clk_adc : std_logic; signal ib_dip : std_logic_vector(3 downto 0); signal ib_gmiiclk : std_logic; --! @} signal wSysReset : std_ulogic; -- Internal system reset. MUST NOT USED BY DEVICES. signal wReset : std_ulogic; -- Global reset active HIGH signal wNReset : std_ulogic; -- Global reset active LOW signal soft_rst : std_logic; -- reset from exteranl debugger signal bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW signal wClkBus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6) signal wClkAdc : std_ulogic; -- 26 MHz from the internal PLL signal wPllLocked : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked. signal uart1i : uart_in_type; signal uart1o : uart_out_type; --! Arbiter is switching only slaves output signal, data from noc --! is connected to all slaves and to the arbiter itself. signal aximi : nasti_master_in_type; signal aximo : nasti_master_out_type; signal axisi : nasti_slave_in_type; signal axiso : nasti_slave_out_type; signal slv_cfg : nasti_slave_cfg_vector; signal mst_cfg : nasti_master_cfg_vector; signal eth_i : eth_in_type; signal eth_o : eth_out_type; signal irq_pins : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0); begin --! PAD buffers: irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst); iclkp0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_p, i_sclk_p); iclkn0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_n, i_sclk_n); iclk1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_clk_adc, i_clk_adc); idip0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(0), i_int_clkrf); dipx : for i in 1 to 3 generate idipz : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(i), i_dip(i)); end generate; igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map ( i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk); --! @todo all other in/out signals via buffers: ------------------------------------ -- @brief Internal PLL device instance. pll0 : SysPLL_tech generic map ( tech => CFG_FABTECH, tmode_always_ena => CFG_TESTMODE_ON ) port map ( i_reset => ib_rst, i_int_clkrf => ib_dip(0), i_clkp => ib_sclk_p, i_clkn => ib_sclk_n, i_clk_adc => ib_clk_adc, o_clk_bus => wClkBus, o_clk_adc => wClkAdc, o_locked => wPllLocked ); wSysReset <= ib_rst or not wPllLocked; ------------------------------------ --! @brief System Reset device instance. rst0 : reset_global port map ( inSysReset => wSysReset, inSysClk => wClkBus, inPllLock => wPllLocked, outReset => wReset ); wNReset <= not wReset; bus_nrst <= not (wReset or soft_rst); aximi.grant <= "1"; aximi.aw_ready <= axiso.aw_ready; aximi.w_ready <= axiso.w_ready; aximi.b_valid <= axiso.b_valid; aximi.b_resp <= axiso.b_resp; aximi.b_id <= axiso.b_id; aximi.b_user <= axiso.b_user; aximi.ar_ready <= axiso.ar_ready; aximi.r_valid <= axiso.r_valid; aximi.r_resp <= axiso.r_resp; aximi.r_data <= axiso.r_data; aximi.r_last <= axiso.r_last; aximi.r_id <= axiso.r_id; aximi.r_user <= axiso.r_user; axisi.aw_valid <= aximo.aw_valid; axisi.aw_bits <= aximo.aw_bits; axisi.aw_id <= aximo.aw_id; axisi.aw_user <= aximo.aw_user; axisi.w_valid <= aximo.w_valid; axisi.w_data <= aximo.w_data; axisi.w_last <= aximo.w_last; axisi.w_strb <= aximo.w_strb; axisi.w_user <= aximo.w_user; axisi.b_ready <= aximo.b_ready; axisi.ar_valid <= aximo.ar_valid; axisi.ar_bits <= aximo.ar_bits; axisi.ar_id <= aximo.ar_id; axisi.ar_user <= aximo.ar_user; axisi.r_ready <= aximo.r_ready; ------------------------------------ --! @brief Controller of the LEDs, DIPs and GPIO with the AXI4 interface. --! @details Map address: --! 0x80000000..0x80000fff (4 KB total) gpio0 : nasti_gpio generic map ( xindex => CFG_NASTI_SLAVE_GPIO, xaddr => 16#80000#, xmask => 16#fffff# ) port map ( clk => wClkBus, nrst => wNReset, cfg => slv_cfg(CFG_NASTI_SLAVE_GPIO), i => axisi, o => axiso, i_dip => ib_dip, o_led => o_led ); --! Gigabit clock phase rotator with buffers clkrot90 : clkp90_tech generic map ( tech => CFG_FABTECH, freq => 125000 -- KHz = 125 MHz ) port map ( i_rst => wReset, i_clk => ib_gmiiclk, o_clk => eth_i.gtx_clk, o_clkp90 => eth_i.tx_clk_90, o_clk2x => open, -- used in gbe 'io_ref' o_lock => open ); --! @brief Ethernet MAC with the AXI4 interface. --! @details Map address: --! 0x80040000..0x8007ffff (256 KB total) --! EDCL IP: 192.168.0.51 = C0.A8.00.33 eth_i.tx_clk <= i_etx_clk; eth_i.rx_clk <= i_erx_clk; eth_i.rxd <= i_erxd; eth_i.rx_dv <= i_erx_dv; eth_i.rx_er <= i_erx_er; eth_i.rx_col <= i_erx_col; eth_i.rx_crs <= i_erx_crs; eth_i.mdint <= i_emdint; mac0 : grethaxi generic map ( xslvindex => CFG_NASTI_SLAVE_ETHMAC, xmstindex => CFG_NASTI_MASTER_ETHMAC, xaddr => 16#80040#, xmask => 16#FFFC0#, xirq => CFG_IRQ_ETHMAC, memtech => CFG_MEMTECH, mdcscaler => 60, --! System Bus clock in MHz enable_mdio => 1, fifosize => 16, nsync => 1, edcl => 1, edclbufsz => 16, macaddrh => 16#20789#, macaddrl => 16#123#, ipaddrh => 16#C0A8#, ipaddrl => 16#0033#, phyrstadr => 7, enable_mdint => 1, maxsize => 1518 ) port map ( rst => wNReset, clk => wClkBus, msti => aximi, msto => aximo, mstcfg => mst_cfg(CFG_NASTI_MASTER_ETHMAC), msto2 => open, -- EDCL separate access is disabled mstcfg2 => open, -- EDCL separate access is disabled slvi => axisi, slvo => open, slvcfg => slv_cfg(CFG_NASTI_SLAVE_ETHMAC), ethi => eth_i, etho => eth_o, irq => irq_pins(CFG_IRQ_ETHMAC) ); emdio_pad : iobuf_tech generic map( CFG_PADTECH ) port map ( o => eth_i.mdio_i, io => io_emdio, i => eth_o.mdio_o, t => eth_o.mdio_oe ); o_egtx_clk <= eth_i.gtx_clk;--eth_i.tx_clk_90; o_etxd <= eth_o.txd; o_etx_en <= eth_o.tx_en; o_etx_er <= eth_o.tx_er; o_emdc <= eth_o.mdc; o_erstn <= wNReset; end arch_rocket_soc;
LIBRARY IEEE; USE IEEE.std_logic_1164.all; PACKAGE RS232_test IS ------------------------------------------------------------------------------- -- Procedure for sending one byte over the RS232 serial input ------------------------------------------------------------------------------- procedure Transmit ( signal TX : out std_logic; -- serial line constant DATA : in std_logic_vector(7 downto 0)); -- byte to be sent ------------------------------------------------------------------------------- -- Procedure for receiving one byte from the RS232 serial output ------------------------------------------------------------------------------- procedure Receive ( signal RX : in std_logic; -- serial line signal DATA : out std_logic_vector(7 downto 0)); -- byte to be received END RS232_test; PACKAGE BODY RS232_test IS ----------------------------------------------------------------------------- -- Procedure for sending one byte over the RS232 serial input ----------------------------------------------------------------------------- procedure Transmit ( signal TX : out std_logic; -- serial output constant DATA : in std_logic_vector(7 downto 0)) is begin TX <= '0'; wait for 8680.6 ns; -- about to send byte for i in 0 to 7 loop TX <= DATA(i); wait for 8680.6 ns; end loop; -- i TX <= '1'; wait for 8680.6 ns; TX <= '1'; end Transmit; ------------------------------------------------------------------------------- -- Procedure for receiving one byte from the RS232 serial output ------------------------------------------------------------------------------- procedure Receive ( signal RX : in std_logic; -- serial line signal DATA : out std_logic_vector(7 downto 0)) is variable tmp : std_logic_vector(7 downto 0); begin while TRUE loop wait until RX='0'; wait for 13021 ns; for i in 0 to 7 loop tmp(i) := RX; wait for 8680.6 ns; end loop; --wait for 4340.3 ns; DATA <= tmp; end loop; end Receive; END RS232_test;
LIBRARY IEEE; USE IEEE.std_logic_1164.all; PACKAGE RS232_test IS ------------------------------------------------------------------------------- -- Procedure for sending one byte over the RS232 serial input ------------------------------------------------------------------------------- procedure Transmit ( signal TX : out std_logic; -- serial line constant DATA : in std_logic_vector(7 downto 0)); -- byte to be sent ------------------------------------------------------------------------------- -- Procedure for receiving one byte from the RS232 serial output ------------------------------------------------------------------------------- procedure Receive ( signal RX : in std_logic; -- serial line signal DATA : out std_logic_vector(7 downto 0)); -- byte to be received END RS232_test; PACKAGE BODY RS232_test IS ----------------------------------------------------------------------------- -- Procedure for sending one byte over the RS232 serial input ----------------------------------------------------------------------------- procedure Transmit ( signal TX : out std_logic; -- serial output constant DATA : in std_logic_vector(7 downto 0)) is begin TX <= '0'; wait for 8680.6 ns; -- about to send byte for i in 0 to 7 loop TX <= DATA(i); wait for 8680.6 ns; end loop; -- i TX <= '1'; wait for 8680.6 ns; TX <= '1'; end Transmit; ------------------------------------------------------------------------------- -- Procedure for receiving one byte from the RS232 serial output ------------------------------------------------------------------------------- procedure Receive ( signal RX : in std_logic; -- serial line signal DATA : out std_logic_vector(7 downto 0)) is variable tmp : std_logic_vector(7 downto 0); begin while TRUE loop wait until RX='0'; wait for 13021 ns; for i in 0 to 7 loop tmp(i) := RX; wait for 8680.6 ns; end loop; --wait for 4340.3 ns; DATA <= tmp; end loop; end Receive; END RS232_test;
------------------------------------------------------------------------------- -- Title : Dynamic adder/subtractor -- Project : ------------------------------------------------------------------------------- -- File : addsub.vhd -- Author : Aylons <[email protected]> -- Company : -- Created : 2014-05-03 -- Last update: 2015-10-15 -- Platform : -- Standard : VHDL'93/02/08 ------------------------------------------------------------------------------- -- Description: Depening on sub_i, result_o may be a_i + b_i or a_i - b_i. -- The three widths must all be the same. ------------------------------------------------------------------------------- -- This file is part of Concordic. -- -- Concordic is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- Concordic is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with Foobar. If not, see <http://www.gnu.org/licenses/>. -- Copyright (c) 2014 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2014-05-03 1.0 aylons Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- entity addsub is port ( a_i : in signed; b_i : in signed; sub_i : in boolean; clk_i : in std_logic; ce_i : in std_logic; rst_i : in std_logic; result_o : out signed; positive_o : out boolean; negative_o : out boolean ); end entity addsub; ------------------------------------------------------------------------------- architecture str of addsub is constant width : natural := a_i'length; signal a_1, b_1 : signed(width-1 downto 0) := (others => '0'); signal mux_result : signed (width-1 downto 0) := (others => '0'); begin -- architecture str assert a_i'length = b_i'length report "a_i and b_i have different widths" severity error; assert a_i'length = result_o'length report "invalid result_o width" severity error; process(clk_i) is variable result : signed(width-1 downto 0) := (others => '0'); begin if rising_edge(clk_i) then if rst_i = '1' then result_o <= (width-1 downto 0 => '0'); positive_o <= true; negative_o <= false; else if ce_i = '1' then result := mux_result; positive_o <= result(result'left) = '0'; negative_o <= result(result'left) = '1'; result_o <= result; end if; end if; end if; end process; mux_result <= a_i + b_i when (not sub_i) else a_i - b_i; end architecture str; -------------------------------------------------------------------------------
-- -- USB Full-Speed/Hi-Speed Device Controller core - ep1_loopback.vhdl -- -- Copyright (c) 2015 Konstantin Oblaukhov -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library work; use work.USBCore.all; use work.USBExtra.all; entity ep1_loopback is port ( led : out std_logic; ulpi_data : inout std_logic_vector(7 downto 0); ulpi_dir : in std_logic; ulpi_nxt : in std_logic; ulpi_stp : out std_logic; ulpi_reset : out std_logic; ulpi_clk60 : in std_logic; main_clk : in std_logic ); end ep1_loopback; architecture ep1_loopback of ep1_loopback is constant USE_HIGH_SPEED: boolean := true; constant CONFIG_DESC : BYTE_ARRAY(0 to 8) := ( X"09", -- bLength = 9 X"02", -- bDescriptionType = Configuration Descriptor X"20", X"00", -- wTotalLength = 32 X"01", -- bNumInterfaces = 1 X"01", -- bConfigurationValue X"00", -- iConfiguration X"C0", -- bmAttributes = Self-powered X"32" -- bMaxPower = 100 mA ); constant INTERFACE_DESC : BYTE_ARRAY(0 to 8) := ( X"09", -- bLength = 9 X"04", -- bDescriptorType = Interface Descriptor X"00", -- bInterfaceNumber = 0 X"00", -- bAlternateSetting X"02", -- bNumEndpoints = 2 X"00", -- bInterfaceClass X"00", -- bInterfaceSubClass X"00", -- bInterfaceProtocol X"00" -- iInterface ); constant EP1_IN_DESC : BYTE_ARRAY(0 to 6) := ( X"07", -- bLength = 7 X"05", -- bDescriptorType = Endpoint Descriptor X"81", -- bEndpointAddress = IN1 B"00_00_00_10", -- bmAttributes = Bulk X"00", X"02", -- wMaxPacketSize = 512 bytes X"00" -- bInterval ); constant EP1_OUT_DESC : BYTE_ARRAY(0 to 6) := ( X"07", -- bLength = 7 X"05", -- bDescriptorType = Endpoint Descriptor X"01", -- bEndpointAddress = OUT1 B"00_00_00_10", -- bmAttributes = Bulk X"00", X"02", -- wMaxPacketSize = 512 bytes X"00" -- bInterval ); signal ulpi_data_in : std_logic_vector(7 downto 0); signal ulpi_data_out : std_logic_vector(7 downto 0); signal usb_clk : std_logic; signal usb_reset : std_logic; signal usb_idle : std_logic; signal usb_suspend : std_logic; signal usb_configured : std_logic; signal usb_crc_error : std_logic; signal usb_sof : std_logic; signal ctl_xfer_endpoint : std_logic_vector(3 downto 0); signal ctl_xfer_type : std_logic_vector(7 downto 0); signal ctl_xfer_request : std_logic_vector(7 downto 0); signal ctl_xfer_value : std_logic_vector(15 downto 0); signal ctl_xfer_index : std_logic_vector(15 downto 0); signal ctl_xfer_length : std_logic_vector(15 downto 0); signal ctl_xfer_accept : std_logic; signal ctl_xfer : std_logic; signal ctl_xfer_done : std_logic; signal ctl_xfer_data_out : std_logic_vector(7 downto 0); signal ctl_xfer_data_out_valid: std_logic; signal ctl_xfer_data_in : std_logic_vector(7 downto 0); signal ctl_xfer_data_in_valid : std_logic; signal ctl_xfer_data_in_last : std_logic; signal ctl_xfer_data_in_ready : std_logic; signal blk_xfer_endpoint : std_logic_vector(3 downto 0); signal blk_in_xfer : std_logic; signal blk_out_xfer : std_logic; signal blk_xfer_in_has_data : std_logic; signal blk_xfer_in_data : std_logic_vector(7 downto 0); signal blk_xfer_in_data_valid : std_logic; signal blk_xfer_in_data_ready : std_logic; signal blk_xfer_in_data_last : std_logic; signal blk_xfer_out_ready_read: std_logic; signal blk_xfer_out_data : std_logic_vector(7 downto 0); signal blk_xfer_out_data_valid: std_logic; signal ep1_in_axis_tdata : std_logic_vector(7 downto 0); signal ep1_in_axis_tvalid : std_logic; signal ep1_in_axis_tready : std_logic; signal ep1_in_axis_tlast : std_logic; signal ep1_out_axis_tdata : std_logic_vector(7 downto 0); signal ep1_out_axis_tvalid : std_logic; signal ep1_out_axis_tready : std_logic; signal ep1_out_axis_tlast : std_logic; signal led_counter : std_logic_vector(25 downto 0); signal ulpi_stp_int : std_logic; begin ULPI_IO: for i in 7 downto 0 generate begin ULPI_IOBUF : IOBUF port map ( O => ulpi_data_in(i), IO => ulpi_data(i), I => ulpi_data_out(i), T => ulpi_dir ); end generate; USB_CONTROLLER: usb_tlp generic map ( VENDOR_ID => X"DEAD", PRODUCT_ID => X"BEEF", MANUFACTURER => "USBCore", PRODUCT => "Endpoint 1 Loopback Device", SERIAL => "", CONFIG_DESC => CONFIG_DESC & INTERFACE_DESC & EP1_IN_DESC & EP1_OUT_DESC, HIGH_SPEED => USE_HIGH_SPEED ) port map ( ulpi_data_in => ulpi_data_in, ulpi_data_out => ulpi_data_out, ulpi_dir => ulpi_dir, ulpi_nxt => ulpi_nxt, ulpi_stp => ulpi_stp, ulpi_reset => ulpi_reset, ulpi_clk60 => ulpi_clk60, usb_clk => usb_clk, usb_reset => usb_reset, usb_idle => usb_idle, usb_suspend => usb_suspend, usb_configured => usb_configured, usb_crc_error => usb_crc_error, usb_sof => usb_sof, ctl_xfer_endpoint => ctl_xfer_endpoint, ctl_xfer_type => ctl_xfer_type, ctl_xfer_request => ctl_xfer_request, ctl_xfer_value => ctl_xfer_value, ctl_xfer_index => ctl_xfer_index, ctl_xfer_length => ctl_xfer_length, ctl_xfer_accept => ctl_xfer_accept, ctl_xfer => ctl_xfer, ctl_xfer_done => ctl_xfer_done, ctl_xfer_data_out => ctl_xfer_data_out, ctl_xfer_data_out_valid => ctl_xfer_data_out_valid, ctl_xfer_data_in => ctl_xfer_data_in, ctl_xfer_data_in_valid => ctl_xfer_data_in_valid, ctl_xfer_data_in_last => ctl_xfer_data_in_last, ctl_xfer_data_in_ready => ctl_xfer_data_in_ready, blk_xfer_endpoint => blk_xfer_endpoint, blk_in_xfer => blk_in_xfer, blk_out_xfer => blk_out_xfer, blk_xfer_in_has_data => blk_xfer_in_has_data, blk_xfer_in_data => blk_xfer_in_data, blk_xfer_in_data_valid => blk_xfer_in_data_valid, blk_xfer_in_data_ready => blk_xfer_in_data_ready, blk_xfer_in_data_last => blk_xfer_in_data_last, blk_xfer_out_ready_read => blk_xfer_out_ready_read, blk_xfer_out_data => blk_xfer_out_data, blk_xfer_out_data_valid => blk_xfer_out_data_valid ); EP1_IN_CTL: blk_ep_in_ctl generic map ( USE_ASYNC_FIFO => true ) port map ( rst => usb_reset, usb_clk => usb_clk, axis_clk => main_clk, blk_in_xfer => blk_in_xfer, blk_xfer_in_has_data => blk_xfer_in_has_data, blk_xfer_in_data => blk_xfer_in_data, blk_xfer_in_data_valid => blk_xfer_in_data_valid, blk_xfer_in_data_ready => blk_xfer_in_data_ready, blk_xfer_in_data_last => blk_xfer_in_data_last, axis_tdata => ep1_in_axis_tdata, axis_tvalid => ep1_in_axis_tvalid, axis_tready => ep1_in_axis_tready, axis_tlast => ep1_in_axis_tlast ); EP1_OUT_CTL: blk_ep_out_ctl generic map ( USE_ASYNC_FIFO => true ) port map ( rst => usb_reset, usb_clk => usb_clk, axis_clk => main_clk, blk_out_xfer => blk_out_xfer, blk_xfer_out_ready_read => blk_xfer_out_ready_read, blk_xfer_out_data => blk_xfer_out_data, blk_xfer_out_data_valid => blk_xfer_out_data_valid, axis_tdata => ep1_out_axis_tdata, axis_tvalid => ep1_out_axis_tvalid, axis_tready => ep1_out_axis_tready, axis_tlast => ep1_out_axis_tlast ); ep1_in_axis_tdata <= ep1_out_axis_tdata; ep1_in_axis_tvalid <= ep1_out_axis_tvalid; ep1_out_axis_tready <= ep1_in_axis_tready; ep1_in_axis_tlast <= ep1_out_axis_tlast; COUNT: process(usb_clk) is begin if rising_edge(usb_clk) then led_counter <= led_counter + 1; end if; end process; led <= '1' when usb_idle = '1' AND usb_configured = '1' else led_counter(led_counter'left) when usb_idle = '1' else '1' when led_counter(led_counter'left downto led_counter'left - 2) = "000" else '0'; end ep1_loopback;
------------------------------------------------------------------------------- -- Title : Testbench for design "2013_big_drive" ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2013 strongly-typed ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.bus_pkg.all; use work.spislave_pkg.all; use work.motor_control_pkg.all; use work.utils_pkg.all; use work.pwm_module_pkg.all; use work.motor_control_pkg.all; use work.encoder_module_pkg.all; use work.servo_module_pkg.all; use work.adc_ad7266_pkg.all; use work.reg_file_pkg.all; use work.utils_pkg.all; ------------------------------------------------------------------------------- entity toplevel_tb is end toplevel_tb; ------------------------------------------------------------------------------- architecture tb of toplevel_tb is component toplevel is port ( bldc0_driver_st_p : out bldc_driver_stage_st_type; bldc0_hall_p : in hall_sensor_type; bldc0_encoder_p : in encoder_type; encoder0_p : in encoder_type; bldc1_driver_st_p : out bldc_driver_stage_st_type; bldc1_hall_p : in hall_sensor_type; bldc1_encoder_p : in encoder_type; encoder1_p : in encoder_type; dc0_driver_st_p : out dc_driver_stage_st_type; dc1_driver_st_p : out dc_driver_stage_st_type; dc2_driver_st_p : out dc_driver_stage_st_type; servo_p : out std_logic_vector(3 downto 2); imotor_tx_p : out std_logic_vector(4 downto 0); imotor_rx_p : in std_logic_vector(4 downto 0); pump_p : out std_logic_vector(3 downto 0); valve_p : out std_logic_vector(3 downto 0); cs_np : in std_logic; sck_p : in std_logic; miso_p : out std_logic; mosi_p : in std_logic; adc_out_p : out adc_ad7266_spi_out_type; adc_in_p : in adc_ad7266_spi_in_type; load_p : in std_logic; clk : in std_logic); end component toplevel; -- signals for component ports signal bldc0_driver_st_p : bldc_driver_stage_st_type; signal bldc0_hall_p : hall_sensor_type; signal bldc0_encoder_p : encoder_type; signal encoder0_p : encoder_type; signal bldc1_driver_st_p : bldc_driver_stage_st_type; signal bldc1_hall_p : hall_sensor_type; signal bldc1_encoder_p : encoder_type; signal encoder1_p : encoder_type; signal dc0_driver_st_p : dc_driver_stage_st_type; signal dc1_driver_st_p : dc_driver_stage_st_type; signal dc2_driver_st_p : dc_driver_stage_st_type; signal servo_p : std_logic_vector(3 downto 2); signal imotor_tx_p : std_logic_vector(4 downto 0); signal imotor_rx_p : std_logic_vector(4 downto 0); signal pump_p : std_logic_vector(3 downto 0); signal valve_p : std_logic_vector(3 downto 0); signal adc_in_p : adc_ad7266_spi_in_type; signal adc_out_p : adc_ad7266_spi_out_type; signal cs_np : std_logic := '0'; signal sck_p : std_logic := '0'; signal miso_p : std_logic; signal mosi_p : std_logic := '0'; signal load_p : std_logic := '1'; signal clk : std_logic := '0'; begin -- tb toplevel_1 : entity work.toplevel port map ( bldc0_driver_st_p => bldc0_driver_st_p, bldc0_hall_p => bldc0_hall_p, bldc0_encoder_p => bldc0_encoder_p, encoder0_p => encoder0_p, bldc1_driver_st_p => bldc1_driver_st_p, bldc1_hall_p => bldc1_hall_p, bldc1_encoder_p => bldc1_encoder_p, encoder1_p => encoder1_p, dc0_driver_st_p => dc0_driver_st_p, dc1_driver_st_p => dc1_driver_st_p, dc2_driver_st_p => dc2_driver_st_p, servo_p => servo_p, imotor_rx_p => imotor_rx_p, imotor_tx_p => imotor_tx_p, adc_out_p => adc_out_p, adc_in_p => adc_in_p, cs_np => cs_np, sck_p => sck_p, miso_p => miso_p, mosi_p => mosi_p, load_p => load_p, clk => clk); -- clock generation Clk <= not Clk after 5.0 ns; process begin wait; end process; end tb;
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2015.4 -- Copyright (C) 2015 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity feedforward_AXILiteS_s_axi is generic ( C_S_AXI_ADDR_WIDTH : INTEGER := 5; C_S_AXI_DATA_WIDTH : INTEGER := 32); port ( -- axi4 lite slave signals ACLK :in STD_LOGIC; ARESET :in STD_LOGIC; ACLK_EN :in STD_LOGIC; AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0); AWVALID :in STD_LOGIC; AWREADY :out STD_LOGIC; WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0); WVALID :in STD_LOGIC; WREADY :out STD_LOGIC; BRESP :out STD_LOGIC_VECTOR(1 downto 0); BVALID :out STD_LOGIC; BREADY :in STD_LOGIC; ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0); ARVALID :in STD_LOGIC; ARREADY :out STD_LOGIC; RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0); RRESP :out STD_LOGIC_VECTOR(1 downto 0); RVALID :out STD_LOGIC; RREADY :in STD_LOGIC; interrupt :out STD_LOGIC; -- user signals ap_start :out STD_LOGIC; ap_done :in STD_LOGIC; ap_ready :in STD_LOGIC; ap_idle :in STD_LOGIC; ap_return :in STD_LOGIC_VECTOR(7 downto 0); P_mode_V :out STD_LOGIC_VECTOR(7 downto 0) ); end entity feedforward_AXILiteS_s_axi; -- ------------------------Address Info------------------- -- 0x00 : Control signals -- bit 0 - ap_start (Read/Write/COH) -- bit 1 - ap_done (Read/COR) -- bit 2 - ap_idle (Read) -- bit 3 - ap_ready (Read) -- bit 7 - auto_restart (Read/Write) -- others - reserved -- 0x04 : Global Interrupt Enable Register -- bit 0 - Global Interrupt Enable (Read/Write) -- others - reserved -- 0x08 : IP Interrupt Enable Register (Read/Write) -- bit 0 - Channel 0 (ap_done) -- bit 1 - Channel 1 (ap_ready) -- others - reserved -- 0x0c : IP Interrupt Status Register (Read/TOW) -- bit 0 - Channel 0 (ap_done) -- bit 1 - Channel 1 (ap_ready) -- others - reserved -- 0x10 : Data signal of ap_return -- bit 7~0 - ap_return[7:0] (Read) -- others - reserved -- 0x18 : Data signal of P_mode_V -- bit 7~0 - P_mode_V[7:0] (Read/Write) -- others - reserved -- 0x1c : reserved -- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) architecture behave of feedforward_AXILiteS_s_axi is type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states signal wstate, wnext, rstate, rnext: states; constant ADDR_AP_CTRL : INTEGER := 16#00#; constant ADDR_GIE : INTEGER := 16#04#; constant ADDR_IER : INTEGER := 16#08#; constant ADDR_ISR : INTEGER := 16#0c#; constant ADDR_AP_RETURN_0 : INTEGER := 16#10#; constant ADDR_P_MODE_V_DATA_0 : INTEGER := 16#18#; constant ADDR_P_MODE_V_CTRL : INTEGER := 16#1c#; constant ADDR_BITS : INTEGER := 5; signal waddr : UNSIGNED(ADDR_BITS-1 downto 0); signal wmask : UNSIGNED(31 downto 0); signal aw_hs : STD_LOGIC; signal w_hs : STD_LOGIC; signal rdata_data : UNSIGNED(31 downto 0); signal ar_hs : STD_LOGIC; signal raddr : UNSIGNED(ADDR_BITS-1 downto 0); signal AWREADY_t : STD_LOGIC; signal WREADY_t : STD_LOGIC; signal ARREADY_t : STD_LOGIC; signal RVALID_t : STD_LOGIC; -- internal registers signal int_ap_idle : STD_LOGIC; signal int_ap_ready : STD_LOGIC; signal int_ap_done : STD_LOGIC; signal int_ap_start : STD_LOGIC; signal int_auto_restart : STD_LOGIC; signal int_gie : STD_LOGIC; signal int_ier : UNSIGNED(1 downto 0); signal int_isr : UNSIGNED(1 downto 0); signal int_ap_return : UNSIGNED(7 downto 0); signal int_P_mode_V : UNSIGNED(7 downto 0); begin -- ----------------------- Instantiation------------------ -- ----------------------- AXI WRITE --------------------- AWREADY_t <= '1' when wstate = wridle else '0'; AWREADY <= AWREADY_t; WREADY_t <= '1' when wstate = wrdata else '0'; WREADY <= WREADY_t; BRESP <= "00"; -- OKAY BVALID <= '1' when wstate = wrresp else '0'; wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0)); aw_hs <= AWVALID and AWREADY_t; w_hs <= WVALID and WREADY_t; -- write FSM process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then wstate <= wridle; elsif (ACLK_EN = '1') then wstate <= wnext; end if; end if; end process; process (wstate, AWVALID, WVALID, BREADY) begin case (wstate) is when wridle => if (AWVALID = '1') then wnext <= wrdata; else wnext <= wridle; end if; when wrdata => if (WVALID = '1') then wnext <= wrresp; else wnext <= wrdata; end if; when wrresp => if (BREADY = '1') then wnext <= wridle; else wnext <= wrresp; end if; when others => wnext <= wridle; end case; end process; waddr_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (aw_hs = '1') then waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)); end if; end if; end process; -- ----------------------- AXI READ ---------------------- ARREADY_t <= '1' when (rstate = rdidle) else '0'; ARREADY <= ARREADY_t; RDATA <= STD_LOGIC_VECTOR(rdata_data); RRESP <= "00"; -- OKAY RVALID_t <= '1' when (rstate = rddata) else '0'; RVALID <= RVALID_t; ar_hs <= ARVALID and ARREADY_t; raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0)); -- read FSM process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then rstate <= rdidle; elsif (ACLK_EN = '1') then rstate <= rnext; end if; end if; end process; process (rstate, ARVALID, RREADY, RVALID_t) begin case (rstate) is when rdidle => if (ARVALID = '1') then rnext <= rddata; else rnext <= rdidle; end if; when rddata => if (RREADY = '1' and RVALID_t = '1') then rnext <= rdidle; else rnext <= rddata; end if; when others => rnext <= rdidle; end case; end process; rdata_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (ar_hs = '1') then case (TO_INTEGER(raddr)) is when ADDR_AP_CTRL => rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0'); when ADDR_GIE => rdata_data <= (0 => int_gie, others => '0'); when ADDR_IER => rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0'); when ADDR_ISR => rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0'); when ADDR_AP_RETURN_0 => rdata_data <= RESIZE(int_ap_return(7 downto 0), 32); when ADDR_P_MODE_V_DATA_0 => rdata_data <= RESIZE(int_P_mode_V(7 downto 0), 32); when others => rdata_data <= (others => '0'); end case; end if; end if; end process; -- ----------------------- Register logic ---------------- interrupt <= int_gie and (int_isr(0) or int_isr(1)); ap_start <= int_ap_start; int_ap_idle <= ap_idle; int_ap_ready <= ap_ready; P_mode_V <= STD_LOGIC_VECTOR(int_P_mode_V); process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_start <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then int_ap_start <= '1'; elsif (int_ap_ready = '1') then int_ap_start <= int_auto_restart; -- clear on handshake/auto restart end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_done <= '0'; elsif (ACLK_EN = '1') then if (ap_done = '1') then int_ap_done <= '1'; elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then int_ap_done <= '0'; -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_auto_restart <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then int_auto_restart <= WDATA(7); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_gie <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then int_gie <= WDATA(0); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ier <= "00"; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then int_ier <= UNSIGNED(WDATA(1 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr(0) <= '0'; elsif (ACLK_EN = '1') then if (int_ier(0) = '1' and ap_done = '1') then int_isr(0) <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr(1) <= '0'; elsif (ACLK_EN = '1') then if (int_ier(1) = '1' and ap_ready = '1') then int_isr(1) <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_return <= (others => '0'); elsif (ACLK_EN = '1') then if (ap_done = '1') then int_ap_return <= UNSIGNED(ap_return); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_P_MODE_V_DATA_0) then int_P_mode_V(7 downto 0) <= (UNSIGNED(WDATA(7 downto 0)) and wmask(7 downto 0)) or ((not wmask(7 downto 0)) and int_P_mode_V(7 downto 0)); end if; end if; end if; end process; -- ----------------------- Memory logic ------------------ end architecture behave;
entity subent is port ( a : in string(1 to 2) := "AB"; b : out string(1 to 2)); end entity subent; architecture test of subent is begin b(1) <= a(1); b(2) <= a(2); end architecture test; entity test is end entity test; architecture test of test is signal b : string(1 to 2); begin e1: entity work.subent port map ( a => open, b(1) => b(1), b(2) => open -- it's not legal to have a mix of OPEN and non-open ); end architecture test;
entity subent is port ( a : in string(1 to 2) := "AB"; b : out string(1 to 2)); end entity subent; architecture test of subent is begin b(1) <= a(1); b(2) <= a(2); end architecture test; entity test is end entity test; architecture test of test is signal b : string(1 to 2); begin e1: entity work.subent port map ( a => open, b(1) => b(1), b(2) => open -- it's not legal to have a mix of OPEN and non-open ); end architecture test;
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Mon Sep 16 04:56:50 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_sim_netlist.vhdl -- Design : design_1_processing_system7_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is port ( CAN0_PHY_TX : out STD_LOGIC; CAN0_PHY_RX : in STD_LOGIC; CAN1_PHY_TX : out STD_LOGIC; CAN1_PHY_RX : in STD_LOGIC; ENET0_GMII_TX_EN : out STD_LOGIC; ENET0_GMII_TX_ER : out STD_LOGIC; ENET0_MDIO_MDC : out STD_LOGIC; ENET0_MDIO_O : out STD_LOGIC; ENET0_MDIO_T : out STD_LOGIC; ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET0_SOF_RX : out STD_LOGIC; ENET0_SOF_TX : out STD_LOGIC; ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET0_GMII_COL : in STD_LOGIC; ENET0_GMII_CRS : in STD_LOGIC; ENET0_GMII_RX_CLK : in STD_LOGIC; ENET0_GMII_RX_DV : in STD_LOGIC; ENET0_GMII_RX_ER : in STD_LOGIC; ENET0_GMII_TX_CLK : in STD_LOGIC; ENET0_MDIO_I : in STD_LOGIC; ENET0_EXT_INTIN : in STD_LOGIC; ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_TX_EN : out STD_LOGIC; ENET1_GMII_TX_ER : out STD_LOGIC; ENET1_MDIO_MDC : out STD_LOGIC; ENET1_MDIO_O : out STD_LOGIC; ENET1_MDIO_T : out STD_LOGIC; ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET1_SOF_RX : out STD_LOGIC; ENET1_SOF_TX : out STD_LOGIC; ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_COL : in STD_LOGIC; ENET1_GMII_CRS : in STD_LOGIC; ENET1_GMII_RX_CLK : in STD_LOGIC; ENET1_GMII_RX_DV : in STD_LOGIC; ENET1_GMII_RX_ER : in STD_LOGIC; ENET1_GMII_TX_CLK : in STD_LOGIC; ENET1_MDIO_I : in STD_LOGIC; ENET1_EXT_INTIN : in STD_LOGIC; ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 ); I2C0_SDA_I : in STD_LOGIC; I2C0_SDA_O : out STD_LOGIC; I2C0_SDA_T : out STD_LOGIC; I2C0_SCL_I : in STD_LOGIC; I2C0_SCL_O : out STD_LOGIC; I2C0_SCL_T : out STD_LOGIC; I2C1_SDA_I : in STD_LOGIC; I2C1_SDA_O : out STD_LOGIC; I2C1_SDA_T : out STD_LOGIC; I2C1_SCL_I : in STD_LOGIC; I2C1_SCL_O : out STD_LOGIC; I2C1_SCL_T : out STD_LOGIC; PJTAG_TCK : in STD_LOGIC; PJTAG_TMS : in STD_LOGIC; PJTAG_TDI : in STD_LOGIC; PJTAG_TDO : out STD_LOGIC; SDIO0_CLK : out STD_LOGIC; SDIO0_CLK_FB : in STD_LOGIC; SDIO0_CMD_O : out STD_LOGIC; SDIO0_CMD_I : in STD_LOGIC; SDIO0_CMD_T : out STD_LOGIC; SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_LED : out STD_LOGIC; SDIO0_CDN : in STD_LOGIC; SDIO0_WP : in STD_LOGIC; SDIO0_BUSPOW : out STD_LOGIC; SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SDIO1_CLK : out STD_LOGIC; SDIO1_CLK_FB : in STD_LOGIC; SDIO1_CMD_O : out STD_LOGIC; SDIO1_CMD_I : in STD_LOGIC; SDIO1_CMD_T : out STD_LOGIC; SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_LED : out STD_LOGIC; SDIO1_CDN : in STD_LOGIC; SDIO1_WP : in STD_LOGIC; SDIO1_BUSPOW : out STD_LOGIC; SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SPI0_SCLK_I : in STD_LOGIC; SPI0_SCLK_O : out STD_LOGIC; SPI0_SCLK_T : out STD_LOGIC; SPI0_MOSI_I : in STD_LOGIC; SPI0_MOSI_O : out STD_LOGIC; SPI0_MOSI_T : out STD_LOGIC; SPI0_MISO_I : in STD_LOGIC; SPI0_MISO_O : out STD_LOGIC; SPI0_MISO_T : out STD_LOGIC; SPI0_SS_I : in STD_LOGIC; SPI0_SS_O : out STD_LOGIC; SPI0_SS1_O : out STD_LOGIC; SPI0_SS2_O : out STD_LOGIC; SPI0_SS_T : out STD_LOGIC; SPI1_SCLK_I : in STD_LOGIC; SPI1_SCLK_O : out STD_LOGIC; SPI1_SCLK_T : out STD_LOGIC; SPI1_MOSI_I : in STD_LOGIC; SPI1_MOSI_O : out STD_LOGIC; SPI1_MOSI_T : out STD_LOGIC; SPI1_MISO_I : in STD_LOGIC; SPI1_MISO_O : out STD_LOGIC; SPI1_MISO_T : out STD_LOGIC; SPI1_SS_I : in STD_LOGIC; SPI1_SS_O : out STD_LOGIC; SPI1_SS1_O : out STD_LOGIC; SPI1_SS2_O : out STD_LOGIC; SPI1_SS_T : out STD_LOGIC; UART0_DTRN : out STD_LOGIC; UART0_RTSN : out STD_LOGIC; UART0_TX : out STD_LOGIC; UART0_CTSN : in STD_LOGIC; UART0_DCDN : in STD_LOGIC; UART0_DSRN : in STD_LOGIC; UART0_RIN : in STD_LOGIC; UART0_RX : in STD_LOGIC; UART1_DTRN : out STD_LOGIC; UART1_RTSN : out STD_LOGIC; UART1_TX : out STD_LOGIC; UART1_CTSN : in STD_LOGIC; UART1_DCDN : in STD_LOGIC; UART1_DSRN : in STD_LOGIC; UART1_RIN : in STD_LOGIC; UART1_RX : in STD_LOGIC; TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; TTC0_CLK0_IN : in STD_LOGIC; TTC0_CLK1_IN : in STD_LOGIC; TTC0_CLK2_IN : in STD_LOGIC; TTC1_WAVE0_OUT : out STD_LOGIC; TTC1_WAVE1_OUT : out STD_LOGIC; TTC1_WAVE2_OUT : out STD_LOGIC; TTC1_CLK0_IN : in STD_LOGIC; TTC1_CLK1_IN : in STD_LOGIC; TTC1_CLK2_IN : in STD_LOGIC; WDT_CLK_IN : in STD_LOGIC; WDT_RST_OUT : out STD_LOGIC; TRACE_CLK : in STD_LOGIC; TRACE_CTL : out STD_LOGIC; TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 ); TRACE_CLK_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB1_VBUS_PWRSELECT : out STD_LOGIC; USB1_VBUS_PWRFAULT : in STD_LOGIC; SRAM_INTIN : in STD_LOGIC; M_AXI_GP0_ARESETN : out STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARESETN : out STD_LOGIC; M_AXI_GP1_ARVALID : out STD_LOGIC; M_AXI_GP1_AWVALID : out STD_LOGIC; M_AXI_GP1_BREADY : out STD_LOGIC; M_AXI_GP1_RREADY : out STD_LOGIC; M_AXI_GP1_WLAST : out STD_LOGIC; M_AXI_GP1_WVALID : out STD_LOGIC; M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ACLK : in STD_LOGIC; M_AXI_GP1_ARREADY : in STD_LOGIC; M_AXI_GP1_AWREADY : in STD_LOGIC; M_AXI_GP1_BVALID : in STD_LOGIC; M_AXI_GP1_RLAST : in STD_LOGIC; M_AXI_GP1_RVALID : in STD_LOGIC; M_AXI_GP1_WREADY : in STD_LOGIC; M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARESETN : out STD_LOGIC; S_AXI_GP0_ARREADY : out STD_LOGIC; S_AXI_GP0_AWREADY : out STD_LOGIC; S_AXI_GP0_BVALID : out STD_LOGIC; S_AXI_GP0_RLAST : out STD_LOGIC; S_AXI_GP0_RVALID : out STD_LOGIC; S_AXI_GP0_WREADY : out STD_LOGIC; S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_ACLK : in STD_LOGIC; S_AXI_GP0_ARVALID : in STD_LOGIC; S_AXI_GP0_AWVALID : in STD_LOGIC; S_AXI_GP0_BREADY : in STD_LOGIC; S_AXI_GP0_RREADY : in STD_LOGIC; S_AXI_GP0_WLAST : in STD_LOGIC; S_AXI_GP0_WVALID : in STD_LOGIC; S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ARESETN : out STD_LOGIC; S_AXI_GP1_ARREADY : out STD_LOGIC; S_AXI_GP1_AWREADY : out STD_LOGIC; S_AXI_GP1_BVALID : out STD_LOGIC; S_AXI_GP1_RLAST : out STD_LOGIC; S_AXI_GP1_RVALID : out STD_LOGIC; S_AXI_GP1_WREADY : out STD_LOGIC; S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ACLK : in STD_LOGIC; S_AXI_GP1_ARVALID : in STD_LOGIC; S_AXI_GP1_AWVALID : in STD_LOGIC; S_AXI_GP1_BREADY : in STD_LOGIC; S_AXI_GP1_RREADY : in STD_LOGIC; S_AXI_GP1_WLAST : in STD_LOGIC; S_AXI_GP1_WVALID : in STD_LOGIC; S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_ACP_ARESETN : out STD_LOGIC; S_AXI_ACP_ARREADY : out STD_LOGIC; S_AXI_ACP_AWREADY : out STD_LOGIC; S_AXI_ACP_BVALID : out STD_LOGIC; S_AXI_ACP_RLAST : out STD_LOGIC; S_AXI_ACP_RVALID : out STD_LOGIC; S_AXI_ACP_WREADY : out STD_LOGIC; S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_ACLK : in STD_LOGIC; S_AXI_ACP_ARVALID : in STD_LOGIC; S_AXI_ACP_AWVALID : in STD_LOGIC; S_AXI_ACP_BREADY : in STD_LOGIC; S_AXI_ACP_RREADY : in STD_LOGIC; S_AXI_ACP_WLAST : in STD_LOGIC; S_AXI_ACP_WVALID : in STD_LOGIC; S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_ARESETN : out STD_LOGIC; S_AXI_HP0_ARREADY : out STD_LOGIC; S_AXI_HP0_AWREADY : out STD_LOGIC; S_AXI_HP0_BVALID : out STD_LOGIC; S_AXI_HP0_RLAST : out STD_LOGIC; S_AXI_HP0_RVALID : out STD_LOGIC; S_AXI_HP0_WREADY : out STD_LOGIC; S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_ACLK : in STD_LOGIC; S_AXI_HP0_ARVALID : in STD_LOGIC; S_AXI_HP0_AWVALID : in STD_LOGIC; S_AXI_HP0_BREADY : in STD_LOGIC; S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_RREADY : in STD_LOGIC; S_AXI_HP0_WLAST : in STD_LOGIC; S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_WVALID : in STD_LOGIC; S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_ARESETN : out STD_LOGIC; S_AXI_HP1_ARREADY : out STD_LOGIC; S_AXI_HP1_AWREADY : out STD_LOGIC; S_AXI_HP1_BVALID : out STD_LOGIC; S_AXI_HP1_RLAST : out STD_LOGIC; S_AXI_HP1_RVALID : out STD_LOGIC; S_AXI_HP1_WREADY : out STD_LOGIC; S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_ACLK : in STD_LOGIC; S_AXI_HP1_ARVALID : in STD_LOGIC; S_AXI_HP1_AWVALID : in STD_LOGIC; S_AXI_HP1_BREADY : in STD_LOGIC; S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_RREADY : in STD_LOGIC; S_AXI_HP1_WLAST : in STD_LOGIC; S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_WVALID : in STD_LOGIC; S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_ARESETN : out STD_LOGIC; S_AXI_HP2_ARREADY : out STD_LOGIC; S_AXI_HP2_AWREADY : out STD_LOGIC; S_AXI_HP2_BVALID : out STD_LOGIC; S_AXI_HP2_RLAST : out STD_LOGIC; S_AXI_HP2_RVALID : out STD_LOGIC; S_AXI_HP2_WREADY : out STD_LOGIC; S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_ACLK : in STD_LOGIC; S_AXI_HP2_ARVALID : in STD_LOGIC; S_AXI_HP2_AWVALID : in STD_LOGIC; S_AXI_HP2_BREADY : in STD_LOGIC; S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_RREADY : in STD_LOGIC; S_AXI_HP2_WLAST : in STD_LOGIC; S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_WVALID : in STD_LOGIC; S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_ARESETN : out STD_LOGIC; S_AXI_HP3_ARREADY : out STD_LOGIC; S_AXI_HP3_AWREADY : out STD_LOGIC; S_AXI_HP3_BVALID : out STD_LOGIC; S_AXI_HP3_RLAST : out STD_LOGIC; S_AXI_HP3_RVALID : out STD_LOGIC; S_AXI_HP3_WREADY : out STD_LOGIC; S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_ACLK : in STD_LOGIC; S_AXI_HP3_ARVALID : in STD_LOGIC; S_AXI_HP3_AWVALID : in STD_LOGIC; S_AXI_HP3_BREADY : in STD_LOGIC; S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_RREADY : in STD_LOGIC; S_AXI_HP3_WLAST : in STD_LOGIC; S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_WVALID : in STD_LOGIC; S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); IRQ_P2F_DMAC_ABORT : out STD_LOGIC; IRQ_P2F_DMAC0 : out STD_LOGIC; IRQ_P2F_DMAC1 : out STD_LOGIC; IRQ_P2F_DMAC2 : out STD_LOGIC; IRQ_P2F_DMAC3 : out STD_LOGIC; IRQ_P2F_DMAC4 : out STD_LOGIC; IRQ_P2F_DMAC5 : out STD_LOGIC; IRQ_P2F_DMAC6 : out STD_LOGIC; IRQ_P2F_DMAC7 : out STD_LOGIC; IRQ_P2F_SMC : out STD_LOGIC; IRQ_P2F_QSPI : out STD_LOGIC; IRQ_P2F_CTI : out STD_LOGIC; IRQ_P2F_GPIO : out STD_LOGIC; IRQ_P2F_USB0 : out STD_LOGIC; IRQ_P2F_ENET0 : out STD_LOGIC; IRQ_P2F_ENET_WAKE0 : out STD_LOGIC; IRQ_P2F_SDIO0 : out STD_LOGIC; IRQ_P2F_I2C0 : out STD_LOGIC; IRQ_P2F_SPI0 : out STD_LOGIC; IRQ_P2F_UART0 : out STD_LOGIC; IRQ_P2F_CAN0 : out STD_LOGIC; IRQ_P2F_USB1 : out STD_LOGIC; IRQ_P2F_ENET1 : out STD_LOGIC; IRQ_P2F_ENET_WAKE1 : out STD_LOGIC; IRQ_P2F_SDIO1 : out STD_LOGIC; IRQ_P2F_I2C1 : out STD_LOGIC; IRQ_P2F_SPI1 : out STD_LOGIC; IRQ_P2F_UART1 : out STD_LOGIC; IRQ_P2F_CAN1 : out STD_LOGIC; IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 ); Core0_nFIQ : in STD_LOGIC; Core0_nIRQ : in STD_LOGIC; Core1_nFIQ : in STD_LOGIC; Core1_nIRQ : in STD_LOGIC; DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA0_DAVALID : out STD_LOGIC; DMA0_DRREADY : out STD_LOGIC; DMA0_RSTN : out STD_LOGIC; DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DAVALID : out STD_LOGIC; DMA1_DRREADY : out STD_LOGIC; DMA1_RSTN : out STD_LOGIC; DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DAVALID : out STD_LOGIC; DMA2_DRREADY : out STD_LOGIC; DMA2_RSTN : out STD_LOGIC; DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DAVALID : out STD_LOGIC; DMA3_DRREADY : out STD_LOGIC; DMA3_RSTN : out STD_LOGIC; DMA0_ACLK : in STD_LOGIC; DMA0_DAREADY : in STD_LOGIC; DMA0_DRLAST : in STD_LOGIC; DMA0_DRVALID : in STD_LOGIC; DMA1_ACLK : in STD_LOGIC; DMA1_DAREADY : in STD_LOGIC; DMA1_DRLAST : in STD_LOGIC; DMA1_DRVALID : in STD_LOGIC; DMA2_ACLK : in STD_LOGIC; DMA2_DAREADY : in STD_LOGIC; DMA2_DRLAST : in STD_LOGIC; DMA2_DRVALID : in STD_LOGIC; DMA3_ACLK : in STD_LOGIC; DMA3_DAREADY : in STD_LOGIC; DMA3_DRLAST : in STD_LOGIC; DMA3_DRVALID : in STD_LOGIC; DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); FCLK_CLK3 : out STD_LOGIC; FCLK_CLK2 : out STD_LOGIC; FCLK_CLK1 : out STD_LOGIC; FCLK_CLK0 : out STD_LOGIC; FCLK_CLKTRIG3_N : in STD_LOGIC; FCLK_CLKTRIG2_N : in STD_LOGIC; FCLK_CLKTRIG1_N : in STD_LOGIC; FCLK_CLKTRIG0_N : in STD_LOGIC; FCLK_RESET3_N : out STD_LOGIC; FCLK_RESET2_N : out STD_LOGIC; FCLK_RESET1_N : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMD_TRACEIN_VALID : in STD_LOGIC; FTMD_TRACEIN_CLK : in STD_LOGIC; FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 ); FTMT_F2P_TRIG_0 : in STD_LOGIC; FTMT_F2P_TRIGACK_0 : out STD_LOGIC; FTMT_F2P_TRIG_1 : in STD_LOGIC; FTMT_F2P_TRIGACK_1 : out STD_LOGIC; FTMT_F2P_TRIG_2 : in STD_LOGIC; FTMT_F2P_TRIGACK_2 : out STD_LOGIC; FTMT_F2P_TRIG_3 : in STD_LOGIC; FTMT_F2P_TRIGACK_3 : out STD_LOGIC; FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMT_P2F_TRIGACK_0 : in STD_LOGIC; FTMT_P2F_TRIG_0 : out STD_LOGIC; FTMT_P2F_TRIGACK_1 : in STD_LOGIC; FTMT_P2F_TRIG_1 : out STD_LOGIC; FTMT_P2F_TRIGACK_2 : in STD_LOGIC; FTMT_P2F_TRIG_2 : out STD_LOGIC; FTMT_P2F_TRIGACK_3 : in STD_LOGIC; FTMT_P2F_TRIG_3 : out STD_LOGIC; FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 ); FPGA_IDLE_N : in STD_LOGIC; EVENT_EVENTO : out STD_LOGIC; EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_EVENTI : in STD_LOGIC; DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 ); MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_GP0_EN_MODIFIABLE_TXN : integer; attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_GP1_EN_MODIFIABLE_TXN : integer; attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT"; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg400"; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION"; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8; attribute C_USE_AXI_NONSECURE : integer; attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_M_AXI_GP0 : integer; attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_USE_M_AXI_GP1 : integer; attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_ACP : integer; attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_GP0 : integer; attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_GP1 : integer; attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP0 : integer; attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP1 : integer; attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP2 : integer; attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP3 : integer; attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute HW_HANDOFF : string; attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "design_1_processing_system7_0_0.hwdef"; attribute POWER : string; attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={50} usageRate={0.5} />/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal ENET0_MDIO_T_n : STD_LOGIC; signal ENET1_MDIO_T_n : STD_LOGIC; signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 ); signal I2C0_SCL_T_n : STD_LOGIC; signal I2C0_SDA_T_n : STD_LOGIC; signal I2C1_SCL_T_n : STD_LOGIC; signal I2C1_SDA_T_n : STD_LOGIC; signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal SDIO0_CMD_T_n : STD_LOGIC; signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal SDIO1_CMD_T_n : STD_LOGIC; signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal SPI0_MISO_T_n : STD_LOGIC; signal SPI0_MOSI_T_n : STD_LOGIC; signal SPI0_SCLK_T_n : STD_LOGIC; signal SPI0_SS_T_n : STD_LOGIC; signal SPI1_MISO_T_n : STD_LOGIC; signal SPI1_MOSI_T_n : STD_LOGIC; signal SPI1_SCLK_T_n : STD_LOGIC; signal SPI1_SS_T_n : STD_LOGIC; signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true"; signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true"; signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true"; signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true"; signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true"; signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true"; signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true"; signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true"; signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true"; signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true"; signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true"; signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true"; signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true"; signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true"; signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true"; signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true"; signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 ); signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal buffered_DDR_CAS_n : STD_LOGIC; signal buffered_DDR_CKE : STD_LOGIC; signal buffered_DDR_CS_n : STD_LOGIC; signal buffered_DDR_Clk : STD_LOGIC; signal buffered_DDR_Clk_n : STD_LOGIC; signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DRSTB : STD_LOGIC; signal buffered_DDR_ODT : STD_LOGIC; signal buffered_DDR_RAS_n : STD_LOGIC; signal buffered_DDR_VRN : STD_LOGIC; signal buffered_DDR_VRP : STD_LOGIC; signal buffered_DDR_WEB : STD_LOGIC; signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); signal buffered_PS_CLK : STD_LOGIC; signal buffered_PS_PORB : STD_LOGIC; signal buffered_PS_SRSTB : STD_LOGIC; signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); attribute BOX_TYPE : string; attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS7_i : label is "PRIMITIVE"; attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; begin ENET0_GMII_TXD(7) <= \<const0>\; ENET0_GMII_TXD(6) <= \<const0>\; ENET0_GMII_TXD(5) <= \<const0>\; ENET0_GMII_TXD(4) <= \<const0>\; ENET0_GMII_TXD(3) <= \<const0>\; ENET0_GMII_TXD(2) <= \<const0>\; ENET0_GMII_TXD(1) <= \<const0>\; ENET0_GMII_TXD(0) <= \<const0>\; ENET0_GMII_TX_EN <= \<const0>\; ENET0_GMII_TX_ER <= \<const0>\; ENET1_GMII_TXD(7) <= \<const0>\; ENET1_GMII_TXD(6) <= \<const0>\; ENET1_GMII_TXD(5) <= \<const0>\; ENET1_GMII_TXD(4) <= \<const0>\; ENET1_GMII_TXD(3) <= \<const0>\; ENET1_GMII_TXD(2) <= \<const0>\; ENET1_GMII_TXD(1) <= \<const0>\; ENET1_GMII_TXD(0) <= \<const0>\; ENET1_GMII_TX_EN <= \<const0>\; ENET1_GMII_TX_ER <= \<const0>\; M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2); M_AXI_GP0_ARCACHE(1) <= \<const1>\; M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0); M_AXI_GP0_ARSIZE(2) <= \<const0>\; M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0); M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2); M_AXI_GP0_AWCACHE(1) <= \<const1>\; M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0); M_AXI_GP0_AWSIZE(2) <= \<const0>\; M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0); M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2); M_AXI_GP1_ARCACHE(1) <= \<const1>\; M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0); M_AXI_GP1_ARSIZE(2) <= \<const0>\; M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0); M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2); M_AXI_GP1_AWCACHE(1) <= \<const1>\; M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0); M_AXI_GP1_AWSIZE(2) <= \<const0>\; M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0); PJTAG_TDO <= \<const0>\; TRACE_CLK_OUT <= \<const0>\; TRACE_CTL <= \TRACE_CTL_PIPE[0]\; TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0); DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CAS_n, PAD => DDR_CAS_n ); DDR_CKE_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CKE, PAD => DDR_CKE ); DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CS_n, PAD => DDR_CS_n ); DDR_Clk_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk, PAD => DDR_Clk ); DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk_n, PAD => DDR_Clk_n ); DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DRSTB, PAD => DDR_DRSTB ); DDR_ODT_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_ODT, PAD => DDR_ODT ); DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_RAS_n, PAD => DDR_RAS_n ); DDR_VRN_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRN, PAD => DDR_VRN ); DDR_VRP_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRP, PAD => DDR_VRP ); DDR_WEB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_WEB, PAD => DDR_WEB ); ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET0_MDIO_T_n, O => ENET0_MDIO_T ); ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET1_MDIO_T_n, O => ENET1_MDIO_T ); GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(0), O => GPIO_T(0) ); \GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(10), O => GPIO_T(10) ); \GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(11), O => GPIO_T(11) ); \GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(12), O => GPIO_T(12) ); \GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(13), O => GPIO_T(13) ); \GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(14), O => GPIO_T(14) ); \GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(15), O => GPIO_T(15) ); \GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(16), O => GPIO_T(16) ); \GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(17), O => GPIO_T(17) ); \GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(18), O => GPIO_T(18) ); \GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(19), O => GPIO_T(19) ); \GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(1), O => GPIO_T(1) ); \GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(20), O => GPIO_T(20) ); \GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(21), O => GPIO_T(21) ); \GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(22), O => GPIO_T(22) ); \GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(23), O => GPIO_T(23) ); \GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(24), O => GPIO_T(24) ); \GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(25), O => GPIO_T(25) ); \GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(26), O => GPIO_T(26) ); \GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(27), O => GPIO_T(27) ); \GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(28), O => GPIO_T(28) ); \GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(29), O => GPIO_T(29) ); \GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(2), O => GPIO_T(2) ); \GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(30), O => GPIO_T(30) ); \GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(31), O => GPIO_T(31) ); \GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(32), O => GPIO_T(32) ); \GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(33), O => GPIO_T(33) ); \GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(34), O => GPIO_T(34) ); \GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(35), O => GPIO_T(35) ); \GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(36), O => GPIO_T(36) ); \GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(37), O => GPIO_T(37) ); \GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(38), O => GPIO_T(38) ); \GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(39), O => GPIO_T(39) ); \GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(3), O => GPIO_T(3) ); \GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(40), O => GPIO_T(40) ); \GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(41), O => GPIO_T(41) ); \GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(42), O => GPIO_T(42) ); \GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(43), O => GPIO_T(43) ); \GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(44), O => GPIO_T(44) ); \GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(45), O => GPIO_T(45) ); \GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(46), O => GPIO_T(46) ); \GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(47), O => GPIO_T(47) ); \GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(48), O => GPIO_T(48) ); \GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(49), O => GPIO_T(49) ); \GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(4), O => GPIO_T(4) ); \GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(50), O => GPIO_T(50) ); \GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(51), O => GPIO_T(51) ); \GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(52), O => GPIO_T(52) ); \GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(53), O => GPIO_T(53) ); \GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(54), O => GPIO_T(54) ); \GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(55), O => GPIO_T(55) ); \GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(56), O => GPIO_T(56) ); \GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(57), O => GPIO_T(57) ); \GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(58), O => GPIO_T(58) ); \GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(59), O => GPIO_T(59) ); \GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(5), O => GPIO_T(5) ); \GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(60), O => GPIO_T(60) ); \GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(61), O => GPIO_T(61) ); \GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(62), O => GPIO_T(62) ); \GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(63), O => GPIO_T(63) ); \GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(6), O => GPIO_T(6) ); \GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(7), O => GPIO_T(7) ); \GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(8), O => GPIO_T(8) ); \GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(9), O => GPIO_T(9) ); I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SCL_T_n, O => I2C0_SCL_T ); I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SDA_T_n, O => I2C0_SDA_T ); I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SCL_T_n, O => I2C1_SCL_T ); I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SDA_T_n, O => I2C1_SDA_T ); PS7_i: unisim.vcomponents.PS7 port map ( DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0), DDRARB(3 downto 0) => DDR_ARB(3 downto 0), DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0), DDRCASB => buffered_DDR_CAS_n, DDRCKE => buffered_DDR_CKE, DDRCKN => buffered_DDR_Clk_n, DDRCKP => buffered_DDR_Clk, DDRCSB => buffered_DDR_CS_n, DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0), DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0), DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0), DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0), DDRDRSTB => buffered_DDR_DRSTB, DDRODT => buffered_DDR_ODT, DDRRASB => buffered_DDR_RAS_n, DDRVRN => buffered_DDR_VRN, DDRVRP => buffered_DDR_VRP, DDRWEB => buffered_DDR_WEB, DMA0ACLK => DMA0_ACLK, DMA0DAREADY => DMA0_DAREADY, DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0), DMA0DAVALID => DMA0_DAVALID, DMA0DRLAST => DMA0_DRLAST, DMA0DRREADY => DMA0_DRREADY, DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0), DMA0DRVALID => DMA0_DRVALID, DMA0RSTN => DMA0_RSTN, DMA1ACLK => DMA1_ACLK, DMA1DAREADY => DMA1_DAREADY, DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0), DMA1DAVALID => DMA1_DAVALID, DMA1DRLAST => DMA1_DRLAST, DMA1DRREADY => DMA1_DRREADY, DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0), DMA1DRVALID => DMA1_DRVALID, DMA1RSTN => DMA1_RSTN, DMA2ACLK => DMA2_ACLK, DMA2DAREADY => DMA2_DAREADY, DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0), DMA2DAVALID => DMA2_DAVALID, DMA2DRLAST => DMA2_DRLAST, DMA2DRREADY => DMA2_DRREADY, DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0), DMA2DRVALID => DMA2_DRVALID, DMA2RSTN => DMA2_RSTN, DMA3ACLK => DMA3_ACLK, DMA3DAREADY => DMA3_DAREADY, DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0), DMA3DAVALID => DMA3_DAVALID, DMA3DRLAST => DMA3_DRLAST, DMA3DRREADY => DMA3_DRREADY, DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0), DMA3DRVALID => DMA3_DRVALID, DMA3RSTN => DMA3_RSTN, EMIOCAN0PHYRX => CAN0_PHY_RX, EMIOCAN0PHYTX => CAN0_PHY_TX, EMIOCAN1PHYRX => CAN1_PHY_RX, EMIOCAN1PHYTX => CAN1_PHY_TX, EMIOENET0EXTINTIN => ENET0_EXT_INTIN, EMIOENET0GMIICOL => '0', EMIOENET0GMIICRS => '0', EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK, EMIOENET0GMIIRXD(7 downto 0) => B"00000000", EMIOENET0GMIIRXDV => '0', EMIOENET0GMIIRXER => '0', EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK, EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0), EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED, EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED, EMIOENET0MDIOI => ENET0_MDIO_I, EMIOENET0MDIOMDC => ENET0_MDIO_MDC, EMIOENET0MDIOO => ENET0_MDIO_O, EMIOENET0MDIOTN => ENET0_MDIO_T_n, EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX, EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX, EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX, EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX, EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX, EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX, EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX, EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX, EMIOENET0SOFRX => ENET0_SOF_RX, EMIOENET0SOFTX => ENET0_SOF_TX, EMIOENET1EXTINTIN => ENET1_EXT_INTIN, EMIOENET1GMIICOL => '0', EMIOENET1GMIICRS => '0', EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK, EMIOENET1GMIIRXD(7 downto 0) => B"00000000", EMIOENET1GMIIRXDV => '0', EMIOENET1GMIIRXER => '0', EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK, EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0), EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED, EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED, EMIOENET1MDIOI => ENET1_MDIO_I, EMIOENET1MDIOMDC => ENET1_MDIO_MDC, EMIOENET1MDIOO => ENET1_MDIO_O, EMIOENET1MDIOTN => ENET1_MDIO_T_n, EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX, EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX, EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX, EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX, EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX, EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX, EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX, EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX, EMIOENET1SOFRX => ENET1_SOF_RX, EMIOENET1SOFTX => ENET1_SOF_TX, EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0), EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0), EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0), EMIOI2C0SCLI => I2C0_SCL_I, EMIOI2C0SCLO => I2C0_SCL_O, EMIOI2C0SCLTN => I2C0_SCL_T_n, EMIOI2C0SDAI => I2C0_SDA_I, EMIOI2C0SDAO => I2C0_SDA_O, EMIOI2C0SDATN => I2C0_SDA_T_n, EMIOI2C1SCLI => I2C1_SCL_I, EMIOI2C1SCLO => I2C1_SCL_O, EMIOI2C1SCLTN => I2C1_SCL_T_n, EMIOI2C1SDAI => I2C1_SDA_I, EMIOI2C1SDAO => I2C1_SDA_O, EMIOI2C1SDATN => I2C1_SDA_T_n, EMIOPJTAGTCK => PJTAG_TCK, EMIOPJTAGTDI => PJTAG_TDI, EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED, EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED, EMIOPJTAGTMS => PJTAG_TMS, EMIOSDIO0BUSPOW => SDIO0_BUSPOW, EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0), EMIOSDIO0CDN => SDIO0_CDN, EMIOSDIO0CLK => SDIO0_CLK, EMIOSDIO0CLKFB => SDIO0_CLK_FB, EMIOSDIO0CMDI => SDIO0_CMD_I, EMIOSDIO0CMDO => SDIO0_CMD_O, EMIOSDIO0CMDTN => SDIO0_CMD_T_n, EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0), EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0), EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0), EMIOSDIO0LED => SDIO0_LED, EMIOSDIO0WP => SDIO0_WP, EMIOSDIO1BUSPOW => SDIO1_BUSPOW, EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0), EMIOSDIO1CDN => SDIO1_CDN, EMIOSDIO1CLK => SDIO1_CLK, EMIOSDIO1CLKFB => SDIO1_CLK_FB, EMIOSDIO1CMDI => SDIO1_CMD_I, EMIOSDIO1CMDO => SDIO1_CMD_O, EMIOSDIO1CMDTN => SDIO1_CMD_T_n, EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0), EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0), EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0), EMIOSDIO1LED => SDIO1_LED, EMIOSDIO1WP => SDIO1_WP, EMIOSPI0MI => SPI0_MISO_I, EMIOSPI0MO => SPI0_MOSI_O, EMIOSPI0MOTN => SPI0_MOSI_T_n, EMIOSPI0SCLKI => SPI0_SCLK_I, EMIOSPI0SCLKO => SPI0_SCLK_O, EMIOSPI0SCLKTN => SPI0_SCLK_T_n, EMIOSPI0SI => SPI0_MOSI_I, EMIOSPI0SO => SPI0_MISO_O, EMIOSPI0SSIN => SPI0_SS_I, EMIOSPI0SSNTN => SPI0_SS_T_n, EMIOSPI0SSON(2) => SPI0_SS2_O, EMIOSPI0SSON(1) => SPI0_SS1_O, EMIOSPI0SSON(0) => SPI0_SS_O, EMIOSPI0STN => SPI0_MISO_T_n, EMIOSPI1MI => SPI1_MISO_I, EMIOSPI1MO => SPI1_MOSI_O, EMIOSPI1MOTN => SPI1_MOSI_T_n, EMIOSPI1SCLKI => SPI1_SCLK_I, EMIOSPI1SCLKO => SPI1_SCLK_O, EMIOSPI1SCLKTN => SPI1_SCLK_T_n, EMIOSPI1SI => SPI1_MOSI_I, EMIOSPI1SO => SPI1_MISO_O, EMIOSPI1SSIN => SPI1_SS_I, EMIOSPI1SSNTN => SPI1_SS_T_n, EMIOSPI1SSON(2) => SPI1_SS2_O, EMIOSPI1SSON(1) => SPI1_SS1_O, EMIOSPI1SSON(0) => SPI1_SS_O, EMIOSPI1STN => SPI1_MISO_T_n, EMIOSRAMINTIN => SRAM_INTIN, EMIOTRACECLK => TRACE_CLK, EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED, EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0), EMIOTTC0CLKI(2) => TTC0_CLK2_IN, EMIOTTC0CLKI(1) => TTC0_CLK1_IN, EMIOTTC0CLKI(0) => TTC0_CLK0_IN, EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT, EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT, EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT, EMIOTTC1CLKI(2) => TTC1_CLK2_IN, EMIOTTC1CLKI(1) => TTC1_CLK1_IN, EMIOTTC1CLKI(0) => TTC1_CLK0_IN, EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT, EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT, EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT, EMIOUART0CTSN => UART0_CTSN, EMIOUART0DCDN => UART0_DCDN, EMIOUART0DSRN => UART0_DSRN, EMIOUART0DTRN => UART0_DTRN, EMIOUART0RIN => UART0_RIN, EMIOUART0RTSN => UART0_RTSN, EMIOUART0RX => UART0_RX, EMIOUART0TX => UART0_TX, EMIOUART1CTSN => UART1_CTSN, EMIOUART1DCDN => UART1_DCDN, EMIOUART1DSRN => UART1_DSRN, EMIOUART1DTRN => UART1_DTRN, EMIOUART1RIN => UART1_RIN, EMIOUART1RTSN => UART1_RTSN, EMIOUART1RX => UART1_RX, EMIOUART1TX => UART1_TX, EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT, EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT, EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0), EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT, EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT, EMIOWDTCLKI => WDT_CLK_IN, EMIOWDTRSTO => WDT_RST_OUT, EVENTEVENTI => EVENT_EVENTI, EVENTEVENTO => EVENT_EVENTO, EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0), EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0), FCLKCLK(3) => FCLK_CLK3, FCLKCLK(2) => FCLK_CLK2, FCLKCLK(1) => FCLK_CLK1, FCLKCLK(0) => FCLK_CLK_unbuffered(0), FCLKCLKTRIGN(3 downto 0) => B"0000", FCLKRESETN(3) => FCLK_RESET3_N, FCLKRESETN(2) => FCLK_RESET2_N, FCLKRESETN(1) => FCLK_RESET1_N, FCLKRESETN(0) => FCLK_RESET0_N, FPGAIDLEN => FPGA_IDLE_N, FTMDTRACEINATID(3 downto 0) => B"0000", FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK, FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000", FTMDTRACEINVALID => '0', FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0), FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3, FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2, FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1, FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0, FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3, FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2, FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1, FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0, FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0), FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3, FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2, FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1, FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0, FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3, FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2, FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1, FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0, IRQF2P(19) => Core1_nFIQ, IRQF2P(18) => Core0_nFIQ, IRQF2P(17) => Core1_nIRQ, IRQF2P(16) => Core0_nIRQ, IRQF2P(15 downto 1) => B"000000000000000", IRQF2P(0) => IRQ_F2P(0), IRQP2F(28) => IRQ_P2F_DMAC_ABORT, IRQP2F(27) => IRQ_P2F_DMAC7, IRQP2F(26) => IRQ_P2F_DMAC6, IRQP2F(25) => IRQ_P2F_DMAC5, IRQP2F(24) => IRQ_P2F_DMAC4, IRQP2F(23) => IRQ_P2F_DMAC3, IRQP2F(22) => IRQ_P2F_DMAC2, IRQP2F(21) => IRQ_P2F_DMAC1, IRQP2F(20) => IRQ_P2F_DMAC0, IRQP2F(19) => IRQ_P2F_SMC, IRQP2F(18) => IRQ_P2F_QSPI, IRQP2F(17) => IRQ_P2F_CTI, IRQP2F(16) => IRQ_P2F_GPIO, IRQP2F(15) => IRQ_P2F_USB0, IRQP2F(14) => IRQ_P2F_ENET0, IRQP2F(13) => IRQ_P2F_ENET_WAKE0, IRQP2F(12) => IRQ_P2F_SDIO0, IRQP2F(11) => IRQ_P2F_I2C0, IRQP2F(10) => IRQ_P2F_SPI0, IRQP2F(9) => IRQ_P2F_UART0, IRQP2F(8) => IRQ_P2F_CAN0, IRQP2F(7) => IRQ_P2F_USB1, IRQP2F(6) => IRQ_P2F_ENET1, IRQP2F(5) => IRQ_P2F_ENET_WAKE1, IRQP2F(4) => IRQ_P2F_SDIO1, IRQP2F(3) => IRQ_P2F_I2C1, IRQP2F(2) => IRQ_P2F_SPI1, IRQP2F(1) => IRQ_P2F_UART1, IRQP2F(0) => IRQ_P2F_CAN1, MAXIGP0ACLK => M_AXI_GP0_ACLK, MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2), MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1), MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0), MAXIGP0ARESETN => M_AXI_GP0_ARESETN, MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), MAXIGP0ARREADY => M_AXI_GP0_ARREADY, MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0), MAXIGP0ARVALID => M_AXI_GP0_ARVALID, MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2), MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1), MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0), MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), MAXIGP0AWREADY => M_AXI_GP0_AWREADY, MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0), MAXIGP0AWVALID => M_AXI_GP0_AWVALID, MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), MAXIGP0BREADY => M_AXI_GP0_BREADY, MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), MAXIGP0BVALID => M_AXI_GP0_BVALID, MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), MAXIGP0RLAST => M_AXI_GP0_RLAST, MAXIGP0RREADY => M_AXI_GP0_RREADY, MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), MAXIGP0RVALID => M_AXI_GP0_RVALID, MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), MAXIGP0WLAST => M_AXI_GP0_WLAST, MAXIGP0WREADY => M_AXI_GP0_WREADY, MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), MAXIGP0WVALID => M_AXI_GP0_WVALID, MAXIGP1ACLK => M_AXI_GP1_ACLK, MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0), MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0), MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2), MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1), MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0), MAXIGP1ARESETN => M_AXI_GP1_ARESETN, MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0), MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0), MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0), MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0), MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0), MAXIGP1ARREADY => M_AXI_GP1_ARREADY, MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0), MAXIGP1ARVALID => M_AXI_GP1_ARVALID, MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0), MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0), MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2), MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1), MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0), MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0), MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0), MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0), MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0), MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0), MAXIGP1AWREADY => M_AXI_GP1_AWREADY, MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0), MAXIGP1AWVALID => M_AXI_GP1_AWVALID, MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0), MAXIGP1BREADY => M_AXI_GP1_BREADY, MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0), MAXIGP1BVALID => M_AXI_GP1_BVALID, MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0), MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0), MAXIGP1RLAST => M_AXI_GP1_RLAST, MAXIGP1RREADY => M_AXI_GP1_RREADY, MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0), MAXIGP1RVALID => M_AXI_GP1_RVALID, MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0), MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0), MAXIGP1WLAST => M_AXI_GP1_WLAST, MAXIGP1WREADY => M_AXI_GP1_WREADY, MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0), MAXIGP1WVALID => M_AXI_GP1_WVALID, MIO(53 downto 0) => buffered_MIO(53 downto 0), PSCLK => buffered_PS_CLK, PSPORB => buffered_PS_PORB, PSSRSTB => buffered_PS_SRSTB, SAXIACPACLK => S_AXI_ACP_ACLK, SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0), SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0), SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0), SAXIACPARESETN => S_AXI_ACP_ARESETN, SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0), SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0), SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0), SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0), SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0), SAXIACPARREADY => S_AXI_ACP_ARREADY, SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0), SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0), SAXIACPARVALID => S_AXI_ACP_ARVALID, SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0), SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0), SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0), SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0), SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0), SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0), SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0), SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0), SAXIACPAWREADY => S_AXI_ACP_AWREADY, SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0), SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0), SAXIACPAWVALID => S_AXI_ACP_AWVALID, SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0), SAXIACPBREADY => S_AXI_ACP_BREADY, SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0), SAXIACPBVALID => S_AXI_ACP_BVALID, SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0), SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0), SAXIACPRLAST => S_AXI_ACP_RLAST, SAXIACPRREADY => S_AXI_ACP_RREADY, SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0), SAXIACPRVALID => S_AXI_ACP_RVALID, SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0), SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0), SAXIACPWLAST => S_AXI_ACP_WLAST, SAXIACPWREADY => S_AXI_ACP_WREADY, SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0), SAXIACPWVALID => S_AXI_ACP_WVALID, SAXIGP0ACLK => S_AXI_GP0_ACLK, SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0), SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0), SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0), SAXIGP0ARESETN => S_AXI_GP0_ARESETN, SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0), SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0), SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0), SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0), SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0), SAXIGP0ARREADY => S_AXI_GP0_ARREADY, SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0), SAXIGP0ARVALID => S_AXI_GP0_ARVALID, SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0), SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0), SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0), SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0), SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0), SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0), SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0), SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0), SAXIGP0AWREADY => S_AXI_GP0_AWREADY, SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0), SAXIGP0AWVALID => S_AXI_GP0_AWVALID, SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0), SAXIGP0BREADY => S_AXI_GP0_BREADY, SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0), SAXIGP0BVALID => S_AXI_GP0_BVALID, SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0), SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0), SAXIGP0RLAST => S_AXI_GP0_RLAST, SAXIGP0RREADY => S_AXI_GP0_RREADY, SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0), SAXIGP0RVALID => S_AXI_GP0_RVALID, SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0), SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0), SAXIGP0WLAST => S_AXI_GP0_WLAST, SAXIGP0WREADY => S_AXI_GP0_WREADY, SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0), SAXIGP0WVALID => S_AXI_GP0_WVALID, SAXIGP1ACLK => S_AXI_GP1_ACLK, SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0), SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0), SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0), SAXIGP1ARESETN => S_AXI_GP1_ARESETN, SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0), SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0), SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0), SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0), SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0), SAXIGP1ARREADY => S_AXI_GP1_ARREADY, SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0), SAXIGP1ARVALID => S_AXI_GP1_ARVALID, SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0), SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0), SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0), SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0), SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0), SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0), SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0), SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0), SAXIGP1AWREADY => S_AXI_GP1_AWREADY, SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0), SAXIGP1AWVALID => S_AXI_GP1_AWVALID, SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0), SAXIGP1BREADY => S_AXI_GP1_BREADY, SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0), SAXIGP1BVALID => S_AXI_GP1_BVALID, SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0), SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0), SAXIGP1RLAST => S_AXI_GP1_RLAST, SAXIGP1RREADY => S_AXI_GP1_RREADY, SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0), SAXIGP1RVALID => S_AXI_GP1_RVALID, SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0), SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0), SAXIGP1WLAST => S_AXI_GP1_WLAST, SAXIGP1WREADY => S_AXI_GP1_WREADY, SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0), SAXIGP1WVALID => S_AXI_GP1_WVALID, SAXIHP0ACLK => S_AXI_HP0_ACLK, SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0), SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0), SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0), SAXIHP0ARESETN => S_AXI_HP0_ARESETN, SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0), SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0), SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0), SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0), SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0), SAXIHP0ARREADY => S_AXI_HP0_ARREADY, SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0), SAXIHP0ARVALID => S_AXI_HP0_ARVALID, SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0), SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0), SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0), SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0), SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0), SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0), SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0), SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0), SAXIHP0AWREADY => S_AXI_HP0_AWREADY, SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0), SAXIHP0AWVALID => S_AXI_HP0_AWVALID, SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0), SAXIHP0BREADY => S_AXI_HP0_BREADY, SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0), SAXIHP0BVALID => S_AXI_HP0_BVALID, SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0), SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0), SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0), SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN, SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0), SAXIHP0RLAST => S_AXI_HP0_RLAST, SAXIHP0RREADY => S_AXI_HP0_RREADY, SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0), SAXIHP0RVALID => S_AXI_HP0_RVALID, SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0), SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0), SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0), SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0), SAXIHP0WLAST => S_AXI_HP0_WLAST, SAXIHP0WREADY => S_AXI_HP0_WREADY, SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN, SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0), SAXIHP0WVALID => S_AXI_HP0_WVALID, SAXIHP1ACLK => S_AXI_HP1_ACLK, SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0), SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0), SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0), SAXIHP1ARESETN => S_AXI_HP1_ARESETN, SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0), SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0), SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0), SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0), SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0), SAXIHP1ARREADY => S_AXI_HP1_ARREADY, SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0), SAXIHP1ARVALID => S_AXI_HP1_ARVALID, SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0), SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0), SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0), SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0), SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0), SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0), SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0), SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0), SAXIHP1AWREADY => S_AXI_HP1_AWREADY, SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0), SAXIHP1AWVALID => S_AXI_HP1_AWVALID, SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0), SAXIHP1BREADY => S_AXI_HP1_BREADY, SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0), SAXIHP1BVALID => S_AXI_HP1_BVALID, SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0), SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0), SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0), SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN, SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0), SAXIHP1RLAST => S_AXI_HP1_RLAST, SAXIHP1RREADY => S_AXI_HP1_RREADY, SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0), SAXIHP1RVALID => S_AXI_HP1_RVALID, SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0), SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0), SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0), SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0), SAXIHP1WLAST => S_AXI_HP1_WLAST, SAXIHP1WREADY => S_AXI_HP1_WREADY, SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN, SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0), SAXIHP1WVALID => S_AXI_HP1_WVALID, SAXIHP2ACLK => S_AXI_HP2_ACLK, SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0), SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0), SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0), SAXIHP2ARESETN => S_AXI_HP2_ARESETN, SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0), SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0), SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0), SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0), SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0), SAXIHP2ARREADY => S_AXI_HP2_ARREADY, SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0), SAXIHP2ARVALID => S_AXI_HP2_ARVALID, SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0), SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0), SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0), SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0), SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0), SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0), SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0), SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0), SAXIHP2AWREADY => S_AXI_HP2_AWREADY, SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0), SAXIHP2AWVALID => S_AXI_HP2_AWVALID, SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0), SAXIHP2BREADY => S_AXI_HP2_BREADY, SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0), SAXIHP2BVALID => S_AXI_HP2_BVALID, SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0), SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0), SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0), SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN, SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0), SAXIHP2RLAST => S_AXI_HP2_RLAST, SAXIHP2RREADY => S_AXI_HP2_RREADY, SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0), SAXIHP2RVALID => S_AXI_HP2_RVALID, SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0), SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0), SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0), SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0), SAXIHP2WLAST => S_AXI_HP2_WLAST, SAXIHP2WREADY => S_AXI_HP2_WREADY, SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN, SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0), SAXIHP2WVALID => S_AXI_HP2_WVALID, SAXIHP3ACLK => S_AXI_HP3_ACLK, SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0), SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0), SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0), SAXIHP3ARESETN => S_AXI_HP3_ARESETN, SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0), SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0), SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0), SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0), SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0), SAXIHP3ARREADY => S_AXI_HP3_ARREADY, SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0), SAXIHP3ARVALID => S_AXI_HP3_ARVALID, SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0), SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0), SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0), SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0), SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0), SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0), SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0), SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0), SAXIHP3AWREADY => S_AXI_HP3_AWREADY, SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0), SAXIHP3AWVALID => S_AXI_HP3_AWVALID, SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0), SAXIHP3BREADY => S_AXI_HP3_BREADY, SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0), SAXIHP3BVALID => S_AXI_HP3_BVALID, SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0), SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0), SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0), SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN, SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0), SAXIHP3RLAST => S_AXI_HP3_RLAST, SAXIHP3RREADY => S_AXI_HP3_RREADY, SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0), SAXIHP3RVALID => S_AXI_HP3_RVALID, SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0), SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0), SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0), SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0), SAXIHP3WLAST => S_AXI_HP3_WLAST, SAXIHP3WREADY => S_AXI_HP3_WREADY, SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN, SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0), SAXIHP3WVALID => S_AXI_HP3_WVALID ); PS_CLK_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_CLK, PAD => PS_CLK ); PS_PORB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_PORB, PAD => PS_PORB ); PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_SRSTB, PAD => PS_SRSTB ); SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_CMD_T_n, O => SDIO0_CMD_T ); \SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(0), O => SDIO0_DATA_T(0) ); \SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(1), O => SDIO0_DATA_T(1) ); \SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(2), O => SDIO0_DATA_T(2) ); \SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(3), O => SDIO0_DATA_T(3) ); SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_CMD_T_n, O => SDIO1_CMD_T ); \SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(0), O => SDIO1_DATA_T(0) ); \SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(1), O => SDIO1_DATA_T(1) ); \SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(2), O => SDIO1_DATA_T(2) ); \SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(3), O => SDIO1_DATA_T(3) ); SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MISO_T_n, O => SPI0_MISO_T ); SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MOSI_T_n, O => SPI0_MOSI_T ); SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SCLK_T_n, O => SPI0_SCLK_T ); SPI0_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SS_T_n, O => SPI0_SS_T ); SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MISO_T_n, O => SPI1_MISO_T ); SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MOSI_T_n, O => SPI1_MOSI_T ); SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SCLK_T_n, O => SPI1_SCLK_T ); SPI1_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SS_T_n, O => SPI1_SS_T ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG port map ( I => FCLK_CLK_unbuffered(0), O => FCLK_CLK0 ); \genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(0), PAD => MIO(0) ); \genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(10), PAD => MIO(10) ); \genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(11), PAD => MIO(11) ); \genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(12), PAD => MIO(12) ); \genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(13), PAD => MIO(13) ); \genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(14), PAD => MIO(14) ); \genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(15), PAD => MIO(15) ); \genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(16), PAD => MIO(16) ); \genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(17), PAD => MIO(17) ); \genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(18), PAD => MIO(18) ); \genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(19), PAD => MIO(19) ); \genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(1), PAD => MIO(1) ); \genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(20), PAD => MIO(20) ); \genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(21), PAD => MIO(21) ); \genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(22), PAD => MIO(22) ); \genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(23), PAD => MIO(23) ); \genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(24), PAD => MIO(24) ); \genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(25), PAD => MIO(25) ); \genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(26), PAD => MIO(26) ); \genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(27), PAD => MIO(27) ); \genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(28), PAD => MIO(28) ); \genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(29), PAD => MIO(29) ); \genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(2), PAD => MIO(2) ); \genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(30), PAD => MIO(30) ); \genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(31), PAD => MIO(31) ); \genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(32), PAD => MIO(32) ); \genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(33), PAD => MIO(33) ); \genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(34), PAD => MIO(34) ); \genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(35), PAD => MIO(35) ); \genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(36), PAD => MIO(36) ); \genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(37), PAD => MIO(37) ); \genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(38), PAD => MIO(38) ); \genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(39), PAD => MIO(39) ); \genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(3), PAD => MIO(3) ); \genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(40), PAD => MIO(40) ); \genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(41), PAD => MIO(41) ); \genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(42), PAD => MIO(42) ); \genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(43), PAD => MIO(43) ); \genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(44), PAD => MIO(44) ); \genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(45), PAD => MIO(45) ); \genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(46), PAD => MIO(46) ); \genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(47), PAD => MIO(47) ); \genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(48), PAD => MIO(48) ); \genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(49), PAD => MIO(49) ); \genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(4), PAD => MIO(4) ); \genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(50), PAD => MIO(50) ); \genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(51), PAD => MIO(51) ); \genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(52), PAD => MIO(52) ); \genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(53), PAD => MIO(53) ); \genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(5), PAD => MIO(5) ); \genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(6), PAD => MIO(6) ); \genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(7), PAD => MIO(7) ); \genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(8), PAD => MIO(8) ); \genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(9), PAD => MIO(9) ); \genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(0), PAD => DDR_BankAddr(0) ); \genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(1), PAD => DDR_BankAddr(1) ); \genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(2), PAD => DDR_BankAddr(2) ); \genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(0), PAD => DDR_Addr(0) ); \genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(10), PAD => DDR_Addr(10) ); \genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(11), PAD => DDR_Addr(11) ); \genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(12), PAD => DDR_Addr(12) ); \genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(13), PAD => DDR_Addr(13) ); \genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(14), PAD => DDR_Addr(14) ); \genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(1), PAD => DDR_Addr(1) ); \genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(2), PAD => DDR_Addr(2) ); \genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(3), PAD => DDR_Addr(3) ); \genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(4), PAD => DDR_Addr(4) ); \genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(5), PAD => DDR_Addr(5) ); \genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(6), PAD => DDR_Addr(6) ); \genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(7), PAD => DDR_Addr(7) ); \genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(8), PAD => DDR_Addr(8) ); \genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(9), PAD => DDR_Addr(9) ); \genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(0), PAD => DDR_DM(0) ); \genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(1), PAD => DDR_DM(1) ); \genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(2), PAD => DDR_DM(2) ); \genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(3), PAD => DDR_DM(3) ); \genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(0), PAD => DDR_DQ(0) ); \genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(10), PAD => DDR_DQ(10) ); \genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(11), PAD => DDR_DQ(11) ); \genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(12), PAD => DDR_DQ(12) ); \genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(13), PAD => DDR_DQ(13) ); \genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(14), PAD => DDR_DQ(14) ); \genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(15), PAD => DDR_DQ(15) ); \genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(16), PAD => DDR_DQ(16) ); \genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(17), PAD => DDR_DQ(17) ); \genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(18), PAD => DDR_DQ(18) ); \genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(19), PAD => DDR_DQ(19) ); \genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(1), PAD => DDR_DQ(1) ); \genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(20), PAD => DDR_DQ(20) ); \genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(21), PAD => DDR_DQ(21) ); \genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(22), PAD => DDR_DQ(22) ); \genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(23), PAD => DDR_DQ(23) ); \genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(24), PAD => DDR_DQ(24) ); \genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(25), PAD => DDR_DQ(25) ); \genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(26), PAD => DDR_DQ(26) ); \genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(27), PAD => DDR_DQ(27) ); \genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(28), PAD => DDR_DQ(28) ); \genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(29), PAD => DDR_DQ(29) ); \genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(2), PAD => DDR_DQ(2) ); \genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(30), PAD => DDR_DQ(30) ); \genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(31), PAD => DDR_DQ(31) ); \genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(3), PAD => DDR_DQ(3) ); \genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(4), PAD => DDR_DQ(4) ); \genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(5), PAD => DDR_DQ(5) ); \genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(6), PAD => DDR_DQ(6) ); \genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(7), PAD => DDR_DQ(7) ); \genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(8), PAD => DDR_DQ(8) ); \genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(9), PAD => DDR_DQ(9) ); \genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(0), PAD => DDR_DQS_n(0) ); \genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(1), PAD => DDR_DQS_n(1) ); \genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(2), PAD => DDR_DQS_n(2) ); \genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(3), PAD => DDR_DQS_n(3) ); \genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(0), PAD => DDR_DQS(0) ); \genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(1), PAD => DDR_DQS(1) ); \genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(2), PAD => DDR_DQS(2) ); \genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(3), PAD => DDR_DQS(3) ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[0]\ ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[0]\(1) ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[7]\(1) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[7]\(0) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[6]\(1) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[6]\(0) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[5]\(1) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[5]\(0) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[4]\(1) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[4]\(0) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[3]\(1) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[3]\(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[0]\(0) ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[2]\(1) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[2]\(0) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[1]\(1) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[1]\(0) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[7]\ ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[6]\ ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[5]\ ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[4]\ ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[3]\ ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[2]\ ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[1]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2018.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of inst : label is 4; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of inst : label is 4; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of inst : label is 32; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of inst : label is 64; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of inst : label is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of inst : label is 0; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of inst : label is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of inst : label is 0; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of inst : label is "TRUE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of inst : label is "FALSE"; attribute C_GP0_EN_MODIFIABLE_TXN : integer; attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1; attribute C_GP1_EN_MODIFIABLE_TXN : integer; attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of inst : label is "DIRECT"; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of inst : label is 54; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of inst : label is "clg400"; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of inst : label is "PRODUCTION"; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8; attribute C_USE_AXI_NONSECURE : integer; attribute C_USE_AXI_NONSECURE of inst : label is 0; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0; attribute C_USE_M_AXI_GP0 : integer; attribute C_USE_M_AXI_GP0 of inst : label is 1; attribute C_USE_M_AXI_GP1 : integer; attribute C_USE_M_AXI_GP1 of inst : label is 0; attribute C_USE_S_AXI_ACP : integer; attribute C_USE_S_AXI_ACP of inst : label is 0; attribute C_USE_S_AXI_GP0 : integer; attribute C_USE_S_AXI_GP0 of inst : label is 0; attribute C_USE_S_AXI_GP1 : integer; attribute C_USE_S_AXI_GP1 of inst : label is 0; attribute C_USE_S_AXI_HP0 : integer; attribute C_USE_S_AXI_HP0 of inst : label is 0; attribute C_USE_S_AXI_HP1 : integer; attribute C_USE_S_AXI_HP1 of inst : label is 0; attribute C_USE_S_AXI_HP2 : integer; attribute C_USE_S_AXI_HP2 of inst : label is 0; attribute C_USE_S_AXI_HP3 : integer; attribute C_USE_S_AXI_HP3 of inst : label is 0; attribute HW_HANDOFF : string; attribute HW_HANDOFF of inst : label is "design_1_processing_system7_0_0.hwdef"; attribute POWER : string; attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={50} usageRate={0.5} />/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N"; attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE"; attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N"; attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P"; attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N"; attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N"; attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT"; attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N"; attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"; attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"; attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N"; attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0"; attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"; attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW"; attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"; attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"; attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"; attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"; attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"; attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"; attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false"; attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"; attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT"; attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT"; attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR"; attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA"; attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM"; attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ"; attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P"; attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11"; attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N"; attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"; attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"; attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"; attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"; attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"; attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"; attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"; attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"; attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"; attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL"; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 port map ( CAN0_PHY_RX => '0', CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED, CAN1_PHY_RX => '0', CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED, Core0_nFIQ => '0', Core0_nIRQ => '0', Core1_nFIQ => '0', Core1_nIRQ => '0', DDR_ARB(3 downto 0) => B"0000", DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0), DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0), DDR_CAS_n => DDR_CAS_n, DDR_CKE => DDR_CKE, DDR_CS_n => DDR_CS_n, DDR_Clk => DDR_Clk, DDR_Clk_n => DDR_Clk_n, DDR_DM(3 downto 0) => DDR_DM(3 downto 0), DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0), DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0), DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0), DDR_DRSTB => DDR_DRSTB, DDR_ODT => DDR_ODT, DDR_RAS_n => DDR_RAS_n, DDR_VRN => DDR_VRN, DDR_VRP => DDR_VRP, DDR_WEB => DDR_WEB, DMA0_ACLK => '0', DMA0_DAREADY => '0', DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0), DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED, DMA0_DRLAST => '0', DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED, DMA0_DRTYPE(1 downto 0) => B"00", DMA0_DRVALID => '0', DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED, DMA1_ACLK => '0', DMA1_DAREADY => '0', DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0), DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED, DMA1_DRLAST => '0', DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED, DMA1_DRTYPE(1 downto 0) => B"00", DMA1_DRVALID => '0', DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED, DMA2_ACLK => '0', DMA2_DAREADY => '0', DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0), DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED, DMA2_DRLAST => '0', DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED, DMA2_DRTYPE(1 downto 0) => B"00", DMA2_DRVALID => '0', DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED, DMA3_ACLK => '0', DMA3_DAREADY => '0', DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0), DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED, DMA3_DRLAST => '0', DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED, DMA3_DRTYPE(1 downto 0) => B"00", DMA3_DRVALID => '0', DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED, ENET0_EXT_INTIN => '0', ENET0_GMII_COL => '0', ENET0_GMII_CRS => '0', ENET0_GMII_RXD(7 downto 0) => B"00000000", ENET0_GMII_RX_CLK => '0', ENET0_GMII_RX_DV => '0', ENET0_GMII_RX_ER => '0', ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0), ENET0_GMII_TX_CLK => '0', ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED, ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED, ENET0_MDIO_I => '0', ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED, ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED, ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED, ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED, ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED, ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED, ENET1_EXT_INTIN => '0', ENET1_GMII_COL => '0', ENET1_GMII_CRS => '0', ENET1_GMII_RXD(7 downto 0) => B"00000000", ENET1_GMII_RX_CLK => '0', ENET1_GMII_RX_DV => '0', ENET1_GMII_RX_ER => '0', ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0), ENET1_GMII_TX_CLK => '0', ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED, ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED, ENET1_MDIO_I => '0', ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED, ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED, ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED, ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED, ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED, ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED, EVENT_EVENTI => '0', EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED, EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0), EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0), FCLK_CLK0 => FCLK_CLK0, FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED, FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED, FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED, FCLK_CLKTRIG0_N => '0', FCLK_CLKTRIG1_N => '0', FCLK_CLKTRIG2_N => '0', FCLK_CLKTRIG3_N => '0', FCLK_RESET0_N => FCLK_RESET0_N, FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED, FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED, FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED, FPGA_IDLE_N => '0', FTMD_TRACEIN_ATID(3 downto 0) => B"0000", FTMD_TRACEIN_CLK => '0', FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000", FTMD_TRACEIN_VALID => '0', FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000", FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED, FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED, FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED, FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED, FTMT_F2P_TRIG_0 => '0', FTMT_F2P_TRIG_1 => '0', FTMT_F2P_TRIG_2 => '0', FTMT_F2P_TRIG_3 => '0', FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0), FTMT_P2F_TRIGACK_0 => '0', FTMT_P2F_TRIGACK_1 => '0', FTMT_P2F_TRIGACK_2 => '0', FTMT_P2F_TRIGACK_3 => '0', FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED, FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED, FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED, FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED, GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0), GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0), I2C0_SCL_I => '0', I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED, I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED, I2C0_SDA_I => '0', I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED, I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED, I2C1_SCL_I => '0', I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED, I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED, I2C1_SDA_I => '0', I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED, I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED, IRQ_F2P(0) => '0', IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED, IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED, IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED, IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED, IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED, IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED, IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED, IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED, IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED, IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED, IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED, IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED, IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED, IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED, IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED, IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED, IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED, IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED, IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED, IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED, IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED, IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED, IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED, IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED, IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED, IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED, IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED, IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED, IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED, MIO(53 downto 0) => MIO(53 downto 0), M_AXI_GP0_ACLK => M_AXI_GP0_ACLK, M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0), M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED, M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY, M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0), M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID, M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0), M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY, M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0), M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID, M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), M_AXI_GP0_BREADY => M_AXI_GP0_BREADY, M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), M_AXI_GP0_BVALID => M_AXI_GP0_BVALID, M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), M_AXI_GP0_RLAST => M_AXI_GP0_RLAST, M_AXI_GP0_RREADY => M_AXI_GP0_RREADY, M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), M_AXI_GP0_RVALID => M_AXI_GP0_RVALID, M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), M_AXI_GP0_WLAST => M_AXI_GP0_WLAST, M_AXI_GP0_WREADY => M_AXI_GP0_WREADY, M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), M_AXI_GP0_WVALID => M_AXI_GP0_WVALID, M_AXI_GP1_ACLK => '0', M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0), M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0), M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0), M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED, M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0), M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0), M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0), M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0), M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0), M_AXI_GP1_ARREADY => '0', M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0), M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED, M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0), M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0), M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0), M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0), M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0), M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0), M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0), M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0), M_AXI_GP1_AWREADY => '0', M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0), M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED, M_AXI_GP1_BID(11 downto 0) => B"000000000000", M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED, M_AXI_GP1_BRESP(1 downto 0) => B"00", M_AXI_GP1_BVALID => '0', M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000", M_AXI_GP1_RID(11 downto 0) => B"000000000000", M_AXI_GP1_RLAST => '0', M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED, M_AXI_GP1_RRESP(1 downto 0) => B"00", M_AXI_GP1_RVALID => '0', M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0), M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0), M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED, M_AXI_GP1_WREADY => '0', M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0), M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED, PJTAG_TCK => '0', PJTAG_TDI => '0', PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED, PJTAG_TMS => '0', PS_CLK => PS_CLK, PS_PORB => PS_PORB, PS_SRSTB => PS_SRSTB, SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED, SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0), SDIO0_CDN => '0', SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED, SDIO0_CLK_FB => '0', SDIO0_CMD_I => '0', SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED, SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED, SDIO0_DATA_I(3 downto 0) => B"0000", SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0), SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0), SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED, SDIO0_WP => '0', SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED, SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0), SDIO1_CDN => '0', SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED, SDIO1_CLK_FB => '0', SDIO1_CMD_I => '0', SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED, SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED, SDIO1_DATA_I(3 downto 0) => B"0000", SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0), SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0), SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED, SDIO1_WP => '0', SPI0_MISO_I => '0', SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED, SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED, SPI0_MOSI_I => '0', SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED, SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED, SPI0_SCLK_I => '0', SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED, SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED, SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED, SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED, SPI0_SS_I => '0', SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED, SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED, SPI1_MISO_I => '0', SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED, SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED, SPI1_MOSI_I => '0', SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED, SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED, SPI1_SCLK_I => '0', SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED, SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED, SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED, SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED, SPI1_SS_I => '0', SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED, SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED, SRAM_INTIN => '0', S_AXI_ACP_ACLK => '0', S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_ACP_ARBURST(1 downto 0) => B"00", S_AXI_ACP_ARCACHE(3 downto 0) => B"0000", S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED, S_AXI_ACP_ARID(2 downto 0) => B"000", S_AXI_ACP_ARLEN(3 downto 0) => B"0000", S_AXI_ACP_ARLOCK(1 downto 0) => B"00", S_AXI_ACP_ARPROT(2 downto 0) => B"000", S_AXI_ACP_ARQOS(3 downto 0) => B"0000", S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED, S_AXI_ACP_ARSIZE(2 downto 0) => B"000", S_AXI_ACP_ARUSER(4 downto 0) => B"00000", S_AXI_ACP_ARVALID => '0', S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_ACP_AWBURST(1 downto 0) => B"00", S_AXI_ACP_AWCACHE(3 downto 0) => B"0000", S_AXI_ACP_AWID(2 downto 0) => B"000", S_AXI_ACP_AWLEN(3 downto 0) => B"0000", S_AXI_ACP_AWLOCK(1 downto 0) => B"00", S_AXI_ACP_AWPROT(2 downto 0) => B"000", S_AXI_ACP_AWQOS(3 downto 0) => B"0000", S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED, S_AXI_ACP_AWSIZE(2 downto 0) => B"000", S_AXI_ACP_AWUSER(4 downto 0) => B"00000", S_AXI_ACP_AWVALID => '0', S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0), S_AXI_ACP_BREADY => '0', S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED, S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0), S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0), S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED, S_AXI_ACP_RREADY => '0', S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED, S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_ACP_WID(2 downto 0) => B"000", S_AXI_ACP_WLAST => '0', S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED, S_AXI_ACP_WSTRB(7 downto 0) => B"00000000", S_AXI_ACP_WVALID => '0', S_AXI_GP0_ACLK => '0', S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_ARBURST(1 downto 0) => B"00", S_AXI_GP0_ARCACHE(3 downto 0) => B"0000", S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED, S_AXI_GP0_ARID(5 downto 0) => B"000000", S_AXI_GP0_ARLEN(3 downto 0) => B"0000", S_AXI_GP0_ARLOCK(1 downto 0) => B"00", S_AXI_GP0_ARPROT(2 downto 0) => B"000", S_AXI_GP0_ARQOS(3 downto 0) => B"0000", S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED, S_AXI_GP0_ARSIZE(2 downto 0) => B"000", S_AXI_GP0_ARVALID => '0', S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_AWBURST(1 downto 0) => B"00", S_AXI_GP0_AWCACHE(3 downto 0) => B"0000", S_AXI_GP0_AWID(5 downto 0) => B"000000", S_AXI_GP0_AWLEN(3 downto 0) => B"0000", S_AXI_GP0_AWLOCK(1 downto 0) => B"00", S_AXI_GP0_AWPROT(2 downto 0) => B"000", S_AXI_GP0_AWQOS(3 downto 0) => B"0000", S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED, S_AXI_GP0_AWSIZE(2 downto 0) => B"000", S_AXI_GP0_AWVALID => '0', S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0), S_AXI_GP0_BREADY => '0', S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED, S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0), S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED, S_AXI_GP0_RREADY => '0', S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED, S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_WID(5 downto 0) => B"000000", S_AXI_GP0_WLAST => '0', S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED, S_AXI_GP0_WSTRB(3 downto 0) => B"0000", S_AXI_GP0_WVALID => '0', S_AXI_GP1_ACLK => '0', S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_ARBURST(1 downto 0) => B"00", S_AXI_GP1_ARCACHE(3 downto 0) => B"0000", S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED, S_AXI_GP1_ARID(5 downto 0) => B"000000", S_AXI_GP1_ARLEN(3 downto 0) => B"0000", S_AXI_GP1_ARLOCK(1 downto 0) => B"00", S_AXI_GP1_ARPROT(2 downto 0) => B"000", S_AXI_GP1_ARQOS(3 downto 0) => B"0000", S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED, S_AXI_GP1_ARSIZE(2 downto 0) => B"000", S_AXI_GP1_ARVALID => '0', S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_AWBURST(1 downto 0) => B"00", S_AXI_GP1_AWCACHE(3 downto 0) => B"0000", S_AXI_GP1_AWID(5 downto 0) => B"000000", S_AXI_GP1_AWLEN(3 downto 0) => B"0000", S_AXI_GP1_AWLOCK(1 downto 0) => B"00", S_AXI_GP1_AWPROT(2 downto 0) => B"000", S_AXI_GP1_AWQOS(3 downto 0) => B"0000", S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED, S_AXI_GP1_AWSIZE(2 downto 0) => B"000", S_AXI_GP1_AWVALID => '0', S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0), S_AXI_GP1_BREADY => '0', S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED, S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0), S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED, S_AXI_GP1_RREADY => '0', S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED, S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_WID(5 downto 0) => B"000000", S_AXI_GP1_WLAST => '0', S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED, S_AXI_GP1_WSTRB(3 downto 0) => B"0000", S_AXI_GP1_WVALID => '0', S_AXI_HP0_ACLK => '0', S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP0_ARBURST(1 downto 0) => B"00", S_AXI_HP0_ARCACHE(3 downto 0) => B"0000", S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED, S_AXI_HP0_ARID(5 downto 0) => B"000000", S_AXI_HP0_ARLEN(3 downto 0) => B"0000", S_AXI_HP0_ARLOCK(1 downto 0) => B"00", S_AXI_HP0_ARPROT(2 downto 0) => B"000", S_AXI_HP0_ARQOS(3 downto 0) => B"0000", S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED, S_AXI_HP0_ARSIZE(2 downto 0) => B"000", S_AXI_HP0_ARVALID => '0', S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP0_AWBURST(1 downto 0) => B"00", S_AXI_HP0_AWCACHE(3 downto 0) => B"0000", S_AXI_HP0_AWID(5 downto 0) => B"000000", S_AXI_HP0_AWLEN(3 downto 0) => B"0000", S_AXI_HP0_AWLOCK(1 downto 0) => B"00", S_AXI_HP0_AWPROT(2 downto 0) => B"000", S_AXI_HP0_AWQOS(3 downto 0) => B"0000", S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED, S_AXI_HP0_AWSIZE(2 downto 0) => B"000", S_AXI_HP0_AWVALID => '0', S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0), S_AXI_HP0_BREADY => '0', S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED, S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP0_RDISSUECAP1_EN => '0', S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0), S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED, S_AXI_HP0_RREADY => '0', S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED, S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP0_WID(5 downto 0) => B"000000", S_AXI_HP0_WLAST => '0', S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED, S_AXI_HP0_WRISSUECAP1_EN => '0', S_AXI_HP0_WSTRB(7 downto 0) => B"00000000", S_AXI_HP0_WVALID => '0', S_AXI_HP1_ACLK => '0', S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP1_ARBURST(1 downto 0) => B"00", S_AXI_HP1_ARCACHE(3 downto 0) => B"0000", S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED, S_AXI_HP1_ARID(5 downto 0) => B"000000", S_AXI_HP1_ARLEN(3 downto 0) => B"0000", S_AXI_HP1_ARLOCK(1 downto 0) => B"00", S_AXI_HP1_ARPROT(2 downto 0) => B"000", S_AXI_HP1_ARQOS(3 downto 0) => B"0000", S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED, S_AXI_HP1_ARSIZE(2 downto 0) => B"000", S_AXI_HP1_ARVALID => '0', S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP1_AWBURST(1 downto 0) => B"00", S_AXI_HP1_AWCACHE(3 downto 0) => B"0000", S_AXI_HP1_AWID(5 downto 0) => B"000000", S_AXI_HP1_AWLEN(3 downto 0) => B"0000", S_AXI_HP1_AWLOCK(1 downto 0) => B"00", S_AXI_HP1_AWPROT(2 downto 0) => B"000", S_AXI_HP1_AWQOS(3 downto 0) => B"0000", S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED, S_AXI_HP1_AWSIZE(2 downto 0) => B"000", S_AXI_HP1_AWVALID => '0', S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0), S_AXI_HP1_BREADY => '0', S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED, S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP1_RDISSUECAP1_EN => '0', S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0), S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED, S_AXI_HP1_RREADY => '0', S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED, S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP1_WID(5 downto 0) => B"000000", S_AXI_HP1_WLAST => '0', S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED, S_AXI_HP1_WRISSUECAP1_EN => '0', S_AXI_HP1_WSTRB(7 downto 0) => B"00000000", S_AXI_HP1_WVALID => '0', S_AXI_HP2_ACLK => '0', S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP2_ARBURST(1 downto 0) => B"00", S_AXI_HP2_ARCACHE(3 downto 0) => B"0000", S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED, S_AXI_HP2_ARID(5 downto 0) => B"000000", S_AXI_HP2_ARLEN(3 downto 0) => B"0000", S_AXI_HP2_ARLOCK(1 downto 0) => B"00", S_AXI_HP2_ARPROT(2 downto 0) => B"000", S_AXI_HP2_ARQOS(3 downto 0) => B"0000", S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED, S_AXI_HP2_ARSIZE(2 downto 0) => B"000", S_AXI_HP2_ARVALID => '0', S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP2_AWBURST(1 downto 0) => B"00", S_AXI_HP2_AWCACHE(3 downto 0) => B"0000", S_AXI_HP2_AWID(5 downto 0) => B"000000", S_AXI_HP2_AWLEN(3 downto 0) => B"0000", S_AXI_HP2_AWLOCK(1 downto 0) => B"00", S_AXI_HP2_AWPROT(2 downto 0) => B"000", S_AXI_HP2_AWQOS(3 downto 0) => B"0000", S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED, S_AXI_HP2_AWSIZE(2 downto 0) => B"000", S_AXI_HP2_AWVALID => '0', S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0), S_AXI_HP2_BREADY => '0', S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED, S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP2_RDISSUECAP1_EN => '0', S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0), S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED, S_AXI_HP2_RREADY => '0', S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED, S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP2_WID(5 downto 0) => B"000000", S_AXI_HP2_WLAST => '0', S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED, S_AXI_HP2_WRISSUECAP1_EN => '0', S_AXI_HP2_WSTRB(7 downto 0) => B"00000000", S_AXI_HP2_WVALID => '0', S_AXI_HP3_ACLK => '0', S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP3_ARBURST(1 downto 0) => B"00", S_AXI_HP3_ARCACHE(3 downto 0) => B"0000", S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED, S_AXI_HP3_ARID(5 downto 0) => B"000000", S_AXI_HP3_ARLEN(3 downto 0) => B"0000", S_AXI_HP3_ARLOCK(1 downto 0) => B"00", S_AXI_HP3_ARPROT(2 downto 0) => B"000", S_AXI_HP3_ARQOS(3 downto 0) => B"0000", S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED, S_AXI_HP3_ARSIZE(2 downto 0) => B"000", S_AXI_HP3_ARVALID => '0', S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP3_AWBURST(1 downto 0) => B"00", S_AXI_HP3_AWCACHE(3 downto 0) => B"0000", S_AXI_HP3_AWID(5 downto 0) => B"000000", S_AXI_HP3_AWLEN(3 downto 0) => B"0000", S_AXI_HP3_AWLOCK(1 downto 0) => B"00", S_AXI_HP3_AWPROT(2 downto 0) => B"000", S_AXI_HP3_AWQOS(3 downto 0) => B"0000", S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED, S_AXI_HP3_AWSIZE(2 downto 0) => B"000", S_AXI_HP3_AWVALID => '0', S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0), S_AXI_HP3_BREADY => '0', S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED, S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP3_RDISSUECAP1_EN => '0', S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0), S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED, S_AXI_HP3_RREADY => '0', S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED, S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP3_WID(5 downto 0) => B"000000", S_AXI_HP3_WLAST => '0', S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED, S_AXI_HP3_WRISSUECAP1_EN => '0', S_AXI_HP3_WSTRB(7 downto 0) => B"00000000", S_AXI_HP3_WVALID => '0', TRACE_CLK => '0', TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED, TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED, TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0), TTC0_CLK0_IN => '0', TTC0_CLK1_IN => '0', TTC0_CLK2_IN => '0', TTC0_WAVE0_OUT => NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED, TTC0_WAVE1_OUT => NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED, TTC0_WAVE2_OUT => NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED, TTC1_CLK0_IN => '0', TTC1_CLK1_IN => '0', TTC1_CLK2_IN => '0', TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED, TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED, TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED, UART0_CTSN => '0', UART0_DCDN => '0', UART0_DSRN => '0', UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED, UART0_RIN => '0', UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED, UART0_RX => '1', UART0_TX => NLW_inst_UART0_TX_UNCONNECTED, UART1_CTSN => '0', UART1_DCDN => '0', UART1_DSRN => '0', UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED, UART1_RIN => '0', UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED, UART1_RX => '1', UART1_TX => NLW_inst_UART1_TX_UNCONNECTED, USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT, USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT, USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0), USB1_VBUS_PWRFAULT => '0', USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED, WDT_CLK_IN => '0', WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED ); end STRUCTURE;
-- NEED RESULT: ARCH00687: Allocators with dynamic composite subtype indication passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00687 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.3.6 (2) -- 7.3.6 (9) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00687) -- ENT00687_Test_Bench(ARCH00687_Test_Bench) -- -- REVISION HISTORY: -- -- 08-SEP-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.test_report ; architecture ARCH00687 of E00000 is procedure p1 ( constant lowb : integer := 1 ; constant highb : integer := 10 ; constant lowb_i2 : integer := 0 ; constant highb_i2 : integer := 1000 ; constant lowb_p : integer := -100 ; constant highb_p : integer := 1000 ; constant lowb_r : real := 0.0 ; constant highb_r : real := 1000.0 ; constant lowb_r2 : real := 8.0 ; constant highb_r2 : real := 80.0 -- ) is -- -- assertion: c_xxxxx_2 >= c_xxxxx_1 -- enumeration types -- predefined -- boolean constant c_boolean_1 : boolean := false ; constant c_boolean_2 : boolean := true ; -- type boolean_vector is array (integer range <>) of boolean ; subtype boolean_vector_range1 is integer range lowb to highb ; subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ; constant c_st_boolean_vector_1 : st_boolean_vector := (others => c_boolean_1) ; constant c_st_boolean_vector_2 : st_boolean_vector := (others => c_boolean_2) ; -- -- bit constant c_bit_1 : bit := '0' ; constant c_bit_2 : bit := '1' ; -- constant c_bit_vector_1 : bit_vector := B"0000" ; constant c_bit_vector_2 : bit_vector := B"1111" ; subtype bit_vector_range1 is integer range lowb to highb ; subtype st_bit_vector is bit_vector (bit_vector_range1) ; constant c_st_bit_vector_1 : st_bit_vector := (others => c_bit_1) ; constant c_st_bit_vector_2 : st_bit_vector := (others => c_bit_2) ; -- severity_level constant c_severity_level_1 : severity_level := NOTE ; constant c_severity_level_2 : severity_level := WARNING ; -- type severity_level_vector is array (integer range <>) of severity_level ; subtype severity_level_vector_range1 is integer range lowb to highb ; subtype st_severity_level_vector is severity_level_vector (severity_level_vector_range1) ; constant c_st_severity_level_vector_1 : st_severity_level_vector := (others => c_severity_level_1) ; constant c_st_severity_level_vector_2 : st_severity_level_vector := (others => c_severity_level_2) ; -- -- character constant c_character_1 : character := 'A' ; constant c_character_2 : character := 'a' ; -- constant c_string_1 : string := "ABC0000" ; constant c_string_2 : string := "ABC1111" ; subtype string_range1 is integer range lowb to highb ; subtype st_string is string (string_range1) ; constant c_st_string_1 : st_string := (others => c_character_1) ; constant c_st_string_2 : st_string := (others => c_character_2) ; -- user defined enumeration type t_enum1 is (en1, en2, en3, en4) ; constant c_t_enum1_1 : t_enum1 := en1 ; constant c_t_enum1_2 : t_enum1 := en2 ; subtype st_enum1 is t_enum1 range en4 downto en1 ; constant c_st_enum1_1 : st_enum1 := en1 ; constant c_st_enum1_2 : st_enum1 := en2 ; -- type enum1_vector is array (integer range <>) of st_enum1 ; subtype enum1_vector_range1 is integer range lowb to highb ; subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ; constant c_st_enum1_vector_1 : st_enum1_vector := (others => c_st_enum1_1) ; constant c_st_enum1_vector_2 : st_enum1_vector := (others => c_st_enum1_2) ; -- integer types -- predefined constant c_integer_1 : integer := lowb ; constant c_integer_2 : integer := highb ; -- type integer_vector is array (integer range <>) of integer ; subtype integer_vector_range1 is integer range lowb to highb ; subtype st_integer_vector is integer_vector (integer_vector_range1) ; constant c_st_integer_vector_1 : st_integer_vector := (others => c_integer_1) ; constant c_st_integer_vector_2 : st_integer_vector := (others => c_integer_2) ; -- -- user defined integer type type t_int1 is range 0 to 100 ; constant c_t_int1_1 : t_int1 := 0 ; constant c_t_int1_2 : t_int1 := 10 ; subtype st_int1 is t_int1 range 8 to 60 ; constant c_st_int1_1 : st_int1 := 8 ; constant c_st_int1_2 : st_int1 := 9 ; -- type int1_vector is array (integer range <>) of st_int1 ; subtype int1_vector_range1 is integer range lowb to highb ; subtype st_int1_vector is int1_vector (int1_vector_range1) ; constant c_st_int1_vector_1 : st_int1_vector := (others => c_st_int1_1) ; constant c_st_int1_vector_2 : st_int1_vector := (others => c_st_int1_2) ; -- -- physical types -- predefined constant c_time_1 : time := 1 ns ; constant c_time_2 : time := 2 ns ; -- type time_vector is array (integer range <>) of time ; subtype time_vector_range1 is integer range lowb to highb ; subtype st_time_vector is time_vector (time_vector_range1) ; constant c_st_time_vector_1 : st_time_vector := (others => c_time_1) ; constant c_st_time_vector_2 : st_time_vector := (others => c_time_2) ; -- -- user defined physical type type t_phys1 is range -100 to 1000 units phys1_1 ; phys1_2 = 10 phys1_1 ; phys1_3 = 10 phys1_2 ; phys1_4 = 10 phys1_3 ; phys1_5 = 10 phys1_4 ; end units ; -- constant c_t_phys1_1 : t_phys1 := phys1_1 ; constant c_t_phys1_2 : t_phys1 := phys1_2 ; subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ; constant c_st_phys1_1 : st_phys1 := phys1_2 ; constant c_st_phys1_2 : st_phys1 := phys1_3 ; -- type phys1_vector is array (integer range <>) of st_phys1 ; subtype phys1_vector_range1 is integer range lowb to highb ; subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ; constant c_st_phys1_vector_1 : st_phys1_vector := (others => c_st_phys1_1) ; constant c_st_phys1_vector_2 : st_phys1_vector := (others => c_st_phys1_2) ; -- -- -- floating point types -- predefined constant c_real_1 : real := 0.0 ; constant c_real_2 : real := 1.0 ; -- type real_vector is array (integer range <>) of real ; subtype real_vector_range1 is integer range lowb to highb ; subtype st_real_vector is real_vector (real_vector_range1) ; constant c_st_real_vector_1 : st_real_vector := (others => c_real_1) ; constant c_st_real_vector_2 : st_real_vector := (others => c_real_2) ; -- -- user defined floating type type t_real1 is range 0.0 to 1000.0 ; constant c_t_real1_1 : t_real1 := 0.0 ; constant c_t_real1_2 : t_real1 := 1.0 ; subtype st_real1 is t_real1 range 8.0 to 80.0 ; constant c_st_real1_1 : st_real1 := 8.0 ; constant c_st_real1_2 : st_real1 := 9.0 ; -- type real1_vector is array (integer range <>) of st_real1 ; subtype real1_vector_range1 is integer range lowb to highb ; subtype st_real1_vector is real1_vector (real1_vector_range1) ; constant c_st_real1_vector_1 : st_real1_vector := (others => c_st_real1_1) ; constant c_st_real1_vector_2 : st_real1_vector := (others => c_st_real1_2) ; -- composite types -- -- simple record type t_rec1 is record f1 : integer range lowb_i2 to highb_i2 ; f2 : time ; f3 : boolean ; f4 : real ; end record ; constant c_t_rec1_1 : t_rec1 := (c_integer_1, c_time_1, c_boolean_1, c_real_1) ; constant c_t_rec1_2 : t_rec1 := (c_integer_2, c_time_2, c_boolean_2, c_real_2) ; subtype st_rec1 is t_rec1 ; constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ; constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ; -- type rec1_vector is array (integer range <>) of st_rec1 ; subtype rec1_vector_range1 is integer range lowb to highb ; subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ; constant c_st_rec1_vector_1 : st_rec1_vector := (others => c_st_rec1_1) ; constant c_st_rec1_vector_2 : st_rec1_vector := (others => c_st_rec1_2) ; -- -- -- more complex record type t_rec2 is record f1 : boolean ; f2 : st_rec1 ; f3 : time ; end record ; constant c_t_rec2_1 : t_rec2 := (c_boolean_1, c_st_rec1_1, c_time_1) ; constant c_t_rec2_2 : t_rec2 := (c_boolean_2, c_st_rec1_2, c_time_2) ; subtype st_rec2 is t_rec2 ; constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ; constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ; -- type rec2_vector is array (integer range <>) of st_rec2 ; subtype rec2_vector_range1 is integer range lowb to highb ; subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ; constant c_st_rec2_vector_1 : st_rec2_vector := (others => c_st_rec2_1) ; constant c_st_rec2_vector_2 : st_rec2_vector := (others => c_st_rec2_2) ; -- -- simple array type t_arr1 is array (integer range <>) of st_int1 ; subtype t_arr1_range1 is integer range lowb to highb ; subtype st_arr1 is t_arr1 (t_arr1_range1) ; constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ; constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ; constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ; constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ; -- type arr1_vector is array (integer range <>) of st_arr1 ; subtype arr1_vector_range1 is integer range lowb to highb ; subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ; constant c_st_arr1_vector_1 : st_arr1_vector := (others => c_st_arr1_1) ; constant c_st_arr1_vector_2 : st_arr1_vector := (others => c_st_arr1_2) ; -- more complex array type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ; subtype t_arr2_range1 is integer range lowb to highb ; subtype t_arr2_range2 is boolean range false to true ; subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2); constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ; constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ; constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ; constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ; -- type arr2_vector is array (integer range <>) of st_arr2 ; subtype arr2_vector_range1 is integer range lowb to highb ; subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ; constant c_st_arr2_vector_1 : st_arr2_vector := (others => c_st_arr2_1) ; constant c_st_arr2_vector_2 : st_arr2_vector := (others => c_st_arr2_2) ; -- -- -- most complex record type t_rec3 is record f1 : boolean ; f2 : st_rec2 ; f3 : st_arr2 ; end record ; constant c_t_rec3_1 : t_rec3 := (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ; constant c_t_rec3_2 : t_rec3 := (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ; subtype st_rec3 is t_rec3 ; constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ; constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ; -- type rec3_vector is array (integer range <>) of st_rec3 ; subtype rec3_vector_range1 is integer range lowb to highb ; subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ; constant c_st_rec3_vector_1 : st_rec3_vector := (others => c_st_rec3_1) ; constant c_st_rec3_vector_2 : st_rec3_vector := (others => c_st_rec3_2) ; -- -- most complex array type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ; subtype t_arr3_range1 is integer range lowb to highb ; subtype t_arr3_range2 is boolean range true downto false ; subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ; constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ; constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ; constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ; constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ; -- type arr3_vector is array (integer range <>) of st_arr3 ; subtype arr3_vector_range1 is integer range lowb to highb ; subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ; constant c_st_arr3_vector_1 : st_arr3_vector := (others => c_st_arr3_1) ; constant c_st_arr3_vector_2 : st_arr3_vector := (others => c_st_arr3_2) ; -- constant d_boolean : boolean := boolean'left ; constant d_bit : bit := bit'left ; constant d_severity_level : severity_level := severity_level'left ; constant d_character : character := character'left ; constant d_t_enum1 : t_enum1 := t_enum1'left ; constant d_st_enum1 : st_enum1 := st_enum1'left ; constant d_integer : integer := integer'left ; constant d_t_int1 : t_int1 := t_int1'left ; constant d_st_int1 : st_int1 := st_int1'left ; constant d_time : time := time'left ; constant d_t_phys1 : t_phys1 := t_phys1'left ; constant d_st_phys1 : st_phys1 := st_phys1'left ; constant d_real : real := real'left ; constant d_t_real1 : t_real1 := t_real1'left ; constant d_st_real1 : st_real1 := st_real1'left ; constant d_st_bit_vector : st_bit_vector := (others => bit'left) ; constant d_st_string : st_string := (others => character'left) ; constant d_t_rec1 : t_rec1 := (lowb_i2, time'left, boolean'left, real'left) ; constant d_st_rec1 : st_rec1 := (lowb_i2, time'left, boolean'left, real'left) ; constant d_t_rec2 : t_rec2 := (boolean'left, d_st_rec1, time'left) ; constant d_st_rec2 : st_rec2 := (boolean'left, d_st_rec1, time'left) ; constant d_st_arr1 : st_arr1 := (others => st_int1'left) ; constant d_st_arr2 : st_arr2 := (others => (others => d_st_arr1) ) ; constant d_t_rec3 : t_rec3 := (boolean'left, d_st_rec2, d_st_arr2) ; constant d_st_rec3 : st_rec3 := (boolean'left, d_st_rec2, d_st_arr2) ; constant d_st_arr3 : st_arr3 := (others => (others => d_st_rec3) ) ; -- enumeration types -- predefined -- boolean function bf_boolean(to_resolve : boolean_vector) return boolean is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return boolean'left ; else for i in to_resolve'range loop sum := sum + boolean'pos(to_resolve(i)) ; end loop ; return boolean'val(integer'pos(sum) mod (boolean'pos(boolean'high) + 1)) ; end if ; end bf_boolean ; -- -- -- bit function bf_bit(to_resolve : bit_vector) return bit is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return bit'left ; else for i in to_resolve'range loop sum := sum + bit'pos(to_resolve(i)) ; end loop ; return bit'val(integer'pos(sum) mod (bit'pos(bit'high) + 1)) ; end if ; end bf_bit ; -- -- severity_level function bf_severity_level(to_resolve : severity_level_vector) return severity_level is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return severity_level'left ; else for i in to_resolve'range loop sum := sum + severity_level'pos(to_resolve(i)) ; end loop ; return severity_level'val(integer'pos(sum) mod (severity_level'pos(severity_level'high) + 1)) ; end if ; end bf_severity_level ; -- -- character function bf_character(to_resolve : string) return character is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return character'left ; else for i in to_resolve'range loop sum := sum + character'pos(to_resolve(i)) ; end loop ; return character'val(integer'pos(sum) mod (character'pos(character'high) + 1)) ; end if ; end bf_character ; -- -- -- user defined enumeration function bf_enum1(to_resolve : enum1_vector) return st_enum1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return st_enum1'left ; else for i in to_resolve'range loop sum := sum + t_enum1'pos(to_resolve(i)) ; end loop ; return t_enum1'val(integer'pos(sum) mod (t_enum1'pos(t_enum1'high) + 1)) ; end if ; end bf_enum1 ; -- -- -- integer types -- predefined function bf_integer(to_resolve : integer_vector) return integer is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return integer'left ; else for i in to_resolve'range loop sum := sum + integer'pos(to_resolve(i)) ; end loop ; return sum ; end if ; end bf_integer ; -- -- -- user defined integer type function bf_int1(to_resolve : int1_vector) return st_int1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return st_int1'left ; else for i in to_resolve'range loop sum := sum + t_int1'pos(to_resolve(i)) ; end loop ; return t_int1'val(integer'pos(sum) mod (t_int1'pos(t_int1'high) + 1)) ; end if ; end bf_int1 ; -- -- -- physical types -- predefined function bf_time(to_resolve : time_vector) return time is variable sum : time := 0 fs; begin if to_resolve'length = 0 then return time'left ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_time ; -- -- -- user defined physical type function bf_phys1(to_resolve : phys1_vector) return st_phys1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return c_st_phys1_1 ; else for i in to_resolve'range loop sum := sum + t_phys1'pos(to_resolve(i)) ; end loop ; return t_phys1'val(integer'pos(sum) mod (t_phys1'pos(t_phys1'high) + 1)) ; end if ; end bf_phys1 ; -- -- -- floating point types -- predefined function bf_real(to_resolve : real_vector) return real is variable sum : real := 0.0 ; begin if to_resolve'length = 0 then return real'left ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_real ; -- -- -- user defined floating type function bf_real1(to_resolve : real1_vector) return st_real1 is variable sum : t_real1 := 0.0 ; begin if to_resolve'length = 0 then return c_st_real1_1 ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_real1 ; -- -- -- composite types -- -- simple record function bf_rec1(to_resolve : rec1_vector) return st_rec1 is variable f1array : integer_vector (to_resolve'range) ; variable f2array : time_vector (to_resolve'range) ; variable f3array : boolean_vector (to_resolve'range) ; variable f4array : real_vector (to_resolve'range) ; variable result : st_rec1 ; begin if to_resolve'length = 0 then return c_st_rec1_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; f4array(i) := to_resolve(i).f4 ; end loop ; result.f1 := bf_integer(f1array) ; result.f2 := bf_time(f2array) ; result.f3 := bf_boolean(f3array) ; result.f4 := bf_real(f4array) ; return result ; end if ; end bf_rec1 ; -- -- -- more complex record function bf_rec2(to_resolve : rec2_vector) return st_rec2 is variable f1array : boolean_vector (to_resolve'range) ; variable f2array : rec1_vector (to_resolve'range) ; variable f3array : time_vector (to_resolve'range) ; variable result : st_rec2 ; begin if to_resolve'length = 0 then return c_st_rec2_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; end loop ; result.f1 := bf_boolean(f1array) ; result.f2 := bf_rec1(f2array) ; result.f3 := bf_time(f3array) ; return result ; end if ; end bf_rec2 ; -- -- -- simple array function bf_arr1(to_resolve : arr1_vector) return st_arr1 is variable temp : int1_vector (to_resolve'range) ; variable result : st_arr1 ; begin if to_resolve'length = 0 then return c_st_arr1_1 ; else for i in st_arr1'range loop for j in to_resolve'range(1) loop temp(j) := to_resolve(j)(i) ; end loop; result(i) := bf_int1(temp) ; end loop ; return result ; end if ; end bf_arr1 ; -- -- -- more complex array function bf_arr2(to_resolve : arr2_vector) return st_arr2 is variable temp : arr1_vector (to_resolve'range) ; variable result : st_arr2 ; begin if to_resolve'length = 0 then return c_st_arr2_1 ; else for i in st_arr2'range(1) loop for j in st_arr2'range(2) loop for k in to_resolve'range loop temp(k) := to_resolve(k)(i,j) ; end loop ; result(i, j) := bf_arr1(temp) ; end loop ; end loop ; return result ; end if ; end bf_arr2 ; -- -- -- most complex record function bf_rec3(to_resolve : rec3_vector) return st_rec3 is variable f1array : boolean_vector (to_resolve'range) ; variable f2array : rec2_vector (to_resolve'range) ; variable f3array : arr2_vector (to_resolve'range) ; variable result : st_rec3 ; begin if to_resolve'length = 0 then return c_st_rec3_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; end loop ; result.f1 := bf_boolean(f1array) ; result.f2 := bf_rec2(f2array) ; result.f3 := bf_arr2(f3array) ; return result ; end if ; end bf_rec3 ; -- -- -- most complex array function bf_arr3(to_resolve : arr3_vector) return st_arr3 is variable temp : rec3_vector (to_resolve'range) ; variable result : st_arr3 ; begin if to_resolve'length = 0 then return c_st_arr3_1 ; else for i in st_arr3'range(1) loop for j in st_arr3'range(2) loop for k in to_resolve'range loop temp(k) := to_resolve(k)(i,j) ; end loop ; result(i, j) := bf_rec3(temp) ; end loop ; end loop ; return result ; end if ; end bf_arr3 ; -- variable correct : boolean := true ; type a_bit_vector is access bit_vector ; variable va_bit_vector_1, va_bit_vector_2 : a_bit_vector := new st_bit_vector ; type a_string is access string ; variable va_string_1, va_string_2 : a_string := new st_string ; type a_t_rec1 is access t_rec1 ; variable va_t_rec1_1, va_t_rec1_2 : a_t_rec1 := new st_rec1 ; type a_st_rec1 is access st_rec1 ; variable va_st_rec1_1, va_st_rec1_2 : a_st_rec1 := new st_rec1 ; type a_t_rec2 is access t_rec2 ; variable va_t_rec2_1, va_t_rec2_2 : a_t_rec2 := new st_rec2 ; type a_st_rec2 is access st_rec2 ; variable va_st_rec2_1, va_st_rec2_2 : a_st_rec2 := new st_rec2 ; type a_t_rec3 is access t_rec3 ; variable va_t_rec3_1, va_t_rec3_2 : a_t_rec3 := new st_rec3 ; type a_st_rec3 is access st_rec3 ; variable va_st_rec3_1, va_st_rec3_2 : a_st_rec3 := new st_rec3 ; type a_t_arr1 is access t_arr1 ; variable va_t_arr1_1, va_t_arr1_2 : a_t_arr1 := new st_arr1 ; type a_st_arr1 is access st_arr1 ; variable va_st_arr1_1, va_st_arr1_2 : a_st_arr1 := new st_arr1 ; type a_t_arr2 is access t_arr2 ; variable va_t_arr2_1, va_t_arr2_2 : a_t_arr2 := new st_arr2 ; type a_st_arr2 is access st_arr2 ; variable va_st_arr2_1, va_st_arr2_2 : a_st_arr2 := new st_arr2 ; type a_t_arr3 is access t_arr3 ; variable va_t_arr3_1, va_t_arr3_2 : a_t_arr3 := new st_arr3 ; type a_st_arr3 is access st_arr3 ; variable va_st_arr3_1, va_st_arr3_2 : a_st_arr3 := new st_arr3 ; begin correct := correct and va_bit_vector_1.all = d_st_bit_vector ; correct := correct and va_string_1.all = d_st_string ; correct := correct and va_t_rec1_1.all = d_st_rec1 ; correct := correct and va_st_rec1_1.all = d_st_rec1 ; correct := correct and va_t_rec2_1.all = d_st_rec2 ; correct := correct and va_st_rec2_1.all = d_st_rec2 ; correct := correct and va_t_rec3_1.all = d_st_rec3 ; correct := correct and va_st_rec3_1.all = d_st_rec3 ; correct := correct and va_t_arr1_1.all = d_st_arr1 ; correct := correct and va_st_arr1_1.all = d_st_arr1 ; correct := correct and va_t_arr2_1.all = d_st_arr2 ; correct := correct and va_st_arr2_1.all = d_st_arr2 ; correct := correct and va_t_arr3_1.all = d_st_arr3 ; correct := correct and va_st_arr3_1.all = d_st_arr3 ; test_report ( "ARCH00687" , "Allocators with dynamic composite subtype indication" , correct) ; end p1 ; begin process begin p1 ; wait ; end process ; end ARCH00687 ; -- entity ENT00687_Test_Bench is end ENT00687_Test_Bench ; -- architecture ARCH00687_Test_Bench of ENT00687_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00687 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00687_Test_Bench ;
library ieee; use ieee.std_logic_1164.all; entity clockgen is port ( ext_clk, async_resetb : in std_ulogic; clk, sync_reset : out std_ulogic ); end clockgen;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2580.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c13s03b01x00p02n01i02580ent IS END c13s03b01x00p02n01i02580ent; ARCHITECTURE c13s03b01x00p02n01i02580arch OF c13s03b01x00p02n01i02580ent IS BEGIN TESTING: PROCESS variable "k : integer; BEGIN assert FALSE report "***FAILED TEST: c13s03b01x00p02n01i02580 - Identifier can only begin with a letter." severity ERROR; wait; END PROCESS TESTING; END c13s03b01x00p02n01i02580arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2580.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c13s03b01x00p02n01i02580ent IS END c13s03b01x00p02n01i02580ent; ARCHITECTURE c13s03b01x00p02n01i02580arch OF c13s03b01x00p02n01i02580ent IS BEGIN TESTING: PROCESS variable "k : integer; BEGIN assert FALSE report "***FAILED TEST: c13s03b01x00p02n01i02580 - Identifier can only begin with a letter." severity ERROR; wait; END PROCESS TESTING; END c13s03b01x00p02n01i02580arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2580.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c13s03b01x00p02n01i02580ent IS END c13s03b01x00p02n01i02580ent; ARCHITECTURE c13s03b01x00p02n01i02580arch OF c13s03b01x00p02n01i02580ent IS BEGIN TESTING: PROCESS variable "k : integer; BEGIN assert FALSE report "***FAILED TEST: c13s03b01x00p02n01i02580 - Identifier can only begin with a letter." severity ERROR; wait; END PROCESS TESTING; END c13s03b01x00p02n01i02580arch;
------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- axi_vdma_afifo_builtin.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010, 2012-2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- LIBRARY ieee; USE ieee.std_logic_1164.ALL; library fifo_generator_v12_0; use fifo_generator_v12_0.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.all; --use proc_common_v4_0.coregen_comp_defs.all; --use proc_common_v4_0.family_support.all; library axi_vdma_v6_2; use axi_vdma_v6_2.axi_vdma_pkg.all; -- synopsys translate_off --library XilinxCoreLib; --use XilinxCoreLib.all; -- synopsys translate_on ENTITY axi_vdma_afifo_builtin IS GENERIC ( ------------------------------------------------------------------------- -- Generic Declarations ------------------------------------------------------------------------- PL_FIFO_TYPE : STRING := "BLOCK_RAM"; -- BLOCK_RAM, LUTRAM, BUILT_IN; Default: BLOCK_RAM PL_READ_MODE : STRING := "STANDARD"; -- STANDARD, FWFT; Default: STANDARD PL_FASTER_CLOCK : STRING := "WR_CLK"; -- WR_CLK, RD_CLK; Default: WR_CLK PL_FULL_FLAGS_RST_VAL : INTEGER := 1; -- 1, 0; Default: 1 PL_DATA_WIDTH : INTEGER := 16; -- 1 - 1024; Default 16 C_FAMILY : string := "virtex7"; PL_FIFO_DEPTH : INTEGER := 1024 -- 16 - 256K; Default 1K ); PORT ( -- Common signal rst : in std_logic := '0'; sleep : in std_logic := '0'; wr_rst_busy : out std_logic := '0'; rd_rst_busy : out std_logic := '0'; -- Write Domain signals wr_clk : in std_logic := '0'; din : in std_logic_vector(PL_DATA_WIDTH-1 downto 0) := (others => '0'); wr_en : in std_logic := '0'; full : out std_logic := '0'; -- Write Domain signals rd_clk : in std_logic := '0'; rd_en : in std_logic := '0'; dout : out std_logic_vector(PL_DATA_WIDTH-1 downto 0) := (others => '0'); empty : out std_logic := '1' ); END ENTITY axi_vdma_afifo_builtin; ARCHITECTURE xilinx OF axi_vdma_afifo_builtin IS attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of xilinx : architecture is "yes"; --------------------------------------------------------------------------- -- FUNCTION : log2roundup --------------------------------------------------------------------------- FUNCTION log2roundup ( data_value : integer) RETURN integer IS VARIABLE width : integer := 0; VARIABLE cnt : integer := 1; CONSTANT lower_limit : integer := 1; CONSTANT upper_limit : integer := 8; BEGIN IF (data_value <= 1) THEN width := 0; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt 2; END LOOP; END IF; RETURN width; END log2roundup; ------------------------------------------------------------------------------ -- This function is used to implement an IF..THEN when such a statement is not -- allowed. ------------------------------------------------------------------------------ FUNCTION if_then_else ( condition : boolean; true_case : integer; false_case : integer) RETURN integer IS VARIABLE retval : integer := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; ------------------------------------------------------------------------------ -- This function is used to implement an IF..THEN when such a statement is not -- allowed and returns string. ------------------------------------------------------------------------------ function if_then_else ( condition : boolean; true_case : string; false_case : string) return string is begin if not condition then return false_case; else return true_case; end if; end if_then_else; ----------------------------------------------------------------------------- -- FUNCTION: to_lower_case_char -- Returns the lower case form of char IF char is an upper case letter. -- Otherwise char is returned. ----------------------------------------------------------------------------- FUNCTION to_lower_case_char( char : character ) RETURN character IS BEGIN ------------------------------------------------------------------------- -- If char is not an upper case letter THEN return char -- -- Otherwise map char to its corresponding lower case character and -- return that ------------------------------------------------------------------------- IF char<'A' OR char>'Z' THEN RETURN char; END IF; CASE char IS WHEN 'A' => RETURN 'a'; WHEN 'B' => RETURN 'b'; WHEN 'C' => RETURN 'c'; WHEN 'D' => RETURN 'd'; WHEN 'E' => RETURN 'e'; WHEN 'F' => RETURN 'f'; WHEN 'G' => RETURN 'g'; WHEN 'H' => RETURN 'h'; WHEN 'I' => RETURN 'i'; WHEN 'J' => RETURN 'j'; WHEN 'K' => RETURN 'k'; WHEN 'L' => RETURN 'l'; WHEN 'M' => RETURN 'm'; WHEN 'N' => RETURN 'n'; WHEN 'O' => RETURN 'o'; WHEN 'P' => RETURN 'p'; WHEN 'Q' => RETURN 'q'; WHEN 'R' => RETURN 'r'; WHEN 'S' => RETURN 's'; WHEN 'T' => RETURN 't'; WHEN 'U' => RETURN 'u'; WHEN 'V' => RETURN 'v'; WHEN 'W' => RETURN 'w'; WHEN 'X' => RETURN 'x'; WHEN 'Y' => RETURN 'y'; WHEN 'Z' => RETURN 'z'; WHEN OTHERS => RETURN char; END CASE; END to_lower_case_char; ----------------------------------------------------------------------------- -- Returns true IF case insensitive string comparison determines that -- str1 and str2 are equal ----------------------------------------------------------------------------- FUNCTION equal_ignore_case( str1 : string; str2 : string ) RETURN boolean IS CONSTANT len1 : integer := str1'length; CONSTANT len2 : integer := str2'length; VARIABLE equal : boolean := TRUE; BEGIN IF NOT (len1=len2) THEN equal := FALSE; ELSE FOR i IN str2'left TO str1'right LOOP IF NOT (to_lower_case_char(str1(i)) = to_lower_case_char(str2(i))) THEN equal := FALSE; END IF; END LOOP; END IF; RETURN equal; END equal_ignore_case; --############################################################# --# --# Get the Primitive fifo type --# Description: Algorithm for Built-In FIFO implementation --# to determine which primitive is most optimal to use --# --############################################################# function get_Prim_Fifo_Type ( width : integer; depth : integer; use_ecc : integer) return string is variable prim_4kx4_used : integer := (((width-1)/4 +1)((depth-1)/4096 +1)); variable prim_2kx9_used : integer := (((width-1)/9 +1)((depth-1)/2048 +1)); variable prim_1kx18_used : integer := (((width-1)/18+1)((depth-1)/1024 +1)); variable prim_512x36_used : integer := (((width-1)/36+1)((depth-1)/512 +1)); variable prim_8kx4_used : integer := (((width-1)/4 +1)((depth-1)/8192 +1)); variable prim_4kx9_used : integer := (((width-1)/9 +1)((depth-1)/4096 +1)); variable prim_2kx18_used : integer := (((width-1)/18+1)((depth-1)/2048 +1)); variable prim_1kx36_used : integer := (((width-1)/36+1)((depth-1)/1024 +1)); variable prim_512x72_used : integer := (((width-1)/72+1)((depth-1)/512 +1)); variable min_used : integer := prim_4kx4_used; variable min_type : string (1 to 6) := "4kx4 "; begin if (use_ecc = 0) then --########################################################## --# Rules: Primitive used should --# - generate correct full flags if depth >= 512 --# - use min number of primitives --# - use primitive that reduces latency when possible --# This creates 3 cases: --# 1) depth <= 512 --# 2) depth = 1k --# 3) depth = 2k --# 4) depth >= 4k --########################################################## if (depth <= 512) then if (min_used > prim_512x72_used) then min_used := prim_512x72_used; min_type := "512x72"; else min_used := prim_512x36_used; min_type := "512x36"; end if; elsif (depth = 1024) then min_used := prim_1kx18_used; min_type := "1kx18 "; if (min_used > prim_512x36_used) then min_used := prim_512x36_used; min_type := "512x36"; end if; if (min_used > prim_1kx36_used) then min_used := prim_1kx36_used; min_type := "1kx36 "; end if; if (min_used > prim_512x72_used) then min_used := prim_512x72_used; min_type := "512x72"; end if; elsif (depth = 2048) then min_used := prim_2kx9_used; min_type := "2kx9 "; if (min_used > prim_1kx18_used) then min_used := prim_1kx18_used; min_type := "1kx18 "; end if; if (min_used > prim_512x36_used) then min_used := prim_512x36_used; min_type := "512x36"; end if; if (min_used > prim_2kx18_used) then min_used := prim_2kx18_used; min_type := "2kx18 "; end if; if (min_used > prim_1kx36_used) then min_used := prim_1kx36_used; min_type := "1kx36 "; end if; if (min_used > prim_512x72_used) then min_used := prim_512x72_used; min_type := "512x72"; end if; else min_used := prim_4kx4_used; min_type := "4kx4 "; if (min_used > prim_2kx9_used) then min_used := prim_2kx9_used; min_type := "2kx9 "; end if; if (min_used > prim_1kx18_used) then min_used := prim_1kx18_used; min_type := "1kx18 "; end if; if (min_used > prim_512x36_used) then min_used := prim_512x36_used; min_type := "512x36"; end if; if (min_used > prim_8kx4_used) then min_used := prim_8kx4_used; min_type := "8kx4 "; end if; if (min_used > prim_4kx9_used) then min_used := prim_4kx9_used; min_type := "4kx9 "; end if; if (min_used > prim_2kx18_used) then min_used := prim_2kx18_used; min_type := "2kx18 "; end if; if (min_used > prim_1kx36_used) then min_used := prim_1kx36_used; min_type := "1kx36 "; end if; if (min_used > prim_512x72_used) then min_used := prim_512x72_used; min_type := "512x72"; end if; end if; else -- if ecc is used, always use the 512x72 primitive min_used := prim_512x72_used; min_type := "512x72"; end if; return min_type; end get_Prim_Fifo_Type; --CONSTANT GND : std_logic := '0'; CONSTANT VCC : std_logic := '1'; CONSTANT ZERO1 : std_logic_vector(0 downto 0) := (others => '0'); CONSTANT ZERO2 : std_logic_vector(1 downto 0) := (others => '0'); CONSTANT ZERO3 : std_logic_vector(2 downto 0) := (others => '0'); CONSTANT ZERO4 : std_logic_vector(3 downto 0) := (others => '0'); CONSTANT ZERO8 : std_logic_vector(7 downto 0) := (others => '0'); CONSTANT ZERO16 : std_logic_vector(15 downto 0) := (others => '0'); CONSTANT ZERO32 : std_logic_vector(31 downto 0) := (others => '0'); CONSTANT ZERO64 : std_logic_vector(63 downto 0) := (others => '0'); --CONSTANT ZERO_pntr : std_logic_vector(log2roundup(pl_fifo_depth)-1 downto 0) := (others => '0'); CONSTANT C_PRELOAD_LATENCY : integer := if_then_else((PL_READ_MODE = "FWFT"), 0, 1); CONSTANT C_PRELOAD_REGS : integer := if_then_else((PL_READ_MODE = "FWFT"), 1, 0); CONSTANT C_WR_FREQ : integer := if_then_else((PL_FASTER_CLOCK = "WR_CLK"), 10, 1); CONSTANT C_RD_FREQ : integer := if_then_else((PL_FASTER_CLOCK = "RD_CLK"), 10, 1); CONSTANT C_MEMORY_TYPE : integer := if_then_else((PL_FIFO_TYPE = "BLOCK_RAM"), 1, if_then_else((PL_FIFO_TYPE = "LUTRAM"), 2, if_then_else((PL_FIFO_TYPE = "BUILT_IN"), 4, 0))); CONSTANT C_IMPLEMENTATION_TYPE : integer := if_then_else((PL_FIFO_TYPE = "BLOCK_RAM"), 0, if_then_else((PL_FIFO_TYPE = "LUTRAM"), 0, if_then_else((PL_FIFO_TYPE = "BUILT_IN"), 6, 8))); CONSTANT PRIM_FIFO_TYPE : string := get_Prim_Fifo_Type(pl_data_width,pl_fifo_depth,0); CONSTANT C_PRIM_FIFO_TYPE : string := if_then_else(PRIM_FIFO_TYPE = "8kx4 ", "8kx4", if_then_else(PRIM_FIFO_TYPE = "4kx9 ", "4kx9", if_then_else(PRIM_FIFO_TYPE = "4kx4 ", "4kx4", if_then_else(PRIM_FIFO_TYPE = "2kx18 ", "2kx18", if_then_else(PRIM_FIFO_TYPE = "2kx9 ", "2kx9", if_then_else(PRIM_FIFO_TYPE = "1kx36 ", "1kx36", if_then_else(PRIM_FIFO_TYPE = "1kx18 ", "1kx18", if_then_else(PRIM_FIFO_TYPE = "512x72", "512x72", if_then_else(PRIM_FIFO_TYPE = "512x36", "512x36",""))))))))); CONSTANT IS_FIFO_TYPE_VLD : integer := if_then_else((PL_FIFO_TYPE = "BLOCK_RAM") or (PL_FIFO_TYPE = "LUTRAM") or (PL_FIFO_TYPE = "BUILT_IN"), 1, 0); CONSTANT IS_READ_MODE_VLD : integer := if_then_else((PL_READ_MODE = "STANDARD") or (PL_READ_MODE = "FWFT"), 1, 0); CONSTANT IS_DATA_WIDTH_VLD : integer := if_then_else(PL_DATA_WIDTH > 0 and PL_DATA_WIDTH <= 1024, 1, 0); CONSTANT IS_FIFO_DEPTH_VLD : integer := if_then_else((PL_FIFO_DEPTH = 16 or PL_FIFO_DEPTH = 32 or PL_FIFO_DEPTH = 64 or PL_FIFO_DEPTH = 128 or PL_FIFO_DEPTH = 256 or PL_FIFO_DEPTH = 512 or PL_FIFO_DEPTH = 1024 or PL_FIFO_DEPTH = 2048 or PL_FIFO_DEPTH = 4096 or PL_FIFO_DEPTH = 8192 or PL_FIFO_DEPTH = 16384 or PL_FIFO_DEPTH = 32768 or PL_FIFO_DEPTH = 65536 or PL_FIFO_DEPTH = 131072 or PL_FIFO_DEPTH = 262144),1,0); CONSTANT VLD_BI_DEPTH : integer := if_then_else((PL_FIFO_DEPTH = 512 or PL_FIFO_DEPTH = 1024 or PL_FIFO_DEPTH = 2048 or PL_FIFO_DEPTH = 4096 or PL_FIFO_DEPTH = 8192 or PL_FIFO_DEPTH = 16384 or PL_FIFO_DEPTH = 32768 or PL_FIFO_DEPTH = 65536 or PL_FIFO_DEPTH = 131072 or PL_FIFO_DEPTH = 262144),1,0); -- CONSTANT IS_BI_DEPTH_VLD : integer := if_then_else((VLD_BI_DEPTH = 1 and PL_FIFO_TYPE = "BUILT_IN"), 1, 0); CONSTANT IS_BI_DEPTH_VLD : integer := if_then_else((VLD_BI_DEPTH = 1), 1, 0); CONSTANT log2roundup_pl_fifo_depth : integer := log2roundup(pl_fifo_depth); CONSTANT PROG_FULL_THRESH_ASSERT_VAL_1 : integer := if_then_else((PL_FIFO_TYPE = "BUILT_IN"), PL_FIFO_DEPTH-150, 14); CONSTANT PROG_FULL_THRESH_NEGATE_VAL_1 : integer := if_then_else((PL_FIFO_TYPE = "BUILT_IN"), PL_FIFO_DEPTH-160, 12); CONSTANT SYNC_RST_PORT : integer := if_then_else(((C_FAMILY = "kintexu") or (C_FAMILY = "virtexu") or (C_FAMILY = "artixu")), 1, 0); -- ultra-scale CONSTANT ASYNC_RST_PORT : integer := if_then_else(((C_FAMILY /= "kintexu") and (C_FAMILY /= "virtexu") and (C_FAMILY /= "artixu")), 1, 0); -- 7-series (not ultrascale) --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal ZERO_pntr : std_logic_vector(log2roundup_pl_fifo_depth-1 downto 0) := (others => '0'); signal GND : std_logic := '0'; signal ALMOST_FULL : std_logic; signal WR_ACK : std_logic; signal OVERFLOW : std_logic; signal ALMOST_EMPTY : std_logic; signal VALID : std_logic; signal UNDERFLOW : std_logic; signal PROG_FULL : std_logic; signal PROG_EMPTY : std_logic; signal SBITERR : std_logic; signal DBITERR : std_logic; signal S_AXI_AWREADY : std_logic; signal S_AXI_WREADY : std_logic; signal S_AXI_BID : std_logic_vector(3 DOWNTO 0); signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_BUSER : std_logic_vector(0 downto 0); signal S_AXI_BVALID : std_logic; -- AXI Full/Lite Master Write Channel (Read side) signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0); signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWUSER : std_logic_vector(0 downto 0); signal M_AXI_AWVALID : std_logic; signal M_AXI_WID : std_logic_vector(3 DOWNTO 0); signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0); signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0); signal M_AXI_WLAST : std_logic; signal M_AXI_WUSER : std_logic_vector(0 downto 0); signal M_AXI_WVALID : std_logic; signal M_AXI_BREADY : std_logic; -- AXI Full/Lite Slave Read Channel (Write side) signal S_AXI_ARREADY : std_logic; signal S_AXI_RID : std_logic_vector(3 DOWNTO 0); signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0); signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_RLAST : std_logic; signal S_AXI_RUSER : std_logic_vector(0 downto 0); signal S_AXI_RVALID : std_logic; -- AXI Full/Lite Master Read Channel (Read side) signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0); signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARUSER : std_logic_vector(0 downto 0); signal M_AXI_ARVALID : std_logic; signal M_AXI_RREADY : std_logic; -- AXI Streaming Slave Signals (Write side) signal S_AXIS_TREADY : std_logic; -- AXI Streaming Master Signals (Read side) signal M_AXIS_TVALID : std_logic; signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0); signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TLAST : std_logic; signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0); signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_SBITERR : std_logic; signal AXI_AW_DBITERR : std_logic; signal AXI_AW_OVERFLOW : std_logic; signal AXI_AW_UNDERFLOW : std_logic; signal AXI_AW_PROG_FULL : STD_LOGIC; signal AXI_AW_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Data Channel Signals signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_SBITERR : std_logic; signal AXI_W_DBITERR : std_logic; signal AXI_W_OVERFLOW : std_logic; signal AXI_W_UNDERFLOW : std_logic; signal AXI_W_PROG_FULL : STD_LOGIC; signal AXI_W_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Response Channel Signals signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_SBITERR : std_logic; signal AXI_B_DBITERR : std_logic; signal AXI_B_OVERFLOW : std_logic; signal AXI_B_UNDERFLOW : std_logic; signal AXI_B_PROG_FULL : STD_LOGIC; signal AXI_B_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Address Channel Signals signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_SBITERR : std_logic; signal AXI_AR_DBITERR : std_logic; signal AXI_AR_OVERFLOW : std_logic; signal AXI_AR_UNDERFLOW : std_logic; signal AXI_AR_PROG_FULL : STD_LOGIC; signal AXI_AR_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Data Channel Signals signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_SBITERR : std_logic; signal AXI_R_DBITERR : std_logic; signal AXI_R_OVERFLOW : std_logic; signal AXI_R_UNDERFLOW : std_logic; signal AXI_R_PROG_FULL : STD_LOGIC; signal AXI_R_PROG_EMPTY : STD_LOGIC; -- AXI Streaming FIFO Related Signals signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_SBITERR : std_logic; signal AXIS_DBITERR : std_logic; signal AXIS_OVERFLOW : std_logic; signal AXIS_UNDERFLOW : std_logic; signal AXIS_PROG_FULL : STD_LOGIC; signal AXIS_PROG_EMPTY : STD_LOGIC; --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal DATA_COUNT : std_logic_vector(log2roundup_pl_fifo_depth-1 DOWNTO 0); signal RD_DATA_COUNT : std_logic_vector(log2roundup_pl_fifo_depth-1 DOWNTO 0); signal WR_DATA_COUNT : std_logic_vector(log2roundup_pl_fifo_depth-1 DOWNTO 0); signal wr_rst_busy_sig : std_logic := '0'; signal rd_rst_busy_sig : std_logic := '0'; signal rst_i : std_logic := '0'; signal srst_i : std_logic := '0'; BEGIN FAMILY_8 : if ((C_FAMILY = "kintexu") or (C_FAMILY = "virtexu") or (C_FAMILY = "artixu")) generate begin wr_rst_busy <= wr_rst_busy_sig; rd_rst_busy <= rd_rst_busy_sig; srst_i <= rst; rst_i <= '0'; end generate FAMILY_8; FAMILY_NOT_8 : if ((C_FAMILY /= "kintexu") and (C_FAMILY /= "virtexu") and (C_FAMILY /= "artixu")) generate begin wr_rst_busy <= '0'; rd_rst_busy <= '0'; srst_i <= '0'; rst_i <= rst; end generate FAMILY_NOT_8; ZERO_pntr <= (others => '0'); GND <= '0'; fg_builtin_fifo_inst : entity fifo_generator_v12_0.fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 0, -- C_COUNT_TYPE => C_COUNT_TYPE, C_DATA_COUNT_WIDTH => log2roundup_pl_fifo_depth, -- C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_DIN_WIDTH => pl_data_width, -- C_DOUT_RST_VAL => C_DOUT_RST_VAL, C_DOUT_WIDTH => pl_data_width, -- C_ENABLE_RLOCS => C_ENABLE_RLOCS, --C_FAMILY => "virtex7", C_FAMILY => C_FAMILY, C_FULL_FLAGS_RST_VAL => pl_full_flags_rst_val, -- C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY, -- C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL, -- C_HAS_BACKUP => C_HAS_BACKUP, -- C_HAS_DATA_COUNT => C_HAS_DATA_COUNT, -- C_HAS_INT_CLK => C_HAS_INT_CLK, -- C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, -- C_HAS_OVERFLOW => C_HAS_OVERFLOW, -- C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT, -- C_HAS_RD_RST => C_HAS_RD_RST, C_HAS_RST => ASYNC_RST_PORT, C_HAS_SRST => SYNC_RST_PORT, -- C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, -- C_HAS_VALID => C_HAS_VALID, -- C_HAS_WR_ACK => C_HAS_WR_ACK, -- C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT, -- C_HAS_WR_RST => C_HAS_WR_RST, C_IMPLEMENTATION_TYPE => C_IMPLEMENTATION_TYPE, -- C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MEMORY_TYPE => C_MEMORY_TYPE, -- C_MIF_FILE_NAME => C_MIF_FILE_NAME, -- C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, -- C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, C_PRELOAD_REGS => C_PRELOAD_REGS, C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE, C_PROG_EMPTY_THRESH_ASSERT_VAL => 10, C_PROG_EMPTY_THRESH_NEGATE_VAL => 9, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL_1, C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL_1, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => log2roundup_pl_fifo_depth, C_RD_DEPTH => pl_fifo_depth, C_RD_FREQ => C_RD_FREQ, C_RD_PNTR_WIDTH => log2roundup_pl_fifo_depth, -- C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, -- C_USE_DOUT_RST => C_USE_DOUT_RST, -- C_USE_ECC => C_USE_ECC, -- C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, -- C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, -- C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT, -- C_VALID_LOW => C_VALID_LOW, -- C_WR_ACK_LOW => C_WR_ACK_LOW, C_WR_DATA_COUNT_WIDTH => log2roundup_pl_fifo_depth, C_WR_DEPTH => pl_fifo_depth, C_WR_FREQ => C_WR_FREQ, C_WR_PNTR_WIDTH => log2roundup_pl_fifo_depth, -- C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY, -- C_MSGON_VAL => C_MSGON_VAL, -- C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC, -- C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE, C_SYNCHRONIZER_STAGE => MTBF_STAGES, -- AXI Interface related parameters start here C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0; C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0; C_HAS_SLAVE_CE => 0, -- : integer := 0; C_HAS_MASTER_CE => 0, -- : integer := 0; C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0; C_USE_COMMON_OVERFLOW => 0, -- : integer := 0; C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0; C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH => 4 , -- : integer := 0; C_AXI_ADDR_WIDTH => 32, -- : integer := 0; C_AXI_DATA_WIDTH => 64, -- : integer := 0; C_AXI_LEN_WIDTH => 8, -- : integer := 8; C_AXI_LOCK_WIDTH => 2, -- : integer := 2; C_HAS_AXI_ID => 0, -- : integer := 0; C_HAS_AXI_AWUSER => 0 , -- : integer := 0; C_HAS_AXI_WUSER => 0 , -- : integer := 0; C_HAS_AXI_BUSER => 0 , -- : integer := 0; C_HAS_AXI_ARUSER => 0 , -- : integer := 0; C_HAS_AXI_RUSER => 0 , -- : integer := 0; C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0; C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0; C_AXI_WUSER_WIDTH => 1 , -- : integer := 0; C_AXI_BUSER_WIDTH => 1 , -- : integer := 0; C_AXI_RUSER_WIDTH => 1 , -- : integer := 0; -- AXI Streaming C_HAS_AXIS_TDATA => 0 , -- : integer := 0; C_HAS_AXIS_TID => 0 , -- : integer := 0; C_HAS_AXIS_TDEST => 0 , -- : integer := 0; C_HAS_AXIS_TUSER => 0 , -- : integer := 0; C_HAS_AXIS_TREADY => 1 , -- : integer := 0; C_HAS_AXIS_TLAST => 0 , -- : integer := 0; C_HAS_AXIS_TSTRB => 0 , -- : integer := 0; C_HAS_AXIS_TKEEP => 0 , -- : integer := 0; C_AXIS_TDATA_WIDTH => 64, -- : integer := 1; C_AXIS_TID_WIDTH => 8 , -- : integer := 1; C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1; C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1; C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1; C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Data FIFO C_APPLICATION_TYPE_WACH => 0, -- : integer := 0; C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0; C_APPLICATION_TYPE_RACH => 0, -- : integer := 0; C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH => 0, -- : integer := 0; C_USE_ECC_WDCH => 0, -- : integer := 0; C_USE_ECC_WRCH => 0, -- : integer := 0; C_USE_ECC_RACH => 0, -- : integer := 0; C_USE_ECC_RDCH => 0, -- : integer := 0; C_USE_ECC_AXIS => 0, -- : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH => 32, -- : integer := 1; C_DIN_WIDTH_WDCH => 64, -- : integer := 1; C_DIN_WIDTH_WRCH => 2 , -- : integer := 1; C_DIN_WIDTH_RACH => 32, -- : integer := 1; C_DIN_WIDTH_RDCH => 64, -- : integer := 1; C_DIN_WIDTH_AXIS => 1 , -- : integer := 1; C_WR_DEPTH_WACH => 16 , -- : integer := 16; C_WR_DEPTH_WDCH => 1024, -- : integer := 16; C_WR_DEPTH_WRCH => 16 , -- : integer := 16; C_WR_DEPTH_RACH => 16 , -- : integer := 16; C_WR_DEPTH_RDCH => 1024, -- : integer := 16; C_WR_DEPTH_AXIS => 1024, -- : integer := 16; C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4; C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0; C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0; C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0; C_REG_SLICE_MODE_WACH => 0, -- : integer := 0; C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0; C_REG_SLICE_MODE_RACH => 0, -- : integer := 0; C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0 ) PORT MAP ( backup => GND, backup_marker => GND, clk => GND, rst => rst_i, srst => srst_i, wr_clk => wr_clk, wr_rst => GND, rd_clk => rd_clk, rd_rst => GND, din => din, wr_en => wr_en, rd_en => rd_en, sleep => sleep, wr_rst_busy => wr_rst_busy_sig, rd_rst_busy => rd_rst_busy_sig, prog_empty_thresh => ZERO_pntr, prog_empty_thresh_assert => ZERO_pntr, prog_empty_thresh_negate => ZERO_pntr, prog_full_thresh => ZERO_pntr, prog_full_thresh_assert => ZERO_pntr, prog_full_thresh_negate => ZERO_pntr, int_clk => GND, injectdbiterr => GND, injectsbiterr => GND, dout => dout, full => full, empty => empty, almost_full => ALMOST_FULL, wr_ack => WR_ACK, overflow => OVERFLOW, almost_empty => ALMOST_EMPTY, valid => VALID, underflow => UNDERFLOW, data_count => DATA_COUNT, rd_data_count => RD_DATA_COUNT, wr_data_count => WR_DATA_COUNT, prog_full => PROG_FULL, prog_empty => PROG_EMPTY, sbiterr => SBITERR, dbiterr => DBITERR, m_aclk => '0', -- : IN std_logic := '0'; s_aclk => '0', -- : IN std_logic := '0'; s_aresetn => '0', -- : IN std_logic := '0'; m_aclk_en => '0', -- : IN std_logic := '0'; s_aclk_en => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Slave Write Channel (write side) s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awvalid => '0', -- : IN std_logic := '0'; s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic; s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wlast => '0', -- : IN std_logic := '0'; s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wvalid => '0', -- : IN std_logic := '0'; s_axi_wready => S_AXI_WREADY, -- : OUT std_logic; s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0); s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic; s_axi_bready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Write Channel (Read side) m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0); m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic; m_axi_awready => '0', -- : IN std_logic := '0'; m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0); m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic; m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0); m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic; m_axi_wready => '0', -- : IN std_logic := '0'; m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bvalid => '0', -- : IN std_logic := '0'; m_axi_bready => M_AXI_BREADY, -- : OUT std_logic; -- AXI Full/Lite Slave Read Channel (Write side) s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arvalid => '0', -- : IN std_logic := '0'; s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic; s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic; s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0); s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic; s_axi_rready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Read Channel (Read side) m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0); m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic; m_axi_arready => '0', -- : IN std_logic := '0'; m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rlast => '0', -- : IN std_logic := '0'; m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rvalid => '0', -- : IN std_logic := '0'; m_axi_rready => M_AXI_RREADY, -- : OUT std_logic; -- AXI Streaming Slave Signals (Write side) s_axis_tvalid => '0', -- : IN std_logic := '0'; s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic; s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tlast => '0', -- : IN std_logic := '0'; s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- AXI Streaming Master Signals (Read side) m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic; m_axis_tready => '0', -- : IN std_logic := '0'; m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0); m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0); m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0); m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic; m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0); m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0); m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals axi_aw_injectsbiterr => '0', -- : IN std_logic := '0'; axi_aw_injectdbiterr => '0', -- : IN std_logic := '0'; axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic; axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic; axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic; axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic; axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Data Channel Signals axi_w_injectsbiterr => '0', -- : IN std_logic := '0'; axi_w_injectdbiterr => '0', -- : IN std_logic := '0'; axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic; axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic; axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic; axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic; axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Response Channel Signals axi_b_injectsbiterr => '0', -- : IN std_logic := '0'; axi_b_injectdbiterr => '0', -- : IN std_logic := '0'; axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic; axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic; axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic; axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic; axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Address Channel Signals axi_ar_injectsbiterr => '0', -- : IN std_logic := '0'; axi_ar_injectdbiterr => '0', -- : IN std_logic := '0'; axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic; axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic; axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic; axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic; axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Data Channel Signals axi_r_injectsbiterr => '0', -- : IN std_logic := '0'; axi_r_injectdbiterr => '0', -- : IN std_logic := '0'; axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic; axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic; axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic; axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic; axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Streaming FIFO Related Signals axis_injectsbiterr => '0', -- : IN std_logic := '0'; axis_injectdbiterr => '0', -- : IN std_logic := '0'; axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic; axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic; axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic; axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0'; axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1'; ); END ARCHITECTURE xilinx;
------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- axi_vdma_afifo_builtin.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010, 2012-2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- LIBRARY ieee; USE ieee.std_logic_1164.ALL; library fifo_generator_v12_0; use fifo_generator_v12_0.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.all; --use proc_common_v4_0.coregen_comp_defs.all; --use proc_common_v4_0.family_support.all; library axi_vdma_v6_2; use axi_vdma_v6_2.axi_vdma_pkg.all; -- synopsys translate_off --library XilinxCoreLib; --use XilinxCoreLib.all; -- synopsys translate_on ENTITY axi_vdma_afifo_builtin IS GENERIC ( ------------------------------------------------------------------------- -- Generic Declarations ------------------------------------------------------------------------- PL_FIFO_TYPE : STRING := "BLOCK_RAM"; -- BLOCK_RAM, LUTRAM, BUILT_IN; Default: BLOCK_RAM PL_READ_MODE : STRING := "STANDARD"; -- STANDARD, FWFT; Default: STANDARD PL_FASTER_CLOCK : STRING := "WR_CLK"; -- WR_CLK, RD_CLK; Default: WR_CLK PL_FULL_FLAGS_RST_VAL : INTEGER := 1; -- 1, 0; Default: 1 PL_DATA_WIDTH : INTEGER := 16; -- 1 - 1024; Default 16 C_FAMILY : string := "virtex7"; PL_FIFO_DEPTH : INTEGER := 1024 -- 16 - 256K; Default 1K ); PORT ( -- Common signal rst : in std_logic := '0'; sleep : in std_logic := '0'; wr_rst_busy : out std_logic := '0'; rd_rst_busy : out std_logic := '0'; -- Write Domain signals wr_clk : in std_logic := '0'; din : in std_logic_vector(PL_DATA_WIDTH-1 downto 0) := (others => '0'); wr_en : in std_logic := '0'; full : out std_logic := '0'; -- Write Domain signals rd_clk : in std_logic := '0'; rd_en : in std_logic := '0'; dout : out std_logic_vector(PL_DATA_WIDTH-1 downto 0) := (others => '0'); empty : out std_logic := '1' ); END ENTITY axi_vdma_afifo_builtin; ARCHITECTURE xilinx OF axi_vdma_afifo_builtin IS attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of xilinx : architecture is "yes"; --------------------------------------------------------------------------- -- FUNCTION : log2roundup --------------------------------------------------------------------------- FUNCTION log2roundup ( data_value : integer) RETURN integer IS VARIABLE width : integer := 0; VARIABLE cnt : integer := 1; CONSTANT lower_limit : integer := 1; CONSTANT upper_limit : integer := 8; BEGIN IF (data_value <= 1) THEN width := 0; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt 2; END LOOP; END IF; RETURN width; END log2roundup; ------------------------------------------------------------------------------ -- This function is used to implement an IF..THEN when such a statement is not -- allowed. ------------------------------------------------------------------------------ FUNCTION if_then_else ( condition : boolean; true_case : integer; false_case : integer) RETURN integer IS VARIABLE retval : integer := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; ------------------------------------------------------------------------------ -- This function is used to implement an IF..THEN when such a statement is not -- allowed and returns string. ------------------------------------------------------------------------------ function if_then_else ( condition : boolean; true_case : string; false_case : string) return string is begin if not condition then return false_case; else return true_case; end if; end if_then_else; ----------------------------------------------------------------------------- -- FUNCTION: to_lower_case_char -- Returns the lower case form of char IF char is an upper case letter. -- Otherwise char is returned. ----------------------------------------------------------------------------- FUNCTION to_lower_case_char( char : character ) RETURN character IS BEGIN ------------------------------------------------------------------------- -- If char is not an upper case letter THEN return char -- -- Otherwise map char to its corresponding lower case character and -- return that ------------------------------------------------------------------------- IF char<'A' OR char>'Z' THEN RETURN char; END IF; CASE char IS WHEN 'A' => RETURN 'a'; WHEN 'B' => RETURN 'b'; WHEN 'C' => RETURN 'c'; WHEN 'D' => RETURN 'd'; WHEN 'E' => RETURN 'e'; WHEN 'F' => RETURN 'f'; WHEN 'G' => RETURN 'g'; WHEN 'H' => RETURN 'h'; WHEN 'I' => RETURN 'i'; WHEN 'J' => RETURN 'j'; WHEN 'K' => RETURN 'k'; WHEN 'L' => RETURN 'l'; WHEN 'M' => RETURN 'm'; WHEN 'N' => RETURN 'n'; WHEN 'O' => RETURN 'o'; WHEN 'P' => RETURN 'p'; WHEN 'Q' => RETURN 'q'; WHEN 'R' => RETURN 'r'; WHEN 'S' => RETURN 's'; WHEN 'T' => RETURN 't'; WHEN 'U' => RETURN 'u'; WHEN 'V' => RETURN 'v'; WHEN 'W' => RETURN 'w'; WHEN 'X' => RETURN 'x'; WHEN 'Y' => RETURN 'y'; WHEN 'Z' => RETURN 'z'; WHEN OTHERS => RETURN char; END CASE; END to_lower_case_char; ----------------------------------------------------------------------------- -- Returns true IF case insensitive string comparison determines that -- str1 and str2 are equal ----------------------------------------------------------------------------- FUNCTION equal_ignore_case( str1 : string; str2 : string ) RETURN boolean IS CONSTANT len1 : integer := str1'length; CONSTANT len2 : integer := str2'length; VARIABLE equal : boolean := TRUE; BEGIN IF NOT (len1=len2) THEN equal := FALSE; ELSE FOR i IN str2'left TO str1'right LOOP IF NOT (to_lower_case_char(str1(i)) = to_lower_case_char(str2(i))) THEN equal := FALSE; END IF; END LOOP; END IF; RETURN equal; END equal_ignore_case; --############################################################# --# --# Get the Primitive fifo type --# Description: Algorithm for Built-In FIFO implementation --# to determine which primitive is most optimal to use --# --############################################################# function get_Prim_Fifo_Type ( width : integer; depth : integer; use_ecc : integer) return string is variable prim_4kx4_used : integer := (((width-1)/4 +1)((depth-1)/4096 +1)); variable prim_2kx9_used : integer := (((width-1)/9 +1)((depth-1)/2048 +1)); variable prim_1kx18_used : integer := (((width-1)/18+1)((depth-1)/1024 +1)); variable prim_512x36_used : integer := (((width-1)/36+1)((depth-1)/512 +1)); variable prim_8kx4_used : integer := (((width-1)/4 +1)((depth-1)/8192 +1)); variable prim_4kx9_used : integer := (((width-1)/9 +1)((depth-1)/4096 +1)); variable prim_2kx18_used : integer := (((width-1)/18+1)((depth-1)/2048 +1)); variable prim_1kx36_used : integer := (((width-1)/36+1)((depth-1)/1024 +1)); variable prim_512x72_used : integer := (((width-1)/72+1)((depth-1)/512 +1)); variable min_used : integer := prim_4kx4_used; variable min_type : string (1 to 6) := "4kx4 "; begin if (use_ecc = 0) then --########################################################## --# Rules: Primitive used should --# - generate correct full flags if depth >= 512 --# - use min number of primitives --# - use primitive that reduces latency when possible --# This creates 3 cases: --# 1) depth <= 512 --# 2) depth = 1k --# 3) depth = 2k --# 4) depth >= 4k --########################################################## if (depth <= 512) then if (min_used > prim_512x72_used) then min_used := prim_512x72_used; min_type := "512x72"; else min_used := prim_512x36_used; min_type := "512x36"; end if; elsif (depth = 1024) then min_used := prim_1kx18_used; min_type := "1kx18 "; if (min_used > prim_512x36_used) then min_used := prim_512x36_used; min_type := "512x36"; end if; if (min_used > prim_1kx36_used) then min_used := prim_1kx36_used; min_type := "1kx36 "; end if; if (min_used > prim_512x72_used) then min_used := prim_512x72_used; min_type := "512x72"; end if; elsif (depth = 2048) then min_used := prim_2kx9_used; min_type := "2kx9 "; if (min_used > prim_1kx18_used) then min_used := prim_1kx18_used; min_type := "1kx18 "; end if; if (min_used > prim_512x36_used) then min_used := prim_512x36_used; min_type := "512x36"; end if; if (min_used > prim_2kx18_used) then min_used := prim_2kx18_used; min_type := "2kx18 "; end if; if (min_used > prim_1kx36_used) then min_used := prim_1kx36_used; min_type := "1kx36 "; end if; if (min_used > prim_512x72_used) then min_used := prim_512x72_used; min_type := "512x72"; end if; else min_used := prim_4kx4_used; min_type := "4kx4 "; if (min_used > prim_2kx9_used) then min_used := prim_2kx9_used; min_type := "2kx9 "; end if; if (min_used > prim_1kx18_used) then min_used := prim_1kx18_used; min_type := "1kx18 "; end if; if (min_used > prim_512x36_used) then min_used := prim_512x36_used; min_type := "512x36"; end if; if (min_used > prim_8kx4_used) then min_used := prim_8kx4_used; min_type := "8kx4 "; end if; if (min_used > prim_4kx9_used) then min_used := prim_4kx9_used; min_type := "4kx9 "; end if; if (min_used > prim_2kx18_used) then min_used := prim_2kx18_used; min_type := "2kx18 "; end if; if (min_used > prim_1kx36_used) then min_used := prim_1kx36_used; min_type := "1kx36 "; end if; if (min_used > prim_512x72_used) then min_used := prim_512x72_used; min_type := "512x72"; end if; end if; else -- if ecc is used, always use the 512x72 primitive min_used := prim_512x72_used; min_type := "512x72"; end if; return min_type; end get_Prim_Fifo_Type; --CONSTANT GND : std_logic := '0'; CONSTANT VCC : std_logic := '1'; CONSTANT ZERO1 : std_logic_vector(0 downto 0) := (others => '0'); CONSTANT ZERO2 : std_logic_vector(1 downto 0) := (others => '0'); CONSTANT ZERO3 : std_logic_vector(2 downto 0) := (others => '0'); CONSTANT ZERO4 : std_logic_vector(3 downto 0) := (others => '0'); CONSTANT ZERO8 : std_logic_vector(7 downto 0) := (others => '0'); CONSTANT ZERO16 : std_logic_vector(15 downto 0) := (others => '0'); CONSTANT ZERO32 : std_logic_vector(31 downto 0) := (others => '0'); CONSTANT ZERO64 : std_logic_vector(63 downto 0) := (others => '0'); --CONSTANT ZERO_pntr : std_logic_vector(log2roundup(pl_fifo_depth)-1 downto 0) := (others => '0'); CONSTANT C_PRELOAD_LATENCY : integer := if_then_else((PL_READ_MODE = "FWFT"), 0, 1); CONSTANT C_PRELOAD_REGS : integer := if_then_else((PL_READ_MODE = "FWFT"), 1, 0); CONSTANT C_WR_FREQ : integer := if_then_else((PL_FASTER_CLOCK = "WR_CLK"), 10, 1); CONSTANT C_RD_FREQ : integer := if_then_else((PL_FASTER_CLOCK = "RD_CLK"), 10, 1); CONSTANT C_MEMORY_TYPE : integer := if_then_else((PL_FIFO_TYPE = "BLOCK_RAM"), 1, if_then_else((PL_FIFO_TYPE = "LUTRAM"), 2, if_then_else((PL_FIFO_TYPE = "BUILT_IN"), 4, 0))); CONSTANT C_IMPLEMENTATION_TYPE : integer := if_then_else((PL_FIFO_TYPE = "BLOCK_RAM"), 0, if_then_else((PL_FIFO_TYPE = "LUTRAM"), 0, if_then_else((PL_FIFO_TYPE = "BUILT_IN"), 6, 8))); CONSTANT PRIM_FIFO_TYPE : string := get_Prim_Fifo_Type(pl_data_width,pl_fifo_depth,0); CONSTANT C_PRIM_FIFO_TYPE : string := if_then_else(PRIM_FIFO_TYPE = "8kx4 ", "8kx4", if_then_else(PRIM_FIFO_TYPE = "4kx9 ", "4kx9", if_then_else(PRIM_FIFO_TYPE = "4kx4 ", "4kx4", if_then_else(PRIM_FIFO_TYPE = "2kx18 ", "2kx18", if_then_else(PRIM_FIFO_TYPE = "2kx9 ", "2kx9", if_then_else(PRIM_FIFO_TYPE = "1kx36 ", "1kx36", if_then_else(PRIM_FIFO_TYPE = "1kx18 ", "1kx18", if_then_else(PRIM_FIFO_TYPE = "512x72", "512x72", if_then_else(PRIM_FIFO_TYPE = "512x36", "512x36",""))))))))); CONSTANT IS_FIFO_TYPE_VLD : integer := if_then_else((PL_FIFO_TYPE = "BLOCK_RAM") or (PL_FIFO_TYPE = "LUTRAM") or (PL_FIFO_TYPE = "BUILT_IN"), 1, 0); CONSTANT IS_READ_MODE_VLD : integer := if_then_else((PL_READ_MODE = "STANDARD") or (PL_READ_MODE = "FWFT"), 1, 0); CONSTANT IS_DATA_WIDTH_VLD : integer := if_then_else(PL_DATA_WIDTH > 0 and PL_DATA_WIDTH <= 1024, 1, 0); CONSTANT IS_FIFO_DEPTH_VLD : integer := if_then_else((PL_FIFO_DEPTH = 16 or PL_FIFO_DEPTH = 32 or PL_FIFO_DEPTH = 64 or PL_FIFO_DEPTH = 128 or PL_FIFO_DEPTH = 256 or PL_FIFO_DEPTH = 512 or PL_FIFO_DEPTH = 1024 or PL_FIFO_DEPTH = 2048 or PL_FIFO_DEPTH = 4096 or PL_FIFO_DEPTH = 8192 or PL_FIFO_DEPTH = 16384 or PL_FIFO_DEPTH = 32768 or PL_FIFO_DEPTH = 65536 or PL_FIFO_DEPTH = 131072 or PL_FIFO_DEPTH = 262144),1,0); CONSTANT VLD_BI_DEPTH : integer := if_then_else((PL_FIFO_DEPTH = 512 or PL_FIFO_DEPTH = 1024 or PL_FIFO_DEPTH = 2048 or PL_FIFO_DEPTH = 4096 or PL_FIFO_DEPTH = 8192 or PL_FIFO_DEPTH = 16384 or PL_FIFO_DEPTH = 32768 or PL_FIFO_DEPTH = 65536 or PL_FIFO_DEPTH = 131072 or PL_FIFO_DEPTH = 262144),1,0); -- CONSTANT IS_BI_DEPTH_VLD : integer := if_then_else((VLD_BI_DEPTH = 1 and PL_FIFO_TYPE = "BUILT_IN"), 1, 0); CONSTANT IS_BI_DEPTH_VLD : integer := if_then_else((VLD_BI_DEPTH = 1), 1, 0); CONSTANT log2roundup_pl_fifo_depth : integer := log2roundup(pl_fifo_depth); CONSTANT PROG_FULL_THRESH_ASSERT_VAL_1 : integer := if_then_else((PL_FIFO_TYPE = "BUILT_IN"), PL_FIFO_DEPTH-150, 14); CONSTANT PROG_FULL_THRESH_NEGATE_VAL_1 : integer := if_then_else((PL_FIFO_TYPE = "BUILT_IN"), PL_FIFO_DEPTH-160, 12); CONSTANT SYNC_RST_PORT : integer := if_then_else(((C_FAMILY = "kintexu") or (C_FAMILY = "virtexu") or (C_FAMILY = "artixu")), 1, 0); -- ultra-scale CONSTANT ASYNC_RST_PORT : integer := if_then_else(((C_FAMILY /= "kintexu") and (C_FAMILY /= "virtexu") and (C_FAMILY /= "artixu")), 1, 0); -- 7-series (not ultrascale) --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal ZERO_pntr : std_logic_vector(log2roundup_pl_fifo_depth-1 downto 0) := (others => '0'); signal GND : std_logic := '0'; signal ALMOST_FULL : std_logic; signal WR_ACK : std_logic; signal OVERFLOW : std_logic; signal ALMOST_EMPTY : std_logic; signal VALID : std_logic; signal UNDERFLOW : std_logic; signal PROG_FULL : std_logic; signal PROG_EMPTY : std_logic; signal SBITERR : std_logic; signal DBITERR : std_logic; signal S_AXI_AWREADY : std_logic; signal S_AXI_WREADY : std_logic; signal S_AXI_BID : std_logic_vector(3 DOWNTO 0); signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_BUSER : std_logic_vector(0 downto 0); signal S_AXI_BVALID : std_logic; -- AXI Full/Lite Master Write Channel (Read side) signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0); signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWUSER : std_logic_vector(0 downto 0); signal M_AXI_AWVALID : std_logic; signal M_AXI_WID : std_logic_vector(3 DOWNTO 0); signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0); signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0); signal M_AXI_WLAST : std_logic; signal M_AXI_WUSER : std_logic_vector(0 downto 0); signal M_AXI_WVALID : std_logic; signal M_AXI_BREADY : std_logic; -- AXI Full/Lite Slave Read Channel (Write side) signal S_AXI_ARREADY : std_logic; signal S_AXI_RID : std_logic_vector(3 DOWNTO 0); signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0); signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_RLAST : std_logic; signal S_AXI_RUSER : std_logic_vector(0 downto 0); signal S_AXI_RVALID : std_logic; -- AXI Full/Lite Master Read Channel (Read side) signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0); signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARUSER : std_logic_vector(0 downto 0); signal M_AXI_ARVALID : std_logic; signal M_AXI_RREADY : std_logic; -- AXI Streaming Slave Signals (Write side) signal S_AXIS_TREADY : std_logic; -- AXI Streaming Master Signals (Read side) signal M_AXIS_TVALID : std_logic; signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0); signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TLAST : std_logic; signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0); signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_SBITERR : std_logic; signal AXI_AW_DBITERR : std_logic; signal AXI_AW_OVERFLOW : std_logic; signal AXI_AW_UNDERFLOW : std_logic; signal AXI_AW_PROG_FULL : STD_LOGIC; signal AXI_AW_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Data Channel Signals signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_SBITERR : std_logic; signal AXI_W_DBITERR : std_logic; signal AXI_W_OVERFLOW : std_logic; signal AXI_W_UNDERFLOW : std_logic; signal AXI_W_PROG_FULL : STD_LOGIC; signal AXI_W_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Response Channel Signals signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_SBITERR : std_logic; signal AXI_B_DBITERR : std_logic; signal AXI_B_OVERFLOW : std_logic; signal AXI_B_UNDERFLOW : std_logic; signal AXI_B_PROG_FULL : STD_LOGIC; signal AXI_B_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Address Channel Signals signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_SBITERR : std_logic; signal AXI_AR_DBITERR : std_logic; signal AXI_AR_OVERFLOW : std_logic; signal AXI_AR_UNDERFLOW : std_logic; signal AXI_AR_PROG_FULL : STD_LOGIC; signal AXI_AR_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Data Channel Signals signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_SBITERR : std_logic; signal AXI_R_DBITERR : std_logic; signal AXI_R_OVERFLOW : std_logic; signal AXI_R_UNDERFLOW : std_logic; signal AXI_R_PROG_FULL : STD_LOGIC; signal AXI_R_PROG_EMPTY : STD_LOGIC; -- AXI Streaming FIFO Related Signals signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_SBITERR : std_logic; signal AXIS_DBITERR : std_logic; signal AXIS_OVERFLOW : std_logic; signal AXIS_UNDERFLOW : std_logic; signal AXIS_PROG_FULL : STD_LOGIC; signal AXIS_PROG_EMPTY : STD_LOGIC; --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal DATA_COUNT : std_logic_vector(log2roundup_pl_fifo_depth-1 DOWNTO 0); signal RD_DATA_COUNT : std_logic_vector(log2roundup_pl_fifo_depth-1 DOWNTO 0); signal WR_DATA_COUNT : std_logic_vector(log2roundup_pl_fifo_depth-1 DOWNTO 0); signal wr_rst_busy_sig : std_logic := '0'; signal rd_rst_busy_sig : std_logic := '0'; signal rst_i : std_logic := '0'; signal srst_i : std_logic := '0'; BEGIN FAMILY_8 : if ((C_FAMILY = "kintexu") or (C_FAMILY = "virtexu") or (C_FAMILY = "artixu")) generate begin wr_rst_busy <= wr_rst_busy_sig; rd_rst_busy <= rd_rst_busy_sig; srst_i <= rst; rst_i <= '0'; end generate FAMILY_8; FAMILY_NOT_8 : if ((C_FAMILY /= "kintexu") and (C_FAMILY /= "virtexu") and (C_FAMILY /= "artixu")) generate begin wr_rst_busy <= '0'; rd_rst_busy <= '0'; srst_i <= '0'; rst_i <= rst; end generate FAMILY_NOT_8; ZERO_pntr <= (others => '0'); GND <= '0'; fg_builtin_fifo_inst : entity fifo_generator_v12_0.fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 0, -- C_COUNT_TYPE => C_COUNT_TYPE, C_DATA_COUNT_WIDTH => log2roundup_pl_fifo_depth, -- C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_DIN_WIDTH => pl_data_width, -- C_DOUT_RST_VAL => C_DOUT_RST_VAL, C_DOUT_WIDTH => pl_data_width, -- C_ENABLE_RLOCS => C_ENABLE_RLOCS, --C_FAMILY => "virtex7", C_FAMILY => C_FAMILY, C_FULL_FLAGS_RST_VAL => pl_full_flags_rst_val, -- C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY, -- C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL, -- C_HAS_BACKUP => C_HAS_BACKUP, -- C_HAS_DATA_COUNT => C_HAS_DATA_COUNT, -- C_HAS_INT_CLK => C_HAS_INT_CLK, -- C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, -- C_HAS_OVERFLOW => C_HAS_OVERFLOW, -- C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT, -- C_HAS_RD_RST => C_HAS_RD_RST, C_HAS_RST => ASYNC_RST_PORT, C_HAS_SRST => SYNC_RST_PORT, -- C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, -- C_HAS_VALID => C_HAS_VALID, -- C_HAS_WR_ACK => C_HAS_WR_ACK, -- C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT, -- C_HAS_WR_RST => C_HAS_WR_RST, C_IMPLEMENTATION_TYPE => C_IMPLEMENTATION_TYPE, -- C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MEMORY_TYPE => C_MEMORY_TYPE, -- C_MIF_FILE_NAME => C_MIF_FILE_NAME, -- C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, -- C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, C_PRELOAD_REGS => C_PRELOAD_REGS, C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE, C_PROG_EMPTY_THRESH_ASSERT_VAL => 10, C_PROG_EMPTY_THRESH_NEGATE_VAL => 9, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL_1, C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL_1, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => log2roundup_pl_fifo_depth, C_RD_DEPTH => pl_fifo_depth, C_RD_FREQ => C_RD_FREQ, C_RD_PNTR_WIDTH => log2roundup_pl_fifo_depth, -- C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, -- C_USE_DOUT_RST => C_USE_DOUT_RST, -- C_USE_ECC => C_USE_ECC, -- C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, -- C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, -- C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT, -- C_VALID_LOW => C_VALID_LOW, -- C_WR_ACK_LOW => C_WR_ACK_LOW, C_WR_DATA_COUNT_WIDTH => log2roundup_pl_fifo_depth, C_WR_DEPTH => pl_fifo_depth, C_WR_FREQ => C_WR_FREQ, C_WR_PNTR_WIDTH => log2roundup_pl_fifo_depth, -- C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY, -- C_MSGON_VAL => C_MSGON_VAL, -- C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC, -- C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE, C_SYNCHRONIZER_STAGE => MTBF_STAGES, -- AXI Interface related parameters start here C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0; C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0; C_HAS_SLAVE_CE => 0, -- : integer := 0; C_HAS_MASTER_CE => 0, -- : integer := 0; C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0; C_USE_COMMON_OVERFLOW => 0, -- : integer := 0; C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0; C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH => 4 , -- : integer := 0; C_AXI_ADDR_WIDTH => 32, -- : integer := 0; C_AXI_DATA_WIDTH => 64, -- : integer := 0; C_AXI_LEN_WIDTH => 8, -- : integer := 8; C_AXI_LOCK_WIDTH => 2, -- : integer := 2; C_HAS_AXI_ID => 0, -- : integer := 0; C_HAS_AXI_AWUSER => 0 , -- : integer := 0; C_HAS_AXI_WUSER => 0 , -- : integer := 0; C_HAS_AXI_BUSER => 0 , -- : integer := 0; C_HAS_AXI_ARUSER => 0 , -- : integer := 0; C_HAS_AXI_RUSER => 0 , -- : integer := 0; C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0; C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0; C_AXI_WUSER_WIDTH => 1 , -- : integer := 0; C_AXI_BUSER_WIDTH => 1 , -- : integer := 0; C_AXI_RUSER_WIDTH => 1 , -- : integer := 0; -- AXI Streaming C_HAS_AXIS_TDATA => 0 , -- : integer := 0; C_HAS_AXIS_TID => 0 , -- : integer := 0; C_HAS_AXIS_TDEST => 0 , -- : integer := 0; C_HAS_AXIS_TUSER => 0 , -- : integer := 0; C_HAS_AXIS_TREADY => 1 , -- : integer := 0; C_HAS_AXIS_TLAST => 0 , -- : integer := 0; C_HAS_AXIS_TSTRB => 0 , -- : integer := 0; C_HAS_AXIS_TKEEP => 0 , -- : integer := 0; C_AXIS_TDATA_WIDTH => 64, -- : integer := 1; C_AXIS_TID_WIDTH => 8 , -- : integer := 1; C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1; C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1; C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1; C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Data FIFO C_APPLICATION_TYPE_WACH => 0, -- : integer := 0; C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0; C_APPLICATION_TYPE_RACH => 0, -- : integer := 0; C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH => 0, -- : integer := 0; C_USE_ECC_WDCH => 0, -- : integer := 0; C_USE_ECC_WRCH => 0, -- : integer := 0; C_USE_ECC_RACH => 0, -- : integer := 0; C_USE_ECC_RDCH => 0, -- : integer := 0; C_USE_ECC_AXIS => 0, -- : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH => 32, -- : integer := 1; C_DIN_WIDTH_WDCH => 64, -- : integer := 1; C_DIN_WIDTH_WRCH => 2 , -- : integer := 1; C_DIN_WIDTH_RACH => 32, -- : integer := 1; C_DIN_WIDTH_RDCH => 64, -- : integer := 1; C_DIN_WIDTH_AXIS => 1 , -- : integer := 1; C_WR_DEPTH_WACH => 16 , -- : integer := 16; C_WR_DEPTH_WDCH => 1024, -- : integer := 16; C_WR_DEPTH_WRCH => 16 , -- : integer := 16; C_WR_DEPTH_RACH => 16 , -- : integer := 16; C_WR_DEPTH_RDCH => 1024, -- : integer := 16; C_WR_DEPTH_AXIS => 1024, -- : integer := 16; C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4; C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0; C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0; C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0; C_REG_SLICE_MODE_WACH => 0, -- : integer := 0; C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0; C_REG_SLICE_MODE_RACH => 0, -- : integer := 0; C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0 ) PORT MAP ( backup => GND, backup_marker => GND, clk => GND, rst => rst_i, srst => srst_i, wr_clk => wr_clk, wr_rst => GND, rd_clk => rd_clk, rd_rst => GND, din => din, wr_en => wr_en, rd_en => rd_en, sleep => sleep, wr_rst_busy => wr_rst_busy_sig, rd_rst_busy => rd_rst_busy_sig, prog_empty_thresh => ZERO_pntr, prog_empty_thresh_assert => ZERO_pntr, prog_empty_thresh_negate => ZERO_pntr, prog_full_thresh => ZERO_pntr, prog_full_thresh_assert => ZERO_pntr, prog_full_thresh_negate => ZERO_pntr, int_clk => GND, injectdbiterr => GND, injectsbiterr => GND, dout => dout, full => full, empty => empty, almost_full => ALMOST_FULL, wr_ack => WR_ACK, overflow => OVERFLOW, almost_empty => ALMOST_EMPTY, valid => VALID, underflow => UNDERFLOW, data_count => DATA_COUNT, rd_data_count => RD_DATA_COUNT, wr_data_count => WR_DATA_COUNT, prog_full => PROG_FULL, prog_empty => PROG_EMPTY, sbiterr => SBITERR, dbiterr => DBITERR, m_aclk => '0', -- : IN std_logic := '0'; s_aclk => '0', -- : IN std_logic := '0'; s_aresetn => '0', -- : IN std_logic := '0'; m_aclk_en => '0', -- : IN std_logic := '0'; s_aclk_en => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Slave Write Channel (write side) s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awvalid => '0', -- : IN std_logic := '0'; s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic; s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wlast => '0', -- : IN std_logic := '0'; s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wvalid => '0', -- : IN std_logic := '0'; s_axi_wready => S_AXI_WREADY, -- : OUT std_logic; s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0); s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic; s_axi_bready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Write Channel (Read side) m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0); m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic; m_axi_awready => '0', -- : IN std_logic := '0'; m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0); m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic; m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0); m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic; m_axi_wready => '0', -- : IN std_logic := '0'; m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bvalid => '0', -- : IN std_logic := '0'; m_axi_bready => M_AXI_BREADY, -- : OUT std_logic; -- AXI Full/Lite Slave Read Channel (Write side) s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arvalid => '0', -- : IN std_logic := '0'; s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic; s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic; s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0); s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic; s_axi_rready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Read Channel (Read side) m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0); m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic; m_axi_arready => '0', -- : IN std_logic := '0'; m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rlast => '0', -- : IN std_logic := '0'; m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rvalid => '0', -- : IN std_logic := '0'; m_axi_rready => M_AXI_RREADY, -- : OUT std_logic; -- AXI Streaming Slave Signals (Write side) s_axis_tvalid => '0', -- : IN std_logic := '0'; s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic; s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tlast => '0', -- : IN std_logic := '0'; s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- AXI Streaming Master Signals (Read side) m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic; m_axis_tready => '0', -- : IN std_logic := '0'; m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0); m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0); m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0); m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic; m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0); m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0); m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals axi_aw_injectsbiterr => '0', -- : IN std_logic := '0'; axi_aw_injectdbiterr => '0', -- : IN std_logic := '0'; axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic; axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic; axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic; axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic; axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Data Channel Signals axi_w_injectsbiterr => '0', -- : IN std_logic := '0'; axi_w_injectdbiterr => '0', -- : IN std_logic := '0'; axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic; axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic; axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic; axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic; axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Response Channel Signals axi_b_injectsbiterr => '0', -- : IN std_logic := '0'; axi_b_injectdbiterr => '0', -- : IN std_logic := '0'; axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic; axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic; axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic; axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic; axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Address Channel Signals axi_ar_injectsbiterr => '0', -- : IN std_logic := '0'; axi_ar_injectdbiterr => '0', -- : IN std_logic := '0'; axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic; axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic; axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic; axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic; axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Data Channel Signals axi_r_injectsbiterr => '0', -- : IN std_logic := '0'; axi_r_injectdbiterr => '0', -- : IN std_logic := '0'; axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic; axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic; axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic; axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic; axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Streaming FIFO Related Signals axis_injectsbiterr => '0', -- : IN std_logic := '0'; axis_injectdbiterr => '0', -- : IN std_logic := '0'; axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic; axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic; axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic; axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0'; axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1'; ); END ARCHITECTURE xilinx;
-- ** -- T80(b) core. In an effort to merge and maintain bug fixes .... -- -- -- Ver 300 started tidyup -- MikeJ March 2005 -- Latest version from www.fpgaarcade.com (original www.opencores.org) -- -- ** -- -- Z80 compatible microprocessor core, asynchronous top level -- -- Version : 0247 -- -- Copyright (c) 2001-2002 Daniel Wallner ([email protected]) -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Please report bugs to the author, but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- -- The latest version of this file can be found at: -- http://www.opencores.org/cvsweb.shtml/t80/ -- -- Limitations : -- -- File history : -- -- 0208 : First complete release -- -- 0211 : Fixed interrupt cycle -- -- 0235 : Updated for T80 interface change -- -- 0238 : Updated for T80 interface change -- -- 0240 : Updated for T80 interface change -- -- 0242 : Updated for T80 interface change -- -- 0247 : Fixed bus req/ack cycle -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.T80_Pack.all; entity T80a is generic( Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB ); port( RESET_n : in std_logic; CLK_n : in std_logic; WAIT_n : in std_logic; INT_n : in std_logic; NMI_n : in std_logic; BUSRQ_n : in std_logic; M1_n : out std_logic; MREQ_n : out std_logic; IORQ_n : out std_logic; RD_n : out std_logic; WR_n : out std_logic; RFSH_n : out std_logic; HALT_n : out std_logic; BUSAK_n : out std_logic; A : out std_logic_vector(15 downto 0); D : inout std_logic_vector(7 downto 0); D_I : in std_logic_vector(7 downto 0); D_O : out std_logic_vector(7 downto 0); ResetPC : in std_logic_vector(15 downto 0); ResetSP : in std_logic_vector(15 downto 0) ); end T80a; architecture rtl of T80a is signal CEN : std_logic; signal Reset_s : std_logic; signal IntCycle_n : std_logic; signal IORQ : std_logic; signal NoRead : std_logic; signal Write : std_logic; signal MREQ : std_logic; signal MReq_Inhibit : std_logic; signal Req_Inhibit : std_logic; signal RD : std_logic; signal MREQ_n_i : std_logic; signal IORQ_n_i : std_logic; signal RD_n_i : std_logic; signal WR_n_i : std_logic; signal RFSH_n_i : std_logic; signal BUSAK_n_i : std_logic; signal A_i : std_logic_vector(15 downto 0); signal DO : std_logic_vector(7 downto 0); signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser signal Wait_s : std_logic; signal MCycle : std_logic_vector(2 downto 0); signal TState : std_logic_vector(2 downto 0); begin CEN <= '1'; BUSAK_n <= BUSAK_n_i; MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit); RD_n_i <= not RD or Req_Inhibit; MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z'; IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z'; RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z'; WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z'; RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z'; A <= A_i when BUSAK_n_i = '1' else (others => 'Z'); D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); D_O <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); process (RESET_n, CLK_n) begin if RESET_n = '0' then Reset_s <= '0'; elsif CLK_n'event and CLK_n = '1' then Reset_s <= '1'; end if; end process; u0 : T80 generic map( Mode => Mode, IOWait => 1) port map( CEN => CEN, M1_n => M1_n, IORQ => IORQ, NoRead => NoRead, Write => Write, RFSH_n => RFSH_n_i, HALT_n => HALT_n, WAIT_n => Wait_s, INT_n => INT_n, NMI_n => NMI_n, RESET_n => Reset_s, BUSRQ_n => BUSRQ_n, BUSAK_n => BUSAK_n_i, CLK_n => CLK_n, A => A_i, DInst => D_I, -- D -> D_I DI => DI_Reg, DO => DO, MC => MCycle, TS => TState, IntCycle_n => IntCycle_n, ResetPC => ResetPC, ResetSP => ResetSP ); process (CLK_n) begin if CLK_n'event and CLK_n = '0' then Wait_s <= WAIT_n; if TState = "011" and BUSAK_n_i = '1' then DI_Reg <= to_x01(D_I); -- D -> D_I end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then WR_n_i <= '1'; elsif CLK_n'event and CLK_n = '1' then WR_n_i <= '1'; if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!! WR_n_i <= not Write; end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then Req_Inhibit <= '0'; elsif CLK_n'event and CLK_n = '1' then if MCycle = "001" and TState = "010" then Req_Inhibit <= '1'; else Req_Inhibit <= '0'; end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then MReq_Inhibit <= '0'; elsif CLK_n'event and CLK_n = '0' then if MCycle = "001" and TState = "010" then MReq_Inhibit <= '1'; else MReq_Inhibit <= '0'; end if; end if; end process; process(Reset_s,CLK_n) begin if Reset_s = '0' then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '0'; elsif CLK_n'event and CLK_n = '0' then if MCycle = "001" then if TState = "001" then RD <= IntCycle_n; MREQ <= IntCycle_n; IORQ_n_i <= IntCycle_n; end if; if TState = "011" then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '1'; end if; if TState = "100" then MREQ <= '0'; end if; else if TState = "001" and NoRead = '0' then RD <= not Write; IORQ_n_i <= not IORQ; MREQ <= not IORQ; end if; if TState = "011" then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '0'; end if; end if; end if; end process; end;
-- ** -- T80(b) core. In an effort to merge and maintain bug fixes .... -- -- -- Ver 300 started tidyup -- MikeJ March 2005 -- Latest version from www.fpgaarcade.com (original www.opencores.org) -- -- ** -- -- Z80 compatible microprocessor core, asynchronous top level -- -- Version : 0247 -- -- Copyright (c) 2001-2002 Daniel Wallner ([email protected]) -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Please report bugs to the author, but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- -- The latest version of this file can be found at: -- http://www.opencores.org/cvsweb.shtml/t80/ -- -- Limitations : -- -- File history : -- -- 0208 : First complete release -- -- 0211 : Fixed interrupt cycle -- -- 0235 : Updated for T80 interface change -- -- 0238 : Updated for T80 interface change -- -- 0240 : Updated for T80 interface change -- -- 0242 : Updated for T80 interface change -- -- 0247 : Fixed bus req/ack cycle -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.T80_Pack.all; entity T80a is generic( Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB ); port( RESET_n : in std_logic; CLK_n : in std_logic; WAIT_n : in std_logic; INT_n : in std_logic; NMI_n : in std_logic; BUSRQ_n : in std_logic; M1_n : out std_logic; MREQ_n : out std_logic; IORQ_n : out std_logic; RD_n : out std_logic; WR_n : out std_logic; RFSH_n : out std_logic; HALT_n : out std_logic; BUSAK_n : out std_logic; A : out std_logic_vector(15 downto 0); D : inout std_logic_vector(7 downto 0); D_I : in std_logic_vector(7 downto 0); D_O : out std_logic_vector(7 downto 0); ResetPC : in std_logic_vector(15 downto 0); ResetSP : in std_logic_vector(15 downto 0) ); end T80a; architecture rtl of T80a is signal CEN : std_logic; signal Reset_s : std_logic; signal IntCycle_n : std_logic; signal IORQ : std_logic; signal NoRead : std_logic; signal Write : std_logic; signal MREQ : std_logic; signal MReq_Inhibit : std_logic; signal Req_Inhibit : std_logic; signal RD : std_logic; signal MREQ_n_i : std_logic; signal IORQ_n_i : std_logic; signal RD_n_i : std_logic; signal WR_n_i : std_logic; signal RFSH_n_i : std_logic; signal BUSAK_n_i : std_logic; signal A_i : std_logic_vector(15 downto 0); signal DO : std_logic_vector(7 downto 0); signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser signal Wait_s : std_logic; signal MCycle : std_logic_vector(2 downto 0); signal TState : std_logic_vector(2 downto 0); begin CEN <= '1'; BUSAK_n <= BUSAK_n_i; MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit); RD_n_i <= not RD or Req_Inhibit; MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z'; IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z'; RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z'; WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z'; RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z'; A <= A_i when BUSAK_n_i = '1' else (others => 'Z'); D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); D_O <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); process (RESET_n, CLK_n) begin if RESET_n = '0' then Reset_s <= '0'; elsif CLK_n'event and CLK_n = '1' then Reset_s <= '1'; end if; end process; u0 : T80 generic map( Mode => Mode, IOWait => 1) port map( CEN => CEN, M1_n => M1_n, IORQ => IORQ, NoRead => NoRead, Write => Write, RFSH_n => RFSH_n_i, HALT_n => HALT_n, WAIT_n => Wait_s, INT_n => INT_n, NMI_n => NMI_n, RESET_n => Reset_s, BUSRQ_n => BUSRQ_n, BUSAK_n => BUSAK_n_i, CLK_n => CLK_n, A => A_i, DInst => D_I, -- D -> D_I DI => DI_Reg, DO => DO, MC => MCycle, TS => TState, IntCycle_n => IntCycle_n, ResetPC => ResetPC, ResetSP => ResetSP ); process (CLK_n) begin if CLK_n'event and CLK_n = '0' then Wait_s <= WAIT_n; if TState = "011" and BUSAK_n_i = '1' then DI_Reg <= to_x01(D_I); -- D -> D_I end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then WR_n_i <= '1'; elsif CLK_n'event and CLK_n = '1' then WR_n_i <= '1'; if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!! WR_n_i <= not Write; end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then Req_Inhibit <= '0'; elsif CLK_n'event and CLK_n = '1' then if MCycle = "001" and TState = "010" then Req_Inhibit <= '1'; else Req_Inhibit <= '0'; end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then MReq_Inhibit <= '0'; elsif CLK_n'event and CLK_n = '0' then if MCycle = "001" and TState = "010" then MReq_Inhibit <= '1'; else MReq_Inhibit <= '0'; end if; end if; end process; process(Reset_s,CLK_n) begin if Reset_s = '0' then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '0'; elsif CLK_n'event and CLK_n = '0' then if MCycle = "001" then if TState = "001" then RD <= IntCycle_n; MREQ <= IntCycle_n; IORQ_n_i <= IntCycle_n; end if; if TState = "011" then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '1'; end if; if TState = "100" then MREQ <= '0'; end if; else if TState = "001" and NoRead = '0' then RD <= not Write; IORQ_n_i <= not IORQ; MREQ <= not IORQ; end if; if TState = "011" then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '0'; end if; end if; end if; end process; end;
-- ** -- T80(b) core. In an effort to merge and maintain bug fixes .... -- -- -- Ver 300 started tidyup -- MikeJ March 2005 -- Latest version from www.fpgaarcade.com (original www.opencores.org) -- -- ** -- -- Z80 compatible microprocessor core, asynchronous top level -- -- Version : 0247 -- -- Copyright (c) 2001-2002 Daniel Wallner ([email protected]) -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Please report bugs to the author, but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- -- The latest version of this file can be found at: -- http://www.opencores.org/cvsweb.shtml/t80/ -- -- Limitations : -- -- File history : -- -- 0208 : First complete release -- -- 0211 : Fixed interrupt cycle -- -- 0235 : Updated for T80 interface change -- -- 0238 : Updated for T80 interface change -- -- 0240 : Updated for T80 interface change -- -- 0242 : Updated for T80 interface change -- -- 0247 : Fixed bus req/ack cycle -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.T80_Pack.all; entity T80a is generic( Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB ); port( RESET_n : in std_logic; CLK_n : in std_logic; WAIT_n : in std_logic; INT_n : in std_logic; NMI_n : in std_logic; BUSRQ_n : in std_logic; M1_n : out std_logic; MREQ_n : out std_logic; IORQ_n : out std_logic; RD_n : out std_logic; WR_n : out std_logic; RFSH_n : out std_logic; HALT_n : out std_logic; BUSAK_n : out std_logic; A : out std_logic_vector(15 downto 0); D : inout std_logic_vector(7 downto 0); D_I : in std_logic_vector(7 downto 0); D_O : out std_logic_vector(7 downto 0); ResetPC : in std_logic_vector(15 downto 0); ResetSP : in std_logic_vector(15 downto 0) ); end T80a; architecture rtl of T80a is signal CEN : std_logic; signal Reset_s : std_logic; signal IntCycle_n : std_logic; signal IORQ : std_logic; signal NoRead : std_logic; signal Write : std_logic; signal MREQ : std_logic; signal MReq_Inhibit : std_logic; signal Req_Inhibit : std_logic; signal RD : std_logic; signal MREQ_n_i : std_logic; signal IORQ_n_i : std_logic; signal RD_n_i : std_logic; signal WR_n_i : std_logic; signal RFSH_n_i : std_logic; signal BUSAK_n_i : std_logic; signal A_i : std_logic_vector(15 downto 0); signal DO : std_logic_vector(7 downto 0); signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser signal Wait_s : std_logic; signal MCycle : std_logic_vector(2 downto 0); signal TState : std_logic_vector(2 downto 0); begin CEN <= '1'; BUSAK_n <= BUSAK_n_i; MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit); RD_n_i <= not RD or Req_Inhibit; MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z'; IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z'; RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z'; WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z'; RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z'; A <= A_i when BUSAK_n_i = '1' else (others => 'Z'); D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); D_O <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); process (RESET_n, CLK_n) begin if RESET_n = '0' then Reset_s <= '0'; elsif CLK_n'event and CLK_n = '1' then Reset_s <= '1'; end if; end process; u0 : T80 generic map( Mode => Mode, IOWait => 1) port map( CEN => CEN, M1_n => M1_n, IORQ => IORQ, NoRead => NoRead, Write => Write, RFSH_n => RFSH_n_i, HALT_n => HALT_n, WAIT_n => Wait_s, INT_n => INT_n, NMI_n => NMI_n, RESET_n => Reset_s, BUSRQ_n => BUSRQ_n, BUSAK_n => BUSAK_n_i, CLK_n => CLK_n, A => A_i, DInst => D_I, -- D -> D_I DI => DI_Reg, DO => DO, MC => MCycle, TS => TState, IntCycle_n => IntCycle_n, ResetPC => ResetPC, ResetSP => ResetSP ); process (CLK_n) begin if CLK_n'event and CLK_n = '0' then Wait_s <= WAIT_n; if TState = "011" and BUSAK_n_i = '1' then DI_Reg <= to_x01(D_I); -- D -> D_I end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then WR_n_i <= '1'; elsif CLK_n'event and CLK_n = '1' then WR_n_i <= '1'; if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!! WR_n_i <= not Write; end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then Req_Inhibit <= '0'; elsif CLK_n'event and CLK_n = '1' then if MCycle = "001" and TState = "010" then Req_Inhibit <= '1'; else Req_Inhibit <= '0'; end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then MReq_Inhibit <= '0'; elsif CLK_n'event and CLK_n = '0' then if MCycle = "001" and TState = "010" then MReq_Inhibit <= '1'; else MReq_Inhibit <= '0'; end if; end if; end process; process(Reset_s,CLK_n) begin if Reset_s = '0' then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '0'; elsif CLK_n'event and CLK_n = '0' then if MCycle = "001" then if TState = "001" then RD <= IntCycle_n; MREQ <= IntCycle_n; IORQ_n_i <= IntCycle_n; end if; if TState = "011" then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '1'; end if; if TState = "100" then MREQ <= '0'; end if; else if TState = "001" and NoRead = '0' then RD <= not Write; IORQ_n_i <= not IORQ; MREQ <= not IORQ; end if; if TState = "011" then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '0'; end if; end if; end if; end process; end;
-- ** -- T80(b) core. In an effort to merge and maintain bug fixes .... -- -- -- Ver 300 started tidyup -- MikeJ March 2005 -- Latest version from www.fpgaarcade.com (original www.opencores.org) -- -- ** -- -- Z80 compatible microprocessor core, asynchronous top level -- -- Version : 0247 -- -- Copyright (c) 2001-2002 Daniel Wallner ([email protected]) -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Please report bugs to the author, but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- -- The latest version of this file can be found at: -- http://www.opencores.org/cvsweb.shtml/t80/ -- -- Limitations : -- -- File history : -- -- 0208 : First complete release -- -- 0211 : Fixed interrupt cycle -- -- 0235 : Updated for T80 interface change -- -- 0238 : Updated for T80 interface change -- -- 0240 : Updated for T80 interface change -- -- 0242 : Updated for T80 interface change -- -- 0247 : Fixed bus req/ack cycle -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.T80_Pack.all; entity T80a is generic( Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB ); port( RESET_n : in std_logic; CLK_n : in std_logic; WAIT_n : in std_logic; INT_n : in std_logic; NMI_n : in std_logic; BUSRQ_n : in std_logic; M1_n : out std_logic; MREQ_n : out std_logic; IORQ_n : out std_logic; RD_n : out std_logic; WR_n : out std_logic; RFSH_n : out std_logic; HALT_n : out std_logic; BUSAK_n : out std_logic; A : out std_logic_vector(15 downto 0); D : inout std_logic_vector(7 downto 0); D_I : in std_logic_vector(7 downto 0); D_O : out std_logic_vector(7 downto 0); ResetPC : in std_logic_vector(15 downto 0); ResetSP : in std_logic_vector(15 downto 0) ); end T80a; architecture rtl of T80a is signal CEN : std_logic; signal Reset_s : std_logic; signal IntCycle_n : std_logic; signal IORQ : std_logic; signal NoRead : std_logic; signal Write : std_logic; signal MREQ : std_logic; signal MReq_Inhibit : std_logic; signal Req_Inhibit : std_logic; signal RD : std_logic; signal MREQ_n_i : std_logic; signal IORQ_n_i : std_logic; signal RD_n_i : std_logic; signal WR_n_i : std_logic; signal RFSH_n_i : std_logic; signal BUSAK_n_i : std_logic; signal A_i : std_logic_vector(15 downto 0); signal DO : std_logic_vector(7 downto 0); signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser signal Wait_s : std_logic; signal MCycle : std_logic_vector(2 downto 0); signal TState : std_logic_vector(2 downto 0); begin CEN <= '1'; BUSAK_n <= BUSAK_n_i; MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit); RD_n_i <= not RD or Req_Inhibit; MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z'; IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z'; RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z'; WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z'; RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z'; A <= A_i when BUSAK_n_i = '1' else (others => 'Z'); D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); D_O <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); process (RESET_n, CLK_n) begin if RESET_n = '0' then Reset_s <= '0'; elsif CLK_n'event and CLK_n = '1' then Reset_s <= '1'; end if; end process; u0 : T80 generic map( Mode => Mode, IOWait => 1) port map( CEN => CEN, M1_n => M1_n, IORQ => IORQ, NoRead => NoRead, Write => Write, RFSH_n => RFSH_n_i, HALT_n => HALT_n, WAIT_n => Wait_s, INT_n => INT_n, NMI_n => NMI_n, RESET_n => Reset_s, BUSRQ_n => BUSRQ_n, BUSAK_n => BUSAK_n_i, CLK_n => CLK_n, A => A_i, DInst => D_I, -- D -> D_I DI => DI_Reg, DO => DO, MC => MCycle, TS => TState, IntCycle_n => IntCycle_n, ResetPC => ResetPC, ResetSP => ResetSP ); process (CLK_n) begin if CLK_n'event and CLK_n = '0' then Wait_s <= WAIT_n; if TState = "011" and BUSAK_n_i = '1' then DI_Reg <= to_x01(D_I); -- D -> D_I end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then WR_n_i <= '1'; elsif CLK_n'event and CLK_n = '1' then WR_n_i <= '1'; if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!! WR_n_i <= not Write; end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then Req_Inhibit <= '0'; elsif CLK_n'event and CLK_n = '1' then if MCycle = "001" and TState = "010" then Req_Inhibit <= '1'; else Req_Inhibit <= '0'; end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then MReq_Inhibit <= '0'; elsif CLK_n'event and CLK_n = '0' then if MCycle = "001" and TState = "010" then MReq_Inhibit <= '1'; else MReq_Inhibit <= '0'; end if; end if; end process; process(Reset_s,CLK_n) begin if Reset_s = '0' then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '0'; elsif CLK_n'event and CLK_n = '0' then if MCycle = "001" then if TState = "001" then RD <= IntCycle_n; MREQ <= IntCycle_n; IORQ_n_i <= IntCycle_n; end if; if TState = "011" then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '1'; end if; if TState = "100" then MREQ <= '0'; end if; else if TState = "001" and NoRead = '0' then RD <= not Write; IORQ_n_i <= not IORQ; MREQ <= not IORQ; end if; if TState = "011" then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '0'; end if; end if; end if; end process; end;
-- ** -- T80(b) core. In an effort to merge and maintain bug fixes .... -- -- -- Ver 300 started tidyup -- MikeJ March 2005 -- Latest version from www.fpgaarcade.com (original www.opencores.org) -- -- ** -- -- Z80 compatible microprocessor core, asynchronous top level -- -- Version : 0247 -- -- Copyright (c) 2001-2002 Daniel Wallner ([email protected]) -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Please report bugs to the author, but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- -- The latest version of this file can be found at: -- http://www.opencores.org/cvsweb.shtml/t80/ -- -- Limitations : -- -- File history : -- -- 0208 : First complete release -- -- 0211 : Fixed interrupt cycle -- -- 0235 : Updated for T80 interface change -- -- 0238 : Updated for T80 interface change -- -- 0240 : Updated for T80 interface change -- -- 0242 : Updated for T80 interface change -- -- 0247 : Fixed bus req/ack cycle -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.T80_Pack.all; entity T80a is generic( Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB ); port( RESET_n : in std_logic; CLK_n : in std_logic; WAIT_n : in std_logic; INT_n : in std_logic; NMI_n : in std_logic; BUSRQ_n : in std_logic; M1_n : out std_logic; MREQ_n : out std_logic; IORQ_n : out std_logic; RD_n : out std_logic; WR_n : out std_logic; RFSH_n : out std_logic; HALT_n : out std_logic; BUSAK_n : out std_logic; A : out std_logic_vector(15 downto 0); D : inout std_logic_vector(7 downto 0); D_I : in std_logic_vector(7 downto 0); D_O : out std_logic_vector(7 downto 0); ResetPC : in std_logic_vector(15 downto 0); ResetSP : in std_logic_vector(15 downto 0) ); end T80a; architecture rtl of T80a is signal CEN : std_logic; signal Reset_s : std_logic; signal IntCycle_n : std_logic; signal IORQ : std_logic; signal NoRead : std_logic; signal Write : std_logic; signal MREQ : std_logic; signal MReq_Inhibit : std_logic; signal Req_Inhibit : std_logic; signal RD : std_logic; signal MREQ_n_i : std_logic; signal IORQ_n_i : std_logic; signal RD_n_i : std_logic; signal WR_n_i : std_logic; signal RFSH_n_i : std_logic; signal BUSAK_n_i : std_logic; signal A_i : std_logic_vector(15 downto 0); signal DO : std_logic_vector(7 downto 0); signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser signal Wait_s : std_logic; signal MCycle : std_logic_vector(2 downto 0); signal TState : std_logic_vector(2 downto 0); begin CEN <= '1'; BUSAK_n <= BUSAK_n_i; MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit); RD_n_i <= not RD or Req_Inhibit; MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z'; IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z'; RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z'; WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z'; RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z'; A <= A_i when BUSAK_n_i = '1' else (others => 'Z'); D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); D_O <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); process (RESET_n, CLK_n) begin if RESET_n = '0' then Reset_s <= '0'; elsif CLK_n'event and CLK_n = '1' then Reset_s <= '1'; end if; end process; u0 : T80 generic map( Mode => Mode, IOWait => 1) port map( CEN => CEN, M1_n => M1_n, IORQ => IORQ, NoRead => NoRead, Write => Write, RFSH_n => RFSH_n_i, HALT_n => HALT_n, WAIT_n => Wait_s, INT_n => INT_n, NMI_n => NMI_n, RESET_n => Reset_s, BUSRQ_n => BUSRQ_n, BUSAK_n => BUSAK_n_i, CLK_n => CLK_n, A => A_i, DInst => D_I, -- D -> D_I DI => DI_Reg, DO => DO, MC => MCycle, TS => TState, IntCycle_n => IntCycle_n, ResetPC => ResetPC, ResetSP => ResetSP ); process (CLK_n) begin if CLK_n'event and CLK_n = '0' then Wait_s <= WAIT_n; if TState = "011" and BUSAK_n_i = '1' then DI_Reg <= to_x01(D_I); -- D -> D_I end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then WR_n_i <= '1'; elsif CLK_n'event and CLK_n = '1' then WR_n_i <= '1'; if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!! WR_n_i <= not Write; end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then Req_Inhibit <= '0'; elsif CLK_n'event and CLK_n = '1' then if MCycle = "001" and TState = "010" then Req_Inhibit <= '1'; else Req_Inhibit <= '0'; end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then MReq_Inhibit <= '0'; elsif CLK_n'event and CLK_n = '0' then if MCycle = "001" and TState = "010" then MReq_Inhibit <= '1'; else MReq_Inhibit <= '0'; end if; end if; end process; process(Reset_s,CLK_n) begin if Reset_s = '0' then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '0'; elsif CLK_n'event and CLK_n = '0' then if MCycle = "001" then if TState = "001" then RD <= IntCycle_n; MREQ <= IntCycle_n; IORQ_n_i <= IntCycle_n; end if; if TState = "011" then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '1'; end if; if TState = "100" then MREQ <= '0'; end if; else if TState = "001" and NoRead = '0' then RD <= not Write; IORQ_n_i <= not IORQ; MREQ <= not IORQ; end if; if TState = "011" then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '0'; end if; end if; end if; end process; end;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7.1 Core - Top-level core wrapper -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: ram_16x1k_sp_exdes.vhd -- -- Description: -- This is the actual BMG core wrapper. -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: August 31, 2005 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY UNISIM; USE UNISIM.VCOMPONENTS.ALL; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- ENTITY ram_16x1k_sp_exdes IS PORT ( --Inputs - Port A ENA : IN STD_LOGIC; --opt port WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); CLKA : IN STD_LOGIC ); END ram_16x1k_sp_exdes; ARCHITECTURE xilinx OF ram_16x1k_sp_exdes IS COMPONENT BUFG IS PORT ( I : IN STD_ULOGIC; O : OUT STD_ULOGIC ); END COMPONENT; COMPONENT ram_16x1k_sp IS PORT ( --Port A ENA : IN STD_LOGIC; --opt port WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); CLKA : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA_buf : STD_LOGIC; SIGNAL CLKB_buf : STD_LOGIC; SIGNAL S_ACLK_buf : STD_LOGIC; BEGIN bufg_A : BUFG PORT MAP ( I => CLKA, O => CLKA_buf ); bmg0 : ram_16x1k_sp PORT MAP ( --Port A ENA => ENA, WEA => WEA, ADDRA => ADDRA, DINA => DINA, DOUTA => DOUTA, CLKA => CLKA_buf ); END xilinx;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: ahb2avl_async -- File: ahb2avl_async.vhd -- Author: Magnus Hjorth - Aeroflex Gaisler -- Description: Asynchronous AHB to Avalon-MM interface based on ddr2spa -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; library gaisler; use gaisler.ddrpkg.all; use gaisler.ddrintpkg.all; entity ahb2avl_async is generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#f00#; burstlen : integer := 8; nosync : integer := 0; ahbbits : integer := ahbdw; avldbits : integer := 32; avlabits : integer := 20 ); port ( rst_ahb : in std_ulogic; clk_ahb : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; rst_avl : in std_ulogic; clk_avl : in std_ulogic; avlsi : out ddravl_slv_in_type; avlso : in ddravl_slv_out_type ); end; architecture struct of ahb2avl_async is constant l2blen: integer := log2(burstlen)+log2(32); constant l2ddrw: integer := log2(avldbits); constant l2ahbw: integer := log2(ahbbits); -- Write buffer dimensions constant wbuf_rabits_s: integer := 1+l2blen-l2ddrw; constant wbuf_rabits_r: integer := wbuf_rabits_s; constant wbuf_rdbits: integer := avldbits; constant wbuf_wabits: integer := 1+l2blen-5; constant wbuf_wdbits: integer := ahbbits; -- Read buffer dimensions constant rbuf_rabits: integer := l2blen-l2ahbw; constant rbuf_rdbits: integer := wbuf_wdbits; constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen32)/(2ddrbits)); constant rbuf_wdbits: integer := avldbits; signal request : ddr_request_type; signal start_tog : std_ulogic; signal response : ddr_response_type; signal wbwaddr: std_logic_vector(wbuf_wabits-1 downto 0); signal wbwdata: std_logic_vector(wbuf_wdbits-1 downto 0); signal wbraddr: std_logic_vector(wbuf_rabits_s-1 downto 0); signal wbrdata: std_logic_vector(wbuf_rdbits-1 downto 0); signal rbwaddr: std_logic_vector(rbuf_wabits-1 downto 0); signal rbwdata: std_logic_vector(rbuf_wdbits-1 downto 0); signal rbraddr: std_logic_vector(rbuf_rabits-1 downto 0); signal rbrdata: std_logic_vector(rbuf_rdbits-1 downto 0); signal wbwrite,wbwritebig,rbwrite: std_ulogic; signal gnd: std_logic_vector(3 downto 0); signal vcc: std_ulogic; begin gnd <= (others => '0'); vcc <= '1'; fe0: ddr2spax_ahb generic map ( hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => 0, iomask => 0, burstlen => burstlen, nosync => nosync, ahbbits => ahbbits, devid => GAISLER_AHB2AVLA, ddrbits => avldbits/2 ) port map ( rst => rst_ahb, clk_ahb => clk_ahb, ahbsi => ahbsi, ahbso => ahbso, request => request, start_tog => start_tog, response => response, wbwaddr => wbwaddr, wbwdata => wbwdata, wbwrite => wbwrite, wbwritebig => wbwritebig, rbraddr => rbraddr, rbrdata => rbrdata, hwidth => gnd(0), beid => gnd(3 downto 0) ); be0: ahb2avl_async_be generic map ( avldbits => avldbits, avlabits => avlabits, ahbbits => ahbbits, burstlen => burstlen, nosync => nosync ) port map ( rst => rst_avl, clk => clk_avl, avlsi => avlsi, avlso => avlso, request => request, start_tog => start_tog, response => response, wbraddr => wbraddr, wbrdata => wbrdata, rbwaddr => rbwaddr, rbwdata => rbwdata, rbwrite => rbwrite ); wbuf: ddr2buf generic map (tech => 0, wabits => wbuf_wabits, wdbits => wbuf_wdbits, rabits => wbuf_rabits_r, rdbits => wbuf_rdbits, sepclk => 1, wrfst => 0) port map ( rclk => clk_avl, renable => vcc, raddress => wbraddr(wbuf_rabits_r-1 downto 0), dataout => wbrdata, wclk => clk_ahb, write => wbwrite, writebig => wbwritebig, waddress => wbwaddr, datain => wbwdata); rbuf: ddr2buf generic map (tech => 0, wabits => rbuf_wabits, wdbits => rbuf_wdbits, rabits => rbuf_rabits, rdbits => rbuf_rdbits, sepclk => 1, wrfst => 0) port map ( rclk => clk_ahb, renable => vcc, raddress => rbraddr, dataout => rbrdata, wclk => clk_avl, write => rbwrite, writebig => '0', waddress => rbwaddr, datain => rbwdata); end;
library IEEE; use IEEE.Std_Logic_1164.all; entity C3 is port (A: in std_logic; B: in std_logic; C: in std_logic; F: out std_logic ); end C3; architecture c3_estr of C3 is begin F <= (B or C) and (not A); end c3_estr;
-- SIMON 64/128 -- feistel round function -- Inner-round pipelining using negative-edge triggered registers -- -- @Author: Jos Wetzels -- @Author: Wouter Bokslag -- -- Parameters: -- v_in: plaintext block -- v_k: subkey -- v_out: ciphertext block -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity round_f is port(clk : in std_logic; rst : in std_logic; v_in : in std_logic_vector(63 downto 0); v_k : in std_logic_vector(31 downto 0); v_out : out std_logic_vector(63 downto 0) ); end round_f; architecture Behavioral of round_f is signal op_0_s : std_logic_vector(31 downto 0); signal stage_0_out_s : std_logic_vector(31 downto 0); signal op_1_s : std_logic_vector(31 downto 0); signal op_2_s : std_logic_vector(31 downto 0); component phi is port(x_in : in std_logic_vector(31 downto 0); x_out : out std_logic_vector(31 downto 0)); end component; component gamma is port(x_in : in std_logic_vector(31 downto 0); y_in : in std_logic_vector(31 downto 0); x_out : out std_logic_vector(31 downto 0)); end component; component neg_reg_32 is port(clk : in std_logic; rst : in std_logic; data_in : in std_logic_vector(31 downto 0); data_out : out std_logic_vector(31 downto 0)); end component; begin PHI_0 : phi port map (v_in(63 downto 32), op_0_s); GAMMA_0 : gamma port map (v_in(31 downto 0), v_k, op_1_s); REG_STAGE_0 : neg_reg_32 port map (clk, rst, op_1_s, stage_0_out_s); GAMMA_1 : gamma port map (op_0_s, stage_0_out_s, op_2_s); v_out <= op_2_s & v_in(63 downto 32); end Behavioral;
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity adder_AXI_CTRL_s_axi is generic ( C_ADDR_WIDTH : INTEGER := 6; C_DATA_WIDTH : INTEGER := 32); port ( -- axi4 lite slave signals ACLK :in STD_LOGIC; ARESET :in STD_LOGIC; ACLK_EN :in STD_LOGIC; AWADDR :in STD_LOGIC_VECTOR(C_ADDR_WIDTH-1 downto 0); AWVALID :in STD_LOGIC; AWREADY :out STD_LOGIC; WDATA :in STD_LOGIC_VECTOR(C_DATA_WIDTH-1 downto 0); WSTRB :in STD_LOGIC_VECTOR(C_DATA_WIDTH/8-1 downto 0); WVALID :in STD_LOGIC; WREADY :out STD_LOGIC; BRESP :out STD_LOGIC_VECTOR(1 downto 0); BVALID :out STD_LOGIC; BREADY :in STD_LOGIC; ARADDR :in STD_LOGIC_VECTOR(C_ADDR_WIDTH-1 downto 0); ARVALID :in STD_LOGIC; ARREADY :out STD_LOGIC; RDATA :out STD_LOGIC_VECTOR(C_DATA_WIDTH-1 downto 0); RRESP :out STD_LOGIC_VECTOR(1 downto 0); RVALID :out STD_LOGIC; RREADY :in STD_LOGIC; interrupt :out STD_LOGIC; -- user signals ap_start :out STD_LOGIC; ap_done :in STD_LOGIC; ap_ready :in STD_LOGIC; ap_idle :in STD_LOGIC; a :out STD_LOGIC_VECTOR(31 downto 0); b :out STD_LOGIC_VECTOR(31 downto 0); c :in STD_LOGIC_VECTOR(31 downto 0); c_ap_vld :in STD_LOGIC); end entity adder_AXI_CTRL_s_axi; --------------------------Address Info------------------- -- 0x00 : Control signals -- bit 0 - ap_start (Read/Write/SC) -- bit 1 - ap_done (Read/COR) -- bit 2 - ap_idle (Read) -- bit 3 - ap_ready (Read) -- bit 7 - auto_restart (Read/Write) -- others - reserved -- 0x04 : Global Interrupt Enable Register -- bit 0 - Global Interrupt Enable (Read/Write) -- others - reserved -- 0x08 : IP Interrupt Enable Register (Read/Write) -- bit 0 - Channel 0 (ap_done) -- others - reserved -- 0x0c : IP Interrupt Status Register (Read/TOW) -- bit 0 - Channel 0 (ap_done) -- others - reserved -- 0x10 : Data signal of a -- bit 31~0 - a[31:0] (Read/Write) -- 0x14 : reserved -- 0x18 : Data signal of b -- bit 31~0 - b[31:0] (Read/Write) -- 0x1c : reserved -- 0x20 : Data signal of c -- bit 31~0 - c[31:0] (Read) -- 0x24 : Control signal of c -- bit 0 - c_ap_vld (Read/COR) -- others - reserved -- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) architecture behave of adder_AXI_CTRL_s_axi is constant ADDR_BITS : INTEGER := 6; constant ADDR_AP_CTRL : INTEGER :=16#00#; constant ADDR_GIE : INTEGER :=16#04#; constant ADDR_IER : INTEGER :=16#08#; constant ADDR_ISR : INTEGER :=16#0c#; constant ADDR_A_DATA_0 : INTEGER :=16#10#; constant ADDR_A_CTRL : INTEGER :=16#14#; constant ADDR_B_DATA_0 : INTEGER :=16#18#; constant ADDR_B_CTRL : INTEGER :=16#1c#; constant ADDR_C_DATA_0 : INTEGER :=16#20#; constant ADDR_C_CTRL : INTEGER :=16#24#; type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write FSM states signal wstate, wnext, rstate, rnext: states; -- Local signal signal waddr : UNSIGNED(ADDR_BITS-1 downto 0); signal wmask : UNSIGNED(31 downto 0); signal aw_hs : STD_LOGIC; signal w_hs : STD_LOGIC; signal rdata_data : UNSIGNED(31 downto 0); signal ar_hs : STD_LOGIC; signal raddr : UNSIGNED(ADDR_BITS-1 downto 0); signal AWREADY_t : STD_LOGIC; signal WREADY_t : STD_LOGIC; signal ARREADY_t : STD_LOGIC; signal RVALID_t : STD_LOGIC; -- internal registers signal int_ap_idle : STD_LOGIC; signal int_ap_ready : STD_LOGIC; signal int_ap_done : STD_LOGIC; signal int_ap_start : STD_LOGIC; signal int_auto_restart : STD_LOGIC; signal int_gie : STD_LOGIC; signal int_ier : STD_LOGIC; signal int_isr : STD_LOGIC; signal int_a : UNSIGNED(31 downto 0); signal int_b : UNSIGNED(31 downto 0); signal int_c : UNSIGNED(31 downto 0); signal int_c_ap_vld : STD_LOGIC; begin -- axi write AWREADY_t <= '1' when wstate = wridle else '0'; AWREADY <= AWREADY_t; WREADY_t <= '1' when wstate = wrdata else '0'; WREADY <= WREADY_t; BRESP <= "00"; -- OKAY BVALID <= '1' when wstate = wrresp else '0'; wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0)); aw_hs <= AWVALID and AWREADY_t; w_hs <= WVALID and WREADY_t; -- write FSM process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (ARESET = '1') then wstate <= wridle; else wstate <= wnext; end if; end if; end process; process (wstate, AWVALID, WVALID, BREADY) begin case (wstate) is when wridle => if (AWVALID = '1') then wnext <= wrdata; else wnext <= wridle; end if; when wrdata => if (WVALID = '1') then wnext <= wrresp; else wnext <= wrdata; end if; when wrresp => if (BREADY = '1') then wnext <= wridle; else wnext <= wrresp; end if; when others => wnext <= wridle; end case; end process; waddr_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (aw_hs = '1') then waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)); end if; end if; end process; -- axi read ARREADY_t <= '1' when (rstate = rdidle) else '0'; ARREADY <= ARREADY_t; RDATA <= STD_LOGIC_VECTOR(rdata_data); RRESP <= "00"; -- OKAY RVALID_t <= '1' when (rstate = rddata) else '0'; RVALID <= RVALID_t; ar_hs <= ARVALID and ARREADY_t; raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0)); -- read FSM process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (ARESET = '1') then rstate <= rdidle; else rstate <= rnext; end if; end if; end process; process (rstate, ARVALID, RREADY, RVALID_t) begin case (rstate) is when rdidle => if (ARVALID = '1') then rnext <= rddata; else rnext <= rdidle; end if; when rddata => if (RREADY = '1' and RVALID_t = '1') then rnext <= rdidle; else rnext <= rddata; end if; when others => rnext <= rdidle; end case; end process; rdata_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (ar_hs = '1') then case (TO_INTEGER(raddr)) is when ADDR_AP_CTRL => rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0'); when ADDR_GIE => rdata_data <= (1 => int_gie, others => '0'); when ADDR_IER => rdata_data <= (1 => int_ier, others => '0'); when ADDR_ISR => rdata_data <= (1 => int_isr, others => '0'); when ADDR_A_DATA_0 => rdata_data <= RESIZE(int_a(31 downto 0), 32); when ADDR_B_DATA_0 => rdata_data <= RESIZE(int_b(31 downto 0), 32); when ADDR_C_DATA_0 => rdata_data <= RESIZE(int_c(31 downto 0), 32); when ADDR_C_CTRL => rdata_data <= (0 => int_c_ap_vld, others => '0'); when others => rdata_data <= (others => '0'); end case; end if; end if; end process; -- internal registers interrupt <= int_gie and int_isr; ap_start <= int_ap_start; int_ap_idle <= ap_idle; int_ap_ready <= ap_ready; a <= STD_LOGIC_VECTOR(int_a); b <= STD_LOGIC_VECTOR(int_b); process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_start <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then int_ap_start <= '1'; elsif (ap_done = '1' and int_auto_restart = '1') then int_ap_start <= '1'; -- auto restart else int_ap_start <= '0'; -- self clear end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_done <= '0'; elsif (ACLK_EN = '1') then if (ap_done = '1') then int_ap_done <= '1'; elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then int_ap_done <= '0'; -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_auto_restart <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then int_auto_restart <= WDATA(7); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_gie <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then int_gie <= WDATA(0); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ier <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then int_ier <= WDATA(0); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr <= '0'; elsif (ACLK_EN = '1') then if (int_ier = '1' and ap_done = '1') then int_isr <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr <= int_isr xor WDATA(0); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_A_DATA_0) then int_a(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_a(31 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_B_DATA_0) then int_b(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_b(31 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_c <= (others => '0'); elsif (ACLK_EN = '1') then if (c_ap_vld = '1') then int_c <= UNSIGNED(c); -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_c_ap_vld <= '0'; elsif (ACLK_EN = '1') then if (c_ap_vld = '1') then int_c_ap_vld <= '1'; elsif (ar_hs = '1' and raddr = ADDR_C_CTRL) then int_c_ap_vld <= '0'; -- clear on read end if; end if; end if; end process; end architecture behave;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package cu is -- Control unit input sizes constant OPCODE_SIZE : integer := 6; -- OPCODE field size constant FUNC_SIZE : integer := 11; -- FUNC field size subtype OPCODE_TYPE is std_logic_vector(OPCODE_SIZE - 1 downto 0); -- I-Type instructions constant ITYPE_ADD : OPCODE_TYPE := "001000"; constant ITYPE_AND : OPCODE_TYPE := "001100"; constant ITYPE_OR : OPCODE_TYPE := "001101"; constant ITYPE_SUB : OPCODE_TYPE := "001010"; constant ITYPE_XOR : OPCODE_TYPE := "001110"; constant ITYPE_SLL : OPCODE_TYPE := "010100"; constant ITYPE_SRL : OPCODE_TYPE := "010110"; constant ITYPE_SRA : OPCODE_TYPE := "010111"; constant ITYPE_SEQ : OPCODE_TYPE := "011000"; constant ITYPE_SNE : OPCODE_TYPE := "011001"; constant ITYPE_SGE : OPCODE_TYPE := "011101"; constant ITYPE_SGT : OPCODE_TYPE := "011011"; constant ITYPE_SLE : OPCODE_TYPE := "011100"; constant ITYPE_SLT : OPCODE_TYPE := "011010"; constant ITYPE_SGEU : OPCODE_TYPE := "111101"; constant ITYPE_SGTU : OPCODE_TYPE := "111011"; constant ITYPE_SLEU : OPCODE_TYPE := "111100"; constant ITYPE_SLTU : OPCODE_TYPE := "111010"; constant NOP : OPCODE_TYPE := "010101"; -- Jump [ OPCODE(6) - PCOFFSET(26) ] constant JTYPE_J : OPCODE_TYPE := "000010"; constant JTYPE_JAL : OPCODE_TYPE := "000011"; constant JTYPE_JR : OPCODE_TYPE := "010010"; -- Branch [ OPCODE(6) - REG(5) - PCOFFSET(21) ] constant BTYPE_BEQZ : OPCODE_TYPE := "000100"; constant BTYPE_BNEZ : OPCODE_TYPE := "000101"; -- Memory [ OPCODE(6) - RDISPLACEMENT(5) - REG(5) - DISPLACEMENT(16) ] constant MTYPE_LW : OPCODE_TYPE := "100011"; constant MTYPE_SW : OPCODE_TYPE := "101011"; -- R-Type instruction -> OPCODE field constant RTYPE : OPCODE_TYPE := "000000"; subtype FUNC_TYPE is std_logic_vector(FUNC_SIZE - 1 downto 0); -- R-Type instruction -> FUNC field constant RTYPE_ADD : FUNC_TYPE := "00000100000"; constant RTYPE_AND : FUNC_TYPE := "00000100100"; constant RTYPE_OR : FUNC_TYPE := "00000100101"; constant RTYPE_SUB : FUNC_TYPE := "00000100010"; constant RTYPE_XOR : FUNC_TYPE := "00000100110"; constant RTYPE_SLL : FUNC_TYPE := "00000000100"; constant RTYPE_SRL : FUNC_TYPE := "00000000110"; constant RTYPE_SRA : FUNC_TYPE := "00000000111"; constant RTYPE_SEQ : FUNC_TYPE := "00000101000"; constant RTYPE_SNE : FUNC_TYPE := "00000101001"; constant RTYPE_SGE : FUNC_TYPE := "00000101101"; constant RTYPE_SGT : FUNC_TYPE := "00000101011"; constant RTYPE_SLE : FUNC_TYPE := "00000101100"; constant RTYPE_SLT : FUNC_TYPE := "00000101010"; constant RTYPE_SGEU : FUNC_TYPE := "00000111101"; constant RTYPE_SGTU : FUNC_TYPE := "00000111011"; constant RTYPE_SLEU : FUNC_TYPE := "00000111100"; constant RTYPE_SLTU : FUNC_TYPE := "00000111010"; constant RTYPE_NOP : FUNC_TYPE := "00000000000"; end cu;
package STRSYN is attribute SigDir : string; attribute SigType : string; attribute SigBias : string; end STRSYN; entity sklp is port ( terminal in1: electrical; terminal out1: electrical; terminal vbias4: electrical; terminal gnd: electrical; terminal vdd: electrical; terminal vbias2: electrical; terminal vbias1: electrical; terminal vbias3: electrical; terminal vref: electrical); end sklp; architecture simple of sklp is -- Attributes for Ports attribute SigDir of in1:terminal is "input"; attribute SigType of in1:terminal is "voltage"; attribute SigDir of out1:terminal is "output"; attribute SigType of out1:terminal is "voltage"; attribute SigDir of vbias4:terminal is "reference"; attribute SigType of vbias4:terminal is "voltage"; attribute SigDir of gnd:terminal is "reference"; attribute SigType of gnd:terminal is "current"; attribute SigBias of gnd:terminal is "negative"; attribute SigDir of vdd:terminal is "reference"; attribute SigType of vdd:terminal is "current"; attribute SigBias of vdd:terminal is "positive"; attribute SigDir of vbias2:terminal is "reference"; attribute SigType of vbias2:terminal is "voltage"; attribute SigDir of vbias1:terminal is "reference"; attribute SigType of vbias1:terminal is "voltage"; attribute SigDir of vbias3:terminal is "reference"; attribute SigType of vbias3:terminal is "voltage"; attribute SigDir of vref:terminal is "reference"; attribute SigType of vref:terminal is "current"; attribute SigBias of vref:terminal is "negative"; terminal net1: electrical; terminal net2: electrical; terminal net3: electrical; terminal net4: electrical; terminal net5: electrical; terminal net6: electrical; terminal net7: electrical; terminal net8: electrical; terminal net9: electrical; terminal net10: electrical; begin subnet0_subnet0_subnet0_m1 : entity nmos(behave) generic map( L => Ldiff_0, Ldiff_0init => 1.15e-06, W => Wdiff_0, Wdiff_0init => 3.2e-06, scope => private ) port map( D => net3, G => net1, S => net5 ); subnet0_subnet0_subnet0_m2 : entity nmos(behave) generic map( L => Ldiff_0, Ldiff_0init => 1.15e-06, W => Wdiff_0, Wdiff_0init => 3.2e-06, scope => private ) port map( D => net2, G => out1, S => net5 ); subnet0_subnet0_subnet0_m3 : entity nmos(behave) generic map( L => LBias, LBiasinit => 8e-07, W => W_0, W_0init => 6.775e-05 ) port map( D => net5, G => vbias4, S => gnd ); subnet0_subnet0_subnet0_m4 : entity nmos(behave) generic map( L => Ldiff_0, Ldiff_0init => 1.15e-06, W => Wdiff_0, Wdiff_0init => 3.2e-06, scope => private ) port map( D => net6, G => net1, S => net5 ); subnet0_subnet0_subnet0_m5 : entity nmos(behave) generic map( L => Ldiff_0, Ldiff_0init => 1.15e-06, W => Wdiff_0, Wdiff_0init => 3.2e-06, scope => private ) port map( D => net6, G => out1, S => net5 ); subnet0_subnet0_subnet0_m6 : entity pmos(behave) generic map( L => Lcmdiffp_0, Lcmdiffp_0init => 9.5e-06, W => Wcmdiffp_0, Wcmdiffp_0init => 6.45e-06, scope => private ) port map( D => net6, G => net6, S => vdd ); subnet0_subnet0_subnet0_m7 : entity pmos(behave) generic map( L => Lcmdiffp_0, Lcmdiffp_0init => 9.5e-06, W => Wcmdiffp_0, Wcmdiffp_0init => 6.45e-06, scope => private ) port map( D => net6, G => net6, S => vdd ); subnet0_subnet0_subnet0_m8 : entity pmos(behave) generic map( L => Lcmdiffp_0, Lcmdiffp_0init => 9.5e-06, W => Wcmdiffp_0, Wcmdiffp_0init => 6.45e-06, scope => private ) port map( D => net2, G => net6, S => vdd ); subnet0_subnet0_subnet0_m9 : entity pmos(behave) generic map( L => Lcmdiffp_0, Lcmdiffp_0init => 9.5e-06, W => Wcmdiffp_0, Wcmdiffp_0init => 6.45e-06, scope => private ) port map( D => net3, G => net6, S => vdd ); subnet0_subnet0_subnet1_m1 : entity nmos(behave) generic map( L => Lsrc, Lsrcinit => 2.65e-06, W => Wsrc_2, Wsrc_2init => 1.22e-05, scope => Wprivate, symmetry_scope => sym_5 ) port map( D => net4, G => net2, S => gnd ); subnet0_subnet0_subnet2_m1 : entity nmos(behave) generic map( L => Lsrc, Lsrcinit => 2.65e-06, W => Wsrc_2, Wsrc_2init => 1.22e-05, scope => Wprivate, symmetry_scope => sym_5 ) port map( D => out1, G => net3, S => gnd ); subnet0_subnet0_subnet3_m1 : entity pmos(behave) generic map( L => LBias, LBiasinit => 8e-07, W => Wcmcasc_1, Wcmcasc_1init => 3.52e-05, scope => Wprivate ) port map( D => net4, G => vbias2, S => net7 ); subnet0_subnet0_subnet3_m2 : entity pmos(behave) generic map( L => Lcm_1, Lcm_1init => 6.5e-07, W => Wcm_1, Wcm_1init => 7.3e-06, scope => private ) port map( D => net7, G => net4, S => vdd ); subnet0_subnet0_subnet3_m3 : entity pmos(behave) generic map( L => Lcm_1, Lcm_1init => 6.5e-07, W => Wcmout_1, Wcmout_1init => 5.605e-05, scope => private ) port map( D => net8, G => net4, S => vdd ); subnet0_subnet0_subnet3_m4 : entity pmos(behave) generic map( L => LBias, LBiasinit => 8e-07, W => Wcmcasc_1, Wcmcasc_1init => 3.52e-05, scope => Wprivate ) port map( D => out1, G => vbias2, S => net8 ); subnet0_subnet1_subnet0_m1 : entity pmos(behave) generic map( L => LBias, LBiasinit => 8e-07, W => (pfak)(WBias), WBiasinit => 9.55e-06 ) port map( D => vbias1, G => vbias1, S => vdd ); subnet0_subnet1_subnet0_m2 : entity pmos(behave) generic map( L => (pfak)(LBias), LBiasinit => 8e-07, W => (pfak)(WBias), WBiasinit => 9.55e-06 ) port map( D => vbias2, G => vbias2, S => vbias1 ); subnet0_subnet1_subnet0_i1 : entity idc(behave) generic map( I => 1.145e-05 ) port map( P => vdd, N => vbias3 ); subnet0_subnet1_subnet0_m3 : entity nmos(behave) generic map( L => (pfak)(LBias), LBiasinit => 8e-07, W => WBias, WBiasinit => 9.55e-06 ) port map( D => vbias3, G => vbias3, S => vbias4 ); subnet0_subnet1_subnet0_m4 : entity nmos(behave) generic map( L => LBias, LBiasinit => 8e-07, W => WBias, WBiasinit => 9.55e-06 ) port map( D => vbias2, G => vbias3, S => net9 ); subnet0_subnet1_subnet0_m5 : entity nmos(behave) generic map( L => LBias, LBiasinit => 8e-07, W => WBias, WBiasinit => 9.55e-06 ) port map( D => vbias4, G => vbias4, S => gnd ); subnet0_subnet1_subnet0_m6 : entity nmos(behave) generic map( L => LBias, LBiasinit => 8e-07, W => WBias, WBiasinit => 9.55e-06 ) port map( D => net9, G => vbias4, S => gnd ); subnet1_subnet0_r1 : entity res(behave) generic map( R => 200000 ) port map( P => net10, N => in1 ); subnet1_subnet0_r2 : entity res(behave) generic map( R => 603000 ) port map( P => net10, N => net1 ); subnet1_subnet0_c2 : entity cap(behave) generic map( C => 1.07e-11 ) port map( P => net10, N => out1 ); subnet1_subnet0_c1 : entity cap(behave) generic map( C => 4e-12 ) port map( P => net1, N => vref ); end simple;
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.std_logic_misc.all; use work.component_pack.all; entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping generic ( DATA_WIDTH: integer := 32; current_address : integer := 0; Rxy_rst : integer := 10; Cx_rst : integer := 10; healthy_counter_threshold : integer := 8; faulty_counter_threshold: integer := 2; counter_depth: integer := 4; NoC_size: integer := 4 ); port ( reset, clk: in std_logic; RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0); credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic; valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic; valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic; credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic; TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0); Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic; Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic; -- should be connected to NI (Outputs for classified fault information) link_faults: out std_logic_vector(4 downto 0); turn_faults: out std_logic_vector(19 downto 0); Rxy_reconf_PE: in std_logic_vector(7 downto 0); Cx_reconf_PE: in std_logic_vector(3 downto 0); Reconfig_command : in std_logic; -- fault injector shift register with serial input signals TCK: in std_logic; SE: in std_logic; -- shift enable UE: in std_logic; -- update enable SI: in std_logic; -- serial Input SO: out std_logic; -- serial output ---- Outputs for non-classified fault information link_faults_async: out std_logic_vector(4 downto 0); turn_faults_async: out std_logic_vector(19 downto 0) ); end router_credit_based_PD_C_SHMU; architecture behavior of router_credit_based_PD_C_SHMU is ------------------------------- -- Added because of Checkers -- ------------------------------- --signal combined_error_signals: std_logic_vector(19 downto 0); -- Shall we only consider this for the 20 bits showing the turn faults or individual checkers ?! --signal shift_parallel_data: std_logic_vector(19 downto 0); ------------------------------- ------------------------------- signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0); -- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic; signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic; signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic; signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic; signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic; signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic; signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic; signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic; signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic; signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic; signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic; signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0); signal LBDR_Fault_N, LBDR_Fault_E, LBDR_Fault_W, LBDR_Fault_S, LBDR_Fault_L: std_logic; signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic; signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic; signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic; -- Signals related to link fault classification modules signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic; signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic; signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic; -- Signals related to Control part checkers fault classification modules signal Healthy_N2E_turn_fault, intermittent_N2E_turn_fault, faulty_N2E_turn_fault: std_logic; signal Healthy_N2W_turn_fault, intermittent_N2W_turn_fault, faulty_N2W_turn_fault: std_logic; signal Healthy_E2N_turn_fault, intermittent_E2N_turn_fault, faulty_E2N_turn_fault: std_logic; signal Healthy_E2S_turn_fault, intermittent_E2S_turn_fault, faulty_E2S_turn_fault: std_logic; signal Healthy_W2N_turn_fault, intermittent_W2N_turn_fault, faulty_W2N_turn_fault: std_logic; signal Healthy_W2S_turn_fault, intermittent_W2S_turn_fault, faulty_W2S_turn_fault: std_logic; signal Healthy_S2E_turn_fault, intermittent_S2E_turn_fault, faulty_S2E_turn_fault: std_logic; signal Healthy_S2W_turn_fault, intermittent_S2W_turn_fault, faulty_S2W_turn_fault: std_logic; signal Healthy_N2S_path_fault, intermittent_N2S_path_fault, faulty_N2S_path_fault: std_logic; signal Healthy_S2N_path_fault, intermittent_S2N_path_fault, faulty_S2N_path_fault: std_logic; signal Healthy_E2W_path_fault, intermittent_E2W_path_fault, faulty_E2W_path_fault: std_logic; signal Healthy_W2E_path_fault, intermittent_W2E_path_fault, faulty_W2E_path_fault: std_logic; signal Healthy_L2N_fault, intermittent_L2N_fault, faulty_L2N_fault: std_logic; signal Healthy_L2E_fault, intermittent_L2E_fault, faulty_L2E_fault: std_logic; signal Healthy_L2W_fault, intermittent_L2W_fault, faulty_L2W_fault: std_logic; signal Healthy_L2S_fault, intermittent_L2S_fault, faulty_L2S_fault: std_logic; signal Healthy_N2L_fault, intermittent_N2L_fault, faulty_N2L_fault: std_logic; signal Healthy_E2L_fault, intermittent_E2L_fault, faulty_E2L_fault: std_logic; signal Healthy_W2L_fault, intermittent_W2L_fault, faulty_W2L_fault: std_logic; signal Healthy_S2L_fault, intermittent_S2L_fault, faulty_S2L_fault: std_logic; -- Signals needed for control part checkers -- Signals needed for LBDR packet drop checkers -- North signal N_err_header_empty_Requests_FF_Requests_in, N_err_tail_Requests_in_all_zero, N_err_tail_empty_Requests_FF_Requests_in, N_err_tail_not_empty_not_grants_Requests_FF_Requests_in, N_err_grants_onehot, N_err_grants_mismatch, N_err_header_tail_Requests_FF_Requests_in, N_err_dst_addr_cur_addr_N1, N_err_dst_addr_cur_addr_not_N1, N_err_dst_addr_cur_addr_E1, N_err_dst_addr_cur_addr_not_E1, N_err_dst_addr_cur_addr_W1, N_err_dst_addr_cur_addr_not_W1, N_err_dst_addr_cur_addr_S1, N_err_dst_addr_cur_addr_not_S1, N_err_dst_addr_cur_addr_Req_L_in, N_err_dst_addr_cur_addr_not_Req_L_in, N_err_header_not_empty_faulty_drop_packet_in, -- added according to new design N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design N_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --N_err_header_not_empty_Req_L_in, -- added according to new design N_err_header_not_empty_Req_N_in, N_err_header_not_empty_Req_E_in, N_err_header_not_empty_Req_W_in, N_err_header_not_empty_Req_S_in, N_err_header_empty_packet_drop_in_packet_drop_equal, N_err_tail_not_empty_packet_drop_not_packet_drop_in, N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, N_err_packet_drop_order, N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- East E_err_header_empty_Requests_FF_Requests_in, E_err_tail_Requests_in_all_zero, E_err_tail_empty_Requests_FF_Requests_in, E_err_tail_not_empty_not_grants_Requests_FF_Requests_in, E_err_grants_onehot, E_err_grants_mismatch, E_err_header_tail_Requests_FF_Requests_in, E_err_dst_addr_cur_addr_N1, E_err_dst_addr_cur_addr_not_N1, E_err_dst_addr_cur_addr_E1, E_err_dst_addr_cur_addr_not_E1, E_err_dst_addr_cur_addr_W1, E_err_dst_addr_cur_addr_not_W1, E_err_dst_addr_cur_addr_S1, E_err_dst_addr_cur_addr_not_S1, E_err_dst_addr_cur_addr_Req_L_in, E_err_dst_addr_cur_addr_not_Req_L_in, E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --E_err_header_not_empty_Req_L_in, -- added according to new design E_err_header_not_empty_Req_N_in, E_err_header_not_empty_Req_E_in, E_err_header_not_empty_Req_W_in, E_err_header_not_empty_Req_S_in, E_err_header_empty_packet_drop_in_packet_drop_equal, E_err_tail_not_empty_packet_drop_not_packet_drop_in, E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, E_err_packet_drop_order, E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- West W_err_header_empty_Requests_FF_Requests_in, W_err_tail_Requests_in_all_zero, W_err_tail_empty_Requests_FF_Requests_in, W_err_tail_not_empty_not_grants_Requests_FF_Requests_in, W_err_grants_onehot, W_err_grants_mismatch, W_err_header_tail_Requests_FF_Requests_in, W_err_dst_addr_cur_addr_N1, W_err_dst_addr_cur_addr_not_N1, W_err_dst_addr_cur_addr_E1, W_err_dst_addr_cur_addr_not_E1, W_err_dst_addr_cur_addr_W1, W_err_dst_addr_cur_addr_not_W1, W_err_dst_addr_cur_addr_S1, W_err_dst_addr_cur_addr_not_S1, W_err_dst_addr_cur_addr_Req_L_in, W_err_dst_addr_cur_addr_not_Req_L_in, W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --W_err_header_not_empty_Req_L_in, -- added according to new design W_err_header_not_empty_Req_N_in, W_err_header_not_empty_Req_E_in, W_err_header_not_empty_Req_W_in, W_err_header_not_empty_Req_S_in, W_err_header_empty_packet_drop_in_packet_drop_equal, W_err_tail_not_empty_packet_drop_not_packet_drop_in, W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, W_err_packet_drop_order, W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- South S_err_header_empty_Requests_FF_Requests_in, S_err_tail_Requests_in_all_zero, S_err_tail_empty_Requests_FF_Requests_in, S_err_tail_not_empty_not_grants_Requests_FF_Requests_in, S_err_grants_onehot, S_err_grants_mismatch, S_err_header_tail_Requests_FF_Requests_in, S_err_dst_addr_cur_addr_N1, S_err_dst_addr_cur_addr_not_N1, S_err_dst_addr_cur_addr_E1, S_err_dst_addr_cur_addr_not_E1, S_err_dst_addr_cur_addr_W1, S_err_dst_addr_cur_addr_not_W1, S_err_dst_addr_cur_addr_S1, S_err_dst_addr_cur_addr_not_S1, S_err_dst_addr_cur_addr_Req_L_in, S_err_dst_addr_cur_addr_not_Req_L_in, S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --S_err_header_not_empty_Req_L_in, -- added according to new design S_err_header_not_empty_Req_N_in, S_err_header_not_empty_Req_E_in, S_err_header_not_empty_Req_W_in, S_err_header_not_empty_Req_S_in, S_err_header_empty_packet_drop_in_packet_drop_equal, S_err_tail_not_empty_packet_drop_not_packet_drop_in, S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, S_err_packet_drop_order, S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- Local L_err_header_empty_Requests_FF_Requests_in, L_err_tail_Requests_in_all_zero, L_err_tail_empty_Requests_FF_Requests_in, L_err_tail_not_empty_not_grants_Requests_FF_Requests_in, L_err_grants_onehot, L_err_grants_mismatch, L_err_header_tail_Requests_FF_Requests_in, L_err_dst_addr_cur_addr_N1, L_err_dst_addr_cur_addr_not_N1, L_err_dst_addr_cur_addr_E1, L_err_dst_addr_cur_addr_not_E1, L_err_dst_addr_cur_addr_W1, L_err_dst_addr_cur_addr_not_W1, L_err_dst_addr_cur_addr_S1, L_err_dst_addr_cur_addr_not_S1, L_err_dst_addr_cur_addr_Req_L_in, L_err_dst_addr_cur_addr_not_Req_L_in, L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --L_err_header_not_empty_Req_L_in, -- added according to new design L_err_header_not_empty_Req_N_in, L_err_header_not_empty_Req_E_in, L_err_header_not_empty_Req_W_in, L_err_header_not_empty_Req_S_in, L_err_header_empty_packet_drop_in_packet_drop_equal, L_err_tail_not_empty_packet_drop_not_packet_drop_in, L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, L_err_packet_drop_order, L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal: std_logic; ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ -- Signals needed for FIFO packet drop with fault classifier support checkers -- North -- Functional checkers signal N_err_empty_full, N_err_empty_read_en, N_err_full_write_en, N_err_state_in_onehot, N_err_read_pointer_in_onehot, N_err_write_pointer_in_onehot, -- Structural checkers N_err_write_en_write_pointer, N_err_not_write_en_write_pointer, N_err_read_pointer_write_pointer_not_empty, N_err_read_pointer_write_pointer_empty, N_err_read_pointer_write_pointer_not_full, N_err_read_pointer_write_pointer_full, N_err_read_pointer_increment, N_err_read_pointer_not_increment, N_err_write_en, N_err_not_write_en, N_err_not_write_en1, N_err_not_write_en2, N_err_read_en_mismatch, N_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! N_err_fake_credit_read_en_fake_credit_counter_in_increment, N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, N_err_fake_credit_read_en_credit_out, N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, N_err_state_out_Idle_not_fault_out_not_fake_credit, N_err_state_out_Idle_not_fault_out_not_fault_info_in, N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, N_err_state_out_Idle_fault_out_fake_credit, N_err_state_out_Idle_fault_out_state_in_Packet_drop, N_err_state_out_Idle_fault_out_fault_info_in, N_err_state_out_Idle_fault_out_faulty_packet_in, N_err_state_out_Idle_not_health_info, N_err_state_out_Idle_not_write_fake_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Header_flit_not_valid_in_not_fault_info_in, N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, N_err_state_out_Header_flit_or_Body_flit_not_fake_credit, N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, N_err_state_out_Body_flit_valid_in_not_fault_out_health_info, N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Body_flit_not_valid_in_not_fault_info_in, N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, N_err_state_out_Body_flit_valid_in_fault_out_not_health_info, N_err_state_out_Body_flit_valid_in_not_health_info, N_err_state_out_Body_flit_not_fake_credit, N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, N_err_state_out_Tail_flit_not_valid_in_state_in_Idle, N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, N_err_state_out_Tail_flit_not_valid_in_not_fake_credit, N_err_state_out_Tail_flit_not_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, N_err_fault_info_fault_info_out_equal, N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- East -- Functional checkers E_err_empty_full, E_err_empty_read_en, E_err_full_write_en, E_err_state_in_onehot, E_err_read_pointer_in_onehot, E_err_write_pointer_in_onehot, -- Structural checkers E_err_write_en_write_pointer, E_err_not_write_en_write_pointer, E_err_read_pointer_write_pointer_not_empty, E_err_read_pointer_write_pointer_empty, E_err_read_pointer_write_pointer_not_full, E_err_read_pointer_write_pointer_full, E_err_read_pointer_increment, E_err_read_pointer_not_increment, E_err_write_en, E_err_not_write_en, E_err_not_write_en1, E_err_not_write_en2, E_err_read_en_mismatch, E_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! E_err_fake_credit_read_en_fake_credit_counter_in_increment, E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, E_err_fake_credit_read_en_credit_out, E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, E_err_state_out_Idle_not_fault_out_not_fake_credit, E_err_state_out_Idle_not_fault_out_not_fault_info_in, E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, E_err_state_out_Idle_fault_out_fake_credit, E_err_state_out_Idle_fault_out_state_in_Packet_drop, E_err_state_out_Idle_fault_out_fault_info_in, E_err_state_out_Idle_fault_out_faulty_packet_in, E_err_state_out_Idle_not_health_info, E_err_state_out_Idle_not_write_fake_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Header_flit_not_valid_in_not_fault_info_in, E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, E_err_state_out_Header_flit_or_Body_flit_not_fake_credit, E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, E_err_state_out_Body_flit_valid_in_not_fault_out_health_info, E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Body_flit_not_valid_in_not_fault_info_in, E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, E_err_state_out_Body_flit_valid_in_fault_out_not_health_info, E_err_state_out_Body_flit_valid_in_not_health_info, E_err_state_out_Body_flit_not_fake_credit, E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, E_err_state_out_Tail_flit_not_valid_in_state_in_Idle, E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, E_err_state_out_Tail_flit_not_valid_in_not_fake_credit, E_err_state_out_Tail_flit_not_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, E_err_fault_info_fault_info_out_equal, E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- West -- Functional checkers W_err_empty_full, W_err_empty_read_en, W_err_full_write_en, W_err_state_in_onehot, W_err_read_pointer_in_onehot, W_err_write_pointer_in_onehot, -- Structural checkers W_err_write_en_write_pointer, W_err_not_write_en_write_pointer, W_err_read_pointer_write_pointer_not_empty, W_err_read_pointer_write_pointer_empty, W_err_read_pointer_write_pointer_not_full, W_err_read_pointer_write_pointer_full, W_err_read_pointer_increment, W_err_read_pointer_not_increment, W_err_write_en, W_err_not_write_en, W_err_not_write_en1, W_err_not_write_en2, W_err_read_en_mismatch, W_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! W_err_fake_credit_read_en_fake_credit_counter_in_increment, W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, W_err_fake_credit_read_en_credit_out, W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, W_err_state_out_Idle_not_fault_out_not_fake_credit, W_err_state_out_Idle_not_fault_out_not_fault_info_in, W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, W_err_state_out_Idle_fault_out_fake_credit, W_err_state_out_Idle_fault_out_state_in_Packet_drop, W_err_state_out_Idle_fault_out_fault_info_in, W_err_state_out_Idle_fault_out_faulty_packet_in, W_err_state_out_Idle_not_health_info, W_err_state_out_Idle_not_write_fake_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Header_flit_not_valid_in_not_fault_info_in, W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, W_err_state_out_Header_flit_or_Body_flit_not_fake_credit, W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, W_err_state_out_Body_flit_valid_in_not_fault_out_health_info, W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Body_flit_not_valid_in_not_fault_info_in, W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, W_err_state_out_Body_flit_valid_in_fault_out_not_health_info, W_err_state_out_Body_flit_valid_in_not_health_info, W_err_state_out_Body_flit_not_fake_credit, W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, W_err_state_out_Tail_flit_not_valid_in_state_in_Idle, W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, W_err_state_out_Tail_flit_not_valid_in_not_fake_credit, W_err_state_out_Tail_flit_not_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, W_err_fault_info_fault_info_out_equal, W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- South -- Functional checkers S_err_empty_full, S_err_empty_read_en, S_err_full_write_en, S_err_state_in_onehot, S_err_read_pointer_in_onehot, S_err_write_pointer_in_onehot, -- Structural checkers S_err_write_en_write_pointer, S_err_not_write_en_write_pointer, S_err_read_pointer_write_pointer_not_empty, S_err_read_pointer_write_pointer_empty, S_err_read_pointer_write_pointer_not_full, S_err_read_pointer_write_pointer_full, S_err_read_pointer_increment, S_err_read_pointer_not_increment, S_err_write_en, S_err_not_write_en, S_err_not_write_en1, S_err_not_write_en2, S_err_read_en_mismatch, S_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! S_err_fake_credit_read_en_fake_credit_counter_in_increment, S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, S_err_fake_credit_read_en_credit_out, S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, S_err_state_out_Idle_not_fault_out_not_fake_credit, S_err_state_out_Idle_not_fault_out_not_fault_info_in, S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, S_err_state_out_Idle_fault_out_fake_credit, S_err_state_out_Idle_fault_out_state_in_Packet_drop, S_err_state_out_Idle_fault_out_fault_info_in, S_err_state_out_Idle_fault_out_faulty_packet_in, S_err_state_out_Idle_not_health_info, S_err_state_out_Idle_not_write_fake_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Header_flit_not_valid_in_not_fault_info_in, S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, S_err_state_out_Header_flit_or_Body_flit_not_fake_credit, S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, S_err_state_out_Body_flit_valid_in_not_fault_out_health_info, S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Body_flit_not_valid_in_not_fault_info_in, S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, S_err_state_out_Body_flit_valid_in_fault_out_not_health_info, S_err_state_out_Body_flit_valid_in_not_health_info, S_err_state_out_Body_flit_not_fake_credit, S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, S_err_state_out_Tail_flit_not_valid_in_state_in_Idle, S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, S_err_state_out_Tail_flit_not_valid_in_not_fake_credit, S_err_state_out_Tail_flit_not_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, S_err_fault_info_fault_info_out_equal, S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- Local -- Functional checkers L_err_empty_full, L_err_empty_read_en, L_err_full_write_en, L_err_state_in_onehot, L_err_read_pointer_in_onehot, L_err_write_pointer_in_onehot, -- Structural checkers L_err_write_en_write_pointer, L_err_not_write_en_write_pointer, L_err_read_pointer_write_pointer_not_empty, L_err_read_pointer_write_pointer_empty, L_err_read_pointer_write_pointer_not_full, L_err_read_pointer_write_pointer_full, L_err_read_pointer_increment, L_err_read_pointer_not_increment, L_err_write_en, L_err_not_write_en, L_err_not_write_en1, L_err_not_write_en2, L_err_read_en_mismatch, L_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! L_err_fake_credit_read_en_fake_credit_counter_in_increment, L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, L_err_fake_credit_read_en_credit_out, L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, L_err_state_out_Idle_not_fault_out_not_fake_credit, L_err_state_out_Idle_not_fault_out_not_fault_info_in, L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, L_err_state_out_Idle_fault_out_fake_credit, L_err_state_out_Idle_fault_out_state_in_Packet_drop, L_err_state_out_Idle_fault_out_fault_info_in, L_err_state_out_Idle_fault_out_faulty_packet_in, L_err_state_out_Idle_not_health_info, L_err_state_out_Idle_not_write_fake_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Header_flit_not_valid_in_not_fault_info_in, L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, L_err_state_out_Header_flit_or_Body_flit_not_fake_credit, L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, L_err_state_out_Body_flit_valid_in_not_fault_out_health_info, L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Body_flit_not_valid_in_not_fault_info_in, L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, L_err_state_out_Body_flit_valid_in_fault_out_not_health_info, L_err_state_out_Body_flit_valid_in_not_health_info, L_err_state_out_Body_flit_not_fake_credit, L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, L_err_state_out_Tail_flit_not_valid_in_state_in_Idle, L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, L_err_state_out_Tail_flit_not_valid_in_not_fake_credit, L_err_state_out_Tail_flit_not_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, L_err_fault_info_fault_info_out_equal, L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in: std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Signals needed for Allocator unit -- Allocator logic checker outputs -- Might need to be changed ?! signal err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N, err_grant_N_E_sig_not_empty_E_grant_N_E, err_not_grant_N_E_sig_or_empty_E_not_grant_N_E, err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W, err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S, err_grant_N_L_sig_not_empty_L_grant_N_L, err_not_grant_N_L_sig_or_empty_L_not_grant_N_L, err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N, err_grant_E_E_sig_not_empty_E_grant_E_E, err_not_grant_E_E_sig_or_empty_E_not_grant_E_E, err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W, err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S, err_grant_E_L_sig_not_empty_L_grant_E_L, err_not_grant_E_L_sig_or_empty_L_not_grant_E_L, err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N, err_grant_W_E_sig_not_empty_E_grant_W_E, err_not_grant_W_E_sig_or_empty_E_not_grant_W_E, err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W, err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S, err_grant_W_L_sig_not_empty_L_grant_W_L, err_not_grant_W_L_sig_or_empty_L_not_grant_W_L, err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N, err_grant_S_E_sig_not_empty_E_grant_S_E, err_not_grant_S_E_sig_or_empty_E_not_grant_S_E, err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W, err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S, err_grant_S_L_sig_not_empty_L_grant_S_L, err_not_grant_S_L_sig_or_empty_L_not_grant_S_L, err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N, err_grant_L_E_sig_not_empty_E_grant_L_E, err_not_grant_L_E_sig_or_empty_E_not_grant_L_E, err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W, err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S, err_grant_L_L_sig_not_empty_L_grant_L_L, err_not_grant_L_L_sig_or_empty_L_not_grant_L_L, err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N, err_grant_signals_not_empty_grant_E, err_not_grant_signals_empty_not_grant_E, err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W, err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S, err_grant_signals_not_empty_grant_L, err_not_grant_signals_empty_not_grant_L, err_grants_valid_not_match: std_logic; -- Allocator credit_counter logic checker outputs signal err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment, err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement, err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change, err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment, err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement, err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change, err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment, err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement, err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change, err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment, err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement, err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change, err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment, err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement, err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change, err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Arbiter_in Checker signals (part of allocator unit) -- North Arbiter_in checker outputs signal N_err_Requests_state_in_state_not_equal, N_err_IDLE_Req_N, N_err_IDLE_grant_N,N_err_North_Req_N, N_err_North_grant_N, N_err_East_Req_E, N_err_East_grant_E, N_err_West_Req_W, N_err_West_grant_W, N_err_South_Req_S,N_err_South_grant_S,N_err_Local_Req_L, N_err_Local_grant_L, N_err_IDLE_Req_E, N_err_IDLE_grant_E, N_err_North_Req_E, N_err_North_grant_E, N_err_East_Req_W, N_err_East_grant_W, N_err_West_Req_S, N_err_West_grant_S, N_err_South_Req_L, N_err_South_grant_L, N_err_Local_Req_N, N_err_Local_grant_N, N_err_IDLE_Req_W, N_err_IDLE_grant_W, N_err_North_Req_W, N_err_North_grant_W, N_err_East_Req_S, N_err_East_grant_S, N_err_West_Req_L, N_err_West_grant_L, N_err_South_Req_N, N_err_South_grant_N, N_err_Local_Req_E, N_err_Local_grant_E, N_err_IDLE_Req_S, N_err_IDLE_grant_S, N_err_North_Req_S, N_err_North_grant_S, N_err_East_Req_L, N_err_East_grant_L, N_err_West_Req_N, N_err_West_grant_N, N_err_South_Req_E, N_err_South_grant_E, N_err_Local_Req_W, N_err_Local_grant_W, N_err_IDLE_Req_L, N_err_IDLE_grant_L, N_err_North_Req_L, N_err_North_grant_L, N_err_East_Req_N, N_err_East_grant_N, N_err_West_Req_E, N_err_West_grant_E, N_err_South_Req_W, N_err_South_grant_W, N_err_Local_Req_S, N_err_Local_grant_S, N_err_arbiter_state_in_onehot, N_err_no_request_grants, N_err_request_no_grants, N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L, -- East Arbiter_in checker outputs E_err_Requests_state_in_state_not_equal, E_err_IDLE_Req_N, E_err_IDLE_grant_N, E_err_North_Req_N, E_err_North_grant_N, E_err_East_Req_E, E_err_East_grant_E, E_err_West_Req_W, E_err_West_grant_W, E_err_South_Req_S, E_err_South_grant_S, E_err_Local_Req_L, E_err_Local_grant_L, E_err_IDLE_Req_E, E_err_IDLE_grant_E, E_err_North_Req_E, E_err_North_grant_E, E_err_East_Req_W, E_err_East_grant_W, E_err_West_Req_S, E_err_West_grant_S, E_err_South_Req_L, E_err_South_grant_L, E_err_Local_Req_N, E_err_Local_grant_N, E_err_IDLE_Req_W, E_err_IDLE_grant_W, E_err_North_Req_W, E_err_North_grant_W, E_err_East_Req_S, E_err_East_grant_S, E_err_West_Req_L, E_err_West_grant_L, E_err_South_Req_N, E_err_South_grant_N, E_err_Local_Req_E, E_err_Local_grant_E, E_err_IDLE_Req_S, E_err_IDLE_grant_S, E_err_North_Req_S, E_err_North_grant_S, E_err_East_Req_L, E_err_East_grant_L, E_err_West_Req_N, E_err_West_grant_N, E_err_South_Req_E, E_err_South_grant_E, E_err_Local_Req_W, E_err_Local_grant_W, E_err_IDLE_Req_L, E_err_IDLE_grant_L, E_err_North_Req_L, E_err_North_grant_L, E_err_East_Req_N, E_err_East_grant_N, E_err_West_Req_E, E_err_West_grant_E, E_err_South_Req_W, E_err_South_grant_W, E_err_Local_Req_S, E_err_Local_grant_S, E_err_arbiter_state_in_onehot, E_err_no_request_grants, E_err_request_no_grants, E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L, -- West Arbiter_in checker outputs W_err_Requests_state_in_state_not_equal, W_err_IDLE_Req_N, W_err_IDLE_grant_N, W_err_North_Req_N, W_err_North_grant_N, W_err_East_Req_E, W_err_East_grant_E, W_err_West_Req_W, W_err_West_grant_W, W_err_South_Req_S, W_err_South_grant_S, W_err_Local_Req_L, W_err_Local_grant_L, W_err_IDLE_Req_E, W_err_IDLE_grant_E, W_err_North_Req_E, W_err_North_grant_E, W_err_East_Req_W, W_err_East_grant_W, W_err_West_Req_S, W_err_West_grant_S, W_err_South_Req_L, W_err_South_grant_L, W_err_Local_Req_N, W_err_Local_grant_N, W_err_IDLE_Req_W, W_err_IDLE_grant_W, W_err_North_Req_W, W_err_North_grant_W, W_err_East_Req_S, W_err_East_grant_S, W_err_West_Req_L, W_err_West_grant_L, W_err_South_Req_N, W_err_South_grant_N, W_err_Local_Req_E, W_err_Local_grant_E, W_err_IDLE_Req_S, W_err_IDLE_grant_S, W_err_North_Req_S, W_err_North_grant_S, W_err_East_Req_L, W_err_East_grant_L, W_err_West_Req_N, W_err_West_grant_N, W_err_South_Req_E, W_err_South_grant_E, W_err_Local_Req_W, W_err_Local_grant_W, W_err_IDLE_Req_L, W_err_IDLE_grant_L, W_err_North_Req_L, W_err_North_grant_L, W_err_East_Req_N, W_err_East_grant_N, W_err_West_Req_E, W_err_West_grant_E, W_err_South_Req_W, W_err_South_grant_W, W_err_Local_Req_S, W_err_Local_grant_S, W_err_arbiter_state_in_onehot, W_err_no_request_grants, W_err_request_no_grants, W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L, -- South Arbiter_in checker outputs S_err_Requests_state_in_state_not_equal, S_err_IDLE_Req_N, S_err_IDLE_grant_N,S_err_North_Req_N, S_err_North_grant_N, S_err_East_Req_E, S_err_East_grant_E, S_err_West_Req_W, S_err_West_grant_W, S_err_South_Req_S,S_err_South_grant_S,S_err_Local_Req_L, S_err_Local_grant_L, S_err_IDLE_Req_E, S_err_IDLE_grant_E, S_err_North_Req_E, S_err_North_grant_E, S_err_East_Req_W, S_err_East_grant_W, S_err_West_Req_S, S_err_West_grant_S, S_err_South_Req_L, S_err_South_grant_L, S_err_Local_Req_N, S_err_Local_grant_N, S_err_IDLE_Req_W, S_err_IDLE_grant_W, S_err_North_Req_W, S_err_North_grant_W, S_err_East_Req_S, S_err_East_grant_S, S_err_West_Req_L, S_err_West_grant_L, S_err_South_Req_N, S_err_South_grant_N, S_err_Local_Req_E, S_err_Local_grant_E, S_err_IDLE_Req_S, S_err_IDLE_grant_S, S_err_North_Req_S, S_err_North_grant_S, S_err_East_Req_L, S_err_East_grant_L, S_err_West_Req_N, S_err_West_grant_N, S_err_South_Req_E, S_err_South_grant_E, S_err_Local_Req_W, S_err_Local_grant_W, S_err_IDLE_Req_L, S_err_IDLE_grant_L, S_err_North_Req_L, S_err_North_grant_L, S_err_East_Req_N, S_err_East_grant_N, S_err_West_Req_E, S_err_West_grant_E, S_err_South_Req_W, S_err_South_grant_W, S_err_Local_Req_S, S_err_Local_grant_S, S_err_arbiter_state_in_onehot, S_err_no_request_grants, S_err_request_no_grants, S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L, -- Local Arbiter_in checker outputs L_err_Requests_state_in_state_not_equal, L_err_IDLE_Req_N, L_err_IDLE_grant_N,L_err_North_Req_N, L_err_North_grant_N, L_err_East_Req_E, L_err_East_grant_E, L_err_West_Req_W, L_err_West_grant_W, L_err_South_Req_S,L_err_South_grant_S, L_err_Local_Req_L, L_err_Local_grant_L, L_err_IDLE_Req_E, L_err_IDLE_grant_E, L_err_North_Req_E, L_err_North_grant_E, L_err_East_Req_W, L_err_East_grant_W, L_err_West_Req_S, L_err_West_grant_S, L_err_South_Req_L, L_err_South_grant_L, L_err_Local_Req_N, L_err_Local_grant_N, L_err_IDLE_Req_W, L_err_IDLE_grant_W, L_err_North_Req_W, L_err_North_grant_W, L_err_East_Req_S, L_err_East_grant_S, L_err_West_Req_L, L_err_West_grant_L, L_err_South_Req_N, L_err_South_grant_N, L_err_Local_Req_E, L_err_Local_grant_E, L_err_IDLE_Req_S, L_err_IDLE_grant_S, L_err_North_Req_S, L_err_North_grant_S, L_err_East_Req_L, L_err_East_grant_L, L_err_West_Req_N, L_err_West_grant_N, L_err_South_Req_E, L_err_South_grant_E, L_err_Local_Req_W, L_err_Local_grant_W, L_err_IDLE_Req_L, L_err_IDLE_grant_L, L_err_North_Req_L, L_err_North_grant_L, L_err_East_Req_N, L_err_East_grant_N, L_err_West_Req_E, L_err_West_grant_E, L_err_South_Req_W, L_err_South_grant_W, L_err_Local_Req_S, L_err_Local_grant_S, L_err_arbiter_state_in_onehot, L_err_no_request_grants, L_err_request_no_grants, L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S, L_err_no_Req_L_grant_L : std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Arbiter_out Checker signals (part of allocator unit) -- North Arbiter_out checker outputs signal N_arbiter_out_err_Requests_state_in_state_not_equal, N_err_IDLE_req_X_N, N_err_North_req_X_N, N_err_North_credit_not_zero_req_X_N_grant_N, N_err_North_credit_zero_or_not_req_X_N_not_grant_N, N_err_East_req_X_E, N_err_East_credit_not_zero_req_X_E_grant_E, N_err_East_credit_zero_or_not_req_X_E_not_grant_E, N_err_West_req_X_W, N_err_West_credit_not_zero_req_X_W_grant_W, N_err_West_credit_zero_or_not_req_X_W_not_grant_W, N_err_South_req_X_S, N_err_South_credit_not_zero_req_X_S_grant_S, N_err_South_credit_zero_or_not_req_X_S_not_grant_S, N_err_Local_req_X_L, N_err_Local_credit_not_zero_req_X_L_grant_L, N_err_Local_credit_zero_or_not_req_X_L_not_grant_L, N_err_IDLE_req_X_E, N_err_North_req_X_E, N_err_East_req_X_W, N_err_West_req_X_S, N_err_South_req_X_L, N_err_Local_req_X_N, N_err_IDLE_req_X_W, N_err_North_req_X_W, N_err_East_req_X_S, N_err_West_req_X_L, N_err_South_req_X_N, N_err_Local_req_X_E, N_err_IDLE_req_X_S, N_err_North_req_X_S, N_err_East_req_X_L, N_err_West_req_X_N, N_err_South_req_X_E, N_err_Local_req_X_W, N_err_IDLE_req_X_L, N_err_North_req_X_L, N_err_East_req_X_N, N_err_West_req_X_E, N_err_South_req_X_W, N_err_Local_req_X_S, N_arbiter_out_err_state_in_onehot, N_arbiter_out_err_no_request_grants, N_err_request_IDLE_state, N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant, N_err_state_West_Invalid_Grant, N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant, N_err_Grants_onehot_or_all_zero, -- East Arbiter_out checker outputs E_arbiter_out_err_Requests_state_in_state_not_equal, E_err_IDLE_req_X_N, E_err_North_req_X_N, E_err_North_credit_not_zero_req_X_N_grant_N, E_err_North_credit_zero_or_not_req_X_N_not_grant_N, E_err_East_req_X_E, E_err_East_credit_not_zero_req_X_E_grant_E, E_err_East_credit_zero_or_not_req_X_E_not_grant_E, E_err_West_req_X_W, E_err_West_credit_not_zero_req_X_W_grant_W, E_err_West_credit_zero_or_not_req_X_W_not_grant_W, E_err_South_req_X_S, E_err_South_credit_not_zero_req_X_S_grant_S, E_err_South_credit_zero_or_not_req_X_S_not_grant_S, E_err_Local_req_X_L, E_err_Local_credit_not_zero_req_X_L_grant_L, E_err_Local_credit_zero_or_not_req_X_L_not_grant_L, E_err_IDLE_req_X_E, E_err_North_req_X_E, E_err_East_req_X_W, E_err_West_req_X_S, E_err_South_req_X_L, E_err_Local_req_X_N, E_err_IDLE_req_X_W, E_err_North_req_X_W, E_err_East_req_X_S, E_err_West_req_X_L, E_err_South_req_X_N, E_err_Local_req_X_E, E_err_IDLE_req_X_S, E_err_North_req_X_S, E_err_East_req_X_L, E_err_West_req_X_N, E_err_South_req_X_E, E_err_Local_req_X_W, E_err_IDLE_req_X_L, E_err_North_req_X_L, E_err_East_req_X_N, E_err_West_req_X_E, E_err_South_req_X_W, E_err_Local_req_X_S, E_arbiter_out_err_state_in_onehot, E_arbiter_out_err_no_request_grants, E_err_request_IDLE_state, E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant, E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant, E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero, -- West Arbiter_out checker outputs W_arbiter_out_err_Requests_state_in_state_not_equal, W_err_IDLE_req_X_N, W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N, W_err_North_credit_zero_or_not_req_X_N_not_grant_N, W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E, W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W, W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S, W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L, W_err_IDLE_req_X_E, W_err_North_req_X_E, W_err_East_req_X_W, W_err_West_req_X_S, W_err_South_req_X_L, W_err_Local_req_X_N, W_err_IDLE_req_X_W, W_err_North_req_X_W, W_err_East_req_X_S, W_err_West_req_X_L, W_err_South_req_X_N, W_err_Local_req_X_E, W_err_IDLE_req_X_S, W_err_North_req_X_S, W_err_East_req_X_L, W_err_West_req_X_N, W_err_South_req_X_E, W_err_Local_req_X_W, W_err_IDLE_req_X_L, W_err_North_req_X_L, W_err_East_req_X_N, W_err_West_req_X_E, W_err_South_req_X_W, W_err_Local_req_X_S, W_arbiter_out_err_state_in_onehot, W_arbiter_out_err_no_request_grants, W_err_request_IDLE_state, W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant,W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant, W_err_state_South_Invalid_Grant,W_err_state_Local_Invalid_Grant, W_err_Grants_onehot_or_all_zero, -- South Arbiter_out checker outputs S_arbiter_out_err_Requests_state_in_state_not_equal, S_err_IDLE_req_X_N, S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N, S_err_North_credit_zero_or_not_req_X_N_not_grant_N, S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E, S_err_East_credit_zero_or_not_req_X_E_not_grant_E, S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W, S_err_West_credit_zero_or_not_req_X_W_not_grant_W, S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S, S_err_South_credit_zero_or_not_req_X_S_not_grant_S, S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L, S_err_Local_credit_zero_or_not_req_X_L_not_grant_L, S_err_IDLE_req_X_E, S_err_North_req_X_E, S_err_East_req_X_W, S_err_West_req_X_S, S_err_South_req_X_L, S_err_Local_req_X_N, S_err_IDLE_req_X_W, S_err_North_req_X_W, S_err_East_req_X_S, S_err_West_req_X_L, S_err_South_req_X_N, S_err_Local_req_X_E, S_err_IDLE_req_X_S, S_err_North_req_X_S, S_err_East_req_X_L, S_err_West_req_X_N, S_err_South_req_X_E, S_err_Local_req_X_W, S_err_IDLE_req_X_L, S_err_North_req_X_L, S_err_East_req_X_N, S_err_West_req_X_E, S_err_South_req_X_W, S_err_Local_req_X_S, S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state, S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant, S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero, -- Local Arbiter_out checker outputs L_arbiter_out_err_Requests_state_in_state_not_equal, L_err_IDLE_req_X_N, L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N, L_err_North_credit_zero_or_not_req_X_N_not_grant_N, L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E, L_err_East_credit_zero_or_not_req_X_E_not_grant_E, L_err_West_req_X_W, L_err_West_credit_not_zero_req_X_W_grant_W, L_err_West_credit_zero_or_not_req_X_W_not_grant_W, L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S, L_err_South_credit_zero_or_not_req_X_S_not_grant_S, L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L, L_err_Local_credit_zero_or_not_req_X_L_not_grant_L, L_err_IDLE_req_X_E, L_err_North_req_X_E, L_err_East_req_X_W, L_err_West_req_X_S, L_err_South_req_X_L, L_err_Local_req_X_N, L_err_IDLE_req_X_W, L_err_North_req_X_W, L_err_East_req_X_S, L_err_West_req_X_L, L_err_South_req_X_N, L_err_Local_req_X_E, L_err_IDLE_req_X_S, L_err_North_req_X_S, L_err_East_req_X_L, L_err_West_req_X_N, L_err_South_req_X_E, L_err_Local_req_X_W, L_err_IDLE_req_X_L, L_err_North_req_X_L, L_err_East_req_X_N, L_err_West_req_X_E, L_err_South_req_X_W, L_err_Local_req_X_S, L_arbiter_out_err_state_in_onehot, L_arbiter_out_err_no_request_grants, L_err_request_IDLE_state, L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant,L_err_state_East_Invalid_Grant, L_err_state_West_Invalid_Grant, L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant, L_err_Grants_onehot_or_all_zero : std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Signals needed for grouping checkers to model turn/path faults signal N_FIFO_checkers_ORed, E_FIFO_checkers_ORed, W_FIFO_checkers_ORed, S_FIFO_checkers_ORed, L_FIFO_checkers_ORed : std_logic; signal N2E_turn_fault, N2W_turn_fault, E2N_turn_fault, E2S_turn_fault, W2N_turn_fault, W2S_turn_fault, S2E_turn_fault, S2W_turn_fault : std_logic; signal N2S_path_fault, S2N_path_fault, E2W_path_fault, W2E_path_fault : std_logic; signal not_N2E_turn_fault, not_N2W_turn_fault, not_E2N_turn_fault, not_E2S_turn_fault, not_W2N_turn_fault, not_W2S_turn_fault, not_S2E_turn_fault, not_S2W_turn_fault : std_logic; signal not_N2S_path_fault, not_S2N_path_fault, not_E2W_path_fault, not_W2E_path_fault : std_logic; signal L2N_fault, L2E_fault, L2W_fault, L2S_fault, N2L_fault, E2L_fault, W2L_fault, S2L_fault : std_logic; signal not_L2N_fault, not_L2E_fault, not_L2W_fault, not_L2S_fault, not_N2L_fault, not_E2L_fault, not_W2L_fault, not_S2L_fault : std_logic; -- Just used temporarily for debugging purposes! signal N_LBDR_checkers_ORed, E_LBDR_checkers_ORed, W_LBDR_checkers_ORed, S_LBDR_checkers_ORed, L_LBDR_checkers_ORed : std_logic; signal Allocator_checkers_ORed : std_logic; --signal turn_faults_sig : std_logic_vector(19 downto 0); ------------------------------------------------------------------------------------------------- -- Added because of the chain we make for sending faulty values --------------------------------- -- The chain is : L, N, E, W and S FIFO, then L, N, E, W and S LBDR, ---------------------------- -- then L, N, E, W and S Arbiter_in, -------------------- -- then L, N, E, W and S Arbiter_out and then Allocator's interlal logic ??!! -- ------------------------------------------------------------------------------------------------- --TODO: the chains should be fixed! --Fixed! signal fault_DO_serial_L_FIFO_to_N_FIFO, fault_DO_serial_N_FIFO_to_E_FIFO: std_logic; signal fault_DO_serial_E_FIFO_to_W_FIFO, fault_DO_serial_W_FIFO_to_S_FIFO: std_logic; signal fault_DO_serial_S_FIFO_to_L_LBDR, fault_DO_serial_L_LBDR_to_N_LBDR: std_logic; signal fault_DO_serial_N_LBDR_to_E_LBDR, fault_DO_serial_E_LBDR_to_W_LBDR: std_logic; signal fault_DO_serial_W_LBDR_to_S_LBDR, fault_DO_serial_S_LBDR_to_Allocator: std_logic; ------------------------------------------------------------------ ------------------------------------------------------------------ begin not_N2E_turn_fault <= not N2E_turn_fault; not_N2W_turn_fault <= not N2W_turn_fault; not_E2N_turn_fault <= not E2N_turn_fault; not_E2S_turn_fault <= not E2S_turn_fault; not_W2N_turn_fault <= not W2N_turn_fault; not_W2S_turn_fault <= not W2S_turn_fault; not_S2E_turn_fault <= not S2E_turn_fault; not_S2W_turn_fault <= not S2W_turn_fault; not_N2S_path_fault <= not N2S_path_fault; not_S2N_path_fault <= not S2N_path_fault; not_E2W_path_fault <= not E2W_path_fault; not_W2E_path_fault <= not W2E_path_fault; not_L2N_fault <= not L2N_fault; not_L2E_fault <= not L2E_fault; not_L2W_fault <= not L2W_fault; not_L2S_fault <= not L2S_fault; not_N2L_fault <= not N2L_fault; not_E2L_fault <= not E2L_fault; not_W2L_fault <= not W2L_fault; not_S2L_fault <= not S2L_fault; -- FIFO contributes to all turns and paths, therefore, for each turn or path (for the input direction), all the outputs of FIFO checkers -- corresponding to that input are ORed together. N_FIFO_checkers_ORed <= N_err_empty_full or N_err_empty_read_en or N_err_full_write_en or N_err_state_in_onehot or N_err_read_pointer_in_onehot or N_err_write_pointer_in_onehot or N_err_write_en_write_pointer or N_err_not_write_en_write_pointer or N_err_read_pointer_write_pointer_not_empty or N_err_read_pointer_write_pointer_empty or N_err_read_pointer_write_pointer_not_full or N_err_read_pointer_write_pointer_full or N_err_read_pointer_increment or N_err_read_pointer_not_increment or N_err_write_en or N_err_not_write_en or N_err_not_write_en1 or N_err_not_write_en2 or N_err_read_en_mismatch or N_err_read_en_mismatch1 or N_err_fake_credit_read_en_fake_credit_counter_in_increment or N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or N_err_fake_credit_read_en_credit_out or N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or N_err_state_out_Idle_not_fault_out_not_fake_credit or N_err_state_out_Idle_not_fault_out_not_fault_info_in or N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or N_err_state_out_Idle_fault_out_fake_credit or N_err_state_out_Idle_fault_out_state_in_Packet_drop or N_err_state_out_Idle_fault_out_fault_info_in or N_err_state_out_Idle_fault_out_faulty_packet_in or N_err_state_out_Idle_not_health_info or N_err_state_out_Idle_not_write_fake_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Header_flit_not_valid_in_not_fault_info_in or N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or N_err_state_out_Header_flit_or_Body_flit_not_fake_credit or N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or N_err_state_out_Body_flit_valid_in_not_fault_out_health_info or N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Body_flit_not_valid_in_not_fault_info_in or N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or N_err_state_out_Body_flit_valid_in_fault_out_not_health_info or N_err_state_out_Body_flit_valid_in_not_health_info or N_err_state_out_Body_flit_not_fake_credit or N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or N_err_state_out_Tail_flit_not_valid_in_state_in_Idle or N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or N_err_state_out_Tail_flit_not_valid_in_not_fake_credit or N_err_state_out_Tail_flit_not_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or N_err_fault_info_fault_info_out_equal or N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- East E_FIFO_checkers_ORed <= E_err_empty_full or E_err_empty_read_en or E_err_full_write_en or E_err_state_in_onehot or E_err_read_pointer_in_onehot or E_err_write_pointer_in_onehot or E_err_write_en_write_pointer or E_err_not_write_en_write_pointer or E_err_read_pointer_write_pointer_not_empty or E_err_read_pointer_write_pointer_empty or E_err_read_pointer_write_pointer_not_full or E_err_read_pointer_write_pointer_full or E_err_read_pointer_increment or E_err_read_pointer_not_increment or E_err_write_en or E_err_not_write_en or E_err_not_write_en1 or E_err_not_write_en2 or E_err_read_en_mismatch or E_err_read_en_mismatch1 or E_err_fake_credit_read_en_fake_credit_counter_in_increment or E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or E_err_fake_credit_read_en_credit_out or E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or E_err_state_out_Idle_not_fault_out_not_fake_credit or E_err_state_out_Idle_not_fault_out_not_fault_info_in or E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or E_err_state_out_Idle_fault_out_fake_credit or E_err_state_out_Idle_fault_out_state_in_Packet_drop or E_err_state_out_Idle_fault_out_fault_info_in or E_err_state_out_Idle_fault_out_faulty_packet_in or E_err_state_out_Idle_not_health_info or E_err_state_out_Idle_not_write_fake_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Header_flit_not_valid_in_not_fault_info_in or E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or E_err_state_out_Header_flit_or_Body_flit_not_fake_credit or E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or E_err_state_out_Body_flit_valid_in_not_fault_out_health_info or E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Body_flit_not_valid_in_not_fault_info_in or E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or E_err_state_out_Body_flit_valid_in_fault_out_not_health_info or E_err_state_out_Body_flit_valid_in_not_health_info or E_err_state_out_Body_flit_not_fake_credit or E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or E_err_state_out_Tail_flit_not_valid_in_state_in_Idle or E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or E_err_state_out_Tail_flit_not_valid_in_not_fake_credit or E_err_state_out_Tail_flit_not_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or E_err_fault_info_fault_info_out_equal or E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- West W_FIFO_checkers_ORed <= W_err_empty_full or W_err_empty_read_en or W_err_full_write_en or W_err_state_in_onehot or W_err_read_pointer_in_onehot or W_err_write_pointer_in_onehot or W_err_write_en_write_pointer or W_err_not_write_en_write_pointer or W_err_read_pointer_write_pointer_not_empty or W_err_read_pointer_write_pointer_empty or W_err_read_pointer_write_pointer_not_full or W_err_read_pointer_write_pointer_full or W_err_read_pointer_increment or W_err_read_pointer_not_increment or W_err_write_en or W_err_not_write_en or W_err_not_write_en1 or W_err_not_write_en2 or W_err_read_en_mismatch or W_err_read_en_mismatch1 or W_err_fake_credit_read_en_fake_credit_counter_in_increment or W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or W_err_fake_credit_read_en_credit_out or W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or W_err_state_out_Idle_not_fault_out_not_fake_credit or W_err_state_out_Idle_not_fault_out_not_fault_info_in or W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or W_err_state_out_Idle_fault_out_fake_credit or W_err_state_out_Idle_fault_out_state_in_Packet_drop or W_err_state_out_Idle_fault_out_fault_info_in or W_err_state_out_Idle_fault_out_faulty_packet_in or W_err_state_out_Idle_not_health_info or W_err_state_out_Idle_not_write_fake_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Header_flit_not_valid_in_not_fault_info_in or W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or W_err_state_out_Header_flit_or_Body_flit_not_fake_credit or W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or W_err_state_out_Body_flit_valid_in_not_fault_out_health_info or W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Body_flit_not_valid_in_not_fault_info_in or W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or W_err_state_out_Body_flit_valid_in_fault_out_not_health_info or W_err_state_out_Body_flit_valid_in_not_health_info or W_err_state_out_Body_flit_not_fake_credit or W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or W_err_state_out_Tail_flit_not_valid_in_state_in_Idle or W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or W_err_state_out_Tail_flit_not_valid_in_not_fake_credit or W_err_state_out_Tail_flit_not_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or W_err_fault_info_fault_info_out_equal or W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- South S_FIFO_checkers_ORed <= S_err_empty_full or S_err_empty_read_en or S_err_full_write_en or S_err_state_in_onehot or S_err_read_pointer_in_onehot or S_err_write_pointer_in_onehot or S_err_write_en_write_pointer or S_err_not_write_en_write_pointer or S_err_read_pointer_write_pointer_not_empty or S_err_read_pointer_write_pointer_empty or S_err_read_pointer_write_pointer_not_full or S_err_read_pointer_write_pointer_full or S_err_read_pointer_increment or S_err_read_pointer_not_increment or S_err_write_en or S_err_not_write_en or S_err_not_write_en1 or S_err_not_write_en2 or S_err_read_en_mismatch or S_err_read_en_mismatch1 or S_err_fake_credit_read_en_fake_credit_counter_in_increment or S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or S_err_fake_credit_read_en_credit_out or S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or S_err_state_out_Idle_not_fault_out_not_fake_credit or S_err_state_out_Idle_not_fault_out_not_fault_info_in or S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or S_err_state_out_Idle_fault_out_fake_credit or S_err_state_out_Idle_fault_out_state_in_Packet_drop or S_err_state_out_Idle_fault_out_fault_info_in or S_err_state_out_Idle_fault_out_faulty_packet_in or S_err_state_out_Idle_not_health_info or S_err_state_out_Idle_not_write_fake_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Header_flit_not_valid_in_not_fault_info_in or S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or S_err_state_out_Header_flit_or_Body_flit_not_fake_credit or S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or S_err_state_out_Body_flit_valid_in_not_fault_out_health_info or S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Body_flit_not_valid_in_not_fault_info_in or S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or S_err_state_out_Body_flit_valid_in_fault_out_not_health_info or S_err_state_out_Body_flit_valid_in_not_health_info or S_err_state_out_Body_flit_not_fake_credit or S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or S_err_state_out_Tail_flit_not_valid_in_state_in_Idle or S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or S_err_state_out_Tail_flit_not_valid_in_not_fake_credit or S_err_state_out_Tail_flit_not_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or S_err_fault_info_fault_info_out_equal or S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- Local L_FIFO_checkers_ORed <= L_err_empty_full or L_err_empty_read_en or L_err_full_write_en or L_err_state_in_onehot or L_err_read_pointer_in_onehot or L_err_write_pointer_in_onehot or L_err_write_en_write_pointer or L_err_not_write_en_write_pointer or L_err_read_pointer_write_pointer_not_empty or L_err_read_pointer_write_pointer_empty or L_err_read_pointer_write_pointer_not_full or L_err_read_pointer_write_pointer_full or L_err_read_pointer_increment or L_err_read_pointer_not_increment or L_err_write_en or L_err_not_write_en or L_err_not_write_en1 or L_err_not_write_en2 or L_err_read_en_mismatch or L_err_read_en_mismatch1 or L_err_fake_credit_read_en_fake_credit_counter_in_increment or L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or L_err_fake_credit_read_en_credit_out or L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or L_err_state_out_Idle_not_fault_out_not_fake_credit or L_err_state_out_Idle_not_fault_out_not_fault_info_in or L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or L_err_state_out_Idle_fault_out_fake_credit or L_err_state_out_Idle_fault_out_state_in_Packet_drop or L_err_state_out_Idle_fault_out_fault_info_in or L_err_state_out_Idle_fault_out_faulty_packet_in or L_err_state_out_Idle_not_health_info or L_err_state_out_Idle_not_write_fake_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Header_flit_not_valid_in_not_fault_info_in or L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or L_err_state_out_Header_flit_or_Body_flit_not_fake_credit or L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or L_err_state_out_Body_flit_valid_in_not_fault_out_health_info or L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Body_flit_not_valid_in_not_fault_info_in or L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or L_err_state_out_Body_flit_valid_in_fault_out_not_health_info or L_err_state_out_Body_flit_valid_in_not_health_info or L_err_state_out_Body_flit_not_fake_credit or L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or L_err_state_out_Tail_flit_not_valid_in_state_in_Idle or L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or L_err_state_out_Tail_flit_not_valid_in_not_fake_credit or L_err_state_out_Tail_flit_not_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or L_err_fault_info_fault_info_out_equal or L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Just for debugging purposes of the checkers! -- LBDR checker outputs ORed -- North -- Routing part checkers N_LBDR_checkers_ORed <= N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_N1 or N_err_dst_addr_cur_addr_not_N1 or N_err_dst_addr_cur_addr_E1 or N_err_dst_addr_cur_addr_not_E1 or N_err_dst_addr_cur_addr_W1 or N_err_dst_addr_cur_addr_not_W1 or N_err_dst_addr_cur_addr_S1 or N_err_dst_addr_cur_addr_not_S1 or N_err_dst_addr_cur_addr_Req_L_in or N_err_dst_addr_cur_addr_not_Req_L_in or N_err_header_not_empty_faulty_drop_packet_in or -- added according to new design N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design N_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --N_err_header_not_empty_Req_L_in or -- added according to new design N_err_header_not_empty_Req_N_in or N_err_header_not_empty_Req_E_in or N_err_header_not_empty_Req_W_in or N_err_header_not_empty_Req_S_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or -- Cx_Reconf checkers N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- East -- Routing part checkers E_LBDR_checkers_ORed <= E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_N1 or E_err_dst_addr_cur_addr_not_N1 or E_err_dst_addr_cur_addr_E1 or E_err_dst_addr_cur_addr_not_E1 or E_err_dst_addr_cur_addr_W1 or E_err_dst_addr_cur_addr_not_W1 or E_err_dst_addr_cur_addr_S1 or E_err_dst_addr_cur_addr_not_S1 or E_err_dst_addr_cur_addr_Req_L_in or E_err_dst_addr_cur_addr_not_Req_L_in or E_err_header_not_empty_faulty_drop_packet_in or -- added according to new design E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design E_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --E_err_header_not_empty_Req_L_in or -- added according to new design E_err_header_not_empty_Req_N_in or E_err_header_not_empty_Req_E_in or E_err_header_not_empty_Req_W_in or E_err_header_not_empty_Req_S_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or -- Cx_Reconf checkers E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- West -- Routing part checkers W_LBDR_checkers_ORed <= W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_N1 or W_err_dst_addr_cur_addr_not_N1 or W_err_dst_addr_cur_addr_E1 or W_err_dst_addr_cur_addr_not_E1 or W_err_dst_addr_cur_addr_W1 or W_err_dst_addr_cur_addr_not_W1 or W_err_dst_addr_cur_addr_S1 or W_err_dst_addr_cur_addr_not_S1 or W_err_dst_addr_cur_addr_Req_L_in or W_err_dst_addr_cur_addr_not_Req_L_in or W_err_header_not_empty_faulty_drop_packet_in or -- added according to new design W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design W_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --W_err_header_not_empty_Req_L_in or -- added according to new design W_err_header_not_empty_Req_N_in or W_err_header_not_empty_Req_E_in or W_err_header_not_empty_Req_W_in or W_err_header_not_empty_Req_S_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or -- Cx_Reconf checkers W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- South -- Routing part checkers S_LBDR_checkers_ORed <= S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_N1 or S_err_dst_addr_cur_addr_not_N1 or S_err_dst_addr_cur_addr_E1 or S_err_dst_addr_cur_addr_not_E1 or S_err_dst_addr_cur_addr_W1 or S_err_dst_addr_cur_addr_not_W1 or S_err_dst_addr_cur_addr_S1 or S_err_dst_addr_cur_addr_not_S1 or S_err_dst_addr_cur_addr_Req_L_in or S_err_dst_addr_cur_addr_not_Req_L_in or S_err_header_not_empty_faulty_drop_packet_in or -- added according to new design S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design S_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --S_err_header_not_empty_Req_L_in or -- added according to new design S_err_header_not_empty_Req_N_in or S_err_header_not_empty_Req_E_in or S_err_header_not_empty_Req_W_in or S_err_header_not_empty_Req_S_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or -- Cx_Reconf checkers S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- Local -- Routing part checkers L_LBDR_checkers_ORed <= L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_N1 or L_err_dst_addr_cur_addr_not_N1 or L_err_dst_addr_cur_addr_E1 or L_err_dst_addr_cur_addr_not_E1 or L_err_dst_addr_cur_addr_W1 or L_err_dst_addr_cur_addr_not_W1 or L_err_dst_addr_cur_addr_S1 or L_err_dst_addr_cur_addr_not_S1 or L_err_dst_addr_cur_addr_Req_L_in or L_err_dst_addr_cur_addr_not_Req_L_in or L_err_header_not_empty_faulty_drop_packet_in or -- added according to new design L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design L_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --L_err_header_not_empty_Req_L_in or -- added according to new design L_err_header_not_empty_Req_N_in or L_err_header_not_empty_Req_E_in or L_err_header_not_empty_Req_W_in or L_err_header_not_empty_Req_S_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or -- Cx_Reconf checkers L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Allocator checker outputs ORed ! -- Allocator logic checker outputs Allocator_checkers_ORed <= err_grant_N_N_sig_not_empty_N_grant_N_N or err_not_grant_N_N_sig_or_empty_N_not_grant_N_N or err_grant_N_E_sig_not_empty_E_grant_N_E or err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or err_grant_N_W_sig_not_empty_W_grant_N_W or err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or err_grant_N_S_sig_not_empty_S_grant_N_S or err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or err_grant_N_L_sig_not_empty_L_grant_N_L or err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or err_grant_E_N_sig_not_empty_N_grant_E_N or err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or err_grant_E_E_sig_not_empty_E_grant_E_E or err_not_grant_E_E_sig_or_empty_E_not_grant_E_E or err_grant_E_W_sig_not_empty_W_grant_E_W or err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or err_grant_E_S_sig_not_empty_S_grant_E_S or err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or err_grant_E_L_sig_not_empty_L_grant_E_L or err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or err_grant_W_N_sig_not_empty_N_grant_W_N or err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or err_grant_W_E_sig_not_empty_E_grant_W_E or err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or err_grant_W_W_sig_not_empty_W_grant_W_W or err_not_grant_W_W_sig_or_empty_W_not_grant_W_W or err_grant_W_S_sig_not_empty_S_grant_W_S or err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or err_grant_W_L_sig_not_empty_L_grant_W_L or err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or err_grant_S_N_sig_not_empty_N_grant_S_N or err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or err_grant_S_E_sig_not_empty_E_grant_S_E or err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or err_grant_S_W_sig_not_empty_W_grant_S_W or err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or err_grant_S_S_sig_not_empty_S_grant_S_S or err_not_grant_S_S_sig_or_empty_S_not_grant_S_S or err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or err_grant_L_N_sig_not_empty_N_grant_L_N or err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or err_grant_L_E_sig_not_empty_E_grant_L_E or err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or err_grant_L_W_sig_not_empty_W_grant_L_W or err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or err_grant_L_L_sig_not_empty_L_grant_L_L or err_not_grant_L_L_sig_or_empty_L_not_grant_L_L or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or -- Allocator credit counter logic checker outputs err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal or -- Arbiter_in checker outputs -- North Arbiter_in checker outputs N_err_Requests_state_in_state_not_equal or N_err_IDLE_Req_N or N_err_IDLE_grant_N or N_err_North_Req_N or N_err_North_grant_N or N_err_East_Req_E or N_err_East_grant_E or N_err_West_Req_W or N_err_West_grant_W or N_err_South_Req_S or N_err_South_grant_S or N_err_Local_Req_L or N_err_Local_grant_L or N_err_IDLE_Req_E or N_err_IDLE_grant_E or N_err_North_Req_E or N_err_North_grant_E or N_err_East_Req_W or N_err_East_grant_W or N_err_West_Req_S or N_err_West_grant_S or N_err_South_Req_L or N_err_South_grant_L or N_err_Local_Req_N or N_err_Local_grant_N or N_err_IDLE_Req_W or N_err_IDLE_grant_W or N_err_North_Req_W or N_err_North_grant_W or N_err_East_Req_S or N_err_East_grant_S or N_err_West_Req_L or N_err_West_grant_L or N_err_South_Req_N or N_err_South_grant_N or N_err_Local_Req_E or N_err_Local_grant_E or N_err_IDLE_Req_S or N_err_IDLE_grant_S or N_err_North_Req_S or N_err_North_grant_S or N_err_East_Req_L or N_err_East_grant_L or N_err_West_Req_N or N_err_West_grant_N or N_err_South_Req_E or N_err_South_grant_E or N_err_Local_Req_W or N_err_Local_grant_W or N_err_IDLE_Req_L or N_err_IDLE_grant_L or N_err_North_Req_L or N_err_North_grant_L or N_err_East_Req_N or N_err_East_grant_N or N_err_West_Req_E or N_err_West_grant_E or N_err_South_Req_W or N_err_South_grant_W or N_err_Local_Req_S or N_err_Local_grant_S or N_err_arbiter_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_N_grant_N or N_err_no_Req_E_grant_E or N_err_no_Req_W_grant_W or N_err_no_Req_S_grant_S or N_err_no_Req_L_grant_L or -- East Arbiter_in checker outputs E_err_Requests_state_in_state_not_equal or E_err_IDLE_Req_N or E_err_IDLE_grant_N or E_err_North_Req_N or E_err_North_grant_N or E_err_East_Req_E or E_err_East_grant_E or E_err_West_Req_W or E_err_West_grant_W or E_err_South_Req_S or E_err_South_grant_S or E_err_Local_Req_L or E_err_Local_grant_L or E_err_IDLE_Req_E or E_err_IDLE_grant_E or E_err_North_Req_E or E_err_North_grant_E or E_err_East_Req_W or E_err_East_grant_W or E_err_West_Req_S or E_err_West_grant_S or E_err_South_Req_L or E_err_South_grant_L or E_err_Local_Req_N or E_err_Local_grant_N or E_err_IDLE_Req_W or E_err_IDLE_grant_W or E_err_North_Req_W or E_err_North_grant_W or E_err_East_Req_S or E_err_East_grant_S or E_err_West_Req_L or E_err_West_grant_L or E_err_South_Req_N or E_err_South_grant_N or E_err_Local_Req_E or E_err_Local_grant_E or E_err_IDLE_Req_S or E_err_IDLE_grant_S or E_err_North_Req_S or E_err_North_grant_S or E_err_East_Req_L or E_err_East_grant_L or E_err_West_Req_N or E_err_West_grant_N or E_err_South_Req_E or E_err_South_grant_E or E_err_Local_Req_W or E_err_Local_grant_W or E_err_IDLE_Req_L or E_err_IDLE_grant_L or E_err_North_Req_L or E_err_North_grant_L or E_err_East_Req_N or E_err_East_grant_N or E_err_West_Req_E or E_err_West_grant_E or E_err_South_Req_W or E_err_South_grant_W or E_err_Local_Req_S or E_err_Local_grant_S or E_err_arbiter_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_N_grant_N or E_err_no_Req_E_grant_E or E_err_no_Req_W_grant_W or E_err_no_Req_S_grant_S or E_err_no_Req_L_grant_L or -- West Arbiter_in checker outputs W_err_Requests_state_in_state_not_equal or W_err_IDLE_Req_N or W_err_IDLE_grant_N or W_err_North_Req_N or W_err_North_grant_N or W_err_East_Req_E or W_err_East_grant_E or W_err_West_Req_W or W_err_West_grant_W or W_err_South_Req_S or W_err_South_grant_S or W_err_Local_Req_L or W_err_Local_grant_L or W_err_IDLE_Req_E or W_err_IDLE_grant_E or W_err_North_Req_E or W_err_North_grant_E or W_err_East_Req_W or W_err_East_grant_W or W_err_West_Req_S or W_err_West_grant_S or W_err_South_Req_L or W_err_South_grant_L or W_err_Local_Req_N or W_err_Local_grant_N or W_err_IDLE_Req_W or W_err_IDLE_grant_W or W_err_North_Req_W or W_err_North_grant_W or W_err_East_Req_S or W_err_East_grant_S or W_err_West_Req_L or W_err_West_grant_L or W_err_South_Req_N or W_err_South_grant_N or W_err_Local_Req_E or W_err_Local_grant_E or W_err_IDLE_Req_S or W_err_IDLE_grant_S or W_err_North_Req_S or W_err_North_grant_S or W_err_East_Req_L or W_err_East_grant_L or W_err_West_Req_N or W_err_West_grant_N or W_err_South_Req_E or W_err_South_grant_E or W_err_Local_Req_W or W_err_Local_grant_W or W_err_IDLE_Req_L or W_err_IDLE_grant_L or W_err_North_Req_L or W_err_North_grant_L or W_err_East_Req_N or W_err_East_grant_N or W_err_West_Req_E or W_err_West_grant_E or W_err_South_Req_W or W_err_South_grant_W or W_err_Local_Req_S or W_err_Local_grant_S or W_err_arbiter_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_N_grant_N or W_err_no_Req_E_grant_E or W_err_no_Req_W_grant_W or W_err_no_Req_S_grant_S or W_err_no_Req_L_grant_L or -- South Arbiter_in checker outputs S_err_Requests_state_in_state_not_equal or S_err_IDLE_Req_N or S_err_IDLE_grant_N or S_err_North_Req_N or S_err_North_grant_N or S_err_East_Req_E or S_err_East_grant_E or S_err_West_Req_W or S_err_West_grant_W or S_err_South_Req_S or S_err_South_grant_S or S_err_Local_Req_L or S_err_Local_grant_L or S_err_IDLE_Req_E or S_err_IDLE_grant_E or S_err_North_Req_E or S_err_North_grant_E or S_err_East_Req_W or S_err_East_grant_W or S_err_West_Req_S or S_err_West_grant_S or S_err_South_Req_L or S_err_South_grant_L or S_err_Local_Req_N or S_err_Local_grant_N or S_err_IDLE_Req_W or S_err_IDLE_grant_W or S_err_North_Req_W or S_err_North_grant_W or S_err_East_Req_S or S_err_East_grant_S or S_err_West_Req_L or S_err_West_grant_L or S_err_South_Req_N or S_err_South_grant_N or S_err_Local_Req_E or S_err_Local_grant_E or S_err_IDLE_Req_S or S_err_IDLE_grant_S or S_err_North_Req_S or S_err_North_grant_S or S_err_East_Req_L or S_err_East_grant_L or S_err_West_Req_N or S_err_West_grant_N or S_err_South_Req_E or S_err_South_grant_E or S_err_Local_Req_W or S_err_Local_grant_W or S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or S_err_East_Req_N or S_err_East_grant_N or S_err_West_Req_E or S_err_West_grant_E or S_err_South_Req_W or S_err_South_grant_W or S_err_Local_Req_S or S_err_Local_grant_S or S_err_arbiter_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_N_grant_N or S_err_no_Req_E_grant_E or S_err_no_Req_W_grant_W or S_err_no_Req_S_grant_S or S_err_no_Req_L_grant_L or -- Local Arbiter_in checker outputs L_err_Requests_state_in_state_not_equal or L_err_IDLE_Req_N or L_err_IDLE_grant_N or L_err_North_Req_N or L_err_North_grant_N or L_err_East_Req_E or L_err_East_grant_E or L_err_West_Req_W or L_err_West_grant_W or L_err_South_Req_S or L_err_South_grant_S or L_err_Local_Req_L or L_err_Local_grant_L or L_err_IDLE_Req_E or L_err_IDLE_grant_E or L_err_North_Req_E or L_err_North_grant_E or L_err_East_Req_W or L_err_East_grant_W or L_err_West_Req_S or L_err_West_grant_S or L_err_South_Req_L or L_err_South_grant_L or L_err_Local_Req_N or L_err_Local_grant_N or L_err_IDLE_Req_W or L_err_IDLE_grant_W or L_err_North_Req_W or L_err_North_grant_W or L_err_East_Req_S or L_err_East_grant_S or L_err_West_Req_L or L_err_West_grant_L or L_err_South_Req_N or L_err_South_grant_N or L_err_Local_Req_E or L_err_Local_grant_E or L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or L_err_East_Req_L or L_err_East_grant_L or L_err_West_Req_N or L_err_West_grant_N or L_err_South_Req_E or L_err_South_grant_E or L_err_Local_Req_W or L_err_Local_grant_W or L_err_IDLE_Req_L or L_err_IDLE_grant_L or L_err_North_Req_L or L_err_North_grant_L or L_err_East_Req_N or L_err_East_grant_N or L_err_West_Req_E or L_err_West_grant_E or L_err_South_Req_W or L_err_South_grant_W or L_err_Local_Req_S or L_err_Local_grant_S or L_err_arbiter_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_N_grant_N or L_err_no_Req_E_grant_E or L_err_no_Req_W_grant_W or L_err_no_Req_S_grant_S or L_err_no_Req_L_grant_L or -- Arbiter_out checker outputs -- North Arbiter_out checker outputs N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_IDLE_req_X_N or N_err_North_req_X_N or N_err_North_credit_not_zero_req_X_N_grant_N or N_err_North_credit_zero_or_not_req_X_N_not_grant_N or N_err_East_req_X_E or N_err_East_credit_not_zero_req_X_E_grant_E or N_err_East_credit_zero_or_not_req_X_E_not_grant_E or N_err_West_req_X_W or N_err_West_credit_not_zero_req_X_W_grant_W or N_err_West_credit_zero_or_not_req_X_W_not_grant_W or N_err_South_req_X_S or N_err_South_credit_not_zero_req_X_S_grant_S or N_err_South_credit_zero_or_not_req_X_S_not_grant_S or N_err_Local_req_X_L or N_err_Local_credit_not_zero_req_X_L_grant_L or N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or N_err_IDLE_req_X_E or N_err_North_req_X_E or N_err_East_req_X_W or N_err_West_req_X_S or N_err_South_req_X_L or N_err_Local_req_X_N or N_err_IDLE_req_X_W or N_err_North_req_X_W or N_err_East_req_X_S or N_err_West_req_X_L or N_err_South_req_X_N or N_err_Local_req_X_E or N_err_IDLE_req_X_S or N_err_North_req_X_S or N_err_East_req_X_L or N_err_West_req_X_N or N_err_South_req_X_E or N_err_Local_req_X_W or N_err_IDLE_req_X_L or N_err_North_req_X_L or N_err_East_req_X_N or N_err_West_req_X_E or N_err_South_req_X_W or N_err_Local_req_X_S or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_state_North_Invalid_Grant or N_err_state_East_Invalid_Grant or N_err_state_West_Invalid_Grant or N_err_state_South_Invalid_Grant or N_err_state_Local_Invalid_Grant or N_err_Grants_onehot_or_all_zero or -- East Arbiter_out checker outputs E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_IDLE_req_X_N or E_err_North_req_X_N or E_err_North_credit_not_zero_req_X_N_grant_N or E_err_North_credit_zero_or_not_req_X_N_not_grant_N or E_err_East_req_X_E or E_err_East_credit_not_zero_req_X_E_grant_E or E_err_East_credit_zero_or_not_req_X_E_not_grant_E or E_err_West_req_X_W or E_err_West_credit_not_zero_req_X_W_grant_W or E_err_West_credit_zero_or_not_req_X_W_not_grant_W or E_err_South_req_X_S or E_err_South_credit_not_zero_req_X_S_grant_S or E_err_South_credit_zero_or_not_req_X_S_not_grant_S or E_err_Local_req_X_L or E_err_Local_credit_not_zero_req_X_L_grant_L or E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or E_err_IDLE_req_X_E or E_err_North_req_X_E or E_err_East_req_X_W or E_err_West_req_X_S or E_err_South_req_X_L or E_err_Local_req_X_N or E_err_IDLE_req_X_W or E_err_North_req_X_W or E_err_East_req_X_S or E_err_West_req_X_L or E_err_South_req_X_N or E_err_Local_req_X_E or E_err_IDLE_req_X_S or E_err_North_req_X_S or E_err_East_req_X_L or E_err_West_req_X_N or E_err_South_req_X_E or E_err_Local_req_X_W or E_err_IDLE_req_X_L or E_err_North_req_X_L or E_err_East_req_X_N or E_err_West_req_X_E or E_err_South_req_X_W or E_err_Local_req_X_S or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_state_North_Invalid_Grant or E_err_state_East_Invalid_Grant or E_err_state_West_Invalid_Grant or E_err_state_South_Invalid_Grant or E_err_state_Local_Invalid_Grant or E_err_Grants_onehot_or_all_zero or -- West Arbiter_out checker outputs W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_IDLE_req_X_N or W_err_North_req_X_N or W_err_North_credit_not_zero_req_X_N_grant_N or W_err_North_credit_zero_or_not_req_X_N_not_grant_N or W_err_East_req_X_E or W_err_East_credit_not_zero_req_X_E_grant_E or W_err_East_credit_zero_or_not_req_X_E_not_grant_E or W_err_West_req_X_W or W_err_West_credit_not_zero_req_X_W_grant_W or W_err_West_credit_zero_or_not_req_X_W_not_grant_W or W_err_South_req_X_S or W_err_South_credit_not_zero_req_X_S_grant_S or W_err_South_credit_zero_or_not_req_X_S_not_grant_S or W_err_Local_req_X_L or W_err_Local_credit_not_zero_req_X_L_grant_L or W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or W_err_IDLE_req_X_E or W_err_North_req_X_E or W_err_East_req_X_W or W_err_West_req_X_S or W_err_South_req_X_L or W_err_Local_req_X_N or W_err_IDLE_req_X_W or W_err_North_req_X_W or W_err_East_req_X_S or W_err_West_req_X_L or W_err_South_req_X_N or W_err_Local_req_X_E or W_err_IDLE_req_X_S or W_err_North_req_X_S or W_err_East_req_X_L or W_err_West_req_X_N or W_err_South_req_X_E or W_err_Local_req_X_W or W_err_IDLE_req_X_L or W_err_North_req_X_L or W_err_East_req_X_N or W_err_West_req_X_E or W_err_South_req_X_W or W_err_Local_req_X_S or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_state_North_Invalid_Grant or W_err_state_East_Invalid_Grant or W_err_state_West_Invalid_Grant or W_err_state_South_Invalid_Grant or W_err_state_Local_Invalid_Grant or W_err_Grants_onehot_or_all_zero or -- South Arbiter_out checker outputs S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_IDLE_req_X_N or S_err_North_req_X_N or S_err_North_credit_not_zero_req_X_N_grant_N or S_err_North_credit_zero_or_not_req_X_N_not_grant_N or S_err_East_req_X_E or S_err_East_credit_not_zero_req_X_E_grant_E or S_err_East_credit_zero_or_not_req_X_E_not_grant_E or S_err_West_req_X_W or S_err_West_credit_not_zero_req_X_W_grant_W or S_err_West_credit_zero_or_not_req_X_W_not_grant_W or S_err_South_req_X_S or S_err_South_credit_not_zero_req_X_S_grant_S or S_err_South_credit_zero_or_not_req_X_S_not_grant_S or S_err_Local_req_X_L or S_err_Local_credit_not_zero_req_X_L_grant_L or S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or S_err_IDLE_req_X_E or S_err_North_req_X_E or S_err_East_req_X_W or S_err_West_req_X_S or S_err_South_req_X_L or S_err_Local_req_X_N or S_err_IDLE_req_X_W or S_err_North_req_X_W or S_err_East_req_X_S or S_err_West_req_X_L or S_err_South_req_X_N or S_err_Local_req_X_E or S_err_IDLE_req_X_S or S_err_North_req_X_S or S_err_East_req_X_L or S_err_West_req_X_N or S_err_South_req_X_E or S_err_Local_req_X_W or S_err_IDLE_req_X_L or S_err_North_req_X_L or S_err_East_req_X_N or S_err_West_req_X_E or S_err_South_req_X_W or S_err_Local_req_X_S or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_state_North_Invalid_Grant or S_err_state_East_Invalid_Grant or S_err_state_West_Invalid_Grant or S_err_state_South_Invalid_Grant or S_err_state_Local_Invalid_Grant or S_err_Grants_onehot_or_all_zero or -- Local Arbiter_out checker outputs L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_IDLE_req_X_N or L_err_North_req_X_N or L_err_North_credit_not_zero_req_X_N_grant_N or L_err_North_credit_zero_or_not_req_X_N_not_grant_N or L_err_East_req_X_E or L_err_East_credit_not_zero_req_X_E_grant_E or L_err_East_credit_zero_or_not_req_X_E_not_grant_E or L_err_West_req_X_W or L_err_West_credit_not_zero_req_X_W_grant_W or L_err_West_credit_zero_or_not_req_X_W_not_grant_W or L_err_South_req_X_S or L_err_South_credit_not_zero_req_X_S_grant_S or L_err_South_credit_zero_or_not_req_X_S_not_grant_S or L_err_Local_req_X_L or L_err_Local_credit_not_zero_req_X_L_grant_L or L_err_Local_credit_zero_or_not_req_X_L_not_grant_L or L_err_IDLE_req_X_E or L_err_North_req_X_E or L_err_East_req_X_W or L_err_West_req_X_S or L_err_South_req_X_L or L_err_Local_req_X_N or L_err_IDLE_req_X_W or L_err_North_req_X_W or L_err_East_req_X_S or L_err_West_req_X_L or L_err_South_req_X_N or L_err_Local_req_X_E or L_err_IDLE_req_X_S or L_err_North_req_X_S or L_err_East_req_X_L or L_err_West_req_X_N or L_err_South_req_X_E or L_err_Local_req_X_W or L_err_IDLE_req_X_L or L_err_North_req_X_L or L_err_East_req_X_N or L_err_West_req_X_E or L_err_South_req_X_W or L_err_Local_req_X_S or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_state_North_Invalid_Grant or L_err_state_East_Invalid_Grant or L_err_state_West_Invalid_Grant or L_err_state_South_Invalid_Grant or L_err_state_Local_Invalid_Grant or L_err_Grants_onehot_or_all_zero; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Turn fault checkers -- FIFO N2E_turn_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_E1 or N_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or N_err_header_not_empty_Req_E_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_East_Req_E or N_err_East_grant_E or N_err_IDLE_Req_E or N_err_IDLE_grant_E or N_err_North_Req_E or N_err_North_grant_E or N_err_Local_Req_E or N_err_Local_grant_E or N_err_South_Req_E or N_err_South_grant_E or N_err_West_Req_E or N_err_West_grant_E or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_IDLE_req_X_N or E_err_North_req_X_N or E_err_North_credit_not_zero_req_X_N_grant_N or E_err_North_credit_zero_or_not_req_X_N_not_grant_N or E_err_Local_req_X_N or E_err_South_req_X_N or E_err_West_req_X_N or E_err_East_req_X_N or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or W_err_South_req_X_N or W_err_West_req_X_N or W_err_East_req_X_N or err_grant_E_N_sig_not_empty_N_grant_E_N or err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- FIFO N2W_turn_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_W1 or N_err_dst_addr_cur_addr_not_W1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or N_err_header_not_empty_Req_W_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_West_Req_W or N_err_West_grant_W or N_err_East_Req_W or N_err_East_grant_W or N_err_IDLE_Req_W or N_err_IDLE_grant_W or N_err_North_Req_W or N_err_North_grant_W or N_err_Local_Req_W or N_err_Local_grant_W or N_err_South_Req_W or N_err_South_grant_W or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_IDLE_req_X_N or W_err_North_req_X_N or W_err_North_credit_not_zero_req_X_N_grant_N or W_err_North_credit_zero_or_not_req_X_N_not_grant_N or W_err_Local_req_X_N or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_N_sig_not_empty_N_grant_W_N or err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- FIFO E2N_turn_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_N1 or E_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or E_err_header_not_empty_Req_N_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_IDLE_Req_N or E_err_IDLE_grant_N or E_err_North_Req_N or E_err_North_grant_N or E_err_Local_Req_N or E_err_Local_grant_N or E_err_South_Req_N or E_err_South_grant_N or E_err_West_Req_N or E_err_West_grant_N or E_err_East_Req_N or E_err_East_grant_N or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_East_req_X_E or N_err_East_credit_not_zero_req_X_E_grant_E or N_err_East_credit_zero_or_not_req_X_E_not_grant_E or N_err_IDLE_req_X_E or N_err_North_req_X_E or N_err_Local_req_X_E or N_err_South_req_X_E or N_err_West_req_X_E or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_Grants_onehot_or_all_zero or err_grant_N_E_sig_not_empty_E_grant_N_E or err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO E2S_turn_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_S1 or E_err_dst_addr_cur_addr_not_S1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or E_err_header_not_empty_Req_S_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_South_Req_S or E_err_South_grant_S or E_err_West_Req_S or E_err_West_grant_S or E_err_East_Req_S or E_err_East_grant_S or E_err_IDLE_Req_S or E_err_IDLE_grant_S or E_err_North_Req_S or E_err_North_grant_S or E_err_Local_Req_S or E_err_Local_grant_S or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_East_req_X_E or S_err_East_credit_not_zero_req_X_E_grant_E or S_err_East_credit_zero_or_not_req_X_E_not_grant_E or S_err_IDLE_req_X_E or S_err_North_req_X_E or S_err_Local_req_X_E or S_err_South_req_X_E or S_err_West_req_X_E or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_E_sig_not_empty_E_grant_S_E or err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO W2N_turn_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_N1 or W_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_N_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_IDLE_Req_N or W_err_IDLE_grant_N or W_err_North_Req_N or W_err_North_grant_N or W_err_Local_Req_N or W_err_Local_grant_N or W_err_South_Req_N or W_err_South_grant_N or W_err_West_Req_N or W_err_West_grant_N or W_err_East_Req_N or W_err_East_grant_N or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_West_req_X_W or N_err_West_credit_not_zero_req_X_W_grant_W or N_err_West_credit_zero_or_not_req_X_W_not_grant_W or N_err_East_req_X_W or N_err_IDLE_req_X_W or N_err_North_req_X_W or N_err_Local_req_X_W or N_err_South_req_X_W or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or err_grant_N_W_sig_not_empty_W_grant_N_W or err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO W2S_turn_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_S1 or W_err_dst_addr_cur_addr_not_S1 or W_err_header_not_empty_faulty_drop_packet_in or W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or W_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_S_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_South_Req_S or W_err_South_grant_S or W_err_West_Req_S or W_err_West_grant_S or W_err_East_Req_S or W_err_East_grant_S or W_err_IDLE_Req_S or W_err_IDLE_grant_S or W_err_North_Req_S or W_err_North_grant_S or W_err_Local_Req_S or W_err_Local_grant_S or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_West_req_X_W or S_err_West_credit_not_zero_req_X_W_grant_W or S_err_West_credit_zero_or_not_req_X_W_not_grant_W or S_err_East_req_X_W or S_err_IDLE_req_X_W or S_err_North_req_X_W or S_err_Local_req_X_W or S_err_South_req_X_W or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_W_sig_not_empty_W_grant_S_W or err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO S2E_turn_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_E1 or S_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_E_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_East_Req_E or S_err_East_grant_E or S_err_IDLE_Req_E or S_err_IDLE_grant_E or S_err_North_Req_E or S_err_North_grant_E or S_err_Local_Req_E or S_err_Local_grant_E or S_err_South_Req_E or S_err_South_grant_E or S_err_West_Req_E or S_err_West_grant_E or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_South_req_X_S or E_err_South_credit_not_zero_req_X_S_grant_S or E_err_South_credit_zero_or_not_req_X_S_not_grant_S or E_err_West_req_X_S or E_err_East_req_X_S or E_err_IDLE_req_X_S or E_err_North_req_X_S or E_err_Local_req_X_S or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or err_grant_E_S_sig_not_empty_S_grant_E_S or err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_grants_valid_not_match or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- FIFO S2W_turn_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_W1 or S_err_dst_addr_cur_addr_not_W1 or S_err_header_not_empty_faulty_drop_packet_in or S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or S_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_W_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_West_Req_W or S_err_West_grant_W or S_err_East_Req_W or S_err_East_grant_W or S_err_IDLE_Req_W or S_err_IDLE_grant_W or S_err_North_Req_W or S_err_North_grant_W or S_err_Local_Req_W or S_err_Local_grant_W or S_err_South_Req_W or S_err_South_grant_W or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_South_req_X_S or W_err_South_credit_not_zero_req_X_S_grant_S or W_err_South_credit_zero_or_not_req_X_S_not_grant_S or W_err_West_req_X_S or W_err_East_req_X_S or W_err_IDLE_req_X_S or W_err_North_req_X_S or W_err_Local_req_X_S or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_S_sig_not_empty_S_grant_W_S or err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- Path fault checkers -- FIFO N2S_path_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_S1 or N_err_dst_addr_cur_addr_not_S1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or N_err_header_not_empty_Req_S_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_South_Req_S or N_err_South_grant_S or N_err_West_Req_S or N_err_West_grant_S or N_err_East_Req_S or N_err_East_grant_S or N_err_IDLE_Req_S or N_err_IDLE_grant_S or N_err_North_Req_S or N_err_North_grant_S or N_err_Local_Req_S or N_err_Local_grant_S or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_IDLE_req_X_N or S_err_North_req_X_N or S_err_North_credit_not_zero_req_X_N_grant_N or S_err_North_credit_zero_or_not_req_X_N_not_grant_N or S_err_Local_req_X_N or S_err_South_req_X_N or S_err_West_req_X_N or S_err_East_req_X_N or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_N_sig_not_empty_N_grant_S_N or err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO S2N_path_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_N1 or S_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_N_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_IDLE_Req_N or S_err_IDLE_grant_N or S_err_North_Req_N or S_err_North_grant_N or S_err_Local_Req_N or S_err_Local_grant_N or S_err_South_Req_N or S_err_South_grant_N or S_err_West_Req_N or S_err_West_grant_N or S_err_East_Req_N or S_err_East_grant_N or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_South_req_X_S or N_err_South_credit_not_zero_req_X_S_grant_S or N_err_South_credit_zero_or_not_req_X_S_not_grant_S or N_err_West_req_X_S or N_err_East_req_X_S or N_err_IDLE_req_X_S or N_err_North_req_X_S or N_err_Local_req_X_S or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or err_grant_N_S_sig_not_empty_S_grant_N_S or err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO E2W_path_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_W1 or E_err_dst_addr_cur_addr_not_W1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or E_err_header_not_empty_Req_W_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_West_Req_W or E_err_West_grant_W or E_err_East_Req_W or E_err_East_grant_W or E_err_IDLE_Req_W or E_err_IDLE_grant_W or E_err_North_Req_W or E_err_North_grant_W or E_err_Local_Req_W or E_err_Local_grant_W or E_err_South_Req_W or E_err_South_grant_W or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_East_req_X_E or W_err_East_credit_not_zero_req_X_E_grant_E or W_err_East_credit_zero_or_not_req_X_E_not_grant_E or W_err_IDLE_req_X_E or W_err_North_req_X_E or W_err_Local_req_X_E or W_err_South_req_X_E or W_err_West_req_X_E or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_E_sig_not_empty_E_grant_W_E or err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- FIFO W2E_path_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_E1 or W_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_E_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_East_Req_E or W_err_East_grant_E or W_err_IDLE_Req_E or W_err_IDLE_grant_E or W_err_North_Req_E or W_err_North_grant_E or W_err_Local_Req_E or W_err_Local_grant_E or W_err_South_Req_E or W_err_South_grant_E or W_err_West_Req_E or W_err_West_grant_E or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_West_req_X_W or E_err_West_credit_not_zero_req_X_W_grant_W or E_err_West_credit_zero_or_not_req_X_W_not_grant_W or E_err_East_req_X_W or E_err_IDLE_req_X_W or E_err_North_req_X_W or E_err_Local_req_X_W or E_err_South_req_X_W or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or err_grant_E_W_sig_not_empty_W_grant_E_W or err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- Checkers for Paths/turns from/to Local port -- FIFO L2N_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_N1 or L_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_N_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_IDLE_Req_N or L_err_IDLE_grant_N or L_err_North_Req_N or L_err_North_grant_N or L_err_Local_Req_N or L_err_Local_grant_N or L_err_South_Req_N or L_err_South_grant_N or L_err_West_Req_N or L_err_West_grant_N or L_err_East_Req_N or L_err_East_grant_N or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_Local_req_X_L or N_err_Local_credit_not_zero_req_X_L_grant_L or N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or N_err_South_req_X_L or N_err_West_req_X_L or N_err_East_req_X_L or N_err_IDLE_req_X_L or N_err_North_req_X_L or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or err_grant_N_L_sig_not_empty_L_grant_N_L or err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO L2E_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_E1 or L_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_E_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_East_Req_E or L_err_East_grant_E or L_err_IDLE_Req_E or L_err_IDLE_grant_E or L_err_North_Req_E or L_err_North_grant_E or L_err_Local_Req_E or L_err_Local_grant_E or L_err_South_Req_E or L_err_South_grant_E or L_err_West_Req_E or L_err_West_grant_E or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_Local_req_X_L or E_err_Local_credit_not_zero_req_X_L_grant_L or E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or E_err_South_req_X_L or E_err_West_req_X_L or E_err_East_req_X_L or E_err_IDLE_req_X_L or E_err_North_req_X_L or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or err_grant_E_L_sig_not_empty_L_grant_E_L or err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_grants_valid_not_match or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- FIFO L2W_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_W1 or L_err_dst_addr_cur_addr_not_W1 or L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_W_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_West_Req_W or L_err_West_grant_W or L_err_East_Req_W or L_err_East_grant_W or L_err_IDLE_Req_W or L_err_IDLE_grant_W or L_err_North_Req_W or L_err_North_grant_W or L_err_Local_Req_W or L_err_Local_grant_W or L_err_South_Req_W or L_err_South_grant_W or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_Local_req_X_L or W_err_Local_credit_not_zero_req_X_L_grant_L or W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or W_err_South_req_X_L or W_err_West_req_X_L or W_err_East_req_X_L or W_err_IDLE_req_X_L or W_err_North_req_X_L or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_L_sig_not_empty_L_grant_W_L or err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- FIFO L2S_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_S1 or L_err_dst_addr_cur_addr_not_S1 or L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_S_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_South_Req_S or L_err_South_grant_S or L_err_West_Req_S or L_err_West_grant_S or L_err_East_Req_S or L_err_East_grant_S or L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or L_err_Local_Req_S or L_err_Local_grant_S or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_Local_req_X_L or S_err_Local_credit_not_zero_req_X_L_grant_L or S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or S_err_South_req_X_L or S_err_West_req_X_L or S_err_East_req_X_L or S_err_IDLE_req_X_L or S_err_North_req_X_L or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO N2L_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_Req_L_in or N_err_dst_addr_cur_addr_not_Req_L_in or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or --N_err_header_not_empty_Req_L_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_Local_Req_L or N_err_Local_grant_L or N_err_South_Req_L or N_err_South_grant_L or N_err_West_Req_L or N_err_West_grant_L or N_err_East_Req_L or N_err_East_grant_L or N_err_IDLE_Req_L or N_err_IDLE_grant_L or N_err_North_Req_L or N_err_North_grant_L or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_IDLE_req_X_N or L_err_North_req_X_N or L_err_North_credit_not_zero_req_X_N_grant_N or L_err_North_credit_zero_or_not_req_X_N_not_grant_N or L_err_Local_req_X_N or L_err_South_req_X_N or L_err_West_req_X_N or L_err_East_req_X_N or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_N_sig_not_empty_N_grant_L_N or err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; -- FIFO E2L_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_Req_L_in or E_err_dst_addr_cur_addr_not_Req_L_in or E_err_header_not_empty_faulty_drop_packet_in or E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or E_err_header_not_empty_faulty_Req_in_all_zero or --E_err_header_not_empty_Req_L_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_Local_Req_L or E_err_Local_grant_L or E_err_South_Req_L or E_err_South_grant_L or E_err_West_Req_L or E_err_West_grant_L or E_err_East_Req_L or E_err_East_grant_L or E_err_IDLE_Req_L or E_err_IDLE_grant_L or E_err_North_Req_L or E_err_North_grant_L or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_East_req_X_E or L_err_East_credit_not_zero_req_X_E_grant_E or L_err_East_credit_zero_or_not_req_X_E_not_grant_E or L_err_IDLE_req_X_E or L_err_North_req_X_E or L_err_Local_req_X_E or L_err_South_req_X_E or L_err_West_req_X_E or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_E_sig_not_empty_E_grant_L_E or err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; -- FIFO W2L_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_Req_L_in or W_err_dst_addr_cur_addr_not_Req_L_in or W_err_header_not_empty_faulty_drop_packet_in or W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or W_err_header_not_empty_faulty_Req_in_all_zero or --W_err_header_not_empty_Req_L_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_Local_Req_L or W_err_Local_grant_L or W_err_South_Req_L or W_err_South_grant_L or W_err_West_Req_L or W_err_West_grant_L or W_err_East_Req_L or W_err_East_grant_L or W_err_IDLE_Req_L or W_err_IDLE_grant_L or W_err_North_Req_L or W_err_North_grant_L or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_West_req_X_W or L_err_West_credit_not_zero_req_X_W_grant_W or L_err_West_credit_zero_or_not_req_X_W_not_grant_W or L_err_East_req_X_W or L_err_IDLE_req_X_W or L_err_North_req_X_W or L_err_Local_req_X_W or L_err_South_req_X_W or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_W_sig_not_empty_W_grant_L_W or err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; -- FIFO S2L_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_Req_L_in or S_err_dst_addr_cur_addr_not_Req_L_in or S_err_header_not_empty_faulty_drop_packet_in or S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or S_err_header_not_empty_faulty_Req_in_all_zero or --S_err_header_not_empty_Req_L_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_Local_Req_L or S_err_Local_grant_L or S_err_South_Req_L or S_err_South_grant_L or S_err_West_Req_L or S_err_West_grant_L or S_err_East_Req_L or S_err_East_grant_L or S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_South_req_X_S or L_err_South_credit_not_zero_req_X_S_grant_S or L_err_South_credit_zero_or_not_req_X_S_not_grant_S or L_err_West_req_X_S or L_err_East_req_X_S or L_err_IDLE_req_X_S or L_err_North_req_X_S or L_err_Local_req_X_S or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Link faults and turn faults -- The order of the turns/paths from left to right (MSB to LSB) -> 20 bits -- N2E, N2W, E2N, E2S, -- W2N, W2S, S2E, S2W, -- N2S, S2N, E2W, W2E, -- L2N, L2E, L2W, L2S, -- N2L, E2L, W2L, S2L ------------------------------------------------------------------------------------------------------------------------------ -- Taking classified fault information to output ------------------------------------------------------------------------------------------------------------------------------ turn_faults <= faulty_N2E_turn_fault & faulty_N2W_turn_fault & faulty_E2N_turn_fault & faulty_E2S_turn_fault & faulty_W2N_turn_fault & faulty_W2S_turn_fault & faulty_S2E_turn_fault & faulty_S2W_turn_fault & faulty_N2S_path_fault & faulty_S2N_path_fault & faulty_E2W_path_fault & faulty_W2E_path_fault & faulty_L2N_fault & faulty_L2E_fault & faulty_L2W_fault & faulty_L2S_fault & faulty_N2L_fault & faulty_E2L_fault & faulty_W2L_fault & faulty_S2L_fault; -- 20 bits because of turn/path faults --link_faults <= '0' & '0' & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L; -- sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L; link_faults <= sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L; ------------------------------------------------------------------------------------------------------------------------------ -- Taking non-classified fault information to output ------------------------------------------------------------------------------------------------------------------------------ turn_faults_async <= N2E_turn_fault & N2W_turn_fault & E2N_turn_fault & E2S_turn_fault & W2N_turn_fault & W2S_turn_fault & S2E_turn_fault & S2W_turn_fault & N2S_path_fault & S2N_path_fault & E2W_path_fault & W2E_path_fault & L2N_fault & L2E_fault & L2W_fault & L2S_fault & N2L_fault & E2L_fault & W2L_fault & S2L_fault; -- 20 bits because of turn/path faults --link_faults_async <= '0' & '0' & faulty_packet_W & faulty_packet_S & faulty_packet_L; -- faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L; link_faults_async <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L; ------------------------------------------------------------------------------------------------------------------------------ Faulty_N_out <= sig_Faulty_N_out; Faulty_E_out <= sig_Faulty_E_out; Faulty_W_out <= sig_Faulty_W_out; Faulty_S_out <= sig_Faulty_S_out; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the counter_threshold modules CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N, Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out); CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E, Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out); CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W, Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out); CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S, Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out); CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L, Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Checker Counter Threshold modules -- Turn faults CHK_CT_N2E_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2E_turn_fault, Healthy_packet => not_N2E_turn_fault, Healthy => Healthy_N2E_turn_fault, Intermittent => intermittent_N2E_turn_fault, Faulty => faulty_N2E_turn_fault); CHK_CT_N2W_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2W_turn_fault, Healthy_packet => not_N2W_turn_fault, Healthy => Healthy_N2W_turn_fault, Intermittent => intermittent_N2W_turn_fault, Faulty => faulty_N2W_turn_fault); CHK_CT_E2N_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2N_turn_fault, Healthy_packet => not_E2N_turn_fault, Healthy => Healthy_E2N_turn_fault, Intermittent => intermittent_E2N_turn_fault, Faulty => faulty_E2N_turn_fault); CHK_CT_E2S_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2S_turn_fault, Healthy_packet => not_E2S_turn_fault, Healthy => Healthy_E2S_turn_fault, Intermittent => intermittent_E2S_turn_fault, Faulty => faulty_E2S_turn_fault); CHK_CT_W2N_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2N_turn_fault, Healthy_packet => not_W2N_turn_fault, Healthy => Healthy_W2N_turn_fault, Intermittent => intermittent_W2N_turn_fault, Faulty => faulty_W2N_turn_fault); CHK_CT_W2S_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2S_turn_fault, Healthy_packet => not_W2S_turn_fault, Healthy => Healthy_W2S_turn_fault, Intermittent => intermittent_W2S_turn_fault, Faulty => faulty_W2S_turn_fault); CHK_CT_S2E_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2E_turn_fault, Healthy_packet => not_S2E_turn_fault, Healthy => Healthy_S2E_turn_fault, Intermittent => intermittent_S2E_turn_fault, Faulty => faulty_S2E_turn_fault); CHK_CT_S2W_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2W_turn_fault, Healthy_packet => not_S2W_turn_fault, Healthy => Healthy_S2W_turn_fault, Intermittent => intermittent_S2W_turn_fault, Faulty => faulty_S2W_turn_fault); --Path faults CHK_CT_N2S_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2S_path_fault, Healthy_packet => not_N2S_path_fault, Healthy => Healthy_N2S_path_fault, Intermittent => intermittent_N2S_path_fault, Faulty => faulty_N2S_path_fault); CHK_CT_S2N_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2N_path_fault, Healthy_packet => not_S2N_path_fault, Healthy => Healthy_S2N_path_fault, Intermittent => intermittent_S2N_path_fault, Faulty => faulty_S2N_path_fault); CHK_CT_E2W_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2W_path_fault, Healthy_packet => not_E2W_path_fault, Healthy => Healthy_E2W_path_fault, Intermittent => intermittent_E2W_path_fault, Faulty => faulty_E2W_path_fault); CHK_CT_W2E_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2E_path_fault, Healthy_packet => not_W2E_path_fault, Healthy => Healthy_W2E_path_fault, Intermittent => intermittent_W2E_path_fault, Faulty => faulty_W2E_path_fault); -- Local port related faults (to/from local port) CHK_CT_L2N_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2N_fault, Healthy_packet => not_L2N_fault, Healthy => Healthy_L2N_fault, Intermittent => intermittent_L2N_fault, Faulty => faulty_L2N_fault); CHK_CT_L2E_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2E_fault, Healthy_packet => not_L2E_fault, Healthy => Healthy_L2E_fault, Intermittent => intermittent_L2E_fault, Faulty => faulty_L2E_fault); CHK_CT_L2W_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2W_fault, Healthy_packet => not_L2W_fault, Healthy => Healthy_L2W_fault, Intermittent => intermittent_L2W_fault, Faulty => faulty_L2W_fault); CHK_CT_L2S_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2S_fault, Healthy_packet => not_L2S_fault, Healthy => Healthy_L2S_fault, Intermittent => intermittent_L2S_fault, Faulty => faulty_L2S_fault); CHK_CT_N2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2L_fault, Healthy_packet => not_N2L_fault, Healthy => Healthy_N2L_fault, Intermittent => intermittent_N2L_fault, Faulty => faulty_N2L_fault); CHK_CT_E2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2L_fault, Healthy_packet => not_E2L_fault, Healthy => Healthy_E2L_fault, Intermittent => intermittent_E2L_fault, Faulty => faulty_E2L_fault); CHK_CT_W2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2L_fault, Healthy_packet => not_W2L_fault, Healthy => Healthy_W2L_fault, Intermittent => intermittent_W2L_fault, Faulty => faulty_W2L_fault); CHK_CT_S2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2L_fault, Healthy_packet => not_S2L_fault, Healthy => Healthy_S2L_fault, Intermittent => intermittent_S2L_fault, Faulty => faulty_S2L_fault); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- All the FIFOs FIFO_N: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N, read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN, credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_FIFO_to_N_FIFO, SO=> fault_DO_serial_N_FIFO_to_E_FIFO, -- Checker outputs -- Functional checkers err_empty_full => N_err_empty_full, err_empty_read_en => N_err_empty_read_en, err_full_write_en => N_err_full_write_en, err_state_in_onehot => N_err_state_in_onehot, err_read_pointer_in_onehot => N_err_read_pointer_in_onehot, err_write_pointer_in_onehot => N_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => N_err_write_en_write_pointer, err_not_write_en_write_pointer => N_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => N_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => N_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => N_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => N_err_read_pointer_write_pointer_full, err_read_pointer_increment => N_err_read_pointer_increment, err_read_pointer_not_increment => N_err_read_pointer_not_increment, err_write_en => N_err_write_en, err_not_write_en => N_err_not_write_en, err_not_write_en1 => N_err_not_write_en1, err_not_write_en2 => N_err_not_write_en2, err_read_en_mismatch => N_err_read_en_mismatch, err_read_en_mismatch1 => N_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => N_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => N_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => N_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => N_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => N_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => N_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => N_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => N_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => N_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => N_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => N_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => N_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => N_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => N_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => N_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => N_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => N_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => N_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => N_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => N_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => N_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_E: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E, read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE, credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_FIFO_to_E_FIFO, SO=> fault_DO_serial_E_FIFO_to_W_FIFO, -- Checker outputs -- Functional checkers err_empty_full => E_err_empty_full, err_empty_read_en => E_err_empty_read_en, err_full_write_en => E_err_full_write_en, err_state_in_onehot => E_err_state_in_onehot, err_read_pointer_in_onehot => E_err_read_pointer_in_onehot, err_write_pointer_in_onehot => E_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => E_err_write_en_write_pointer, err_not_write_en_write_pointer => E_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => E_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => E_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => E_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => E_err_read_pointer_write_pointer_full, err_read_pointer_increment => E_err_read_pointer_increment, err_read_pointer_not_increment => E_err_read_pointer_not_increment, err_write_en => E_err_write_en, err_not_write_en => E_err_not_write_en, err_not_write_en1 => E_err_not_write_en1, err_not_write_en2 => E_err_not_write_en2, err_read_en_mismatch => E_err_read_en_mismatch, err_read_en_mismatch1 => E_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => E_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => E_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => E_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => E_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => E_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => E_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => E_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => E_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => E_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => E_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => E_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => E_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => E_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => E_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => E_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => E_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => E_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => E_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => E_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => E_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_W: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W, read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW, credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_FIFO_to_W_FIFO, SO=> fault_DO_serial_W_FIFO_to_S_FIFO, -- Checker outputs -- Functional checkers err_empty_full => W_err_empty_full, err_empty_read_en => W_err_empty_read_en, err_full_write_en => W_err_full_write_en, err_state_in_onehot => W_err_state_in_onehot, err_read_pointer_in_onehot => W_err_read_pointer_in_onehot, err_write_pointer_in_onehot => W_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => W_err_write_en_write_pointer, err_not_write_en_write_pointer => W_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => W_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => W_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => W_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => W_err_read_pointer_write_pointer_full, err_read_pointer_increment => W_err_read_pointer_increment, err_read_pointer_not_increment => W_err_read_pointer_not_increment, err_write_en => W_err_write_en, err_not_write_en => W_err_not_write_en, err_not_write_en1 => W_err_not_write_en1, err_not_write_en2 => W_err_not_write_en2, err_read_en_mismatch => W_err_read_en_mismatch, err_read_en_mismatch1 => W_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => W_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => W_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => W_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => W_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => W_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => W_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => W_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => W_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => W_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => W_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => W_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => W_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => W_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => W_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => W_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => W_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => W_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => W_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => W_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => W_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_S: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S, read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS, credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_FIFO_to_S_FIFO, SO=> fault_DO_serial_S_FIFO_to_L_LBDR, -- Checker outputs -- Functional checkers err_empty_full => S_err_empty_full, err_empty_read_en => S_err_empty_read_en, err_full_write_en => S_err_full_write_en, err_state_in_onehot => S_err_state_in_onehot, err_read_pointer_in_onehot => S_err_read_pointer_in_onehot, err_write_pointer_in_onehot => S_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => S_err_write_en_write_pointer, err_not_write_en_write_pointer => S_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => S_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => S_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => S_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => S_err_read_pointer_write_pointer_full, err_read_pointer_increment => S_err_read_pointer_increment, err_read_pointer_not_increment => S_err_read_pointer_not_increment, err_write_en => S_err_write_en, err_not_write_en => S_err_not_write_en, err_not_write_en1 => S_err_not_write_en1, err_not_write_en2 => S_err_not_write_en2, err_read_en_mismatch => S_err_read_en_mismatch, err_read_en_mismatch1 => S_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => S_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => S_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => S_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => S_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => S_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => S_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => S_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => S_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => S_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => S_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => S_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => S_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => S_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => S_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => S_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => S_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => S_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => S_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => S_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => S_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_L: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L, read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L, credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L, TCK=> TCK, SE=> SE, UE=> UE, SI=> SI, SO=> fault_DO_serial_L_FIFO_to_N_FIFO, -- Checker outputs -- Functional checkers err_empty_full => L_err_empty_full, err_empty_read_en => L_err_empty_read_en, err_full_write_en => L_err_full_write_en, err_state_in_onehot => L_err_state_in_onehot, err_read_pointer_in_onehot => L_err_read_pointer_in_onehot, err_write_pointer_in_onehot => L_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => L_err_write_en_write_pointer, err_not_write_en_write_pointer => L_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => L_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => L_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => L_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => L_err_read_pointer_write_pointer_full, err_read_pointer_increment => L_err_read_pointer_increment, err_read_pointer_not_increment => L_err_read_pointer_not_increment, err_write_en => L_err_write_en, err_not_write_en => L_err_not_write_en, err_not_write_en1 => L_err_not_write_en1, err_not_write_en2 => L_err_not_write_en2, err_read_en_mismatch => L_err_read_en_mismatch, err_read_en_mismatch1 => L_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => L_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => L_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => L_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => L_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => L_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => L_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => L_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => L_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => L_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => L_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => L_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => L_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => L_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => L_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => L_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => L_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => L_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => L_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => L_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => L_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ parity_LBDR_N: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_N, empty_N, LBDR_Fault_N); parity_LBDR_E: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_E, empty_E, LBDR_Fault_E); parity_LBDR_W: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_W, empty_W, LBDR_Fault_W); parity_LBDR_S: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_S, empty_S, LBDR_Fault_S); parity_LBDR_L: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_L, empty_L, LBDR_Fault_L); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ --- all the LBDRs LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_N, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_N, packet_drop_order => packet_drop_order_N, grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN, Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_LBDR_to_N_LBDR, SO=> fault_DO_serial_N_LBDR_to_E_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => N_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => N_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => N_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => N_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => N_err_grants_onehot, err_grants_mismatch => N_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => N_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => N_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => N_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => N_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => N_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => N_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => N_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => N_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => N_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => N_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => N_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => N_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => N_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => N_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => N_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => N_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => N_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => N_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => N_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => N_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => N_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_E, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_E, packet_drop_order => packet_drop_order_E, grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE, Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_LBDR_to_E_LBDR, SO=> fault_DO_serial_E_LBDR_to_W_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => E_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => E_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => E_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => E_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => E_err_grants_onehot, err_grants_mismatch => E_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => E_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => E_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => E_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => E_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => E_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => E_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => E_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => E_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => E_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => E_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => E_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => E_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => E_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => E_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => E_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => E_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => E_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => E_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => E_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_W, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_W, packet_drop_order => packet_drop_order_W, grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW, Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_LBDR_to_W_LBDR, SO=> fault_DO_serial_W_LBDR_to_S_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => W_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => W_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => W_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => W_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => W_err_grants_onehot, err_grants_mismatch => W_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => W_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => W_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => W_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => W_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => W_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => W_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => W_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => W_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => W_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => W_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => W_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => W_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => W_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => W_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => W_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => W_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => W_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => W_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => W_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_S, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_S, packet_drop_order => packet_drop_order_S, grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS, Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_LBDR_to_S_LBDR, SO=> fault_DO_serial_S_LBDR_to_Allocator, -- Checker outputs err_header_empty_Requests_FF_Requests_in => S_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => S_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => S_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => S_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => S_err_grants_onehot, err_grants_mismatch => S_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => S_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => S_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => S_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => S_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => S_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => S_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => S_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => S_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => S_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => S_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => S_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => S_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => S_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => S_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => S_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => S_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => S_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => S_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => S_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_L, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_L, packet_drop_order => packet_drop_order_L, grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0', Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_FIFO_to_L_LBDR, SO=> fault_DO_serial_L_LBDR_to_N_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => L_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => L_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => L_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => L_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => L_err_grants_onehot, err_grants_mismatch => L_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => L_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => L_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => L_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => L_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => L_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => L_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => L_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => L_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => L_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => L_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => L_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => L_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => L_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => L_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => L_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => L_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => L_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => L_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => L_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- switch allocator allocator_unit: allocator port map ( reset => reset, clk => clk, -- flow control credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L, -- requests from the LBDRS req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL, req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL, req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL, req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL, req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0', empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L, valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L, -- grant_X_Y means the grant for X output port towards Y input port -- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot! grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL, grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL, grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL, grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL, grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_LBDR_to_Allocator, SO=> SO, -- Make sure this is correction -- Also check inside Allocator's logic -- Checker outputs -- Allocator logic checker outputs err_grant_N_N_sig_not_empty_N_grant_N_N => err_grant_N_N_sig_not_empty_N_grant_N_N , err_not_grant_N_N_sig_or_empty_N_not_grant_N_N => err_not_grant_N_N_sig_or_empty_N_not_grant_N_N , err_grant_N_E_sig_not_empty_E_grant_N_E => err_grant_N_E_sig_not_empty_E_grant_N_E , err_not_grant_N_E_sig_or_empty_E_not_grant_N_E => err_not_grant_N_E_sig_or_empty_E_not_grant_N_E , err_grant_N_W_sig_not_empty_W_grant_N_W => err_grant_N_W_sig_not_empty_W_grant_N_W , err_not_grant_N_W_sig_or_empty_W_not_grant_N_W => err_not_grant_N_W_sig_or_empty_W_not_grant_N_W , err_grant_N_S_sig_not_empty_S_grant_N_S => err_grant_N_S_sig_not_empty_S_grant_N_S , err_not_grant_N_S_sig_or_empty_S_not_grant_N_S => err_not_grant_N_S_sig_or_empty_S_not_grant_N_S , err_grant_N_L_sig_not_empty_L_grant_N_L => err_grant_N_L_sig_not_empty_L_grant_N_L , err_not_grant_N_L_sig_or_empty_L_not_grant_N_L => err_not_grant_N_L_sig_or_empty_L_not_grant_N_L , err_grant_E_N_sig_not_empty_N_grant_E_N => err_grant_E_N_sig_not_empty_N_grant_E_N , err_not_grant_E_N_sig_or_empty_N_not_grant_E_N => err_not_grant_E_N_sig_or_empty_N_not_grant_E_N , err_grant_E_E_sig_not_empty_E_grant_E_E => err_grant_E_E_sig_not_empty_E_grant_E_E , err_not_grant_E_E_sig_or_empty_E_not_grant_E_E => err_not_grant_E_E_sig_or_empty_E_not_grant_E_E , err_grant_E_W_sig_not_empty_W_grant_E_W => err_grant_E_W_sig_not_empty_W_grant_E_W , err_not_grant_E_W_sig_or_empty_W_not_grant_E_W => err_not_grant_E_W_sig_or_empty_W_not_grant_E_W , err_grant_E_S_sig_not_empty_S_grant_E_S => err_grant_E_S_sig_not_empty_S_grant_E_S , err_not_grant_E_S_sig_or_empty_S_not_grant_E_S => err_not_grant_E_S_sig_or_empty_S_not_grant_E_S , err_grant_E_L_sig_not_empty_L_grant_E_L => err_grant_E_L_sig_not_empty_L_grant_E_L , err_not_grant_E_L_sig_or_empty_L_not_grant_E_L => err_not_grant_E_L_sig_or_empty_L_not_grant_E_L , err_grant_W_N_sig_not_empty_N_grant_W_N => err_grant_W_N_sig_not_empty_N_grant_W_N , err_not_grant_W_N_sig_or_empty_N_not_grant_W_N => err_not_grant_W_N_sig_or_empty_N_not_grant_W_N , err_grant_W_E_sig_not_empty_E_grant_W_E => err_grant_W_E_sig_not_empty_E_grant_W_E , err_not_grant_W_E_sig_or_empty_E_not_grant_W_E => err_not_grant_W_E_sig_or_empty_E_not_grant_W_E , err_grant_W_W_sig_not_empty_W_grant_W_W => err_grant_W_W_sig_not_empty_W_grant_W_W , err_not_grant_W_W_sig_or_empty_W_not_grant_W_W => err_not_grant_W_W_sig_or_empty_W_not_grant_W_W , err_grant_W_S_sig_not_empty_S_grant_W_S => err_grant_W_S_sig_not_empty_S_grant_W_S , err_not_grant_W_S_sig_or_empty_S_not_grant_W_S => err_not_grant_W_S_sig_or_empty_S_not_grant_W_S , err_grant_W_L_sig_not_empty_L_grant_W_L => err_grant_W_L_sig_not_empty_L_grant_W_L , err_not_grant_W_L_sig_or_empty_L_not_grant_W_L => err_not_grant_W_L_sig_or_empty_L_not_grant_W_L , err_grant_S_N_sig_not_empty_N_grant_S_N => err_grant_S_N_sig_not_empty_N_grant_S_N , err_not_grant_S_N_sig_or_empty_N_not_grant_S_N => err_not_grant_S_N_sig_or_empty_N_not_grant_S_N , err_grant_S_E_sig_not_empty_E_grant_S_E => err_grant_S_E_sig_not_empty_E_grant_S_E , err_not_grant_S_E_sig_or_empty_E_not_grant_S_E => err_not_grant_S_E_sig_or_empty_E_not_grant_S_E , err_grant_S_W_sig_not_empty_W_grant_S_W => err_grant_S_W_sig_not_empty_W_grant_S_W , err_not_grant_S_W_sig_or_empty_W_not_grant_S_W => err_not_grant_S_W_sig_or_empty_W_not_grant_S_W , err_grant_S_S_sig_not_empty_S_grant_S_S => err_grant_S_S_sig_not_empty_S_grant_S_S , err_not_grant_S_S_sig_or_empty_S_not_grant_S_S => err_not_grant_S_S_sig_or_empty_S_not_grant_S_S , err_grant_S_L_sig_not_empty_L_grant_S_L => err_grant_S_L_sig_not_empty_L_grant_S_L , err_not_grant_S_L_sig_or_empty_L_not_grant_S_L => err_not_grant_S_L_sig_or_empty_L_not_grant_S_L , err_grant_L_N_sig_not_empty_N_grant_L_N => err_grant_L_N_sig_not_empty_N_grant_L_N , err_not_grant_L_N_sig_or_empty_N_not_grant_L_N => err_not_grant_L_N_sig_or_empty_N_not_grant_L_N , err_grant_L_E_sig_not_empty_E_grant_L_E => err_grant_L_E_sig_not_empty_E_grant_L_E , err_not_grant_L_E_sig_or_empty_E_not_grant_L_E => err_not_grant_L_E_sig_or_empty_E_not_grant_L_E , err_grant_L_W_sig_not_empty_W_grant_L_W => err_grant_L_W_sig_not_empty_W_grant_L_W , err_not_grant_L_W_sig_or_empty_W_not_grant_L_W => err_not_grant_L_W_sig_or_empty_W_not_grant_L_W , err_grant_L_S_sig_not_empty_S_grant_L_S => err_grant_L_S_sig_not_empty_S_grant_L_S , err_not_grant_L_S_sig_or_empty_S_not_grant_L_S => err_not_grant_L_S_sig_or_empty_S_not_grant_L_S , err_grant_L_L_sig_not_empty_L_grant_L_L => err_grant_L_L_sig_not_empty_L_grant_L_L , err_not_grant_L_L_sig_or_empty_L_not_grant_L_L => err_not_grant_L_L_sig_or_empty_L_not_grant_L_L , err_grant_signals_not_empty_grant_N => err_grant_signals_not_empty_grant_N , err_not_grant_signals_empty_not_grant_N => err_not_grant_signals_empty_not_grant_N , err_grant_signals_not_empty_grant_E => err_grant_signals_not_empty_grant_E , err_not_grant_signals_empty_not_grant_E => err_not_grant_signals_empty_not_grant_E , err_grant_signals_not_empty_grant_W => err_grant_signals_not_empty_grant_W , err_not_grant_signals_empty_not_grant_W => err_not_grant_signals_empty_not_grant_W , err_grant_signals_not_empty_grant_S => err_grant_signals_not_empty_grant_S , err_not_grant_signals_empty_not_grant_S => err_not_grant_signals_empty_not_grant_S , err_grant_signals_not_empty_grant_L => err_grant_signals_not_empty_grant_L , err_not_grant_signals_empty_not_grant_L => err_not_grant_signals_empty_not_grant_L , err_grants_valid_not_match => err_grants_valid_not_match , -- Allocator credit counter logic checker outputs err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal , err_credit_in_N_credit_counter_N_out_increment => err_credit_in_N_credit_counter_N_out_increment , err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change => err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change , err_grant_N_credit_counter_N_out_decrement => err_grant_N_credit_counter_N_out_decrement , err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change => err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change , err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal , err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal , err_credit_in_E_credit_counter_E_out_increment => err_credit_in_E_credit_counter_E_out_increment , err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change => err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change , err_grant_E_credit_counter_E_out_decrement => err_grant_E_credit_counter_E_out_decrement , err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change => err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change , err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal , err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal , err_credit_in_W_credit_counter_W_out_increment => err_credit_in_W_credit_counter_W_out_increment , err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change => err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change , err_grant_W_credit_counter_W_out_decrement => err_grant_W_credit_counter_W_out_decrement , err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change => err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change , err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal , err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal , err_credit_in_S_credit_counter_S_out_increment => err_credit_in_S_credit_counter_S_out_increment , err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change => err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change , err_grant_S_credit_counter_S_out_decrement => err_grant_S_credit_counter_S_out_decrement , err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change => err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change , err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal , err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal , err_credit_in_L_credit_counter_L_out_increment => err_credit_in_L_credit_counter_L_out_increment , err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change => err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change , err_grant_L_credit_counter_L_out_decrement => err_grant_L_credit_counter_L_out_decrement , err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change => err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change , err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal , -- North Arbiter_in Checker outputs N_err_Requests_state_in_state_not_equal => N_err_Requests_state_in_state_not_equal, N_err_IDLE_Req_N => N_err_IDLE_Req_N, N_err_IDLE_grant_N => N_err_IDLE_grant_N, N_err_North_Req_N => N_err_North_Req_N, N_err_North_grant_N => N_err_North_grant_N, N_err_East_Req_E => N_err_East_Req_E, N_err_East_grant_E => N_err_East_grant_E, N_err_West_Req_W => N_err_West_Req_W, N_err_West_grant_W => N_err_West_grant_W, N_err_South_Req_S => N_err_South_Req_S, N_err_South_grant_S => N_err_South_grant_S, N_err_Local_Req_L => N_err_Local_Req_L, N_err_Local_grant_L => N_err_Local_grant_L, N_err_IDLE_Req_E => N_err_IDLE_Req_E, N_err_IDLE_grant_E => N_err_IDLE_grant_E, N_err_North_Req_E => N_err_North_Req_E, N_err_North_grant_E => N_err_North_grant_E, N_err_East_Req_W => N_err_East_Req_W, N_err_East_grant_W => N_err_East_grant_W, N_err_West_Req_S => N_err_West_Req_S, N_err_West_grant_S => N_err_West_grant_S, N_err_South_Req_L => N_err_South_Req_L, N_err_South_grant_L => N_err_South_grant_L, N_err_Local_Req_N => N_err_Local_Req_N, N_err_Local_grant_N => N_err_Local_grant_N, N_err_IDLE_Req_W => N_err_IDLE_Req_W, N_err_IDLE_grant_W => N_err_IDLE_grant_W, N_err_North_Req_W => N_err_North_Req_W, N_err_North_grant_W => N_err_North_grant_W, N_err_East_Req_S => N_err_East_Req_S, N_err_East_grant_S => N_err_East_grant_S, N_err_West_Req_L => N_err_West_Req_L, N_err_West_grant_L => N_err_West_grant_L, N_err_South_Req_N => N_err_South_Req_N, N_err_South_grant_N => N_err_South_grant_N, N_err_Local_Req_E => N_err_Local_Req_E, N_err_Local_grant_E => N_err_Local_grant_E, N_err_IDLE_Req_S => N_err_IDLE_Req_S, N_err_IDLE_grant_S => N_err_IDLE_grant_S, N_err_North_Req_S => N_err_North_Req_S, N_err_North_grant_S => N_err_North_grant_S, N_err_East_Req_L => N_err_East_Req_L, N_err_East_grant_L => N_err_East_grant_L, N_err_West_Req_N => N_err_West_Req_N, N_err_West_grant_N => N_err_West_grant_N, N_err_South_Req_E => N_err_South_Req_E, N_err_South_grant_E => N_err_South_grant_E, N_err_Local_Req_W => N_err_Local_Req_W, N_err_Local_grant_W => N_err_Local_grant_W, N_err_IDLE_Req_L => N_err_IDLE_Req_L, N_err_IDLE_grant_L => N_err_IDLE_grant_L, N_err_North_Req_L => N_err_North_Req_L, N_err_North_grant_L => N_err_North_grant_L, N_err_East_Req_N => N_err_East_Req_N, N_err_East_grant_N => N_err_East_grant_N, N_err_West_Req_E => N_err_West_Req_E, N_err_West_grant_E => N_err_West_grant_E, N_err_South_Req_W => N_err_South_Req_W, N_err_South_grant_W => N_err_South_grant_W, N_err_Local_Req_S => N_err_Local_Req_S, N_err_Local_grant_S => N_err_Local_grant_S, N_err_state_in_onehot => N_err_arbiter_state_in_onehot, N_err_no_request_grants => N_err_no_request_grants, N_err_request_no_grants => N_err_request_no_grants, N_err_no_Req_N_grant_N => N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E => N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W => N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S => N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L => N_err_no_Req_L_grant_L, -- East Arbiter_in Checker outputs E_err_Requests_state_in_state_not_equal => E_err_Requests_state_in_state_not_equal, E_err_IDLE_Req_N => E_err_IDLE_Req_N, E_err_IDLE_grant_N => E_err_IDLE_grant_N, E_err_North_Req_N => E_err_North_Req_N, E_err_North_grant_N => E_err_North_grant_N, E_err_East_Req_E => E_err_East_Req_E, E_err_East_grant_E => E_err_East_grant_E, E_err_West_Req_W => E_err_West_Req_W, E_err_West_grant_W => E_err_West_grant_W, E_err_South_Req_S => E_err_South_Req_S, E_err_South_grant_S => E_err_South_grant_S, E_err_Local_Req_L => E_err_Local_Req_L, E_err_Local_grant_L => E_err_Local_grant_L, E_err_IDLE_Req_E => E_err_IDLE_Req_E, E_err_IDLE_grant_E => E_err_IDLE_grant_E, E_err_North_Req_E => E_err_North_Req_E, E_err_North_grant_E => E_err_North_grant_E, E_err_East_Req_W => E_err_East_Req_W, E_err_East_grant_W => E_err_East_grant_W, E_err_West_Req_S => E_err_West_Req_S, E_err_West_grant_S => E_err_West_grant_S, E_err_South_Req_L => E_err_South_Req_L, E_err_South_grant_L => E_err_South_grant_L, E_err_Local_Req_N => E_err_Local_Req_N, E_err_Local_grant_N => E_err_Local_grant_N, E_err_IDLE_Req_W => E_err_IDLE_Req_W, E_err_IDLE_grant_W => E_err_IDLE_grant_W, E_err_North_Req_W => E_err_North_Req_W, E_err_North_grant_W => E_err_North_grant_W, E_err_East_Req_S => E_err_East_Req_S, E_err_East_grant_S => E_err_East_grant_S, E_err_West_Req_L => E_err_West_Req_L, E_err_West_grant_L => E_err_West_grant_L, E_err_South_Req_N => E_err_South_Req_N, E_err_South_grant_N => E_err_South_grant_N, E_err_Local_Req_E => E_err_Local_Req_E, E_err_Local_grant_E => E_err_Local_grant_E, E_err_IDLE_Req_S => E_err_IDLE_Req_S, E_err_IDLE_grant_S => E_err_IDLE_grant_S, E_err_North_Req_S => E_err_North_Req_S, E_err_North_grant_S => E_err_North_grant_S, E_err_East_Req_L => E_err_East_Req_L, E_err_East_grant_L => E_err_East_grant_L, E_err_West_Req_N => E_err_West_Req_N, E_err_West_grant_N => E_err_West_grant_N, E_err_South_Req_E => E_err_South_Req_E, E_err_South_grant_E => E_err_South_grant_E, E_err_Local_Req_W => E_err_Local_Req_W, E_err_Local_grant_W => E_err_Local_grant_W, E_err_IDLE_Req_L => E_err_IDLE_Req_L, E_err_IDLE_grant_L => E_err_IDLE_grant_L, E_err_North_Req_L => E_err_North_Req_L, E_err_North_grant_L => E_err_North_grant_L, E_err_East_Req_N => E_err_East_Req_N, E_err_East_grant_N => E_err_East_grant_N, E_err_West_Req_E => E_err_West_Req_E, E_err_West_grant_E => E_err_West_grant_E, E_err_South_Req_W => E_err_South_Req_W, E_err_South_grant_W => E_err_South_grant_W, E_err_Local_Req_S => E_err_Local_Req_S, E_err_Local_grant_S => E_err_Local_grant_S, E_err_state_in_onehot => E_err_arbiter_state_in_onehot, E_err_no_request_grants => E_err_no_request_grants, E_err_request_no_grants => E_err_request_no_grants, E_err_no_Req_N_grant_N => E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E => E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W => E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S => E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L => E_err_no_Req_L_grant_L, -- West Arbiter_in Checker outputs W_err_Requests_state_in_state_not_equal => W_err_Requests_state_in_state_not_equal, W_err_IDLE_Req_N => W_err_IDLE_Req_N, W_err_IDLE_grant_N => W_err_IDLE_grant_N, W_err_North_Req_N => W_err_North_Req_N, W_err_North_grant_N => W_err_North_grant_N, W_err_East_Req_E => W_err_East_Req_E, W_err_East_grant_E => W_err_East_grant_E, W_err_West_Req_W => W_err_West_Req_W, W_err_West_grant_W => W_err_West_grant_W, W_err_South_Req_S => W_err_South_Req_S, W_err_South_grant_S => W_err_South_grant_S, W_err_Local_Req_L => W_err_Local_Req_L, W_err_Local_grant_L => W_err_Local_grant_L, W_err_IDLE_Req_E => W_err_IDLE_Req_E, W_err_IDLE_grant_E => W_err_IDLE_grant_E, W_err_North_Req_E => W_err_North_Req_E, W_err_North_grant_E => W_err_North_grant_E, W_err_East_Req_W => W_err_East_Req_W, W_err_East_grant_W => W_err_East_grant_W, W_err_West_Req_S => W_err_West_Req_S, W_err_West_grant_S => W_err_West_grant_S, W_err_South_Req_L => W_err_South_Req_L, W_err_South_grant_L => W_err_South_grant_L, W_err_Local_Req_N => W_err_Local_Req_N, W_err_Local_grant_N => W_err_Local_grant_N, W_err_IDLE_Req_W => W_err_IDLE_Req_W, W_err_IDLE_grant_W => W_err_IDLE_grant_W, W_err_North_Req_W => W_err_North_Req_W, W_err_North_grant_W => W_err_North_grant_W, W_err_East_Req_S => W_err_East_Req_S, W_err_East_grant_S => W_err_East_grant_S, W_err_West_Req_L => W_err_West_Req_L, W_err_West_grant_L => W_err_West_grant_L, W_err_South_Req_N => W_err_South_Req_N, W_err_South_grant_N => W_err_South_grant_N, W_err_Local_Req_E => W_err_Local_Req_E, W_err_Local_grant_E => W_err_Local_grant_E, W_err_IDLE_Req_S => W_err_IDLE_Req_S, W_err_IDLE_grant_S => W_err_IDLE_grant_S, W_err_North_Req_S => W_err_North_Req_S, W_err_North_grant_S => W_err_North_grant_S, W_err_East_Req_L => W_err_East_Req_L, W_err_East_grant_L => W_err_East_grant_L, W_err_West_Req_N => W_err_West_Req_N, W_err_West_grant_N => W_err_West_grant_N, W_err_South_Req_E => W_err_South_Req_E, W_err_South_grant_E => W_err_South_grant_E, W_err_Local_Req_W => W_err_Local_Req_W, W_err_Local_grant_W => W_err_Local_grant_W, W_err_IDLE_Req_L => W_err_IDLE_Req_L, W_err_IDLE_grant_L => W_err_IDLE_grant_L, W_err_North_Req_L => W_err_North_Req_L, W_err_North_grant_L => W_err_North_grant_L, W_err_East_Req_N => W_err_East_Req_N, W_err_East_grant_N => W_err_East_grant_N, W_err_West_Req_E => W_err_West_Req_E, W_err_West_grant_E => W_err_West_grant_E, W_err_South_Req_W => W_err_South_Req_W, W_err_South_grant_W => W_err_South_grant_W, W_err_Local_Req_S => W_err_Local_Req_S, W_err_Local_grant_S => W_err_Local_grant_S, W_err_state_in_onehot => W_err_arbiter_state_in_onehot, W_err_no_request_grants => W_err_no_request_grants, W_err_request_no_grants => W_err_request_no_grants, W_err_no_Req_N_grant_N => W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E => W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W => W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S => W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L => W_err_no_Req_L_grant_L, -- South Arbiter_in Checker outputs S_err_Requests_state_in_state_not_equal => S_err_Requests_state_in_state_not_equal, S_err_IDLE_Req_N => S_err_IDLE_Req_N, S_err_IDLE_grant_N => S_err_IDLE_grant_N, S_err_North_Req_N => S_err_North_Req_N, S_err_North_grant_N => S_err_North_grant_N, S_err_East_Req_E => S_err_East_Req_E, S_err_East_grant_E => S_err_East_grant_E, S_err_West_Req_W => S_err_West_Req_W, S_err_West_grant_W => S_err_West_grant_W, S_err_South_Req_S => S_err_South_Req_S, S_err_South_grant_S => S_err_South_grant_S, S_err_Local_Req_L => S_err_Local_Req_L, S_err_Local_grant_L => S_err_Local_grant_L, S_err_IDLE_Req_E => S_err_IDLE_Req_E, S_err_IDLE_grant_E => S_err_IDLE_grant_E, S_err_North_Req_E => S_err_North_Req_E, S_err_North_grant_E => S_err_North_grant_E, S_err_East_Req_W => S_err_East_Req_W, S_err_East_grant_W => S_err_East_grant_W, S_err_West_Req_S => S_err_West_Req_S, S_err_West_grant_S => S_err_West_grant_S, S_err_South_Req_L => S_err_South_Req_L, S_err_South_grant_L => S_err_South_grant_L, S_err_Local_Req_N => S_err_Local_Req_N, S_err_Local_grant_N => S_err_Local_grant_N, S_err_IDLE_Req_W => S_err_IDLE_Req_W, S_err_IDLE_grant_W => S_err_IDLE_grant_W, S_err_North_Req_W => S_err_North_Req_W, S_err_North_grant_W => S_err_North_grant_W, S_err_East_Req_S => S_err_East_Req_S, S_err_East_grant_S => S_err_East_grant_S, S_err_West_Req_L => S_err_West_Req_L, S_err_West_grant_L => S_err_West_grant_L, S_err_South_Req_N => S_err_South_Req_N, S_err_South_grant_N => S_err_South_grant_N, S_err_Local_Req_E => S_err_Local_Req_E, S_err_Local_grant_E => S_err_Local_grant_E, S_err_IDLE_Req_S => S_err_IDLE_Req_S, S_err_IDLE_grant_S => S_err_IDLE_grant_S, S_err_North_Req_S => S_err_North_Req_S, S_err_North_grant_S => S_err_North_grant_S, S_err_East_Req_L => S_err_East_Req_L, S_err_East_grant_L => S_err_East_grant_L, S_err_West_Req_N => S_err_West_Req_N, S_err_West_grant_N => S_err_West_grant_N, S_err_South_Req_E => S_err_South_Req_E, S_err_South_grant_E => S_err_South_grant_E, S_err_Local_Req_W => S_err_Local_Req_W, S_err_Local_grant_W => S_err_Local_grant_W, S_err_IDLE_Req_L => S_err_IDLE_Req_L, S_err_IDLE_grant_L => S_err_IDLE_grant_L, S_err_North_Req_L => S_err_North_Req_L, S_err_North_grant_L => S_err_North_grant_L, S_err_East_Req_N => S_err_East_Req_N, S_err_East_grant_N => S_err_East_grant_N, S_err_West_Req_E => S_err_West_Req_E, S_err_West_grant_E => S_err_West_grant_E, S_err_South_Req_W => S_err_South_Req_W, S_err_South_grant_W => S_err_South_grant_W, S_err_Local_Req_S => S_err_Local_Req_S, S_err_Local_grant_S => S_err_Local_grant_S, S_err_state_in_onehot => S_err_arbiter_state_in_onehot, S_err_no_request_grants => S_err_no_request_grants, S_err_request_no_grants => S_err_request_no_grants, S_err_no_Req_N_grant_N => S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E => S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W => S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S => S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L => S_err_no_Req_L_grant_L, -- Local Arbiter_in Checker outputs L_err_Requests_state_in_state_not_equal => L_err_Requests_state_in_state_not_equal, L_err_IDLE_Req_N => L_err_IDLE_Req_N, L_err_IDLE_grant_N => L_err_IDLE_grant_N, L_err_North_Req_N => L_err_North_Req_N, L_err_North_grant_N => L_err_North_grant_N, L_err_East_Req_E => L_err_East_Req_E, L_err_East_grant_E => L_err_East_grant_E, L_err_West_Req_W => L_err_West_Req_W, L_err_West_grant_W => L_err_West_grant_W, L_err_South_Req_S => L_err_South_Req_S, L_err_South_grant_S => L_err_South_grant_S, L_err_Local_Req_L => L_err_Local_Req_L, L_err_Local_grant_L => L_err_Local_grant_L, L_err_IDLE_Req_E => L_err_IDLE_Req_E, L_err_IDLE_grant_E => L_err_IDLE_grant_E, L_err_North_Req_E => L_err_North_Req_E, L_err_North_grant_E => L_err_North_grant_E, L_err_East_Req_W => L_err_East_Req_W, L_err_East_grant_W => L_err_East_grant_W, L_err_West_Req_S => L_err_West_Req_S, L_err_West_grant_S => L_err_West_grant_S, L_err_South_Req_L => L_err_South_Req_L, L_err_South_grant_L => L_err_South_grant_L, L_err_Local_Req_N => L_err_Local_Req_N, L_err_Local_grant_N => L_err_Local_grant_N, L_err_IDLE_Req_W => L_err_IDLE_Req_W, L_err_IDLE_grant_W => L_err_IDLE_grant_W, L_err_North_Req_W => L_err_North_Req_W, L_err_North_grant_W => L_err_North_grant_W, L_err_East_Req_S => L_err_East_Req_S, L_err_East_grant_S => L_err_East_grant_S, L_err_West_Req_L => L_err_West_Req_L, L_err_West_grant_L => L_err_West_grant_L, L_err_South_Req_N => L_err_South_Req_N, L_err_South_grant_N => L_err_South_grant_N, L_err_Local_Req_E => L_err_Local_Req_E, L_err_Local_grant_E => L_err_Local_grant_E, L_err_IDLE_Req_S => L_err_IDLE_Req_S, L_err_IDLE_grant_S => L_err_IDLE_grant_S, L_err_North_Req_S => L_err_North_Req_S, L_err_North_grant_S => L_err_North_grant_S, L_err_East_Req_L => L_err_East_Req_L, L_err_East_grant_L => L_err_East_grant_L, L_err_West_Req_N => L_err_West_Req_N, L_err_West_grant_N => L_err_West_grant_N, L_err_South_Req_E => L_err_South_Req_E, L_err_South_grant_E => L_err_South_grant_E, L_err_Local_Req_W => L_err_Local_Req_W, L_err_Local_grant_W => L_err_Local_grant_W, L_err_IDLE_Req_L => L_err_IDLE_Req_L, L_err_IDLE_grant_L => L_err_IDLE_grant_L, L_err_North_Req_L => L_err_North_Req_L, L_err_North_grant_L => L_err_North_grant_L, L_err_East_Req_N => L_err_East_Req_N, L_err_East_grant_N => L_err_East_grant_N, L_err_West_Req_E => L_err_West_Req_E, L_err_West_grant_E => L_err_West_grant_E, L_err_South_Req_W => L_err_South_Req_W, L_err_South_grant_W => L_err_South_grant_W, L_err_Local_Req_S => L_err_Local_Req_S, L_err_Local_grant_S => L_err_Local_grant_S, L_err_state_in_onehot => L_err_arbiter_state_in_onehot, L_err_no_request_grants => L_err_no_request_grants, L_err_request_no_grants => L_err_request_no_grants, L_err_no_Req_N_grant_N => L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E => L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W => L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S => L_err_no_Req_S_grant_S, L_err_no_Req_L_grant_L => L_err_no_Req_L_grant_L, -- Arbiter_out checker outputs -- North Arbiter_out checker outputs N_arbiter_out_err_Requests_state_in_state_not_equal => N_arbiter_out_err_Requests_state_in_state_not_equal, N_err_IDLE_req_X_N => N_err_IDLE_req_X_N, N_err_North_req_X_N => N_err_North_req_X_N, N_err_North_credit_not_zero_req_X_N_grant_N => N_err_North_credit_not_zero_req_X_N_grant_N, N_err_North_credit_zero_or_not_req_X_N_not_grant_N => N_err_North_credit_zero_or_not_req_X_N_not_grant_N, N_err_East_req_X_E => N_err_East_req_X_E, N_err_East_credit_not_zero_req_X_E_grant_E => N_err_East_credit_not_zero_req_X_E_grant_E, N_err_East_credit_zero_or_not_req_X_E_not_grant_E => N_err_East_credit_zero_or_not_req_X_E_not_grant_E, N_err_West_req_X_W => N_err_West_req_X_W, N_err_West_credit_not_zero_req_X_W_grant_W => N_err_West_credit_not_zero_req_X_W_grant_W, N_err_West_credit_zero_or_not_req_X_W_not_grant_W => N_err_West_credit_zero_or_not_req_X_W_not_grant_W, N_err_South_req_X_S => N_err_South_req_X_S, N_err_South_credit_not_zero_req_X_S_grant_S => N_err_South_credit_not_zero_req_X_S_grant_S, N_err_South_credit_zero_or_not_req_X_S_not_grant_S => N_err_South_credit_zero_or_not_req_X_S_not_grant_S, N_err_Local_req_X_L => N_err_Local_req_X_L, N_err_Local_credit_not_zero_req_X_L_grant_L => N_err_Local_credit_not_zero_req_X_L_grant_L, N_err_Local_credit_zero_or_not_req_X_L_not_grant_L => N_err_Local_credit_zero_or_not_req_X_L_not_grant_L, N_err_IDLE_req_X_E => N_err_IDLE_req_X_E, N_err_North_req_X_E => N_err_North_req_X_E, N_err_East_req_X_W => N_err_East_req_X_W, N_err_West_req_X_S => N_err_West_req_X_S, N_err_South_req_X_L => N_err_South_req_X_L, N_err_Local_req_X_N => N_err_Local_req_X_N, N_err_IDLE_req_X_W => N_err_IDLE_req_X_W, N_err_North_req_X_W => N_err_North_req_X_W, N_err_East_req_X_S => N_err_East_req_X_S, N_err_West_req_X_L => N_err_West_req_X_L, N_err_South_req_X_N => N_err_South_req_X_N, N_err_Local_req_X_E => N_err_Local_req_X_E, N_err_IDLE_req_X_S => N_err_IDLE_req_X_S, N_err_North_req_X_S => N_err_North_req_X_S, N_err_East_req_X_L => N_err_East_req_X_L, N_err_West_req_X_N => N_err_West_req_X_N, N_err_South_req_X_E => N_err_South_req_X_E, N_err_Local_req_X_W => N_err_Local_req_X_W, N_err_IDLE_req_X_L => N_err_IDLE_req_X_L, N_err_North_req_X_L => N_err_North_req_X_L, N_err_East_req_X_N => N_err_East_req_X_N, N_err_West_req_X_E => N_err_West_req_X_E, N_err_South_req_X_W => N_err_South_req_X_W, N_err_Local_req_X_S => N_err_Local_req_X_S, N_arbiter_out_err_state_in_onehot => N_arbiter_out_err_state_in_onehot, N_arbiter_out_err_no_request_grants => N_arbiter_out_err_no_request_grants, N_err_request_IDLE_state => N_err_request_IDLE_state, N_err_request_IDLE_not_Grants => N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant => N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant => N_err_state_East_Invalid_Grant, N_err_state_West_Invalid_Grant => N_err_state_West_Invalid_Grant, N_err_state_South_Invalid_Grant => N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant => N_err_state_Local_Invalid_Grant, N_err_Grants_onehot_or_all_zero => N_err_Grants_onehot_or_all_zero, -- East Arbiter_out checker outputs E_arbiter_out_err_Requests_state_in_state_not_equal => E_arbiter_out_err_Requests_state_in_state_not_equal, E_err_IDLE_req_X_N => E_err_IDLE_req_X_N, E_err_North_req_X_N => E_err_North_req_X_N, E_err_North_credit_not_zero_req_X_N_grant_N => E_err_North_credit_not_zero_req_X_N_grant_N, E_err_North_credit_zero_or_not_req_X_N_not_grant_N => E_err_North_credit_zero_or_not_req_X_N_not_grant_N, E_err_East_req_X_E => E_err_East_req_X_E, E_err_East_credit_not_zero_req_X_E_grant_E => E_err_East_credit_not_zero_req_X_E_grant_E, E_err_East_credit_zero_or_not_req_X_E_not_grant_E => E_err_East_credit_zero_or_not_req_X_E_not_grant_E, E_err_West_req_X_W => E_err_West_req_X_W, E_err_West_credit_not_zero_req_X_W_grant_W => E_err_West_credit_not_zero_req_X_W_grant_W, E_err_West_credit_zero_or_not_req_X_W_not_grant_W => E_err_West_credit_zero_or_not_req_X_W_not_grant_W, E_err_South_req_X_S => E_err_South_req_X_S, E_err_South_credit_not_zero_req_X_S_grant_S => E_err_South_credit_not_zero_req_X_S_grant_S, E_err_South_credit_zero_or_not_req_X_S_not_grant_S => E_err_South_credit_zero_or_not_req_X_S_not_grant_S, E_err_Local_req_X_L => E_err_Local_req_X_L, E_err_Local_credit_not_zero_req_X_L_grant_L => E_err_Local_credit_not_zero_req_X_L_grant_L, E_err_Local_credit_zero_or_not_req_X_L_not_grant_L => E_err_Local_credit_zero_or_not_req_X_L_not_grant_L, E_err_IDLE_req_X_E => E_err_IDLE_req_X_E, E_err_North_req_X_E => E_err_North_req_X_E, E_err_East_req_X_W => E_err_East_req_X_W, E_err_West_req_X_S => E_err_West_req_X_S, E_err_South_req_X_L => E_err_South_req_X_L, E_err_Local_req_X_N => E_err_Local_req_X_N, E_err_IDLE_req_X_W => E_err_IDLE_req_X_W, E_err_North_req_X_W => E_err_North_req_X_W, E_err_East_req_X_S => E_err_East_req_X_S, E_err_West_req_X_L => E_err_West_req_X_L, E_err_South_req_X_N => E_err_South_req_X_N, E_err_Local_req_X_E => E_err_Local_req_X_E, E_err_IDLE_req_X_S => E_err_IDLE_req_X_S, E_err_North_req_X_S => E_err_North_req_X_S, E_err_East_req_X_L => E_err_East_req_X_L, E_err_West_req_X_N => E_err_West_req_X_N, E_err_South_req_X_E => E_err_South_req_X_E, E_err_Local_req_X_W => E_err_Local_req_X_W, E_err_IDLE_req_X_L => E_err_IDLE_req_X_L, E_err_North_req_X_L => E_err_North_req_X_L, E_err_East_req_X_N => E_err_East_req_X_N, E_err_West_req_X_E => E_err_West_req_X_E, E_err_South_req_X_W => E_err_South_req_X_W, E_err_Local_req_X_S => E_err_Local_req_X_S, E_arbiter_out_err_state_in_onehot => E_arbiter_out_err_state_in_onehot, E_arbiter_out_err_no_request_grants => E_arbiter_out_err_no_request_grants, E_err_request_IDLE_state => E_err_request_IDLE_state, E_err_request_IDLE_not_Grants => E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant => E_err_state_North_Invalid_Grant, E_err_state_East_Invalid_Grant => E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant => E_err_state_West_Invalid_Grant, E_err_state_South_Invalid_Grant => E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant => E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero => E_err_Grants_onehot_or_all_zero, -- West Arbiter_out checker outputs W_arbiter_out_err_Requests_state_in_state_not_equal => W_arbiter_out_err_Requests_state_in_state_not_equal, W_err_IDLE_req_X_N => W_err_IDLE_req_X_N, W_err_North_req_X_N => W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N => W_err_North_credit_not_zero_req_X_N_grant_N, W_err_North_credit_zero_or_not_req_X_N_not_grant_N => W_err_North_credit_zero_or_not_req_X_N_not_grant_N, W_err_East_req_X_E => W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E => W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E => W_err_East_credit_zero_or_not_req_X_E_not_grant_E, W_err_West_req_X_W => W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W => W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W => W_err_West_credit_zero_or_not_req_X_W_not_grant_W, W_err_South_req_X_S => W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S => W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S => W_err_South_credit_zero_or_not_req_X_S_not_grant_S, W_err_Local_req_X_L => W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L => W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L => W_err_Local_credit_zero_or_not_req_X_L_not_grant_L, W_err_IDLE_req_X_E => W_err_IDLE_req_X_E, W_err_North_req_X_E => W_err_North_req_X_E, W_err_East_req_X_W => W_err_East_req_X_W, W_err_West_req_X_S => W_err_West_req_X_S, W_err_South_req_X_L => W_err_South_req_X_L, W_err_Local_req_X_N => W_err_Local_req_X_N, W_err_IDLE_req_X_W => W_err_IDLE_req_X_W, W_err_North_req_X_W => W_err_North_req_X_W, W_err_East_req_X_S => W_err_East_req_X_S, W_err_West_req_X_L => W_err_West_req_X_L, W_err_South_req_X_N => W_err_South_req_X_N, W_err_Local_req_X_E => W_err_Local_req_X_E, W_err_IDLE_req_X_S => W_err_IDLE_req_X_S, W_err_North_req_X_S => W_err_North_req_X_S, W_err_East_req_X_L => W_err_East_req_X_L, W_err_West_req_X_N => W_err_West_req_X_N, W_err_South_req_X_E => W_err_South_req_X_E, W_err_Local_req_X_W => W_err_Local_req_X_W, W_err_IDLE_req_X_L => W_err_IDLE_req_X_L, W_err_North_req_X_L => W_err_North_req_X_L, W_err_East_req_X_N => W_err_East_req_X_N, W_err_West_req_X_E => W_err_West_req_X_E, W_err_South_req_X_W => W_err_South_req_X_W, W_err_Local_req_X_S => W_err_Local_req_X_S, W_arbiter_out_err_state_in_onehot => W_arbiter_out_err_state_in_onehot, W_arbiter_out_err_no_request_grants => W_arbiter_out_err_no_request_grants, W_err_request_IDLE_state => W_err_request_IDLE_state, W_err_request_IDLE_not_Grants => W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant => W_err_state_North_Invalid_Grant, W_err_state_East_Invalid_Grant => W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant => W_err_state_West_Invalid_Grant, W_err_state_South_Invalid_Grant => W_err_state_South_Invalid_Grant, W_err_state_Local_Invalid_Grant => W_err_state_Local_Invalid_Grant, W_err_Grants_onehot_or_all_zero => W_err_Grants_onehot_or_all_zero, -- South Arbiter_out checker outputs S_arbiter_out_err_Requests_state_in_state_not_equal => S_arbiter_out_err_Requests_state_in_state_not_equal, S_err_IDLE_req_X_N => S_err_IDLE_req_X_N, S_err_North_req_X_N => S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N => S_err_North_credit_not_zero_req_X_N_grant_N, S_err_North_credit_zero_or_not_req_X_N_not_grant_N => S_err_North_credit_zero_or_not_req_X_N_not_grant_N, S_err_East_req_X_E => S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E => S_err_East_credit_not_zero_req_X_E_grant_E, S_err_East_credit_zero_or_not_req_X_E_not_grant_E => S_err_East_credit_zero_or_not_req_X_E_not_grant_E, S_err_West_req_X_W => S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W => S_err_West_credit_not_zero_req_X_W_grant_W, S_err_West_credit_zero_or_not_req_X_W_not_grant_W => S_err_West_credit_zero_or_not_req_X_W_not_grant_W, S_err_South_req_X_S => S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S => S_err_South_credit_not_zero_req_X_S_grant_S, S_err_South_credit_zero_or_not_req_X_S_not_grant_S => S_err_South_credit_zero_or_not_req_X_S_not_grant_S, S_err_Local_req_X_L => S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L => S_err_Local_credit_not_zero_req_X_L_grant_L, S_err_Local_credit_zero_or_not_req_X_L_not_grant_L => S_err_Local_credit_zero_or_not_req_X_L_not_grant_L, S_err_IDLE_req_X_E => S_err_IDLE_req_X_E, S_err_North_req_X_E => S_err_North_req_X_E, S_err_East_req_X_W => S_err_East_req_X_W, S_err_West_req_X_S => S_err_West_req_X_S, S_err_South_req_X_L => S_err_South_req_X_L, S_err_Local_req_X_N => S_err_Local_req_X_N, S_err_IDLE_req_X_W => S_err_IDLE_req_X_W, S_err_North_req_X_W => S_err_North_req_X_W, S_err_East_req_X_S => S_err_East_req_X_S, S_err_West_req_X_L => S_err_West_req_X_L, S_err_South_req_X_N => S_err_South_req_X_N, S_err_Local_req_X_E => S_err_Local_req_X_E, S_err_IDLE_req_X_S => S_err_IDLE_req_X_S, S_err_North_req_X_S => S_err_North_req_X_S, S_err_East_req_X_L => S_err_East_req_X_L, S_err_West_req_X_N => S_err_West_req_X_N, S_err_South_req_X_E => S_err_South_req_X_E, S_err_Local_req_X_W => S_err_Local_req_X_W, S_err_IDLE_req_X_L => S_err_IDLE_req_X_L, S_err_North_req_X_L => S_err_North_req_X_L, S_err_East_req_X_N => S_err_East_req_X_N, S_err_West_req_X_E => S_err_West_req_X_E, S_err_South_req_X_W => S_err_South_req_X_W, S_err_Local_req_X_S => S_err_Local_req_X_S, S_arbiter_out_err_state_in_onehot => S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants => S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state => S_err_request_IDLE_state, S_err_request_IDLE_not_Grants => S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant => S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant => S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant => S_err_state_West_Invalid_Grant, S_err_state_South_Invalid_Grant => S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant => S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero => S_err_Grants_onehot_or_all_zero, -- Local Arbiter_out checker outputs L_arbiter_out_err_Requests_state_in_state_not_equal => L_arbiter_out_err_Requests_state_in_state_not_equal, L_err_IDLE_req_X_N => L_err_IDLE_req_X_N, L_err_North_req_X_N => L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N => L_err_North_credit_not_zero_req_X_N_grant_N, L_err_North_credit_zero_or_not_req_X_N_not_grant_N => L_err_North_credit_zero_or_not_req_X_N_not_grant_N, L_err_East_req_X_E => L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E => L_err_East_credit_not_zero_req_X_E_grant_E, L_err_East_credit_zero_or_not_req_X_E_not_grant_E => L_err_East_credit_zero_or_not_req_X_E_not_grant_E, L_err_West_req_X_W => L_err_West_req_X_W, L_err_West_credit_not_zero_req_X_W_grant_W => L_err_West_credit_not_zero_req_X_W_grant_W, L_err_West_credit_zero_or_not_req_X_W_not_grant_W => L_err_West_credit_zero_or_not_req_X_W_not_grant_W, L_err_South_req_X_S => L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S => L_err_South_credit_not_zero_req_X_S_grant_S, L_err_South_credit_zero_or_not_req_X_S_not_grant_S => L_err_South_credit_zero_or_not_req_X_S_not_grant_S, L_err_Local_req_X_L => L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L => L_err_Local_credit_not_zero_req_X_L_grant_L, L_err_Local_credit_zero_or_not_req_X_L_not_grant_L => L_err_Local_credit_zero_or_not_req_X_L_not_grant_L, L_err_IDLE_req_X_E => L_err_IDLE_req_X_E, L_err_North_req_X_E => L_err_North_req_X_E, L_err_East_req_X_W => L_err_East_req_X_W, L_err_West_req_X_S => L_err_West_req_X_S, L_err_South_req_X_L => L_err_South_req_X_L, L_err_Local_req_X_N => L_err_Local_req_X_N, L_err_IDLE_req_X_W => L_err_IDLE_req_X_W, L_err_North_req_X_W => L_err_North_req_X_W, L_err_East_req_X_S => L_err_East_req_X_S, L_err_West_req_X_L => L_err_West_req_X_L, L_err_South_req_X_N => L_err_South_req_X_N, L_err_Local_req_X_E => L_err_Local_req_X_E, L_err_IDLE_req_X_S => L_err_IDLE_req_X_S, L_err_North_req_X_S => L_err_North_req_X_S, L_err_East_req_X_L => L_err_East_req_X_L, L_err_West_req_X_N => L_err_West_req_X_N, L_err_South_req_X_E => L_err_South_req_X_E, L_err_Local_req_X_W => L_err_Local_req_X_W, L_err_IDLE_req_X_L => L_err_IDLE_req_X_L, L_err_North_req_X_L => L_err_North_req_X_L, L_err_East_req_X_N => L_err_East_req_X_N, L_err_West_req_X_E => L_err_West_req_X_E, L_err_South_req_X_W => L_err_South_req_X_W, L_err_Local_req_X_S => L_err_Local_req_X_S, L_arbiter_out_err_state_in_onehot => L_arbiter_out_err_state_in_onehot, L_arbiter_out_err_no_request_grants => L_arbiter_out_err_no_request_grants, L_err_request_IDLE_state => L_err_request_IDLE_state, L_err_request_IDLE_not_Grants => L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant => L_err_state_North_Invalid_Grant, L_err_state_East_Invalid_Grant => L_err_state_East_Invalid_Grant, L_err_state_West_Invalid_Grant => L_err_state_West_Invalid_Grant, L_err_state_South_Invalid_Grant => L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant => L_err_state_Local_Invalid_Grant, L_err_Grants_onehot_or_all_zero => L_err_Grants_onehot_or_all_zero ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Xbar select_signals Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL; Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL; Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL; Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL; Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0'; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Xbars -- all the Xbars XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_N, Data_out=> TX_N); XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_E, Data_out=> TX_E); XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_W, Data_out=> TX_W); XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_S, Data_out=> TX_S); XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_L, Data_out=> TX_L); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ end;
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.std_logic_misc.all; use work.component_pack.all; entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping generic ( DATA_WIDTH: integer := 32; current_address : integer := 0; Rxy_rst : integer := 10; Cx_rst : integer := 10; healthy_counter_threshold : integer := 8; faulty_counter_threshold: integer := 2; counter_depth: integer := 4; NoC_size: integer := 4 ); port ( reset, clk: in std_logic; RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0); credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic; valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic; valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic; credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic; TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0); Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic; Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic; -- should be connected to NI (Outputs for classified fault information) link_faults: out std_logic_vector(4 downto 0); turn_faults: out std_logic_vector(19 downto 0); Rxy_reconf_PE: in std_logic_vector(7 downto 0); Cx_reconf_PE: in std_logic_vector(3 downto 0); Reconfig_command : in std_logic; -- fault injector shift register with serial input signals TCK: in std_logic; SE: in std_logic; -- shift enable UE: in std_logic; -- update enable SI: in std_logic; -- serial Input SO: out std_logic; -- serial output ---- Outputs for non-classified fault information link_faults_async: out std_logic_vector(4 downto 0); turn_faults_async: out std_logic_vector(19 downto 0) ); end router_credit_based_PD_C_SHMU; architecture behavior of router_credit_based_PD_C_SHMU is ------------------------------- -- Added because of Checkers -- ------------------------------- --signal combined_error_signals: std_logic_vector(19 downto 0); -- Shall we only consider this for the 20 bits showing the turn faults or individual checkers ?! --signal shift_parallel_data: std_logic_vector(19 downto 0); ------------------------------- ------------------------------- signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0); -- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic; signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic; signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic; signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic; signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic; signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic; signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic; signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic; signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic; signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic; signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic; signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0); signal LBDR_Fault_N, LBDR_Fault_E, LBDR_Fault_W, LBDR_Fault_S, LBDR_Fault_L: std_logic; signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic; signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic; signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic; -- Signals related to link fault classification modules signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic; signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic; signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic; -- Signals related to Control part checkers fault classification modules signal Healthy_N2E_turn_fault, intermittent_N2E_turn_fault, faulty_N2E_turn_fault: std_logic; signal Healthy_N2W_turn_fault, intermittent_N2W_turn_fault, faulty_N2W_turn_fault: std_logic; signal Healthy_E2N_turn_fault, intermittent_E2N_turn_fault, faulty_E2N_turn_fault: std_logic; signal Healthy_E2S_turn_fault, intermittent_E2S_turn_fault, faulty_E2S_turn_fault: std_logic; signal Healthy_W2N_turn_fault, intermittent_W2N_turn_fault, faulty_W2N_turn_fault: std_logic; signal Healthy_W2S_turn_fault, intermittent_W2S_turn_fault, faulty_W2S_turn_fault: std_logic; signal Healthy_S2E_turn_fault, intermittent_S2E_turn_fault, faulty_S2E_turn_fault: std_logic; signal Healthy_S2W_turn_fault, intermittent_S2W_turn_fault, faulty_S2W_turn_fault: std_logic; signal Healthy_N2S_path_fault, intermittent_N2S_path_fault, faulty_N2S_path_fault: std_logic; signal Healthy_S2N_path_fault, intermittent_S2N_path_fault, faulty_S2N_path_fault: std_logic; signal Healthy_E2W_path_fault, intermittent_E2W_path_fault, faulty_E2W_path_fault: std_logic; signal Healthy_W2E_path_fault, intermittent_W2E_path_fault, faulty_W2E_path_fault: std_logic; signal Healthy_L2N_fault, intermittent_L2N_fault, faulty_L2N_fault: std_logic; signal Healthy_L2E_fault, intermittent_L2E_fault, faulty_L2E_fault: std_logic; signal Healthy_L2W_fault, intermittent_L2W_fault, faulty_L2W_fault: std_logic; signal Healthy_L2S_fault, intermittent_L2S_fault, faulty_L2S_fault: std_logic; signal Healthy_N2L_fault, intermittent_N2L_fault, faulty_N2L_fault: std_logic; signal Healthy_E2L_fault, intermittent_E2L_fault, faulty_E2L_fault: std_logic; signal Healthy_W2L_fault, intermittent_W2L_fault, faulty_W2L_fault: std_logic; signal Healthy_S2L_fault, intermittent_S2L_fault, faulty_S2L_fault: std_logic; -- Signals needed for control part checkers -- Signals needed for LBDR packet drop checkers -- North signal N_err_header_empty_Requests_FF_Requests_in, N_err_tail_Requests_in_all_zero, N_err_tail_empty_Requests_FF_Requests_in, N_err_tail_not_empty_not_grants_Requests_FF_Requests_in, N_err_grants_onehot, N_err_grants_mismatch, N_err_header_tail_Requests_FF_Requests_in, N_err_dst_addr_cur_addr_N1, N_err_dst_addr_cur_addr_not_N1, N_err_dst_addr_cur_addr_E1, N_err_dst_addr_cur_addr_not_E1, N_err_dst_addr_cur_addr_W1, N_err_dst_addr_cur_addr_not_W1, N_err_dst_addr_cur_addr_S1, N_err_dst_addr_cur_addr_not_S1, N_err_dst_addr_cur_addr_Req_L_in, N_err_dst_addr_cur_addr_not_Req_L_in, N_err_header_not_empty_faulty_drop_packet_in, -- added according to new design N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design N_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --N_err_header_not_empty_Req_L_in, -- added according to new design N_err_header_not_empty_Req_N_in, N_err_header_not_empty_Req_E_in, N_err_header_not_empty_Req_W_in, N_err_header_not_empty_Req_S_in, N_err_header_empty_packet_drop_in_packet_drop_equal, N_err_tail_not_empty_packet_drop_not_packet_drop_in, N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, N_err_packet_drop_order, N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- East E_err_header_empty_Requests_FF_Requests_in, E_err_tail_Requests_in_all_zero, E_err_tail_empty_Requests_FF_Requests_in, E_err_tail_not_empty_not_grants_Requests_FF_Requests_in, E_err_grants_onehot, E_err_grants_mismatch, E_err_header_tail_Requests_FF_Requests_in, E_err_dst_addr_cur_addr_N1, E_err_dst_addr_cur_addr_not_N1, E_err_dst_addr_cur_addr_E1, E_err_dst_addr_cur_addr_not_E1, E_err_dst_addr_cur_addr_W1, E_err_dst_addr_cur_addr_not_W1, E_err_dst_addr_cur_addr_S1, E_err_dst_addr_cur_addr_not_S1, E_err_dst_addr_cur_addr_Req_L_in, E_err_dst_addr_cur_addr_not_Req_L_in, E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --E_err_header_not_empty_Req_L_in, -- added according to new design E_err_header_not_empty_Req_N_in, E_err_header_not_empty_Req_E_in, E_err_header_not_empty_Req_W_in, E_err_header_not_empty_Req_S_in, E_err_header_empty_packet_drop_in_packet_drop_equal, E_err_tail_not_empty_packet_drop_not_packet_drop_in, E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, E_err_packet_drop_order, E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- West W_err_header_empty_Requests_FF_Requests_in, W_err_tail_Requests_in_all_zero, W_err_tail_empty_Requests_FF_Requests_in, W_err_tail_not_empty_not_grants_Requests_FF_Requests_in, W_err_grants_onehot, W_err_grants_mismatch, W_err_header_tail_Requests_FF_Requests_in, W_err_dst_addr_cur_addr_N1, W_err_dst_addr_cur_addr_not_N1, W_err_dst_addr_cur_addr_E1, W_err_dst_addr_cur_addr_not_E1, W_err_dst_addr_cur_addr_W1, W_err_dst_addr_cur_addr_not_W1, W_err_dst_addr_cur_addr_S1, W_err_dst_addr_cur_addr_not_S1, W_err_dst_addr_cur_addr_Req_L_in, W_err_dst_addr_cur_addr_not_Req_L_in, W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --W_err_header_not_empty_Req_L_in, -- added according to new design W_err_header_not_empty_Req_N_in, W_err_header_not_empty_Req_E_in, W_err_header_not_empty_Req_W_in, W_err_header_not_empty_Req_S_in, W_err_header_empty_packet_drop_in_packet_drop_equal, W_err_tail_not_empty_packet_drop_not_packet_drop_in, W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, W_err_packet_drop_order, W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- South S_err_header_empty_Requests_FF_Requests_in, S_err_tail_Requests_in_all_zero, S_err_tail_empty_Requests_FF_Requests_in, S_err_tail_not_empty_not_grants_Requests_FF_Requests_in, S_err_grants_onehot, S_err_grants_mismatch, S_err_header_tail_Requests_FF_Requests_in, S_err_dst_addr_cur_addr_N1, S_err_dst_addr_cur_addr_not_N1, S_err_dst_addr_cur_addr_E1, S_err_dst_addr_cur_addr_not_E1, S_err_dst_addr_cur_addr_W1, S_err_dst_addr_cur_addr_not_W1, S_err_dst_addr_cur_addr_S1, S_err_dst_addr_cur_addr_not_S1, S_err_dst_addr_cur_addr_Req_L_in, S_err_dst_addr_cur_addr_not_Req_L_in, S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --S_err_header_not_empty_Req_L_in, -- added according to new design S_err_header_not_empty_Req_N_in, S_err_header_not_empty_Req_E_in, S_err_header_not_empty_Req_W_in, S_err_header_not_empty_Req_S_in, S_err_header_empty_packet_drop_in_packet_drop_equal, S_err_tail_not_empty_packet_drop_not_packet_drop_in, S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, S_err_packet_drop_order, S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- Local L_err_header_empty_Requests_FF_Requests_in, L_err_tail_Requests_in_all_zero, L_err_tail_empty_Requests_FF_Requests_in, L_err_tail_not_empty_not_grants_Requests_FF_Requests_in, L_err_grants_onehot, L_err_grants_mismatch, L_err_header_tail_Requests_FF_Requests_in, L_err_dst_addr_cur_addr_N1, L_err_dst_addr_cur_addr_not_N1, L_err_dst_addr_cur_addr_E1, L_err_dst_addr_cur_addr_not_E1, L_err_dst_addr_cur_addr_W1, L_err_dst_addr_cur_addr_not_W1, L_err_dst_addr_cur_addr_S1, L_err_dst_addr_cur_addr_not_S1, L_err_dst_addr_cur_addr_Req_L_in, L_err_dst_addr_cur_addr_not_Req_L_in, L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --L_err_header_not_empty_Req_L_in, -- added according to new design L_err_header_not_empty_Req_N_in, L_err_header_not_empty_Req_E_in, L_err_header_not_empty_Req_W_in, L_err_header_not_empty_Req_S_in, L_err_header_empty_packet_drop_in_packet_drop_equal, L_err_tail_not_empty_packet_drop_not_packet_drop_in, L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, L_err_packet_drop_order, L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal: std_logic; ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ -- Signals needed for FIFO packet drop with fault classifier support checkers -- North -- Functional checkers signal N_err_empty_full, N_err_empty_read_en, N_err_full_write_en, N_err_state_in_onehot, N_err_read_pointer_in_onehot, N_err_write_pointer_in_onehot, -- Structural checkers N_err_write_en_write_pointer, N_err_not_write_en_write_pointer, N_err_read_pointer_write_pointer_not_empty, N_err_read_pointer_write_pointer_empty, N_err_read_pointer_write_pointer_not_full, N_err_read_pointer_write_pointer_full, N_err_read_pointer_increment, N_err_read_pointer_not_increment, N_err_write_en, N_err_not_write_en, N_err_not_write_en1, N_err_not_write_en2, N_err_read_en_mismatch, N_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! N_err_fake_credit_read_en_fake_credit_counter_in_increment, N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, N_err_fake_credit_read_en_credit_out, N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, N_err_state_out_Idle_not_fault_out_not_fake_credit, N_err_state_out_Idle_not_fault_out_not_fault_info_in, N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, N_err_state_out_Idle_fault_out_fake_credit, N_err_state_out_Idle_fault_out_state_in_Packet_drop, N_err_state_out_Idle_fault_out_fault_info_in, N_err_state_out_Idle_fault_out_faulty_packet_in, N_err_state_out_Idle_not_health_info, N_err_state_out_Idle_not_write_fake_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Header_flit_not_valid_in_not_fault_info_in, N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, N_err_state_out_Header_flit_or_Body_flit_not_fake_credit, N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, N_err_state_out_Body_flit_valid_in_not_fault_out_health_info, N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Body_flit_not_valid_in_not_fault_info_in, N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, N_err_state_out_Body_flit_valid_in_fault_out_not_health_info, N_err_state_out_Body_flit_valid_in_not_health_info, N_err_state_out_Body_flit_not_fake_credit, N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, N_err_state_out_Tail_flit_not_valid_in_state_in_Idle, N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, N_err_state_out_Tail_flit_not_valid_in_not_fake_credit, N_err_state_out_Tail_flit_not_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, N_err_fault_info_fault_info_out_equal, N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- East -- Functional checkers E_err_empty_full, E_err_empty_read_en, E_err_full_write_en, E_err_state_in_onehot, E_err_read_pointer_in_onehot, E_err_write_pointer_in_onehot, -- Structural checkers E_err_write_en_write_pointer, E_err_not_write_en_write_pointer, E_err_read_pointer_write_pointer_not_empty, E_err_read_pointer_write_pointer_empty, E_err_read_pointer_write_pointer_not_full, E_err_read_pointer_write_pointer_full, E_err_read_pointer_increment, E_err_read_pointer_not_increment, E_err_write_en, E_err_not_write_en, E_err_not_write_en1, E_err_not_write_en2, E_err_read_en_mismatch, E_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! E_err_fake_credit_read_en_fake_credit_counter_in_increment, E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, E_err_fake_credit_read_en_credit_out, E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, E_err_state_out_Idle_not_fault_out_not_fake_credit, E_err_state_out_Idle_not_fault_out_not_fault_info_in, E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, E_err_state_out_Idle_fault_out_fake_credit, E_err_state_out_Idle_fault_out_state_in_Packet_drop, E_err_state_out_Idle_fault_out_fault_info_in, E_err_state_out_Idle_fault_out_faulty_packet_in, E_err_state_out_Idle_not_health_info, E_err_state_out_Idle_not_write_fake_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Header_flit_not_valid_in_not_fault_info_in, E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, E_err_state_out_Header_flit_or_Body_flit_not_fake_credit, E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, E_err_state_out_Body_flit_valid_in_not_fault_out_health_info, E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Body_flit_not_valid_in_not_fault_info_in, E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, E_err_state_out_Body_flit_valid_in_fault_out_not_health_info, E_err_state_out_Body_flit_valid_in_not_health_info, E_err_state_out_Body_flit_not_fake_credit, E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, E_err_state_out_Tail_flit_not_valid_in_state_in_Idle, E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, E_err_state_out_Tail_flit_not_valid_in_not_fake_credit, E_err_state_out_Tail_flit_not_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, E_err_fault_info_fault_info_out_equal, E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- West -- Functional checkers W_err_empty_full, W_err_empty_read_en, W_err_full_write_en, W_err_state_in_onehot, W_err_read_pointer_in_onehot, W_err_write_pointer_in_onehot, -- Structural checkers W_err_write_en_write_pointer, W_err_not_write_en_write_pointer, W_err_read_pointer_write_pointer_not_empty, W_err_read_pointer_write_pointer_empty, W_err_read_pointer_write_pointer_not_full, W_err_read_pointer_write_pointer_full, W_err_read_pointer_increment, W_err_read_pointer_not_increment, W_err_write_en, W_err_not_write_en, W_err_not_write_en1, W_err_not_write_en2, W_err_read_en_mismatch, W_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! W_err_fake_credit_read_en_fake_credit_counter_in_increment, W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, W_err_fake_credit_read_en_credit_out, W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, W_err_state_out_Idle_not_fault_out_not_fake_credit, W_err_state_out_Idle_not_fault_out_not_fault_info_in, W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, W_err_state_out_Idle_fault_out_fake_credit, W_err_state_out_Idle_fault_out_state_in_Packet_drop, W_err_state_out_Idle_fault_out_fault_info_in, W_err_state_out_Idle_fault_out_faulty_packet_in, W_err_state_out_Idle_not_health_info, W_err_state_out_Idle_not_write_fake_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Header_flit_not_valid_in_not_fault_info_in, W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, W_err_state_out_Header_flit_or_Body_flit_not_fake_credit, W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, W_err_state_out_Body_flit_valid_in_not_fault_out_health_info, W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Body_flit_not_valid_in_not_fault_info_in, W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, W_err_state_out_Body_flit_valid_in_fault_out_not_health_info, W_err_state_out_Body_flit_valid_in_not_health_info, W_err_state_out_Body_flit_not_fake_credit, W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, W_err_state_out_Tail_flit_not_valid_in_state_in_Idle, W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, W_err_state_out_Tail_flit_not_valid_in_not_fake_credit, W_err_state_out_Tail_flit_not_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, W_err_fault_info_fault_info_out_equal, W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- South -- Functional checkers S_err_empty_full, S_err_empty_read_en, S_err_full_write_en, S_err_state_in_onehot, S_err_read_pointer_in_onehot, S_err_write_pointer_in_onehot, -- Structural checkers S_err_write_en_write_pointer, S_err_not_write_en_write_pointer, S_err_read_pointer_write_pointer_not_empty, S_err_read_pointer_write_pointer_empty, S_err_read_pointer_write_pointer_not_full, S_err_read_pointer_write_pointer_full, S_err_read_pointer_increment, S_err_read_pointer_not_increment, S_err_write_en, S_err_not_write_en, S_err_not_write_en1, S_err_not_write_en2, S_err_read_en_mismatch, S_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! S_err_fake_credit_read_en_fake_credit_counter_in_increment, S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, S_err_fake_credit_read_en_credit_out, S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, S_err_state_out_Idle_not_fault_out_not_fake_credit, S_err_state_out_Idle_not_fault_out_not_fault_info_in, S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, S_err_state_out_Idle_fault_out_fake_credit, S_err_state_out_Idle_fault_out_state_in_Packet_drop, S_err_state_out_Idle_fault_out_fault_info_in, S_err_state_out_Idle_fault_out_faulty_packet_in, S_err_state_out_Idle_not_health_info, S_err_state_out_Idle_not_write_fake_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Header_flit_not_valid_in_not_fault_info_in, S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, S_err_state_out_Header_flit_or_Body_flit_not_fake_credit, S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, S_err_state_out_Body_flit_valid_in_not_fault_out_health_info, S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Body_flit_not_valid_in_not_fault_info_in, S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, S_err_state_out_Body_flit_valid_in_fault_out_not_health_info, S_err_state_out_Body_flit_valid_in_not_health_info, S_err_state_out_Body_flit_not_fake_credit, S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, S_err_state_out_Tail_flit_not_valid_in_state_in_Idle, S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, S_err_state_out_Tail_flit_not_valid_in_not_fake_credit, S_err_state_out_Tail_flit_not_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, S_err_fault_info_fault_info_out_equal, S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- Local -- Functional checkers L_err_empty_full, L_err_empty_read_en, L_err_full_write_en, L_err_state_in_onehot, L_err_read_pointer_in_onehot, L_err_write_pointer_in_onehot, -- Structural checkers L_err_write_en_write_pointer, L_err_not_write_en_write_pointer, L_err_read_pointer_write_pointer_not_empty, L_err_read_pointer_write_pointer_empty, L_err_read_pointer_write_pointer_not_full, L_err_read_pointer_write_pointer_full, L_err_read_pointer_increment, L_err_read_pointer_not_increment, L_err_write_en, L_err_not_write_en, L_err_not_write_en1, L_err_not_write_en2, L_err_read_en_mismatch, L_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! L_err_fake_credit_read_en_fake_credit_counter_in_increment, L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, L_err_fake_credit_read_en_credit_out, L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, L_err_state_out_Idle_not_fault_out_not_fake_credit, L_err_state_out_Idle_not_fault_out_not_fault_info_in, L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, L_err_state_out_Idle_fault_out_fake_credit, L_err_state_out_Idle_fault_out_state_in_Packet_drop, L_err_state_out_Idle_fault_out_fault_info_in, L_err_state_out_Idle_fault_out_faulty_packet_in, L_err_state_out_Idle_not_health_info, L_err_state_out_Idle_not_write_fake_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Header_flit_not_valid_in_not_fault_info_in, L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, L_err_state_out_Header_flit_or_Body_flit_not_fake_credit, L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, L_err_state_out_Body_flit_valid_in_not_fault_out_health_info, L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Body_flit_not_valid_in_not_fault_info_in, L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, L_err_state_out_Body_flit_valid_in_fault_out_not_health_info, L_err_state_out_Body_flit_valid_in_not_health_info, L_err_state_out_Body_flit_not_fake_credit, L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, L_err_state_out_Tail_flit_not_valid_in_state_in_Idle, L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, L_err_state_out_Tail_flit_not_valid_in_not_fake_credit, L_err_state_out_Tail_flit_not_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, L_err_fault_info_fault_info_out_equal, L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in: std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Signals needed for Allocator unit -- Allocator logic checker outputs -- Might need to be changed ?! signal err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N, err_grant_N_E_sig_not_empty_E_grant_N_E, err_not_grant_N_E_sig_or_empty_E_not_grant_N_E, err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W, err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S, err_grant_N_L_sig_not_empty_L_grant_N_L, err_not_grant_N_L_sig_or_empty_L_not_grant_N_L, err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N, err_grant_E_E_sig_not_empty_E_grant_E_E, err_not_grant_E_E_sig_or_empty_E_not_grant_E_E, err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W, err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S, err_grant_E_L_sig_not_empty_L_grant_E_L, err_not_grant_E_L_sig_or_empty_L_not_grant_E_L, err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N, err_grant_W_E_sig_not_empty_E_grant_W_E, err_not_grant_W_E_sig_or_empty_E_not_grant_W_E, err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W, err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S, err_grant_W_L_sig_not_empty_L_grant_W_L, err_not_grant_W_L_sig_or_empty_L_not_grant_W_L, err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N, err_grant_S_E_sig_not_empty_E_grant_S_E, err_not_grant_S_E_sig_or_empty_E_not_grant_S_E, err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W, err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S, err_grant_S_L_sig_not_empty_L_grant_S_L, err_not_grant_S_L_sig_or_empty_L_not_grant_S_L, err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N, err_grant_L_E_sig_not_empty_E_grant_L_E, err_not_grant_L_E_sig_or_empty_E_not_grant_L_E, err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W, err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S, err_grant_L_L_sig_not_empty_L_grant_L_L, err_not_grant_L_L_sig_or_empty_L_not_grant_L_L, err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N, err_grant_signals_not_empty_grant_E, err_not_grant_signals_empty_not_grant_E, err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W, err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S, err_grant_signals_not_empty_grant_L, err_not_grant_signals_empty_not_grant_L, err_grants_valid_not_match: std_logic; -- Allocator credit_counter logic checker outputs signal err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment, err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement, err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change, err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment, err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement, err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change, err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment, err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement, err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change, err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment, err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement, err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change, err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment, err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement, err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change, err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Arbiter_in Checker signals (part of allocator unit) -- North Arbiter_in checker outputs signal N_err_Requests_state_in_state_not_equal, N_err_IDLE_Req_N, N_err_IDLE_grant_N,N_err_North_Req_N, N_err_North_grant_N, N_err_East_Req_E, N_err_East_grant_E, N_err_West_Req_W, N_err_West_grant_W, N_err_South_Req_S,N_err_South_grant_S,N_err_Local_Req_L, N_err_Local_grant_L, N_err_IDLE_Req_E, N_err_IDLE_grant_E, N_err_North_Req_E, N_err_North_grant_E, N_err_East_Req_W, N_err_East_grant_W, N_err_West_Req_S, N_err_West_grant_S, N_err_South_Req_L, N_err_South_grant_L, N_err_Local_Req_N, N_err_Local_grant_N, N_err_IDLE_Req_W, N_err_IDLE_grant_W, N_err_North_Req_W, N_err_North_grant_W, N_err_East_Req_S, N_err_East_grant_S, N_err_West_Req_L, N_err_West_grant_L, N_err_South_Req_N, N_err_South_grant_N, N_err_Local_Req_E, N_err_Local_grant_E, N_err_IDLE_Req_S, N_err_IDLE_grant_S, N_err_North_Req_S, N_err_North_grant_S, N_err_East_Req_L, N_err_East_grant_L, N_err_West_Req_N, N_err_West_grant_N, N_err_South_Req_E, N_err_South_grant_E, N_err_Local_Req_W, N_err_Local_grant_W, N_err_IDLE_Req_L, N_err_IDLE_grant_L, N_err_North_Req_L, N_err_North_grant_L, N_err_East_Req_N, N_err_East_grant_N, N_err_West_Req_E, N_err_West_grant_E, N_err_South_Req_W, N_err_South_grant_W, N_err_Local_Req_S, N_err_Local_grant_S, N_err_arbiter_state_in_onehot, N_err_no_request_grants, N_err_request_no_grants, N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L, -- East Arbiter_in checker outputs E_err_Requests_state_in_state_not_equal, E_err_IDLE_Req_N, E_err_IDLE_grant_N, E_err_North_Req_N, E_err_North_grant_N, E_err_East_Req_E, E_err_East_grant_E, E_err_West_Req_W, E_err_West_grant_W, E_err_South_Req_S, E_err_South_grant_S, E_err_Local_Req_L, E_err_Local_grant_L, E_err_IDLE_Req_E, E_err_IDLE_grant_E, E_err_North_Req_E, E_err_North_grant_E, E_err_East_Req_W, E_err_East_grant_W, E_err_West_Req_S, E_err_West_grant_S, E_err_South_Req_L, E_err_South_grant_L, E_err_Local_Req_N, E_err_Local_grant_N, E_err_IDLE_Req_W, E_err_IDLE_grant_W, E_err_North_Req_W, E_err_North_grant_W, E_err_East_Req_S, E_err_East_grant_S, E_err_West_Req_L, E_err_West_grant_L, E_err_South_Req_N, E_err_South_grant_N, E_err_Local_Req_E, E_err_Local_grant_E, E_err_IDLE_Req_S, E_err_IDLE_grant_S, E_err_North_Req_S, E_err_North_grant_S, E_err_East_Req_L, E_err_East_grant_L, E_err_West_Req_N, E_err_West_grant_N, E_err_South_Req_E, E_err_South_grant_E, E_err_Local_Req_W, E_err_Local_grant_W, E_err_IDLE_Req_L, E_err_IDLE_grant_L, E_err_North_Req_L, E_err_North_grant_L, E_err_East_Req_N, E_err_East_grant_N, E_err_West_Req_E, E_err_West_grant_E, E_err_South_Req_W, E_err_South_grant_W, E_err_Local_Req_S, E_err_Local_grant_S, E_err_arbiter_state_in_onehot, E_err_no_request_grants, E_err_request_no_grants, E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L, -- West Arbiter_in checker outputs W_err_Requests_state_in_state_not_equal, W_err_IDLE_Req_N, W_err_IDLE_grant_N, W_err_North_Req_N, W_err_North_grant_N, W_err_East_Req_E, W_err_East_grant_E, W_err_West_Req_W, W_err_West_grant_W, W_err_South_Req_S, W_err_South_grant_S, W_err_Local_Req_L, W_err_Local_grant_L, W_err_IDLE_Req_E, W_err_IDLE_grant_E, W_err_North_Req_E, W_err_North_grant_E, W_err_East_Req_W, W_err_East_grant_W, W_err_West_Req_S, W_err_West_grant_S, W_err_South_Req_L, W_err_South_grant_L, W_err_Local_Req_N, W_err_Local_grant_N, W_err_IDLE_Req_W, W_err_IDLE_grant_W, W_err_North_Req_W, W_err_North_grant_W, W_err_East_Req_S, W_err_East_grant_S, W_err_West_Req_L, W_err_West_grant_L, W_err_South_Req_N, W_err_South_grant_N, W_err_Local_Req_E, W_err_Local_grant_E, W_err_IDLE_Req_S, W_err_IDLE_grant_S, W_err_North_Req_S, W_err_North_grant_S, W_err_East_Req_L, W_err_East_grant_L, W_err_West_Req_N, W_err_West_grant_N, W_err_South_Req_E, W_err_South_grant_E, W_err_Local_Req_W, W_err_Local_grant_W, W_err_IDLE_Req_L, W_err_IDLE_grant_L, W_err_North_Req_L, W_err_North_grant_L, W_err_East_Req_N, W_err_East_grant_N, W_err_West_Req_E, W_err_West_grant_E, W_err_South_Req_W, W_err_South_grant_W, W_err_Local_Req_S, W_err_Local_grant_S, W_err_arbiter_state_in_onehot, W_err_no_request_grants, W_err_request_no_grants, W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L, -- South Arbiter_in checker outputs S_err_Requests_state_in_state_not_equal, S_err_IDLE_Req_N, S_err_IDLE_grant_N,S_err_North_Req_N, S_err_North_grant_N, S_err_East_Req_E, S_err_East_grant_E, S_err_West_Req_W, S_err_West_grant_W, S_err_South_Req_S,S_err_South_grant_S,S_err_Local_Req_L, S_err_Local_grant_L, S_err_IDLE_Req_E, S_err_IDLE_grant_E, S_err_North_Req_E, S_err_North_grant_E, S_err_East_Req_W, S_err_East_grant_W, S_err_West_Req_S, S_err_West_grant_S, S_err_South_Req_L, S_err_South_grant_L, S_err_Local_Req_N, S_err_Local_grant_N, S_err_IDLE_Req_W, S_err_IDLE_grant_W, S_err_North_Req_W, S_err_North_grant_W, S_err_East_Req_S, S_err_East_grant_S, S_err_West_Req_L, S_err_West_grant_L, S_err_South_Req_N, S_err_South_grant_N, S_err_Local_Req_E, S_err_Local_grant_E, S_err_IDLE_Req_S, S_err_IDLE_grant_S, S_err_North_Req_S, S_err_North_grant_S, S_err_East_Req_L, S_err_East_grant_L, S_err_West_Req_N, S_err_West_grant_N, S_err_South_Req_E, S_err_South_grant_E, S_err_Local_Req_W, S_err_Local_grant_W, S_err_IDLE_Req_L, S_err_IDLE_grant_L, S_err_North_Req_L, S_err_North_grant_L, S_err_East_Req_N, S_err_East_grant_N, S_err_West_Req_E, S_err_West_grant_E, S_err_South_Req_W, S_err_South_grant_W, S_err_Local_Req_S, S_err_Local_grant_S, S_err_arbiter_state_in_onehot, S_err_no_request_grants, S_err_request_no_grants, S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L, -- Local Arbiter_in checker outputs L_err_Requests_state_in_state_not_equal, L_err_IDLE_Req_N, L_err_IDLE_grant_N,L_err_North_Req_N, L_err_North_grant_N, L_err_East_Req_E, L_err_East_grant_E, L_err_West_Req_W, L_err_West_grant_W, L_err_South_Req_S,L_err_South_grant_S, L_err_Local_Req_L, L_err_Local_grant_L, L_err_IDLE_Req_E, L_err_IDLE_grant_E, L_err_North_Req_E, L_err_North_grant_E, L_err_East_Req_W, L_err_East_grant_W, L_err_West_Req_S, L_err_West_grant_S, L_err_South_Req_L, L_err_South_grant_L, L_err_Local_Req_N, L_err_Local_grant_N, L_err_IDLE_Req_W, L_err_IDLE_grant_W, L_err_North_Req_W, L_err_North_grant_W, L_err_East_Req_S, L_err_East_grant_S, L_err_West_Req_L, L_err_West_grant_L, L_err_South_Req_N, L_err_South_grant_N, L_err_Local_Req_E, L_err_Local_grant_E, L_err_IDLE_Req_S, L_err_IDLE_grant_S, L_err_North_Req_S, L_err_North_grant_S, L_err_East_Req_L, L_err_East_grant_L, L_err_West_Req_N, L_err_West_grant_N, L_err_South_Req_E, L_err_South_grant_E, L_err_Local_Req_W, L_err_Local_grant_W, L_err_IDLE_Req_L, L_err_IDLE_grant_L, L_err_North_Req_L, L_err_North_grant_L, L_err_East_Req_N, L_err_East_grant_N, L_err_West_Req_E, L_err_West_grant_E, L_err_South_Req_W, L_err_South_grant_W, L_err_Local_Req_S, L_err_Local_grant_S, L_err_arbiter_state_in_onehot, L_err_no_request_grants, L_err_request_no_grants, L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S, L_err_no_Req_L_grant_L : std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Arbiter_out Checker signals (part of allocator unit) -- North Arbiter_out checker outputs signal N_arbiter_out_err_Requests_state_in_state_not_equal, N_err_IDLE_req_X_N, N_err_North_req_X_N, N_err_North_credit_not_zero_req_X_N_grant_N, N_err_North_credit_zero_or_not_req_X_N_not_grant_N, N_err_East_req_X_E, N_err_East_credit_not_zero_req_X_E_grant_E, N_err_East_credit_zero_or_not_req_X_E_not_grant_E, N_err_West_req_X_W, N_err_West_credit_not_zero_req_X_W_grant_W, N_err_West_credit_zero_or_not_req_X_W_not_grant_W, N_err_South_req_X_S, N_err_South_credit_not_zero_req_X_S_grant_S, N_err_South_credit_zero_or_not_req_X_S_not_grant_S, N_err_Local_req_X_L, N_err_Local_credit_not_zero_req_X_L_grant_L, N_err_Local_credit_zero_or_not_req_X_L_not_grant_L, N_err_IDLE_req_X_E, N_err_North_req_X_E, N_err_East_req_X_W, N_err_West_req_X_S, N_err_South_req_X_L, N_err_Local_req_X_N, N_err_IDLE_req_X_W, N_err_North_req_X_W, N_err_East_req_X_S, N_err_West_req_X_L, N_err_South_req_X_N, N_err_Local_req_X_E, N_err_IDLE_req_X_S, N_err_North_req_X_S, N_err_East_req_X_L, N_err_West_req_X_N, N_err_South_req_X_E, N_err_Local_req_X_W, N_err_IDLE_req_X_L, N_err_North_req_X_L, N_err_East_req_X_N, N_err_West_req_X_E, N_err_South_req_X_W, N_err_Local_req_X_S, N_arbiter_out_err_state_in_onehot, N_arbiter_out_err_no_request_grants, N_err_request_IDLE_state, N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant, N_err_state_West_Invalid_Grant, N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant, N_err_Grants_onehot_or_all_zero, -- East Arbiter_out checker outputs E_arbiter_out_err_Requests_state_in_state_not_equal, E_err_IDLE_req_X_N, E_err_North_req_X_N, E_err_North_credit_not_zero_req_X_N_grant_N, E_err_North_credit_zero_or_not_req_X_N_not_grant_N, E_err_East_req_X_E, E_err_East_credit_not_zero_req_X_E_grant_E, E_err_East_credit_zero_or_not_req_X_E_not_grant_E, E_err_West_req_X_W, E_err_West_credit_not_zero_req_X_W_grant_W, E_err_West_credit_zero_or_not_req_X_W_not_grant_W, E_err_South_req_X_S, E_err_South_credit_not_zero_req_X_S_grant_S, E_err_South_credit_zero_or_not_req_X_S_not_grant_S, E_err_Local_req_X_L, E_err_Local_credit_not_zero_req_X_L_grant_L, E_err_Local_credit_zero_or_not_req_X_L_not_grant_L, E_err_IDLE_req_X_E, E_err_North_req_X_E, E_err_East_req_X_W, E_err_West_req_X_S, E_err_South_req_X_L, E_err_Local_req_X_N, E_err_IDLE_req_X_W, E_err_North_req_X_W, E_err_East_req_X_S, E_err_West_req_X_L, E_err_South_req_X_N, E_err_Local_req_X_E, E_err_IDLE_req_X_S, E_err_North_req_X_S, E_err_East_req_X_L, E_err_West_req_X_N, E_err_South_req_X_E, E_err_Local_req_X_W, E_err_IDLE_req_X_L, E_err_North_req_X_L, E_err_East_req_X_N, E_err_West_req_X_E, E_err_South_req_X_W, E_err_Local_req_X_S, E_arbiter_out_err_state_in_onehot, E_arbiter_out_err_no_request_grants, E_err_request_IDLE_state, E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant, E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant, E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero, -- West Arbiter_out checker outputs W_arbiter_out_err_Requests_state_in_state_not_equal, W_err_IDLE_req_X_N, W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N, W_err_North_credit_zero_or_not_req_X_N_not_grant_N, W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E, W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W, W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S, W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L, W_err_IDLE_req_X_E, W_err_North_req_X_E, W_err_East_req_X_W, W_err_West_req_X_S, W_err_South_req_X_L, W_err_Local_req_X_N, W_err_IDLE_req_X_W, W_err_North_req_X_W, W_err_East_req_X_S, W_err_West_req_X_L, W_err_South_req_X_N, W_err_Local_req_X_E, W_err_IDLE_req_X_S, W_err_North_req_X_S, W_err_East_req_X_L, W_err_West_req_X_N, W_err_South_req_X_E, W_err_Local_req_X_W, W_err_IDLE_req_X_L, W_err_North_req_X_L, W_err_East_req_X_N, W_err_West_req_X_E, W_err_South_req_X_W, W_err_Local_req_X_S, W_arbiter_out_err_state_in_onehot, W_arbiter_out_err_no_request_grants, W_err_request_IDLE_state, W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant,W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant, W_err_state_South_Invalid_Grant,W_err_state_Local_Invalid_Grant, W_err_Grants_onehot_or_all_zero, -- South Arbiter_out checker outputs S_arbiter_out_err_Requests_state_in_state_not_equal, S_err_IDLE_req_X_N, S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N, S_err_North_credit_zero_or_not_req_X_N_not_grant_N, S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E, S_err_East_credit_zero_or_not_req_X_E_not_grant_E, S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W, S_err_West_credit_zero_or_not_req_X_W_not_grant_W, S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S, S_err_South_credit_zero_or_not_req_X_S_not_grant_S, S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L, S_err_Local_credit_zero_or_not_req_X_L_not_grant_L, S_err_IDLE_req_X_E, S_err_North_req_X_E, S_err_East_req_X_W, S_err_West_req_X_S, S_err_South_req_X_L, S_err_Local_req_X_N, S_err_IDLE_req_X_W, S_err_North_req_X_W, S_err_East_req_X_S, S_err_West_req_X_L, S_err_South_req_X_N, S_err_Local_req_X_E, S_err_IDLE_req_X_S, S_err_North_req_X_S, S_err_East_req_X_L, S_err_West_req_X_N, S_err_South_req_X_E, S_err_Local_req_X_W, S_err_IDLE_req_X_L, S_err_North_req_X_L, S_err_East_req_X_N, S_err_West_req_X_E, S_err_South_req_X_W, S_err_Local_req_X_S, S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state, S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant, S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero, -- Local Arbiter_out checker outputs L_arbiter_out_err_Requests_state_in_state_not_equal, L_err_IDLE_req_X_N, L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N, L_err_North_credit_zero_or_not_req_X_N_not_grant_N, L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E, L_err_East_credit_zero_or_not_req_X_E_not_grant_E, L_err_West_req_X_W, L_err_West_credit_not_zero_req_X_W_grant_W, L_err_West_credit_zero_or_not_req_X_W_not_grant_W, L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S, L_err_South_credit_zero_or_not_req_X_S_not_grant_S, L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L, L_err_Local_credit_zero_or_not_req_X_L_not_grant_L, L_err_IDLE_req_X_E, L_err_North_req_X_E, L_err_East_req_X_W, L_err_West_req_X_S, L_err_South_req_X_L, L_err_Local_req_X_N, L_err_IDLE_req_X_W, L_err_North_req_X_W, L_err_East_req_X_S, L_err_West_req_X_L, L_err_South_req_X_N, L_err_Local_req_X_E, L_err_IDLE_req_X_S, L_err_North_req_X_S, L_err_East_req_X_L, L_err_West_req_X_N, L_err_South_req_X_E, L_err_Local_req_X_W, L_err_IDLE_req_X_L, L_err_North_req_X_L, L_err_East_req_X_N, L_err_West_req_X_E, L_err_South_req_X_W, L_err_Local_req_X_S, L_arbiter_out_err_state_in_onehot, L_arbiter_out_err_no_request_grants, L_err_request_IDLE_state, L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant,L_err_state_East_Invalid_Grant, L_err_state_West_Invalid_Grant, L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant, L_err_Grants_onehot_or_all_zero : std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Signals needed for grouping checkers to model turn/path faults signal N_FIFO_checkers_ORed, E_FIFO_checkers_ORed, W_FIFO_checkers_ORed, S_FIFO_checkers_ORed, L_FIFO_checkers_ORed : std_logic; signal N2E_turn_fault, N2W_turn_fault, E2N_turn_fault, E2S_turn_fault, W2N_turn_fault, W2S_turn_fault, S2E_turn_fault, S2W_turn_fault : std_logic; signal N2S_path_fault, S2N_path_fault, E2W_path_fault, W2E_path_fault : std_logic; signal not_N2E_turn_fault, not_N2W_turn_fault, not_E2N_turn_fault, not_E2S_turn_fault, not_W2N_turn_fault, not_W2S_turn_fault, not_S2E_turn_fault, not_S2W_turn_fault : std_logic; signal not_N2S_path_fault, not_S2N_path_fault, not_E2W_path_fault, not_W2E_path_fault : std_logic; signal L2N_fault, L2E_fault, L2W_fault, L2S_fault, N2L_fault, E2L_fault, W2L_fault, S2L_fault : std_logic; signal not_L2N_fault, not_L2E_fault, not_L2W_fault, not_L2S_fault, not_N2L_fault, not_E2L_fault, not_W2L_fault, not_S2L_fault : std_logic; -- Just used temporarily for debugging purposes! signal N_LBDR_checkers_ORed, E_LBDR_checkers_ORed, W_LBDR_checkers_ORed, S_LBDR_checkers_ORed, L_LBDR_checkers_ORed : std_logic; signal Allocator_checkers_ORed : std_logic; --signal turn_faults_sig : std_logic_vector(19 downto 0); ------------------------------------------------------------------------------------------------- -- Added because of the chain we make for sending faulty values --------------------------------- -- The chain is : L, N, E, W and S FIFO, then L, N, E, W and S LBDR, ---------------------------- -- then L, N, E, W and S Arbiter_in, -------------------- -- then L, N, E, W and S Arbiter_out and then Allocator's interlal logic ??!! -- ------------------------------------------------------------------------------------------------- --TODO: the chains should be fixed! --Fixed! signal fault_DO_serial_L_FIFO_to_N_FIFO, fault_DO_serial_N_FIFO_to_E_FIFO: std_logic; signal fault_DO_serial_E_FIFO_to_W_FIFO, fault_DO_serial_W_FIFO_to_S_FIFO: std_logic; signal fault_DO_serial_S_FIFO_to_L_LBDR, fault_DO_serial_L_LBDR_to_N_LBDR: std_logic; signal fault_DO_serial_N_LBDR_to_E_LBDR, fault_DO_serial_E_LBDR_to_W_LBDR: std_logic; signal fault_DO_serial_W_LBDR_to_S_LBDR, fault_DO_serial_S_LBDR_to_Allocator: std_logic; ------------------------------------------------------------------ ------------------------------------------------------------------ begin not_N2E_turn_fault <= not N2E_turn_fault; not_N2W_turn_fault <= not N2W_turn_fault; not_E2N_turn_fault <= not E2N_turn_fault; not_E2S_turn_fault <= not E2S_turn_fault; not_W2N_turn_fault <= not W2N_turn_fault; not_W2S_turn_fault <= not W2S_turn_fault; not_S2E_turn_fault <= not S2E_turn_fault; not_S2W_turn_fault <= not S2W_turn_fault; not_N2S_path_fault <= not N2S_path_fault; not_S2N_path_fault <= not S2N_path_fault; not_E2W_path_fault <= not E2W_path_fault; not_W2E_path_fault <= not W2E_path_fault; not_L2N_fault <= not L2N_fault; not_L2E_fault <= not L2E_fault; not_L2W_fault <= not L2W_fault; not_L2S_fault <= not L2S_fault; not_N2L_fault <= not N2L_fault; not_E2L_fault <= not E2L_fault; not_W2L_fault <= not W2L_fault; not_S2L_fault <= not S2L_fault; -- FIFO contributes to all turns and paths, therefore, for each turn or path (for the input direction), all the outputs of FIFO checkers -- corresponding to that input are ORed together. N_FIFO_checkers_ORed <= N_err_empty_full or N_err_empty_read_en or N_err_full_write_en or N_err_state_in_onehot or N_err_read_pointer_in_onehot or N_err_write_pointer_in_onehot or N_err_write_en_write_pointer or N_err_not_write_en_write_pointer or N_err_read_pointer_write_pointer_not_empty or N_err_read_pointer_write_pointer_empty or N_err_read_pointer_write_pointer_not_full or N_err_read_pointer_write_pointer_full or N_err_read_pointer_increment or N_err_read_pointer_not_increment or N_err_write_en or N_err_not_write_en or N_err_not_write_en1 or N_err_not_write_en2 or N_err_read_en_mismatch or N_err_read_en_mismatch1 or N_err_fake_credit_read_en_fake_credit_counter_in_increment or N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or N_err_fake_credit_read_en_credit_out or N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or N_err_state_out_Idle_not_fault_out_not_fake_credit or N_err_state_out_Idle_not_fault_out_not_fault_info_in or N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or N_err_state_out_Idle_fault_out_fake_credit or N_err_state_out_Idle_fault_out_state_in_Packet_drop or N_err_state_out_Idle_fault_out_fault_info_in or N_err_state_out_Idle_fault_out_faulty_packet_in or N_err_state_out_Idle_not_health_info or N_err_state_out_Idle_not_write_fake_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Header_flit_not_valid_in_not_fault_info_in or N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or N_err_state_out_Header_flit_or_Body_flit_not_fake_credit or N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or N_err_state_out_Body_flit_valid_in_not_fault_out_health_info or N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Body_flit_not_valid_in_not_fault_info_in or N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or N_err_state_out_Body_flit_valid_in_fault_out_not_health_info or N_err_state_out_Body_flit_valid_in_not_health_info or N_err_state_out_Body_flit_not_fake_credit or N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or N_err_state_out_Tail_flit_not_valid_in_state_in_Idle or N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or N_err_state_out_Tail_flit_not_valid_in_not_fake_credit or N_err_state_out_Tail_flit_not_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or N_err_fault_info_fault_info_out_equal or N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- East E_FIFO_checkers_ORed <= E_err_empty_full or E_err_empty_read_en or E_err_full_write_en or E_err_state_in_onehot or E_err_read_pointer_in_onehot or E_err_write_pointer_in_onehot or E_err_write_en_write_pointer or E_err_not_write_en_write_pointer or E_err_read_pointer_write_pointer_not_empty or E_err_read_pointer_write_pointer_empty or E_err_read_pointer_write_pointer_not_full or E_err_read_pointer_write_pointer_full or E_err_read_pointer_increment or E_err_read_pointer_not_increment or E_err_write_en or E_err_not_write_en or E_err_not_write_en1 or E_err_not_write_en2 or E_err_read_en_mismatch or E_err_read_en_mismatch1 or E_err_fake_credit_read_en_fake_credit_counter_in_increment or E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or E_err_fake_credit_read_en_credit_out or E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or E_err_state_out_Idle_not_fault_out_not_fake_credit or E_err_state_out_Idle_not_fault_out_not_fault_info_in or E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or E_err_state_out_Idle_fault_out_fake_credit or E_err_state_out_Idle_fault_out_state_in_Packet_drop or E_err_state_out_Idle_fault_out_fault_info_in or E_err_state_out_Idle_fault_out_faulty_packet_in or E_err_state_out_Idle_not_health_info or E_err_state_out_Idle_not_write_fake_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Header_flit_not_valid_in_not_fault_info_in or E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or E_err_state_out_Header_flit_or_Body_flit_not_fake_credit or E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or E_err_state_out_Body_flit_valid_in_not_fault_out_health_info or E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Body_flit_not_valid_in_not_fault_info_in or E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or E_err_state_out_Body_flit_valid_in_fault_out_not_health_info or E_err_state_out_Body_flit_valid_in_not_health_info or E_err_state_out_Body_flit_not_fake_credit or E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or E_err_state_out_Tail_flit_not_valid_in_state_in_Idle or E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or E_err_state_out_Tail_flit_not_valid_in_not_fake_credit or E_err_state_out_Tail_flit_not_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or E_err_fault_info_fault_info_out_equal or E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- West W_FIFO_checkers_ORed <= W_err_empty_full or W_err_empty_read_en or W_err_full_write_en or W_err_state_in_onehot or W_err_read_pointer_in_onehot or W_err_write_pointer_in_onehot or W_err_write_en_write_pointer or W_err_not_write_en_write_pointer or W_err_read_pointer_write_pointer_not_empty or W_err_read_pointer_write_pointer_empty or W_err_read_pointer_write_pointer_not_full or W_err_read_pointer_write_pointer_full or W_err_read_pointer_increment or W_err_read_pointer_not_increment or W_err_write_en or W_err_not_write_en or W_err_not_write_en1 or W_err_not_write_en2 or W_err_read_en_mismatch or W_err_read_en_mismatch1 or W_err_fake_credit_read_en_fake_credit_counter_in_increment or W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or W_err_fake_credit_read_en_credit_out or W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or W_err_state_out_Idle_not_fault_out_not_fake_credit or W_err_state_out_Idle_not_fault_out_not_fault_info_in or W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or W_err_state_out_Idle_fault_out_fake_credit or W_err_state_out_Idle_fault_out_state_in_Packet_drop or W_err_state_out_Idle_fault_out_fault_info_in or W_err_state_out_Idle_fault_out_faulty_packet_in or W_err_state_out_Idle_not_health_info or W_err_state_out_Idle_not_write_fake_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Header_flit_not_valid_in_not_fault_info_in or W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or W_err_state_out_Header_flit_or_Body_flit_not_fake_credit or W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or W_err_state_out_Body_flit_valid_in_not_fault_out_health_info or W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Body_flit_not_valid_in_not_fault_info_in or W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or W_err_state_out_Body_flit_valid_in_fault_out_not_health_info or W_err_state_out_Body_flit_valid_in_not_health_info or W_err_state_out_Body_flit_not_fake_credit or W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or W_err_state_out_Tail_flit_not_valid_in_state_in_Idle or W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or W_err_state_out_Tail_flit_not_valid_in_not_fake_credit or W_err_state_out_Tail_flit_not_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or W_err_fault_info_fault_info_out_equal or W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- South S_FIFO_checkers_ORed <= S_err_empty_full or S_err_empty_read_en or S_err_full_write_en or S_err_state_in_onehot or S_err_read_pointer_in_onehot or S_err_write_pointer_in_onehot or S_err_write_en_write_pointer or S_err_not_write_en_write_pointer or S_err_read_pointer_write_pointer_not_empty or S_err_read_pointer_write_pointer_empty or S_err_read_pointer_write_pointer_not_full or S_err_read_pointer_write_pointer_full or S_err_read_pointer_increment or S_err_read_pointer_not_increment or S_err_write_en or S_err_not_write_en or S_err_not_write_en1 or S_err_not_write_en2 or S_err_read_en_mismatch or S_err_read_en_mismatch1 or S_err_fake_credit_read_en_fake_credit_counter_in_increment or S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or S_err_fake_credit_read_en_credit_out or S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or S_err_state_out_Idle_not_fault_out_not_fake_credit or S_err_state_out_Idle_not_fault_out_not_fault_info_in or S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or S_err_state_out_Idle_fault_out_fake_credit or S_err_state_out_Idle_fault_out_state_in_Packet_drop or S_err_state_out_Idle_fault_out_fault_info_in or S_err_state_out_Idle_fault_out_faulty_packet_in or S_err_state_out_Idle_not_health_info or S_err_state_out_Idle_not_write_fake_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Header_flit_not_valid_in_not_fault_info_in or S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or S_err_state_out_Header_flit_or_Body_flit_not_fake_credit or S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or S_err_state_out_Body_flit_valid_in_not_fault_out_health_info or S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Body_flit_not_valid_in_not_fault_info_in or S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or S_err_state_out_Body_flit_valid_in_fault_out_not_health_info or S_err_state_out_Body_flit_valid_in_not_health_info or S_err_state_out_Body_flit_not_fake_credit or S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or S_err_state_out_Tail_flit_not_valid_in_state_in_Idle or S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or S_err_state_out_Tail_flit_not_valid_in_not_fake_credit or S_err_state_out_Tail_flit_not_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or S_err_fault_info_fault_info_out_equal or S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- Local L_FIFO_checkers_ORed <= L_err_empty_full or L_err_empty_read_en or L_err_full_write_en or L_err_state_in_onehot or L_err_read_pointer_in_onehot or L_err_write_pointer_in_onehot or L_err_write_en_write_pointer or L_err_not_write_en_write_pointer or L_err_read_pointer_write_pointer_not_empty or L_err_read_pointer_write_pointer_empty or L_err_read_pointer_write_pointer_not_full or L_err_read_pointer_write_pointer_full or L_err_read_pointer_increment or L_err_read_pointer_not_increment or L_err_write_en or L_err_not_write_en or L_err_not_write_en1 or L_err_not_write_en2 or L_err_read_en_mismatch or L_err_read_en_mismatch1 or L_err_fake_credit_read_en_fake_credit_counter_in_increment or L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or L_err_fake_credit_read_en_credit_out or L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or L_err_state_out_Idle_not_fault_out_not_fake_credit or L_err_state_out_Idle_not_fault_out_not_fault_info_in or L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or L_err_state_out_Idle_fault_out_fake_credit or L_err_state_out_Idle_fault_out_state_in_Packet_drop or L_err_state_out_Idle_fault_out_fault_info_in or L_err_state_out_Idle_fault_out_faulty_packet_in or L_err_state_out_Idle_not_health_info or L_err_state_out_Idle_not_write_fake_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Header_flit_not_valid_in_not_fault_info_in or L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or L_err_state_out_Header_flit_or_Body_flit_not_fake_credit or L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or L_err_state_out_Body_flit_valid_in_not_fault_out_health_info or L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Body_flit_not_valid_in_not_fault_info_in or L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or L_err_state_out_Body_flit_valid_in_fault_out_not_health_info or L_err_state_out_Body_flit_valid_in_not_health_info or L_err_state_out_Body_flit_not_fake_credit or L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or L_err_state_out_Tail_flit_not_valid_in_state_in_Idle or L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or L_err_state_out_Tail_flit_not_valid_in_not_fake_credit or L_err_state_out_Tail_flit_not_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or L_err_fault_info_fault_info_out_equal or L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Just for debugging purposes of the checkers! -- LBDR checker outputs ORed -- North -- Routing part checkers N_LBDR_checkers_ORed <= N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_N1 or N_err_dst_addr_cur_addr_not_N1 or N_err_dst_addr_cur_addr_E1 or N_err_dst_addr_cur_addr_not_E1 or N_err_dst_addr_cur_addr_W1 or N_err_dst_addr_cur_addr_not_W1 or N_err_dst_addr_cur_addr_S1 or N_err_dst_addr_cur_addr_not_S1 or N_err_dst_addr_cur_addr_Req_L_in or N_err_dst_addr_cur_addr_not_Req_L_in or N_err_header_not_empty_faulty_drop_packet_in or -- added according to new design N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design N_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --N_err_header_not_empty_Req_L_in or -- added according to new design N_err_header_not_empty_Req_N_in or N_err_header_not_empty_Req_E_in or N_err_header_not_empty_Req_W_in or N_err_header_not_empty_Req_S_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or -- Cx_Reconf checkers N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- East -- Routing part checkers E_LBDR_checkers_ORed <= E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_N1 or E_err_dst_addr_cur_addr_not_N1 or E_err_dst_addr_cur_addr_E1 or E_err_dst_addr_cur_addr_not_E1 or E_err_dst_addr_cur_addr_W1 or E_err_dst_addr_cur_addr_not_W1 or E_err_dst_addr_cur_addr_S1 or E_err_dst_addr_cur_addr_not_S1 or E_err_dst_addr_cur_addr_Req_L_in or E_err_dst_addr_cur_addr_not_Req_L_in or E_err_header_not_empty_faulty_drop_packet_in or -- added according to new design E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design E_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --E_err_header_not_empty_Req_L_in or -- added according to new design E_err_header_not_empty_Req_N_in or E_err_header_not_empty_Req_E_in or E_err_header_not_empty_Req_W_in or E_err_header_not_empty_Req_S_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or -- Cx_Reconf checkers E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- West -- Routing part checkers W_LBDR_checkers_ORed <= W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_N1 or W_err_dst_addr_cur_addr_not_N1 or W_err_dst_addr_cur_addr_E1 or W_err_dst_addr_cur_addr_not_E1 or W_err_dst_addr_cur_addr_W1 or W_err_dst_addr_cur_addr_not_W1 or W_err_dst_addr_cur_addr_S1 or W_err_dst_addr_cur_addr_not_S1 or W_err_dst_addr_cur_addr_Req_L_in or W_err_dst_addr_cur_addr_not_Req_L_in or W_err_header_not_empty_faulty_drop_packet_in or -- added according to new design W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design W_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --W_err_header_not_empty_Req_L_in or -- added according to new design W_err_header_not_empty_Req_N_in or W_err_header_not_empty_Req_E_in or W_err_header_not_empty_Req_W_in or W_err_header_not_empty_Req_S_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or -- Cx_Reconf checkers W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- South -- Routing part checkers S_LBDR_checkers_ORed <= S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_N1 or S_err_dst_addr_cur_addr_not_N1 or S_err_dst_addr_cur_addr_E1 or S_err_dst_addr_cur_addr_not_E1 or S_err_dst_addr_cur_addr_W1 or S_err_dst_addr_cur_addr_not_W1 or S_err_dst_addr_cur_addr_S1 or S_err_dst_addr_cur_addr_not_S1 or S_err_dst_addr_cur_addr_Req_L_in or S_err_dst_addr_cur_addr_not_Req_L_in or S_err_header_not_empty_faulty_drop_packet_in or -- added according to new design S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design S_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --S_err_header_not_empty_Req_L_in or -- added according to new design S_err_header_not_empty_Req_N_in or S_err_header_not_empty_Req_E_in or S_err_header_not_empty_Req_W_in or S_err_header_not_empty_Req_S_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or -- Cx_Reconf checkers S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- Local -- Routing part checkers L_LBDR_checkers_ORed <= L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_N1 or L_err_dst_addr_cur_addr_not_N1 or L_err_dst_addr_cur_addr_E1 or L_err_dst_addr_cur_addr_not_E1 or L_err_dst_addr_cur_addr_W1 or L_err_dst_addr_cur_addr_not_W1 or L_err_dst_addr_cur_addr_S1 or L_err_dst_addr_cur_addr_not_S1 or L_err_dst_addr_cur_addr_Req_L_in or L_err_dst_addr_cur_addr_not_Req_L_in or L_err_header_not_empty_faulty_drop_packet_in or -- added according to new design L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design L_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --L_err_header_not_empty_Req_L_in or -- added according to new design L_err_header_not_empty_Req_N_in or L_err_header_not_empty_Req_E_in or L_err_header_not_empty_Req_W_in or L_err_header_not_empty_Req_S_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or -- Cx_Reconf checkers L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Allocator checker outputs ORed ! -- Allocator logic checker outputs Allocator_checkers_ORed <= err_grant_N_N_sig_not_empty_N_grant_N_N or err_not_grant_N_N_sig_or_empty_N_not_grant_N_N or err_grant_N_E_sig_not_empty_E_grant_N_E or err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or err_grant_N_W_sig_not_empty_W_grant_N_W or err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or err_grant_N_S_sig_not_empty_S_grant_N_S or err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or err_grant_N_L_sig_not_empty_L_grant_N_L or err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or err_grant_E_N_sig_not_empty_N_grant_E_N or err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or err_grant_E_E_sig_not_empty_E_grant_E_E or err_not_grant_E_E_sig_or_empty_E_not_grant_E_E or err_grant_E_W_sig_not_empty_W_grant_E_W or err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or err_grant_E_S_sig_not_empty_S_grant_E_S or err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or err_grant_E_L_sig_not_empty_L_grant_E_L or err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or err_grant_W_N_sig_not_empty_N_grant_W_N or err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or err_grant_W_E_sig_not_empty_E_grant_W_E or err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or err_grant_W_W_sig_not_empty_W_grant_W_W or err_not_grant_W_W_sig_or_empty_W_not_grant_W_W or err_grant_W_S_sig_not_empty_S_grant_W_S or err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or err_grant_W_L_sig_not_empty_L_grant_W_L or err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or err_grant_S_N_sig_not_empty_N_grant_S_N or err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or err_grant_S_E_sig_not_empty_E_grant_S_E or err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or err_grant_S_W_sig_not_empty_W_grant_S_W or err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or err_grant_S_S_sig_not_empty_S_grant_S_S or err_not_grant_S_S_sig_or_empty_S_not_grant_S_S or err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or err_grant_L_N_sig_not_empty_N_grant_L_N or err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or err_grant_L_E_sig_not_empty_E_grant_L_E or err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or err_grant_L_W_sig_not_empty_W_grant_L_W or err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or err_grant_L_L_sig_not_empty_L_grant_L_L or err_not_grant_L_L_sig_or_empty_L_not_grant_L_L or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or -- Allocator credit counter logic checker outputs err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal or -- Arbiter_in checker outputs -- North Arbiter_in checker outputs N_err_Requests_state_in_state_not_equal or N_err_IDLE_Req_N or N_err_IDLE_grant_N or N_err_North_Req_N or N_err_North_grant_N or N_err_East_Req_E or N_err_East_grant_E or N_err_West_Req_W or N_err_West_grant_W or N_err_South_Req_S or N_err_South_grant_S or N_err_Local_Req_L or N_err_Local_grant_L or N_err_IDLE_Req_E or N_err_IDLE_grant_E or N_err_North_Req_E or N_err_North_grant_E or N_err_East_Req_W or N_err_East_grant_W or N_err_West_Req_S or N_err_West_grant_S or N_err_South_Req_L or N_err_South_grant_L or N_err_Local_Req_N or N_err_Local_grant_N or N_err_IDLE_Req_W or N_err_IDLE_grant_W or N_err_North_Req_W or N_err_North_grant_W or N_err_East_Req_S or N_err_East_grant_S or N_err_West_Req_L or N_err_West_grant_L or N_err_South_Req_N or N_err_South_grant_N or N_err_Local_Req_E or N_err_Local_grant_E or N_err_IDLE_Req_S or N_err_IDLE_grant_S or N_err_North_Req_S or N_err_North_grant_S or N_err_East_Req_L or N_err_East_grant_L or N_err_West_Req_N or N_err_West_grant_N or N_err_South_Req_E or N_err_South_grant_E or N_err_Local_Req_W or N_err_Local_grant_W or N_err_IDLE_Req_L or N_err_IDLE_grant_L or N_err_North_Req_L or N_err_North_grant_L or N_err_East_Req_N or N_err_East_grant_N or N_err_West_Req_E or N_err_West_grant_E or N_err_South_Req_W or N_err_South_grant_W or N_err_Local_Req_S or N_err_Local_grant_S or N_err_arbiter_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_N_grant_N or N_err_no_Req_E_grant_E or N_err_no_Req_W_grant_W or N_err_no_Req_S_grant_S or N_err_no_Req_L_grant_L or -- East Arbiter_in checker outputs E_err_Requests_state_in_state_not_equal or E_err_IDLE_Req_N or E_err_IDLE_grant_N or E_err_North_Req_N or E_err_North_grant_N or E_err_East_Req_E or E_err_East_grant_E or E_err_West_Req_W or E_err_West_grant_W or E_err_South_Req_S or E_err_South_grant_S or E_err_Local_Req_L or E_err_Local_grant_L or E_err_IDLE_Req_E or E_err_IDLE_grant_E or E_err_North_Req_E or E_err_North_grant_E or E_err_East_Req_W or E_err_East_grant_W or E_err_West_Req_S or E_err_West_grant_S or E_err_South_Req_L or E_err_South_grant_L or E_err_Local_Req_N or E_err_Local_grant_N or E_err_IDLE_Req_W or E_err_IDLE_grant_W or E_err_North_Req_W or E_err_North_grant_W or E_err_East_Req_S or E_err_East_grant_S or E_err_West_Req_L or E_err_West_grant_L or E_err_South_Req_N or E_err_South_grant_N or E_err_Local_Req_E or E_err_Local_grant_E or E_err_IDLE_Req_S or E_err_IDLE_grant_S or E_err_North_Req_S or E_err_North_grant_S or E_err_East_Req_L or E_err_East_grant_L or E_err_West_Req_N or E_err_West_grant_N or E_err_South_Req_E or E_err_South_grant_E or E_err_Local_Req_W or E_err_Local_grant_W or E_err_IDLE_Req_L or E_err_IDLE_grant_L or E_err_North_Req_L or E_err_North_grant_L or E_err_East_Req_N or E_err_East_grant_N or E_err_West_Req_E or E_err_West_grant_E or E_err_South_Req_W or E_err_South_grant_W or E_err_Local_Req_S or E_err_Local_grant_S or E_err_arbiter_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_N_grant_N or E_err_no_Req_E_grant_E or E_err_no_Req_W_grant_W or E_err_no_Req_S_grant_S or E_err_no_Req_L_grant_L or -- West Arbiter_in checker outputs W_err_Requests_state_in_state_not_equal or W_err_IDLE_Req_N or W_err_IDLE_grant_N or W_err_North_Req_N or W_err_North_grant_N or W_err_East_Req_E or W_err_East_grant_E or W_err_West_Req_W or W_err_West_grant_W or W_err_South_Req_S or W_err_South_grant_S or W_err_Local_Req_L or W_err_Local_grant_L or W_err_IDLE_Req_E or W_err_IDLE_grant_E or W_err_North_Req_E or W_err_North_grant_E or W_err_East_Req_W or W_err_East_grant_W or W_err_West_Req_S or W_err_West_grant_S or W_err_South_Req_L or W_err_South_grant_L or W_err_Local_Req_N or W_err_Local_grant_N or W_err_IDLE_Req_W or W_err_IDLE_grant_W or W_err_North_Req_W or W_err_North_grant_W or W_err_East_Req_S or W_err_East_grant_S or W_err_West_Req_L or W_err_West_grant_L or W_err_South_Req_N or W_err_South_grant_N or W_err_Local_Req_E or W_err_Local_grant_E or W_err_IDLE_Req_S or W_err_IDLE_grant_S or W_err_North_Req_S or W_err_North_grant_S or W_err_East_Req_L or W_err_East_grant_L or W_err_West_Req_N or W_err_West_grant_N or W_err_South_Req_E or W_err_South_grant_E or W_err_Local_Req_W or W_err_Local_grant_W or W_err_IDLE_Req_L or W_err_IDLE_grant_L or W_err_North_Req_L or W_err_North_grant_L or W_err_East_Req_N or W_err_East_grant_N or W_err_West_Req_E or W_err_West_grant_E or W_err_South_Req_W or W_err_South_grant_W or W_err_Local_Req_S or W_err_Local_grant_S or W_err_arbiter_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_N_grant_N or W_err_no_Req_E_grant_E or W_err_no_Req_W_grant_W or W_err_no_Req_S_grant_S or W_err_no_Req_L_grant_L or -- South Arbiter_in checker outputs S_err_Requests_state_in_state_not_equal or S_err_IDLE_Req_N or S_err_IDLE_grant_N or S_err_North_Req_N or S_err_North_grant_N or S_err_East_Req_E or S_err_East_grant_E or S_err_West_Req_W or S_err_West_grant_W or S_err_South_Req_S or S_err_South_grant_S or S_err_Local_Req_L or S_err_Local_grant_L or S_err_IDLE_Req_E or S_err_IDLE_grant_E or S_err_North_Req_E or S_err_North_grant_E or S_err_East_Req_W or S_err_East_grant_W or S_err_West_Req_S or S_err_West_grant_S or S_err_South_Req_L or S_err_South_grant_L or S_err_Local_Req_N or S_err_Local_grant_N or S_err_IDLE_Req_W or S_err_IDLE_grant_W or S_err_North_Req_W or S_err_North_grant_W or S_err_East_Req_S or S_err_East_grant_S or S_err_West_Req_L or S_err_West_grant_L or S_err_South_Req_N or S_err_South_grant_N or S_err_Local_Req_E or S_err_Local_grant_E or S_err_IDLE_Req_S or S_err_IDLE_grant_S or S_err_North_Req_S or S_err_North_grant_S or S_err_East_Req_L or S_err_East_grant_L or S_err_West_Req_N or S_err_West_grant_N or S_err_South_Req_E or S_err_South_grant_E or S_err_Local_Req_W or S_err_Local_grant_W or S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or S_err_East_Req_N or S_err_East_grant_N or S_err_West_Req_E or S_err_West_grant_E or S_err_South_Req_W or S_err_South_grant_W or S_err_Local_Req_S or S_err_Local_grant_S or S_err_arbiter_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_N_grant_N or S_err_no_Req_E_grant_E or S_err_no_Req_W_grant_W or S_err_no_Req_S_grant_S or S_err_no_Req_L_grant_L or -- Local Arbiter_in checker outputs L_err_Requests_state_in_state_not_equal or L_err_IDLE_Req_N or L_err_IDLE_grant_N or L_err_North_Req_N or L_err_North_grant_N or L_err_East_Req_E or L_err_East_grant_E or L_err_West_Req_W or L_err_West_grant_W or L_err_South_Req_S or L_err_South_grant_S or L_err_Local_Req_L or L_err_Local_grant_L or L_err_IDLE_Req_E or L_err_IDLE_grant_E or L_err_North_Req_E or L_err_North_grant_E or L_err_East_Req_W or L_err_East_grant_W or L_err_West_Req_S or L_err_West_grant_S or L_err_South_Req_L or L_err_South_grant_L or L_err_Local_Req_N or L_err_Local_grant_N or L_err_IDLE_Req_W or L_err_IDLE_grant_W or L_err_North_Req_W or L_err_North_grant_W or L_err_East_Req_S or L_err_East_grant_S or L_err_West_Req_L or L_err_West_grant_L or L_err_South_Req_N or L_err_South_grant_N or L_err_Local_Req_E or L_err_Local_grant_E or L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or L_err_East_Req_L or L_err_East_grant_L or L_err_West_Req_N or L_err_West_grant_N or L_err_South_Req_E or L_err_South_grant_E or L_err_Local_Req_W or L_err_Local_grant_W or L_err_IDLE_Req_L or L_err_IDLE_grant_L or L_err_North_Req_L or L_err_North_grant_L or L_err_East_Req_N or L_err_East_grant_N or L_err_West_Req_E or L_err_West_grant_E or L_err_South_Req_W or L_err_South_grant_W or L_err_Local_Req_S or L_err_Local_grant_S or L_err_arbiter_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_N_grant_N or L_err_no_Req_E_grant_E or L_err_no_Req_W_grant_W or L_err_no_Req_S_grant_S or L_err_no_Req_L_grant_L or -- Arbiter_out checker outputs -- North Arbiter_out checker outputs N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_IDLE_req_X_N or N_err_North_req_X_N or N_err_North_credit_not_zero_req_X_N_grant_N or N_err_North_credit_zero_or_not_req_X_N_not_grant_N or N_err_East_req_X_E or N_err_East_credit_not_zero_req_X_E_grant_E or N_err_East_credit_zero_or_not_req_X_E_not_grant_E or N_err_West_req_X_W or N_err_West_credit_not_zero_req_X_W_grant_W or N_err_West_credit_zero_or_not_req_X_W_not_grant_W or N_err_South_req_X_S or N_err_South_credit_not_zero_req_X_S_grant_S or N_err_South_credit_zero_or_not_req_X_S_not_grant_S or N_err_Local_req_X_L or N_err_Local_credit_not_zero_req_X_L_grant_L or N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or N_err_IDLE_req_X_E or N_err_North_req_X_E or N_err_East_req_X_W or N_err_West_req_X_S or N_err_South_req_X_L or N_err_Local_req_X_N or N_err_IDLE_req_X_W or N_err_North_req_X_W or N_err_East_req_X_S or N_err_West_req_X_L or N_err_South_req_X_N or N_err_Local_req_X_E or N_err_IDLE_req_X_S or N_err_North_req_X_S or N_err_East_req_X_L or N_err_West_req_X_N or N_err_South_req_X_E or N_err_Local_req_X_W or N_err_IDLE_req_X_L or N_err_North_req_X_L or N_err_East_req_X_N or N_err_West_req_X_E or N_err_South_req_X_W or N_err_Local_req_X_S or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_state_North_Invalid_Grant or N_err_state_East_Invalid_Grant or N_err_state_West_Invalid_Grant or N_err_state_South_Invalid_Grant or N_err_state_Local_Invalid_Grant or N_err_Grants_onehot_or_all_zero or -- East Arbiter_out checker outputs E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_IDLE_req_X_N or E_err_North_req_X_N or E_err_North_credit_not_zero_req_X_N_grant_N or E_err_North_credit_zero_or_not_req_X_N_not_grant_N or E_err_East_req_X_E or E_err_East_credit_not_zero_req_X_E_grant_E or E_err_East_credit_zero_or_not_req_X_E_not_grant_E or E_err_West_req_X_W or E_err_West_credit_not_zero_req_X_W_grant_W or E_err_West_credit_zero_or_not_req_X_W_not_grant_W or E_err_South_req_X_S or E_err_South_credit_not_zero_req_X_S_grant_S or E_err_South_credit_zero_or_not_req_X_S_not_grant_S or E_err_Local_req_X_L or E_err_Local_credit_not_zero_req_X_L_grant_L or E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or E_err_IDLE_req_X_E or E_err_North_req_X_E or E_err_East_req_X_W or E_err_West_req_X_S or E_err_South_req_X_L or E_err_Local_req_X_N or E_err_IDLE_req_X_W or E_err_North_req_X_W or E_err_East_req_X_S or E_err_West_req_X_L or E_err_South_req_X_N or E_err_Local_req_X_E or E_err_IDLE_req_X_S or E_err_North_req_X_S or E_err_East_req_X_L or E_err_West_req_X_N or E_err_South_req_X_E or E_err_Local_req_X_W or E_err_IDLE_req_X_L or E_err_North_req_X_L or E_err_East_req_X_N or E_err_West_req_X_E or E_err_South_req_X_W or E_err_Local_req_X_S or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_state_North_Invalid_Grant or E_err_state_East_Invalid_Grant or E_err_state_West_Invalid_Grant or E_err_state_South_Invalid_Grant or E_err_state_Local_Invalid_Grant or E_err_Grants_onehot_or_all_zero or -- West Arbiter_out checker outputs W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_IDLE_req_X_N or W_err_North_req_X_N or W_err_North_credit_not_zero_req_X_N_grant_N or W_err_North_credit_zero_or_not_req_X_N_not_grant_N or W_err_East_req_X_E or W_err_East_credit_not_zero_req_X_E_grant_E or W_err_East_credit_zero_or_not_req_X_E_not_grant_E or W_err_West_req_X_W or W_err_West_credit_not_zero_req_X_W_grant_W or W_err_West_credit_zero_or_not_req_X_W_not_grant_W or W_err_South_req_X_S or W_err_South_credit_not_zero_req_X_S_grant_S or W_err_South_credit_zero_or_not_req_X_S_not_grant_S or W_err_Local_req_X_L or W_err_Local_credit_not_zero_req_X_L_grant_L or W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or W_err_IDLE_req_X_E or W_err_North_req_X_E or W_err_East_req_X_W or W_err_West_req_X_S or W_err_South_req_X_L or W_err_Local_req_X_N or W_err_IDLE_req_X_W or W_err_North_req_X_W or W_err_East_req_X_S or W_err_West_req_X_L or W_err_South_req_X_N or W_err_Local_req_X_E or W_err_IDLE_req_X_S or W_err_North_req_X_S or W_err_East_req_X_L or W_err_West_req_X_N or W_err_South_req_X_E or W_err_Local_req_X_W or W_err_IDLE_req_X_L or W_err_North_req_X_L or W_err_East_req_X_N or W_err_West_req_X_E or W_err_South_req_X_W or W_err_Local_req_X_S or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_state_North_Invalid_Grant or W_err_state_East_Invalid_Grant or W_err_state_West_Invalid_Grant or W_err_state_South_Invalid_Grant or W_err_state_Local_Invalid_Grant or W_err_Grants_onehot_or_all_zero or -- South Arbiter_out checker outputs S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_IDLE_req_X_N or S_err_North_req_X_N or S_err_North_credit_not_zero_req_X_N_grant_N or S_err_North_credit_zero_or_not_req_X_N_not_grant_N or S_err_East_req_X_E or S_err_East_credit_not_zero_req_X_E_grant_E or S_err_East_credit_zero_or_not_req_X_E_not_grant_E or S_err_West_req_X_W or S_err_West_credit_not_zero_req_X_W_grant_W or S_err_West_credit_zero_or_not_req_X_W_not_grant_W or S_err_South_req_X_S or S_err_South_credit_not_zero_req_X_S_grant_S or S_err_South_credit_zero_or_not_req_X_S_not_grant_S or S_err_Local_req_X_L or S_err_Local_credit_not_zero_req_X_L_grant_L or S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or S_err_IDLE_req_X_E or S_err_North_req_X_E or S_err_East_req_X_W or S_err_West_req_X_S or S_err_South_req_X_L or S_err_Local_req_X_N or S_err_IDLE_req_X_W or S_err_North_req_X_W or S_err_East_req_X_S or S_err_West_req_X_L or S_err_South_req_X_N or S_err_Local_req_X_E or S_err_IDLE_req_X_S or S_err_North_req_X_S or S_err_East_req_X_L or S_err_West_req_X_N or S_err_South_req_X_E or S_err_Local_req_X_W or S_err_IDLE_req_X_L or S_err_North_req_X_L or S_err_East_req_X_N or S_err_West_req_X_E or S_err_South_req_X_W or S_err_Local_req_X_S or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_state_North_Invalid_Grant or S_err_state_East_Invalid_Grant or S_err_state_West_Invalid_Grant or S_err_state_South_Invalid_Grant or S_err_state_Local_Invalid_Grant or S_err_Grants_onehot_or_all_zero or -- Local Arbiter_out checker outputs L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_IDLE_req_X_N or L_err_North_req_X_N or L_err_North_credit_not_zero_req_X_N_grant_N or L_err_North_credit_zero_or_not_req_X_N_not_grant_N or L_err_East_req_X_E or L_err_East_credit_not_zero_req_X_E_grant_E or L_err_East_credit_zero_or_not_req_X_E_not_grant_E or L_err_West_req_X_W or L_err_West_credit_not_zero_req_X_W_grant_W or L_err_West_credit_zero_or_not_req_X_W_not_grant_W or L_err_South_req_X_S or L_err_South_credit_not_zero_req_X_S_grant_S or L_err_South_credit_zero_or_not_req_X_S_not_grant_S or L_err_Local_req_X_L or L_err_Local_credit_not_zero_req_X_L_grant_L or L_err_Local_credit_zero_or_not_req_X_L_not_grant_L or L_err_IDLE_req_X_E or L_err_North_req_X_E or L_err_East_req_X_W or L_err_West_req_X_S or L_err_South_req_X_L or L_err_Local_req_X_N or L_err_IDLE_req_X_W or L_err_North_req_X_W or L_err_East_req_X_S or L_err_West_req_X_L or L_err_South_req_X_N or L_err_Local_req_X_E or L_err_IDLE_req_X_S or L_err_North_req_X_S or L_err_East_req_X_L or L_err_West_req_X_N or L_err_South_req_X_E or L_err_Local_req_X_W or L_err_IDLE_req_X_L or L_err_North_req_X_L or L_err_East_req_X_N or L_err_West_req_X_E or L_err_South_req_X_W or L_err_Local_req_X_S or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_state_North_Invalid_Grant or L_err_state_East_Invalid_Grant or L_err_state_West_Invalid_Grant or L_err_state_South_Invalid_Grant or L_err_state_Local_Invalid_Grant or L_err_Grants_onehot_or_all_zero; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Turn fault checkers -- FIFO N2E_turn_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_E1 or N_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or N_err_header_not_empty_Req_E_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_East_Req_E or N_err_East_grant_E or N_err_IDLE_Req_E or N_err_IDLE_grant_E or N_err_North_Req_E or N_err_North_grant_E or N_err_Local_Req_E or N_err_Local_grant_E or N_err_South_Req_E or N_err_South_grant_E or N_err_West_Req_E or N_err_West_grant_E or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_IDLE_req_X_N or E_err_North_req_X_N or E_err_North_credit_not_zero_req_X_N_grant_N or E_err_North_credit_zero_or_not_req_X_N_not_grant_N or E_err_Local_req_X_N or E_err_South_req_X_N or E_err_West_req_X_N or E_err_East_req_X_N or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or W_err_South_req_X_N or W_err_West_req_X_N or W_err_East_req_X_N or err_grant_E_N_sig_not_empty_N_grant_E_N or err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- FIFO N2W_turn_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_W1 or N_err_dst_addr_cur_addr_not_W1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or N_err_header_not_empty_Req_W_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_West_Req_W or N_err_West_grant_W or N_err_East_Req_W or N_err_East_grant_W or N_err_IDLE_Req_W or N_err_IDLE_grant_W or N_err_North_Req_W or N_err_North_grant_W or N_err_Local_Req_W or N_err_Local_grant_W or N_err_South_Req_W or N_err_South_grant_W or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_IDLE_req_X_N or W_err_North_req_X_N or W_err_North_credit_not_zero_req_X_N_grant_N or W_err_North_credit_zero_or_not_req_X_N_not_grant_N or W_err_Local_req_X_N or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_N_sig_not_empty_N_grant_W_N or err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- FIFO E2N_turn_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_N1 or E_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or E_err_header_not_empty_Req_N_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_IDLE_Req_N or E_err_IDLE_grant_N or E_err_North_Req_N or E_err_North_grant_N or E_err_Local_Req_N or E_err_Local_grant_N or E_err_South_Req_N or E_err_South_grant_N or E_err_West_Req_N or E_err_West_grant_N or E_err_East_Req_N or E_err_East_grant_N or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_East_req_X_E or N_err_East_credit_not_zero_req_X_E_grant_E or N_err_East_credit_zero_or_not_req_X_E_not_grant_E or N_err_IDLE_req_X_E or N_err_North_req_X_E or N_err_Local_req_X_E or N_err_South_req_X_E or N_err_West_req_X_E or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_Grants_onehot_or_all_zero or err_grant_N_E_sig_not_empty_E_grant_N_E or err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO E2S_turn_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_S1 or E_err_dst_addr_cur_addr_not_S1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or E_err_header_not_empty_Req_S_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_South_Req_S or E_err_South_grant_S or E_err_West_Req_S or E_err_West_grant_S or E_err_East_Req_S or E_err_East_grant_S or E_err_IDLE_Req_S or E_err_IDLE_grant_S or E_err_North_Req_S or E_err_North_grant_S or E_err_Local_Req_S or E_err_Local_grant_S or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_East_req_X_E or S_err_East_credit_not_zero_req_X_E_grant_E or S_err_East_credit_zero_or_not_req_X_E_not_grant_E or S_err_IDLE_req_X_E or S_err_North_req_X_E or S_err_Local_req_X_E or S_err_South_req_X_E or S_err_West_req_X_E or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_E_sig_not_empty_E_grant_S_E or err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO W2N_turn_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_N1 or W_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_N_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_IDLE_Req_N or W_err_IDLE_grant_N or W_err_North_Req_N or W_err_North_grant_N or W_err_Local_Req_N or W_err_Local_grant_N or W_err_South_Req_N or W_err_South_grant_N or W_err_West_Req_N or W_err_West_grant_N or W_err_East_Req_N or W_err_East_grant_N or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_West_req_X_W or N_err_West_credit_not_zero_req_X_W_grant_W or N_err_West_credit_zero_or_not_req_X_W_not_grant_W or N_err_East_req_X_W or N_err_IDLE_req_X_W or N_err_North_req_X_W or N_err_Local_req_X_W or N_err_South_req_X_W or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or err_grant_N_W_sig_not_empty_W_grant_N_W or err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO W2S_turn_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_S1 or W_err_dst_addr_cur_addr_not_S1 or W_err_header_not_empty_faulty_drop_packet_in or W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or W_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_S_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_South_Req_S or W_err_South_grant_S or W_err_West_Req_S or W_err_West_grant_S or W_err_East_Req_S or W_err_East_grant_S or W_err_IDLE_Req_S or W_err_IDLE_grant_S or W_err_North_Req_S or W_err_North_grant_S or W_err_Local_Req_S or W_err_Local_grant_S or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_West_req_X_W or S_err_West_credit_not_zero_req_X_W_grant_W or S_err_West_credit_zero_or_not_req_X_W_not_grant_W or S_err_East_req_X_W or S_err_IDLE_req_X_W or S_err_North_req_X_W or S_err_Local_req_X_W or S_err_South_req_X_W or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_W_sig_not_empty_W_grant_S_W or err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO S2E_turn_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_E1 or S_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_E_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_East_Req_E or S_err_East_grant_E or S_err_IDLE_Req_E or S_err_IDLE_grant_E or S_err_North_Req_E or S_err_North_grant_E or S_err_Local_Req_E or S_err_Local_grant_E or S_err_South_Req_E or S_err_South_grant_E or S_err_West_Req_E or S_err_West_grant_E or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_South_req_X_S or E_err_South_credit_not_zero_req_X_S_grant_S or E_err_South_credit_zero_or_not_req_X_S_not_grant_S or E_err_West_req_X_S or E_err_East_req_X_S or E_err_IDLE_req_X_S or E_err_North_req_X_S or E_err_Local_req_X_S or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or err_grant_E_S_sig_not_empty_S_grant_E_S or err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_grants_valid_not_match or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- FIFO S2W_turn_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_W1 or S_err_dst_addr_cur_addr_not_W1 or S_err_header_not_empty_faulty_drop_packet_in or S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or S_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_W_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_West_Req_W or S_err_West_grant_W or S_err_East_Req_W or S_err_East_grant_W or S_err_IDLE_Req_W or S_err_IDLE_grant_W or S_err_North_Req_W or S_err_North_grant_W or S_err_Local_Req_W or S_err_Local_grant_W or S_err_South_Req_W or S_err_South_grant_W or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_South_req_X_S or W_err_South_credit_not_zero_req_X_S_grant_S or W_err_South_credit_zero_or_not_req_X_S_not_grant_S or W_err_West_req_X_S or W_err_East_req_X_S or W_err_IDLE_req_X_S or W_err_North_req_X_S or W_err_Local_req_X_S or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_S_sig_not_empty_S_grant_W_S or err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- Path fault checkers -- FIFO N2S_path_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_S1 or N_err_dst_addr_cur_addr_not_S1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or N_err_header_not_empty_Req_S_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_South_Req_S or N_err_South_grant_S or N_err_West_Req_S or N_err_West_grant_S or N_err_East_Req_S or N_err_East_grant_S or N_err_IDLE_Req_S or N_err_IDLE_grant_S or N_err_North_Req_S or N_err_North_grant_S or N_err_Local_Req_S or N_err_Local_grant_S or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_IDLE_req_X_N or S_err_North_req_X_N or S_err_North_credit_not_zero_req_X_N_grant_N or S_err_North_credit_zero_or_not_req_X_N_not_grant_N or S_err_Local_req_X_N or S_err_South_req_X_N or S_err_West_req_X_N or S_err_East_req_X_N or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_N_sig_not_empty_N_grant_S_N or err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO S2N_path_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_N1 or S_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_N_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_IDLE_Req_N or S_err_IDLE_grant_N or S_err_North_Req_N or S_err_North_grant_N or S_err_Local_Req_N or S_err_Local_grant_N or S_err_South_Req_N or S_err_South_grant_N or S_err_West_Req_N or S_err_West_grant_N or S_err_East_Req_N or S_err_East_grant_N or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_South_req_X_S or N_err_South_credit_not_zero_req_X_S_grant_S or N_err_South_credit_zero_or_not_req_X_S_not_grant_S or N_err_West_req_X_S or N_err_East_req_X_S or N_err_IDLE_req_X_S or N_err_North_req_X_S or N_err_Local_req_X_S or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or err_grant_N_S_sig_not_empty_S_grant_N_S or err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO E2W_path_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_W1 or E_err_dst_addr_cur_addr_not_W1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or E_err_header_not_empty_Req_W_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_West_Req_W or E_err_West_grant_W or E_err_East_Req_W or E_err_East_grant_W or E_err_IDLE_Req_W or E_err_IDLE_grant_W or E_err_North_Req_W or E_err_North_grant_W or E_err_Local_Req_W or E_err_Local_grant_W or E_err_South_Req_W or E_err_South_grant_W or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_East_req_X_E or W_err_East_credit_not_zero_req_X_E_grant_E or W_err_East_credit_zero_or_not_req_X_E_not_grant_E or W_err_IDLE_req_X_E or W_err_North_req_X_E or W_err_Local_req_X_E or W_err_South_req_X_E or W_err_West_req_X_E or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_E_sig_not_empty_E_grant_W_E or err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- FIFO W2E_path_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_E1 or W_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_E_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_East_Req_E or W_err_East_grant_E or W_err_IDLE_Req_E or W_err_IDLE_grant_E or W_err_North_Req_E or W_err_North_grant_E or W_err_Local_Req_E or W_err_Local_grant_E or W_err_South_Req_E or W_err_South_grant_E or W_err_West_Req_E or W_err_West_grant_E or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_West_req_X_W or E_err_West_credit_not_zero_req_X_W_grant_W or E_err_West_credit_zero_or_not_req_X_W_not_grant_W or E_err_East_req_X_W or E_err_IDLE_req_X_W or E_err_North_req_X_W or E_err_Local_req_X_W or E_err_South_req_X_W or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or err_grant_E_W_sig_not_empty_W_grant_E_W or err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- Checkers for Paths/turns from/to Local port -- FIFO L2N_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_N1 or L_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_N_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_IDLE_Req_N or L_err_IDLE_grant_N or L_err_North_Req_N or L_err_North_grant_N or L_err_Local_Req_N or L_err_Local_grant_N or L_err_South_Req_N or L_err_South_grant_N or L_err_West_Req_N or L_err_West_grant_N or L_err_East_Req_N or L_err_East_grant_N or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_Local_req_X_L or N_err_Local_credit_not_zero_req_X_L_grant_L or N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or N_err_South_req_X_L or N_err_West_req_X_L or N_err_East_req_X_L or N_err_IDLE_req_X_L or N_err_North_req_X_L or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or err_grant_N_L_sig_not_empty_L_grant_N_L or err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO L2E_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_E1 or L_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_E_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_East_Req_E or L_err_East_grant_E or L_err_IDLE_Req_E or L_err_IDLE_grant_E or L_err_North_Req_E or L_err_North_grant_E or L_err_Local_Req_E or L_err_Local_grant_E or L_err_South_Req_E or L_err_South_grant_E or L_err_West_Req_E or L_err_West_grant_E or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_Local_req_X_L or E_err_Local_credit_not_zero_req_X_L_grant_L or E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or E_err_South_req_X_L or E_err_West_req_X_L or E_err_East_req_X_L or E_err_IDLE_req_X_L or E_err_North_req_X_L or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or err_grant_E_L_sig_not_empty_L_grant_E_L or err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_grants_valid_not_match or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- FIFO L2W_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_W1 or L_err_dst_addr_cur_addr_not_W1 or L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_W_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_West_Req_W or L_err_West_grant_W or L_err_East_Req_W or L_err_East_grant_W or L_err_IDLE_Req_W or L_err_IDLE_grant_W or L_err_North_Req_W or L_err_North_grant_W or L_err_Local_Req_W or L_err_Local_grant_W or L_err_South_Req_W or L_err_South_grant_W or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_Local_req_X_L or W_err_Local_credit_not_zero_req_X_L_grant_L or W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or W_err_South_req_X_L or W_err_West_req_X_L or W_err_East_req_X_L or W_err_IDLE_req_X_L or W_err_North_req_X_L or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_L_sig_not_empty_L_grant_W_L or err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- FIFO L2S_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_S1 or L_err_dst_addr_cur_addr_not_S1 or L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_S_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_South_Req_S or L_err_South_grant_S or L_err_West_Req_S or L_err_West_grant_S or L_err_East_Req_S or L_err_East_grant_S or L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or L_err_Local_Req_S or L_err_Local_grant_S or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_Local_req_X_L or S_err_Local_credit_not_zero_req_X_L_grant_L or S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or S_err_South_req_X_L or S_err_West_req_X_L or S_err_East_req_X_L or S_err_IDLE_req_X_L or S_err_North_req_X_L or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO N2L_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_Req_L_in or N_err_dst_addr_cur_addr_not_Req_L_in or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or --N_err_header_not_empty_Req_L_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_Local_Req_L or N_err_Local_grant_L or N_err_South_Req_L or N_err_South_grant_L or N_err_West_Req_L or N_err_West_grant_L or N_err_East_Req_L or N_err_East_grant_L or N_err_IDLE_Req_L or N_err_IDLE_grant_L or N_err_North_Req_L or N_err_North_grant_L or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_IDLE_req_X_N or L_err_North_req_X_N or L_err_North_credit_not_zero_req_X_N_grant_N or L_err_North_credit_zero_or_not_req_X_N_not_grant_N or L_err_Local_req_X_N or L_err_South_req_X_N or L_err_West_req_X_N or L_err_East_req_X_N or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_N_sig_not_empty_N_grant_L_N or err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; -- FIFO E2L_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_Req_L_in or E_err_dst_addr_cur_addr_not_Req_L_in or E_err_header_not_empty_faulty_drop_packet_in or E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or E_err_header_not_empty_faulty_Req_in_all_zero or --E_err_header_not_empty_Req_L_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_Local_Req_L or E_err_Local_grant_L or E_err_South_Req_L or E_err_South_grant_L or E_err_West_Req_L or E_err_West_grant_L or E_err_East_Req_L or E_err_East_grant_L or E_err_IDLE_Req_L or E_err_IDLE_grant_L or E_err_North_Req_L or E_err_North_grant_L or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_East_req_X_E or L_err_East_credit_not_zero_req_X_E_grant_E or L_err_East_credit_zero_or_not_req_X_E_not_grant_E or L_err_IDLE_req_X_E or L_err_North_req_X_E or L_err_Local_req_X_E or L_err_South_req_X_E or L_err_West_req_X_E or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_E_sig_not_empty_E_grant_L_E or err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; -- FIFO W2L_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_Req_L_in or W_err_dst_addr_cur_addr_not_Req_L_in or W_err_header_not_empty_faulty_drop_packet_in or W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or W_err_header_not_empty_faulty_Req_in_all_zero or --W_err_header_not_empty_Req_L_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_Local_Req_L or W_err_Local_grant_L or W_err_South_Req_L or W_err_South_grant_L or W_err_West_Req_L or W_err_West_grant_L or W_err_East_Req_L or W_err_East_grant_L or W_err_IDLE_Req_L or W_err_IDLE_grant_L or W_err_North_Req_L or W_err_North_grant_L or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_West_req_X_W or L_err_West_credit_not_zero_req_X_W_grant_W or L_err_West_credit_zero_or_not_req_X_W_not_grant_W or L_err_East_req_X_W or L_err_IDLE_req_X_W or L_err_North_req_X_W or L_err_Local_req_X_W or L_err_South_req_X_W or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_W_sig_not_empty_W_grant_L_W or err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; -- FIFO S2L_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_Req_L_in or S_err_dst_addr_cur_addr_not_Req_L_in or S_err_header_not_empty_faulty_drop_packet_in or S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or S_err_header_not_empty_faulty_Req_in_all_zero or --S_err_header_not_empty_Req_L_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_Local_Req_L or S_err_Local_grant_L or S_err_South_Req_L or S_err_South_grant_L or S_err_West_Req_L or S_err_West_grant_L or S_err_East_Req_L or S_err_East_grant_L or S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_South_req_X_S or L_err_South_credit_not_zero_req_X_S_grant_S or L_err_South_credit_zero_or_not_req_X_S_not_grant_S or L_err_West_req_X_S or L_err_East_req_X_S or L_err_IDLE_req_X_S or L_err_North_req_X_S or L_err_Local_req_X_S or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Link faults and turn faults -- The order of the turns/paths from left to right (MSB to LSB) -> 20 bits -- N2E, N2W, E2N, E2S, -- W2N, W2S, S2E, S2W, -- N2S, S2N, E2W, W2E, -- L2N, L2E, L2W, L2S, -- N2L, E2L, W2L, S2L ------------------------------------------------------------------------------------------------------------------------------ -- Taking classified fault information to output ------------------------------------------------------------------------------------------------------------------------------ turn_faults <= faulty_N2E_turn_fault & faulty_N2W_turn_fault & faulty_E2N_turn_fault & faulty_E2S_turn_fault & faulty_W2N_turn_fault & faulty_W2S_turn_fault & faulty_S2E_turn_fault & faulty_S2W_turn_fault & faulty_N2S_path_fault & faulty_S2N_path_fault & faulty_E2W_path_fault & faulty_W2E_path_fault & faulty_L2N_fault & faulty_L2E_fault & faulty_L2W_fault & faulty_L2S_fault & faulty_N2L_fault & faulty_E2L_fault & faulty_W2L_fault & faulty_S2L_fault; -- 20 bits because of turn/path faults --link_faults <= '0' & '0' & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L; -- sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L; link_faults <= sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L; ------------------------------------------------------------------------------------------------------------------------------ -- Taking non-classified fault information to output ------------------------------------------------------------------------------------------------------------------------------ turn_faults_async <= N2E_turn_fault & N2W_turn_fault & E2N_turn_fault & E2S_turn_fault & W2N_turn_fault & W2S_turn_fault & S2E_turn_fault & S2W_turn_fault & N2S_path_fault & S2N_path_fault & E2W_path_fault & W2E_path_fault & L2N_fault & L2E_fault & L2W_fault & L2S_fault & N2L_fault & E2L_fault & W2L_fault & S2L_fault; -- 20 bits because of turn/path faults --link_faults_async <= '0' & '0' & faulty_packet_W & faulty_packet_S & faulty_packet_L; -- faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L; link_faults_async <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L; ------------------------------------------------------------------------------------------------------------------------------ Faulty_N_out <= sig_Faulty_N_out; Faulty_E_out <= sig_Faulty_E_out; Faulty_W_out <= sig_Faulty_W_out; Faulty_S_out <= sig_Faulty_S_out; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the counter_threshold modules CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N, Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out); CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E, Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out); CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W, Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out); CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S, Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out); CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L, Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Checker Counter Threshold modules -- Turn faults CHK_CT_N2E_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2E_turn_fault, Healthy_packet => not_N2E_turn_fault, Healthy => Healthy_N2E_turn_fault, Intermittent => intermittent_N2E_turn_fault, Faulty => faulty_N2E_turn_fault); CHK_CT_N2W_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2W_turn_fault, Healthy_packet => not_N2W_turn_fault, Healthy => Healthy_N2W_turn_fault, Intermittent => intermittent_N2W_turn_fault, Faulty => faulty_N2W_turn_fault); CHK_CT_E2N_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2N_turn_fault, Healthy_packet => not_E2N_turn_fault, Healthy => Healthy_E2N_turn_fault, Intermittent => intermittent_E2N_turn_fault, Faulty => faulty_E2N_turn_fault); CHK_CT_E2S_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2S_turn_fault, Healthy_packet => not_E2S_turn_fault, Healthy => Healthy_E2S_turn_fault, Intermittent => intermittent_E2S_turn_fault, Faulty => faulty_E2S_turn_fault); CHK_CT_W2N_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2N_turn_fault, Healthy_packet => not_W2N_turn_fault, Healthy => Healthy_W2N_turn_fault, Intermittent => intermittent_W2N_turn_fault, Faulty => faulty_W2N_turn_fault); CHK_CT_W2S_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2S_turn_fault, Healthy_packet => not_W2S_turn_fault, Healthy => Healthy_W2S_turn_fault, Intermittent => intermittent_W2S_turn_fault, Faulty => faulty_W2S_turn_fault); CHK_CT_S2E_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2E_turn_fault, Healthy_packet => not_S2E_turn_fault, Healthy => Healthy_S2E_turn_fault, Intermittent => intermittent_S2E_turn_fault, Faulty => faulty_S2E_turn_fault); CHK_CT_S2W_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2W_turn_fault, Healthy_packet => not_S2W_turn_fault, Healthy => Healthy_S2W_turn_fault, Intermittent => intermittent_S2W_turn_fault, Faulty => faulty_S2W_turn_fault); --Path faults CHK_CT_N2S_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2S_path_fault, Healthy_packet => not_N2S_path_fault, Healthy => Healthy_N2S_path_fault, Intermittent => intermittent_N2S_path_fault, Faulty => faulty_N2S_path_fault); CHK_CT_S2N_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2N_path_fault, Healthy_packet => not_S2N_path_fault, Healthy => Healthy_S2N_path_fault, Intermittent => intermittent_S2N_path_fault, Faulty => faulty_S2N_path_fault); CHK_CT_E2W_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2W_path_fault, Healthy_packet => not_E2W_path_fault, Healthy => Healthy_E2W_path_fault, Intermittent => intermittent_E2W_path_fault, Faulty => faulty_E2W_path_fault); CHK_CT_W2E_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2E_path_fault, Healthy_packet => not_W2E_path_fault, Healthy => Healthy_W2E_path_fault, Intermittent => intermittent_W2E_path_fault, Faulty => faulty_W2E_path_fault); -- Local port related faults (to/from local port) CHK_CT_L2N_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2N_fault, Healthy_packet => not_L2N_fault, Healthy => Healthy_L2N_fault, Intermittent => intermittent_L2N_fault, Faulty => faulty_L2N_fault); CHK_CT_L2E_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2E_fault, Healthy_packet => not_L2E_fault, Healthy => Healthy_L2E_fault, Intermittent => intermittent_L2E_fault, Faulty => faulty_L2E_fault); CHK_CT_L2W_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2W_fault, Healthy_packet => not_L2W_fault, Healthy => Healthy_L2W_fault, Intermittent => intermittent_L2W_fault, Faulty => faulty_L2W_fault); CHK_CT_L2S_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2S_fault, Healthy_packet => not_L2S_fault, Healthy => Healthy_L2S_fault, Intermittent => intermittent_L2S_fault, Faulty => faulty_L2S_fault); CHK_CT_N2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2L_fault, Healthy_packet => not_N2L_fault, Healthy => Healthy_N2L_fault, Intermittent => intermittent_N2L_fault, Faulty => faulty_N2L_fault); CHK_CT_E2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2L_fault, Healthy_packet => not_E2L_fault, Healthy => Healthy_E2L_fault, Intermittent => intermittent_E2L_fault, Faulty => faulty_E2L_fault); CHK_CT_W2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2L_fault, Healthy_packet => not_W2L_fault, Healthy => Healthy_W2L_fault, Intermittent => intermittent_W2L_fault, Faulty => faulty_W2L_fault); CHK_CT_S2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2L_fault, Healthy_packet => not_S2L_fault, Healthy => Healthy_S2L_fault, Intermittent => intermittent_S2L_fault, Faulty => faulty_S2L_fault); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- All the FIFOs FIFO_N: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N, read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN, credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_FIFO_to_N_FIFO, SO=> fault_DO_serial_N_FIFO_to_E_FIFO, -- Checker outputs -- Functional checkers err_empty_full => N_err_empty_full, err_empty_read_en => N_err_empty_read_en, err_full_write_en => N_err_full_write_en, err_state_in_onehot => N_err_state_in_onehot, err_read_pointer_in_onehot => N_err_read_pointer_in_onehot, err_write_pointer_in_onehot => N_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => N_err_write_en_write_pointer, err_not_write_en_write_pointer => N_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => N_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => N_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => N_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => N_err_read_pointer_write_pointer_full, err_read_pointer_increment => N_err_read_pointer_increment, err_read_pointer_not_increment => N_err_read_pointer_not_increment, err_write_en => N_err_write_en, err_not_write_en => N_err_not_write_en, err_not_write_en1 => N_err_not_write_en1, err_not_write_en2 => N_err_not_write_en2, err_read_en_mismatch => N_err_read_en_mismatch, err_read_en_mismatch1 => N_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => N_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => N_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => N_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => N_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => N_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => N_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => N_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => N_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => N_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => N_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => N_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => N_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => N_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => N_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => N_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => N_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => N_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => N_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => N_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => N_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => N_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_E: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E, read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE, credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_FIFO_to_E_FIFO, SO=> fault_DO_serial_E_FIFO_to_W_FIFO, -- Checker outputs -- Functional checkers err_empty_full => E_err_empty_full, err_empty_read_en => E_err_empty_read_en, err_full_write_en => E_err_full_write_en, err_state_in_onehot => E_err_state_in_onehot, err_read_pointer_in_onehot => E_err_read_pointer_in_onehot, err_write_pointer_in_onehot => E_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => E_err_write_en_write_pointer, err_not_write_en_write_pointer => E_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => E_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => E_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => E_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => E_err_read_pointer_write_pointer_full, err_read_pointer_increment => E_err_read_pointer_increment, err_read_pointer_not_increment => E_err_read_pointer_not_increment, err_write_en => E_err_write_en, err_not_write_en => E_err_not_write_en, err_not_write_en1 => E_err_not_write_en1, err_not_write_en2 => E_err_not_write_en2, err_read_en_mismatch => E_err_read_en_mismatch, err_read_en_mismatch1 => E_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => E_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => E_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => E_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => E_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => E_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => E_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => E_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => E_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => E_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => E_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => E_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => E_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => E_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => E_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => E_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => E_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => E_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => E_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => E_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => E_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_W: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W, read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW, credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_FIFO_to_W_FIFO, SO=> fault_DO_serial_W_FIFO_to_S_FIFO, -- Checker outputs -- Functional checkers err_empty_full => W_err_empty_full, err_empty_read_en => W_err_empty_read_en, err_full_write_en => W_err_full_write_en, err_state_in_onehot => W_err_state_in_onehot, err_read_pointer_in_onehot => W_err_read_pointer_in_onehot, err_write_pointer_in_onehot => W_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => W_err_write_en_write_pointer, err_not_write_en_write_pointer => W_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => W_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => W_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => W_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => W_err_read_pointer_write_pointer_full, err_read_pointer_increment => W_err_read_pointer_increment, err_read_pointer_not_increment => W_err_read_pointer_not_increment, err_write_en => W_err_write_en, err_not_write_en => W_err_not_write_en, err_not_write_en1 => W_err_not_write_en1, err_not_write_en2 => W_err_not_write_en2, err_read_en_mismatch => W_err_read_en_mismatch, err_read_en_mismatch1 => W_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => W_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => W_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => W_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => W_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => W_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => W_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => W_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => W_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => W_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => W_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => W_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => W_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => W_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => W_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => W_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => W_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => W_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => W_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => W_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => W_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_S: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S, read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS, credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_FIFO_to_S_FIFO, SO=> fault_DO_serial_S_FIFO_to_L_LBDR, -- Checker outputs -- Functional checkers err_empty_full => S_err_empty_full, err_empty_read_en => S_err_empty_read_en, err_full_write_en => S_err_full_write_en, err_state_in_onehot => S_err_state_in_onehot, err_read_pointer_in_onehot => S_err_read_pointer_in_onehot, err_write_pointer_in_onehot => S_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => S_err_write_en_write_pointer, err_not_write_en_write_pointer => S_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => S_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => S_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => S_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => S_err_read_pointer_write_pointer_full, err_read_pointer_increment => S_err_read_pointer_increment, err_read_pointer_not_increment => S_err_read_pointer_not_increment, err_write_en => S_err_write_en, err_not_write_en => S_err_not_write_en, err_not_write_en1 => S_err_not_write_en1, err_not_write_en2 => S_err_not_write_en2, err_read_en_mismatch => S_err_read_en_mismatch, err_read_en_mismatch1 => S_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => S_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => S_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => S_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => S_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => S_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => S_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => S_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => S_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => S_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => S_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => S_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => S_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => S_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => S_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => S_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => S_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => S_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => S_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => S_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => S_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_L: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L, read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L, credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L, TCK=> TCK, SE=> SE, UE=> UE, SI=> SI, SO=> fault_DO_serial_L_FIFO_to_N_FIFO, -- Checker outputs -- Functional checkers err_empty_full => L_err_empty_full, err_empty_read_en => L_err_empty_read_en, err_full_write_en => L_err_full_write_en, err_state_in_onehot => L_err_state_in_onehot, err_read_pointer_in_onehot => L_err_read_pointer_in_onehot, err_write_pointer_in_onehot => L_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => L_err_write_en_write_pointer, err_not_write_en_write_pointer => L_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => L_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => L_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => L_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => L_err_read_pointer_write_pointer_full, err_read_pointer_increment => L_err_read_pointer_increment, err_read_pointer_not_increment => L_err_read_pointer_not_increment, err_write_en => L_err_write_en, err_not_write_en => L_err_not_write_en, err_not_write_en1 => L_err_not_write_en1, err_not_write_en2 => L_err_not_write_en2, err_read_en_mismatch => L_err_read_en_mismatch, err_read_en_mismatch1 => L_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => L_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => L_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => L_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => L_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => L_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => L_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => L_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => L_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => L_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => L_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => L_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => L_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => L_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => L_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => L_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => L_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => L_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => L_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => L_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => L_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ parity_LBDR_N: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_N, empty_N, LBDR_Fault_N); parity_LBDR_E: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_E, empty_E, LBDR_Fault_E); parity_LBDR_W: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_W, empty_W, LBDR_Fault_W); parity_LBDR_S: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_S, empty_S, LBDR_Fault_S); parity_LBDR_L: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_L, empty_L, LBDR_Fault_L); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ --- all the LBDRs LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_N, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_N, packet_drop_order => packet_drop_order_N, grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN, Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_LBDR_to_N_LBDR, SO=> fault_DO_serial_N_LBDR_to_E_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => N_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => N_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => N_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => N_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => N_err_grants_onehot, err_grants_mismatch => N_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => N_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => N_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => N_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => N_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => N_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => N_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => N_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => N_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => N_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => N_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => N_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => N_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => N_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => N_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => N_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => N_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => N_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => N_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => N_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => N_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => N_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_E, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_E, packet_drop_order => packet_drop_order_E, grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE, Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_LBDR_to_E_LBDR, SO=> fault_DO_serial_E_LBDR_to_W_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => E_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => E_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => E_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => E_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => E_err_grants_onehot, err_grants_mismatch => E_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => E_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => E_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => E_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => E_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => E_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => E_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => E_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => E_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => E_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => E_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => E_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => E_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => E_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => E_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => E_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => E_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => E_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => E_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => E_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_W, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_W, packet_drop_order => packet_drop_order_W, grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW, Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_LBDR_to_W_LBDR, SO=> fault_DO_serial_W_LBDR_to_S_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => W_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => W_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => W_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => W_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => W_err_grants_onehot, err_grants_mismatch => W_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => W_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => W_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => W_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => W_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => W_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => W_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => W_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => W_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => W_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => W_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => W_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => W_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => W_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => W_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => W_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => W_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => W_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => W_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => W_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_S, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_S, packet_drop_order => packet_drop_order_S, grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS, Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_LBDR_to_S_LBDR, SO=> fault_DO_serial_S_LBDR_to_Allocator, -- Checker outputs err_header_empty_Requests_FF_Requests_in => S_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => S_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => S_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => S_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => S_err_grants_onehot, err_grants_mismatch => S_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => S_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => S_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => S_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => S_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => S_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => S_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => S_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => S_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => S_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => S_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => S_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => S_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => S_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => S_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => S_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => S_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => S_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => S_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => S_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_L, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_L, packet_drop_order => packet_drop_order_L, grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0', Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_FIFO_to_L_LBDR, SO=> fault_DO_serial_L_LBDR_to_N_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => L_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => L_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => L_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => L_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => L_err_grants_onehot, err_grants_mismatch => L_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => L_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => L_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => L_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => L_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => L_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => L_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => L_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => L_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => L_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => L_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => L_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => L_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => L_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => L_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => L_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => L_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => L_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => L_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => L_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- switch allocator allocator_unit: allocator port map ( reset => reset, clk => clk, -- flow control credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L, -- requests from the LBDRS req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL, req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL, req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL, req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL, req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0', empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L, valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L, -- grant_X_Y means the grant for X output port towards Y input port -- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot! grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL, grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL, grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL, grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL, grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_LBDR_to_Allocator, SO=> SO, -- Make sure this is correction -- Also check inside Allocator's logic -- Checker outputs -- Allocator logic checker outputs err_grant_N_N_sig_not_empty_N_grant_N_N => err_grant_N_N_sig_not_empty_N_grant_N_N , err_not_grant_N_N_sig_or_empty_N_not_grant_N_N => err_not_grant_N_N_sig_or_empty_N_not_grant_N_N , err_grant_N_E_sig_not_empty_E_grant_N_E => err_grant_N_E_sig_not_empty_E_grant_N_E , err_not_grant_N_E_sig_or_empty_E_not_grant_N_E => err_not_grant_N_E_sig_or_empty_E_not_grant_N_E , err_grant_N_W_sig_not_empty_W_grant_N_W => err_grant_N_W_sig_not_empty_W_grant_N_W , err_not_grant_N_W_sig_or_empty_W_not_grant_N_W => err_not_grant_N_W_sig_or_empty_W_not_grant_N_W , err_grant_N_S_sig_not_empty_S_grant_N_S => err_grant_N_S_sig_not_empty_S_grant_N_S , err_not_grant_N_S_sig_or_empty_S_not_grant_N_S => err_not_grant_N_S_sig_or_empty_S_not_grant_N_S , err_grant_N_L_sig_not_empty_L_grant_N_L => err_grant_N_L_sig_not_empty_L_grant_N_L , err_not_grant_N_L_sig_or_empty_L_not_grant_N_L => err_not_grant_N_L_sig_or_empty_L_not_grant_N_L , err_grant_E_N_sig_not_empty_N_grant_E_N => err_grant_E_N_sig_not_empty_N_grant_E_N , err_not_grant_E_N_sig_or_empty_N_not_grant_E_N => err_not_grant_E_N_sig_or_empty_N_not_grant_E_N , err_grant_E_E_sig_not_empty_E_grant_E_E => err_grant_E_E_sig_not_empty_E_grant_E_E , err_not_grant_E_E_sig_or_empty_E_not_grant_E_E => err_not_grant_E_E_sig_or_empty_E_not_grant_E_E , err_grant_E_W_sig_not_empty_W_grant_E_W => err_grant_E_W_sig_not_empty_W_grant_E_W , err_not_grant_E_W_sig_or_empty_W_not_grant_E_W => err_not_grant_E_W_sig_or_empty_W_not_grant_E_W , err_grant_E_S_sig_not_empty_S_grant_E_S => err_grant_E_S_sig_not_empty_S_grant_E_S , err_not_grant_E_S_sig_or_empty_S_not_grant_E_S => err_not_grant_E_S_sig_or_empty_S_not_grant_E_S , err_grant_E_L_sig_not_empty_L_grant_E_L => err_grant_E_L_sig_not_empty_L_grant_E_L , err_not_grant_E_L_sig_or_empty_L_not_grant_E_L => err_not_grant_E_L_sig_or_empty_L_not_grant_E_L , err_grant_W_N_sig_not_empty_N_grant_W_N => err_grant_W_N_sig_not_empty_N_grant_W_N , err_not_grant_W_N_sig_or_empty_N_not_grant_W_N => err_not_grant_W_N_sig_or_empty_N_not_grant_W_N , err_grant_W_E_sig_not_empty_E_grant_W_E => err_grant_W_E_sig_not_empty_E_grant_W_E , err_not_grant_W_E_sig_or_empty_E_not_grant_W_E => err_not_grant_W_E_sig_or_empty_E_not_grant_W_E , err_grant_W_W_sig_not_empty_W_grant_W_W => err_grant_W_W_sig_not_empty_W_grant_W_W , err_not_grant_W_W_sig_or_empty_W_not_grant_W_W => err_not_grant_W_W_sig_or_empty_W_not_grant_W_W , err_grant_W_S_sig_not_empty_S_grant_W_S => err_grant_W_S_sig_not_empty_S_grant_W_S , err_not_grant_W_S_sig_or_empty_S_not_grant_W_S => err_not_grant_W_S_sig_or_empty_S_not_grant_W_S , err_grant_W_L_sig_not_empty_L_grant_W_L => err_grant_W_L_sig_not_empty_L_grant_W_L , err_not_grant_W_L_sig_or_empty_L_not_grant_W_L => err_not_grant_W_L_sig_or_empty_L_not_grant_W_L , err_grant_S_N_sig_not_empty_N_grant_S_N => err_grant_S_N_sig_not_empty_N_grant_S_N , err_not_grant_S_N_sig_or_empty_N_not_grant_S_N => err_not_grant_S_N_sig_or_empty_N_not_grant_S_N , err_grant_S_E_sig_not_empty_E_grant_S_E => err_grant_S_E_sig_not_empty_E_grant_S_E , err_not_grant_S_E_sig_or_empty_E_not_grant_S_E => err_not_grant_S_E_sig_or_empty_E_not_grant_S_E , err_grant_S_W_sig_not_empty_W_grant_S_W => err_grant_S_W_sig_not_empty_W_grant_S_W , err_not_grant_S_W_sig_or_empty_W_not_grant_S_W => err_not_grant_S_W_sig_or_empty_W_not_grant_S_W , err_grant_S_S_sig_not_empty_S_grant_S_S => err_grant_S_S_sig_not_empty_S_grant_S_S , err_not_grant_S_S_sig_or_empty_S_not_grant_S_S => err_not_grant_S_S_sig_or_empty_S_not_grant_S_S , err_grant_S_L_sig_not_empty_L_grant_S_L => err_grant_S_L_sig_not_empty_L_grant_S_L , err_not_grant_S_L_sig_or_empty_L_not_grant_S_L => err_not_grant_S_L_sig_or_empty_L_not_grant_S_L , err_grant_L_N_sig_not_empty_N_grant_L_N => err_grant_L_N_sig_not_empty_N_grant_L_N , err_not_grant_L_N_sig_or_empty_N_not_grant_L_N => err_not_grant_L_N_sig_or_empty_N_not_grant_L_N , err_grant_L_E_sig_not_empty_E_grant_L_E => err_grant_L_E_sig_not_empty_E_grant_L_E , err_not_grant_L_E_sig_or_empty_E_not_grant_L_E => err_not_grant_L_E_sig_or_empty_E_not_grant_L_E , err_grant_L_W_sig_not_empty_W_grant_L_W => err_grant_L_W_sig_not_empty_W_grant_L_W , err_not_grant_L_W_sig_or_empty_W_not_grant_L_W => err_not_grant_L_W_sig_or_empty_W_not_grant_L_W , err_grant_L_S_sig_not_empty_S_grant_L_S => err_grant_L_S_sig_not_empty_S_grant_L_S , err_not_grant_L_S_sig_or_empty_S_not_grant_L_S => err_not_grant_L_S_sig_or_empty_S_not_grant_L_S , err_grant_L_L_sig_not_empty_L_grant_L_L => err_grant_L_L_sig_not_empty_L_grant_L_L , err_not_grant_L_L_sig_or_empty_L_not_grant_L_L => err_not_grant_L_L_sig_or_empty_L_not_grant_L_L , err_grant_signals_not_empty_grant_N => err_grant_signals_not_empty_grant_N , err_not_grant_signals_empty_not_grant_N => err_not_grant_signals_empty_not_grant_N , err_grant_signals_not_empty_grant_E => err_grant_signals_not_empty_grant_E , err_not_grant_signals_empty_not_grant_E => err_not_grant_signals_empty_not_grant_E , err_grant_signals_not_empty_grant_W => err_grant_signals_not_empty_grant_W , err_not_grant_signals_empty_not_grant_W => err_not_grant_signals_empty_not_grant_W , err_grant_signals_not_empty_grant_S => err_grant_signals_not_empty_grant_S , err_not_grant_signals_empty_not_grant_S => err_not_grant_signals_empty_not_grant_S , err_grant_signals_not_empty_grant_L => err_grant_signals_not_empty_grant_L , err_not_grant_signals_empty_not_grant_L => err_not_grant_signals_empty_not_grant_L , err_grants_valid_not_match => err_grants_valid_not_match , -- Allocator credit counter logic checker outputs err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal , err_credit_in_N_credit_counter_N_out_increment => err_credit_in_N_credit_counter_N_out_increment , err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change => err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change , err_grant_N_credit_counter_N_out_decrement => err_grant_N_credit_counter_N_out_decrement , err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change => err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change , err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal , err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal , err_credit_in_E_credit_counter_E_out_increment => err_credit_in_E_credit_counter_E_out_increment , err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change => err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change , err_grant_E_credit_counter_E_out_decrement => err_grant_E_credit_counter_E_out_decrement , err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change => err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change , err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal , err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal , err_credit_in_W_credit_counter_W_out_increment => err_credit_in_W_credit_counter_W_out_increment , err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change => err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change , err_grant_W_credit_counter_W_out_decrement => err_grant_W_credit_counter_W_out_decrement , err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change => err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change , err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal , err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal , err_credit_in_S_credit_counter_S_out_increment => err_credit_in_S_credit_counter_S_out_increment , err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change => err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change , err_grant_S_credit_counter_S_out_decrement => err_grant_S_credit_counter_S_out_decrement , err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change => err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change , err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal , err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal , err_credit_in_L_credit_counter_L_out_increment => err_credit_in_L_credit_counter_L_out_increment , err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change => err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change , err_grant_L_credit_counter_L_out_decrement => err_grant_L_credit_counter_L_out_decrement , err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change => err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change , err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal , -- North Arbiter_in Checker outputs N_err_Requests_state_in_state_not_equal => N_err_Requests_state_in_state_not_equal, N_err_IDLE_Req_N => N_err_IDLE_Req_N, N_err_IDLE_grant_N => N_err_IDLE_grant_N, N_err_North_Req_N => N_err_North_Req_N, N_err_North_grant_N => N_err_North_grant_N, N_err_East_Req_E => N_err_East_Req_E, N_err_East_grant_E => N_err_East_grant_E, N_err_West_Req_W => N_err_West_Req_W, N_err_West_grant_W => N_err_West_grant_W, N_err_South_Req_S => N_err_South_Req_S, N_err_South_grant_S => N_err_South_grant_S, N_err_Local_Req_L => N_err_Local_Req_L, N_err_Local_grant_L => N_err_Local_grant_L, N_err_IDLE_Req_E => N_err_IDLE_Req_E, N_err_IDLE_grant_E => N_err_IDLE_grant_E, N_err_North_Req_E => N_err_North_Req_E, N_err_North_grant_E => N_err_North_grant_E, N_err_East_Req_W => N_err_East_Req_W, N_err_East_grant_W => N_err_East_grant_W, N_err_West_Req_S => N_err_West_Req_S, N_err_West_grant_S => N_err_West_grant_S, N_err_South_Req_L => N_err_South_Req_L, N_err_South_grant_L => N_err_South_grant_L, N_err_Local_Req_N => N_err_Local_Req_N, N_err_Local_grant_N => N_err_Local_grant_N, N_err_IDLE_Req_W => N_err_IDLE_Req_W, N_err_IDLE_grant_W => N_err_IDLE_grant_W, N_err_North_Req_W => N_err_North_Req_W, N_err_North_grant_W => N_err_North_grant_W, N_err_East_Req_S => N_err_East_Req_S, N_err_East_grant_S => N_err_East_grant_S, N_err_West_Req_L => N_err_West_Req_L, N_err_West_grant_L => N_err_West_grant_L, N_err_South_Req_N => N_err_South_Req_N, N_err_South_grant_N => N_err_South_grant_N, N_err_Local_Req_E => N_err_Local_Req_E, N_err_Local_grant_E => N_err_Local_grant_E, N_err_IDLE_Req_S => N_err_IDLE_Req_S, N_err_IDLE_grant_S => N_err_IDLE_grant_S, N_err_North_Req_S => N_err_North_Req_S, N_err_North_grant_S => N_err_North_grant_S, N_err_East_Req_L => N_err_East_Req_L, N_err_East_grant_L => N_err_East_grant_L, N_err_West_Req_N => N_err_West_Req_N, N_err_West_grant_N => N_err_West_grant_N, N_err_South_Req_E => N_err_South_Req_E, N_err_South_grant_E => N_err_South_grant_E, N_err_Local_Req_W => N_err_Local_Req_W, N_err_Local_grant_W => N_err_Local_grant_W, N_err_IDLE_Req_L => N_err_IDLE_Req_L, N_err_IDLE_grant_L => N_err_IDLE_grant_L, N_err_North_Req_L => N_err_North_Req_L, N_err_North_grant_L => N_err_North_grant_L, N_err_East_Req_N => N_err_East_Req_N, N_err_East_grant_N => N_err_East_grant_N, N_err_West_Req_E => N_err_West_Req_E, N_err_West_grant_E => N_err_West_grant_E, N_err_South_Req_W => N_err_South_Req_W, N_err_South_grant_W => N_err_South_grant_W, N_err_Local_Req_S => N_err_Local_Req_S, N_err_Local_grant_S => N_err_Local_grant_S, N_err_state_in_onehot => N_err_arbiter_state_in_onehot, N_err_no_request_grants => N_err_no_request_grants, N_err_request_no_grants => N_err_request_no_grants, N_err_no_Req_N_grant_N => N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E => N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W => N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S => N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L => N_err_no_Req_L_grant_L, -- East Arbiter_in Checker outputs E_err_Requests_state_in_state_not_equal => E_err_Requests_state_in_state_not_equal, E_err_IDLE_Req_N => E_err_IDLE_Req_N, E_err_IDLE_grant_N => E_err_IDLE_grant_N, E_err_North_Req_N => E_err_North_Req_N, E_err_North_grant_N => E_err_North_grant_N, E_err_East_Req_E => E_err_East_Req_E, E_err_East_grant_E => E_err_East_grant_E, E_err_West_Req_W => E_err_West_Req_W, E_err_West_grant_W => E_err_West_grant_W, E_err_South_Req_S => E_err_South_Req_S, E_err_South_grant_S => E_err_South_grant_S, E_err_Local_Req_L => E_err_Local_Req_L, E_err_Local_grant_L => E_err_Local_grant_L, E_err_IDLE_Req_E => E_err_IDLE_Req_E, E_err_IDLE_grant_E => E_err_IDLE_grant_E, E_err_North_Req_E => E_err_North_Req_E, E_err_North_grant_E => E_err_North_grant_E, E_err_East_Req_W => E_err_East_Req_W, E_err_East_grant_W => E_err_East_grant_W, E_err_West_Req_S => E_err_West_Req_S, E_err_West_grant_S => E_err_West_grant_S, E_err_South_Req_L => E_err_South_Req_L, E_err_South_grant_L => E_err_South_grant_L, E_err_Local_Req_N => E_err_Local_Req_N, E_err_Local_grant_N => E_err_Local_grant_N, E_err_IDLE_Req_W => E_err_IDLE_Req_W, E_err_IDLE_grant_W => E_err_IDLE_grant_W, E_err_North_Req_W => E_err_North_Req_W, E_err_North_grant_W => E_err_North_grant_W, E_err_East_Req_S => E_err_East_Req_S, E_err_East_grant_S => E_err_East_grant_S, E_err_West_Req_L => E_err_West_Req_L, E_err_West_grant_L => E_err_West_grant_L, E_err_South_Req_N => E_err_South_Req_N, E_err_South_grant_N => E_err_South_grant_N, E_err_Local_Req_E => E_err_Local_Req_E, E_err_Local_grant_E => E_err_Local_grant_E, E_err_IDLE_Req_S => E_err_IDLE_Req_S, E_err_IDLE_grant_S => E_err_IDLE_grant_S, E_err_North_Req_S => E_err_North_Req_S, E_err_North_grant_S => E_err_North_grant_S, E_err_East_Req_L => E_err_East_Req_L, E_err_East_grant_L => E_err_East_grant_L, E_err_West_Req_N => E_err_West_Req_N, E_err_West_grant_N => E_err_West_grant_N, E_err_South_Req_E => E_err_South_Req_E, E_err_South_grant_E => E_err_South_grant_E, E_err_Local_Req_W => E_err_Local_Req_W, E_err_Local_grant_W => E_err_Local_grant_W, E_err_IDLE_Req_L => E_err_IDLE_Req_L, E_err_IDLE_grant_L => E_err_IDLE_grant_L, E_err_North_Req_L => E_err_North_Req_L, E_err_North_grant_L => E_err_North_grant_L, E_err_East_Req_N => E_err_East_Req_N, E_err_East_grant_N => E_err_East_grant_N, E_err_West_Req_E => E_err_West_Req_E, E_err_West_grant_E => E_err_West_grant_E, E_err_South_Req_W => E_err_South_Req_W, E_err_South_grant_W => E_err_South_grant_W, E_err_Local_Req_S => E_err_Local_Req_S, E_err_Local_grant_S => E_err_Local_grant_S, E_err_state_in_onehot => E_err_arbiter_state_in_onehot, E_err_no_request_grants => E_err_no_request_grants, E_err_request_no_grants => E_err_request_no_grants, E_err_no_Req_N_grant_N => E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E => E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W => E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S => E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L => E_err_no_Req_L_grant_L, -- West Arbiter_in Checker outputs W_err_Requests_state_in_state_not_equal => W_err_Requests_state_in_state_not_equal, W_err_IDLE_Req_N => W_err_IDLE_Req_N, W_err_IDLE_grant_N => W_err_IDLE_grant_N, W_err_North_Req_N => W_err_North_Req_N, W_err_North_grant_N => W_err_North_grant_N, W_err_East_Req_E => W_err_East_Req_E, W_err_East_grant_E => W_err_East_grant_E, W_err_West_Req_W => W_err_West_Req_W, W_err_West_grant_W => W_err_West_grant_W, W_err_South_Req_S => W_err_South_Req_S, W_err_South_grant_S => W_err_South_grant_S, W_err_Local_Req_L => W_err_Local_Req_L, W_err_Local_grant_L => W_err_Local_grant_L, W_err_IDLE_Req_E => W_err_IDLE_Req_E, W_err_IDLE_grant_E => W_err_IDLE_grant_E, W_err_North_Req_E => W_err_North_Req_E, W_err_North_grant_E => W_err_North_grant_E, W_err_East_Req_W => W_err_East_Req_W, W_err_East_grant_W => W_err_East_grant_W, W_err_West_Req_S => W_err_West_Req_S, W_err_West_grant_S => W_err_West_grant_S, W_err_South_Req_L => W_err_South_Req_L, W_err_South_grant_L => W_err_South_grant_L, W_err_Local_Req_N => W_err_Local_Req_N, W_err_Local_grant_N => W_err_Local_grant_N, W_err_IDLE_Req_W => W_err_IDLE_Req_W, W_err_IDLE_grant_W => W_err_IDLE_grant_W, W_err_North_Req_W => W_err_North_Req_W, W_err_North_grant_W => W_err_North_grant_W, W_err_East_Req_S => W_err_East_Req_S, W_err_East_grant_S => W_err_East_grant_S, W_err_West_Req_L => W_err_West_Req_L, W_err_West_grant_L => W_err_West_grant_L, W_err_South_Req_N => W_err_South_Req_N, W_err_South_grant_N => W_err_South_grant_N, W_err_Local_Req_E => W_err_Local_Req_E, W_err_Local_grant_E => W_err_Local_grant_E, W_err_IDLE_Req_S => W_err_IDLE_Req_S, W_err_IDLE_grant_S => W_err_IDLE_grant_S, W_err_North_Req_S => W_err_North_Req_S, W_err_North_grant_S => W_err_North_grant_S, W_err_East_Req_L => W_err_East_Req_L, W_err_East_grant_L => W_err_East_grant_L, W_err_West_Req_N => W_err_West_Req_N, W_err_West_grant_N => W_err_West_grant_N, W_err_South_Req_E => W_err_South_Req_E, W_err_South_grant_E => W_err_South_grant_E, W_err_Local_Req_W => W_err_Local_Req_W, W_err_Local_grant_W => W_err_Local_grant_W, W_err_IDLE_Req_L => W_err_IDLE_Req_L, W_err_IDLE_grant_L => W_err_IDLE_grant_L, W_err_North_Req_L => W_err_North_Req_L, W_err_North_grant_L => W_err_North_grant_L, W_err_East_Req_N => W_err_East_Req_N, W_err_East_grant_N => W_err_East_grant_N, W_err_West_Req_E => W_err_West_Req_E, W_err_West_grant_E => W_err_West_grant_E, W_err_South_Req_W => W_err_South_Req_W, W_err_South_grant_W => W_err_South_grant_W, W_err_Local_Req_S => W_err_Local_Req_S, W_err_Local_grant_S => W_err_Local_grant_S, W_err_state_in_onehot => W_err_arbiter_state_in_onehot, W_err_no_request_grants => W_err_no_request_grants, W_err_request_no_grants => W_err_request_no_grants, W_err_no_Req_N_grant_N => W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E => W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W => W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S => W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L => W_err_no_Req_L_grant_L, -- South Arbiter_in Checker outputs S_err_Requests_state_in_state_not_equal => S_err_Requests_state_in_state_not_equal, S_err_IDLE_Req_N => S_err_IDLE_Req_N, S_err_IDLE_grant_N => S_err_IDLE_grant_N, S_err_North_Req_N => S_err_North_Req_N, S_err_North_grant_N => S_err_North_grant_N, S_err_East_Req_E => S_err_East_Req_E, S_err_East_grant_E => S_err_East_grant_E, S_err_West_Req_W => S_err_West_Req_W, S_err_West_grant_W => S_err_West_grant_W, S_err_South_Req_S => S_err_South_Req_S, S_err_South_grant_S => S_err_South_grant_S, S_err_Local_Req_L => S_err_Local_Req_L, S_err_Local_grant_L => S_err_Local_grant_L, S_err_IDLE_Req_E => S_err_IDLE_Req_E, S_err_IDLE_grant_E => S_err_IDLE_grant_E, S_err_North_Req_E => S_err_North_Req_E, S_err_North_grant_E => S_err_North_grant_E, S_err_East_Req_W => S_err_East_Req_W, S_err_East_grant_W => S_err_East_grant_W, S_err_West_Req_S => S_err_West_Req_S, S_err_West_grant_S => S_err_West_grant_S, S_err_South_Req_L => S_err_South_Req_L, S_err_South_grant_L => S_err_South_grant_L, S_err_Local_Req_N => S_err_Local_Req_N, S_err_Local_grant_N => S_err_Local_grant_N, S_err_IDLE_Req_W => S_err_IDLE_Req_W, S_err_IDLE_grant_W => S_err_IDLE_grant_W, S_err_North_Req_W => S_err_North_Req_W, S_err_North_grant_W => S_err_North_grant_W, S_err_East_Req_S => S_err_East_Req_S, S_err_East_grant_S => S_err_East_grant_S, S_err_West_Req_L => S_err_West_Req_L, S_err_West_grant_L => S_err_West_grant_L, S_err_South_Req_N => S_err_South_Req_N, S_err_South_grant_N => S_err_South_grant_N, S_err_Local_Req_E => S_err_Local_Req_E, S_err_Local_grant_E => S_err_Local_grant_E, S_err_IDLE_Req_S => S_err_IDLE_Req_S, S_err_IDLE_grant_S => S_err_IDLE_grant_S, S_err_North_Req_S => S_err_North_Req_S, S_err_North_grant_S => S_err_North_grant_S, S_err_East_Req_L => S_err_East_Req_L, S_err_East_grant_L => S_err_East_grant_L, S_err_West_Req_N => S_err_West_Req_N, S_err_West_grant_N => S_err_West_grant_N, S_err_South_Req_E => S_err_South_Req_E, S_err_South_grant_E => S_err_South_grant_E, S_err_Local_Req_W => S_err_Local_Req_W, S_err_Local_grant_W => S_err_Local_grant_W, S_err_IDLE_Req_L => S_err_IDLE_Req_L, S_err_IDLE_grant_L => S_err_IDLE_grant_L, S_err_North_Req_L => S_err_North_Req_L, S_err_North_grant_L => S_err_North_grant_L, S_err_East_Req_N => S_err_East_Req_N, S_err_East_grant_N => S_err_East_grant_N, S_err_West_Req_E => S_err_West_Req_E, S_err_West_grant_E => S_err_West_grant_E, S_err_South_Req_W => S_err_South_Req_W, S_err_South_grant_W => S_err_South_grant_W, S_err_Local_Req_S => S_err_Local_Req_S, S_err_Local_grant_S => S_err_Local_grant_S, S_err_state_in_onehot => S_err_arbiter_state_in_onehot, S_err_no_request_grants => S_err_no_request_grants, S_err_request_no_grants => S_err_request_no_grants, S_err_no_Req_N_grant_N => S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E => S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W => S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S => S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L => S_err_no_Req_L_grant_L, -- Local Arbiter_in Checker outputs L_err_Requests_state_in_state_not_equal => L_err_Requests_state_in_state_not_equal, L_err_IDLE_Req_N => L_err_IDLE_Req_N, L_err_IDLE_grant_N => L_err_IDLE_grant_N, L_err_North_Req_N => L_err_North_Req_N, L_err_North_grant_N => L_err_North_grant_N, L_err_East_Req_E => L_err_East_Req_E, L_err_East_grant_E => L_err_East_grant_E, L_err_West_Req_W => L_err_West_Req_W, L_err_West_grant_W => L_err_West_grant_W, L_err_South_Req_S => L_err_South_Req_S, L_err_South_grant_S => L_err_South_grant_S, L_err_Local_Req_L => L_err_Local_Req_L, L_err_Local_grant_L => L_err_Local_grant_L, L_err_IDLE_Req_E => L_err_IDLE_Req_E, L_err_IDLE_grant_E => L_err_IDLE_grant_E, L_err_North_Req_E => L_err_North_Req_E, L_err_North_grant_E => L_err_North_grant_E, L_err_East_Req_W => L_err_East_Req_W, L_err_East_grant_W => L_err_East_grant_W, L_err_West_Req_S => L_err_West_Req_S, L_err_West_grant_S => L_err_West_grant_S, L_err_South_Req_L => L_err_South_Req_L, L_err_South_grant_L => L_err_South_grant_L, L_err_Local_Req_N => L_err_Local_Req_N, L_err_Local_grant_N => L_err_Local_grant_N, L_err_IDLE_Req_W => L_err_IDLE_Req_W, L_err_IDLE_grant_W => L_err_IDLE_grant_W, L_err_North_Req_W => L_err_North_Req_W, L_err_North_grant_W => L_err_North_grant_W, L_err_East_Req_S => L_err_East_Req_S, L_err_East_grant_S => L_err_East_grant_S, L_err_West_Req_L => L_err_West_Req_L, L_err_West_grant_L => L_err_West_grant_L, L_err_South_Req_N => L_err_South_Req_N, L_err_South_grant_N => L_err_South_grant_N, L_err_Local_Req_E => L_err_Local_Req_E, L_err_Local_grant_E => L_err_Local_grant_E, L_err_IDLE_Req_S => L_err_IDLE_Req_S, L_err_IDLE_grant_S => L_err_IDLE_grant_S, L_err_North_Req_S => L_err_North_Req_S, L_err_North_grant_S => L_err_North_grant_S, L_err_East_Req_L => L_err_East_Req_L, L_err_East_grant_L => L_err_East_grant_L, L_err_West_Req_N => L_err_West_Req_N, L_err_West_grant_N => L_err_West_grant_N, L_err_South_Req_E => L_err_South_Req_E, L_err_South_grant_E => L_err_South_grant_E, L_err_Local_Req_W => L_err_Local_Req_W, L_err_Local_grant_W => L_err_Local_grant_W, L_err_IDLE_Req_L => L_err_IDLE_Req_L, L_err_IDLE_grant_L => L_err_IDLE_grant_L, L_err_North_Req_L => L_err_North_Req_L, L_err_North_grant_L => L_err_North_grant_L, L_err_East_Req_N => L_err_East_Req_N, L_err_East_grant_N => L_err_East_grant_N, L_err_West_Req_E => L_err_West_Req_E, L_err_West_grant_E => L_err_West_grant_E, L_err_South_Req_W => L_err_South_Req_W, L_err_South_grant_W => L_err_South_grant_W, L_err_Local_Req_S => L_err_Local_Req_S, L_err_Local_grant_S => L_err_Local_grant_S, L_err_state_in_onehot => L_err_arbiter_state_in_onehot, L_err_no_request_grants => L_err_no_request_grants, L_err_request_no_grants => L_err_request_no_grants, L_err_no_Req_N_grant_N => L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E => L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W => L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S => L_err_no_Req_S_grant_S, L_err_no_Req_L_grant_L => L_err_no_Req_L_grant_L, -- Arbiter_out checker outputs -- North Arbiter_out checker outputs N_arbiter_out_err_Requests_state_in_state_not_equal => N_arbiter_out_err_Requests_state_in_state_not_equal, N_err_IDLE_req_X_N => N_err_IDLE_req_X_N, N_err_North_req_X_N => N_err_North_req_X_N, N_err_North_credit_not_zero_req_X_N_grant_N => N_err_North_credit_not_zero_req_X_N_grant_N, N_err_North_credit_zero_or_not_req_X_N_not_grant_N => N_err_North_credit_zero_or_not_req_X_N_not_grant_N, N_err_East_req_X_E => N_err_East_req_X_E, N_err_East_credit_not_zero_req_X_E_grant_E => N_err_East_credit_not_zero_req_X_E_grant_E, N_err_East_credit_zero_or_not_req_X_E_not_grant_E => N_err_East_credit_zero_or_not_req_X_E_not_grant_E, N_err_West_req_X_W => N_err_West_req_X_W, N_err_West_credit_not_zero_req_X_W_grant_W => N_err_West_credit_not_zero_req_X_W_grant_W, N_err_West_credit_zero_or_not_req_X_W_not_grant_W => N_err_West_credit_zero_or_not_req_X_W_not_grant_W, N_err_South_req_X_S => N_err_South_req_X_S, N_err_South_credit_not_zero_req_X_S_grant_S => N_err_South_credit_not_zero_req_X_S_grant_S, N_err_South_credit_zero_or_not_req_X_S_not_grant_S => N_err_South_credit_zero_or_not_req_X_S_not_grant_S, N_err_Local_req_X_L => N_err_Local_req_X_L, N_err_Local_credit_not_zero_req_X_L_grant_L => N_err_Local_credit_not_zero_req_X_L_grant_L, N_err_Local_credit_zero_or_not_req_X_L_not_grant_L => N_err_Local_credit_zero_or_not_req_X_L_not_grant_L, N_err_IDLE_req_X_E => N_err_IDLE_req_X_E, N_err_North_req_X_E => N_err_North_req_X_E, N_err_East_req_X_W => N_err_East_req_X_W, N_err_West_req_X_S => N_err_West_req_X_S, N_err_South_req_X_L => N_err_South_req_X_L, N_err_Local_req_X_N => N_err_Local_req_X_N, N_err_IDLE_req_X_W => N_err_IDLE_req_X_W, N_err_North_req_X_W => N_err_North_req_X_W, N_err_East_req_X_S => N_err_East_req_X_S, N_err_West_req_X_L => N_err_West_req_X_L, N_err_South_req_X_N => N_err_South_req_X_N, N_err_Local_req_X_E => N_err_Local_req_X_E, N_err_IDLE_req_X_S => N_err_IDLE_req_X_S, N_err_North_req_X_S => N_err_North_req_X_S, N_err_East_req_X_L => N_err_East_req_X_L, N_err_West_req_X_N => N_err_West_req_X_N, N_err_South_req_X_E => N_err_South_req_X_E, N_err_Local_req_X_W => N_err_Local_req_X_W, N_err_IDLE_req_X_L => N_err_IDLE_req_X_L, N_err_North_req_X_L => N_err_North_req_X_L, N_err_East_req_X_N => N_err_East_req_X_N, N_err_West_req_X_E => N_err_West_req_X_E, N_err_South_req_X_W => N_err_South_req_X_W, N_err_Local_req_X_S => N_err_Local_req_X_S, N_arbiter_out_err_state_in_onehot => N_arbiter_out_err_state_in_onehot, N_arbiter_out_err_no_request_grants => N_arbiter_out_err_no_request_grants, N_err_request_IDLE_state => N_err_request_IDLE_state, N_err_request_IDLE_not_Grants => N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant => N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant => N_err_state_East_Invalid_Grant, N_err_state_West_Invalid_Grant => N_err_state_West_Invalid_Grant, N_err_state_South_Invalid_Grant => N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant => N_err_state_Local_Invalid_Grant, N_err_Grants_onehot_or_all_zero => N_err_Grants_onehot_or_all_zero, -- East Arbiter_out checker outputs E_arbiter_out_err_Requests_state_in_state_not_equal => E_arbiter_out_err_Requests_state_in_state_not_equal, E_err_IDLE_req_X_N => E_err_IDLE_req_X_N, E_err_North_req_X_N => E_err_North_req_X_N, E_err_North_credit_not_zero_req_X_N_grant_N => E_err_North_credit_not_zero_req_X_N_grant_N, E_err_North_credit_zero_or_not_req_X_N_not_grant_N => E_err_North_credit_zero_or_not_req_X_N_not_grant_N, E_err_East_req_X_E => E_err_East_req_X_E, E_err_East_credit_not_zero_req_X_E_grant_E => E_err_East_credit_not_zero_req_X_E_grant_E, E_err_East_credit_zero_or_not_req_X_E_not_grant_E => E_err_East_credit_zero_or_not_req_X_E_not_grant_E, E_err_West_req_X_W => E_err_West_req_X_W, E_err_West_credit_not_zero_req_X_W_grant_W => E_err_West_credit_not_zero_req_X_W_grant_W, E_err_West_credit_zero_or_not_req_X_W_not_grant_W => E_err_West_credit_zero_or_not_req_X_W_not_grant_W, E_err_South_req_X_S => E_err_South_req_X_S, E_err_South_credit_not_zero_req_X_S_grant_S => E_err_South_credit_not_zero_req_X_S_grant_S, E_err_South_credit_zero_or_not_req_X_S_not_grant_S => E_err_South_credit_zero_or_not_req_X_S_not_grant_S, E_err_Local_req_X_L => E_err_Local_req_X_L, E_err_Local_credit_not_zero_req_X_L_grant_L => E_err_Local_credit_not_zero_req_X_L_grant_L, E_err_Local_credit_zero_or_not_req_X_L_not_grant_L => E_err_Local_credit_zero_or_not_req_X_L_not_grant_L, E_err_IDLE_req_X_E => E_err_IDLE_req_X_E, E_err_North_req_X_E => E_err_North_req_X_E, E_err_East_req_X_W => E_err_East_req_X_W, E_err_West_req_X_S => E_err_West_req_X_S, E_err_South_req_X_L => E_err_South_req_X_L, E_err_Local_req_X_N => E_err_Local_req_X_N, E_err_IDLE_req_X_W => E_err_IDLE_req_X_W, E_err_North_req_X_W => E_err_North_req_X_W, E_err_East_req_X_S => E_err_East_req_X_S, E_err_West_req_X_L => E_err_West_req_X_L, E_err_South_req_X_N => E_err_South_req_X_N, E_err_Local_req_X_E => E_err_Local_req_X_E, E_err_IDLE_req_X_S => E_err_IDLE_req_X_S, E_err_North_req_X_S => E_err_North_req_X_S, E_err_East_req_X_L => E_err_East_req_X_L, E_err_West_req_X_N => E_err_West_req_X_N, E_err_South_req_X_E => E_err_South_req_X_E, E_err_Local_req_X_W => E_err_Local_req_X_W, E_err_IDLE_req_X_L => E_err_IDLE_req_X_L, E_err_North_req_X_L => E_err_North_req_X_L, E_err_East_req_X_N => E_err_East_req_X_N, E_err_West_req_X_E => E_err_West_req_X_E, E_err_South_req_X_W => E_err_South_req_X_W, E_err_Local_req_X_S => E_err_Local_req_X_S, E_arbiter_out_err_state_in_onehot => E_arbiter_out_err_state_in_onehot, E_arbiter_out_err_no_request_grants => E_arbiter_out_err_no_request_grants, E_err_request_IDLE_state => E_err_request_IDLE_state, E_err_request_IDLE_not_Grants => E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant => E_err_state_North_Invalid_Grant, E_err_state_East_Invalid_Grant => E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant => E_err_state_West_Invalid_Grant, E_err_state_South_Invalid_Grant => E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant => E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero => E_err_Grants_onehot_or_all_zero, -- West Arbiter_out checker outputs W_arbiter_out_err_Requests_state_in_state_not_equal => W_arbiter_out_err_Requests_state_in_state_not_equal, W_err_IDLE_req_X_N => W_err_IDLE_req_X_N, W_err_North_req_X_N => W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N => W_err_North_credit_not_zero_req_X_N_grant_N, W_err_North_credit_zero_or_not_req_X_N_not_grant_N => W_err_North_credit_zero_or_not_req_X_N_not_grant_N, W_err_East_req_X_E => W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E => W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E => W_err_East_credit_zero_or_not_req_X_E_not_grant_E, W_err_West_req_X_W => W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W => W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W => W_err_West_credit_zero_or_not_req_X_W_not_grant_W, W_err_South_req_X_S => W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S => W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S => W_err_South_credit_zero_or_not_req_X_S_not_grant_S, W_err_Local_req_X_L => W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L => W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L => W_err_Local_credit_zero_or_not_req_X_L_not_grant_L, W_err_IDLE_req_X_E => W_err_IDLE_req_X_E, W_err_North_req_X_E => W_err_North_req_X_E, W_err_East_req_X_W => W_err_East_req_X_W, W_err_West_req_X_S => W_err_West_req_X_S, W_err_South_req_X_L => W_err_South_req_X_L, W_err_Local_req_X_N => W_err_Local_req_X_N, W_err_IDLE_req_X_W => W_err_IDLE_req_X_W, W_err_North_req_X_W => W_err_North_req_X_W, W_err_East_req_X_S => W_err_East_req_X_S, W_err_West_req_X_L => W_err_West_req_X_L, W_err_South_req_X_N => W_err_South_req_X_N, W_err_Local_req_X_E => W_err_Local_req_X_E, W_err_IDLE_req_X_S => W_err_IDLE_req_X_S, W_err_North_req_X_S => W_err_North_req_X_S, W_err_East_req_X_L => W_err_East_req_X_L, W_err_West_req_X_N => W_err_West_req_X_N, W_err_South_req_X_E => W_err_South_req_X_E, W_err_Local_req_X_W => W_err_Local_req_X_W, W_err_IDLE_req_X_L => W_err_IDLE_req_X_L, W_err_North_req_X_L => W_err_North_req_X_L, W_err_East_req_X_N => W_err_East_req_X_N, W_err_West_req_X_E => W_err_West_req_X_E, W_err_South_req_X_W => W_err_South_req_X_W, W_err_Local_req_X_S => W_err_Local_req_X_S, W_arbiter_out_err_state_in_onehot => W_arbiter_out_err_state_in_onehot, W_arbiter_out_err_no_request_grants => W_arbiter_out_err_no_request_grants, W_err_request_IDLE_state => W_err_request_IDLE_state, W_err_request_IDLE_not_Grants => W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant => W_err_state_North_Invalid_Grant, W_err_state_East_Invalid_Grant => W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant => W_err_state_West_Invalid_Grant, W_err_state_South_Invalid_Grant => W_err_state_South_Invalid_Grant, W_err_state_Local_Invalid_Grant => W_err_state_Local_Invalid_Grant, W_err_Grants_onehot_or_all_zero => W_err_Grants_onehot_or_all_zero, -- South Arbiter_out checker outputs S_arbiter_out_err_Requests_state_in_state_not_equal => S_arbiter_out_err_Requests_state_in_state_not_equal, S_err_IDLE_req_X_N => S_err_IDLE_req_X_N, S_err_North_req_X_N => S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N => S_err_North_credit_not_zero_req_X_N_grant_N, S_err_North_credit_zero_or_not_req_X_N_not_grant_N => S_err_North_credit_zero_or_not_req_X_N_not_grant_N, S_err_East_req_X_E => S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E => S_err_East_credit_not_zero_req_X_E_grant_E, S_err_East_credit_zero_or_not_req_X_E_not_grant_E => S_err_East_credit_zero_or_not_req_X_E_not_grant_E, S_err_West_req_X_W => S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W => S_err_West_credit_not_zero_req_X_W_grant_W, S_err_West_credit_zero_or_not_req_X_W_not_grant_W => S_err_West_credit_zero_or_not_req_X_W_not_grant_W, S_err_South_req_X_S => S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S => S_err_South_credit_not_zero_req_X_S_grant_S, S_err_South_credit_zero_or_not_req_X_S_not_grant_S => S_err_South_credit_zero_or_not_req_X_S_not_grant_S, S_err_Local_req_X_L => S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L => S_err_Local_credit_not_zero_req_X_L_grant_L, S_err_Local_credit_zero_or_not_req_X_L_not_grant_L => S_err_Local_credit_zero_or_not_req_X_L_not_grant_L, S_err_IDLE_req_X_E => S_err_IDLE_req_X_E, S_err_North_req_X_E => S_err_North_req_X_E, S_err_East_req_X_W => S_err_East_req_X_W, S_err_West_req_X_S => S_err_West_req_X_S, S_err_South_req_X_L => S_err_South_req_X_L, S_err_Local_req_X_N => S_err_Local_req_X_N, S_err_IDLE_req_X_W => S_err_IDLE_req_X_W, S_err_North_req_X_W => S_err_North_req_X_W, S_err_East_req_X_S => S_err_East_req_X_S, S_err_West_req_X_L => S_err_West_req_X_L, S_err_South_req_X_N => S_err_South_req_X_N, S_err_Local_req_X_E => S_err_Local_req_X_E, S_err_IDLE_req_X_S => S_err_IDLE_req_X_S, S_err_North_req_X_S => S_err_North_req_X_S, S_err_East_req_X_L => S_err_East_req_X_L, S_err_West_req_X_N => S_err_West_req_X_N, S_err_South_req_X_E => S_err_South_req_X_E, S_err_Local_req_X_W => S_err_Local_req_X_W, S_err_IDLE_req_X_L => S_err_IDLE_req_X_L, S_err_North_req_X_L => S_err_North_req_X_L, S_err_East_req_X_N => S_err_East_req_X_N, S_err_West_req_X_E => S_err_West_req_X_E, S_err_South_req_X_W => S_err_South_req_X_W, S_err_Local_req_X_S => S_err_Local_req_X_S, S_arbiter_out_err_state_in_onehot => S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants => S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state => S_err_request_IDLE_state, S_err_request_IDLE_not_Grants => S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant => S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant => S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant => S_err_state_West_Invalid_Grant, S_err_state_South_Invalid_Grant => S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant => S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero => S_err_Grants_onehot_or_all_zero, -- Local Arbiter_out checker outputs L_arbiter_out_err_Requests_state_in_state_not_equal => L_arbiter_out_err_Requests_state_in_state_not_equal, L_err_IDLE_req_X_N => L_err_IDLE_req_X_N, L_err_North_req_X_N => L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N => L_err_North_credit_not_zero_req_X_N_grant_N, L_err_North_credit_zero_or_not_req_X_N_not_grant_N => L_err_North_credit_zero_or_not_req_X_N_not_grant_N, L_err_East_req_X_E => L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E => L_err_East_credit_not_zero_req_X_E_grant_E, L_err_East_credit_zero_or_not_req_X_E_not_grant_E => L_err_East_credit_zero_or_not_req_X_E_not_grant_E, L_err_West_req_X_W => L_err_West_req_X_W, L_err_West_credit_not_zero_req_X_W_grant_W => L_err_West_credit_not_zero_req_X_W_grant_W, L_err_West_credit_zero_or_not_req_X_W_not_grant_W => L_err_West_credit_zero_or_not_req_X_W_not_grant_W, L_err_South_req_X_S => L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S => L_err_South_credit_not_zero_req_X_S_grant_S, L_err_South_credit_zero_or_not_req_X_S_not_grant_S => L_err_South_credit_zero_or_not_req_X_S_not_grant_S, L_err_Local_req_X_L => L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L => L_err_Local_credit_not_zero_req_X_L_grant_L, L_err_Local_credit_zero_or_not_req_X_L_not_grant_L => L_err_Local_credit_zero_or_not_req_X_L_not_grant_L, L_err_IDLE_req_X_E => L_err_IDLE_req_X_E, L_err_North_req_X_E => L_err_North_req_X_E, L_err_East_req_X_W => L_err_East_req_X_W, L_err_West_req_X_S => L_err_West_req_X_S, L_err_South_req_X_L => L_err_South_req_X_L, L_err_Local_req_X_N => L_err_Local_req_X_N, L_err_IDLE_req_X_W => L_err_IDLE_req_X_W, L_err_North_req_X_W => L_err_North_req_X_W, L_err_East_req_X_S => L_err_East_req_X_S, L_err_West_req_X_L => L_err_West_req_X_L, L_err_South_req_X_N => L_err_South_req_X_N, L_err_Local_req_X_E => L_err_Local_req_X_E, L_err_IDLE_req_X_S => L_err_IDLE_req_X_S, L_err_North_req_X_S => L_err_North_req_X_S, L_err_East_req_X_L => L_err_East_req_X_L, L_err_West_req_X_N => L_err_West_req_X_N, L_err_South_req_X_E => L_err_South_req_X_E, L_err_Local_req_X_W => L_err_Local_req_X_W, L_err_IDLE_req_X_L => L_err_IDLE_req_X_L, L_err_North_req_X_L => L_err_North_req_X_L, L_err_East_req_X_N => L_err_East_req_X_N, L_err_West_req_X_E => L_err_West_req_X_E, L_err_South_req_X_W => L_err_South_req_X_W, L_err_Local_req_X_S => L_err_Local_req_X_S, L_arbiter_out_err_state_in_onehot => L_arbiter_out_err_state_in_onehot, L_arbiter_out_err_no_request_grants => L_arbiter_out_err_no_request_grants, L_err_request_IDLE_state => L_err_request_IDLE_state, L_err_request_IDLE_not_Grants => L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant => L_err_state_North_Invalid_Grant, L_err_state_East_Invalid_Grant => L_err_state_East_Invalid_Grant, L_err_state_West_Invalid_Grant => L_err_state_West_Invalid_Grant, L_err_state_South_Invalid_Grant => L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant => L_err_state_Local_Invalid_Grant, L_err_Grants_onehot_or_all_zero => L_err_Grants_onehot_or_all_zero ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Xbar select_signals Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL; Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL; Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL; Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL; Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0'; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Xbars -- all the Xbars XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_N, Data_out=> TX_N); XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_E, Data_out=> TX_E); XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_W, Data_out=> TX_W); XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_S, Data_out=> TX_S); XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_L, Data_out=> TX_L); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ end;
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.std_logic_misc.all; use work.component_pack.all; entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping generic ( DATA_WIDTH: integer := 32; current_address : integer := 0; Rxy_rst : integer := 10; Cx_rst : integer := 10; healthy_counter_threshold : integer := 8; faulty_counter_threshold: integer := 2; counter_depth: integer := 4; NoC_size: integer := 4 ); port ( reset, clk: in std_logic; RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0); credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic; valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic; valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic; credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic; TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0); Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic; Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic; -- should be connected to NI (Outputs for classified fault information) link_faults: out std_logic_vector(4 downto 0); turn_faults: out std_logic_vector(19 downto 0); Rxy_reconf_PE: in std_logic_vector(7 downto 0); Cx_reconf_PE: in std_logic_vector(3 downto 0); Reconfig_command : in std_logic; -- fault injector shift register with serial input signals TCK: in std_logic; SE: in std_logic; -- shift enable UE: in std_logic; -- update enable SI: in std_logic; -- serial Input SO: out std_logic; -- serial output ---- Outputs for non-classified fault information link_faults_async: out std_logic_vector(4 downto 0); turn_faults_async: out std_logic_vector(19 downto 0) ); end router_credit_based_PD_C_SHMU; architecture behavior of router_credit_based_PD_C_SHMU is ------------------------------- -- Added because of Checkers -- ------------------------------- --signal combined_error_signals: std_logic_vector(19 downto 0); -- Shall we only consider this for the 20 bits showing the turn faults or individual checkers ?! --signal shift_parallel_data: std_logic_vector(19 downto 0); ------------------------------- ------------------------------- signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0); -- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic; signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic; signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic; signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic; signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic; signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic; signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic; signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic; signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic; signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic; signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic; signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0); signal LBDR_Fault_N, LBDR_Fault_E, LBDR_Fault_W, LBDR_Fault_S, LBDR_Fault_L: std_logic; signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic; signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic; signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic; -- Signals related to link fault classification modules signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic; signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic; signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic; -- Signals related to Control part checkers fault classification modules signal Healthy_N2E_turn_fault, intermittent_N2E_turn_fault, faulty_N2E_turn_fault: std_logic; signal Healthy_N2W_turn_fault, intermittent_N2W_turn_fault, faulty_N2W_turn_fault: std_logic; signal Healthy_E2N_turn_fault, intermittent_E2N_turn_fault, faulty_E2N_turn_fault: std_logic; signal Healthy_E2S_turn_fault, intermittent_E2S_turn_fault, faulty_E2S_turn_fault: std_logic; signal Healthy_W2N_turn_fault, intermittent_W2N_turn_fault, faulty_W2N_turn_fault: std_logic; signal Healthy_W2S_turn_fault, intermittent_W2S_turn_fault, faulty_W2S_turn_fault: std_logic; signal Healthy_S2E_turn_fault, intermittent_S2E_turn_fault, faulty_S2E_turn_fault: std_logic; signal Healthy_S2W_turn_fault, intermittent_S2W_turn_fault, faulty_S2W_turn_fault: std_logic; signal Healthy_N2S_path_fault, intermittent_N2S_path_fault, faulty_N2S_path_fault: std_logic; signal Healthy_S2N_path_fault, intermittent_S2N_path_fault, faulty_S2N_path_fault: std_logic; signal Healthy_E2W_path_fault, intermittent_E2W_path_fault, faulty_E2W_path_fault: std_logic; signal Healthy_W2E_path_fault, intermittent_W2E_path_fault, faulty_W2E_path_fault: std_logic; signal Healthy_L2N_fault, intermittent_L2N_fault, faulty_L2N_fault: std_logic; signal Healthy_L2E_fault, intermittent_L2E_fault, faulty_L2E_fault: std_logic; signal Healthy_L2W_fault, intermittent_L2W_fault, faulty_L2W_fault: std_logic; signal Healthy_L2S_fault, intermittent_L2S_fault, faulty_L2S_fault: std_logic; signal Healthy_N2L_fault, intermittent_N2L_fault, faulty_N2L_fault: std_logic; signal Healthy_E2L_fault, intermittent_E2L_fault, faulty_E2L_fault: std_logic; signal Healthy_W2L_fault, intermittent_W2L_fault, faulty_W2L_fault: std_logic; signal Healthy_S2L_fault, intermittent_S2L_fault, faulty_S2L_fault: std_logic; -- Signals needed for control part checkers -- Signals needed for LBDR packet drop checkers -- North signal N_err_header_empty_Requests_FF_Requests_in, N_err_tail_Requests_in_all_zero, N_err_tail_empty_Requests_FF_Requests_in, N_err_tail_not_empty_not_grants_Requests_FF_Requests_in, N_err_grants_onehot, N_err_grants_mismatch, N_err_header_tail_Requests_FF_Requests_in, N_err_dst_addr_cur_addr_N1, N_err_dst_addr_cur_addr_not_N1, N_err_dst_addr_cur_addr_E1, N_err_dst_addr_cur_addr_not_E1, N_err_dst_addr_cur_addr_W1, N_err_dst_addr_cur_addr_not_W1, N_err_dst_addr_cur_addr_S1, N_err_dst_addr_cur_addr_not_S1, N_err_dst_addr_cur_addr_Req_L_in, N_err_dst_addr_cur_addr_not_Req_L_in, N_err_header_not_empty_faulty_drop_packet_in, -- added according to new design N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design N_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --N_err_header_not_empty_Req_L_in, -- added according to new design N_err_header_not_empty_Req_N_in, N_err_header_not_empty_Req_E_in, N_err_header_not_empty_Req_W_in, N_err_header_not_empty_Req_S_in, N_err_header_empty_packet_drop_in_packet_drop_equal, N_err_tail_not_empty_packet_drop_not_packet_drop_in, N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, N_err_packet_drop_order, N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- East E_err_header_empty_Requests_FF_Requests_in, E_err_tail_Requests_in_all_zero, E_err_tail_empty_Requests_FF_Requests_in, E_err_tail_not_empty_not_grants_Requests_FF_Requests_in, E_err_grants_onehot, E_err_grants_mismatch, E_err_header_tail_Requests_FF_Requests_in, E_err_dst_addr_cur_addr_N1, E_err_dst_addr_cur_addr_not_N1, E_err_dst_addr_cur_addr_E1, E_err_dst_addr_cur_addr_not_E1, E_err_dst_addr_cur_addr_W1, E_err_dst_addr_cur_addr_not_W1, E_err_dst_addr_cur_addr_S1, E_err_dst_addr_cur_addr_not_S1, E_err_dst_addr_cur_addr_Req_L_in, E_err_dst_addr_cur_addr_not_Req_L_in, E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --E_err_header_not_empty_Req_L_in, -- added according to new design E_err_header_not_empty_Req_N_in, E_err_header_not_empty_Req_E_in, E_err_header_not_empty_Req_W_in, E_err_header_not_empty_Req_S_in, E_err_header_empty_packet_drop_in_packet_drop_equal, E_err_tail_not_empty_packet_drop_not_packet_drop_in, E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, E_err_packet_drop_order, E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- West W_err_header_empty_Requests_FF_Requests_in, W_err_tail_Requests_in_all_zero, W_err_tail_empty_Requests_FF_Requests_in, W_err_tail_not_empty_not_grants_Requests_FF_Requests_in, W_err_grants_onehot, W_err_grants_mismatch, W_err_header_tail_Requests_FF_Requests_in, W_err_dst_addr_cur_addr_N1, W_err_dst_addr_cur_addr_not_N1, W_err_dst_addr_cur_addr_E1, W_err_dst_addr_cur_addr_not_E1, W_err_dst_addr_cur_addr_W1, W_err_dst_addr_cur_addr_not_W1, W_err_dst_addr_cur_addr_S1, W_err_dst_addr_cur_addr_not_S1, W_err_dst_addr_cur_addr_Req_L_in, W_err_dst_addr_cur_addr_not_Req_L_in, W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --W_err_header_not_empty_Req_L_in, -- added according to new design W_err_header_not_empty_Req_N_in, W_err_header_not_empty_Req_E_in, W_err_header_not_empty_Req_W_in, W_err_header_not_empty_Req_S_in, W_err_header_empty_packet_drop_in_packet_drop_equal, W_err_tail_not_empty_packet_drop_not_packet_drop_in, W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, W_err_packet_drop_order, W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- South S_err_header_empty_Requests_FF_Requests_in, S_err_tail_Requests_in_all_zero, S_err_tail_empty_Requests_FF_Requests_in, S_err_tail_not_empty_not_grants_Requests_FF_Requests_in, S_err_grants_onehot, S_err_grants_mismatch, S_err_header_tail_Requests_FF_Requests_in, S_err_dst_addr_cur_addr_N1, S_err_dst_addr_cur_addr_not_N1, S_err_dst_addr_cur_addr_E1, S_err_dst_addr_cur_addr_not_E1, S_err_dst_addr_cur_addr_W1, S_err_dst_addr_cur_addr_not_W1, S_err_dst_addr_cur_addr_S1, S_err_dst_addr_cur_addr_not_S1, S_err_dst_addr_cur_addr_Req_L_in, S_err_dst_addr_cur_addr_not_Req_L_in, S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --S_err_header_not_empty_Req_L_in, -- added according to new design S_err_header_not_empty_Req_N_in, S_err_header_not_empty_Req_E_in, S_err_header_not_empty_Req_W_in, S_err_header_not_empty_Req_S_in, S_err_header_empty_packet_drop_in_packet_drop_equal, S_err_tail_not_empty_packet_drop_not_packet_drop_in, S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, S_err_packet_drop_order, S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- Local L_err_header_empty_Requests_FF_Requests_in, L_err_tail_Requests_in_all_zero, L_err_tail_empty_Requests_FF_Requests_in, L_err_tail_not_empty_not_grants_Requests_FF_Requests_in, L_err_grants_onehot, L_err_grants_mismatch, L_err_header_tail_Requests_FF_Requests_in, L_err_dst_addr_cur_addr_N1, L_err_dst_addr_cur_addr_not_N1, L_err_dst_addr_cur_addr_E1, L_err_dst_addr_cur_addr_not_E1, L_err_dst_addr_cur_addr_W1, L_err_dst_addr_cur_addr_not_W1, L_err_dst_addr_cur_addr_S1, L_err_dst_addr_cur_addr_not_S1, L_err_dst_addr_cur_addr_Req_L_in, L_err_dst_addr_cur_addr_not_Req_L_in, L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --L_err_header_not_empty_Req_L_in, -- added according to new design L_err_header_not_empty_Req_N_in, L_err_header_not_empty_Req_E_in, L_err_header_not_empty_Req_W_in, L_err_header_not_empty_Req_S_in, L_err_header_empty_packet_drop_in_packet_drop_equal, L_err_tail_not_empty_packet_drop_not_packet_drop_in, L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, L_err_packet_drop_order, L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal: std_logic; ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ -- Signals needed for FIFO packet drop with fault classifier support checkers -- North -- Functional checkers signal N_err_empty_full, N_err_empty_read_en, N_err_full_write_en, N_err_state_in_onehot, N_err_read_pointer_in_onehot, N_err_write_pointer_in_onehot, -- Structural checkers N_err_write_en_write_pointer, N_err_not_write_en_write_pointer, N_err_read_pointer_write_pointer_not_empty, N_err_read_pointer_write_pointer_empty, N_err_read_pointer_write_pointer_not_full, N_err_read_pointer_write_pointer_full, N_err_read_pointer_increment, N_err_read_pointer_not_increment, N_err_write_en, N_err_not_write_en, N_err_not_write_en1, N_err_not_write_en2, N_err_read_en_mismatch, N_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! N_err_fake_credit_read_en_fake_credit_counter_in_increment, N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, N_err_fake_credit_read_en_credit_out, N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, N_err_state_out_Idle_not_fault_out_not_fake_credit, N_err_state_out_Idle_not_fault_out_not_fault_info_in, N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, N_err_state_out_Idle_fault_out_fake_credit, N_err_state_out_Idle_fault_out_state_in_Packet_drop, N_err_state_out_Idle_fault_out_fault_info_in, N_err_state_out_Idle_fault_out_faulty_packet_in, N_err_state_out_Idle_not_health_info, N_err_state_out_Idle_not_write_fake_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Header_flit_not_valid_in_not_fault_info_in, N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, N_err_state_out_Header_flit_or_Body_flit_not_fake_credit, N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, N_err_state_out_Body_flit_valid_in_not_fault_out_health_info, N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Body_flit_not_valid_in_not_fault_info_in, N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, N_err_state_out_Body_flit_valid_in_fault_out_not_health_info, N_err_state_out_Body_flit_valid_in_not_health_info, N_err_state_out_Body_flit_not_fake_credit, N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, N_err_state_out_Tail_flit_not_valid_in_state_in_Idle, N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, N_err_state_out_Tail_flit_not_valid_in_not_fake_credit, N_err_state_out_Tail_flit_not_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, N_err_fault_info_fault_info_out_equal, N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- East -- Functional checkers E_err_empty_full, E_err_empty_read_en, E_err_full_write_en, E_err_state_in_onehot, E_err_read_pointer_in_onehot, E_err_write_pointer_in_onehot, -- Structural checkers E_err_write_en_write_pointer, E_err_not_write_en_write_pointer, E_err_read_pointer_write_pointer_not_empty, E_err_read_pointer_write_pointer_empty, E_err_read_pointer_write_pointer_not_full, E_err_read_pointer_write_pointer_full, E_err_read_pointer_increment, E_err_read_pointer_not_increment, E_err_write_en, E_err_not_write_en, E_err_not_write_en1, E_err_not_write_en2, E_err_read_en_mismatch, E_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! E_err_fake_credit_read_en_fake_credit_counter_in_increment, E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, E_err_fake_credit_read_en_credit_out, E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, E_err_state_out_Idle_not_fault_out_not_fake_credit, E_err_state_out_Idle_not_fault_out_not_fault_info_in, E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, E_err_state_out_Idle_fault_out_fake_credit, E_err_state_out_Idle_fault_out_state_in_Packet_drop, E_err_state_out_Idle_fault_out_fault_info_in, E_err_state_out_Idle_fault_out_faulty_packet_in, E_err_state_out_Idle_not_health_info, E_err_state_out_Idle_not_write_fake_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Header_flit_not_valid_in_not_fault_info_in, E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, E_err_state_out_Header_flit_or_Body_flit_not_fake_credit, E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, E_err_state_out_Body_flit_valid_in_not_fault_out_health_info, E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Body_flit_not_valid_in_not_fault_info_in, E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, E_err_state_out_Body_flit_valid_in_fault_out_not_health_info, E_err_state_out_Body_flit_valid_in_not_health_info, E_err_state_out_Body_flit_not_fake_credit, E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, E_err_state_out_Tail_flit_not_valid_in_state_in_Idle, E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, E_err_state_out_Tail_flit_not_valid_in_not_fake_credit, E_err_state_out_Tail_flit_not_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, E_err_fault_info_fault_info_out_equal, E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- West -- Functional checkers W_err_empty_full, W_err_empty_read_en, W_err_full_write_en, W_err_state_in_onehot, W_err_read_pointer_in_onehot, W_err_write_pointer_in_onehot, -- Structural checkers W_err_write_en_write_pointer, W_err_not_write_en_write_pointer, W_err_read_pointer_write_pointer_not_empty, W_err_read_pointer_write_pointer_empty, W_err_read_pointer_write_pointer_not_full, W_err_read_pointer_write_pointer_full, W_err_read_pointer_increment, W_err_read_pointer_not_increment, W_err_write_en, W_err_not_write_en, W_err_not_write_en1, W_err_not_write_en2, W_err_read_en_mismatch, W_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! W_err_fake_credit_read_en_fake_credit_counter_in_increment, W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, W_err_fake_credit_read_en_credit_out, W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, W_err_state_out_Idle_not_fault_out_not_fake_credit, W_err_state_out_Idle_not_fault_out_not_fault_info_in, W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, W_err_state_out_Idle_fault_out_fake_credit, W_err_state_out_Idle_fault_out_state_in_Packet_drop, W_err_state_out_Idle_fault_out_fault_info_in, W_err_state_out_Idle_fault_out_faulty_packet_in, W_err_state_out_Idle_not_health_info, W_err_state_out_Idle_not_write_fake_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Header_flit_not_valid_in_not_fault_info_in, W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, W_err_state_out_Header_flit_or_Body_flit_not_fake_credit, W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, W_err_state_out_Body_flit_valid_in_not_fault_out_health_info, W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Body_flit_not_valid_in_not_fault_info_in, W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, W_err_state_out_Body_flit_valid_in_fault_out_not_health_info, W_err_state_out_Body_flit_valid_in_not_health_info, W_err_state_out_Body_flit_not_fake_credit, W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, W_err_state_out_Tail_flit_not_valid_in_state_in_Idle, W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, W_err_state_out_Tail_flit_not_valid_in_not_fake_credit, W_err_state_out_Tail_flit_not_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, W_err_fault_info_fault_info_out_equal, W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- South -- Functional checkers S_err_empty_full, S_err_empty_read_en, S_err_full_write_en, S_err_state_in_onehot, S_err_read_pointer_in_onehot, S_err_write_pointer_in_onehot, -- Structural checkers S_err_write_en_write_pointer, S_err_not_write_en_write_pointer, S_err_read_pointer_write_pointer_not_empty, S_err_read_pointer_write_pointer_empty, S_err_read_pointer_write_pointer_not_full, S_err_read_pointer_write_pointer_full, S_err_read_pointer_increment, S_err_read_pointer_not_increment, S_err_write_en, S_err_not_write_en, S_err_not_write_en1, S_err_not_write_en2, S_err_read_en_mismatch, S_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! S_err_fake_credit_read_en_fake_credit_counter_in_increment, S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, S_err_fake_credit_read_en_credit_out, S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, S_err_state_out_Idle_not_fault_out_not_fake_credit, S_err_state_out_Idle_not_fault_out_not_fault_info_in, S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, S_err_state_out_Idle_fault_out_fake_credit, S_err_state_out_Idle_fault_out_state_in_Packet_drop, S_err_state_out_Idle_fault_out_fault_info_in, S_err_state_out_Idle_fault_out_faulty_packet_in, S_err_state_out_Idle_not_health_info, S_err_state_out_Idle_not_write_fake_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Header_flit_not_valid_in_not_fault_info_in, S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, S_err_state_out_Header_flit_or_Body_flit_not_fake_credit, S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, S_err_state_out_Body_flit_valid_in_not_fault_out_health_info, S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Body_flit_not_valid_in_not_fault_info_in, S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, S_err_state_out_Body_flit_valid_in_fault_out_not_health_info, S_err_state_out_Body_flit_valid_in_not_health_info, S_err_state_out_Body_flit_not_fake_credit, S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, S_err_state_out_Tail_flit_not_valid_in_state_in_Idle, S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, S_err_state_out_Tail_flit_not_valid_in_not_fake_credit, S_err_state_out_Tail_flit_not_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, S_err_fault_info_fault_info_out_equal, S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- Local -- Functional checkers L_err_empty_full, L_err_empty_read_en, L_err_full_write_en, L_err_state_in_onehot, L_err_read_pointer_in_onehot, L_err_write_pointer_in_onehot, -- Structural checkers L_err_write_en_write_pointer, L_err_not_write_en_write_pointer, L_err_read_pointer_write_pointer_not_empty, L_err_read_pointer_write_pointer_empty, L_err_read_pointer_write_pointer_not_full, L_err_read_pointer_write_pointer_full, L_err_read_pointer_increment, L_err_read_pointer_not_increment, L_err_write_en, L_err_not_write_en, L_err_not_write_en1, L_err_not_write_en2, L_err_read_en_mismatch, L_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! L_err_fake_credit_read_en_fake_credit_counter_in_increment, L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, L_err_fake_credit_read_en_credit_out, L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, L_err_state_out_Idle_not_fault_out_not_fake_credit, L_err_state_out_Idle_not_fault_out_not_fault_info_in, L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, L_err_state_out_Idle_fault_out_fake_credit, L_err_state_out_Idle_fault_out_state_in_Packet_drop, L_err_state_out_Idle_fault_out_fault_info_in, L_err_state_out_Idle_fault_out_faulty_packet_in, L_err_state_out_Idle_not_health_info, L_err_state_out_Idle_not_write_fake_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Header_flit_not_valid_in_not_fault_info_in, L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, L_err_state_out_Header_flit_or_Body_flit_not_fake_credit, L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, L_err_state_out_Body_flit_valid_in_not_fault_out_health_info, L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Body_flit_not_valid_in_not_fault_info_in, L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, L_err_state_out_Body_flit_valid_in_fault_out_not_health_info, L_err_state_out_Body_flit_valid_in_not_health_info, L_err_state_out_Body_flit_not_fake_credit, L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, L_err_state_out_Tail_flit_not_valid_in_state_in_Idle, L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, L_err_state_out_Tail_flit_not_valid_in_not_fake_credit, L_err_state_out_Tail_flit_not_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, L_err_fault_info_fault_info_out_equal, L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in: std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Signals needed for Allocator unit -- Allocator logic checker outputs -- Might need to be changed ?! signal err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N, err_grant_N_E_sig_not_empty_E_grant_N_E, err_not_grant_N_E_sig_or_empty_E_not_grant_N_E, err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W, err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S, err_grant_N_L_sig_not_empty_L_grant_N_L, err_not_grant_N_L_sig_or_empty_L_not_grant_N_L, err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N, err_grant_E_E_sig_not_empty_E_grant_E_E, err_not_grant_E_E_sig_or_empty_E_not_grant_E_E, err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W, err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S, err_grant_E_L_sig_not_empty_L_grant_E_L, err_not_grant_E_L_sig_or_empty_L_not_grant_E_L, err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N, err_grant_W_E_sig_not_empty_E_grant_W_E, err_not_grant_W_E_sig_or_empty_E_not_grant_W_E, err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W, err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S, err_grant_W_L_sig_not_empty_L_grant_W_L, err_not_grant_W_L_sig_or_empty_L_not_grant_W_L, err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N, err_grant_S_E_sig_not_empty_E_grant_S_E, err_not_grant_S_E_sig_or_empty_E_not_grant_S_E, err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W, err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S, err_grant_S_L_sig_not_empty_L_grant_S_L, err_not_grant_S_L_sig_or_empty_L_not_grant_S_L, err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N, err_grant_L_E_sig_not_empty_E_grant_L_E, err_not_grant_L_E_sig_or_empty_E_not_grant_L_E, err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W, err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S, err_grant_L_L_sig_not_empty_L_grant_L_L, err_not_grant_L_L_sig_or_empty_L_not_grant_L_L, err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N, err_grant_signals_not_empty_grant_E, err_not_grant_signals_empty_not_grant_E, err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W, err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S, err_grant_signals_not_empty_grant_L, err_not_grant_signals_empty_not_grant_L, err_grants_valid_not_match: std_logic; -- Allocator credit_counter logic checker outputs signal err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment, err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement, err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change, err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment, err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement, err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change, err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment, err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement, err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change, err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment, err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement, err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change, err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment, err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement, err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change, err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Arbiter_in Checker signals (part of allocator unit) -- North Arbiter_in checker outputs signal N_err_Requests_state_in_state_not_equal, N_err_IDLE_Req_N, N_err_IDLE_grant_N,N_err_North_Req_N, N_err_North_grant_N, N_err_East_Req_E, N_err_East_grant_E, N_err_West_Req_W, N_err_West_grant_W, N_err_South_Req_S,N_err_South_grant_S,N_err_Local_Req_L, N_err_Local_grant_L, N_err_IDLE_Req_E, N_err_IDLE_grant_E, N_err_North_Req_E, N_err_North_grant_E, N_err_East_Req_W, N_err_East_grant_W, N_err_West_Req_S, N_err_West_grant_S, N_err_South_Req_L, N_err_South_grant_L, N_err_Local_Req_N, N_err_Local_grant_N, N_err_IDLE_Req_W, N_err_IDLE_grant_W, N_err_North_Req_W, N_err_North_grant_W, N_err_East_Req_S, N_err_East_grant_S, N_err_West_Req_L, N_err_West_grant_L, N_err_South_Req_N, N_err_South_grant_N, N_err_Local_Req_E, N_err_Local_grant_E, N_err_IDLE_Req_S, N_err_IDLE_grant_S, N_err_North_Req_S, N_err_North_grant_S, N_err_East_Req_L, N_err_East_grant_L, N_err_West_Req_N, N_err_West_grant_N, N_err_South_Req_E, N_err_South_grant_E, N_err_Local_Req_W, N_err_Local_grant_W, N_err_IDLE_Req_L, N_err_IDLE_grant_L, N_err_North_Req_L, N_err_North_grant_L, N_err_East_Req_N, N_err_East_grant_N, N_err_West_Req_E, N_err_West_grant_E, N_err_South_Req_W, N_err_South_grant_W, N_err_Local_Req_S, N_err_Local_grant_S, N_err_arbiter_state_in_onehot, N_err_no_request_grants, N_err_request_no_grants, N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L, -- East Arbiter_in checker outputs E_err_Requests_state_in_state_not_equal, E_err_IDLE_Req_N, E_err_IDLE_grant_N, E_err_North_Req_N, E_err_North_grant_N, E_err_East_Req_E, E_err_East_grant_E, E_err_West_Req_W, E_err_West_grant_W, E_err_South_Req_S, E_err_South_grant_S, E_err_Local_Req_L, E_err_Local_grant_L, E_err_IDLE_Req_E, E_err_IDLE_grant_E, E_err_North_Req_E, E_err_North_grant_E, E_err_East_Req_W, E_err_East_grant_W, E_err_West_Req_S, E_err_West_grant_S, E_err_South_Req_L, E_err_South_grant_L, E_err_Local_Req_N, E_err_Local_grant_N, E_err_IDLE_Req_W, E_err_IDLE_grant_W, E_err_North_Req_W, E_err_North_grant_W, E_err_East_Req_S, E_err_East_grant_S, E_err_West_Req_L, E_err_West_grant_L, E_err_South_Req_N, E_err_South_grant_N, E_err_Local_Req_E, E_err_Local_grant_E, E_err_IDLE_Req_S, E_err_IDLE_grant_S, E_err_North_Req_S, E_err_North_grant_S, E_err_East_Req_L, E_err_East_grant_L, E_err_West_Req_N, E_err_West_grant_N, E_err_South_Req_E, E_err_South_grant_E, E_err_Local_Req_W, E_err_Local_grant_W, E_err_IDLE_Req_L, E_err_IDLE_grant_L, E_err_North_Req_L, E_err_North_grant_L, E_err_East_Req_N, E_err_East_grant_N, E_err_West_Req_E, E_err_West_grant_E, E_err_South_Req_W, E_err_South_grant_W, E_err_Local_Req_S, E_err_Local_grant_S, E_err_arbiter_state_in_onehot, E_err_no_request_grants, E_err_request_no_grants, E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L, -- West Arbiter_in checker outputs W_err_Requests_state_in_state_not_equal, W_err_IDLE_Req_N, W_err_IDLE_grant_N, W_err_North_Req_N, W_err_North_grant_N, W_err_East_Req_E, W_err_East_grant_E, W_err_West_Req_W, W_err_West_grant_W, W_err_South_Req_S, W_err_South_grant_S, W_err_Local_Req_L, W_err_Local_grant_L, W_err_IDLE_Req_E, W_err_IDLE_grant_E, W_err_North_Req_E, W_err_North_grant_E, W_err_East_Req_W, W_err_East_grant_W, W_err_West_Req_S, W_err_West_grant_S, W_err_South_Req_L, W_err_South_grant_L, W_err_Local_Req_N, W_err_Local_grant_N, W_err_IDLE_Req_W, W_err_IDLE_grant_W, W_err_North_Req_W, W_err_North_grant_W, W_err_East_Req_S, W_err_East_grant_S, W_err_West_Req_L, W_err_West_grant_L, W_err_South_Req_N, W_err_South_grant_N, W_err_Local_Req_E, W_err_Local_grant_E, W_err_IDLE_Req_S, W_err_IDLE_grant_S, W_err_North_Req_S, W_err_North_grant_S, W_err_East_Req_L, W_err_East_grant_L, W_err_West_Req_N, W_err_West_grant_N, W_err_South_Req_E, W_err_South_grant_E, W_err_Local_Req_W, W_err_Local_grant_W, W_err_IDLE_Req_L, W_err_IDLE_grant_L, W_err_North_Req_L, W_err_North_grant_L, W_err_East_Req_N, W_err_East_grant_N, W_err_West_Req_E, W_err_West_grant_E, W_err_South_Req_W, W_err_South_grant_W, W_err_Local_Req_S, W_err_Local_grant_S, W_err_arbiter_state_in_onehot, W_err_no_request_grants, W_err_request_no_grants, W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L, -- South Arbiter_in checker outputs S_err_Requests_state_in_state_not_equal, S_err_IDLE_Req_N, S_err_IDLE_grant_N,S_err_North_Req_N, S_err_North_grant_N, S_err_East_Req_E, S_err_East_grant_E, S_err_West_Req_W, S_err_West_grant_W, S_err_South_Req_S,S_err_South_grant_S,S_err_Local_Req_L, S_err_Local_grant_L, S_err_IDLE_Req_E, S_err_IDLE_grant_E, S_err_North_Req_E, S_err_North_grant_E, S_err_East_Req_W, S_err_East_grant_W, S_err_West_Req_S, S_err_West_grant_S, S_err_South_Req_L, S_err_South_grant_L, S_err_Local_Req_N, S_err_Local_grant_N, S_err_IDLE_Req_W, S_err_IDLE_grant_W, S_err_North_Req_W, S_err_North_grant_W, S_err_East_Req_S, S_err_East_grant_S, S_err_West_Req_L, S_err_West_grant_L, S_err_South_Req_N, S_err_South_grant_N, S_err_Local_Req_E, S_err_Local_grant_E, S_err_IDLE_Req_S, S_err_IDLE_grant_S, S_err_North_Req_S, S_err_North_grant_S, S_err_East_Req_L, S_err_East_grant_L, S_err_West_Req_N, S_err_West_grant_N, S_err_South_Req_E, S_err_South_grant_E, S_err_Local_Req_W, S_err_Local_grant_W, S_err_IDLE_Req_L, S_err_IDLE_grant_L, S_err_North_Req_L, S_err_North_grant_L, S_err_East_Req_N, S_err_East_grant_N, S_err_West_Req_E, S_err_West_grant_E, S_err_South_Req_W, S_err_South_grant_W, S_err_Local_Req_S, S_err_Local_grant_S, S_err_arbiter_state_in_onehot, S_err_no_request_grants, S_err_request_no_grants, S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L, -- Local Arbiter_in checker outputs L_err_Requests_state_in_state_not_equal, L_err_IDLE_Req_N, L_err_IDLE_grant_N,L_err_North_Req_N, L_err_North_grant_N, L_err_East_Req_E, L_err_East_grant_E, L_err_West_Req_W, L_err_West_grant_W, L_err_South_Req_S,L_err_South_grant_S, L_err_Local_Req_L, L_err_Local_grant_L, L_err_IDLE_Req_E, L_err_IDLE_grant_E, L_err_North_Req_E, L_err_North_grant_E, L_err_East_Req_W, L_err_East_grant_W, L_err_West_Req_S, L_err_West_grant_S, L_err_South_Req_L, L_err_South_grant_L, L_err_Local_Req_N, L_err_Local_grant_N, L_err_IDLE_Req_W, L_err_IDLE_grant_W, L_err_North_Req_W, L_err_North_grant_W, L_err_East_Req_S, L_err_East_grant_S, L_err_West_Req_L, L_err_West_grant_L, L_err_South_Req_N, L_err_South_grant_N, L_err_Local_Req_E, L_err_Local_grant_E, L_err_IDLE_Req_S, L_err_IDLE_grant_S, L_err_North_Req_S, L_err_North_grant_S, L_err_East_Req_L, L_err_East_grant_L, L_err_West_Req_N, L_err_West_grant_N, L_err_South_Req_E, L_err_South_grant_E, L_err_Local_Req_W, L_err_Local_grant_W, L_err_IDLE_Req_L, L_err_IDLE_grant_L, L_err_North_Req_L, L_err_North_grant_L, L_err_East_Req_N, L_err_East_grant_N, L_err_West_Req_E, L_err_West_grant_E, L_err_South_Req_W, L_err_South_grant_W, L_err_Local_Req_S, L_err_Local_grant_S, L_err_arbiter_state_in_onehot, L_err_no_request_grants, L_err_request_no_grants, L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S, L_err_no_Req_L_grant_L : std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Arbiter_out Checker signals (part of allocator unit) -- North Arbiter_out checker outputs signal N_arbiter_out_err_Requests_state_in_state_not_equal, N_err_IDLE_req_X_N, N_err_North_req_X_N, N_err_North_credit_not_zero_req_X_N_grant_N, N_err_North_credit_zero_or_not_req_X_N_not_grant_N, N_err_East_req_X_E, N_err_East_credit_not_zero_req_X_E_grant_E, N_err_East_credit_zero_or_not_req_X_E_not_grant_E, N_err_West_req_X_W, N_err_West_credit_not_zero_req_X_W_grant_W, N_err_West_credit_zero_or_not_req_X_W_not_grant_W, N_err_South_req_X_S, N_err_South_credit_not_zero_req_X_S_grant_S, N_err_South_credit_zero_or_not_req_X_S_not_grant_S, N_err_Local_req_X_L, N_err_Local_credit_not_zero_req_X_L_grant_L, N_err_Local_credit_zero_or_not_req_X_L_not_grant_L, N_err_IDLE_req_X_E, N_err_North_req_X_E, N_err_East_req_X_W, N_err_West_req_X_S, N_err_South_req_X_L, N_err_Local_req_X_N, N_err_IDLE_req_X_W, N_err_North_req_X_W, N_err_East_req_X_S, N_err_West_req_X_L, N_err_South_req_X_N, N_err_Local_req_X_E, N_err_IDLE_req_X_S, N_err_North_req_X_S, N_err_East_req_X_L, N_err_West_req_X_N, N_err_South_req_X_E, N_err_Local_req_X_W, N_err_IDLE_req_X_L, N_err_North_req_X_L, N_err_East_req_X_N, N_err_West_req_X_E, N_err_South_req_X_W, N_err_Local_req_X_S, N_arbiter_out_err_state_in_onehot, N_arbiter_out_err_no_request_grants, N_err_request_IDLE_state, N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant, N_err_state_West_Invalid_Grant, N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant, N_err_Grants_onehot_or_all_zero, -- East Arbiter_out checker outputs E_arbiter_out_err_Requests_state_in_state_not_equal, E_err_IDLE_req_X_N, E_err_North_req_X_N, E_err_North_credit_not_zero_req_X_N_grant_N, E_err_North_credit_zero_or_not_req_X_N_not_grant_N, E_err_East_req_X_E, E_err_East_credit_not_zero_req_X_E_grant_E, E_err_East_credit_zero_or_not_req_X_E_not_grant_E, E_err_West_req_X_W, E_err_West_credit_not_zero_req_X_W_grant_W, E_err_West_credit_zero_or_not_req_X_W_not_grant_W, E_err_South_req_X_S, E_err_South_credit_not_zero_req_X_S_grant_S, E_err_South_credit_zero_or_not_req_X_S_not_grant_S, E_err_Local_req_X_L, E_err_Local_credit_not_zero_req_X_L_grant_L, E_err_Local_credit_zero_or_not_req_X_L_not_grant_L, E_err_IDLE_req_X_E, E_err_North_req_X_E, E_err_East_req_X_W, E_err_West_req_X_S, E_err_South_req_X_L, E_err_Local_req_X_N, E_err_IDLE_req_X_W, E_err_North_req_X_W, E_err_East_req_X_S, E_err_West_req_X_L, E_err_South_req_X_N, E_err_Local_req_X_E, E_err_IDLE_req_X_S, E_err_North_req_X_S, E_err_East_req_X_L, E_err_West_req_X_N, E_err_South_req_X_E, E_err_Local_req_X_W, E_err_IDLE_req_X_L, E_err_North_req_X_L, E_err_East_req_X_N, E_err_West_req_X_E, E_err_South_req_X_W, E_err_Local_req_X_S, E_arbiter_out_err_state_in_onehot, E_arbiter_out_err_no_request_grants, E_err_request_IDLE_state, E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant, E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant, E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero, -- West Arbiter_out checker outputs W_arbiter_out_err_Requests_state_in_state_not_equal, W_err_IDLE_req_X_N, W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N, W_err_North_credit_zero_or_not_req_X_N_not_grant_N, W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E, W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W, W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S, W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L, W_err_IDLE_req_X_E, W_err_North_req_X_E, W_err_East_req_X_W, W_err_West_req_X_S, W_err_South_req_X_L, W_err_Local_req_X_N, W_err_IDLE_req_X_W, W_err_North_req_X_W, W_err_East_req_X_S, W_err_West_req_X_L, W_err_South_req_X_N, W_err_Local_req_X_E, W_err_IDLE_req_X_S, W_err_North_req_X_S, W_err_East_req_X_L, W_err_West_req_X_N, W_err_South_req_X_E, W_err_Local_req_X_W, W_err_IDLE_req_X_L, W_err_North_req_X_L, W_err_East_req_X_N, W_err_West_req_X_E, W_err_South_req_X_W, W_err_Local_req_X_S, W_arbiter_out_err_state_in_onehot, W_arbiter_out_err_no_request_grants, W_err_request_IDLE_state, W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant,W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant, W_err_state_South_Invalid_Grant,W_err_state_Local_Invalid_Grant, W_err_Grants_onehot_or_all_zero, -- South Arbiter_out checker outputs S_arbiter_out_err_Requests_state_in_state_not_equal, S_err_IDLE_req_X_N, S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N, S_err_North_credit_zero_or_not_req_X_N_not_grant_N, S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E, S_err_East_credit_zero_or_not_req_X_E_not_grant_E, S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W, S_err_West_credit_zero_or_not_req_X_W_not_grant_W, S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S, S_err_South_credit_zero_or_not_req_X_S_not_grant_S, S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L, S_err_Local_credit_zero_or_not_req_X_L_not_grant_L, S_err_IDLE_req_X_E, S_err_North_req_X_E, S_err_East_req_X_W, S_err_West_req_X_S, S_err_South_req_X_L, S_err_Local_req_X_N, S_err_IDLE_req_X_W, S_err_North_req_X_W, S_err_East_req_X_S, S_err_West_req_X_L, S_err_South_req_X_N, S_err_Local_req_X_E, S_err_IDLE_req_X_S, S_err_North_req_X_S, S_err_East_req_X_L, S_err_West_req_X_N, S_err_South_req_X_E, S_err_Local_req_X_W, S_err_IDLE_req_X_L, S_err_North_req_X_L, S_err_East_req_X_N, S_err_West_req_X_E, S_err_South_req_X_W, S_err_Local_req_X_S, S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state, S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant, S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero, -- Local Arbiter_out checker outputs L_arbiter_out_err_Requests_state_in_state_not_equal, L_err_IDLE_req_X_N, L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N, L_err_North_credit_zero_or_not_req_X_N_not_grant_N, L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E, L_err_East_credit_zero_or_not_req_X_E_not_grant_E, L_err_West_req_X_W, L_err_West_credit_not_zero_req_X_W_grant_W, L_err_West_credit_zero_or_not_req_X_W_not_grant_W, L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S, L_err_South_credit_zero_or_not_req_X_S_not_grant_S, L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L, L_err_Local_credit_zero_or_not_req_X_L_not_grant_L, L_err_IDLE_req_X_E, L_err_North_req_X_E, L_err_East_req_X_W, L_err_West_req_X_S, L_err_South_req_X_L, L_err_Local_req_X_N, L_err_IDLE_req_X_W, L_err_North_req_X_W, L_err_East_req_X_S, L_err_West_req_X_L, L_err_South_req_X_N, L_err_Local_req_X_E, L_err_IDLE_req_X_S, L_err_North_req_X_S, L_err_East_req_X_L, L_err_West_req_X_N, L_err_South_req_X_E, L_err_Local_req_X_W, L_err_IDLE_req_X_L, L_err_North_req_X_L, L_err_East_req_X_N, L_err_West_req_X_E, L_err_South_req_X_W, L_err_Local_req_X_S, L_arbiter_out_err_state_in_onehot, L_arbiter_out_err_no_request_grants, L_err_request_IDLE_state, L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant,L_err_state_East_Invalid_Grant, L_err_state_West_Invalid_Grant, L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant, L_err_Grants_onehot_or_all_zero : std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Signals needed for grouping checkers to model turn/path faults signal N_FIFO_checkers_ORed, E_FIFO_checkers_ORed, W_FIFO_checkers_ORed, S_FIFO_checkers_ORed, L_FIFO_checkers_ORed : std_logic; signal N2E_turn_fault, N2W_turn_fault, E2N_turn_fault, E2S_turn_fault, W2N_turn_fault, W2S_turn_fault, S2E_turn_fault, S2W_turn_fault : std_logic; signal N2S_path_fault, S2N_path_fault, E2W_path_fault, W2E_path_fault : std_logic; signal not_N2E_turn_fault, not_N2W_turn_fault, not_E2N_turn_fault, not_E2S_turn_fault, not_W2N_turn_fault, not_W2S_turn_fault, not_S2E_turn_fault, not_S2W_turn_fault : std_logic; signal not_N2S_path_fault, not_S2N_path_fault, not_E2W_path_fault, not_W2E_path_fault : std_logic; signal L2N_fault, L2E_fault, L2W_fault, L2S_fault, N2L_fault, E2L_fault, W2L_fault, S2L_fault : std_logic; signal not_L2N_fault, not_L2E_fault, not_L2W_fault, not_L2S_fault, not_N2L_fault, not_E2L_fault, not_W2L_fault, not_S2L_fault : std_logic; -- Just used temporarily for debugging purposes! signal N_LBDR_checkers_ORed, E_LBDR_checkers_ORed, W_LBDR_checkers_ORed, S_LBDR_checkers_ORed, L_LBDR_checkers_ORed : std_logic; signal Allocator_checkers_ORed : std_logic; --signal turn_faults_sig : std_logic_vector(19 downto 0); ------------------------------------------------------------------------------------------------- -- Added because of the chain we make for sending faulty values --------------------------------- -- The chain is : L, N, E, W and S FIFO, then L, N, E, W and S LBDR, ---------------------------- -- then L, N, E, W and S Arbiter_in, -------------------- -- then L, N, E, W and S Arbiter_out and then Allocator's interlal logic ??!! -- ------------------------------------------------------------------------------------------------- --TODO: the chains should be fixed! --Fixed! signal fault_DO_serial_L_FIFO_to_N_FIFO, fault_DO_serial_N_FIFO_to_E_FIFO: std_logic; signal fault_DO_serial_E_FIFO_to_W_FIFO, fault_DO_serial_W_FIFO_to_S_FIFO: std_logic; signal fault_DO_serial_S_FIFO_to_L_LBDR, fault_DO_serial_L_LBDR_to_N_LBDR: std_logic; signal fault_DO_serial_N_LBDR_to_E_LBDR, fault_DO_serial_E_LBDR_to_W_LBDR: std_logic; signal fault_DO_serial_W_LBDR_to_S_LBDR, fault_DO_serial_S_LBDR_to_Allocator: std_logic; ------------------------------------------------------------------ ------------------------------------------------------------------ begin not_N2E_turn_fault <= not N2E_turn_fault; not_N2W_turn_fault <= not N2W_turn_fault; not_E2N_turn_fault <= not E2N_turn_fault; not_E2S_turn_fault <= not E2S_turn_fault; not_W2N_turn_fault <= not W2N_turn_fault; not_W2S_turn_fault <= not W2S_turn_fault; not_S2E_turn_fault <= not S2E_turn_fault; not_S2W_turn_fault <= not S2W_turn_fault; not_N2S_path_fault <= not N2S_path_fault; not_S2N_path_fault <= not S2N_path_fault; not_E2W_path_fault <= not E2W_path_fault; not_W2E_path_fault <= not W2E_path_fault; not_L2N_fault <= not L2N_fault; not_L2E_fault <= not L2E_fault; not_L2W_fault <= not L2W_fault; not_L2S_fault <= not L2S_fault; not_N2L_fault <= not N2L_fault; not_E2L_fault <= not E2L_fault; not_W2L_fault <= not W2L_fault; not_S2L_fault <= not S2L_fault; -- FIFO contributes to all turns and paths, therefore, for each turn or path (for the input direction), all the outputs of FIFO checkers -- corresponding to that input are ORed together. N_FIFO_checkers_ORed <= N_err_empty_full or N_err_empty_read_en or N_err_full_write_en or N_err_state_in_onehot or N_err_read_pointer_in_onehot or N_err_write_pointer_in_onehot or N_err_write_en_write_pointer or N_err_not_write_en_write_pointer or N_err_read_pointer_write_pointer_not_empty or N_err_read_pointer_write_pointer_empty or N_err_read_pointer_write_pointer_not_full or N_err_read_pointer_write_pointer_full or N_err_read_pointer_increment or N_err_read_pointer_not_increment or N_err_write_en or N_err_not_write_en or N_err_not_write_en1 or N_err_not_write_en2 or N_err_read_en_mismatch or N_err_read_en_mismatch1 or N_err_fake_credit_read_en_fake_credit_counter_in_increment or N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or N_err_fake_credit_read_en_credit_out or N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or N_err_state_out_Idle_not_fault_out_not_fake_credit or N_err_state_out_Idle_not_fault_out_not_fault_info_in or N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or N_err_state_out_Idle_fault_out_fake_credit or N_err_state_out_Idle_fault_out_state_in_Packet_drop or N_err_state_out_Idle_fault_out_fault_info_in or N_err_state_out_Idle_fault_out_faulty_packet_in or N_err_state_out_Idle_not_health_info or N_err_state_out_Idle_not_write_fake_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Header_flit_not_valid_in_not_fault_info_in or N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or N_err_state_out_Header_flit_or_Body_flit_not_fake_credit or N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or N_err_state_out_Body_flit_valid_in_not_fault_out_health_info or N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Body_flit_not_valid_in_not_fault_info_in or N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or N_err_state_out_Body_flit_valid_in_fault_out_not_health_info or N_err_state_out_Body_flit_valid_in_not_health_info or N_err_state_out_Body_flit_not_fake_credit or N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or N_err_state_out_Tail_flit_not_valid_in_state_in_Idle or N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or N_err_state_out_Tail_flit_not_valid_in_not_fake_credit or N_err_state_out_Tail_flit_not_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or N_err_fault_info_fault_info_out_equal or N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- East E_FIFO_checkers_ORed <= E_err_empty_full or E_err_empty_read_en or E_err_full_write_en or E_err_state_in_onehot or E_err_read_pointer_in_onehot or E_err_write_pointer_in_onehot or E_err_write_en_write_pointer or E_err_not_write_en_write_pointer or E_err_read_pointer_write_pointer_not_empty or E_err_read_pointer_write_pointer_empty or E_err_read_pointer_write_pointer_not_full or E_err_read_pointer_write_pointer_full or E_err_read_pointer_increment or E_err_read_pointer_not_increment or E_err_write_en or E_err_not_write_en or E_err_not_write_en1 or E_err_not_write_en2 or E_err_read_en_mismatch or E_err_read_en_mismatch1 or E_err_fake_credit_read_en_fake_credit_counter_in_increment or E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or E_err_fake_credit_read_en_credit_out or E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or E_err_state_out_Idle_not_fault_out_not_fake_credit or E_err_state_out_Idle_not_fault_out_not_fault_info_in or E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or E_err_state_out_Idle_fault_out_fake_credit or E_err_state_out_Idle_fault_out_state_in_Packet_drop or E_err_state_out_Idle_fault_out_fault_info_in or E_err_state_out_Idle_fault_out_faulty_packet_in or E_err_state_out_Idle_not_health_info or E_err_state_out_Idle_not_write_fake_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Header_flit_not_valid_in_not_fault_info_in or E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or E_err_state_out_Header_flit_or_Body_flit_not_fake_credit or E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or E_err_state_out_Body_flit_valid_in_not_fault_out_health_info or E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Body_flit_not_valid_in_not_fault_info_in or E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or E_err_state_out_Body_flit_valid_in_fault_out_not_health_info or E_err_state_out_Body_flit_valid_in_not_health_info or E_err_state_out_Body_flit_not_fake_credit or E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or E_err_state_out_Tail_flit_not_valid_in_state_in_Idle or E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or E_err_state_out_Tail_flit_not_valid_in_not_fake_credit or E_err_state_out_Tail_flit_not_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or E_err_fault_info_fault_info_out_equal or E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- West W_FIFO_checkers_ORed <= W_err_empty_full or W_err_empty_read_en or W_err_full_write_en or W_err_state_in_onehot or W_err_read_pointer_in_onehot or W_err_write_pointer_in_onehot or W_err_write_en_write_pointer or W_err_not_write_en_write_pointer or W_err_read_pointer_write_pointer_not_empty or W_err_read_pointer_write_pointer_empty or W_err_read_pointer_write_pointer_not_full or W_err_read_pointer_write_pointer_full or W_err_read_pointer_increment or W_err_read_pointer_not_increment or W_err_write_en or W_err_not_write_en or W_err_not_write_en1 or W_err_not_write_en2 or W_err_read_en_mismatch or W_err_read_en_mismatch1 or W_err_fake_credit_read_en_fake_credit_counter_in_increment or W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or W_err_fake_credit_read_en_credit_out or W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or W_err_state_out_Idle_not_fault_out_not_fake_credit or W_err_state_out_Idle_not_fault_out_not_fault_info_in or W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or W_err_state_out_Idle_fault_out_fake_credit or W_err_state_out_Idle_fault_out_state_in_Packet_drop or W_err_state_out_Idle_fault_out_fault_info_in or W_err_state_out_Idle_fault_out_faulty_packet_in or W_err_state_out_Idle_not_health_info or W_err_state_out_Idle_not_write_fake_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Header_flit_not_valid_in_not_fault_info_in or W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or W_err_state_out_Header_flit_or_Body_flit_not_fake_credit or W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or W_err_state_out_Body_flit_valid_in_not_fault_out_health_info or W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Body_flit_not_valid_in_not_fault_info_in or W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or W_err_state_out_Body_flit_valid_in_fault_out_not_health_info or W_err_state_out_Body_flit_valid_in_not_health_info or W_err_state_out_Body_flit_not_fake_credit or W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or W_err_state_out_Tail_flit_not_valid_in_state_in_Idle or W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or W_err_state_out_Tail_flit_not_valid_in_not_fake_credit or W_err_state_out_Tail_flit_not_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or W_err_fault_info_fault_info_out_equal or W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- South S_FIFO_checkers_ORed <= S_err_empty_full or S_err_empty_read_en or S_err_full_write_en or S_err_state_in_onehot or S_err_read_pointer_in_onehot or S_err_write_pointer_in_onehot or S_err_write_en_write_pointer or S_err_not_write_en_write_pointer or S_err_read_pointer_write_pointer_not_empty or S_err_read_pointer_write_pointer_empty or S_err_read_pointer_write_pointer_not_full or S_err_read_pointer_write_pointer_full or S_err_read_pointer_increment or S_err_read_pointer_not_increment or S_err_write_en or S_err_not_write_en or S_err_not_write_en1 or S_err_not_write_en2 or S_err_read_en_mismatch or S_err_read_en_mismatch1 or S_err_fake_credit_read_en_fake_credit_counter_in_increment or S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or S_err_fake_credit_read_en_credit_out or S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or S_err_state_out_Idle_not_fault_out_not_fake_credit or S_err_state_out_Idle_not_fault_out_not_fault_info_in or S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or S_err_state_out_Idle_fault_out_fake_credit or S_err_state_out_Idle_fault_out_state_in_Packet_drop or S_err_state_out_Idle_fault_out_fault_info_in or S_err_state_out_Idle_fault_out_faulty_packet_in or S_err_state_out_Idle_not_health_info or S_err_state_out_Idle_not_write_fake_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Header_flit_not_valid_in_not_fault_info_in or S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or S_err_state_out_Header_flit_or_Body_flit_not_fake_credit or S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or S_err_state_out_Body_flit_valid_in_not_fault_out_health_info or S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Body_flit_not_valid_in_not_fault_info_in or S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or S_err_state_out_Body_flit_valid_in_fault_out_not_health_info or S_err_state_out_Body_flit_valid_in_not_health_info or S_err_state_out_Body_flit_not_fake_credit or S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or S_err_state_out_Tail_flit_not_valid_in_state_in_Idle or S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or S_err_state_out_Tail_flit_not_valid_in_not_fake_credit or S_err_state_out_Tail_flit_not_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or S_err_fault_info_fault_info_out_equal or S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- Local L_FIFO_checkers_ORed <= L_err_empty_full or L_err_empty_read_en or L_err_full_write_en or L_err_state_in_onehot or L_err_read_pointer_in_onehot or L_err_write_pointer_in_onehot or L_err_write_en_write_pointer or L_err_not_write_en_write_pointer or L_err_read_pointer_write_pointer_not_empty or L_err_read_pointer_write_pointer_empty or L_err_read_pointer_write_pointer_not_full or L_err_read_pointer_write_pointer_full or L_err_read_pointer_increment or L_err_read_pointer_not_increment or L_err_write_en or L_err_not_write_en or L_err_not_write_en1 or L_err_not_write_en2 or L_err_read_en_mismatch or L_err_read_en_mismatch1 or L_err_fake_credit_read_en_fake_credit_counter_in_increment or L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or L_err_fake_credit_read_en_credit_out or L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or L_err_state_out_Idle_not_fault_out_not_fake_credit or L_err_state_out_Idle_not_fault_out_not_fault_info_in or L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or L_err_state_out_Idle_fault_out_fake_credit or L_err_state_out_Idle_fault_out_state_in_Packet_drop or L_err_state_out_Idle_fault_out_fault_info_in or L_err_state_out_Idle_fault_out_faulty_packet_in or L_err_state_out_Idle_not_health_info or L_err_state_out_Idle_not_write_fake_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Header_flit_not_valid_in_not_fault_info_in or L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or L_err_state_out_Header_flit_or_Body_flit_not_fake_credit or L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or L_err_state_out_Body_flit_valid_in_not_fault_out_health_info or L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Body_flit_not_valid_in_not_fault_info_in or L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or L_err_state_out_Body_flit_valid_in_fault_out_not_health_info or L_err_state_out_Body_flit_valid_in_not_health_info or L_err_state_out_Body_flit_not_fake_credit or L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or L_err_state_out_Tail_flit_not_valid_in_state_in_Idle or L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or L_err_state_out_Tail_flit_not_valid_in_not_fake_credit or L_err_state_out_Tail_flit_not_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or L_err_fault_info_fault_info_out_equal or L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Just for debugging purposes of the checkers! -- LBDR checker outputs ORed -- North -- Routing part checkers N_LBDR_checkers_ORed <= N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_N1 or N_err_dst_addr_cur_addr_not_N1 or N_err_dst_addr_cur_addr_E1 or N_err_dst_addr_cur_addr_not_E1 or N_err_dst_addr_cur_addr_W1 or N_err_dst_addr_cur_addr_not_W1 or N_err_dst_addr_cur_addr_S1 or N_err_dst_addr_cur_addr_not_S1 or N_err_dst_addr_cur_addr_Req_L_in or N_err_dst_addr_cur_addr_not_Req_L_in or N_err_header_not_empty_faulty_drop_packet_in or -- added according to new design N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design N_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --N_err_header_not_empty_Req_L_in or -- added according to new design N_err_header_not_empty_Req_N_in or N_err_header_not_empty_Req_E_in or N_err_header_not_empty_Req_W_in or N_err_header_not_empty_Req_S_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or -- Cx_Reconf checkers N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- East -- Routing part checkers E_LBDR_checkers_ORed <= E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_N1 or E_err_dst_addr_cur_addr_not_N1 or E_err_dst_addr_cur_addr_E1 or E_err_dst_addr_cur_addr_not_E1 or E_err_dst_addr_cur_addr_W1 or E_err_dst_addr_cur_addr_not_W1 or E_err_dst_addr_cur_addr_S1 or E_err_dst_addr_cur_addr_not_S1 or E_err_dst_addr_cur_addr_Req_L_in or E_err_dst_addr_cur_addr_not_Req_L_in or E_err_header_not_empty_faulty_drop_packet_in or -- added according to new design E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design E_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --E_err_header_not_empty_Req_L_in or -- added according to new design E_err_header_not_empty_Req_N_in or E_err_header_not_empty_Req_E_in or E_err_header_not_empty_Req_W_in or E_err_header_not_empty_Req_S_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or -- Cx_Reconf checkers E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- West -- Routing part checkers W_LBDR_checkers_ORed <= W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_N1 or W_err_dst_addr_cur_addr_not_N1 or W_err_dst_addr_cur_addr_E1 or W_err_dst_addr_cur_addr_not_E1 or W_err_dst_addr_cur_addr_W1 or W_err_dst_addr_cur_addr_not_W1 or W_err_dst_addr_cur_addr_S1 or W_err_dst_addr_cur_addr_not_S1 or W_err_dst_addr_cur_addr_Req_L_in or W_err_dst_addr_cur_addr_not_Req_L_in or W_err_header_not_empty_faulty_drop_packet_in or -- added according to new design W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design W_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --W_err_header_not_empty_Req_L_in or -- added according to new design W_err_header_not_empty_Req_N_in or W_err_header_not_empty_Req_E_in or W_err_header_not_empty_Req_W_in or W_err_header_not_empty_Req_S_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or -- Cx_Reconf checkers W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- South -- Routing part checkers S_LBDR_checkers_ORed <= S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_N1 or S_err_dst_addr_cur_addr_not_N1 or S_err_dst_addr_cur_addr_E1 or S_err_dst_addr_cur_addr_not_E1 or S_err_dst_addr_cur_addr_W1 or S_err_dst_addr_cur_addr_not_W1 or S_err_dst_addr_cur_addr_S1 or S_err_dst_addr_cur_addr_not_S1 or S_err_dst_addr_cur_addr_Req_L_in or S_err_dst_addr_cur_addr_not_Req_L_in or S_err_header_not_empty_faulty_drop_packet_in or -- added according to new design S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design S_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --S_err_header_not_empty_Req_L_in or -- added according to new design S_err_header_not_empty_Req_N_in or S_err_header_not_empty_Req_E_in or S_err_header_not_empty_Req_W_in or S_err_header_not_empty_Req_S_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or -- Cx_Reconf checkers S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- Local -- Routing part checkers L_LBDR_checkers_ORed <= L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_N1 or L_err_dst_addr_cur_addr_not_N1 or L_err_dst_addr_cur_addr_E1 or L_err_dst_addr_cur_addr_not_E1 or L_err_dst_addr_cur_addr_W1 or L_err_dst_addr_cur_addr_not_W1 or L_err_dst_addr_cur_addr_S1 or L_err_dst_addr_cur_addr_not_S1 or L_err_dst_addr_cur_addr_Req_L_in or L_err_dst_addr_cur_addr_not_Req_L_in or L_err_header_not_empty_faulty_drop_packet_in or -- added according to new design L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design L_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --L_err_header_not_empty_Req_L_in or -- added according to new design L_err_header_not_empty_Req_N_in or L_err_header_not_empty_Req_E_in or L_err_header_not_empty_Req_W_in or L_err_header_not_empty_Req_S_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or -- Cx_Reconf checkers L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Allocator checker outputs ORed ! -- Allocator logic checker outputs Allocator_checkers_ORed <= err_grant_N_N_sig_not_empty_N_grant_N_N or err_not_grant_N_N_sig_or_empty_N_not_grant_N_N or err_grant_N_E_sig_not_empty_E_grant_N_E or err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or err_grant_N_W_sig_not_empty_W_grant_N_W or err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or err_grant_N_S_sig_not_empty_S_grant_N_S or err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or err_grant_N_L_sig_not_empty_L_grant_N_L or err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or err_grant_E_N_sig_not_empty_N_grant_E_N or err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or err_grant_E_E_sig_not_empty_E_grant_E_E or err_not_grant_E_E_sig_or_empty_E_not_grant_E_E or err_grant_E_W_sig_not_empty_W_grant_E_W or err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or err_grant_E_S_sig_not_empty_S_grant_E_S or err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or err_grant_E_L_sig_not_empty_L_grant_E_L or err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or err_grant_W_N_sig_not_empty_N_grant_W_N or err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or err_grant_W_E_sig_not_empty_E_grant_W_E or err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or err_grant_W_W_sig_not_empty_W_grant_W_W or err_not_grant_W_W_sig_or_empty_W_not_grant_W_W or err_grant_W_S_sig_not_empty_S_grant_W_S or err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or err_grant_W_L_sig_not_empty_L_grant_W_L or err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or err_grant_S_N_sig_not_empty_N_grant_S_N or err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or err_grant_S_E_sig_not_empty_E_grant_S_E or err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or err_grant_S_W_sig_not_empty_W_grant_S_W or err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or err_grant_S_S_sig_not_empty_S_grant_S_S or err_not_grant_S_S_sig_or_empty_S_not_grant_S_S or err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or err_grant_L_N_sig_not_empty_N_grant_L_N or err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or err_grant_L_E_sig_not_empty_E_grant_L_E or err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or err_grant_L_W_sig_not_empty_W_grant_L_W or err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or err_grant_L_L_sig_not_empty_L_grant_L_L or err_not_grant_L_L_sig_or_empty_L_not_grant_L_L or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or -- Allocator credit counter logic checker outputs err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal or -- Arbiter_in checker outputs -- North Arbiter_in checker outputs N_err_Requests_state_in_state_not_equal or N_err_IDLE_Req_N or N_err_IDLE_grant_N or N_err_North_Req_N or N_err_North_grant_N or N_err_East_Req_E or N_err_East_grant_E or N_err_West_Req_W or N_err_West_grant_W or N_err_South_Req_S or N_err_South_grant_S or N_err_Local_Req_L or N_err_Local_grant_L or N_err_IDLE_Req_E or N_err_IDLE_grant_E or N_err_North_Req_E or N_err_North_grant_E or N_err_East_Req_W or N_err_East_grant_W or N_err_West_Req_S or N_err_West_grant_S or N_err_South_Req_L or N_err_South_grant_L or N_err_Local_Req_N or N_err_Local_grant_N or N_err_IDLE_Req_W or N_err_IDLE_grant_W or N_err_North_Req_W or N_err_North_grant_W or N_err_East_Req_S or N_err_East_grant_S or N_err_West_Req_L or N_err_West_grant_L or N_err_South_Req_N or N_err_South_grant_N or N_err_Local_Req_E or N_err_Local_grant_E or N_err_IDLE_Req_S or N_err_IDLE_grant_S or N_err_North_Req_S or N_err_North_grant_S or N_err_East_Req_L or N_err_East_grant_L or N_err_West_Req_N or N_err_West_grant_N or N_err_South_Req_E or N_err_South_grant_E or N_err_Local_Req_W or N_err_Local_grant_W or N_err_IDLE_Req_L or N_err_IDLE_grant_L or N_err_North_Req_L or N_err_North_grant_L or N_err_East_Req_N or N_err_East_grant_N or N_err_West_Req_E or N_err_West_grant_E or N_err_South_Req_W or N_err_South_grant_W or N_err_Local_Req_S or N_err_Local_grant_S or N_err_arbiter_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_N_grant_N or N_err_no_Req_E_grant_E or N_err_no_Req_W_grant_W or N_err_no_Req_S_grant_S or N_err_no_Req_L_grant_L or -- East Arbiter_in checker outputs E_err_Requests_state_in_state_not_equal or E_err_IDLE_Req_N or E_err_IDLE_grant_N or E_err_North_Req_N or E_err_North_grant_N or E_err_East_Req_E or E_err_East_grant_E or E_err_West_Req_W or E_err_West_grant_W or E_err_South_Req_S or E_err_South_grant_S or E_err_Local_Req_L or E_err_Local_grant_L or E_err_IDLE_Req_E or E_err_IDLE_grant_E or E_err_North_Req_E or E_err_North_grant_E or E_err_East_Req_W or E_err_East_grant_W or E_err_West_Req_S or E_err_West_grant_S or E_err_South_Req_L or E_err_South_grant_L or E_err_Local_Req_N or E_err_Local_grant_N or E_err_IDLE_Req_W or E_err_IDLE_grant_W or E_err_North_Req_W or E_err_North_grant_W or E_err_East_Req_S or E_err_East_grant_S or E_err_West_Req_L or E_err_West_grant_L or E_err_South_Req_N or E_err_South_grant_N or E_err_Local_Req_E or E_err_Local_grant_E or E_err_IDLE_Req_S or E_err_IDLE_grant_S or E_err_North_Req_S or E_err_North_grant_S or E_err_East_Req_L or E_err_East_grant_L or E_err_West_Req_N or E_err_West_grant_N or E_err_South_Req_E or E_err_South_grant_E or E_err_Local_Req_W or E_err_Local_grant_W or E_err_IDLE_Req_L or E_err_IDLE_grant_L or E_err_North_Req_L or E_err_North_grant_L or E_err_East_Req_N or E_err_East_grant_N or E_err_West_Req_E or E_err_West_grant_E or E_err_South_Req_W or E_err_South_grant_W or E_err_Local_Req_S or E_err_Local_grant_S or E_err_arbiter_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_N_grant_N or E_err_no_Req_E_grant_E or E_err_no_Req_W_grant_W or E_err_no_Req_S_grant_S or E_err_no_Req_L_grant_L or -- West Arbiter_in checker outputs W_err_Requests_state_in_state_not_equal or W_err_IDLE_Req_N or W_err_IDLE_grant_N or W_err_North_Req_N or W_err_North_grant_N or W_err_East_Req_E or W_err_East_grant_E or W_err_West_Req_W or W_err_West_grant_W or W_err_South_Req_S or W_err_South_grant_S or W_err_Local_Req_L or W_err_Local_grant_L or W_err_IDLE_Req_E or W_err_IDLE_grant_E or W_err_North_Req_E or W_err_North_grant_E or W_err_East_Req_W or W_err_East_grant_W or W_err_West_Req_S or W_err_West_grant_S or W_err_South_Req_L or W_err_South_grant_L or W_err_Local_Req_N or W_err_Local_grant_N or W_err_IDLE_Req_W or W_err_IDLE_grant_W or W_err_North_Req_W or W_err_North_grant_W or W_err_East_Req_S or W_err_East_grant_S or W_err_West_Req_L or W_err_West_grant_L or W_err_South_Req_N or W_err_South_grant_N or W_err_Local_Req_E or W_err_Local_grant_E or W_err_IDLE_Req_S or W_err_IDLE_grant_S or W_err_North_Req_S or W_err_North_grant_S or W_err_East_Req_L or W_err_East_grant_L or W_err_West_Req_N or W_err_West_grant_N or W_err_South_Req_E or W_err_South_grant_E or W_err_Local_Req_W or W_err_Local_grant_W or W_err_IDLE_Req_L or W_err_IDLE_grant_L or W_err_North_Req_L or W_err_North_grant_L or W_err_East_Req_N or W_err_East_grant_N or W_err_West_Req_E or W_err_West_grant_E or W_err_South_Req_W or W_err_South_grant_W or W_err_Local_Req_S or W_err_Local_grant_S or W_err_arbiter_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_N_grant_N or W_err_no_Req_E_grant_E or W_err_no_Req_W_grant_W or W_err_no_Req_S_grant_S or W_err_no_Req_L_grant_L or -- South Arbiter_in checker outputs S_err_Requests_state_in_state_not_equal or S_err_IDLE_Req_N or S_err_IDLE_grant_N or S_err_North_Req_N or S_err_North_grant_N or S_err_East_Req_E or S_err_East_grant_E or S_err_West_Req_W or S_err_West_grant_W or S_err_South_Req_S or S_err_South_grant_S or S_err_Local_Req_L or S_err_Local_grant_L or S_err_IDLE_Req_E or S_err_IDLE_grant_E or S_err_North_Req_E or S_err_North_grant_E or S_err_East_Req_W or S_err_East_grant_W or S_err_West_Req_S or S_err_West_grant_S or S_err_South_Req_L or S_err_South_grant_L or S_err_Local_Req_N or S_err_Local_grant_N or S_err_IDLE_Req_W or S_err_IDLE_grant_W or S_err_North_Req_W or S_err_North_grant_W or S_err_East_Req_S or S_err_East_grant_S or S_err_West_Req_L or S_err_West_grant_L or S_err_South_Req_N or S_err_South_grant_N or S_err_Local_Req_E or S_err_Local_grant_E or S_err_IDLE_Req_S or S_err_IDLE_grant_S or S_err_North_Req_S or S_err_North_grant_S or S_err_East_Req_L or S_err_East_grant_L or S_err_West_Req_N or S_err_West_grant_N or S_err_South_Req_E or S_err_South_grant_E or S_err_Local_Req_W or S_err_Local_grant_W or S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or S_err_East_Req_N or S_err_East_grant_N or S_err_West_Req_E or S_err_West_grant_E or S_err_South_Req_W or S_err_South_grant_W or S_err_Local_Req_S or S_err_Local_grant_S or S_err_arbiter_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_N_grant_N or S_err_no_Req_E_grant_E or S_err_no_Req_W_grant_W or S_err_no_Req_S_grant_S or S_err_no_Req_L_grant_L or -- Local Arbiter_in checker outputs L_err_Requests_state_in_state_not_equal or L_err_IDLE_Req_N or L_err_IDLE_grant_N or L_err_North_Req_N or L_err_North_grant_N or L_err_East_Req_E or L_err_East_grant_E or L_err_West_Req_W or L_err_West_grant_W or L_err_South_Req_S or L_err_South_grant_S or L_err_Local_Req_L or L_err_Local_grant_L or L_err_IDLE_Req_E or L_err_IDLE_grant_E or L_err_North_Req_E or L_err_North_grant_E or L_err_East_Req_W or L_err_East_grant_W or L_err_West_Req_S or L_err_West_grant_S or L_err_South_Req_L or L_err_South_grant_L or L_err_Local_Req_N or L_err_Local_grant_N or L_err_IDLE_Req_W or L_err_IDLE_grant_W or L_err_North_Req_W or L_err_North_grant_W or L_err_East_Req_S or L_err_East_grant_S or L_err_West_Req_L or L_err_West_grant_L or L_err_South_Req_N or L_err_South_grant_N or L_err_Local_Req_E or L_err_Local_grant_E or L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or L_err_East_Req_L or L_err_East_grant_L or L_err_West_Req_N or L_err_West_grant_N or L_err_South_Req_E or L_err_South_grant_E or L_err_Local_Req_W or L_err_Local_grant_W or L_err_IDLE_Req_L or L_err_IDLE_grant_L or L_err_North_Req_L or L_err_North_grant_L or L_err_East_Req_N or L_err_East_grant_N or L_err_West_Req_E or L_err_West_grant_E or L_err_South_Req_W or L_err_South_grant_W or L_err_Local_Req_S or L_err_Local_grant_S or L_err_arbiter_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_N_grant_N or L_err_no_Req_E_grant_E or L_err_no_Req_W_grant_W or L_err_no_Req_S_grant_S or L_err_no_Req_L_grant_L or -- Arbiter_out checker outputs -- North Arbiter_out checker outputs N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_IDLE_req_X_N or N_err_North_req_X_N or N_err_North_credit_not_zero_req_X_N_grant_N or N_err_North_credit_zero_or_not_req_X_N_not_grant_N or N_err_East_req_X_E or N_err_East_credit_not_zero_req_X_E_grant_E or N_err_East_credit_zero_or_not_req_X_E_not_grant_E or N_err_West_req_X_W or N_err_West_credit_not_zero_req_X_W_grant_W or N_err_West_credit_zero_or_not_req_X_W_not_grant_W or N_err_South_req_X_S or N_err_South_credit_not_zero_req_X_S_grant_S or N_err_South_credit_zero_or_not_req_X_S_not_grant_S or N_err_Local_req_X_L or N_err_Local_credit_not_zero_req_X_L_grant_L or N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or N_err_IDLE_req_X_E or N_err_North_req_X_E or N_err_East_req_X_W or N_err_West_req_X_S or N_err_South_req_X_L or N_err_Local_req_X_N or N_err_IDLE_req_X_W or N_err_North_req_X_W or N_err_East_req_X_S or N_err_West_req_X_L or N_err_South_req_X_N or N_err_Local_req_X_E or N_err_IDLE_req_X_S or N_err_North_req_X_S or N_err_East_req_X_L or N_err_West_req_X_N or N_err_South_req_X_E or N_err_Local_req_X_W or N_err_IDLE_req_X_L or N_err_North_req_X_L or N_err_East_req_X_N or N_err_West_req_X_E or N_err_South_req_X_W or N_err_Local_req_X_S or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_state_North_Invalid_Grant or N_err_state_East_Invalid_Grant or N_err_state_West_Invalid_Grant or N_err_state_South_Invalid_Grant or N_err_state_Local_Invalid_Grant or N_err_Grants_onehot_or_all_zero or -- East Arbiter_out checker outputs E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_IDLE_req_X_N or E_err_North_req_X_N or E_err_North_credit_not_zero_req_X_N_grant_N or E_err_North_credit_zero_or_not_req_X_N_not_grant_N or E_err_East_req_X_E or E_err_East_credit_not_zero_req_X_E_grant_E or E_err_East_credit_zero_or_not_req_X_E_not_grant_E or E_err_West_req_X_W or E_err_West_credit_not_zero_req_X_W_grant_W or E_err_West_credit_zero_or_not_req_X_W_not_grant_W or E_err_South_req_X_S or E_err_South_credit_not_zero_req_X_S_grant_S or E_err_South_credit_zero_or_not_req_X_S_not_grant_S or E_err_Local_req_X_L or E_err_Local_credit_not_zero_req_X_L_grant_L or E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or E_err_IDLE_req_X_E or E_err_North_req_X_E or E_err_East_req_X_W or E_err_West_req_X_S or E_err_South_req_X_L or E_err_Local_req_X_N or E_err_IDLE_req_X_W or E_err_North_req_X_W or E_err_East_req_X_S or E_err_West_req_X_L or E_err_South_req_X_N or E_err_Local_req_X_E or E_err_IDLE_req_X_S or E_err_North_req_X_S or E_err_East_req_X_L or E_err_West_req_X_N or E_err_South_req_X_E or E_err_Local_req_X_W or E_err_IDLE_req_X_L or E_err_North_req_X_L or E_err_East_req_X_N or E_err_West_req_X_E or E_err_South_req_X_W or E_err_Local_req_X_S or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_state_North_Invalid_Grant or E_err_state_East_Invalid_Grant or E_err_state_West_Invalid_Grant or E_err_state_South_Invalid_Grant or E_err_state_Local_Invalid_Grant or E_err_Grants_onehot_or_all_zero or -- West Arbiter_out checker outputs W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_IDLE_req_X_N or W_err_North_req_X_N or W_err_North_credit_not_zero_req_X_N_grant_N or W_err_North_credit_zero_or_not_req_X_N_not_grant_N or W_err_East_req_X_E or W_err_East_credit_not_zero_req_X_E_grant_E or W_err_East_credit_zero_or_not_req_X_E_not_grant_E or W_err_West_req_X_W or W_err_West_credit_not_zero_req_X_W_grant_W or W_err_West_credit_zero_or_not_req_X_W_not_grant_W or W_err_South_req_X_S or W_err_South_credit_not_zero_req_X_S_grant_S or W_err_South_credit_zero_or_not_req_X_S_not_grant_S or W_err_Local_req_X_L or W_err_Local_credit_not_zero_req_X_L_grant_L or W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or W_err_IDLE_req_X_E or W_err_North_req_X_E or W_err_East_req_X_W or W_err_West_req_X_S or W_err_South_req_X_L or W_err_Local_req_X_N or W_err_IDLE_req_X_W or W_err_North_req_X_W or W_err_East_req_X_S or W_err_West_req_X_L or W_err_South_req_X_N or W_err_Local_req_X_E or W_err_IDLE_req_X_S or W_err_North_req_X_S or W_err_East_req_X_L or W_err_West_req_X_N or W_err_South_req_X_E or W_err_Local_req_X_W or W_err_IDLE_req_X_L or W_err_North_req_X_L or W_err_East_req_X_N or W_err_West_req_X_E or W_err_South_req_X_W or W_err_Local_req_X_S or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_state_North_Invalid_Grant or W_err_state_East_Invalid_Grant or W_err_state_West_Invalid_Grant or W_err_state_South_Invalid_Grant or W_err_state_Local_Invalid_Grant or W_err_Grants_onehot_or_all_zero or -- South Arbiter_out checker outputs S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_IDLE_req_X_N or S_err_North_req_X_N or S_err_North_credit_not_zero_req_X_N_grant_N or S_err_North_credit_zero_or_not_req_X_N_not_grant_N or S_err_East_req_X_E or S_err_East_credit_not_zero_req_X_E_grant_E or S_err_East_credit_zero_or_not_req_X_E_not_grant_E or S_err_West_req_X_W or S_err_West_credit_not_zero_req_X_W_grant_W or S_err_West_credit_zero_or_not_req_X_W_not_grant_W or S_err_South_req_X_S or S_err_South_credit_not_zero_req_X_S_grant_S or S_err_South_credit_zero_or_not_req_X_S_not_grant_S or S_err_Local_req_X_L or S_err_Local_credit_not_zero_req_X_L_grant_L or S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or S_err_IDLE_req_X_E or S_err_North_req_X_E or S_err_East_req_X_W or S_err_West_req_X_S or S_err_South_req_X_L or S_err_Local_req_X_N or S_err_IDLE_req_X_W or S_err_North_req_X_W or S_err_East_req_X_S or S_err_West_req_X_L or S_err_South_req_X_N or S_err_Local_req_X_E or S_err_IDLE_req_X_S or S_err_North_req_X_S or S_err_East_req_X_L or S_err_West_req_X_N or S_err_South_req_X_E or S_err_Local_req_X_W or S_err_IDLE_req_X_L or S_err_North_req_X_L or S_err_East_req_X_N or S_err_West_req_X_E or S_err_South_req_X_W or S_err_Local_req_X_S or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_state_North_Invalid_Grant or S_err_state_East_Invalid_Grant or S_err_state_West_Invalid_Grant or S_err_state_South_Invalid_Grant or S_err_state_Local_Invalid_Grant or S_err_Grants_onehot_or_all_zero or -- Local Arbiter_out checker outputs L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_IDLE_req_X_N or L_err_North_req_X_N or L_err_North_credit_not_zero_req_X_N_grant_N or L_err_North_credit_zero_or_not_req_X_N_not_grant_N or L_err_East_req_X_E or L_err_East_credit_not_zero_req_X_E_grant_E or L_err_East_credit_zero_or_not_req_X_E_not_grant_E or L_err_West_req_X_W or L_err_West_credit_not_zero_req_X_W_grant_W or L_err_West_credit_zero_or_not_req_X_W_not_grant_W or L_err_South_req_X_S or L_err_South_credit_not_zero_req_X_S_grant_S or L_err_South_credit_zero_or_not_req_X_S_not_grant_S or L_err_Local_req_X_L or L_err_Local_credit_not_zero_req_X_L_grant_L or L_err_Local_credit_zero_or_not_req_X_L_not_grant_L or L_err_IDLE_req_X_E or L_err_North_req_X_E or L_err_East_req_X_W or L_err_West_req_X_S or L_err_South_req_X_L or L_err_Local_req_X_N or L_err_IDLE_req_X_W or L_err_North_req_X_W or L_err_East_req_X_S or L_err_West_req_X_L or L_err_South_req_X_N or L_err_Local_req_X_E or L_err_IDLE_req_X_S or L_err_North_req_X_S or L_err_East_req_X_L or L_err_West_req_X_N or L_err_South_req_X_E or L_err_Local_req_X_W or L_err_IDLE_req_X_L or L_err_North_req_X_L or L_err_East_req_X_N or L_err_West_req_X_E or L_err_South_req_X_W or L_err_Local_req_X_S or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_state_North_Invalid_Grant or L_err_state_East_Invalid_Grant or L_err_state_West_Invalid_Grant or L_err_state_South_Invalid_Grant or L_err_state_Local_Invalid_Grant or L_err_Grants_onehot_or_all_zero; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Turn fault checkers -- FIFO N2E_turn_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_E1 or N_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or N_err_header_not_empty_Req_E_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_East_Req_E or N_err_East_grant_E or N_err_IDLE_Req_E or N_err_IDLE_grant_E or N_err_North_Req_E or N_err_North_grant_E or N_err_Local_Req_E or N_err_Local_grant_E or N_err_South_Req_E or N_err_South_grant_E or N_err_West_Req_E or N_err_West_grant_E or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_IDLE_req_X_N or E_err_North_req_X_N or E_err_North_credit_not_zero_req_X_N_grant_N or E_err_North_credit_zero_or_not_req_X_N_not_grant_N or E_err_Local_req_X_N or E_err_South_req_X_N or E_err_West_req_X_N or E_err_East_req_X_N or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or W_err_South_req_X_N or W_err_West_req_X_N or W_err_East_req_X_N or err_grant_E_N_sig_not_empty_N_grant_E_N or err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- FIFO N2W_turn_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_W1 or N_err_dst_addr_cur_addr_not_W1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or N_err_header_not_empty_Req_W_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_West_Req_W or N_err_West_grant_W or N_err_East_Req_W or N_err_East_grant_W or N_err_IDLE_Req_W or N_err_IDLE_grant_W or N_err_North_Req_W or N_err_North_grant_W or N_err_Local_Req_W or N_err_Local_grant_W or N_err_South_Req_W or N_err_South_grant_W or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_IDLE_req_X_N or W_err_North_req_X_N or W_err_North_credit_not_zero_req_X_N_grant_N or W_err_North_credit_zero_or_not_req_X_N_not_grant_N or W_err_Local_req_X_N or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_N_sig_not_empty_N_grant_W_N or err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- FIFO E2N_turn_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_N1 or E_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or E_err_header_not_empty_Req_N_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_IDLE_Req_N or E_err_IDLE_grant_N or E_err_North_Req_N or E_err_North_grant_N or E_err_Local_Req_N or E_err_Local_grant_N or E_err_South_Req_N or E_err_South_grant_N or E_err_West_Req_N or E_err_West_grant_N or E_err_East_Req_N or E_err_East_grant_N or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_East_req_X_E or N_err_East_credit_not_zero_req_X_E_grant_E or N_err_East_credit_zero_or_not_req_X_E_not_grant_E or N_err_IDLE_req_X_E or N_err_North_req_X_E or N_err_Local_req_X_E or N_err_South_req_X_E or N_err_West_req_X_E or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_Grants_onehot_or_all_zero or err_grant_N_E_sig_not_empty_E_grant_N_E or err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO E2S_turn_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_S1 or E_err_dst_addr_cur_addr_not_S1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or E_err_header_not_empty_Req_S_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_South_Req_S or E_err_South_grant_S or E_err_West_Req_S or E_err_West_grant_S or E_err_East_Req_S or E_err_East_grant_S or E_err_IDLE_Req_S or E_err_IDLE_grant_S or E_err_North_Req_S or E_err_North_grant_S or E_err_Local_Req_S or E_err_Local_grant_S or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_East_req_X_E or S_err_East_credit_not_zero_req_X_E_grant_E or S_err_East_credit_zero_or_not_req_X_E_not_grant_E or S_err_IDLE_req_X_E or S_err_North_req_X_E or S_err_Local_req_X_E or S_err_South_req_X_E or S_err_West_req_X_E or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_E_sig_not_empty_E_grant_S_E or err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO W2N_turn_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_N1 or W_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_N_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_IDLE_Req_N or W_err_IDLE_grant_N or W_err_North_Req_N or W_err_North_grant_N or W_err_Local_Req_N or W_err_Local_grant_N or W_err_South_Req_N or W_err_South_grant_N or W_err_West_Req_N or W_err_West_grant_N or W_err_East_Req_N or W_err_East_grant_N or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_West_req_X_W or N_err_West_credit_not_zero_req_X_W_grant_W or N_err_West_credit_zero_or_not_req_X_W_not_grant_W or N_err_East_req_X_W or N_err_IDLE_req_X_W or N_err_North_req_X_W or N_err_Local_req_X_W or N_err_South_req_X_W or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or err_grant_N_W_sig_not_empty_W_grant_N_W or err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO W2S_turn_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_S1 or W_err_dst_addr_cur_addr_not_S1 or W_err_header_not_empty_faulty_drop_packet_in or W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or W_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_S_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_South_Req_S or W_err_South_grant_S or W_err_West_Req_S or W_err_West_grant_S or W_err_East_Req_S or W_err_East_grant_S or W_err_IDLE_Req_S or W_err_IDLE_grant_S or W_err_North_Req_S or W_err_North_grant_S or W_err_Local_Req_S or W_err_Local_grant_S or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_West_req_X_W or S_err_West_credit_not_zero_req_X_W_grant_W or S_err_West_credit_zero_or_not_req_X_W_not_grant_W or S_err_East_req_X_W or S_err_IDLE_req_X_W or S_err_North_req_X_W or S_err_Local_req_X_W or S_err_South_req_X_W or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_W_sig_not_empty_W_grant_S_W or err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO S2E_turn_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_E1 or S_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_E_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_East_Req_E or S_err_East_grant_E or S_err_IDLE_Req_E or S_err_IDLE_grant_E or S_err_North_Req_E or S_err_North_grant_E or S_err_Local_Req_E or S_err_Local_grant_E or S_err_South_Req_E or S_err_South_grant_E or S_err_West_Req_E or S_err_West_grant_E or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_South_req_X_S or E_err_South_credit_not_zero_req_X_S_grant_S or E_err_South_credit_zero_or_not_req_X_S_not_grant_S or E_err_West_req_X_S or E_err_East_req_X_S or E_err_IDLE_req_X_S or E_err_North_req_X_S or E_err_Local_req_X_S or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or err_grant_E_S_sig_not_empty_S_grant_E_S or err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_grants_valid_not_match or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- FIFO S2W_turn_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_W1 or S_err_dst_addr_cur_addr_not_W1 or S_err_header_not_empty_faulty_drop_packet_in or S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or S_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_W_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_West_Req_W or S_err_West_grant_W or S_err_East_Req_W or S_err_East_grant_W or S_err_IDLE_Req_W or S_err_IDLE_grant_W or S_err_North_Req_W or S_err_North_grant_W or S_err_Local_Req_W or S_err_Local_grant_W or S_err_South_Req_W or S_err_South_grant_W or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_South_req_X_S or W_err_South_credit_not_zero_req_X_S_grant_S or W_err_South_credit_zero_or_not_req_X_S_not_grant_S or W_err_West_req_X_S or W_err_East_req_X_S or W_err_IDLE_req_X_S or W_err_North_req_X_S or W_err_Local_req_X_S or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_S_sig_not_empty_S_grant_W_S or err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- Path fault checkers -- FIFO N2S_path_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_S1 or N_err_dst_addr_cur_addr_not_S1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or N_err_header_not_empty_Req_S_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_South_Req_S or N_err_South_grant_S or N_err_West_Req_S or N_err_West_grant_S or N_err_East_Req_S or N_err_East_grant_S or N_err_IDLE_Req_S or N_err_IDLE_grant_S or N_err_North_Req_S or N_err_North_grant_S or N_err_Local_Req_S or N_err_Local_grant_S or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_IDLE_req_X_N or S_err_North_req_X_N or S_err_North_credit_not_zero_req_X_N_grant_N or S_err_North_credit_zero_or_not_req_X_N_not_grant_N or S_err_Local_req_X_N or S_err_South_req_X_N or S_err_West_req_X_N or S_err_East_req_X_N or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_N_sig_not_empty_N_grant_S_N or err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO S2N_path_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_N1 or S_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_N_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_IDLE_Req_N or S_err_IDLE_grant_N or S_err_North_Req_N or S_err_North_grant_N or S_err_Local_Req_N or S_err_Local_grant_N or S_err_South_Req_N or S_err_South_grant_N or S_err_West_Req_N or S_err_West_grant_N or S_err_East_Req_N or S_err_East_grant_N or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_South_req_X_S or N_err_South_credit_not_zero_req_X_S_grant_S or N_err_South_credit_zero_or_not_req_X_S_not_grant_S or N_err_West_req_X_S or N_err_East_req_X_S or N_err_IDLE_req_X_S or N_err_North_req_X_S or N_err_Local_req_X_S or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or err_grant_N_S_sig_not_empty_S_grant_N_S or err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO E2W_path_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_W1 or E_err_dst_addr_cur_addr_not_W1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or E_err_header_not_empty_Req_W_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_West_Req_W or E_err_West_grant_W or E_err_East_Req_W or E_err_East_grant_W or E_err_IDLE_Req_W or E_err_IDLE_grant_W or E_err_North_Req_W or E_err_North_grant_W or E_err_Local_Req_W or E_err_Local_grant_W or E_err_South_Req_W or E_err_South_grant_W or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_East_req_X_E or W_err_East_credit_not_zero_req_X_E_grant_E or W_err_East_credit_zero_or_not_req_X_E_not_grant_E or W_err_IDLE_req_X_E or W_err_North_req_X_E or W_err_Local_req_X_E or W_err_South_req_X_E or W_err_West_req_X_E or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_E_sig_not_empty_E_grant_W_E or err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- FIFO W2E_path_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_E1 or W_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_E_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_East_Req_E or W_err_East_grant_E or W_err_IDLE_Req_E or W_err_IDLE_grant_E or W_err_North_Req_E or W_err_North_grant_E or W_err_Local_Req_E or W_err_Local_grant_E or W_err_South_Req_E or W_err_South_grant_E or W_err_West_Req_E or W_err_West_grant_E or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_West_req_X_W or E_err_West_credit_not_zero_req_X_W_grant_W or E_err_West_credit_zero_or_not_req_X_W_not_grant_W or E_err_East_req_X_W or E_err_IDLE_req_X_W or E_err_North_req_X_W or E_err_Local_req_X_W or E_err_South_req_X_W or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or err_grant_E_W_sig_not_empty_W_grant_E_W or err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- Checkers for Paths/turns from/to Local port -- FIFO L2N_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_N1 or L_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_N_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_IDLE_Req_N or L_err_IDLE_grant_N or L_err_North_Req_N or L_err_North_grant_N or L_err_Local_Req_N or L_err_Local_grant_N or L_err_South_Req_N or L_err_South_grant_N or L_err_West_Req_N or L_err_West_grant_N or L_err_East_Req_N or L_err_East_grant_N or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_Local_req_X_L or N_err_Local_credit_not_zero_req_X_L_grant_L or N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or N_err_South_req_X_L or N_err_West_req_X_L or N_err_East_req_X_L or N_err_IDLE_req_X_L or N_err_North_req_X_L or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or err_grant_N_L_sig_not_empty_L_grant_N_L or err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO L2E_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_E1 or L_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_E_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_East_Req_E or L_err_East_grant_E or L_err_IDLE_Req_E or L_err_IDLE_grant_E or L_err_North_Req_E or L_err_North_grant_E or L_err_Local_Req_E or L_err_Local_grant_E or L_err_South_Req_E or L_err_South_grant_E or L_err_West_Req_E or L_err_West_grant_E or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_Local_req_X_L or E_err_Local_credit_not_zero_req_X_L_grant_L or E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or E_err_South_req_X_L or E_err_West_req_X_L or E_err_East_req_X_L or E_err_IDLE_req_X_L or E_err_North_req_X_L or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or err_grant_E_L_sig_not_empty_L_grant_E_L or err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_grants_valid_not_match or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- FIFO L2W_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_W1 or L_err_dst_addr_cur_addr_not_W1 or L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_W_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_West_Req_W or L_err_West_grant_W or L_err_East_Req_W or L_err_East_grant_W or L_err_IDLE_Req_W or L_err_IDLE_grant_W or L_err_North_Req_W or L_err_North_grant_W or L_err_Local_Req_W or L_err_Local_grant_W or L_err_South_Req_W or L_err_South_grant_W or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_Local_req_X_L or W_err_Local_credit_not_zero_req_X_L_grant_L or W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or W_err_South_req_X_L or W_err_West_req_X_L or W_err_East_req_X_L or W_err_IDLE_req_X_L or W_err_North_req_X_L or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_L_sig_not_empty_L_grant_W_L or err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- FIFO L2S_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_S1 or L_err_dst_addr_cur_addr_not_S1 or L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_S_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_South_Req_S or L_err_South_grant_S or L_err_West_Req_S or L_err_West_grant_S or L_err_East_Req_S or L_err_East_grant_S or L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or L_err_Local_Req_S or L_err_Local_grant_S or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_Local_req_X_L or S_err_Local_credit_not_zero_req_X_L_grant_L or S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or S_err_South_req_X_L or S_err_West_req_X_L or S_err_East_req_X_L or S_err_IDLE_req_X_L or S_err_North_req_X_L or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO N2L_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_Req_L_in or N_err_dst_addr_cur_addr_not_Req_L_in or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or --N_err_header_not_empty_Req_L_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_Local_Req_L or N_err_Local_grant_L or N_err_South_Req_L or N_err_South_grant_L or N_err_West_Req_L or N_err_West_grant_L or N_err_East_Req_L or N_err_East_grant_L or N_err_IDLE_Req_L or N_err_IDLE_grant_L or N_err_North_Req_L or N_err_North_grant_L or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_IDLE_req_X_N or L_err_North_req_X_N or L_err_North_credit_not_zero_req_X_N_grant_N or L_err_North_credit_zero_or_not_req_X_N_not_grant_N or L_err_Local_req_X_N or L_err_South_req_X_N or L_err_West_req_X_N or L_err_East_req_X_N or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_N_sig_not_empty_N_grant_L_N or err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; -- FIFO E2L_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_Req_L_in or E_err_dst_addr_cur_addr_not_Req_L_in or E_err_header_not_empty_faulty_drop_packet_in or E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or E_err_header_not_empty_faulty_Req_in_all_zero or --E_err_header_not_empty_Req_L_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_Local_Req_L or E_err_Local_grant_L or E_err_South_Req_L or E_err_South_grant_L or E_err_West_Req_L or E_err_West_grant_L or E_err_East_Req_L or E_err_East_grant_L or E_err_IDLE_Req_L or E_err_IDLE_grant_L or E_err_North_Req_L or E_err_North_grant_L or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_East_req_X_E or L_err_East_credit_not_zero_req_X_E_grant_E or L_err_East_credit_zero_or_not_req_X_E_not_grant_E or L_err_IDLE_req_X_E or L_err_North_req_X_E or L_err_Local_req_X_E or L_err_South_req_X_E or L_err_West_req_X_E or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_E_sig_not_empty_E_grant_L_E or err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; -- FIFO W2L_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_Req_L_in or W_err_dst_addr_cur_addr_not_Req_L_in or W_err_header_not_empty_faulty_drop_packet_in or W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or W_err_header_not_empty_faulty_Req_in_all_zero or --W_err_header_not_empty_Req_L_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_Local_Req_L or W_err_Local_grant_L or W_err_South_Req_L or W_err_South_grant_L or W_err_West_Req_L or W_err_West_grant_L or W_err_East_Req_L or W_err_East_grant_L or W_err_IDLE_Req_L or W_err_IDLE_grant_L or W_err_North_Req_L or W_err_North_grant_L or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_West_req_X_W or L_err_West_credit_not_zero_req_X_W_grant_W or L_err_West_credit_zero_or_not_req_X_W_not_grant_W or L_err_East_req_X_W or L_err_IDLE_req_X_W or L_err_North_req_X_W or L_err_Local_req_X_W or L_err_South_req_X_W or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_W_sig_not_empty_W_grant_L_W or err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; -- FIFO S2L_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_Req_L_in or S_err_dst_addr_cur_addr_not_Req_L_in or S_err_header_not_empty_faulty_drop_packet_in or S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or S_err_header_not_empty_faulty_Req_in_all_zero or --S_err_header_not_empty_Req_L_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_Local_Req_L or S_err_Local_grant_L or S_err_South_Req_L or S_err_South_grant_L or S_err_West_Req_L or S_err_West_grant_L or S_err_East_Req_L or S_err_East_grant_L or S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_South_req_X_S or L_err_South_credit_not_zero_req_X_S_grant_S or L_err_South_credit_zero_or_not_req_X_S_not_grant_S or L_err_West_req_X_S or L_err_East_req_X_S or L_err_IDLE_req_X_S or L_err_North_req_X_S or L_err_Local_req_X_S or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Link faults and turn faults -- The order of the turns/paths from left to right (MSB to LSB) -> 20 bits -- N2E, N2W, E2N, E2S, -- W2N, W2S, S2E, S2W, -- N2S, S2N, E2W, W2E, -- L2N, L2E, L2W, L2S, -- N2L, E2L, W2L, S2L ------------------------------------------------------------------------------------------------------------------------------ -- Taking classified fault information to output ------------------------------------------------------------------------------------------------------------------------------ turn_faults <= faulty_N2E_turn_fault & faulty_N2W_turn_fault & faulty_E2N_turn_fault & faulty_E2S_turn_fault & faulty_W2N_turn_fault & faulty_W2S_turn_fault & faulty_S2E_turn_fault & faulty_S2W_turn_fault & faulty_N2S_path_fault & faulty_S2N_path_fault & faulty_E2W_path_fault & faulty_W2E_path_fault & faulty_L2N_fault & faulty_L2E_fault & faulty_L2W_fault & faulty_L2S_fault & faulty_N2L_fault & faulty_E2L_fault & faulty_W2L_fault & faulty_S2L_fault; -- 20 bits because of turn/path faults --link_faults <= '0' & '0' & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L; -- sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L; link_faults <= sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L; ------------------------------------------------------------------------------------------------------------------------------ -- Taking non-classified fault information to output ------------------------------------------------------------------------------------------------------------------------------ turn_faults_async <= N2E_turn_fault & N2W_turn_fault & E2N_turn_fault & E2S_turn_fault & W2N_turn_fault & W2S_turn_fault & S2E_turn_fault & S2W_turn_fault & N2S_path_fault & S2N_path_fault & E2W_path_fault & W2E_path_fault & L2N_fault & L2E_fault & L2W_fault & L2S_fault & N2L_fault & E2L_fault & W2L_fault & S2L_fault; -- 20 bits because of turn/path faults --link_faults_async <= '0' & '0' & faulty_packet_W & faulty_packet_S & faulty_packet_L; -- faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L; link_faults_async <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L; ------------------------------------------------------------------------------------------------------------------------------ Faulty_N_out <= sig_Faulty_N_out; Faulty_E_out <= sig_Faulty_E_out; Faulty_W_out <= sig_Faulty_W_out; Faulty_S_out <= sig_Faulty_S_out; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the counter_threshold modules CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N, Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out); CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E, Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out); CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W, Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out); CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S, Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out); CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L, Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Checker Counter Threshold modules -- Turn faults CHK_CT_N2E_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2E_turn_fault, Healthy_packet => not_N2E_turn_fault, Healthy => Healthy_N2E_turn_fault, Intermittent => intermittent_N2E_turn_fault, Faulty => faulty_N2E_turn_fault); CHK_CT_N2W_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2W_turn_fault, Healthy_packet => not_N2W_turn_fault, Healthy => Healthy_N2W_turn_fault, Intermittent => intermittent_N2W_turn_fault, Faulty => faulty_N2W_turn_fault); CHK_CT_E2N_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2N_turn_fault, Healthy_packet => not_E2N_turn_fault, Healthy => Healthy_E2N_turn_fault, Intermittent => intermittent_E2N_turn_fault, Faulty => faulty_E2N_turn_fault); CHK_CT_E2S_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2S_turn_fault, Healthy_packet => not_E2S_turn_fault, Healthy => Healthy_E2S_turn_fault, Intermittent => intermittent_E2S_turn_fault, Faulty => faulty_E2S_turn_fault); CHK_CT_W2N_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2N_turn_fault, Healthy_packet => not_W2N_turn_fault, Healthy => Healthy_W2N_turn_fault, Intermittent => intermittent_W2N_turn_fault, Faulty => faulty_W2N_turn_fault); CHK_CT_W2S_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2S_turn_fault, Healthy_packet => not_W2S_turn_fault, Healthy => Healthy_W2S_turn_fault, Intermittent => intermittent_W2S_turn_fault, Faulty => faulty_W2S_turn_fault); CHK_CT_S2E_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2E_turn_fault, Healthy_packet => not_S2E_turn_fault, Healthy => Healthy_S2E_turn_fault, Intermittent => intermittent_S2E_turn_fault, Faulty => faulty_S2E_turn_fault); CHK_CT_S2W_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2W_turn_fault, Healthy_packet => not_S2W_turn_fault, Healthy => Healthy_S2W_turn_fault, Intermittent => intermittent_S2W_turn_fault, Faulty => faulty_S2W_turn_fault); --Path faults CHK_CT_N2S_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2S_path_fault, Healthy_packet => not_N2S_path_fault, Healthy => Healthy_N2S_path_fault, Intermittent => intermittent_N2S_path_fault, Faulty => faulty_N2S_path_fault); CHK_CT_S2N_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2N_path_fault, Healthy_packet => not_S2N_path_fault, Healthy => Healthy_S2N_path_fault, Intermittent => intermittent_S2N_path_fault, Faulty => faulty_S2N_path_fault); CHK_CT_E2W_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2W_path_fault, Healthy_packet => not_E2W_path_fault, Healthy => Healthy_E2W_path_fault, Intermittent => intermittent_E2W_path_fault, Faulty => faulty_E2W_path_fault); CHK_CT_W2E_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2E_path_fault, Healthy_packet => not_W2E_path_fault, Healthy => Healthy_W2E_path_fault, Intermittent => intermittent_W2E_path_fault, Faulty => faulty_W2E_path_fault); -- Local port related faults (to/from local port) CHK_CT_L2N_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2N_fault, Healthy_packet => not_L2N_fault, Healthy => Healthy_L2N_fault, Intermittent => intermittent_L2N_fault, Faulty => faulty_L2N_fault); CHK_CT_L2E_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2E_fault, Healthy_packet => not_L2E_fault, Healthy => Healthy_L2E_fault, Intermittent => intermittent_L2E_fault, Faulty => faulty_L2E_fault); CHK_CT_L2W_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2W_fault, Healthy_packet => not_L2W_fault, Healthy => Healthy_L2W_fault, Intermittent => intermittent_L2W_fault, Faulty => faulty_L2W_fault); CHK_CT_L2S_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2S_fault, Healthy_packet => not_L2S_fault, Healthy => Healthy_L2S_fault, Intermittent => intermittent_L2S_fault, Faulty => faulty_L2S_fault); CHK_CT_N2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2L_fault, Healthy_packet => not_N2L_fault, Healthy => Healthy_N2L_fault, Intermittent => intermittent_N2L_fault, Faulty => faulty_N2L_fault); CHK_CT_E2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2L_fault, Healthy_packet => not_E2L_fault, Healthy => Healthy_E2L_fault, Intermittent => intermittent_E2L_fault, Faulty => faulty_E2L_fault); CHK_CT_W2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2L_fault, Healthy_packet => not_W2L_fault, Healthy => Healthy_W2L_fault, Intermittent => intermittent_W2L_fault, Faulty => faulty_W2L_fault); CHK_CT_S2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2L_fault, Healthy_packet => not_S2L_fault, Healthy => Healthy_S2L_fault, Intermittent => intermittent_S2L_fault, Faulty => faulty_S2L_fault); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- All the FIFOs FIFO_N: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N, read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN, credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_FIFO_to_N_FIFO, SO=> fault_DO_serial_N_FIFO_to_E_FIFO, -- Checker outputs -- Functional checkers err_empty_full => N_err_empty_full, err_empty_read_en => N_err_empty_read_en, err_full_write_en => N_err_full_write_en, err_state_in_onehot => N_err_state_in_onehot, err_read_pointer_in_onehot => N_err_read_pointer_in_onehot, err_write_pointer_in_onehot => N_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => N_err_write_en_write_pointer, err_not_write_en_write_pointer => N_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => N_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => N_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => N_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => N_err_read_pointer_write_pointer_full, err_read_pointer_increment => N_err_read_pointer_increment, err_read_pointer_not_increment => N_err_read_pointer_not_increment, err_write_en => N_err_write_en, err_not_write_en => N_err_not_write_en, err_not_write_en1 => N_err_not_write_en1, err_not_write_en2 => N_err_not_write_en2, err_read_en_mismatch => N_err_read_en_mismatch, err_read_en_mismatch1 => N_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => N_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => N_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => N_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => N_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => N_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => N_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => N_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => N_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => N_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => N_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => N_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => N_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => N_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => N_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => N_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => N_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => N_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => N_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => N_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => N_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => N_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_E: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E, read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE, credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_FIFO_to_E_FIFO, SO=> fault_DO_serial_E_FIFO_to_W_FIFO, -- Checker outputs -- Functional checkers err_empty_full => E_err_empty_full, err_empty_read_en => E_err_empty_read_en, err_full_write_en => E_err_full_write_en, err_state_in_onehot => E_err_state_in_onehot, err_read_pointer_in_onehot => E_err_read_pointer_in_onehot, err_write_pointer_in_onehot => E_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => E_err_write_en_write_pointer, err_not_write_en_write_pointer => E_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => E_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => E_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => E_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => E_err_read_pointer_write_pointer_full, err_read_pointer_increment => E_err_read_pointer_increment, err_read_pointer_not_increment => E_err_read_pointer_not_increment, err_write_en => E_err_write_en, err_not_write_en => E_err_not_write_en, err_not_write_en1 => E_err_not_write_en1, err_not_write_en2 => E_err_not_write_en2, err_read_en_mismatch => E_err_read_en_mismatch, err_read_en_mismatch1 => E_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => E_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => E_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => E_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => E_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => E_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => E_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => E_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => E_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => E_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => E_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => E_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => E_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => E_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => E_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => E_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => E_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => E_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => E_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => E_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => E_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_W: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W, read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW, credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_FIFO_to_W_FIFO, SO=> fault_DO_serial_W_FIFO_to_S_FIFO, -- Checker outputs -- Functional checkers err_empty_full => W_err_empty_full, err_empty_read_en => W_err_empty_read_en, err_full_write_en => W_err_full_write_en, err_state_in_onehot => W_err_state_in_onehot, err_read_pointer_in_onehot => W_err_read_pointer_in_onehot, err_write_pointer_in_onehot => W_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => W_err_write_en_write_pointer, err_not_write_en_write_pointer => W_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => W_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => W_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => W_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => W_err_read_pointer_write_pointer_full, err_read_pointer_increment => W_err_read_pointer_increment, err_read_pointer_not_increment => W_err_read_pointer_not_increment, err_write_en => W_err_write_en, err_not_write_en => W_err_not_write_en, err_not_write_en1 => W_err_not_write_en1, err_not_write_en2 => W_err_not_write_en2, err_read_en_mismatch => W_err_read_en_mismatch, err_read_en_mismatch1 => W_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => W_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => W_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => W_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => W_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => W_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => W_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => W_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => W_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => W_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => W_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => W_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => W_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => W_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => W_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => W_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => W_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => W_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => W_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => W_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => W_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_S: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S, read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS, credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_FIFO_to_S_FIFO, SO=> fault_DO_serial_S_FIFO_to_L_LBDR, -- Checker outputs -- Functional checkers err_empty_full => S_err_empty_full, err_empty_read_en => S_err_empty_read_en, err_full_write_en => S_err_full_write_en, err_state_in_onehot => S_err_state_in_onehot, err_read_pointer_in_onehot => S_err_read_pointer_in_onehot, err_write_pointer_in_onehot => S_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => S_err_write_en_write_pointer, err_not_write_en_write_pointer => S_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => S_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => S_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => S_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => S_err_read_pointer_write_pointer_full, err_read_pointer_increment => S_err_read_pointer_increment, err_read_pointer_not_increment => S_err_read_pointer_not_increment, err_write_en => S_err_write_en, err_not_write_en => S_err_not_write_en, err_not_write_en1 => S_err_not_write_en1, err_not_write_en2 => S_err_not_write_en2, err_read_en_mismatch => S_err_read_en_mismatch, err_read_en_mismatch1 => S_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => S_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => S_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => S_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => S_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => S_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => S_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => S_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => S_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => S_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => S_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => S_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => S_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => S_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => S_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => S_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => S_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => S_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => S_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => S_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => S_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_L: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L, read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L, credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L, TCK=> TCK, SE=> SE, UE=> UE, SI=> SI, SO=> fault_DO_serial_L_FIFO_to_N_FIFO, -- Checker outputs -- Functional checkers err_empty_full => L_err_empty_full, err_empty_read_en => L_err_empty_read_en, err_full_write_en => L_err_full_write_en, err_state_in_onehot => L_err_state_in_onehot, err_read_pointer_in_onehot => L_err_read_pointer_in_onehot, err_write_pointer_in_onehot => L_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => L_err_write_en_write_pointer, err_not_write_en_write_pointer => L_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => L_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => L_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => L_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => L_err_read_pointer_write_pointer_full, err_read_pointer_increment => L_err_read_pointer_increment, err_read_pointer_not_increment => L_err_read_pointer_not_increment, err_write_en => L_err_write_en, err_not_write_en => L_err_not_write_en, err_not_write_en1 => L_err_not_write_en1, err_not_write_en2 => L_err_not_write_en2, err_read_en_mismatch => L_err_read_en_mismatch, err_read_en_mismatch1 => L_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => L_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => L_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => L_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => L_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => L_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => L_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => L_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => L_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => L_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => L_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => L_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => L_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => L_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => L_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => L_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => L_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => L_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => L_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => L_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => L_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ parity_LBDR_N: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_N, empty_N, LBDR_Fault_N); parity_LBDR_E: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_E, empty_E, LBDR_Fault_E); parity_LBDR_W: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_W, empty_W, LBDR_Fault_W); parity_LBDR_S: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_S, empty_S, LBDR_Fault_S); parity_LBDR_L: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_L, empty_L, LBDR_Fault_L); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ --- all the LBDRs LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_N, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_N, packet_drop_order => packet_drop_order_N, grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN, Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_LBDR_to_N_LBDR, SO=> fault_DO_serial_N_LBDR_to_E_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => N_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => N_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => N_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => N_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => N_err_grants_onehot, err_grants_mismatch => N_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => N_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => N_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => N_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => N_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => N_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => N_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => N_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => N_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => N_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => N_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => N_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => N_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => N_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => N_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => N_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => N_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => N_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => N_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => N_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => N_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => N_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_E, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_E, packet_drop_order => packet_drop_order_E, grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE, Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_LBDR_to_E_LBDR, SO=> fault_DO_serial_E_LBDR_to_W_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => E_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => E_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => E_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => E_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => E_err_grants_onehot, err_grants_mismatch => E_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => E_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => E_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => E_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => E_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => E_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => E_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => E_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => E_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => E_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => E_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => E_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => E_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => E_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => E_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => E_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => E_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => E_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => E_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => E_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_W, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_W, packet_drop_order => packet_drop_order_W, grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW, Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_LBDR_to_W_LBDR, SO=> fault_DO_serial_W_LBDR_to_S_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => W_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => W_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => W_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => W_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => W_err_grants_onehot, err_grants_mismatch => W_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => W_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => W_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => W_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => W_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => W_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => W_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => W_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => W_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => W_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => W_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => W_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => W_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => W_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => W_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => W_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => W_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => W_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => W_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => W_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_S, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_S, packet_drop_order => packet_drop_order_S, grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS, Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_LBDR_to_S_LBDR, SO=> fault_DO_serial_S_LBDR_to_Allocator, -- Checker outputs err_header_empty_Requests_FF_Requests_in => S_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => S_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => S_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => S_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => S_err_grants_onehot, err_grants_mismatch => S_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => S_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => S_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => S_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => S_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => S_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => S_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => S_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => S_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => S_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => S_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => S_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => S_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => S_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => S_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => S_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => S_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => S_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => S_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => S_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_L, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_L, packet_drop_order => packet_drop_order_L, grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0', Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_FIFO_to_L_LBDR, SO=> fault_DO_serial_L_LBDR_to_N_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => L_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => L_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => L_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => L_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => L_err_grants_onehot, err_grants_mismatch => L_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => L_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => L_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => L_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => L_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => L_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => L_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => L_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => L_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => L_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => L_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => L_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => L_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => L_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => L_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => L_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => L_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => L_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => L_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => L_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- switch allocator allocator_unit: allocator port map ( reset => reset, clk => clk, -- flow control credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L, -- requests from the LBDRS req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL, req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL, req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL, req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL, req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0', empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L, valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L, -- grant_X_Y means the grant for X output port towards Y input port -- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot! grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL, grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL, grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL, grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL, grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_LBDR_to_Allocator, SO=> SO, -- Make sure this is correction -- Also check inside Allocator's logic -- Checker outputs -- Allocator logic checker outputs err_grant_N_N_sig_not_empty_N_grant_N_N => err_grant_N_N_sig_not_empty_N_grant_N_N , err_not_grant_N_N_sig_or_empty_N_not_grant_N_N => err_not_grant_N_N_sig_or_empty_N_not_grant_N_N , err_grant_N_E_sig_not_empty_E_grant_N_E => err_grant_N_E_sig_not_empty_E_grant_N_E , err_not_grant_N_E_sig_or_empty_E_not_grant_N_E => err_not_grant_N_E_sig_or_empty_E_not_grant_N_E , err_grant_N_W_sig_not_empty_W_grant_N_W => err_grant_N_W_sig_not_empty_W_grant_N_W , err_not_grant_N_W_sig_or_empty_W_not_grant_N_W => err_not_grant_N_W_sig_or_empty_W_not_grant_N_W , err_grant_N_S_sig_not_empty_S_grant_N_S => err_grant_N_S_sig_not_empty_S_grant_N_S , err_not_grant_N_S_sig_or_empty_S_not_grant_N_S => err_not_grant_N_S_sig_or_empty_S_not_grant_N_S , err_grant_N_L_sig_not_empty_L_grant_N_L => err_grant_N_L_sig_not_empty_L_grant_N_L , err_not_grant_N_L_sig_or_empty_L_not_grant_N_L => err_not_grant_N_L_sig_or_empty_L_not_grant_N_L , err_grant_E_N_sig_not_empty_N_grant_E_N => err_grant_E_N_sig_not_empty_N_grant_E_N , err_not_grant_E_N_sig_or_empty_N_not_grant_E_N => err_not_grant_E_N_sig_or_empty_N_not_grant_E_N , err_grant_E_E_sig_not_empty_E_grant_E_E => err_grant_E_E_sig_not_empty_E_grant_E_E , err_not_grant_E_E_sig_or_empty_E_not_grant_E_E => err_not_grant_E_E_sig_or_empty_E_not_grant_E_E , err_grant_E_W_sig_not_empty_W_grant_E_W => err_grant_E_W_sig_not_empty_W_grant_E_W , err_not_grant_E_W_sig_or_empty_W_not_grant_E_W => err_not_grant_E_W_sig_or_empty_W_not_grant_E_W , err_grant_E_S_sig_not_empty_S_grant_E_S => err_grant_E_S_sig_not_empty_S_grant_E_S , err_not_grant_E_S_sig_or_empty_S_not_grant_E_S => err_not_grant_E_S_sig_or_empty_S_not_grant_E_S , err_grant_E_L_sig_not_empty_L_grant_E_L => err_grant_E_L_sig_not_empty_L_grant_E_L , err_not_grant_E_L_sig_or_empty_L_not_grant_E_L => err_not_grant_E_L_sig_or_empty_L_not_grant_E_L , err_grant_W_N_sig_not_empty_N_grant_W_N => err_grant_W_N_sig_not_empty_N_grant_W_N , err_not_grant_W_N_sig_or_empty_N_not_grant_W_N => err_not_grant_W_N_sig_or_empty_N_not_grant_W_N , err_grant_W_E_sig_not_empty_E_grant_W_E => err_grant_W_E_sig_not_empty_E_grant_W_E , err_not_grant_W_E_sig_or_empty_E_not_grant_W_E => err_not_grant_W_E_sig_or_empty_E_not_grant_W_E , err_grant_W_W_sig_not_empty_W_grant_W_W => err_grant_W_W_sig_not_empty_W_grant_W_W , err_not_grant_W_W_sig_or_empty_W_not_grant_W_W => err_not_grant_W_W_sig_or_empty_W_not_grant_W_W , err_grant_W_S_sig_not_empty_S_grant_W_S => err_grant_W_S_sig_not_empty_S_grant_W_S , err_not_grant_W_S_sig_or_empty_S_not_grant_W_S => err_not_grant_W_S_sig_or_empty_S_not_grant_W_S , err_grant_W_L_sig_not_empty_L_grant_W_L => err_grant_W_L_sig_not_empty_L_grant_W_L , err_not_grant_W_L_sig_or_empty_L_not_grant_W_L => err_not_grant_W_L_sig_or_empty_L_not_grant_W_L , err_grant_S_N_sig_not_empty_N_grant_S_N => err_grant_S_N_sig_not_empty_N_grant_S_N , err_not_grant_S_N_sig_or_empty_N_not_grant_S_N => err_not_grant_S_N_sig_or_empty_N_not_grant_S_N , err_grant_S_E_sig_not_empty_E_grant_S_E => err_grant_S_E_sig_not_empty_E_grant_S_E , err_not_grant_S_E_sig_or_empty_E_not_grant_S_E => err_not_grant_S_E_sig_or_empty_E_not_grant_S_E , err_grant_S_W_sig_not_empty_W_grant_S_W => err_grant_S_W_sig_not_empty_W_grant_S_W , err_not_grant_S_W_sig_or_empty_W_not_grant_S_W => err_not_grant_S_W_sig_or_empty_W_not_grant_S_W , err_grant_S_S_sig_not_empty_S_grant_S_S => err_grant_S_S_sig_not_empty_S_grant_S_S , err_not_grant_S_S_sig_or_empty_S_not_grant_S_S => err_not_grant_S_S_sig_or_empty_S_not_grant_S_S , err_grant_S_L_sig_not_empty_L_grant_S_L => err_grant_S_L_sig_not_empty_L_grant_S_L , err_not_grant_S_L_sig_or_empty_L_not_grant_S_L => err_not_grant_S_L_sig_or_empty_L_not_grant_S_L , err_grant_L_N_sig_not_empty_N_grant_L_N => err_grant_L_N_sig_not_empty_N_grant_L_N , err_not_grant_L_N_sig_or_empty_N_not_grant_L_N => err_not_grant_L_N_sig_or_empty_N_not_grant_L_N , err_grant_L_E_sig_not_empty_E_grant_L_E => err_grant_L_E_sig_not_empty_E_grant_L_E , err_not_grant_L_E_sig_or_empty_E_not_grant_L_E => err_not_grant_L_E_sig_or_empty_E_not_grant_L_E , err_grant_L_W_sig_not_empty_W_grant_L_W => err_grant_L_W_sig_not_empty_W_grant_L_W , err_not_grant_L_W_sig_or_empty_W_not_grant_L_W => err_not_grant_L_W_sig_or_empty_W_not_grant_L_W , err_grant_L_S_sig_not_empty_S_grant_L_S => err_grant_L_S_sig_not_empty_S_grant_L_S , err_not_grant_L_S_sig_or_empty_S_not_grant_L_S => err_not_grant_L_S_sig_or_empty_S_not_grant_L_S , err_grant_L_L_sig_not_empty_L_grant_L_L => err_grant_L_L_sig_not_empty_L_grant_L_L , err_not_grant_L_L_sig_or_empty_L_not_grant_L_L => err_not_grant_L_L_sig_or_empty_L_not_grant_L_L , err_grant_signals_not_empty_grant_N => err_grant_signals_not_empty_grant_N , err_not_grant_signals_empty_not_grant_N => err_not_grant_signals_empty_not_grant_N , err_grant_signals_not_empty_grant_E => err_grant_signals_not_empty_grant_E , err_not_grant_signals_empty_not_grant_E => err_not_grant_signals_empty_not_grant_E , err_grant_signals_not_empty_grant_W => err_grant_signals_not_empty_grant_W , err_not_grant_signals_empty_not_grant_W => err_not_grant_signals_empty_not_grant_W , err_grant_signals_not_empty_grant_S => err_grant_signals_not_empty_grant_S , err_not_grant_signals_empty_not_grant_S => err_not_grant_signals_empty_not_grant_S , err_grant_signals_not_empty_grant_L => err_grant_signals_not_empty_grant_L , err_not_grant_signals_empty_not_grant_L => err_not_grant_signals_empty_not_grant_L , err_grants_valid_not_match => err_grants_valid_not_match , -- Allocator credit counter logic checker outputs err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal , err_credit_in_N_credit_counter_N_out_increment => err_credit_in_N_credit_counter_N_out_increment , err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change => err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change , err_grant_N_credit_counter_N_out_decrement => err_grant_N_credit_counter_N_out_decrement , err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change => err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change , err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal , err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal , err_credit_in_E_credit_counter_E_out_increment => err_credit_in_E_credit_counter_E_out_increment , err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change => err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change , err_grant_E_credit_counter_E_out_decrement => err_grant_E_credit_counter_E_out_decrement , err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change => err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change , err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal , err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal , err_credit_in_W_credit_counter_W_out_increment => err_credit_in_W_credit_counter_W_out_increment , err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change => err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change , err_grant_W_credit_counter_W_out_decrement => err_grant_W_credit_counter_W_out_decrement , err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change => err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change , err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal , err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal , err_credit_in_S_credit_counter_S_out_increment => err_credit_in_S_credit_counter_S_out_increment , err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change => err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change , err_grant_S_credit_counter_S_out_decrement => err_grant_S_credit_counter_S_out_decrement , err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change => err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change , err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal , err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal , err_credit_in_L_credit_counter_L_out_increment => err_credit_in_L_credit_counter_L_out_increment , err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change => err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change , err_grant_L_credit_counter_L_out_decrement => err_grant_L_credit_counter_L_out_decrement , err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change => err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change , err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal , -- North Arbiter_in Checker outputs N_err_Requests_state_in_state_not_equal => N_err_Requests_state_in_state_not_equal, N_err_IDLE_Req_N => N_err_IDLE_Req_N, N_err_IDLE_grant_N => N_err_IDLE_grant_N, N_err_North_Req_N => N_err_North_Req_N, N_err_North_grant_N => N_err_North_grant_N, N_err_East_Req_E => N_err_East_Req_E, N_err_East_grant_E => N_err_East_grant_E, N_err_West_Req_W => N_err_West_Req_W, N_err_West_grant_W => N_err_West_grant_W, N_err_South_Req_S => N_err_South_Req_S, N_err_South_grant_S => N_err_South_grant_S, N_err_Local_Req_L => N_err_Local_Req_L, N_err_Local_grant_L => N_err_Local_grant_L, N_err_IDLE_Req_E => N_err_IDLE_Req_E, N_err_IDLE_grant_E => N_err_IDLE_grant_E, N_err_North_Req_E => N_err_North_Req_E, N_err_North_grant_E => N_err_North_grant_E, N_err_East_Req_W => N_err_East_Req_W, N_err_East_grant_W => N_err_East_grant_W, N_err_West_Req_S => N_err_West_Req_S, N_err_West_grant_S => N_err_West_grant_S, N_err_South_Req_L => N_err_South_Req_L, N_err_South_grant_L => N_err_South_grant_L, N_err_Local_Req_N => N_err_Local_Req_N, N_err_Local_grant_N => N_err_Local_grant_N, N_err_IDLE_Req_W => N_err_IDLE_Req_W, N_err_IDLE_grant_W => N_err_IDLE_grant_W, N_err_North_Req_W => N_err_North_Req_W, N_err_North_grant_W => N_err_North_grant_W, N_err_East_Req_S => N_err_East_Req_S, N_err_East_grant_S => N_err_East_grant_S, N_err_West_Req_L => N_err_West_Req_L, N_err_West_grant_L => N_err_West_grant_L, N_err_South_Req_N => N_err_South_Req_N, N_err_South_grant_N => N_err_South_grant_N, N_err_Local_Req_E => N_err_Local_Req_E, N_err_Local_grant_E => N_err_Local_grant_E, N_err_IDLE_Req_S => N_err_IDLE_Req_S, N_err_IDLE_grant_S => N_err_IDLE_grant_S, N_err_North_Req_S => N_err_North_Req_S, N_err_North_grant_S => N_err_North_grant_S, N_err_East_Req_L => N_err_East_Req_L, N_err_East_grant_L => N_err_East_grant_L, N_err_West_Req_N => N_err_West_Req_N, N_err_West_grant_N => N_err_West_grant_N, N_err_South_Req_E => N_err_South_Req_E, N_err_South_grant_E => N_err_South_grant_E, N_err_Local_Req_W => N_err_Local_Req_W, N_err_Local_grant_W => N_err_Local_grant_W, N_err_IDLE_Req_L => N_err_IDLE_Req_L, N_err_IDLE_grant_L => N_err_IDLE_grant_L, N_err_North_Req_L => N_err_North_Req_L, N_err_North_grant_L => N_err_North_grant_L, N_err_East_Req_N => N_err_East_Req_N, N_err_East_grant_N => N_err_East_grant_N, N_err_West_Req_E => N_err_West_Req_E, N_err_West_grant_E => N_err_West_grant_E, N_err_South_Req_W => N_err_South_Req_W, N_err_South_grant_W => N_err_South_grant_W, N_err_Local_Req_S => N_err_Local_Req_S, N_err_Local_grant_S => N_err_Local_grant_S, N_err_state_in_onehot => N_err_arbiter_state_in_onehot, N_err_no_request_grants => N_err_no_request_grants, N_err_request_no_grants => N_err_request_no_grants, N_err_no_Req_N_grant_N => N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E => N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W => N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S => N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L => N_err_no_Req_L_grant_L, -- East Arbiter_in Checker outputs E_err_Requests_state_in_state_not_equal => E_err_Requests_state_in_state_not_equal, E_err_IDLE_Req_N => E_err_IDLE_Req_N, E_err_IDLE_grant_N => E_err_IDLE_grant_N, E_err_North_Req_N => E_err_North_Req_N, E_err_North_grant_N => E_err_North_grant_N, E_err_East_Req_E => E_err_East_Req_E, E_err_East_grant_E => E_err_East_grant_E, E_err_West_Req_W => E_err_West_Req_W, E_err_West_grant_W => E_err_West_grant_W, E_err_South_Req_S => E_err_South_Req_S, E_err_South_grant_S => E_err_South_grant_S, E_err_Local_Req_L => E_err_Local_Req_L, E_err_Local_grant_L => E_err_Local_grant_L, E_err_IDLE_Req_E => E_err_IDLE_Req_E, E_err_IDLE_grant_E => E_err_IDLE_grant_E, E_err_North_Req_E => E_err_North_Req_E, E_err_North_grant_E => E_err_North_grant_E, E_err_East_Req_W => E_err_East_Req_W, E_err_East_grant_W => E_err_East_grant_W, E_err_West_Req_S => E_err_West_Req_S, E_err_West_grant_S => E_err_West_grant_S, E_err_South_Req_L => E_err_South_Req_L, E_err_South_grant_L => E_err_South_grant_L, E_err_Local_Req_N => E_err_Local_Req_N, E_err_Local_grant_N => E_err_Local_grant_N, E_err_IDLE_Req_W => E_err_IDLE_Req_W, E_err_IDLE_grant_W => E_err_IDLE_grant_W, E_err_North_Req_W => E_err_North_Req_W, E_err_North_grant_W => E_err_North_grant_W, E_err_East_Req_S => E_err_East_Req_S, E_err_East_grant_S => E_err_East_grant_S, E_err_West_Req_L => E_err_West_Req_L, E_err_West_grant_L => E_err_West_grant_L, E_err_South_Req_N => E_err_South_Req_N, E_err_South_grant_N => E_err_South_grant_N, E_err_Local_Req_E => E_err_Local_Req_E, E_err_Local_grant_E => E_err_Local_grant_E, E_err_IDLE_Req_S => E_err_IDLE_Req_S, E_err_IDLE_grant_S => E_err_IDLE_grant_S, E_err_North_Req_S => E_err_North_Req_S, E_err_North_grant_S => E_err_North_grant_S, E_err_East_Req_L => E_err_East_Req_L, E_err_East_grant_L => E_err_East_grant_L, E_err_West_Req_N => E_err_West_Req_N, E_err_West_grant_N => E_err_West_grant_N, E_err_South_Req_E => E_err_South_Req_E, E_err_South_grant_E => E_err_South_grant_E, E_err_Local_Req_W => E_err_Local_Req_W, E_err_Local_grant_W => E_err_Local_grant_W, E_err_IDLE_Req_L => E_err_IDLE_Req_L, E_err_IDLE_grant_L => E_err_IDLE_grant_L, E_err_North_Req_L => E_err_North_Req_L, E_err_North_grant_L => E_err_North_grant_L, E_err_East_Req_N => E_err_East_Req_N, E_err_East_grant_N => E_err_East_grant_N, E_err_West_Req_E => E_err_West_Req_E, E_err_West_grant_E => E_err_West_grant_E, E_err_South_Req_W => E_err_South_Req_W, E_err_South_grant_W => E_err_South_grant_W, E_err_Local_Req_S => E_err_Local_Req_S, E_err_Local_grant_S => E_err_Local_grant_S, E_err_state_in_onehot => E_err_arbiter_state_in_onehot, E_err_no_request_grants => E_err_no_request_grants, E_err_request_no_grants => E_err_request_no_grants, E_err_no_Req_N_grant_N => E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E => E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W => E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S => E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L => E_err_no_Req_L_grant_L, -- West Arbiter_in Checker outputs W_err_Requests_state_in_state_not_equal => W_err_Requests_state_in_state_not_equal, W_err_IDLE_Req_N => W_err_IDLE_Req_N, W_err_IDLE_grant_N => W_err_IDLE_grant_N, W_err_North_Req_N => W_err_North_Req_N, W_err_North_grant_N => W_err_North_grant_N, W_err_East_Req_E => W_err_East_Req_E, W_err_East_grant_E => W_err_East_grant_E, W_err_West_Req_W => W_err_West_Req_W, W_err_West_grant_W => W_err_West_grant_W, W_err_South_Req_S => W_err_South_Req_S, W_err_South_grant_S => W_err_South_grant_S, W_err_Local_Req_L => W_err_Local_Req_L, W_err_Local_grant_L => W_err_Local_grant_L, W_err_IDLE_Req_E => W_err_IDLE_Req_E, W_err_IDLE_grant_E => W_err_IDLE_grant_E, W_err_North_Req_E => W_err_North_Req_E, W_err_North_grant_E => W_err_North_grant_E, W_err_East_Req_W => W_err_East_Req_W, W_err_East_grant_W => W_err_East_grant_W, W_err_West_Req_S => W_err_West_Req_S, W_err_West_grant_S => W_err_West_grant_S, W_err_South_Req_L => W_err_South_Req_L, W_err_South_grant_L => W_err_South_grant_L, W_err_Local_Req_N => W_err_Local_Req_N, W_err_Local_grant_N => W_err_Local_grant_N, W_err_IDLE_Req_W => W_err_IDLE_Req_W, W_err_IDLE_grant_W => W_err_IDLE_grant_W, W_err_North_Req_W => W_err_North_Req_W, W_err_North_grant_W => W_err_North_grant_W, W_err_East_Req_S => W_err_East_Req_S, W_err_East_grant_S => W_err_East_grant_S, W_err_West_Req_L => W_err_West_Req_L, W_err_West_grant_L => W_err_West_grant_L, W_err_South_Req_N => W_err_South_Req_N, W_err_South_grant_N => W_err_South_grant_N, W_err_Local_Req_E => W_err_Local_Req_E, W_err_Local_grant_E => W_err_Local_grant_E, W_err_IDLE_Req_S => W_err_IDLE_Req_S, W_err_IDLE_grant_S => W_err_IDLE_grant_S, W_err_North_Req_S => W_err_North_Req_S, W_err_North_grant_S => W_err_North_grant_S, W_err_East_Req_L => W_err_East_Req_L, W_err_East_grant_L => W_err_East_grant_L, W_err_West_Req_N => W_err_West_Req_N, W_err_West_grant_N => W_err_West_grant_N, W_err_South_Req_E => W_err_South_Req_E, W_err_South_grant_E => W_err_South_grant_E, W_err_Local_Req_W => W_err_Local_Req_W, W_err_Local_grant_W => W_err_Local_grant_W, W_err_IDLE_Req_L => W_err_IDLE_Req_L, W_err_IDLE_grant_L => W_err_IDLE_grant_L, W_err_North_Req_L => W_err_North_Req_L, W_err_North_grant_L => W_err_North_grant_L, W_err_East_Req_N => W_err_East_Req_N, W_err_East_grant_N => W_err_East_grant_N, W_err_West_Req_E => W_err_West_Req_E, W_err_West_grant_E => W_err_West_grant_E, W_err_South_Req_W => W_err_South_Req_W, W_err_South_grant_W => W_err_South_grant_W, W_err_Local_Req_S => W_err_Local_Req_S, W_err_Local_grant_S => W_err_Local_grant_S, W_err_state_in_onehot => W_err_arbiter_state_in_onehot, W_err_no_request_grants => W_err_no_request_grants, W_err_request_no_grants => W_err_request_no_grants, W_err_no_Req_N_grant_N => W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E => W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W => W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S => W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L => W_err_no_Req_L_grant_L, -- South Arbiter_in Checker outputs S_err_Requests_state_in_state_not_equal => S_err_Requests_state_in_state_not_equal, S_err_IDLE_Req_N => S_err_IDLE_Req_N, S_err_IDLE_grant_N => S_err_IDLE_grant_N, S_err_North_Req_N => S_err_North_Req_N, S_err_North_grant_N => S_err_North_grant_N, S_err_East_Req_E => S_err_East_Req_E, S_err_East_grant_E => S_err_East_grant_E, S_err_West_Req_W => S_err_West_Req_W, S_err_West_grant_W => S_err_West_grant_W, S_err_South_Req_S => S_err_South_Req_S, S_err_South_grant_S => S_err_South_grant_S, S_err_Local_Req_L => S_err_Local_Req_L, S_err_Local_grant_L => S_err_Local_grant_L, S_err_IDLE_Req_E => S_err_IDLE_Req_E, S_err_IDLE_grant_E => S_err_IDLE_grant_E, S_err_North_Req_E => S_err_North_Req_E, S_err_North_grant_E => S_err_North_grant_E, S_err_East_Req_W => S_err_East_Req_W, S_err_East_grant_W => S_err_East_grant_W, S_err_West_Req_S => S_err_West_Req_S, S_err_West_grant_S => S_err_West_grant_S, S_err_South_Req_L => S_err_South_Req_L, S_err_South_grant_L => S_err_South_grant_L, S_err_Local_Req_N => S_err_Local_Req_N, S_err_Local_grant_N => S_err_Local_grant_N, S_err_IDLE_Req_W => S_err_IDLE_Req_W, S_err_IDLE_grant_W => S_err_IDLE_grant_W, S_err_North_Req_W => S_err_North_Req_W, S_err_North_grant_W => S_err_North_grant_W, S_err_East_Req_S => S_err_East_Req_S, S_err_East_grant_S => S_err_East_grant_S, S_err_West_Req_L => S_err_West_Req_L, S_err_West_grant_L => S_err_West_grant_L, S_err_South_Req_N => S_err_South_Req_N, S_err_South_grant_N => S_err_South_grant_N, S_err_Local_Req_E => S_err_Local_Req_E, S_err_Local_grant_E => S_err_Local_grant_E, S_err_IDLE_Req_S => S_err_IDLE_Req_S, S_err_IDLE_grant_S => S_err_IDLE_grant_S, S_err_North_Req_S => S_err_North_Req_S, S_err_North_grant_S => S_err_North_grant_S, S_err_East_Req_L => S_err_East_Req_L, S_err_East_grant_L => S_err_East_grant_L, S_err_West_Req_N => S_err_West_Req_N, S_err_West_grant_N => S_err_West_grant_N, S_err_South_Req_E => S_err_South_Req_E, S_err_South_grant_E => S_err_South_grant_E, S_err_Local_Req_W => S_err_Local_Req_W, S_err_Local_grant_W => S_err_Local_grant_W, S_err_IDLE_Req_L => S_err_IDLE_Req_L, S_err_IDLE_grant_L => S_err_IDLE_grant_L, S_err_North_Req_L => S_err_North_Req_L, S_err_North_grant_L => S_err_North_grant_L, S_err_East_Req_N => S_err_East_Req_N, S_err_East_grant_N => S_err_East_grant_N, S_err_West_Req_E => S_err_West_Req_E, S_err_West_grant_E => S_err_West_grant_E, S_err_South_Req_W => S_err_South_Req_W, S_err_South_grant_W => S_err_South_grant_W, S_err_Local_Req_S => S_err_Local_Req_S, S_err_Local_grant_S => S_err_Local_grant_S, S_err_state_in_onehot => S_err_arbiter_state_in_onehot, S_err_no_request_grants => S_err_no_request_grants, S_err_request_no_grants => S_err_request_no_grants, S_err_no_Req_N_grant_N => S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E => S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W => S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S => S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L => S_err_no_Req_L_grant_L, -- Local Arbiter_in Checker outputs L_err_Requests_state_in_state_not_equal => L_err_Requests_state_in_state_not_equal, L_err_IDLE_Req_N => L_err_IDLE_Req_N, L_err_IDLE_grant_N => L_err_IDLE_grant_N, L_err_North_Req_N => L_err_North_Req_N, L_err_North_grant_N => L_err_North_grant_N, L_err_East_Req_E => L_err_East_Req_E, L_err_East_grant_E => L_err_East_grant_E, L_err_West_Req_W => L_err_West_Req_W, L_err_West_grant_W => L_err_West_grant_W, L_err_South_Req_S => L_err_South_Req_S, L_err_South_grant_S => L_err_South_grant_S, L_err_Local_Req_L => L_err_Local_Req_L, L_err_Local_grant_L => L_err_Local_grant_L, L_err_IDLE_Req_E => L_err_IDLE_Req_E, L_err_IDLE_grant_E => L_err_IDLE_grant_E, L_err_North_Req_E => L_err_North_Req_E, L_err_North_grant_E => L_err_North_grant_E, L_err_East_Req_W => L_err_East_Req_W, L_err_East_grant_W => L_err_East_grant_W, L_err_West_Req_S => L_err_West_Req_S, L_err_West_grant_S => L_err_West_grant_S, L_err_South_Req_L => L_err_South_Req_L, L_err_South_grant_L => L_err_South_grant_L, L_err_Local_Req_N => L_err_Local_Req_N, L_err_Local_grant_N => L_err_Local_grant_N, L_err_IDLE_Req_W => L_err_IDLE_Req_W, L_err_IDLE_grant_W => L_err_IDLE_grant_W, L_err_North_Req_W => L_err_North_Req_W, L_err_North_grant_W => L_err_North_grant_W, L_err_East_Req_S => L_err_East_Req_S, L_err_East_grant_S => L_err_East_grant_S, L_err_West_Req_L => L_err_West_Req_L, L_err_West_grant_L => L_err_West_grant_L, L_err_South_Req_N => L_err_South_Req_N, L_err_South_grant_N => L_err_South_grant_N, L_err_Local_Req_E => L_err_Local_Req_E, L_err_Local_grant_E => L_err_Local_grant_E, L_err_IDLE_Req_S => L_err_IDLE_Req_S, L_err_IDLE_grant_S => L_err_IDLE_grant_S, L_err_North_Req_S => L_err_North_Req_S, L_err_North_grant_S => L_err_North_grant_S, L_err_East_Req_L => L_err_East_Req_L, L_err_East_grant_L => L_err_East_grant_L, L_err_West_Req_N => L_err_West_Req_N, L_err_West_grant_N => L_err_West_grant_N, L_err_South_Req_E => L_err_South_Req_E, L_err_South_grant_E => L_err_South_grant_E, L_err_Local_Req_W => L_err_Local_Req_W, L_err_Local_grant_W => L_err_Local_grant_W, L_err_IDLE_Req_L => L_err_IDLE_Req_L, L_err_IDLE_grant_L => L_err_IDLE_grant_L, L_err_North_Req_L => L_err_North_Req_L, L_err_North_grant_L => L_err_North_grant_L, L_err_East_Req_N => L_err_East_Req_N, L_err_East_grant_N => L_err_East_grant_N, L_err_West_Req_E => L_err_West_Req_E, L_err_West_grant_E => L_err_West_grant_E, L_err_South_Req_W => L_err_South_Req_W, L_err_South_grant_W => L_err_South_grant_W, L_err_Local_Req_S => L_err_Local_Req_S, L_err_Local_grant_S => L_err_Local_grant_S, L_err_state_in_onehot => L_err_arbiter_state_in_onehot, L_err_no_request_grants => L_err_no_request_grants, L_err_request_no_grants => L_err_request_no_grants, L_err_no_Req_N_grant_N => L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E => L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W => L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S => L_err_no_Req_S_grant_S, L_err_no_Req_L_grant_L => L_err_no_Req_L_grant_L, -- Arbiter_out checker outputs -- North Arbiter_out checker outputs N_arbiter_out_err_Requests_state_in_state_not_equal => N_arbiter_out_err_Requests_state_in_state_not_equal, N_err_IDLE_req_X_N => N_err_IDLE_req_X_N, N_err_North_req_X_N => N_err_North_req_X_N, N_err_North_credit_not_zero_req_X_N_grant_N => N_err_North_credit_not_zero_req_X_N_grant_N, N_err_North_credit_zero_or_not_req_X_N_not_grant_N => N_err_North_credit_zero_or_not_req_X_N_not_grant_N, N_err_East_req_X_E => N_err_East_req_X_E, N_err_East_credit_not_zero_req_X_E_grant_E => N_err_East_credit_not_zero_req_X_E_grant_E, N_err_East_credit_zero_or_not_req_X_E_not_grant_E => N_err_East_credit_zero_or_not_req_X_E_not_grant_E, N_err_West_req_X_W => N_err_West_req_X_W, N_err_West_credit_not_zero_req_X_W_grant_W => N_err_West_credit_not_zero_req_X_W_grant_W, N_err_West_credit_zero_or_not_req_X_W_not_grant_W => N_err_West_credit_zero_or_not_req_X_W_not_grant_W, N_err_South_req_X_S => N_err_South_req_X_S, N_err_South_credit_not_zero_req_X_S_grant_S => N_err_South_credit_not_zero_req_X_S_grant_S, N_err_South_credit_zero_or_not_req_X_S_not_grant_S => N_err_South_credit_zero_or_not_req_X_S_not_grant_S, N_err_Local_req_X_L => N_err_Local_req_X_L, N_err_Local_credit_not_zero_req_X_L_grant_L => N_err_Local_credit_not_zero_req_X_L_grant_L, N_err_Local_credit_zero_or_not_req_X_L_not_grant_L => N_err_Local_credit_zero_or_not_req_X_L_not_grant_L, N_err_IDLE_req_X_E => N_err_IDLE_req_X_E, N_err_North_req_X_E => N_err_North_req_X_E, N_err_East_req_X_W => N_err_East_req_X_W, N_err_West_req_X_S => N_err_West_req_X_S, N_err_South_req_X_L => N_err_South_req_X_L, N_err_Local_req_X_N => N_err_Local_req_X_N, N_err_IDLE_req_X_W => N_err_IDLE_req_X_W, N_err_North_req_X_W => N_err_North_req_X_W, N_err_East_req_X_S => N_err_East_req_X_S, N_err_West_req_X_L => N_err_West_req_X_L, N_err_South_req_X_N => N_err_South_req_X_N, N_err_Local_req_X_E => N_err_Local_req_X_E, N_err_IDLE_req_X_S => N_err_IDLE_req_X_S, N_err_North_req_X_S => N_err_North_req_X_S, N_err_East_req_X_L => N_err_East_req_X_L, N_err_West_req_X_N => N_err_West_req_X_N, N_err_South_req_X_E => N_err_South_req_X_E, N_err_Local_req_X_W => N_err_Local_req_X_W, N_err_IDLE_req_X_L => N_err_IDLE_req_X_L, N_err_North_req_X_L => N_err_North_req_X_L, N_err_East_req_X_N => N_err_East_req_X_N, N_err_West_req_X_E => N_err_West_req_X_E, N_err_South_req_X_W => N_err_South_req_X_W, N_err_Local_req_X_S => N_err_Local_req_X_S, N_arbiter_out_err_state_in_onehot => N_arbiter_out_err_state_in_onehot, N_arbiter_out_err_no_request_grants => N_arbiter_out_err_no_request_grants, N_err_request_IDLE_state => N_err_request_IDLE_state, N_err_request_IDLE_not_Grants => N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant => N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant => N_err_state_East_Invalid_Grant, N_err_state_West_Invalid_Grant => N_err_state_West_Invalid_Grant, N_err_state_South_Invalid_Grant => N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant => N_err_state_Local_Invalid_Grant, N_err_Grants_onehot_or_all_zero => N_err_Grants_onehot_or_all_zero, -- East Arbiter_out checker outputs E_arbiter_out_err_Requests_state_in_state_not_equal => E_arbiter_out_err_Requests_state_in_state_not_equal, E_err_IDLE_req_X_N => E_err_IDLE_req_X_N, E_err_North_req_X_N => E_err_North_req_X_N, E_err_North_credit_not_zero_req_X_N_grant_N => E_err_North_credit_not_zero_req_X_N_grant_N, E_err_North_credit_zero_or_not_req_X_N_not_grant_N => E_err_North_credit_zero_or_not_req_X_N_not_grant_N, E_err_East_req_X_E => E_err_East_req_X_E, E_err_East_credit_not_zero_req_X_E_grant_E => E_err_East_credit_not_zero_req_X_E_grant_E, E_err_East_credit_zero_or_not_req_X_E_not_grant_E => E_err_East_credit_zero_or_not_req_X_E_not_grant_E, E_err_West_req_X_W => E_err_West_req_X_W, E_err_West_credit_not_zero_req_X_W_grant_W => E_err_West_credit_not_zero_req_X_W_grant_W, E_err_West_credit_zero_or_not_req_X_W_not_grant_W => E_err_West_credit_zero_or_not_req_X_W_not_grant_W, E_err_South_req_X_S => E_err_South_req_X_S, E_err_South_credit_not_zero_req_X_S_grant_S => E_err_South_credit_not_zero_req_X_S_grant_S, E_err_South_credit_zero_or_not_req_X_S_not_grant_S => E_err_South_credit_zero_or_not_req_X_S_not_grant_S, E_err_Local_req_X_L => E_err_Local_req_X_L, E_err_Local_credit_not_zero_req_X_L_grant_L => E_err_Local_credit_not_zero_req_X_L_grant_L, E_err_Local_credit_zero_or_not_req_X_L_not_grant_L => E_err_Local_credit_zero_or_not_req_X_L_not_grant_L, E_err_IDLE_req_X_E => E_err_IDLE_req_X_E, E_err_North_req_X_E => E_err_North_req_X_E, E_err_East_req_X_W => E_err_East_req_X_W, E_err_West_req_X_S => E_err_West_req_X_S, E_err_South_req_X_L => E_err_South_req_X_L, E_err_Local_req_X_N => E_err_Local_req_X_N, E_err_IDLE_req_X_W => E_err_IDLE_req_X_W, E_err_North_req_X_W => E_err_North_req_X_W, E_err_East_req_X_S => E_err_East_req_X_S, E_err_West_req_X_L => E_err_West_req_X_L, E_err_South_req_X_N => E_err_South_req_X_N, E_err_Local_req_X_E => E_err_Local_req_X_E, E_err_IDLE_req_X_S => E_err_IDLE_req_X_S, E_err_North_req_X_S => E_err_North_req_X_S, E_err_East_req_X_L => E_err_East_req_X_L, E_err_West_req_X_N => E_err_West_req_X_N, E_err_South_req_X_E => E_err_South_req_X_E, E_err_Local_req_X_W => E_err_Local_req_X_W, E_err_IDLE_req_X_L => E_err_IDLE_req_X_L, E_err_North_req_X_L => E_err_North_req_X_L, E_err_East_req_X_N => E_err_East_req_X_N, E_err_West_req_X_E => E_err_West_req_X_E, E_err_South_req_X_W => E_err_South_req_X_W, E_err_Local_req_X_S => E_err_Local_req_X_S, E_arbiter_out_err_state_in_onehot => E_arbiter_out_err_state_in_onehot, E_arbiter_out_err_no_request_grants => E_arbiter_out_err_no_request_grants, E_err_request_IDLE_state => E_err_request_IDLE_state, E_err_request_IDLE_not_Grants => E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant => E_err_state_North_Invalid_Grant, E_err_state_East_Invalid_Grant => E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant => E_err_state_West_Invalid_Grant, E_err_state_South_Invalid_Grant => E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant => E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero => E_err_Grants_onehot_or_all_zero, -- West Arbiter_out checker outputs W_arbiter_out_err_Requests_state_in_state_not_equal => W_arbiter_out_err_Requests_state_in_state_not_equal, W_err_IDLE_req_X_N => W_err_IDLE_req_X_N, W_err_North_req_X_N => W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N => W_err_North_credit_not_zero_req_X_N_grant_N, W_err_North_credit_zero_or_not_req_X_N_not_grant_N => W_err_North_credit_zero_or_not_req_X_N_not_grant_N, W_err_East_req_X_E => W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E => W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E => W_err_East_credit_zero_or_not_req_X_E_not_grant_E, W_err_West_req_X_W => W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W => W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W => W_err_West_credit_zero_or_not_req_X_W_not_grant_W, W_err_South_req_X_S => W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S => W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S => W_err_South_credit_zero_or_not_req_X_S_not_grant_S, W_err_Local_req_X_L => W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L => W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L => W_err_Local_credit_zero_or_not_req_X_L_not_grant_L, W_err_IDLE_req_X_E => W_err_IDLE_req_X_E, W_err_North_req_X_E => W_err_North_req_X_E, W_err_East_req_X_W => W_err_East_req_X_W, W_err_West_req_X_S => W_err_West_req_X_S, W_err_South_req_X_L => W_err_South_req_X_L, W_err_Local_req_X_N => W_err_Local_req_X_N, W_err_IDLE_req_X_W => W_err_IDLE_req_X_W, W_err_North_req_X_W => W_err_North_req_X_W, W_err_East_req_X_S => W_err_East_req_X_S, W_err_West_req_X_L => W_err_West_req_X_L, W_err_South_req_X_N => W_err_South_req_X_N, W_err_Local_req_X_E => W_err_Local_req_X_E, W_err_IDLE_req_X_S => W_err_IDLE_req_X_S, W_err_North_req_X_S => W_err_North_req_X_S, W_err_East_req_X_L => W_err_East_req_X_L, W_err_West_req_X_N => W_err_West_req_X_N, W_err_South_req_X_E => W_err_South_req_X_E, W_err_Local_req_X_W => W_err_Local_req_X_W, W_err_IDLE_req_X_L => W_err_IDLE_req_X_L, W_err_North_req_X_L => W_err_North_req_X_L, W_err_East_req_X_N => W_err_East_req_X_N, W_err_West_req_X_E => W_err_West_req_X_E, W_err_South_req_X_W => W_err_South_req_X_W, W_err_Local_req_X_S => W_err_Local_req_X_S, W_arbiter_out_err_state_in_onehot => W_arbiter_out_err_state_in_onehot, W_arbiter_out_err_no_request_grants => W_arbiter_out_err_no_request_grants, W_err_request_IDLE_state => W_err_request_IDLE_state, W_err_request_IDLE_not_Grants => W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant => W_err_state_North_Invalid_Grant, W_err_state_East_Invalid_Grant => W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant => W_err_state_West_Invalid_Grant, W_err_state_South_Invalid_Grant => W_err_state_South_Invalid_Grant, W_err_state_Local_Invalid_Grant => W_err_state_Local_Invalid_Grant, W_err_Grants_onehot_or_all_zero => W_err_Grants_onehot_or_all_zero, -- South Arbiter_out checker outputs S_arbiter_out_err_Requests_state_in_state_not_equal => S_arbiter_out_err_Requests_state_in_state_not_equal, S_err_IDLE_req_X_N => S_err_IDLE_req_X_N, S_err_North_req_X_N => S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N => S_err_North_credit_not_zero_req_X_N_grant_N, S_err_North_credit_zero_or_not_req_X_N_not_grant_N => S_err_North_credit_zero_or_not_req_X_N_not_grant_N, S_err_East_req_X_E => S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E => S_err_East_credit_not_zero_req_X_E_grant_E, S_err_East_credit_zero_or_not_req_X_E_not_grant_E => S_err_East_credit_zero_or_not_req_X_E_not_grant_E, S_err_West_req_X_W => S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W => S_err_West_credit_not_zero_req_X_W_grant_W, S_err_West_credit_zero_or_not_req_X_W_not_grant_W => S_err_West_credit_zero_or_not_req_X_W_not_grant_W, S_err_South_req_X_S => S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S => S_err_South_credit_not_zero_req_X_S_grant_S, S_err_South_credit_zero_or_not_req_X_S_not_grant_S => S_err_South_credit_zero_or_not_req_X_S_not_grant_S, S_err_Local_req_X_L => S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L => S_err_Local_credit_not_zero_req_X_L_grant_L, S_err_Local_credit_zero_or_not_req_X_L_not_grant_L => S_err_Local_credit_zero_or_not_req_X_L_not_grant_L, S_err_IDLE_req_X_E => S_err_IDLE_req_X_E, S_err_North_req_X_E => S_err_North_req_X_E, S_err_East_req_X_W => S_err_East_req_X_W, S_err_West_req_X_S => S_err_West_req_X_S, S_err_South_req_X_L => S_err_South_req_X_L, S_err_Local_req_X_N => S_err_Local_req_X_N, S_err_IDLE_req_X_W => S_err_IDLE_req_X_W, S_err_North_req_X_W => S_err_North_req_X_W, S_err_East_req_X_S => S_err_East_req_X_S, S_err_West_req_X_L => S_err_West_req_X_L, S_err_South_req_X_N => S_err_South_req_X_N, S_err_Local_req_X_E => S_err_Local_req_X_E, S_err_IDLE_req_X_S => S_err_IDLE_req_X_S, S_err_North_req_X_S => S_err_North_req_X_S, S_err_East_req_X_L => S_err_East_req_X_L, S_err_West_req_X_N => S_err_West_req_X_N, S_err_South_req_X_E => S_err_South_req_X_E, S_err_Local_req_X_W => S_err_Local_req_X_W, S_err_IDLE_req_X_L => S_err_IDLE_req_X_L, S_err_North_req_X_L => S_err_North_req_X_L, S_err_East_req_X_N => S_err_East_req_X_N, S_err_West_req_X_E => S_err_West_req_X_E, S_err_South_req_X_W => S_err_South_req_X_W, S_err_Local_req_X_S => S_err_Local_req_X_S, S_arbiter_out_err_state_in_onehot => S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants => S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state => S_err_request_IDLE_state, S_err_request_IDLE_not_Grants => S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant => S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant => S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant => S_err_state_West_Invalid_Grant, S_err_state_South_Invalid_Grant => S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant => S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero => S_err_Grants_onehot_or_all_zero, -- Local Arbiter_out checker outputs L_arbiter_out_err_Requests_state_in_state_not_equal => L_arbiter_out_err_Requests_state_in_state_not_equal, L_err_IDLE_req_X_N => L_err_IDLE_req_X_N, L_err_North_req_X_N => L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N => L_err_North_credit_not_zero_req_X_N_grant_N, L_err_North_credit_zero_or_not_req_X_N_not_grant_N => L_err_North_credit_zero_or_not_req_X_N_not_grant_N, L_err_East_req_X_E => L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E => L_err_East_credit_not_zero_req_X_E_grant_E, L_err_East_credit_zero_or_not_req_X_E_not_grant_E => L_err_East_credit_zero_or_not_req_X_E_not_grant_E, L_err_West_req_X_W => L_err_West_req_X_W, L_err_West_credit_not_zero_req_X_W_grant_W => L_err_West_credit_not_zero_req_X_W_grant_W, L_err_West_credit_zero_or_not_req_X_W_not_grant_W => L_err_West_credit_zero_or_not_req_X_W_not_grant_W, L_err_South_req_X_S => L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S => L_err_South_credit_not_zero_req_X_S_grant_S, L_err_South_credit_zero_or_not_req_X_S_not_grant_S => L_err_South_credit_zero_or_not_req_X_S_not_grant_S, L_err_Local_req_X_L => L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L => L_err_Local_credit_not_zero_req_X_L_grant_L, L_err_Local_credit_zero_or_not_req_X_L_not_grant_L => L_err_Local_credit_zero_or_not_req_X_L_not_grant_L, L_err_IDLE_req_X_E => L_err_IDLE_req_X_E, L_err_North_req_X_E => L_err_North_req_X_E, L_err_East_req_X_W => L_err_East_req_X_W, L_err_West_req_X_S => L_err_West_req_X_S, L_err_South_req_X_L => L_err_South_req_X_L, L_err_Local_req_X_N => L_err_Local_req_X_N, L_err_IDLE_req_X_W => L_err_IDLE_req_X_W, L_err_North_req_X_W => L_err_North_req_X_W, L_err_East_req_X_S => L_err_East_req_X_S, L_err_West_req_X_L => L_err_West_req_X_L, L_err_South_req_X_N => L_err_South_req_X_N, L_err_Local_req_X_E => L_err_Local_req_X_E, L_err_IDLE_req_X_S => L_err_IDLE_req_X_S, L_err_North_req_X_S => L_err_North_req_X_S, L_err_East_req_X_L => L_err_East_req_X_L, L_err_West_req_X_N => L_err_West_req_X_N, L_err_South_req_X_E => L_err_South_req_X_E, L_err_Local_req_X_W => L_err_Local_req_X_W, L_err_IDLE_req_X_L => L_err_IDLE_req_X_L, L_err_North_req_X_L => L_err_North_req_X_L, L_err_East_req_X_N => L_err_East_req_X_N, L_err_West_req_X_E => L_err_West_req_X_E, L_err_South_req_X_W => L_err_South_req_X_W, L_err_Local_req_X_S => L_err_Local_req_X_S, L_arbiter_out_err_state_in_onehot => L_arbiter_out_err_state_in_onehot, L_arbiter_out_err_no_request_grants => L_arbiter_out_err_no_request_grants, L_err_request_IDLE_state => L_err_request_IDLE_state, L_err_request_IDLE_not_Grants => L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant => L_err_state_North_Invalid_Grant, L_err_state_East_Invalid_Grant => L_err_state_East_Invalid_Grant, L_err_state_West_Invalid_Grant => L_err_state_West_Invalid_Grant, L_err_state_South_Invalid_Grant => L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant => L_err_state_Local_Invalid_Grant, L_err_Grants_onehot_or_all_zero => L_err_Grants_onehot_or_all_zero ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Xbar select_signals Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL; Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL; Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL; Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL; Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0'; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Xbars -- all the Xbars XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_N, Data_out=> TX_N); XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_E, Data_out=> TX_E); XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_W, Data_out=> TX_W); XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_S, Data_out=> TX_S); XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_L, Data_out=> TX_L); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ end;
--############################### --# Project Name : I2C slave --# File : i2cslave.vhd --# Project : i2c slave for FPGA --# Engineer : Philippe THIRION --# Modification History --############################### library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity I2CSLAVE is generic( DEVICE : std_logic_vector(7 downto 0) := x"38" ); port( MCLK : in std_logic; nRST : in std_logic; SDA_IN : in std_logic; SCL_IN : in std_logic; SDA_OUT : out std_logic; SCL_OUT : out std_logic; ADDRESS : out std_logic_vector(7 downto 0); DATA_OUT : out std_logic_vector(7 downto 0); DATA_IN : in std_logic_vector(7 downto 0); WR : out std_logic; RD : out std_logic; READ_DONE : out std_logic ); end I2CSLAVE; architecture rtl of I2CSLAVE is type tstate is ( S_IDLE, S_START, S_SHIFTIN, S_RW, S_SENDACK, S_SENDACK2, S_SENDNACK, S_ADDRESS, S_WRITE, S_SHIFTOUT, S_READ, S_WAITACK ); type toperation is (OP_READ, OP_WRITE); signal state : tstate; signal next_state : tstate; signal operation : toperation; signal rising_scl, falling_scl : std_logic; signal address_i : std_logic_vector(7 downto 0); signal next_address : std_logic_vector(7 downto 0); signal counter : integer range 0 to 7; signal start_cond : std_logic; signal stop_cond : std_logic; signal sda_q, sda_qq, sda_qqq : std_logic; signal scl_q, scl_qq, scl_qqq : std_logic; signal shiftreg : std_logic_vector(7 downto 0); signal sda: std_logic; signal address_incr : std_logic; signal rd_d : std_logic; signal read_data_done : std_logic; begin ADDRESS <= address_i; next_address <= (others=>'0') when (address_i = x"FF") else std_logic_vector(to_unsigned(to_integer(unsigned( address_i )) + 1, 8)); S_RSY: process(MCLK,nRST) begin if (nRST = '0') then sda_q <= '1'; sda_qq <= '1'; sda_qqq <= '1'; scl_q <= '1'; scl_qq <= '1'; scl_qqq <= '1'; elsif (MCLK'event and MCLK='1') then sda_q <= SDA_IN; sda_qq <= sda_q; sda_qqq <= sda_qq; scl_q <= SCL_IN; scl_qq <= scl_q; scl_qqq <= scl_qq; end if; end process S_RSY; rising_scl <= scl_qq and not scl_qqq; falling_scl <= not scl_qq and scl_qqq; START_BIT: process(MCLK,nRST) begin if (nRST = '0') then start_cond <= '0'; elsif (MCLK'event and MCLK='1') then if (sda_qqq = '1' and sda_qq = '0' and scl_qq = '1') then start_cond <= '1'; else start_cond <= '0'; end if; end if; end process START_BIT; STOP_BIT: process(MCLK,nRST) begin if (nRST = '0') then stop_cond <= '0'; elsif (MCLK'event and MCLK='1') then if (sda_qqq = '0' and sda_qq = '1' and scl_qq = '1') then stop_cond <= '1'; else stop_cond <= '0'; end if; end if; end process STOP_BIT; sda <= sda_qq; RD_DELAY: process(MCLK, nRST) begin if (nRST = '0') then RD <= '0'; elsif (MCLK'event and MCLK='1') then RD <= rd_d; end if; end process RD_DELAY; OTO: process(MCLK, nRST) begin if (nRST = '0') then state <= S_IDLE; SDA_OUT <= '1'; SCL_OUT <= '1'; WR <= '0'; rd_d <= '0'; address_i <= (others=>'0'); DATA_OUT <= (others=>'0'); shiftreg <= (others=>'0'); read_data_done <= '0'; elsif (MCLK'event and MCLK='1') then if (stop_cond = '1') then state <= S_IDLE; SDA_OUT <= '1'; SCL_OUT <= '1'; operation <= OP_READ; WR <= '0'; rd_d <= '0'; address_incr <= '0'; elsif(start_cond = '1') then state <= S_START; SDA_OUT <= '1'; SCL_OUT <= '1'; operation <= OP_READ; WR <= '0'; rd_d <= '0'; address_incr <= '0'; elsif(state = S_IDLE) then state <= S_IDLE; SDA_OUT <= '1'; SCL_OUT <= '1'; operation <= OP_READ; WR <= '0'; rd_d <= '0'; address_incr <= '0'; elsif(state = S_START) then shiftreg <= (others=>'0'); state <= S_SHIFTIN; next_state <= S_RW; counter <= 6; elsif(state = S_SHIFTIN) then if (rising_scl = '1') then shiftreg(7 downto 1) <= shiftreg(6 downto 0); shiftreg(0) <= sda; if (counter = 0) then state <= next_state; counter <= 7; else counter <= counter - 1; end if; end if; elsif(state = S_RW) then if (rising_scl = '1') then if (shiftreg = DEVICE) then state <= S_SENDACK; if (sda = '1') then operation <= OP_READ; -- next_state <= S_READ; -- no needed rd_d <= '1'; else operation <= OP_WRITE; next_state <= S_ADDRESS; address_incr <= '0'; end if; else state <= S_SENDNACK; end if; end if; elsif(state = S_SENDACK) then WR <= '0'; rd_d <= '0'; if (falling_scl = '1') then SDA_OUT <= '0'; counter <= 7; if (operation= OP_WRITE) then state <= S_SENDACK2; else -- OP_READ state <= S_SHIFTOUT; shiftreg <= DATA_IN; read_data_done <= '1'; end if; end if; elsif(state = S_SENDACK2) then if (falling_scl = '1') then SDA_OUT <= '1'; state <= S_SHIFTIN; shiftreg <= (others=>'0'); if (address_incr = '1') then address_i <= next_address; end if; end if; elsif(state = S_SENDNACK) then if (falling_scl = '1') then SDA_OUT <= '1'; state <= S_IDLE; end if; elsif(state = S_ADDRESS) then address_i <= shiftreg; next_state <= S_WRITE; state <= S_SENDACK; address_incr <= '0'; elsif(state = S_WRITE) then DATA_OUT <= shiftreg; next_state <= S_WRITE; state <= S_SENDACK; WR <= '1'; address_incr <= '1'; elsif(state = S_SHIFTOUT) then read_data_done <= '0'; if (falling_scl = '1') then SDA_OUT <= shiftreg(7); shiftreg(7 downto 1) <= shiftreg(6 downto 0); shiftreg(0) <= '1'; if (counter = 0) then state <= S_READ; address_i <= next_address; rd_d <= '1'; else counter <= counter - 1; end if; end if; elsif(state = S_READ) then rd_d <= '0'; if (falling_scl = '1') then SDA_OUT <= '1'; state <= S_WAITACK; end if; elsif(state = S_WAITACK) then if (rising_scl = '1') then if (sda = '0') then state <= S_SHIFTOUT; counter <= 7; shiftreg <= DATA_IN; read_data_done <= '1'; else state <= S_IDLE; end if; end if; end if; end if; end process OTO; READ_DONE <= read_data_done; end rtl;
------------------------------------------------------------------------------------------------- -- Company : CNES -- Author : Mickael Carl (CNES) -- Copyright : Copyright (c) CNES. -- Licensing : GNU GPLv3 ------------------------------------------------------------------------------------------------- -- Version : V1 -- Version history : -- V1 : 2015-04-08 : Mickael Carl (CNES): Creation ------------------------------------------------------------------------------------------------- -- File name : STD_03700_good.vhd -- File Creation date : 2015-04-08 -- Project name : VHDL Handbook CNES Edition ------------------------------------------------------------------------------------------------- -- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor) ------------------------------------------------------------------------------------------------- -- Description : Handbook example: Reset assertion and deassertion: good example -- -- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at -- demonstrating good practices in VHDL and as such, its design is minimalistic. -- It is provided as is, without any warranty. -- This example is compliant with the Handbook version 1. -- ------------------------------------------------------------------------------------------------- -- Naming conventions: -- -- i_Port: Input entity port -- o_Port: Output entity port -- b_Port: Bidirectional entity port -- g_My_Generic: Generic entity port -- -- c_My_Constant: Constant definition -- t_My_Type: Custom type definition -- -- My_Signal_n: Active low signal -- v_My_Variable: Variable -- sm_My_Signal: FSM signal -- pkg_Param: Element Param coming from a package -- -- My_Signal_re: Rising edge detection of My_Signal -- My_Signal_fe: Falling edge detection of My_Signal -- My_Signal_rX: X times registered My_Signal signal -- -- P_Process_Name: Process -- ------------------------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; --CODE entity STD_03700_good is port ( i_Clock : in std_logic; -- Clock signal i_Reset_Input_n : in std_logic; -- Reset input o_Main_Reset_n : out std_logic -- Global reset signal active low ); end STD_03700_good; architecture Behavioral of STD_03700_good is signal Main_Reset_n : std_logic; -- Internal signal between FlipFlops signal Main_Reset_n_r : std_logic; -- Assertion block output begin P_Reset_Assert : process(i_Reset_Input_n, i_Clock) begin if (i_Reset_Input_n = '0') then Main_Reset_n <= '0'; -- Output reset signal is active low Main_Reset_n_r <= '0'; elsif rising_edge(i_Clock) then Main_Reset_n <= '1'; -- Reset is deasserted. Since it is active low, the inactive value is 1 Main_Reset_n_r <= Main_Reset_n; end if; end process; o_Main_Reset_n <= Main_Reset_n_r; end Behavioral; --CODE
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Mon May 29 22:11:05 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode synth_stub -- C:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_xlconstant_0_1/system_xlconstant_0_1_stub.vhdl -- Design : system_xlconstant_0_1 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity system_xlconstant_0_1 is Port ( dout : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); end system_xlconstant_0_1; architecture stub of system_xlconstant_0_1 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "dout[31:0]"; begin end;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 04.03.2016 11:22:26 -- Design Name: -- Module Name: rem_testbench - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity asl64_testbench is end asl64_testbench; architecture Behavioural of asl64_testbench is signal sig_i00, sig_i01, sig_i02, sig_r00, sig_r01, sig_r02, sig_FP, sig_FPout,sig_MDAT : std_logic_vector(31 DOWNTO 0); signal sig_reset, sig_CLK, sig_MWAIT : std_logic; component ASL64CoreAndMemory is PORT ( in0 : IN std_logic_vector(31 DOWNTO 0); in1 : IN std_logic_vector(31 DOWNTO 0); in2 : IN std_logic_vector(31 DOWNTO 0); out0 : OUT std_logic_vector(31 DOWNTO 0); out1 : OUT std_logic_vector(31 DOWNTO 0); out2 : OUT std_logic_vector(31 DOWNTO 0); frame_pointer : IN std_logic_vector(31 DOWNTO 0); frame_pointer_out : OUT std_logic_vector(31 DOWNTO 0); rst : IN std_logic; clck : IN std_logic; mem_wait : IN std_logic; mem_push : IN std_logic_vector(31 DOWNTO 0) ); end component; begin uut: ASL64CoreAndMemory port map ( in0 => sig_i00, in1 => sig_i01, in2 => sig_i02, out0 => sig_r00, out1 => sig_r01, out2 => sig_r02, frame_pointer => sig_FP, frame_pointer_out => sig_FPout, rst => sig_reset, clck => sig_CLK, mem_wait => sig_MWAIT, mem_push => sig_MDAT ); clock: process constant clock_period:time := 40ns; begin wait for 200ns; for I in 0 to 100 loop sig_CLK <= '0'; wait for clock_period/2; sig_CLK <= '1'; wait for clock_period/2; end loop; wait; end process clock; test: process begin sig_MWAIT <= '1'; sig_reset <= '1'; wait for 100ns; sig_reset <= '0'; wait for 100ns; sig_i00 <= "00000000000000000000000000100101"; sig_i01 <= "00000000000000000000000000000100"; sig_i02 <= "00000000000000000000000000010011"; sig_MDAT <= "00000000000000000000000000011111"; sig_FP <= "00000000000000000000000001010000"; wait; end process test; end Behavioural;
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014 -- Date : Fri Nov 2 15:01:50 2018 -- Host : graviton running 64-bit Debian GNU/Linux 7.11 (wheezy) -- Command : write_vhdl -force -mode funcsim -- /home/guest/cae/fpga/ntpserver/sv/ip/ocxo_clk_pll/ocxo_clk_pll_funcsim.vhdl -- Design : ocxo_clk_pll -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ocxo_clk_pll_ocxo_clk_pll_clk_wiz is port ( clk_in1 : in STD_LOGIC; clk_out1 : out STD_LOGIC; resetn : in STD_LOGIC; locked : out STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of ocxo_clk_pll_ocxo_clk_pll_clk_wiz : entity is "ocxo_clk_pll_clk_wiz"; end ocxo_clk_pll_ocxo_clk_pll_clk_wiz; architecture STRUCTURE of ocxo_clk_pll_ocxo_clk_pll_clk_wiz is signal clk_in1_ocxo_clk_pll : STD_LOGIC; signal clkfbout_ocxo_clk_pll : STD_LOGIC; signal reset_high : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE"; attribute CAPACITANCE : string; attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; attribute IBUF_DELAY_VALUE : string; attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; attribute IFD_DELAY_VALUE : string; attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; begin clkin1_ibufg: unisim.vcomponents.IBUF generic map( IOSTANDARD => "DEFAULT" ) port map ( I => clk_in1, O => clk_in1_ocxo_clk_pll ); mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV generic map( BANDWIDTH => "OPTIMIZED", CLKFBOUT_MULT_F => 63.750000, CLKFBOUT_PHASE => 0.000000, CLKFBOUT_USE_FINE_PS => false, CLKIN1_PERIOD => 100.000000, CLKIN2_PERIOD => 0.000000, CLKOUT0_DIVIDE_F => 6.375000, CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT0_USE_FINE_PS => false, CLKOUT1_DIVIDE => 1, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT1_USE_FINE_PS => false, CLKOUT2_DIVIDE => 1, CLKOUT2_DUTY_CYCLE => 0.500000, CLKOUT2_PHASE => 0.000000, CLKOUT2_USE_FINE_PS => false, CLKOUT3_DIVIDE => 1, CLKOUT3_DUTY_CYCLE => 0.500000, CLKOUT3_PHASE => 0.000000, CLKOUT3_USE_FINE_PS => false, CLKOUT4_CASCADE => false, CLKOUT4_DIVIDE => 1, CLKOUT4_DUTY_CYCLE => 0.500000, CLKOUT4_PHASE => 0.000000, CLKOUT4_USE_FINE_PS => false, CLKOUT5_DIVIDE => 1, CLKOUT5_DUTY_CYCLE => 0.500000, CLKOUT5_PHASE => 0.000000, CLKOUT5_USE_FINE_PS => false, CLKOUT6_DIVIDE => 1, CLKOUT6_DUTY_CYCLE => 0.500000, CLKOUT6_PHASE => 0.000000, CLKOUT6_USE_FINE_PS => false, COMPENSATION => "INTERNAL", DIVCLK_DIVIDE => 1, IS_CLKINSEL_INVERTED => '0', IS_PSEN_INVERTED => '0', IS_PSINCDEC_INVERTED => '0', IS_PWRDWN_INVERTED => '0', IS_RST_INVERTED => '0', REF_JITTER1 => 0.010000, REF_JITTER2 => 0.010000, SS_EN => "FALSE", SS_MODE => "CENTER_HIGH", SS_MOD_PERIOD => 10000, STARTUP_WAIT => false ) port map ( CLKFBIN => clkfbout_ocxo_clk_pll, CLKFBOUT => clkfbout_ocxo_clk_pll, CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, CLKIN1 => clk_in1_ocxo_clk_pll, CLKIN2 => '0', CLKINSEL => '1', CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, CLKOUT0 => clk_out1, CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, DADDR(6) => '0', DADDR(5) => '0', DADDR(4) => '0', DADDR(3) => '0', DADDR(2) => '0', DADDR(1) => '0', DADDR(0) => '0', DCLK => '0', DEN => '0', DI(15) => '0', DI(14) => '0', DI(13) => '0', DI(12) => '0', DI(11) => '0', DI(10) => '0', DI(9) => '0', DI(8) => '0', DI(7) => '0', DI(6) => '0', DI(5) => '0', DI(4) => '0', DI(3) => '0', DI(2) => '0', DI(1) => '0', DI(0) => '0', DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, DWE => '0', LOCKED => locked, PSCLK => '0', PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, PSEN => '0', PSINCDEC => '0', PWRDWN => '0', RST => reset_high ); mmcm_adv_inst_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => resetn, O => reset_high ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ocxo_clk_pll is port ( clk_in1 : in STD_LOGIC; clk_out1 : out STD_LOGIC; resetn : in STD_LOGIC; locked : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of ocxo_clk_pll : entity is true; attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of ocxo_clk_pll : entity is "ocxo_clk_pll,clk_wiz_v5_1,{component_name=ocxo_clk_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_ONCHIP,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=100.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; end ocxo_clk_pll; architecture STRUCTURE of ocxo_clk_pll is begin inst: entity work.ocxo_clk_pll_ocxo_clk_pll_clk_wiz port map ( clk_in1 => clk_in1, clk_out1 => clk_out1, locked => locked, resetn => resetn ); end STRUCTURE;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity biaser_tb is end entity; architecture biaser_tb_arq of biaser_tb is signal operation : std_logic := '0'; signal exp_in: std_logic_vector(2 downto 0) := (others => '0'); signal exp_out: std_logic_vector(2 downto 0) := (others => '0'); component biaser is generic( EXP_BITS: natural := 6 ); port ( operation : in std_logic; exp_in: in std_logic_vector(EXP_BITS - 1 downto 0); exp_out : out std_logic_vector(EXP_BITS - 1 downto 0) ); end component; for biaser_0: biaser use entity work.biaser; begin biaser_0: biaser generic map(EXP_BITS => 3) port map( operation => operation, exp_in => exp_in, exp_out => exp_out ); process type pattern_type is record o : std_logic; ei : std_logic_vector(2 downto 0); eo : std_logic_vector(2 downto 0); end record; -- The patterns to apply. type pattern_array is array (natural range<>) of pattern_type; constant patterns : pattern_array := ( ('1',"000","101"), ('1',"001","110"), ('0',"000","011") ); begin for i in patterns'range loop -- Set the inputs. operation <= patterns(i).o; exp_in <= patterns(i).ei; -- Wait for the results. wait for 1 ns; -- Check the outputs. assert exp_out = patterns(i).eo report "BAD EXPONENT: " & integer'image(to_integer(unsigned(exp_out))) severity error; end loop; assert false report "end of test" severity note; wait; end process; end;
-- Library Declaration library IEEE; use IEEE.std_logic_1164.all; library WORK; use WORK.globals.all; -- Component Declaration entity sbox is port ( b_in : in std_logic_vector (7 downto 0); ctrl_dec : T_ENCDEC; clock, reset : in std_logic; b_out : out std_logic_vector (7 downto 0) ); end sbox; -- Architecture of the Component architecture a_sbox of sbox is component DDR_register is generic( SIZE : integer := 8 ); port( din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 ); -- dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 ); rst, clk : in std_logic ); end component; component aff_trans port ( a : in std_logic_vector (7 downto 0); b_out : out std_logic_vector (7 downto 0) ); end component; component aff_trans_inv port ( a : in std_logic_vector (7 downto 0); b_out : out std_logic_vector (7 downto 0) ); end component; component gfmap port ( a : in std_logic_vector (7 downto 0); ah, al : out std_logic_vector (3 downto 0)); end component; component quadrato port ( a : in std_logic_vector (3 downto 0); d : out std_logic_vector (3 downto 0)); end component; component x_e is port ( a : in std_logic_vector (3 downto 0); d : out std_logic_vector (3 downto 0) ); end component; component gf_molt is port ( a, b: in std_logic_vector (3 downto 0); d : out std_logic_vector (3 downto 0)); end component; component gf_inv is port ( a_in : std_logic_vector (3 downto 0); d : out std_logic_vector (3 downto 0)); end component; component gfmapinv is port ( ah, al : in std_logic_vector (3 downto 0); a : out std_logic_vector (7 downto 0) ); end component; -- Internal Signal (4 std_logic) signal ah, a1h, al, a1l, o, n, m, l, i, g, f, p, p_hi, p_lo, q, d, d_hi, d_lo, r, r_hi, r_lo : std_logic_vector (3 downto 0); -- Internal Signal (8 bit) signal s, t, v, z : std_logic_vector (7 downto 0); signal s_enc_buffer : T_ENCDEC; begin -- Affine Trasnformation gen000e : if ( not C_INCLUDE_DECODING_LOGIC ) generate v <= b_in; end generate; gen000d : if ( C_INCLUDE_DECODING_LOGIC ) generate ati:aff_trans_inv port map (b_in, s); v <= s when (ctrl_dec = C_DEC) else b_in; end generate; -- Map mp:gfmap port map (v, ah, al); -- First Square qua1:quadrato port map (ah, o); -- Second Square qua2:quadrato port map (al, n); -- X [e] xe:x_e port map (o, m); -- First Moltiplicator molt1:gf_molt port map (ah, al, l); f <= ah xor al; i <= m xor n; g <= i xor l; -- Inverter --inv:gf_inv port map (q, d); inv:gf_inv port map (g, q); temp_reg_p : DDR_register generic map ( SIZE=>4 ) port map( din_hi=>ah, din_lo=>ah, --dout=>p, dout_hi=>p_hi, dout_lo=>p_lo, rst=>reset, clk=>clock ); p <= p_hi when ( clock = '1' ) else p_lo; --temp_reg_q : DDR_register generic map ( SIZE=>4 ) port map( g, q, reset, clock ); temp_reg_q : DDR_register generic map ( SIZE=>4 ) port map( din_hi=>q, din_lo=>q, --dout=>d, dout_hi=>d_hi, dout_lo=>d_lo, rst=>reset, clk=>clock ); d <= d_hi when ( clock = '1' ) else d_lo; temp_reg_r : DDR_register generic map ( SIZE=>4 ) port map( din_hi=>f, din_lo=>f, --dout=>r, dout_hi=>r_hi, dout_lo=>r_lo, rst=>reset, clk=>clock ); r <= r_hi when ( clock = '1' ) else r_lo; gen002e : if ( not C_INCLUDE_DECODING_LOGIC ) generate s_enc_buffer <= C_ENC; end generate; -- gen002e : if ( not C_INCLUDE_DECODING_LOGIC ) gen002d : if ( C_INCLUDE_DECODING_LOGIC ) generate S_ENC_PROC : process( reset, clock ) begin if ( reset=RESET_ACTIVE ) then s_enc_buffer <= C_ENC; elsif ( clock'event and clock='1' ) then s_enc_buffer <= ctrl_dec; end if; end process S_ENC_PROC; end generate; -- gen002d : if ( C_INCLUDE_DECODING_LOGIC ) -- Second Moltiplicator molt2:gf_molt port map (p, d, a1h); -- Third Moltiplicator molt3:gf_molt port map (d, r, a1l); -- Inverse Map mapinv:gfmapinv port map (a1h, a1l, z); -- Inverse Affine Transformation at:aff_trans port map (z, t); gen001e : if ( not C_INCLUDE_DECODING_LOGIC ) generate b_out <= t; end generate; gen001d : if ( C_INCLUDE_DECODING_LOGIC ) generate b_out <= z when ( s_enc_buffer=C_DEC ) else t; end generate; end a_sbox;
-- Library Declaration library IEEE; use IEEE.std_logic_1164.all; library WORK; use WORK.globals.all; -- Component Declaration entity sbox is port ( b_in : in std_logic_vector (7 downto 0); ctrl_dec : T_ENCDEC; clock, reset : in std_logic; b_out : out std_logic_vector (7 downto 0) ); end sbox; -- Architecture of the Component architecture a_sbox of sbox is component DDR_register is generic( SIZE : integer := 8 ); port( din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 ); -- dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 ); rst, clk : in std_logic ); end component; component aff_trans port ( a : in std_logic_vector (7 downto 0); b_out : out std_logic_vector (7 downto 0) ); end component; component aff_trans_inv port ( a : in std_logic_vector (7 downto 0); b_out : out std_logic_vector (7 downto 0) ); end component; component gfmap port ( a : in std_logic_vector (7 downto 0); ah, al : out std_logic_vector (3 downto 0)); end component; component quadrato port ( a : in std_logic_vector (3 downto 0); d : out std_logic_vector (3 downto 0)); end component; component x_e is port ( a : in std_logic_vector (3 downto 0); d : out std_logic_vector (3 downto 0) ); end component; component gf_molt is port ( a, b: in std_logic_vector (3 downto 0); d : out std_logic_vector (3 downto 0)); end component; component gf_inv is port ( a_in : std_logic_vector (3 downto 0); d : out std_logic_vector (3 downto 0)); end component; component gfmapinv is port ( ah, al : in std_logic_vector (3 downto 0); a : out std_logic_vector (7 downto 0) ); end component; -- Internal Signal (4 std_logic) signal ah, a1h, al, a1l, o, n, m, l, i, g, f, p, p_hi, p_lo, q, d, d_hi, d_lo, r, r_hi, r_lo : std_logic_vector (3 downto 0); -- Internal Signal (8 bit) signal s, t, v, z : std_logic_vector (7 downto 0); signal s_enc_buffer : T_ENCDEC; begin -- Affine Trasnformation gen000e : if ( not C_INCLUDE_DECODING_LOGIC ) generate v <= b_in; end generate; gen000d : if ( C_INCLUDE_DECODING_LOGIC ) generate ati:aff_trans_inv port map (b_in, s); v <= s when (ctrl_dec = C_DEC) else b_in; end generate; -- Map mp:gfmap port map (v, ah, al); -- First Square qua1:quadrato port map (ah, o); -- Second Square qua2:quadrato port map (al, n); -- X [e] xe:x_e port map (o, m); -- First Moltiplicator molt1:gf_molt port map (ah, al, l); f <= ah xor al; i <= m xor n; g <= i xor l; -- Inverter --inv:gf_inv port map (q, d); inv:gf_inv port map (g, q); temp_reg_p : DDR_register generic map ( SIZE=>4 ) port map( din_hi=>ah, din_lo=>ah, --dout=>p, dout_hi=>p_hi, dout_lo=>p_lo, rst=>reset, clk=>clock ); p <= p_hi when ( clock = '1' ) else p_lo; --temp_reg_q : DDR_register generic map ( SIZE=>4 ) port map( g, q, reset, clock ); temp_reg_q : DDR_register generic map ( SIZE=>4 ) port map( din_hi=>q, din_lo=>q, --dout=>d, dout_hi=>d_hi, dout_lo=>d_lo, rst=>reset, clk=>clock ); d <= d_hi when ( clock = '1' ) else d_lo; temp_reg_r : DDR_register generic map ( SIZE=>4 ) port map( din_hi=>f, din_lo=>f, --dout=>r, dout_hi=>r_hi, dout_lo=>r_lo, rst=>reset, clk=>clock ); r <= r_hi when ( clock = '1' ) else r_lo; gen002e : if ( not C_INCLUDE_DECODING_LOGIC ) generate s_enc_buffer <= C_ENC; end generate; -- gen002e : if ( not C_INCLUDE_DECODING_LOGIC ) gen002d : if ( C_INCLUDE_DECODING_LOGIC ) generate S_ENC_PROC : process( reset, clock ) begin if ( reset=RESET_ACTIVE ) then s_enc_buffer <= C_ENC; elsif ( clock'event and clock='1' ) then s_enc_buffer <= ctrl_dec; end if; end process S_ENC_PROC; end generate; -- gen002d : if ( C_INCLUDE_DECODING_LOGIC ) -- Second Moltiplicator molt2:gf_molt port map (p, d, a1h); -- Third Moltiplicator molt3:gf_molt port map (d, r, a1l); -- Inverse Map mapinv:gfmapinv port map (a1h, a1l, z); -- Inverse Affine Transformation at:aff_trans port map (z, t); gen001e : if ( not C_INCLUDE_DECODING_LOGIC ) generate b_out <= t; end generate; gen001d : if ( C_INCLUDE_DECODING_LOGIC ) generate b_out <= z when ( s_enc_buffer=C_DEC ) else t; end generate; end a_sbox;
library IEEE, STD; use STD.textio.all; use WORK.std_logic_textio.all; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity bstest_tb is end bstest_tb; architecture tb_arch of bstest_tb is -- UUT component component bstest port ( sldsw : in std_logic_vector(3 downto 0); button : in std_logic_vector(3 downto 0); -- N-E-W-S led : out std_logic_vector(7 downto 0) ); end component; -- I/O signals signal clk : std_logic := '0'; signal sldsw : std_logic_vector(3 downto 0); signal button : std_logic_vector(3 downto 0); signal led : std_logic_vector(7 downto 0); -- Constant declarations constant CLK_PERIOD : time := 20 ns; -- Declare results file file ResultsFile: text open write_mode is "bstest_results.txt"; begin uut : bstest port map ( sldsw => sldsw, button => button, led => led ); DATA_STIM: process variable count_hi : integer range 0 to 15 := 0; variable count_lo : integer range 0 to 15 := 0; variable line_el: line; begin for i in 0 to 255 loop count_hi := i / 16; count_lo := i mod 16; sldsw <= std_logic_vector(to_unsigned(count_hi, 4)); button <= std_logic_vector(to_unsigned(count_lo, 4)); -- Write the time write(line_el, now); -- write the line write(line_el, ':'); -- write the line -- Write the sldsw signal write(line_el, ' '); write(line_el, sldsw); -- write the line -- Write the button signal write(line_el, ' '); write(line_el, button); -- write the line wait for CLK_PERIOD; -- Write the led signal write(line_el, ' '); write(line_el, led); -- write the line writeline(ResultsFile, line_el); -- write the contents into the file wait for 9*CLK_PERIOD; end loop; wait for CLK_PERIOD; end process DATA_STIM; end tb_arch;
-- cpu.vhd: Simple 8-bit CPU (BrainFuck interpreter) -- Copyright (C) 2014 Brno University of Technology, -- Faculty of Information Technology -- Author(s): Ján Jusko xjusko00 -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -- ---------------------------------------------------------------------------- -- Entity declaration -- ---------------------------------------------------------------------------- entity cpu is port ( CLK : in std_logic; -- hodinovy signal RESET : in std_logic; -- asynchronni reset procesoru EN : in std_logic; -- povoleni cinnosti procesoru -- synchronni pamet RAM DATA_ADDR : out std_logic_vector(12 downto 0); -- adresa do pameti DATA_WDATA : out std_logic_vector(7 downto 0); -- mem[DATA_ADDR] <- DATA_WDATA pokud DATA_EN='1' DATA_RDATA : in std_logic_vector(7 downto 0); -- DATA_RDATA <- ram[DATA_ADDR] pokud DATA_EN='1' DATA_RDWR : out std_logic; -- cteni (0) / zapis (1) DATA_EN : out std_logic; -- povoleni cinnosti -- vstupni port IN_DATA : in std_logic_vector(7 downto 0); -- IN_DATA <- stav klavesnice pokud IN_VLD='1' a IN_REQ='1' IN_VLD : in std_logic; -- data platna IN_REQ : out std_logic; -- pozadavek na vstup data -- vystupni port OUT_DATA : out std_logic_vector(7 downto 0); -- zapisovana data OUT_BUSY : in std_logic; -- LCD je zaneprazdnen (1), nelze zapisovat OUT_WE : out std_logic -- LCD <- OUT_DATA pokud OUT_WE='1' a OUT_BUSY='0' ); end cpu; -- ---------------------------------------------------------------------------- -- Architecture declaration -- ---------------------------------------------------------------------------- architecture behavioral of cpu is -- PROGRAM COUNTER 13b signal PC_reg : std_logic_vector(12 downto 0); signal PC_inc : std_logic; signal PC_dec : std_logic; -- MEMORY POINTER 13b signal PTR_reg : std_logic_vector(12 downto 0); signal PTR_inc : std_logic; signal PTR_dec : std_logic; -- LOOP COUNTER 8b signal CNT_reg : std_logic_vector(7 downto 0); signal CNT_inc : std_logic; signal CNT_dec : std_logic; -- MULTIPLEXORY signal sel : std_logic := '0'; signal sel2 : std_logic_vector(1 downto 0) := "01"; -- INSTRUKCIE type inst is (incPTR, decPTR, incVALUE, decVALUE, whileS, whileE, putchar, readchar, halt, skip); signal decoded_inst : inst; -- STAVY MOOROVA FSM AUTOMATU type FSM_state is (SIDLE, SFETCH, SDECODE, SHALT, SSKIP, SINCPTR, SDECPTR, -- >/< SINCVALUE, SINCVALUE2, SDECVALUE, SDECVALUE2, -- +/- SPUTCHAR, SPUTCHAR2, -- . SREADCHAR, SREADCHAR2, -- , SWHILES,SWHILES2,SWHILES3,SWHILES4,SWHILES5, -- [ SWHILEE,SWHILEE1,SWHILEE2,SWHILEE3,SWHILEE4 -- ] ); signal Present_state: FSM_state; signal Next_state : FSM_state; begin -----------------------Program Counter----------------------- ------------------------------------------------------------- PC: process (CLK,RESET) begin if (RESET = '1') then PC_reg <= (others => '0'); elsif (CLK'event) and (CLK = '1') then if (PC_inc = '1') then PC_reg <= PC_reg + "0000000000001"; end if; if (PC_dec = '1') then PC_reg <= PC_reg - "0000000000001"; end if; end if; end process PC; -----------------------Memory pointer------------------------ ------------------------------------------------------------- PTR: process (CLK,RESET) begin if (RESET = '1') then PTR_reg <= "1000000000000"; elsif (CLK'event) and (CLK = '1') then if (PTR_inc = '1') then if (PTR_reg = "1111111111111") then -- KRUHOVOST OVERFLOW PTR_reg <= "1000000000000"; else PTR_reg <= PTR_reg + "0000000000001"; end if; end if; if (PTR_dec = '1') then if (PTR_reg = "1000000000000") then -- KRUHOVOST UNDERFLOW PTR_reg <= "1111111111111"; else PTR_reg <= PTR_reg - "0000000000001"; end if; end if; end if; end process PTR; -----------------------Loop counter-------------------------- ------------------------------------------------------------- CNT: process (CLK, RESET) begin if (RESET = '1') then CNT_reg <= (others=>'0'); elsif (CLK'event) and (CLK = '1') then if (CNT_inc = '1') then CNT_reg <= CNT_reg + "00000001"; end if; if (CNT_dec = '1') then CNT_reg <= CNT_reg - "00000001"; end if; end if; end process CNT; --------------------Finite state machine--------------------- ------------------------------------------------------------- FSM_pstate: process (CLK, RESET, EN) begin if (RESET = '1') then Present_state <= SIDLE; elsif (CLK'event) and (CLK = '1') then if (EN = '1') then Present_state <= Next_state; end if; end if; end process FSM_pstate; -----------------MULTIPLEXOR PC vs. PTR---------------------- ------------------------------------------------------------- MUX1: process (sel, PTR_reg, PC_reg) begin case sel is when '1' => DATA_ADDR <= PTR_reg; when '0' => DATA_ADDR <= PC_reg; when others => end case; end process MUX1; -----------------MULTIPLEXOR WRITE DATA---------------------- ------------------------------------------------------------- MUX2: process (sel2, DATA_RDATA, IN_DATA) begin case sel2 is when "01" => DATA_WDATA <= DATA_RDATA + "00000001"; when "10" => DATA_WDATA <= DATA_RDATA - "00000001"; when "11" => DATA_WDATA <= IN_DATA; when others => end case; end process MUX2; --------------------Instruction decoder---------------------- ------------------------------------------------------------- INST_decoder: process (DATA_RDATA) begin case DATA_RDATA is when X"00" => decoded_inst <= halt; when X"3E" => decoded_inst <= incPTR; when X"3C" => decoded_inst <= decPTR; when X"2B" => decoded_inst <= incVALUE; when X"2D" => decoded_inst <= decVALUE; when X"5B" => decoded_inst <= whileS; when X"5D" => decoded_inst <= whileE; when X"2E" => decoded_inst <= putchar; when X"2C" => decoded_inst <= readchar; when others=> decoded_inst <= skip; end case; end process INST_decoder; --------------------FSM PROCESSOR---------------------------- ------------------------------------------------------------- FSMPROCESSOR: process (Present_state, decoded_inst, OUT_BUSY, DATA_RDATA, IN_VLD, CNT_reg) begin IN_REQ <='0'; OUT_WE<='0'; DATA_RDWR<='0'; DATA_EN<='0'; PC_inc<='0'; PC_dec<='0'; PTR_inc<='0'; PTR_dec<='0'; CNT_inc<='0'; CNT_dec<='0'; sel <= '0'; sel2 <= "01"; OUT_DATA <= (others => '0'); case Present_state is when SIDLE => -- zaciatok, init, pri resete Next_state <= SFETCH; when SHALT => -- koniec programu Next_state <= SHALT; when SSKIP => -- preskoc komentare PC_inc <= '1'; Next_state <= SFETCH; when SFETCH => -- nacitaj instrukciu DATA_EN <= '1'; DATA_RDWR <= '0'; sel <= '0'; Next_state <= SDECODE; when SDECODE => -- dekoduj instrukciu case decoded_inst is when halt => Next_state <= SHALT; when incPTR => Next_state <= SINCPTR; when decPTR => Next_state <= SDECPTR; when incVALUE => Next_state <= SINCVALUE; when decVALUE => Next_state <= SDECVALUE; when whileS => Next_state <= SWHILES; when whileE => Next_state <= SWHILEE; when putchar => Next_state <= SPUTCHAR; when readchar => Next_state <= SREADCHAR; when skip => Next_state <= SSKIP; end case; -- PTR inkrement (>) when SINCPTR => PC_inc <= '1'; PTR_inc <= '1'; Next_state <= SFETCH; -- PTR dekrement (<) when SDECPTR => PC_inc <= '1'; PTR_dec <= '1'; Next_state <= SFETCH; -- PTR inkrement (+) when SINCVALUE => sel <= '1'; DATA_RDWR <= '0'; DATA_EN <= '1'; Next_state <= SINCVALUE2; when SINCVALUE2 => DATA_RDWR <= '1'; DATA_EN <= '1'; sel <= '1'; sel2 <= "01"; PC_inc <= '1'; Next_state <= SFETCH; -- PTR dekrement (-) when SDECVALUE => sel <= '1'; DATA_RDWR <= '0'; DATA_EN <= '1'; Next_state <= SDECVALUE2; when SDECVALUE2 => DATA_RDWR <= '1'; DATA_EN <= '1'; sel <= '1'; sel2 <= "10"; PC_inc <= '1'; Next_state <= SFETCH; -- vypis znak (.) when SPUTCHAR => DATA_RDWR <= '0'; DATA_EN <= '1'; sel <= '1'; Next_state <= SPUTCHAR2; when SPUTCHAR2 => if (OUT_BUSY = '0') then OUT_WE <= '1'; OUT_DATA <= DATA_RDATA; PC_inc <= '1'; Next_state <= SFETCH; else Next_state <= SPUTCHAR2; end if; -- nacitaj znak (,) when SREADCHAR => IN_REQ <= '1'; Next_state <= SREADCHAR2; when SREADCHAR2 => if (IN_VLD = '1') then sel <= '1'; sel2 <= "11"; DATA_RDWR <= '1'; DATA_EN <= '1'; PC_inc <= '1'; Next_state <= SFETCH; else IN_REQ <= '1'; Next_state <= SREADCHAR2; end if; -- WHILE ZACIATOK -- when SWHILES => DATA_RDWR <= '0'; DATA_EN <= '1'; PC_inc <= '1'; sel <= '1'; Next_state <= SWHILES2; when SWHILES2 => if (DATA_RDATA = "00000000") then CNT_inc <= '1'; Next_state <= SWHILES3; else Next_state <= SFETCH; end if; when SWHILES3 => DATA_RDWR <= '0'; DATA_EN <= '1'; sel <= '0'; Next_state <= SWHILES4; when SWHILES4 => if (decoded_inst = whileE) then CNT_dec <= '1'; elsif (decoded_inst = whileS) then CNT_inc <= '1'; end if; PC_inc <= '1'; Next_state <= SWHILES5; when SWHILES5 => if (CNT_reg = "00000000") then Next_state <= SFETCH; else Next_state <= SWHILES3; end if; -- WHILE KONIEC -- when SWHILEE => DATA_RDWR <= '0'; DATA_EN <= '1'; sel <= '1'; Next_state <= SWHILEE1; when SWHILEE1 => if (DATA_RDATA = "00000000") then PC_inc <= '1'; Next_state <= SFETCH; else CNT_inc <= '1'; PC_dec <= '1'; Next_state <= SWHILEE2; end if; when SWHILEE2 => sel <= '0'; DATA_RDWR <= '0'; DATA_EN <= '1'; Next_state <= SWHILEE3; when SWHILEE3 => if (decoded_inst = whileS) then CNT_dec <= '1'; elsif (decoded_inst = whileE) then CNT_inc <= '1'; end if; Next_state <= SWHILEE4; when SWHILEE4 => if (CNT_reg = "00000000") then PC_inc <= '1'; Next_state <= SFETCH; else PC_dec <= '1'; Next_state <= SWHILEE2; end if; end case; end process FSMPROCESSOR; end behavioral;
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; PACKAGE rc5_pkg IS type rc5_rom_26 is array (0 to 25) of std_logic_vector(31 downto 0); type rc5_rom_4 is array (0 to 3) of std_logic_vector(31 downto 0); type rc5_key_StateType is (ST_IDLE, -- In this state RC5 key expansion is ready for input ST_KEY_IN, -- In this state key has been fully loaded ST_KEY_EXP, -- In this state key expansion is in progress ST_READY); -- In this state RC5 key expansion has completed --RC5 state machine has five key states TYPE enc_StateType IS( ST_IDLE, -- In this state RC5 is ready for input ST_PRE_ROUND, -- In this state RC5 pre-round op is performed ST_ROUND_OP, -- In this state RC5 round op is performed. -- The state machine remains in this state -- for twelve clock cycles. ST_READY -- In this state RC5 has completed encryption ); TYPE dec_StateType IS( ST_IDLE, -- In this state RC5 is ready for input ST_ROUND_OP, -- In this state RC5 round op is performed. -- The state machine remains in this state -- for twelve clock cycles. ST_POST_ROUND, -- In this state RC5 post-round op is performed ST_READY -- In this state RC5 has completed encryption ); COMPONENT rc5_key -- Key expansion module PORT( clr,clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal key : in std_logic_vector(127 downto 0); key_vld : in std_logic; skey : out rc5_rom_26; key_rdy : out std_logic); END COMPONENT; COMPONENT rc5_enc -- Encryption module PORT( clr,clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit input di_vld : IN STD_LOGIC; -- Valid Input key_rdy : IN STD_LOGIC; skey : IN rc5_rom_26; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit output do_rdy : OUT STD_LOGIC --Output is Ready ); END COMPONENT; COMPONENT rc5_dec -- Decryption module PORT( clr,clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit input di_vld : IN STD_LOGIC; -- Valid Input key_rdy : IN STD_LOGIC; skey : IN rc5_rom_26; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit output do_rdy : OUT STD_LOGIC --Output is Ready ); END COMPONENT; END rc5_pkg;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc940.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c10s05b00x00p03n02i00940pkg1 is function F1(B:in integer) return integer; end c10s05b00x00p03n02i00940pkg1; package body c10s05b00x00p03n02i00940pkg1 is function F1(B:in integer) return integer is begin return 1; end; end c10s05b00x00p03n02i00940pkg1; package c10s05b00x00p03n02i00940pkg2 is function F1(B:in bit) return boolean; end c10s05b00x00p03n02i00940pkg2; package body c10s05b00x00p03n02i00940pkg2 is function F1(B:in bit) return boolean is begin return false; end; end c10s05b00x00p03n02i00940pkg2; use work.c10s05b00x00p03n02i00940pkg1.all, work.c10s05b00x00p03n02i00940pkg2.all; ENTITY c10s05b00x00p03n02i00940ent IS END c10s05b00x00p03n02i00940ent; ARCHITECTURE c10s05b00x00p03n02i00940arch OF c10s05b00x00p03n02i00940ent IS BEGIN TESTING: PROCESS BEGIN if (F1('1') = F1('0')) then -- No_Failure_here assert FALSE report "*PASSED TEST: c10s05b00x00p03n02i00940" severity NOTE; else assert FALSE report "*FAILED TEST: c10s05b00x00p03n02i00940 - A single interpretation of each constituent of the innermost complete context is not an error." severity ERROR; end if; wait; END PROCESS TESTING; END c10s05b00x00p03n02i00940arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc940.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c10s05b00x00p03n02i00940pkg1 is function F1(B:in integer) return integer; end c10s05b00x00p03n02i00940pkg1; package body c10s05b00x00p03n02i00940pkg1 is function F1(B:in integer) return integer is begin return 1; end; end c10s05b00x00p03n02i00940pkg1; package c10s05b00x00p03n02i00940pkg2 is function F1(B:in bit) return boolean; end c10s05b00x00p03n02i00940pkg2; package body c10s05b00x00p03n02i00940pkg2 is function F1(B:in bit) return boolean is begin return false; end; end c10s05b00x00p03n02i00940pkg2; use work.c10s05b00x00p03n02i00940pkg1.all, work.c10s05b00x00p03n02i00940pkg2.all; ENTITY c10s05b00x00p03n02i00940ent IS END c10s05b00x00p03n02i00940ent; ARCHITECTURE c10s05b00x00p03n02i00940arch OF c10s05b00x00p03n02i00940ent IS BEGIN TESTING: PROCESS BEGIN if (F1('1') = F1('0')) then -- No_Failure_here assert FALSE report "*PASSED TEST: c10s05b00x00p03n02i00940" severity NOTE; else assert FALSE report "*FAILED TEST: c10s05b00x00p03n02i00940 - A single interpretation of each constituent of the innermost complete context is not an error." severity ERROR; end if; wait; END PROCESS TESTING; END c10s05b00x00p03n02i00940arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc940.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c10s05b00x00p03n02i00940pkg1 is function F1(B:in integer) return integer; end c10s05b00x00p03n02i00940pkg1; package body c10s05b00x00p03n02i00940pkg1 is function F1(B:in integer) return integer is begin return 1; end; end c10s05b00x00p03n02i00940pkg1; package c10s05b00x00p03n02i00940pkg2 is function F1(B:in bit) return boolean; end c10s05b00x00p03n02i00940pkg2; package body c10s05b00x00p03n02i00940pkg2 is function F1(B:in bit) return boolean is begin return false; end; end c10s05b00x00p03n02i00940pkg2; use work.c10s05b00x00p03n02i00940pkg1.all, work.c10s05b00x00p03n02i00940pkg2.all; ENTITY c10s05b00x00p03n02i00940ent IS END c10s05b00x00p03n02i00940ent; ARCHITECTURE c10s05b00x00p03n02i00940arch OF c10s05b00x00p03n02i00940ent IS BEGIN TESTING: PROCESS BEGIN if (F1('1') = F1('0')) then -- No_Failure_here assert FALSE report "*PASSED TEST: c10s05b00x00p03n02i00940" severity NOTE; else assert FALSE report "*FAILED TEST: c10s05b00x00p03n02i00940 - A single interpretation of each constituent of the innermost complete context is not an error." severity ERROR; end if; wait; END PROCESS TESTING; END c10s05b00x00p03n02i00940arch;
library ieee; use ieee.std_logic_1164.all; entity ent is port ( clk : in std_logic; set : in std_logic; reset : in std_logic; q : out std_logic ); end; architecture a of ent is signal s : std_logic; begin process(clk, set, reset) begin if set = '1' then s <= '1'; elsif reset = '1' then s <= '0'; elsif rising_edge(clk) then s <= not s; end if; end process; q <= s; end;
-- Algoritmo CORDIC -- (Rehecho de forma iterativa) library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.MATH_REAL.all; library work; use work.cordic_lib.all; entity cordic is generic ( P : natural := 16 -- Cantidad de iteraciones, determina la precisión ); port ( clk : in std_logic; rst : in std_logic; load : in std_logic; x_in, y_in : in t_coord; angle : in t_num; x_rot, y_rot : out t_coord; rotRdy : out std_logic ); end entity cordic; architecture cordic_arq of cordic is constant N_K : natural := N_BITS / 2; constant Nrom : natural := 32; type t_angles is array(natural range <>) of std_logic_vector(N_BITS-1 downto 0); constant ANGLES : t_angles(0 to Nrom-1) := ( -- Nrom primeros valores de atan(2^-i), convertidos std_logic_vector(to_unsigned(integer(round(0.785398163397448278999490867136 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.463647609000806093515478778500 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.244978663126864143473326862477 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.124354994546761438156678991618 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.062418809995957350023054743815 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.031239833430268277442154456480 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.015623728620476831294161534913 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.007812341060101111143987306917 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.003906230131966971757390139075 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.001953122516478818758434155001 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000976562189559319459436492750 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000488281211194898289926213941 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000244140620149361771244744812 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000122070311893670207853065945 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000061035156174208772593501454 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000030517578115526095727154735 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000015258789061315761542377868 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000007629394531101969981038997 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000003814697265606496141750756 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000001907348632810186964779285 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000953674316405960844127631 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000476837158203088842281064 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000238418579101557973667688 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000119209289550780680899739 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000059604644775390552208106 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000029802322387695302573833 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000014901161193847654595639 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000007450580596923828125000 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000003725290298461914062500 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000001862645149230957031250 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000000931322574615478515625 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000000465661287307739257812 * real(2*(N_BITS-0)) / (2.0MATH_PI) )), N_BITS)) ); type t_kvalues is array(natural range <>) of std_logic_vector(N_K-1 downto 0); constant K_VALUES : t_kvalues(0 to Nrom-1) := ( -- Nrom primeros cumprod(1 ./ abs(1 + 1j2.^(-(0:25)))) std_logic_vector(to_signed(integer(round( real(2N_K) 0.707106781186547461715008466854)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.632455532033675771330649695301)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.613571991077896283783843500714)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.608833912517752429138795378094)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607648256256168139977091868786)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607351770141295932425862247328)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607277644093526025592666428565)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607259112298892733683430833480)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607254479332562269178197311703)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607253321089875175431416209904)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607253031529134346122589249717)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252959138944836681162087189)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252941041397154009473524638)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252936517010177830400152743)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935385913406030056194140)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935103139268591121435747)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935032445706475812130520)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935014772288191409188585)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935010353933620308453101)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935009249372733108884859)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935008973260266884608427)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935008904204394752923690)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935008886884915568771248)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935008882666068075195653)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935008881555845050570497)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935008881222778143182950)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935008881222778143182950)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935008881222778143182950)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935008881222778143182950)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935008881222778143182950)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935008881222778143182950)), N_K)), std_logic_vector(to_signed(integer(round( real(2*N_K) 0.607252935008881222778143182950)), N_K)) ); signal x_in_e, x_in_n, x0, x_1, x_2, x_2_sh, x_3, x_4 : t_coord_e := (others => '0'); signal y_in_e, y_in_n, y0, y_1, y_2, y_2_sh, y_3, y_4 : t_coord_e := (others => '0'); signal x_5, y_5 : std_logic_vector((N_EXTR+N_K)-1 downto 0) := (others => '0'); signal angle0, angle_1, angle_2, angle_3 : t_num := (others => '0'); subtype natural_i is natural range 0 to 31; signal i : natural_i := P; signal cuadrante : std_logic_vector(1 downto 0) := "00"; signal angle_i : std_logic_vector(N_BITS-1 downto 0) := (others => '0'); --signal angle_i : unsigned(N_BITS-1 downto 0) := (others => '0'); signal sigma : std_logic := '0'; signal ena_reg : std_logic := '0'; signal stRdy : std_logic := '0'; type t_estado is (IDLE, LOADING, ROTA, RDY); signal estado : t_estado := IDLE; begin -- Extiendo coordenadas x_in_e <= (N_EXTR-N_BITS-1 downto 0 => x_in(N_BITS-1)) & x_in; y_in_e <= (N_EXTR-N_BITS-1 downto 0 => y_in(N_BITS-1)) & y_in; -- Versiones negativas x_in_n <= std_logic_vector(signed(not x_in_e) + 1); y_in_n <= std_logic_vector(signed(not y_in_e) + 1); -- Iterador process(clk, rst, load) begin if rst = '1' then i <= P; estado <= IDLE; elsif rising_edge(clk) then if load = '1' then -- Cargo nueva posición para rotar estado <= LOADING; i <= 0; elsif i < P-2 then -- Sigo rotando estado <= ROTA; i <= i + 1; elsif i = P-2 then -- Terminé de rotar posición estado <= RDY; i <= i + 1; else estado <= IDLE; end if; end if; end process; ena_reg <= '1' when (estado = LOADING or estado = ROTA or load = '1') else '0'; stRdy <= '1' when (estado = RDY) else '0'; -- Averiguo cuadrante con los 2 MSBs del ángulo cuadrante <= angle(N_BITS-1 downto N_BITS-2); -- Rotación inicial (pongo en el cuadrante correcto) x0 <= x_in_e when cuadrante = "00" else y_in_n when cuadrante = "01" else x_in_n when cuadrante = "10" else y_in_e when cuadrante = "11"; y0 <= y_in_e when cuadrante = "00" else x_in_e when cuadrante = "01" else y_in_n when cuadrante = "10" else x_in_n when cuadrante = "11"; angle0 <= "00" & angle(N_BITS-3 downto 0); -- Uso pos nueva si cargando o sigo rotando x_1 <= x0 when load = '1' else x_3; y_1 <= y0 when load = '1' else y_3; angle_1 <= angle0 when load = '1' else angle_3; -- ... reg_x: entity work.registroNb generic map( N => N_EXTR ) port map( clk => clk, rst => rst, ena => ena_reg, d => x_1, q => x_2 ); reg_y: entity work.registroNb generic map( N => N_EXTR ) port map( clk => clk, rst => rst, ena => ena_reg, d => y_1, q => y_2 ); reg_angle: entity work.registroNb generic map( N => N_BITS ) port map( clk => clk, rst => rst, ena => ena_reg, d => angle_1, q => angle_2 ); -- ... bshift_x: entity work.barrel_shifterNb generic map( N => N_EXTR ) port map( to_left => '0', M => i, a => x_2, o => x_2_sh ); bshift_y: entity work.barrel_shifterNb generic map( N => N_EXTR ) port map( to_left => '0', M => i, a => y_2, o => y_2_sh ); -- ... x_3 <= std_logic_vector(unsigned(x_2) + unsigned(y_2_sh)) when sigma = '1' else std_logic_vector(unsigned(x_2) - unsigned(y_2_sh)); y_3 <= std_logic_vector(unsigned(y_2) + unsigned(x_2_sh)) when sigma = '0' else std_logic_vector(unsigned(y_2) - unsigned(x_2_sh)); angle_i <= ANGLES(i); ----ANGLES_DEG(i);---- when (i < ANGLES'length) else ----(angle(ANGLES'length-1) / (2*(i - ANGLES'length + 1))); ------ Si me paso de la tabla, aproximo angle_3 <= std_logic_vector(unsigned(angle_2) + unsigned(angle_i)) when sigma = '1' else std_logic_vector(unsigned(angle_2) - unsigned(angle_i)); -- Signo del ángulo de rotación restante sigma <= angle_2(N_BITS-1) when (estado = ROTA) else '0'; -- ... pipe_reg_x: entity work.registroNb generic map( N => N_EXTR ) port map( clk => clk, rst => rst, ena => '1', d => x_3, q => x_4 ); pipe_reg_y: entity work.registroNb generic map( N => N_EXTR ) port map( clk => clk, rst => rst, ena => '1', d => y_3, q => y_4 ); -- ... delay_Rdy: entity work.ffd port map( clk => clk, rst => rst, ena => '1', d => stRdy, q => rotRdy ); -- Intermedio x_5 <= std_logic_vector( signed(x_4) signed(K_VALUES(i)) ); y_5 <= std_logic_vector( signed(y_4) * signed(K_VALUES(i)) ); -- Salida de la rotación (si rotRdy) x_rot <= x_5(N_EXTR+N_K-3 downto N_EXTR+N_K-3-N_BITS+1); y_rot <= y_5(N_EXTR+N_K-3 downto N_EXTR+N_K-3-N_BITS+1); end cordic_arq;
-- ========== Copyright Header Begin ============================================= -- AmgPacman File: rom.vhd -- Copyright (c) 2015 Alberto Miedes Garcés -- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. -- -- The above named program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- The above named program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with Foobar. If not, see <http://www.gnu.org/licenses/>. -- ========== Copyright Header End =============================================== ---------------------------------------------------------------------------------- -- Engineer: Alberto Miedes Garcés -- Correo: [email protected] -- Create Date: January 2015 -- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent) ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tablero_rom is port ( clk: in std_logic; x : in std_logic_vector(2 downto 0); y : in std_logic_vector(2 downto 0); rgb: out std_logic_vector(2 downto 0) ); end tablero_rom; architecture arq of tablero_rom is type memory_slv is array (0 to 7) of std_logic_vector(2 downto 0); type memory_img is array (0 to 7) of memory_slv; constant rom_img : memory_img := ( ("001","001","001","001","001","001","001","001"), ("001","000","000","000","000","000","000","001"), ("001","000","001","000","000","001","000","001"), ("001","000","000","000","000","000","000","001"), ("001","000","000","000","001","000","000","001"), ("001","000","001","000","000","001","000","001"), ("001","000","000","000","000","000","000","001"), ("001","001","001","001","001","001","001","001") ); begin process(clk,x,y ) begin if clk'event and clk='1' then rgb(2 downto 0) <= rom_img(to_integer(unsigned(y)))(to_integer(unsigned(x)))(2 downto 0); end if; end process; end arq;
-- -------------------------------------------------------------------- -- -- Copyright © 2008 by IEEE. All rights reserved. -- -- This source file is an essential part of IEEE Std 1076-2008, -- IEEE Standard VHDL Language Reference Manual. This source file may not be -- copied, sold, or included with software that is sold without written -- permission from the IEEE Standards Department. This source file may be -- copied for individual use between licensed users. This source file is -- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR -- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE -- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify -- and hold IEEE harmless from any damages or liability arising out of the -- use thereof. -- -- Title : Fixed-point package (Generic package declaration) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: Accellera VHDL-TC and IEEE P1076 Working Group -- : -- Purpose : This packages defines basic binary fixed point -- : arithmetic functions -- : -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- use STD.TEXTIO.all; library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.fixed_float_types.all; package fixed_generic_pkg is generic ( -- Rounding routine to use in fixed point, fixed_round or fixed_truncate fixed_round_style : fixed_round_style_type := fixed_round; -- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap fixed_overflow_style : fixed_overflow_style_type := fixed_saturate; -- Extra bits used in divide routines fixed_guard_bits : NATURAL := 3; -- If TRUE, then turn off warnings on "X" propagation no_warning : BOOLEAN := false ); -- Author David Bishop ([email protected]) constant CopyRightNotice : STRING := "Copyright 2008 by IEEE. All rights reserved."; -- base Unsigned fixed point type, downto direction assumed type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC; -- base Signed fixed point type, downto direction assumed type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC; alias U_ufixed is UNRESOLVED_ufixed; alias U_sfixed is UNRESOLVED_sfixed; subtype ufixed is (resolved) UNRESOLVED_ufixed; subtype sfixed is (resolved) UNRESOLVED_sfixed; --=========================================================================== -- Arithmetic Operators: --=========================================================================== -- Absolute value, 2's complement -- abs sfixed(a downto b) = sfixed(a+1 downto b) function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- Negation, 2's complement -- - sfixed(a downto b) = sfixed(a+1 downto b) function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed; -- Addition -- ufixed(a downto b) + ufixed(c downto d) -- = ufixed(maximum(a,c)+1 downto minimum(b,d)) function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- sfixed(a downto b) + sfixed(c downto d) -- = sfixed(maximum(a,c)+1 downto minimum(b,d)) function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- Subtraction -- ufixed(a downto b) - ufixed(c downto d) -- = ufixed(maximum(a,c)+1 downto minimum(b,d)) function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- sfixed(a downto b) - sfixed(c downto d) -- = sfixed(maximum(a,c)+1 downto minimum(b,d)) function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- Multiplication -- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d) function "" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- sfixed(a downto b) sfixed(c downto d) = sfixed(a+c+1 downto b+d) function "" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- Division -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1) function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c) function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- Remainder -- ufixed (a downto b) rem ufixed (c downto d) -- = ufixed (minimum(a,c) downto minimum(b,d)) function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- sfixed (a downto b) rem sfixed (c downto d) -- = sfixed (minimum(a,c) downto minimum(b,d)) function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- Modulo -- ufixed (a downto b) mod ufixed (c downto d) -- = ufixed (minimum(a,c) downto minimum(b, d)) function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- sfixed (a downto b) mod sfixed (c downto d) -- = sfixed (c downto minimum(b, d)) function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; ---------------------------------------------------------------------------- -- In these routines the "real" or "natural" (integer) -- are converted into a fixed point number and then the operation is -- performed. It is assumed that the array will be large enough. -- If the input is "real" then the real number is converted into a fixed of -- the same size as the fixed point input. If the number is an "integer" -- then it is converted into fixed with the range (l'high downto 0). ---------------------------------------------------------------------------- -- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b) function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; -- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d) function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b)) function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d)) function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b) function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; -- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d) function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b)) function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d)) function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed(a downto b) ufixed(a downto b) = ufixed(2a+1 downto 2b) function "" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; -- ufixed(c downto d) ufixed(c downto d) = ufixed(2c+1 downto 2d) function "" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed (a downto b) ufixed (a downto 0) = ufixed (2a+1 downto b) function "" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; -- ufixed (a downto b) ufixed (a downto 0) = ufixed (2a+1 downto b) function "" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1) function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1) function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1) function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; -- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1) function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b) function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; -- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d) function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0)) function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; -- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0)) function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b) function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; -- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d) function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0)) function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; -- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0)) function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b) function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; -- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d) function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b)) function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; -- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d)) function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b) function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; -- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d) function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b)) function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; -- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d)) function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed(a downto b) sfixed(a downto b) = sfixed(2a+1 downto 2b) function "" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; -- sfixed(c downto d) sfixed(c downto d) = sfixed(2c+1 downto 2d) function "" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed(a downto b) sfixed(a downto 0) = sfixed(2a+1 downto b) function "" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; -- sfixed(c downto 0) sfixed(c downto d) = sfixed(2c+1 downto d) function "" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a) function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; -- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c) function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a) function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; -- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c) function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b) function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; -- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d) function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0)) function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; -- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0)) function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b) function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; -- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d) function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0)) function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; -- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0)) function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- This version of divide gives the user more control -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1) function divide ( l, r : UNRESOLVED_ufixed; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_ufixed; -- This version of divide gives the user more control -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c) function divide ( l, r : UNRESOLVED_sfixed; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_sfixed; -- These functions return 1/X -- 1 / ufixed(a downto b) = ufixed(-b downto -a-1) function reciprocal ( arg : UNRESOLVED_ufixed; -- fixed point input constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_ufixed; -- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a) function reciprocal ( arg : UNRESOLVED_sfixed; -- fixed point input constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_sfixed; -- REM function -- ufixed (a downto b) rem ufixed (c downto d) -- = ufixed (minimum(a,c) downto minimum(b,d)) function remainder ( l, r : UNRESOLVED_ufixed; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_ufixed; -- sfixed (a downto b) rem sfixed (c downto d) -- = sfixed (minimum(a,c) downto minimum(b,d)) function remainder ( l, r : UNRESOLVED_sfixed; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_sfixed; -- mod function -- ufixed (a downto b) mod ufixed (c downto d) -- = ufixed (minimum(a,c) downto minimum(b, d)) function modulo ( l, r : UNRESOLVED_ufixed; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_ufixed; -- sfixed (a downto b) mod sfixed (c downto d) -- = sfixed (c downto minimum(b, d)) function modulo ( l, r : UNRESOLVED_sfixed; constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_sfixed; -- Procedure for those who need an "accumulator" function. -- add_carry (ufixed(a downto b), ufixed (c downto d)) -- = ufixed (maximum(a,c) downto minimum(b,d)) procedure add_carry ( L, R : in UNRESOLVED_ufixed; c_in : in STD_ULOGIC; result : out UNRESOLVED_ufixed; c_out : out STD_ULOGIC); -- add_carry (sfixed(a downto b), sfixed (c downto d)) -- = sfixed (maximum(a,c) downto minimum(b,d)) procedure add_carry ( L, R : in UNRESOLVED_sfixed; c_in : in STD_ULOGIC; result : out UNRESOLVED_sfixed; c_out : out STD_ULOGIC); -- Scales the result by a power of 2. Width of input = width of output with -- the binary point moved. function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed; function scalb (y : UNRESOLVED_ufixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_ufixed; function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed; function scalb (y : UNRESOLVED_sfixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_sfixed; function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN; --=========================================================================== -- Comparison Operators --=========================================================================== function ">" (l, r : UNRESOLVED_ufixed) return BOOLEAN; function ">" (l, r : UNRESOLVED_sfixed) return BOOLEAN; function "<" (l, r : UNRESOLVED_ufixed) return BOOLEAN; function "<" (l, r : UNRESOLVED_sfixed) return BOOLEAN; function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN; function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN; function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN; function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN; function "=" (l, r : UNRESOLVED_ufixed) return BOOLEAN; function "=" (l, r : UNRESOLVED_sfixed) return BOOLEAN; function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN; function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN; function "?=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?/=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?>" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?>=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?<" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?<=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?/=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?>" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?>=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?<" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?<=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN; function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN; -- Overloads the default "maximum" and "minimum" function function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; ---------------------------------------------------------------------------- -- In these compare functions a natural is converted into a -- fixed point number of the bounds "maximum(l'high,0) downto 0" ---------------------------------------------------------------------------- function "=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; function ">" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; function "<" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; function "=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; function ">" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "<" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "?=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; function "?/=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; function "?>=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; function "?<=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; function "?>" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; function "?<" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; function "?=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?/=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?>=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?<=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?>" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?<" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function maximum (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; function minimum (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; function maximum (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function minimum (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; ---------------------------------------------------------------------------- -- In these compare functions a real is converted into a -- fixed point number of the bounds "l'high+1 downto l'low" ---------------------------------------------------------------------------- function "=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; function ">" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; function "<" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; function "=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; function ">" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "<" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "?=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; function "?/=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; function "?>=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; function "?<=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; function "?>" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; function "?<" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; function "?=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?/=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?>=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?<=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?>" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?<" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; ---------------------------------------------------------------------------- -- In these compare functions an integer is converted into a -- fixed point number of the bounds "maximum(l'high,1) downto 0" ---------------------------------------------------------------------------- function "=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; function ">" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; function "<" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; function "=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; function ">" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; function "<" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; function "?=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; function "?/=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; function "?>=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; function "?<=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; function "?>" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; function "?<" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; function "?=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?/=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?>=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?<=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?>" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?<" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; function maximum (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; function maximum (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function minimum (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; function minimum (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; ---------------------------------------------------------------------------- -- In these compare functions a real is converted into a -- fixed point number of the bounds "l'high+1 downto l'low" ---------------------------------------------------------------------------- function "=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; function ">" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; function "<" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; function "=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; function ">" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; function "<" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; function "?=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; function "?/=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; function "?>=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; function "?<=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; function "?>" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; function "?<" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; function "?=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?/=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?>=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?<=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?>" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?<" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; --=========================================================================== -- Shift and Rotate Functions. -- Note that sra and sla are not the same as the BIT_VECTOR version --=========================================================================== function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) return UNRESOLVED_ufixed; function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) return UNRESOLVED_ufixed; function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) return UNRESOLVED_ufixed; function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) return UNRESOLVED_ufixed; function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) return UNRESOLVED_ufixed; function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) return UNRESOLVED_ufixed; function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) return UNRESOLVED_sfixed; function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) return UNRESOLVED_sfixed; function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) return UNRESOLVED_sfixed; function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) return UNRESOLVED_sfixed; function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) return UNRESOLVED_sfixed; function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) return UNRESOLVED_sfixed; function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL) return UNRESOLVED_ufixed; function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL) return UNRESOLVED_ufixed; function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL) return UNRESOLVED_sfixed; function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL) return UNRESOLVED_sfixed; ---------------------------------------------------------------------------- -- logical functions ---------------------------------------------------------------------------- function "not" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "and" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "or" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "nor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "xor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "not" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "and" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "or" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "nor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "xor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- Vector and std_ulogic functions, same as functions in numeric_std function "and" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "and" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) return UNRESOLVED_ufixed; function "or" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "or" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) return UNRESOLVED_ufixed; function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) return UNRESOLVED_ufixed; function "nor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "nor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) return UNRESOLVED_ufixed; function "xor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "xor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) return UNRESOLVED_ufixed; function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) return UNRESOLVED_ufixed; function "and" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "and" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) return UNRESOLVED_sfixed; function "or" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "or" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) return UNRESOLVED_sfixed; function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) return UNRESOLVED_sfixed; function "nor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "nor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) return UNRESOLVED_sfixed; function "xor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "xor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) return UNRESOLVED_sfixed; function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) return UNRESOLVED_sfixed; -- Reduction operators, same as numeric_std functions function "and" (l : UNRESOLVED_ufixed) return STD_ULOGIC; function "nand" (l : UNRESOLVED_ufixed) return STD_ULOGIC; function "or" (l : UNRESOLVED_ufixed) return STD_ULOGIC; function "nor" (l : UNRESOLVED_ufixed) return STD_ULOGIC; function "xor" (l : UNRESOLVED_ufixed) return STD_ULOGIC; function "xnor" (l : UNRESOLVED_ufixed) return STD_ULOGIC; function "and" (l : UNRESOLVED_sfixed) return STD_ULOGIC; function "nand" (l : UNRESOLVED_sfixed) return STD_ULOGIC; function "or" (l : UNRESOLVED_sfixed) return STD_ULOGIC; function "nor" (l : UNRESOLVED_sfixed) return STD_ULOGIC; function "xor" (l : UNRESOLVED_sfixed) return STD_ULOGIC; function "xnor" (l : UNRESOLVED_sfixed) return STD_ULOGIC; -- returns arg'low-1 if not found function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC) return INTEGER; function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC) return INTEGER; -- returns arg'high+1 if not found function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC) return INTEGER; function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC) return INTEGER; --=========================================================================== -- RESIZE Functions --=========================================================================== -- resizes the number (larger or smaller) -- The returned result will be ufixed (left_index downto right_index) -- If "round_style" is fixed_round, then the result will be rounded. -- If the MSB of the remainder is a "1" AND the LSB of the unrounded result -- is a '1' or the lower bits of the remainder include a '1' then the result -- will be increased by the smallest representable number for that type. -- "overflow_style" can be fixed_saturate or fixed_wrap. -- In saturate mode, if the number overflows then the largest possible -- representable number is returned. If wrap mode, then the upper bits -- of the number are truncated. function resize ( arg : UNRESOLVED_ufixed; -- input constant left_index : INTEGER; -- integer portion constant right_index : INTEGER; -- size of fraction constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_ufixed; -- "size_res" functions create the size of the output from the indices -- of the "size_res" input. The actual value of "size_res" is not used. function resize ( arg : UNRESOLVED_ufixed; -- input size_res : UNRESOLVED_ufixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_ufixed; -- Note that in "wrap" mode the sign bit is not replicated. Thus the -- resize of a negative number can have a positive result in wrap mode. function resize ( arg : UNRESOLVED_sfixed; -- input constant left_index : INTEGER; -- integer portion constant right_index : INTEGER; -- size of fraction constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_sfixed; function resize ( arg : UNRESOLVED_sfixed; -- input size_res : UNRESOLVED_sfixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_sfixed; --=========================================================================== -- Conversion Functions --=========================================================================== -- integer (natural) to unsigned fixed point. -- arguments are the upper and lower bounds of the number, thus -- ufixed (7 downto -3) <= to_ufixed (int, 7, -3); function to_ufixed ( arg : NATURAL; -- integer constant left_index : INTEGER; -- left index (high index) constant right_index : INTEGER := 0; -- right index constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_ufixed; function to_ufixed ( arg : NATURAL; -- integer size_res : UNRESOLVED_ufixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_ufixed; -- real to unsigned fixed point function to_ufixed ( arg : REAL; -- real constant left_index : INTEGER; -- left index (high index) constant right_index : INTEGER; -- right index constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_ufixed; function to_ufixed ( arg : REAL; -- real size_res : UNRESOLVED_ufixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_ufixed; -- unsigned to unsigned fixed point function to_ufixed ( arg : UNRESOLVED_UNSIGNED; -- unsigned constant left_index : INTEGER; -- left index (high index) constant right_index : INTEGER := 0; -- right index constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_ufixed; function to_ufixed ( arg : UNRESOLVED_UNSIGNED; -- unsigned size_res : UNRESOLVED_ufixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_ufixed; -- Performs a conversion. ufixed (arg'range) is returned function to_ufixed ( arg : UNRESOLVED_UNSIGNED) -- unsigned return UNRESOLVED_ufixed; -- unsigned fixed point to unsigned function to_unsigned ( arg : UNRESOLVED_ufixed; -- fixed point input constant size : NATURAL; -- length of output constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_UNSIGNED; -- unsigned fixed point to unsigned function to_unsigned ( arg : UNRESOLVED_ufixed; -- fixed point input size_res : UNRESOLVED_UNSIGNED; -- used for length of output constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_UNSIGNED; -- unsigned fixed point to real function to_real ( arg : UNRESOLVED_ufixed) -- fixed point input return REAL; -- unsigned fixed point to integer function to_integer ( arg : UNRESOLVED_ufixed; -- fixed point input constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return NATURAL; -- Integer to UNRESOLVED_sfixed function to_sfixed ( arg : INTEGER; -- integer constant left_index : INTEGER; -- left index (high index) constant right_index : INTEGER := 0; -- right index constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_sfixed; function to_sfixed ( arg : INTEGER; -- integer size_res : UNRESOLVED_sfixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_sfixed; -- Real to sfixed function to_sfixed ( arg : REAL; -- real constant left_index : INTEGER; -- left index (high index) constant right_index : INTEGER; -- right index constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_sfixed; function to_sfixed ( arg : REAL; -- real size_res : UNRESOLVED_sfixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_sfixed; -- signed to sfixed function to_sfixed ( arg : UNRESOLVED_SIGNED; -- signed constant left_index : INTEGER; -- left index (high index) constant right_index : INTEGER := 0; -- right index constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_sfixed; function to_sfixed ( arg : UNRESOLVED_SIGNED; -- signed size_res : UNRESOLVED_sfixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_sfixed; -- signed to sfixed (output assumed to be size of signed input) function to_sfixed ( arg : UNRESOLVED_SIGNED) -- signed return UNRESOLVED_sfixed; -- Conversion from ufixed to sfixed function to_sfixed ( arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed; -- signed fixed point to signed function to_signed ( arg : UNRESOLVED_sfixed; -- fixed point input constant size : NATURAL; -- length of output constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_SIGNED; -- signed fixed point to signed function to_signed ( arg : UNRESOLVED_sfixed; -- fixed point input size_res : UNRESOLVED_SIGNED; -- used for length of output constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_SIGNED; -- signed fixed point to real function to_real ( arg : UNRESOLVED_sfixed) -- fixed point input return REAL; -- signed fixed point to integer function to_integer ( arg : UNRESOLVED_sfixed; -- fixed point input constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return INTEGER; -- Because of the fairly complicated sizing rules in the fixed point -- packages these functions are provided to compute the result ranges -- Example: -- signal uf1 : ufixed (3 downto -3); -- signal uf2 : ufixed (4 downto -2); -- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '', 4, -2) downto -- ufixed_low (3, -3, '', 4, -2)); -- uf1multuf2 <= uf1 uf2; -- Valid characters: '+', '-', '', '/', 'r' or 'R' (rem), 'm' or 'M' (mod), -- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -) function ufixed_high (left_index, right_index : INTEGER; operation : CHARACTER := 'X'; left_index2, right_index2 : INTEGER := 0) return INTEGER; function ufixed_low (left_index, right_index : INTEGER; operation : CHARACTER := 'X'; left_index2, right_index2 : INTEGER := 0) return INTEGER; function sfixed_high (left_index, right_index : INTEGER; operation : CHARACTER := 'X'; left_index2, right_index2 : INTEGER := 0) return INTEGER; function sfixed_low (left_index, right_index : INTEGER; operation : CHARACTER := 'X'; left_index2, right_index2 : INTEGER := 0) return INTEGER; -- Same as above, but using the "size_res" input only for their ranges: -- signal uf1multuf2 : ufixed (ufixed_high (uf1, '', uf2) downto -- ufixed_low (uf1, '', uf2)); -- uf1multuf2 <= uf1 uf2; -- function ufixed_high (size_res : UNRESOLVED_ufixed; operation : CHARACTER := 'X'; size_res2 : UNRESOLVED_ufixed) return INTEGER; function ufixed_low (size_res : UNRESOLVED_ufixed; operation : CHARACTER := 'X'; size_res2 : UNRESOLVED_ufixed) return INTEGER; function sfixed_high (size_res : UNRESOLVED_sfixed; operation : CHARACTER := 'X'; size_res2 : UNRESOLVED_sfixed) return INTEGER; function sfixed_low (size_res : UNRESOLVED_sfixed; operation : CHARACTER := 'X'; size_res2 : UNRESOLVED_sfixed) return INTEGER; -- purpose: returns a saturated number function saturate ( constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_ufixed; -- purpose: returns a saturated number function saturate ( constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_sfixed; function saturate ( size_res : UNRESOLVED_ufixed) -- only the size of this is used return UNRESOLVED_ufixed; function saturate ( size_res : UNRESOLVED_sfixed) -- only the size of this is used return UNRESOLVED_sfixed; --=========================================================================== -- Translation Functions --=========================================================================== -- maps meta-logical values function to_01 ( s : UNRESOLVED_ufixed; -- fixed point input constant XMAP : STD_ULOGIC := '0') -- Map x to return UNRESOLVED_ufixed; -- maps meta-logical values function to_01 ( s : UNRESOLVED_sfixed; -- fixed point input constant XMAP : STD_ULOGIC := '0') -- Map x to return UNRESOLVED_sfixed; function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN; function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN; function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- straight vector conversion routines, needed for synthesis. -- These functions are here so that a std_logic_vector can be -- converted to and from sfixed and ufixed. Note that you can -- not convert these vectors because of their negative index. function to_slv ( arg : UNRESOLVED_ufixed) -- fixed point vector return STD_LOGIC_VECTOR; alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed return STD_LOGIC_VECTOR]; alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed return STD_LOGIC_VECTOR]; function to_slv ( arg : UNRESOLVED_sfixed) -- fixed point vector return STD_LOGIC_VECTOR; alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed return STD_LOGIC_VECTOR]; alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed return STD_LOGIC_VECTOR]; function to_sulv ( arg : UNRESOLVED_ufixed) -- fixed point vector return STD_ULOGIC_VECTOR; alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed return STD_ULOGIC_VECTOR]; alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed return STD_ULOGIC_VECTOR]; function to_sulv ( arg : UNRESOLVED_sfixed) -- fixed point vector return STD_ULOGIC_VECTOR; alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed return STD_ULOGIC_VECTOR]; alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed return STD_ULOGIC_VECTOR]; function to_ufixed ( arg : STD_ULOGIC_VECTOR; -- shifted vector constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_ufixed; function to_ufixed ( arg : STD_ULOGIC_VECTOR; -- shifted vector size_res : UNRESOLVED_ufixed) -- for size only return UNRESOLVED_ufixed; function to_sfixed ( arg : STD_ULOGIC_VECTOR; -- shifted vector constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_sfixed; function to_sfixed ( arg : STD_ULOGIC_VECTOR; -- shifted vector size_res : UNRESOLVED_sfixed) -- for size only return UNRESOLVED_sfixed; -- As a concession to those who use a graphical DSP environment, -- these functions take parameters in those tools format and create -- fixed point numbers. These functions are designed to convert from -- a std_logic_vector to the VHDL fixed point format using the conventions -- of these packages. In a pure VHDL environment you should use the -- "to_ufixed" and "to_sfixed" routines. -- unsigned fixed point function to_UFix ( arg : STD_ULOGIC_VECTOR; width : NATURAL; -- width of vector fraction : NATURAL) -- width of fraction return UNRESOLVED_ufixed; -- signed fixed point function to_SFix ( arg : STD_ULOGIC_VECTOR; width : NATURAL; -- width of vector fraction : NATURAL) -- width of fraction return UNRESOLVED_sfixed; -- finding the bounds of a number. These functions can be used like this: -- signal xxx : ufixed (7 downto -3); -- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))" -- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3) -- downto UFix_low(11, 3, "+", 11, 3)); -- Where "11" is the width of xxx (xxx'length), -- and 3 is the lower bound (abs (xxx'low)) -- In a pure VHDL environment use "ufixed_high" and "ufixed_low" function UFix_high (width, fraction : NATURAL; operation : CHARACTER := 'X'; width2, fraction2 : NATURAL := 0) return INTEGER; function UFix_low (width, fraction : NATURAL; operation : CHARACTER := 'X'; width2, fraction2 : NATURAL := 0) return INTEGER; -- Same as above but for signed fixed point. Note that the width -- of a signed fixed point number ignores the sign bit, thus -- width = sxxx'length-1 function SFix_high (width, fraction : NATURAL; operation : CHARACTER := 'X'; width2, fraction2 : NATURAL := 0) return INTEGER; function SFix_low (width, fraction : NATURAL; operation : CHARACTER := 'X'; width2, fraction2 : NATURAL := 0) return INTEGER; --=========================================================================== -- string and textio Functions --=========================================================================== -- purpose: writes fixed point into a line procedure WRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_ufixed; -- fixed point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); -- purpose: writes fixed point into a line procedure WRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_sfixed; -- fixed point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); procedure READ(L : inout LINE; VALUE : out UNRESOLVED_ufixed); procedure READ(L : inout LINE; VALUE : out UNRESOLVED_ufixed; GOOD : out BOOLEAN); procedure READ(L : inout LINE; VALUE : out UNRESOLVED_sfixed); procedure READ(L : inout LINE; VALUE : out UNRESOLVED_sfixed; GOOD : out BOOLEAN); alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width]; alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width]; alias bread is READ [LINE, UNRESOLVED_ufixed]; alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN]; alias bread is READ [LINE, UNRESOLVED_sfixed]; alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN]; alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width]; alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width]; alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN]; alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed]; alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN]; alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed]; -- octal read and write procedure OWRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_ufixed; -- fixed point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); procedure OWRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_sfixed; -- fixed point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_ufixed); procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_ufixed; GOOD : out BOOLEAN); procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_sfixed); procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_sfixed; GOOD : out BOOLEAN); alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN]; alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed]; alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN]; alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed]; alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH]; alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH]; -- hex read and write procedure HWRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_ufixed; -- fixed point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); -- purpose: writes fixed point into a line procedure HWRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_sfixed; -- fixed point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); procedure HREAD(L : inout LINE; VALUE : out UNRESOLVED_ufixed); procedure HREAD(L : inout LINE; VALUE : out UNRESOLVED_ufixed; GOOD : out BOOLEAN); procedure HREAD(L : inout LINE; VALUE : out UNRESOLVED_sfixed); procedure HREAD(L : inout LINE; VALUE : out UNRESOLVED_sfixed; GOOD : out BOOLEAN); alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN]; alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN]; alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed]; alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed]; alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH]; alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH]; -- returns a string, useful for: -- assert (x = y) report "error found " & to_string(x) severity error; function to_string (value : UNRESOLVED_ufixed) return STRING; alias to_bstring is to_string [UNRESOLVED_ufixed return STRING]; alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING]; function to_ostring (value : UNRESOLVED_ufixed) return STRING; alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING]; function to_hstring (value : UNRESOLVED_ufixed) return STRING; alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING]; function to_string (value : UNRESOLVED_sfixed) return STRING; alias to_bstring is to_string [UNRESOLVED_sfixed return STRING]; alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING]; function to_ostring (value : UNRESOLVED_sfixed) return STRING; alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING]; function to_hstring (value : UNRESOLVED_sfixed) return STRING; alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING]; -- From string functions allow you to convert a string into a fixed -- point number. Example: -- signal uf1 : ufixed (3 downto -3); -- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5 -- The "." is optional in this syntax, however it exist and is -- in the wrong location an error is produced. Overflow will -- result in saturation. function from_string ( bstring : STRING; -- binary string constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_ufixed; alias from_bstring is from_string [STRING, INTEGER, INTEGER return UNRESOLVED_ufixed]; alias from_binary_string is from_string [STRING, INTEGER, INTEGER return UNRESOLVED_ufixed]; -- Octal and hex conversions work as follows: -- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped) -- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped) function from_ostring ( ostring : STRING; -- Octal string constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_ufixed; alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER return UNRESOLVED_ufixed]; function from_hstring ( hstring : STRING; -- hex string constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_ufixed; alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER return UNRESOLVED_ufixed]; function from_string ( bstring : STRING; -- binary string constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_sfixed; alias from_bstring is from_string [STRING, INTEGER, INTEGER return UNRESOLVED_sfixed]; alias from_binary_string is from_string [STRING, INTEGER, INTEGER return UNRESOLVED_sfixed]; function from_ostring ( ostring : STRING; -- Octal string constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_sfixed; alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER return UNRESOLVED_sfixed]; function from_hstring ( hstring : STRING; -- hex string constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_sfixed; alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER return UNRESOLVED_sfixed]; -- Same as above, "size_res" is used for it's range only. function from_string ( bstring : STRING; -- binary string size_res : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; alias from_bstring is from_string [STRING, UNRESOLVED_ufixed return UNRESOLVED_ufixed]; alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed return UNRESOLVED_ufixed]; function from_ostring ( ostring : STRING; -- Octal string size_res : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed return UNRESOLVED_ufixed]; function from_hstring ( hstring : STRING; -- hex string size_res : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed return UNRESOLVED_ufixed]; function from_string ( bstring : STRING; -- binary string size_res : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; alias from_bstring is from_string [STRING, UNRESOLVED_sfixed return UNRESOLVED_sfixed]; alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed return UNRESOLVED_sfixed]; function from_ostring ( ostring : STRING; -- Octal string size_res : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed return UNRESOLVED_sfixed]; function from_hstring ( hstring : STRING; -- hex string size_res : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed return UNRESOLVED_sfixed]; -- Direct conversion functions. Example: -- signal uf1 : ufixed (3 downto -3); -- uf1 <= from_string ("0110.100"); -- 6.5 -- In this case the "." is not optional, and the size of -- the output must match exactly. function from_string ( bstring : STRING) -- binary string return UNRESOLVED_ufixed; alias from_bstring is from_string [STRING return UNRESOLVED_ufixed]; alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed]; -- Direct octal and hex conversion functions. In this case -- the string lengths must match. Example: -- signal sf1 := sfixed (5 downto -3); -- sf1 <= from_ostring ("71.4") -- -6.5 function from_ostring ( ostring : STRING) -- Octal string return UNRESOLVED_ufixed; alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed]; function from_hstring ( hstring : STRING) -- hex string return UNRESOLVED_ufixed; alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed]; function from_string ( bstring : STRING) -- binary string return UNRESOLVED_sfixed; alias from_bstring is from_string [STRING return UNRESOLVED_sfixed]; alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed]; function from_ostring ( ostring : STRING) -- Octal string return UNRESOLVED_sfixed; alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed]; function from_hstring ( hstring : STRING) -- hex string return UNRESOLVED_sfixed; alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed]; end package fixed_generic_pkg;

constant SPIFSMLength : integer := 1295; constant SPIFSMCfg : std_logic_vector(SPIFSMLength-1 downto 0) := "00001001110000100110010000010000000000000111000000001010101000000100101000000110000110000010010000100011100100000010011000100000000000010001000000000001110000000000000000100100011000000100100000000010000000010100010000000010100001000100000000110010000000010010000010001100000010100001100000000100000000011000000100101001000010001000000010000000000011001010000010010100000100100000000110001000001000010000001010000000100100001000010001000000010100000001010010100000000010000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000";

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-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_2 Core - Top File for the Example Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- Filename: ram_16x1k_sp_tb.vhd -- Description: -- Testbench Top -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.ALL; ENTITY ram_16x1k_sp_tb IS END ENTITY; ARCHITECTURE ram_16x1k_sp_tb_ARCH OF ram_16x1k_sp_tb IS SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL CLK : STD_LOGIC := '1'; SIGNAL RESET : STD_LOGIC; BEGIN CLK_GEN: PROCESS BEGIN CLK <= NOT CLK; WAIT FOR 100 NS; CLK <= NOT CLK; WAIT FOR 100 NS; END PROCESS; RST_GEN: PROCESS BEGIN RESET <= '1'; WAIT FOR 1000 NS; RESET <= '0'; WAIT; END PROCESS; --STOP_SIM: PROCESS BEGIN -- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS -- ASSERT FALSE -- REPORT "END SIMULATION TIME REACHED" -- SEVERITY FAILURE; --END PROCESS; -- PROCESS BEGIN WAIT UNTIL STATUS(8)='1'; IF( STATUS(7 downto 0)/="0") THEN ASSERT false REPORT "Simulation Failed" SEVERITY FAILURE; ELSE ASSERT false REPORT "Test Completed Successfully" SEVERITY FAILURE; END IF; END PROCESS; ram_16x1k_sp_synth_inst:ENTITY work.ram_16x1k_sp_synth PORT MAP( CLK_IN => CLK, RESET_IN => RESET, STATUS => STATUS ); END ARCHITECTURE;

architecture RTL of FIFO is shared variable shar_var1 : integer; begin process variable var1 : integer; begin end process; end architecture RTL; -- Violations below architecture RTL of FIFO is shared variable shar_var1 : integer; begin process variable var1 : integer; begin end process; end architecture RTL;

architecture rtl of fifo is begin process begin my_signal := '1' when input = "00" else my_signal2 or my_sig3 when input = "01" else my_sig4 and my_sig5 when input = "10" else '0'; my_signal := '1' when input = "0000" else my_signal2 or my_sig3 when input = "0100" and input = "1100" else my_sig4 when input = "0010" else '0'; my_signal := '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else '0' when input(3 downto 0) = "0010" else 'Z'; my_signal := '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else '0' when input(3 downto 0) = "0010" else 'Z'; my_signal := '1' when a = "0000" and func1(345) or b = "1000" and func2(567) and c = "00" else sig1 when a = "1000" and func2(560) and b = "0010" else '0'; my_signal := '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; -- Testing no code after assignment my_signal := '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; my_signal := (others => '0') when input(1 downto 0) = "00" and func1(func2(G_VALUE1), to_integer(cons1(37 downto 0))) = 256 else my_signal when input(3 downto 0) = "0010" else 'Z'; end process; end architecture rtl;

-- DDR2 memory interface -- Andrew Read, March 2016 -- This project is based on a working DDR2 interface very kindly donated by a friend LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_textio.all; entity SDRAM_CTRL is port ( CLK : in std_logic; -- 125MHz clock CLK_130 : in std_logic; -- 125MHz clock 130 degree phase shift reset : in std_logic; wrrd_ba_add : in std_logic_vector(2 downto 0); -- bank address wrrd_ras_add : in std_logic_vector(12 downto 0); -- row address wrrd_cas_add : in std_logic_vector(8 downto 0); -- column address -- this is technically a 16-bit word address but SDRAM_PHY ignores the least significant bit of the column address -- so the address space is effectively 32-bit word addressable wr_we : in std_logic_vector(3 downto 0); wr_add : in std_logic_vector(25 downto 0); -- not used wr_dat : in std_logic_vector(31 downto 0); wr_ack : out std_logic; rd_re : in std_logic; rd_add : in std_logic_vector(25 downto 0); -- not used rd_dat : out std_logic_vector(31 downto 0); rd_ack : out std_logic; rd_valid : out std_logic; SDRAM_A : out std_logic_vector(13 downto 0); SDRAM_BA : out std_logic_vector(2 downto 0); SDRAM_CKE : out std_logic; SDRAM_CK : out std_logic; SDRAM_nCK : out std_logic; SDRAM_DQ : inout std_logic_vector(15 downto 0); SDRAM_DQS : inout std_logic_vector(1 downto 0); --SDRAM_nDQS : inout std_logic_vector(1 downto 0); SDRAM_DM : out std_logic_vector(1 downto 0); SDRAM_nCAS : out std_logic; SDRAM_nCS : out std_logic; SDRAM_nRAS : out std_logic; SDRAM_nWE : out std_logic); end SDRAM_CTRL; architecture Struct of SDRAM_CTRL is component SDRAM_PHYIO is port ( CLK : in std_logic; CLK_130 : in std_logic; reset : in std_logic; wrrd_ba_add : in std_logic_vector(2 downto 0); wrrd_ras_add : in std_logic_vector(12 downto 0); wrrd_cas_add : in std_logic_vector(8 downto 0); wr_we : in std_logic_vector(3 downto 0); wr_add : in std_logic_vector(25 downto 0); wr_dat : in std_logic_vector(31 downto 0); wr_ack : out std_logic; rd_re : in std_logic; rd_add : in std_logic_vector(25 downto 0); rd_dat : out std_logic_vector(31 downto 0); rd_ack : out std_logic; rd_valid : out std_logic; refresh : in std_logic; ref_ack : out std_logic; SDRAM_A : out std_logic_vector(13 downto 0); SDRAM_BA : out std_logic_vector(2 downto 0); SDRAM_CKE : out std_logic; SDRAM_CK : out std_logic; SDRAM_nCK : out std_logic; SDRAM_DQ : inout std_logic_vector(15 downto 0); SDRAM_DQS : inout std_logic_vector(1 downto 0); --SDRAM_nDQS : inout std_logic_vector(1 downto 0); SDRAM_DM : out std_logic_vector(1 downto 0); SDRAM_nCAS : out std_logic; SDRAM_nCS : out std_logic; SDRAM_nRAS : out std_logic; SDRAM_nWE : out std_logic); end component; ---------------------------------------------------- -- Refresh parameters ---------------------------------------------------- -- This module, SDRAM_CTRL, raises a refresh request each refreshInterval clock cycles -- SDRAM_PHY issues refreshCount consecutive REFRESH commands in response to each refresh request -- Each REFRESH command takes at least tRFC = 127.5 ns -- The refresh period of the MT47H64M16HR-25E is 64ms, thus to comply with the specification -- refreshInterval * ( refreshCount [defined in SDRAM_PHYIO.vhd] + 1 ) * clock_period <= 64ms -- Example refresh strategies at 125MHz (based on a 7.2us clock period including allowance) -- 1. Refresh the entire SDRAM once each 64ms, blocking the device for 1ms each time -- constant refreshInterval : integer range 0 to 16777215 := 8888888; -- constant refreshCount : integer range 0 to 8191 := 8191; -- -- 2. Refresh the entire SDRAM once each 0.75ms, blocking the device for 12.5us each time -- constant refreshInterval : integer range 0 to 16777215 := 54000; -- constant refreshCount : integer range 0 to 8191 := 95; -- -- 3. Refresh the SRDRAM once each 62.5us, blocking the device for 1us each time -- constant refreshInterval : integer range 0 to 16777215 := 4500; -- constant refreshCount : integer range 0 to 8191 := 7; constant refreshInterval : integer range 0 to 16777215 := 4500; -- number of clock cycles between each refresh request signal refresh_time_cnt : integer range 0 to 16777215; signal refresh : std_logic; signal ref_ack : std_logic; begin ----------------------------------------------------- -- Refresh Mechanism ----------------------------------------------------- refresh_gen : process (CLK, reset) begin if (reset='1') then refresh_time_cnt <= 0; refresh <= '0'; elsif (CLK'event and CLK='1') then -- free running timer/counter if (refresh_time_cnt = refreshInterval) then refresh_time_cnt <= 0; else refresh_time_cnt <= refresh_time_cnt + 1; end if; -- refresh request signal if (refresh_time_cnt = refreshInterval) then refresh <= '1'; elsif (ref_ack = '1') then refresh <= '0'; end if; end if; end process; -- instantiate SDRAM_PHYIO SDRAM_PHYIOi : SDRAM_PHYIO port map ( CLK => CLK, CLK_130 => CLK_130, reset => reset, wrrd_ba_add => wrrd_ba_add, wrrd_ras_add => wrrd_ras_add, wrrd_cas_add => wrrd_cas_add, wr_we => wr_we, wr_add => wr_add, wr_dat => wr_dat, wr_ack => wr_ack, rd_re => rd_re, rd_add => rd_add, rd_dat => rd_dat, rd_ack => rd_ack, rd_valid => rd_valid, refresh => refresh, ref_ack => ref_ack, SDRAM_A => SDRAM_A, SDRAM_BA => SDRAM_BA, SDRAM_CKE => SDRAM_CKE, SDRAM_CK => SDRAM_CK, SDRAM_nCK => SDRAM_nCK, SDRAM_DQ => SDRAM_DQ, SDRAM_DQS => SDRAM_DQS, --SDRAM_nDQS => SDRAM_nDQS, SDRAM_DM => SDRAM_DM, SDRAM_nCAS => SDRAM_nCAS, SDRAM_nCS => SDRAM_nCS, SDRAM_nRAS => SDRAM_nRAS, SDRAM_nWE => SDRAM_nWE); end Struct;

library ieee; use ieee.std_logic_1164.all; package memory_types is type memory_16b is array (15 downto 0) of std_logic_vector(7 downto 0); end package memory_types;

-- ------------------------------------------------------------- -- -- Entity Declaration for inst_ac_e -- -- Generated -- by: wig -- on: Sat Mar 3 17:08:41 2007 -- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_ac_e-e.vhd,v 1.2 2007/03/03 17:24:06 wig Exp $ -- $Date: 2007/03/03 17:24:06 $ -- $Log: inst_ac_e-e.vhd,v $ -- Revision 1.2 2007/03/03 17:24:06 wig -- Updated testcase for case matches. Added filename serialization. -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.47 , [email protected] -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_ac_e -- entity inst_ac_e is -- Generics: -- No Generated Generics for Entity inst_ac_e -- Generated Port Declaration: -- No Generated Port for Entity inst_ac_e end inst_ac_e; -- -- End of Generated Entity inst_ac_e -- -- --!End of Entity/ies -- --------------------------------------------------------------

------------------------------------------------------------------------------ -- LEON3 Demonstration design -- Copyright (C) 2006 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015 - 2016, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; library techmap; use techmap.gencomp.all; use techmap.allclkgen.all; library gaisler; use gaisler.memctrl.all; use gaisler.ddrpkg.all; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; use gaisler.net.all; use gaisler.jtag.all; library esa; use esa.memoryctrl.all; use work.config.all; entity leon3mp is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; ddrfreq : integer := 100000 -- frequency of ddr clock in kHz ); port ( resetn : in std_ulogic; resoutn : out std_logic; clk_100mhz : in std_ulogic; errorn : out std_ulogic; -- prom interface address : out std_logic_vector(21 downto 0); data : inout std_logic_vector(15 downto 0); romsn : out std_ulogic; oen : out std_ulogic; writen : out std_ulogic; romrstn : out std_ulogic; -- pragma translate_off iosn : out std_ulogic; testdata : inout std_logic_vector(15 downto 0); -- pragma translate_on -- ddr memory ddr_clk0 : out std_logic; ddr_clk0b : out std_logic; ddr_clk_fb_out : out std_logic; ddr_clk_fb : in std_logic; ddr_cke0 : out std_logic; ddr_cs0b : out std_logic; ddr_web : out std_ulogic; -- ddr write enable ddr_rasb : out std_ulogic; -- ddr ras ddr_casb : out std_ulogic; -- ddr cas ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs ddr_ad : out std_logic_vector (12 downto 0); -- ddr address ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data -- debug support unit dsuen : in std_ulogic; dsubre : in std_ulogic; dsuact : out std_ulogic; -- UART for serial DCL/console I/O serrx : in std_ulogic; sertx : out std_ulogic; rtsn : out std_ulogic; ctsn : in std_ulogic; led_rx : out std_ulogic; led_tx : out std_ulogic; -- ethernet signals emdio : inout std_logic; -- ethernet PHY interface etx_clk : in std_ulogic; erx_clk : in std_ulogic; erxd : in std_logic_vector(3 downto 0); erx_dv : in std_ulogic; erx_er : in std_ulogic; erx_col : in std_ulogic; erx_crs : in std_ulogic; etxd : out std_logic_vector(3 downto 0); etx_en : out std_ulogic; etx_er : out std_ulogic; emdc : out std_ulogic; erstn : out std_ulogic; -- OLED display signals disp_dcn : out std_ulogic; disp_csn : out std_ulogic; disp_rdn : out std_ulogic; disp_wrn : out std_ulogic; disp_d : inout std_logic_vector(7 downto 0) ); end; architecture rtl of leon3mp is constant blength : integer := 12; constant fifodepth : integer := 8; signal vcc, gnd : std_logic_vector(4 downto 0); signal memi : memory_in_type; signal memo : memory_out_type; signal wpo : wprot_out_type; signal sdi : sdctrl_in_type; signal sdo : sdctrl_out_type; signal gpioi : gpio_in_type; signal gpioo : gpio_out_type; signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); signal lclk : std_ulogic; signal ddrclk, ddrrst, ddrclkfb : std_ulogic; signal clkm, rstn, clkml, clk2x : std_ulogic; signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; signal u1i, dui : uart_in_type; signal u1o, duo : uart_out_type; signal irqi : irq_in_vector(0 to CFG_NCPU-1); signal irqo : irq_out_vector(0 to CFG_NCPU-1); signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); signal dsui : dsu_in_type; signal dsuo : dsu_out_type; signal ethi, ethi1, ethi2 : eth_in_type; signal etho, etho1, etho2 : eth_out_type; signal gpti : gptimer_in_type; signal tck, tms, tdi, tdo : std_ulogic; -- signal dsubre : std_logic; signal duart, ldsuen : std_logic; signal rsertx, rserrx, rdsuen : std_logic; signal rstraw : std_logic; signal rstneg : std_logic; signal rxd1 : std_logic; signal txd1 : std_logic; signal lock : std_logic; signal ddr_clk : std_logic_vector(2 downto 0); signal ddr_clkb : std_logic_vector(2 downto 0); signal ddr_cke : std_logic_vector(1 downto 0); signal ddr_csb : std_logic_vector(1 downto 0); signal ddr_adl : std_logic_vector(13 downto 0); -- ddr address attribute keep : boolean; attribute syn_keep : boolean; attribute syn_preserve : boolean; attribute syn_keep of lock : signal is true; attribute syn_keep of clkml : signal is true; attribute syn_preserve of clkml : signal is true; attribute keep of lock : signal is true; attribute keep of clkml : signal is true; attribute keep of clkm : signal is true; constant BOARD_FREQ : integer := 100000; -- input frequency in KHz constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz begin romrstn <= rstn; ---------------------------------------------------------------------- --- Reset and Clock generation ------------------------------------- ---------------------------------------------------------------------- vcc <= (others => '1'); gnd <= (others => '0'); cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; rstneg <= not resetn; rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw); clk_pad : clkpad generic map (tech => padtech) port map (clk_100mhz, lclk); clkgen0 : clkgen -- clock generator generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, 0, 1, 0, 0, 0, BOARD_FREQ, 0) port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo); ---------------------------------------------------------------------- --- AHB CONTROLLER -------------------------------------------------- ---------------------------------------------------------------------- ahb0 : ahbctrl -- AHB arbiter/multiplexer generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1, nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1, nahbs => 8) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- --- LEON3 processor and DSU ----------------------------------------- ---------------------------------------------------------------------- leon3gen : if CFG_LEON3 = 1 generate cpu : for i in 0 to CFG_NCPU-1 generate u0 : leon3s -- LEON3 processor generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); end generate; error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error); dsugen : if CFG_DSU = 1 generate dsu0 : dsu3 -- LEON3 Debug Support Unit generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); dsui.enable <= '1'; dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); end generate; end generate; nodsu : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; end generate; dcomgen : if CFG_AHB_UART = 1 generate dcom0 : ahbuart -- Debug UART generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7) port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU)); end generate; nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate; ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART) port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART), open, open, open, open, open, open, open, gnd(0)); end generate; ---------------------------------------------------------------------- --- Memory controllers ---------------------------------------------- ---------------------------------------------------------------------- mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0, srbanks => 1, ramaddr => 16#600#, rammask => 16#F00#, ram16 => 1 ) port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open); end generate; memi.brdyn <= '1'; memi.bexcn <= '1'; memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01"; mg0 : if (CFG_MCTRL_LEON2 = 0) generate apbo(0) <= apb_none; ahbso(0) <= ahbs_none; roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0)); end generate; mgpads : if (CFG_MCTRL_LEON2 /= 0) generate addr_pad : outpadv generic map (width => 22, tech => padtech) port map (address, memo.address(22 downto 1)); roms_pad : outpad generic map (tech => padtech) port map (romsn, memo.romsn(0)); oen_pad : outpad generic map (tech => padtech) port map (oen, memo.oen); wri_pad : outpad generic map (tech => padtech) port map (writen, memo.writen); -- pragma translate_off iosn_pad : outpad generic map (tech => padtech) port map (iosn, memo.iosn); tbdr : for i in 0 to 1 generate data_pad : iopadv generic map (tech => padtech, width => 8) port map (testdata(15-i*8 downto 8-i*8), memo.data(15-i*8 downto 8-i*8), memo.bdrive(i+2), memi.data(15-i*8 downto 8-i*8)); end generate; -- pragma translate_on bdr : for i in 0 to 1 generate data_pad : iopadv generic map (tech => padtech, width => 8) port map (data(15-i*8 downto 8-i*8), memo.data(31-i*8 downto 24-i*8), memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); end generate; end generate; ---------------------------------------------------------------------- --- DDR memory controller ------------------------------------------- ---------------------------------------------------------------------- ddrsp0 : if (CFG_DDRSP /= 0) generate ddrc : ddrspa generic map ( fabtech => virtex4, memtech => memtech, hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1, pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => -95 -- pragma translate_off * 0 -- disable clock skew during simulation -- pragma translate_on , clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000, ddrbits => 16) port map ( rstneg, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(4), ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq); ddr_clk0 <= ddr_clk(0); ddr_clk0b <= ddr_clkb(0); ddr_cke0 <= ddr_cke(0); ddr_cs0b <= ddr_csb(0); ddr_ad <= ddr_adl(12 downto 0); end generate; noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate; ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- ---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge generic map (hindex => 1, haddr => CFG_APBADDR) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); ua1 : if CFG_UART1_ENABLE /= 0 generate uart1 : apbuart -- UART 1 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO) port map (rstn, clkm, apbi, apbo(1), u1i, u1o); u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd; end generate; noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; irqctrl : if CFG_IRQ3_ENABLE /= 0 generate irqctrl0 : irqmp -- interrupt controller generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) port map (rstn, clkm, apbi, apbo(2), irqo, irqi); end generate; irq3 : if CFG_IRQ3_ENABLE = 0 generate x : for i in 0 to CFG_NCPU-1 generate irqi(i).irl <= "0000"; end generate; apbo(2) <= apb_none; end generate; gpt : if CFG_GPT_ENABLE /= 0 generate timer0 : gptimer -- timer unit generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW) port map (rstn, clkm, apbi, apbo(3), gpti, open); gpti <= gpti_dhalt_drive(dsuo.tstop); end generate; notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit grgpio0: grgpio generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12 --CFG_GRGPIO_WIDTH ) port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); disp_csn_pad : outpad generic map (tech => padtech) port map (disp_csn, gpioo.dout(8)); disp_dcn_pad : outpad generic map (tech => padtech) port map (disp_dcn, gpioo.dout(9)); disp_rdn_pad : outpad generic map (tech => padtech) port map (disp_rdn, gpioo.dout(10)); disp_wrn_pad : outpad generic map (tech => padtech) port map (disp_wrn, gpioo.dout(11)); disp_d_pads : for i in 0 to 7 generate pio_pad : iopad generic map (tech => padtech) port map (disp_d(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); end generate; end generate; ----------------------------------------------------------------------- --- ETHERNET --------------------------------------------------------- ----------------------------------------------------------------------- eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC e1 : grethm generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, pindex => 15, paddr => 15, pirq => 12, memtech => memtech, mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO, nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, phyrstadr => 3, giga => CFG_GRETH1G) port map( rst => rstn, clk => clkm, ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho); emdio_pad : iopad generic map (tech => padtech) port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i); etxc_pad : inpad generic map (tech => padtech) port map (etx_clk, ethi.tx_clk); erxc_pad : inpad generic map (tech => padtech) port map (erx_clk, ethi.rx_clk); erxd_pad : inpadv generic map (tech => padtech, width => 4) port map (erxd, ethi.rxd(3 downto 0)); erxdv_pad : inpad generic map (tech => padtech) port map (erx_dv, ethi.rx_dv); erxer_pad : inpad generic map (tech => padtech) port map (erx_er, ethi.rx_er); erxco_pad : inpad generic map (tech => padtech) port map (erx_col, ethi.rx_col); erxcr_pad : inpad generic map (tech => padtech) port map (erx_crs, ethi.rx_crs); etxd_pad : outpadv generic map (tech => padtech, width => 4) port map (etxd, etho.txd(3 downto 0)); etxen_pad : outpad generic map (tech => padtech) port map (etx_en, etho.tx_en); etxer_pad : outpad generic map (tech => padtech) port map (etx_er, etho.tx_er); emdc_pad : outpad generic map (tech => padtech) port map (emdc, etho.mdc); erstn_pad : outpad generic map (tech => padtech) port map (erstn, rstn); end generate; ----------------------------------------------------------------------- --- AHB DMA ---------------------------------------------------------- ----------------------------------------------------------------------- -- dma0 : ahbdma -- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH, -- pindex => 12, paddr => 12, dbuf => 32) -- port map (rstn, clkm, apbi, apbo(12), ahbmi, -- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH)); -- -- at0 : ahbtrace -- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#, -- tech => memtech, irq => 0, kbytes => 8) -- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7)); ----------------------------------------------------------------------- --- AHB ROM ---------------------------------------------------------- ----------------------------------------------------------------------- bpromgen : if CFG_AHBROMEN /= 0 generate brom : entity work.ahbrom generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP) port map ( rstn, clkm, ahbsi, ahbso(6)); end generate; nobpromgen : if CFG_AHBROMEN = 0 generate ahbso(6) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- AHB RAM ---------------------------------------------------------- ----------------------------------------------------------------------- ahbramgen : if CFG_AHBRAMEN = 1 generate ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ) port map (rstn, clkm, ahbsi, ahbso(3)); end generate; nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- Drive unused bus elements --------------------------------------- ----------------------------------------------------------------------- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate ahbmo(i) <= ahbm_none; end generate; -- nap0 : for i in 9 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate; -- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate; resoutn <= rstn; ----------------------------------------------------------------------- --- Boot message ---------------------------------------------------- ----------------------------------------------------------------------- -- pragma translate_off x : report_design generic map ( msg1 => "LEON3 MP Demonstration design for Avnet Virtex4 Eval board", fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1 ); -- pragma translate_on -- use switch 1 to multiplex DSU UART and UART1 dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, ldsuen); duart <= rdsuen when CFG_AHB_UART /= 0 else '0'; rxd1 <= txd1 when duart = '1' else rserrx; rsertx <= duo.txd when duart = '1' else txd1; dui.rxd <= rserrx when duart = '1' else '1'; led_rx <= not rserrx; p1 : process(clkm) begin if rising_edge(clkm) then sertx <= rsertx; rserrx <= serrx; rdsuen <= ldsuen; rtsn <= '0'; led_tx <= not rsertx; end if; end process; end rtl;

-- VHDL Entity R6502_TC.Core.symbol -- -- Created: -- by - eda.UNKNOWN (ENTW1) -- at - 14:13:52 08.03.2010 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY Core IS PORT( clk_clk_i : IN std_logic; d_i : IN std_logic_vector (7 DOWNTO 0); irq_n_i : IN std_logic; nmi_n_i : IN std_logic; rdy_i : IN std_logic; rst_rst_n_i : IN std_logic; so_n_i : IN std_logic; a_o : OUT std_logic_vector (15 DOWNTO 0); d_o : OUT std_logic_vector (7 DOWNTO 0); rd_o : OUT std_logic; sync_o : OUT std_logic; wr_n_o : OUT std_logic; wr_o : OUT std_logic ); -- Declarations END Core ; -- Jens-D. Gutschmidt Project: R6502_TC -- [email protected] -- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG -- -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version -- 3 of the License, or any later version. -- -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A -- PARTICULAR PURPOSE. See the GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- CVS Revisins History -- -- $Log: struct.bd,v $ -- <<-- more -->> -- Title: Core -- Path: R6502_TC/Core/struct -- Edited: by eda on 08 Feb 2010 -- -- VHDL Architecture R6502_TC.Core.struct -- -- Created: -- by - eda.UNKNOWN (ENTW1) -- at - 14:13:53 08.03.2010 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; LIBRARY R6502_TC; ARCHITECTURE struct OF Core IS -- Architecture declarations -- Internal signal declarations SIGNAL adr_nxt_pc_o_i : std_logic_vector(15 DOWNTO 0); SIGNAL adr_o_i : std_logic_vector(15 DOWNTO 0); SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0); SIGNAL adr_sp_o_i : std_logic_vector(15 DOWNTO 0); SIGNAL ch_a_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL ch_b_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL d_alu_n_o_i : std_logic; SIGNAL d_alu_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL d_alu_or_o_i : std_logic; SIGNAL d_regs_in_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL d_regs_out_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL ld_o_i : std_logic_vector(1 DOWNTO 0); SIGNAL ld_pc_o_i : std_logic; SIGNAL ld_sp_o_i : std_logic; SIGNAL load_regs_o_i : std_logic; SIGNAL nmi_o_i : std_logic; SIGNAL offset_o_i : std_logic_vector(15 DOWNTO 0); SIGNAL q_a_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL q_x_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL q_y_o_i : std_logic_vector(7 DOWNTO 0); SIGNAL reg_0flag_o_i : std_logic; SIGNAL reg_1flag_o_i : std_logic; SIGNAL reg_7flag_o_i : std_logic; SIGNAL rst_nmi_o_i : std_logic; SIGNAL sel_pc_in_o_i : std_logic; SIGNAL sel_pc_val_o_i : std_logic_vector(1 DOWNTO 0); SIGNAL sel_rb_in_o_i : std_logic_vector(1 DOWNTO 0); SIGNAL sel_rb_out_o_i : std_logic_vector(1 DOWNTO 0); SIGNAL sel_reg_o_i : std_logic_vector(1 DOWNTO 0); SIGNAL sel_sp_as_o_i : std_logic; SIGNAL sel_sp_in_o_i : std_logic; -- Component Declarations COMPONENT FSM_Execution_Unit PORT ( adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0); adr_pc_i : IN std_logic_vector (15 DOWNTO 0); adr_sp_i : IN std_logic_vector (15 DOWNTO 0); clk_clk_i : IN std_logic ; d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 ); d_i : IN std_logic_vector ( 7 DOWNTO 0 ); d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 ); irq_n_i : IN std_logic ; nmi_i : IN std_logic ; q_a_i : IN std_logic_vector ( 7 DOWNTO 0 ); q_x_i : IN std_logic_vector ( 7 DOWNTO 0 ); q_y_i : IN std_logic_vector ( 7 DOWNTO 0 ); rdy_i : IN std_logic ; reg_0flag_i : IN std_logic ; reg_1flag_i : IN std_logic ; reg_7flag_i : IN std_logic ; rst_rst_n_i : IN std_logic ; so_n_i : IN std_logic ; a_o : OUT std_logic_vector (15 DOWNTO 0); adr_o : OUT std_logic_vector (15 DOWNTO 0); ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 ); ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 ); d_o : OUT std_logic_vector ( 7 DOWNTO 0 ); d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 ); ld_o : OUT std_logic_vector ( 1 DOWNTO 0 ); ld_pc_o : OUT std_logic ; ld_sp_o : OUT std_logic ; load_regs_o : OUT std_logic ; offset_o : OUT std_logic_vector ( 15 DOWNTO 0 ); rd_o : OUT std_logic ; rst_nmi_o : OUT std_logic ; sel_pc_in_o : OUT std_logic ; sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 ); sel_sp_as_o : OUT std_logic ; sel_sp_in_o : OUT std_logic ; sync_o : OUT std_logic ; wr_n_o : OUT std_logic ; wr_o : OUT std_logic ); END COMPONENT; COMPONENT FSM_NMI PORT ( clk_clk_i : IN std_logic ; nmi_n_i : IN std_logic ; rst_nmi_i : IN std_logic ; rst_rst_n_i : IN std_logic ; nmi_o : OUT std_logic ); END COMPONENT; COMPONENT RegBank_AXY PORT ( clk_clk_i : IN std_logic ; d_regs_in_i : IN std_logic_vector (7 DOWNTO 0); load_regs_i : IN std_logic ; rst_rst_n_i : IN std_logic ; sel_rb_in_i : IN std_logic_vector (1 DOWNTO 0); sel_rb_out_i : IN std_logic_vector (1 DOWNTO 0); sel_reg_i : IN std_logic_vector (1 DOWNTO 0); d_regs_out_o : OUT std_logic_vector (7 DOWNTO 0); q_a_o : OUT std_logic_vector (7 DOWNTO 0); q_x_o : OUT std_logic_vector (7 DOWNTO 0); q_y_o : OUT std_logic_vector (7 DOWNTO 0) ); END COMPONENT; COMPONENT Reg_PC PORT ( adr_i : IN std_logic_vector (15 DOWNTO 0); clk_clk_i : IN std_logic ; ld_i : IN std_logic_vector (1 DOWNTO 0); ld_pc_i : IN std_logic ; offset_i : IN std_logic_vector (15 DOWNTO 0); rst_rst_n_i : IN std_logic ; sel_pc_in_i : IN std_logic ; sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0); adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0); adr_pc_o : OUT std_logic_vector (15 DOWNTO 0) ); END COMPONENT; COMPONENT Reg_SP PORT ( adr_low_i : IN std_logic_vector (7 DOWNTO 0); clk_clk_i : IN std_logic ; ld_low_i : IN std_logic ; ld_sp_i : IN std_logic ; rst_rst_n_i : IN std_logic ; sel_sp_as_i : IN std_logic ; sel_sp_in_i : IN std_logic ; adr_sp_o : OUT std_logic_vector (15 DOWNTO 0) ); END COMPONENT; -- Optional embedded configurations -- pragma synthesis_off FOR ALL : FSM_Execution_Unit USE ENTITY R6502_TC.FSM_Execution_Unit; FOR ALL : FSM_NMI USE ENTITY R6502_TC.FSM_NMI; FOR ALL : RegBank_AXY USE ENTITY R6502_TC.RegBank_AXY; FOR ALL : Reg_PC USE ENTITY R6502_TC.Reg_PC; FOR ALL : Reg_SP USE ENTITY R6502_TC.Reg_SP; -- pragma synthesis_on BEGIN -- ModuleWare code(v1.9) for instance 'U_11' of 'add' u_11combo_proc: PROCESS (ch_a_o_i, ch_b_o_i) VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0); VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0); VARIABLE temp_sum : unsigned(8 DOWNTO 0); VARIABLE temp_carry : std_logic; BEGIN temp_din0 := '0' & ch_a_o_i; temp_din1 := '0' & ch_b_o_i; temp_carry := '0'; temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry; d_alu_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8); reg_0flag_o_i <= temp_sum(8) ; END PROCESS u_11combo_proc; -- ModuleWare code(v1.9) for instance 'U_8' of 'inv' reg_1flag_o_i <= NOT(d_alu_or_o_i); -- ModuleWare code(v1.9) for instance 'U_9' of 'inv' reg_7flag_o_i <= NOT(d_alu_n_o_i); -- ModuleWare code(v1.9) for instance 'U_10' of 'inv' d_alu_n_o_i <= NOT(d_alu_o_i(7)); -- ModuleWare code(v1.9) for instance 'U_7' of 'por' d_alu_or_o_i <= d_alu_o_i(0) OR d_alu_o_i(1) OR d_alu_o_i(2) OR d_alu_o_i(3) OR d_alu_o_i(4) OR d_alu_o_i(5) OR d_alu_o_i(6) OR d_alu_o_i(7); -- Instance port mappings. U_4 : FSM_Execution_Unit PORT MAP ( adr_nxt_pc_i => adr_nxt_pc_o_i, adr_pc_i => adr_pc_o_i, adr_sp_i => adr_sp_o_i, clk_clk_i => clk_clk_i, d_alu_i => d_alu_o_i, d_i => d_i, d_regs_out_i => d_regs_out_o_i, irq_n_i => irq_n_i, nmi_i => nmi_o_i, q_a_i => q_a_o_i, q_x_i => q_x_o_i, q_y_i => q_y_o_i, rdy_i => rdy_i, reg_0flag_i => reg_0flag_o_i, reg_1flag_i => reg_1flag_o_i, reg_7flag_i => reg_7flag_o_i, rst_rst_n_i => rst_rst_n_i, so_n_i => so_n_i, a_o => a_o, adr_o => adr_o_i, ch_a_o => ch_a_o_i, ch_b_o => ch_b_o_i, d_o => d_o, d_regs_in_o => d_regs_in_o_i, ld_o => ld_o_i, ld_pc_o => ld_pc_o_i, ld_sp_o => ld_sp_o_i, load_regs_o => load_regs_o_i, offset_o => offset_o_i, rd_o => rd_o, rst_nmi_o => rst_nmi_o_i, sel_pc_in_o => sel_pc_in_o_i, sel_pc_val_o => sel_pc_val_o_i, sel_rb_in_o => sel_rb_in_o_i, sel_rb_out_o => sel_rb_out_o_i, sel_reg_o => sel_reg_o_i, sel_sp_as_o => sel_sp_as_o_i, sel_sp_in_o => sel_sp_in_o_i, sync_o => sync_o, wr_n_o => wr_n_o, wr_o => wr_o ); U_6 : FSM_NMI PORT MAP ( clk_clk_i => clk_clk_i, nmi_n_i => nmi_n_i, rst_nmi_i => rst_nmi_o_i, rst_rst_n_i => rst_rst_n_i, nmi_o => nmi_o_i ); U_2 : RegBank_AXY PORT MAP ( clk_clk_i => clk_clk_i, d_regs_in_i => d_regs_in_o_i, load_regs_i => load_regs_o_i, rst_rst_n_i => rst_rst_n_i, sel_rb_in_i => sel_rb_in_o_i, sel_rb_out_i => sel_rb_out_o_i, sel_reg_i => sel_reg_o_i, d_regs_out_o => d_regs_out_o_i, q_a_o => q_a_o_i, q_x_o => q_x_o_i, q_y_o => q_y_o_i ); U_0 : Reg_PC PORT MAP ( adr_i => adr_o_i, clk_clk_i => clk_clk_i, ld_i => ld_o_i, ld_pc_i => ld_pc_o_i, offset_i => offset_o_i, rst_rst_n_i => rst_rst_n_i, sel_pc_in_i => sel_pc_in_o_i, sel_pc_val_i => sel_pc_val_o_i, adr_nxt_pc_o => adr_nxt_pc_o_i, adr_pc_o => adr_pc_o_i ); U_1 : Reg_SP PORT MAP ( adr_low_i => adr_o_i(7 DOWNTO 0), clk_clk_i => clk_clk_i, ld_low_i => ld_o_i(0), ld_sp_i => ld_sp_o_i, rst_rst_n_i => rst_rst_n_i, sel_sp_as_i => sel_sp_as_o_i, sel_sp_in_i => sel_sp_in_o_i, adr_sp_o => adr_sp_o_i ); END struct;

component soc_design is port ( clock_clk : in std_logic := 'X'; -- clk fpga_reset_n : in std_logic := 'X' -- reset_n ); end component soc_design; u0 : component soc_design port map ( clock_clk => CONNECTED_TO_clock_clk, -- clock.clk fpga_reset_n => CONNECTED_TO_fpga_reset_n -- fpga.reset_n );

---------------------------------------------------------------------------------------------------- -- ENTITY - GF(2^M) Binary polynomial divider -- Computes the g/h mod f IN GF(2**m) -- -- Ports: -- clk_i - Clock -- rst_i - Reset flag -- enable_i - Enable computation -- g_i - First input value -- h_i - Seccond input value -- z_o - Output value -- ready_o - Ready flag after computation -- -- Example: -- 1100101 / 1101 = 1001 -- -- BIT-SHIFT and XOR: -- 1100101 / 1101 = 1001 -- 1101 -- 0011 -- 0000 -- 0110 -- 0000 -- 1101 -- 1101 -- 0 Remainder -- -- Based on: -- http://arithmetic-circuits.org/finite-field/vhdl_Models/chapter10_codes/VHDL/K-163/binary_algorithm_polynomials.vhd -- -- Autor: Lennart Bublies (inf100434) -- Date: 22.06.2017 ---------------------------------------------------------------------------------------------------- ------------------------------------------------------------ -- GF(2^M) binary polynomial divider ------------------------------------------------------------ LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_unsigned.all; USE work.tld_ecdsa_package.all; ENTITY e_gf2m_divider IS GENERIC ( MODULO : std_logic_vector(M DOWNTO 0) := ONE ); PORT( -- Clock, reset and enable clk_i: IN std_logic; rst_i: IN std_logic; enable_i: IN std_logic; -- Input signals g_i: IN std_logic_vector(M-1 DOWNTO 0); h_i: IN std_logic_vector(M-1 DOWNTO 0); -- Output signals z_o: OUT std_logic_vector(M-1 DOWNTO 0); ready_o: OUT std_logic ); END e_gf2m_divider; ARCHITECTURE rtl of e_gf2m_divider IS -- Internal signals SIGNAL a : std_logic_vector(M DOWNTO 0); SIGNAL b, c, d, next_b, next_d: std_logic_vector(M-1 DOWNTO 0); SIGNAL alpha, beta, next_beta, dec_input: std_logic_vector(logM-1 DOWNTO 0); SIGNAL ce_ac, ce_bd, load, beta_non_negative, alpha_gt_beta, b_zero: std_logic; -- Define all available states type states IS RANGE 0 TO 4; SIGNAL current_state: states; BEGIN -- Load arguments for next computation registers_ac: PROCESS(clk_i) BEGIN IF clk_i'event and clk_i = '1' THEN -- First computation (global arguments) IF load = '1' THEN a <= MODULO; c <= (OTHERS => '0'); -- Seccond computation ELSIF ce_ac = '1' THEN a <= '0'&b; c <= d; END IF; END IF; END PROCESS registers_ac; registers_bd: PROCESS(clk_i) BEGIN IF clk_i'event and clk_i = '1' THEN -- First computation (input arguments) IF load = '1' THEN b <= h_i; d <= g_i; -- Seccond computation ELSIF ce_bd = '1' THEN b <= next_b; d <= next_d; END IF; END IF; END PROCESS registers_bd; register_alpha: PROCESS(clk_i) BEGIN IF clk_i'event and clk_i = '1' THEN -- First computation (input arguments) IF load = '1' THEN alpha <= conv_std_logic_vector(M, logM); -- Seccond computation ELSIF ce_ac = '1' THEN alpha <= beta; END IF; END IF; END PROCESS register_alpha; register_beta: PROCESS(clk_i) BEGIN IF clk_i'event and clk_i = '1' THEN -- First computation (input arguments) IF load = '1' THEN beta <= conv_std_logic_vector(M-1, logM); -- Seccond computation ELSIF ce_bd = '1' THEN beta <= next_beta; END IF; END IF; END PROCESS register_beta; -- Shift and Add -- IF b(0)=0 THEN -- next_b(i) = b(i+1) -- ELSIF b(0)=1 THEN -- next_b(i) = b(i+1) + a(i+1) -- ENDIF first_iteration: FOR i IN 0 TO M-2 GENERATE next_b(i) <= (b(0) and (b(i+1) xor a(i+1))) or (not(b(0)) and b(i+1)); END GENERATE; next_b(M-1) <= b(0) and a(M); -- Shift and Add -- IF b(0)=0 THEN -- next_d(i) = (MODULO(i+1)&next_d(M-1)) + d(i+1) ????? (MODULO(i+1)&next_d(M-1)) ????? -- ELSIF b(0)=1 THEN -- next_d(i) = (MODULO(i+1)&next_d(M-1)) + d(i+1) + c(i+1) ????? (MODULO(i+1)&next_d(M-1)) ????? -- ENDIF second_iteration: FOR i IN 0 TO M-2 GENERATE next_d(i) <= (MODULO(i+1) and next_d(M-1)) xor ((b(0) and (d(i+1) xor c(i+1))) or (not(b(0)) and d(i+1))); END GENERATE; next_d(M-1) <= (b(0) and (d(0) xor c(0))) or (not(b(0)) and d(0)); WITH ce_ac SELECT dec_input <= beta WHEN '0', alpha WHEN OTHERS; next_beta <= dec_input - 1; beta_non_negative <= '1' WHEN beta(logM-1) = '0' ELSE '0'; alpha_gt_beta <= '1' WHEN alpha > beta ELSE '0'; b_zero <= '1' WHEN b(0) = '0' ELSE '0'; -- Set output z_o <= c; -- State machine control_unit: PROCESS(clk_i, rst_i, current_state, beta_non_negative, alpha_gt_beta, b_zero) BEGIN -- Handle current state -- 0,1 : Default state -- 2 : Load input arguments -- 3,4 : Calculation... CASE current_state IS WHEN 0 TO 1 => ce_ac <= '0'; ce_bd <='0'; load <= '0'; ready_o <= '1'; WHEN 2 => ce_ac <= '0'; ce_bd <= '0'; load <= '1'; ready_o <= '0'; WHEN 3 => IF beta_non_negative = '0' THEN ce_ac <= '0'; ce_bd <= '0'; ELSIF b_zero = '1' THEN ce_ac <= '0'; ce_bd <= '1'; ELSIF alpha_gt_beta = '1' THEN ce_ac <= '1'; ce_bd <= '1'; ELSE ce_ac <= '0'; ce_bd <= '1'; END IF; load <= '0'; ready_o <='0'; WHEN 4 => ce_ac <= '0'; ce_bd <='0'; load <= '0'; ready_o <= '0'; END CASE; IF rst_i = '1' THEN -- Reset state if reset is high current_state <= 0; ELSIF clk_i'event and clk_i = '1' THEN -- Set next state CASE current_state IS WHEN 0 => IF enable_i = '0' THEN current_state <= 1; END IF; WHEN 1 => IF enable_i = '1' THEN current_state <= 2; END IF; WHEN 2 => current_state <= 3; WHEN 3 => IF beta_non_negative = '0' THEN current_state <= 4; END IF; WHEN 4 => current_state <= 0; END CASE; END IF; END PROCESS control_unit; END rtl;

------------------------------------------------------------------------------- --! @file asyncFifo-syn-a.vhd -- --! @brief The asynchronous Fifo architecture for Altera -- --! @details This is a dual clock fifo generated in Megawizard! -- ------------------------------------------------------------------------------- -- -- (c) B&R Industrial Automation GmbH, 2014 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --! use altera_mf library library altera_mf; use altera_mf.altera_mf_components.all; architecture syn of asyncFifo is begin theAlteraDcFifo : dcfifo generic map ( intended_device_family => "Cyclone IV E", lpm_width => gDataWidth, lpm_widthu => logDualis(gWordSize), lpm_numwords => gWordSize, lpm_showahead => "OFF", lpm_type => "DCFIFO", overflow_checking => "ON", underflow_checking => "ON", delay_rdusedw => 1, delay_wrusedw => 1, add_usedw_msb_bit => "OFF", rdsync_delaypipe => gSyncStages+2, wrsync_delaypipe => gSyncStages+2, use_eab => gMemRes, write_aclr_synch => "ON", read_aclr_synch => "ON", clocks_are_synchronized => "FALSE", add_ram_output_register => "ON" ) port map ( aclr => iAclr, data => iWrData, q => oRdData, rdclk => iRdClk, rdempty => oRdEmpty, rdfull => oRdFull, rdreq => iRdReq, rdusedw => oRdUsedw, wrclk => iWrClk, wrempty => oWrEmpty, wrfull => oWrFull, wrreq => iWrReq, wrusedw => oWrUsedw ); end architecture syn;

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 21:28:33 10/18/2017 -- Design Name: -- Module Name: C:/Users/Kalugy/Documents/xilinx/secondooooooooo/Tbfirstpartnew.vhd -- Project Name: secondooooooooo -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: firstrpart -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY Tbfirstpartnew IS END Tbfirstpartnew; ARCHITECTURE behavior OF Tbfirstpartnew IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT firstrpart PORT( Resetext : IN std_logic; Clkinext : IN std_logic; Adressext : OUT std_logic_vector(31 downto 0) ); END COMPONENT; --Inputs signal Resetext : std_logic := '0'; signal Clkinext : std_logic := '0'; --Outputs signal Adressext : std_logic_vector(31 downto 0); -- Clock period definitions constant Clkinext_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: firstrpart PORT MAP ( Resetext => Resetext, Clkinext => Clkinext, Adressext => Adressext ); -- Clock process definitions Clkinext_process :process begin Clkinext <= '0'; wait for Clkinext_period/2; Clkinext <= '1'; wait for Clkinext_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. Resetext <= '0'; wait for 100 ns; Resetext <= '1'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; Resetext <= '0'; wait for 100 ns; -- insert stimulus here -- insert stimulus here wait; end process; END;

-- ------------------------------------------------------------- -- -- Entity Declaration for inst_bug_e -- -- Generated -- by: wig -- on: Thu Oct 6 12:55:50 2005 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_bug_e-e.vhd,v 1.1 2005/10/06 13:36:57 wig Exp $ -- $Date: 2005/10/06 13:36:57 $ -- $Log: inst_bug_e-e.vhd,v $ -- Revision 1.1 2005/10/06 13:36:57 wig -- New testcase or generics -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.37 , [email protected] -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_bug_e -- entity inst_bug_e is -- Generics: generic( -- Generated Generics for Entity inst_bug_e CHROMA_GROUP_DELAY2_G : integer := 1; CHROMA_GROUP_DELAY_G : integer := 12; CHROMA_LINE_DELAY2_G : integer := 3; CHROMA_LINE_DELAY_G : integer := 0; CHROMA_PIPE_DELAY2_G : integer := 2; CHROMA_PIPE_DELAY_G : integer := 1 -- End of Generated Generics for Entity inst_bug_e ); -- Generated Port Declaration: -- No Generated Port for Entity inst_bug_e end inst_bug_e; -- -- End of Generated Entity inst_bug_e -- -- --!End of Entity/ies -- --------------------------------------------------------------

entity tb_ret03 is end tb_ret03; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_ret03 is signal d : std_logic_vector (7 downto 0); signal r : integer; begin dut: entity work.ret03 port map (d, r); process begin d <= x"01"; wait for 1 ns; assert r = 0 severity failure; d <= x"1f"; wait for 1 ns; assert r = 4 severity failure; d <= x"e2"; wait for 1 ns; assert r = 7 severity failure; d <= x"00"; wait for 1 ns; assert r = -1 severity failure; wait; end process; end behav;

-- Company: ZPU4 generic memory interface CPU -- Engineer: Øyvind Harboe library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_arith.ALL; library work; use work.zpu_config.all; use work.zpupkg.all; entity zpu_core is Port ( clk : in std_logic; areset : in std_logic; enable : in std_logic; mem_req : out std_logic; mem_we : out std_logic; mem_ack : in std_logic; mem_read : in std_logic_vector(wordSize-1 downto 0); mem_write : out std_logic_vector(wordSize-1 downto 0); out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0); mem_writeMask: out std_logic_vector(wordBytes-1 downto 0); interrupt : in std_logic; break : out std_logic; zpu_status : out std_logic_vector(63 downto 0)); end zpu_core; architecture behave of zpu_core is type InsnType is ( State_AddTop, State_Dup, State_DupStackB, State_Pop, State_Popdown, State_Add, State_Or, State_And, State_Store, State_AddSP, State_Shift, State_Nop, State_Im, State_LoadSP, State_StoreSP, State_Emulate, State_Load, State_PushPC, State_PushSP, State_PopPC, State_PopPCRel, State_Not, State_Flip, State_PopSP, State_Neqbranch, State_Eq, State_Loadb, State_Mult, State_Lessthan, State_Lessthanorequal, State_Ulessthanorequal, State_Ulessthan, State_Pushspadd, State_Call, State_Callpcrel, State_Sub, State_Break, State_Storeb, State_Interrupt, State_InsnFetch ); type StateType is ( State_Idle, -- using first state first on the list out of paranoia State_Load2, State_Popped, State_LoadSP2, State_LoadSP3, State_AddSP2, State_Fetch, State_Execute, State_Decode, State_Decode2, State_Resync, State_StoreSP2, State_Resync2, State_Resync3, State_Loadb2, State_Storeb2, State_Mult2, State_Mult3, State_Mult5, State_Mult6, State_Mult4, State_BinaryOpResult ); signal pc : std_logic_vector(maxAddrBitIncIO downto 0); signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal stackA : std_logic_vector(wordSize-1 downto 0); signal binaryOpResult : std_logic_vector(wordSize-1 downto 0); signal multResult2 : std_logic_vector(wordSize-1 downto 0); signal multResult3 : std_logic_vector(wordSize-1 downto 0); signal multResult : std_logic_vector(wordSize-1 downto 0); signal multA : std_logic_vector(wordSize-1 downto 0); signal multB : std_logic_vector(wordSize-1 downto 0); signal stackB : std_logic_vector(wordSize-1 downto 0); signal idim_flag : std_logic; signal busy : std_logic; signal mem_readEnable : std_logic; signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal mem_delayReadEnable : std_logic; signal mem_busy : std_logic; signal decodeWord : std_logic_vector(wordSize-1 downto 0); signal state : StateType; signal insn : InsnType; type InsnArray is array(0 to wordBytes-1) of InsnType; signal decodedOpcode : InsnArray; type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0); signal opcode : OpcodeArray; signal begin_inst : std_logic; signal trace_opcode : std_logic_vector(7 downto 0); signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0); signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit); signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0); signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0); signal out_mem_req : std_logic; signal inInterrupt : std_logic; -- state machine. begin zpu_status(maxAddrBitIncIO downto 0) <= trace_pc; zpu_status(31) <= '1'; zpu_status(39 downto 32) <= trace_opcode; zpu_status(40) <= '1' when (state = State_Idle) else '0'; zpu_status(62) <= '1'; traceFileGenerate: if Generate_Trace generate trace_file: trace port map ( clk => clk, begin_inst => begin_inst, pc => trace_pc, opcode => trace_opcode, sp => trace_sp, memA => trace_topOfStack, memB => trace_topOfStackB, busy => busy, intsp => (others => 'U') ); end generate; -- the memory subsystem will tell us one cycle later whether or -- not it is busy out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr; out_mem_addr(minAddrBit-1 downto 0) <= (others => '0'); mem_req <= out_mem_req; incSp <= sp + 1; incIncSp <= sp + 2; decSp <= sp - 1; mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy opcodeControl: process(clk, areset) variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0); variable spOffset : std_logic_vector(4 downto 0); variable tSpOffset : std_logic_vector(4 downto 0); variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0); variable tNextState : InsnType; variable tDecodedOpcode : InsnArray; variable tMultResult : std_logic_vector(wordSize*2-1 downto 0); begin if areset = '1' then state <= State_Idle; break <= '0'; sp <= spStart(maxAddrBitIncIO downto minAddrBit); pc <= (others => '0'); idim_flag <= '0'; begin_inst <= '0'; mem_we <= '0'; multA <= (others => '0'); multB <= (others => '0'); mem_writeMask <= (others => '1'); out_mem_req <= '0'; mem_addr <= (others => DontCareValue); mem_write <= (others => DontCareValue); inInterrupt <= '0'; elsif (clk'event and clk = '1') then -- we must multiply unconditionally to get pipelined multiplication tMultResult := multA * multB; multResult3 <= multResult2; multResult2 <= multResult; multResult <= tMultResult(wordSize-1 downto 0); spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4); spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0); nextPC := pc + 1; -- prepare trace snapshot trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0))); trace_pc <= pc; trace_sp <= sp; trace_topOfStack <= stackA; trace_topOfStackB <= stackB; begin_inst <= '0'; -- we terminate the requeset as soon as we get acknowledge if mem_ack = '1' then out_mem_req <= '0'; mem_we <= '0'; end if; if interrupt='0' then inInterrupt <= '0'; -- no longer in an interrupt end if; case state is when State_Idle => if enable='1' then state <= State_Resync; end if; -- Initial state of ZPU, fetch top of stack + first instruction when State_Resync => if mem_busy='0' then mem_addr <= sp; out_mem_req <= '1'; state <= State_Resync2; end if; when State_Resync2 => if mem_busy='0' then stackA <= mem_read; mem_addr <= incSp; out_mem_req <= '1'; state <= State_Resync3; end if; when State_Resync3 => if mem_busy='0' then stackB <= mem_read; mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); out_mem_req <= '1'; state <= State_Decode; end if; when State_Decode => if mem_busy='0' then decodeWord <= mem_read; state <= State_Decode2; end if; when State_Decode2 => -- decode 4 instructions in parallel for i in 0 to wordBytes-1 loop tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8); tSpOffset(4):=not tOpcode(4); tSpOffset(3 downto 0):=tOpcode(3 downto 0); opcode(i) <= tOpcode; if (tOpcode(7 downto 7)=OpCode_Im) then tNextState:=State_Im; elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then if tSpOffset = 0 then tNextState := State_Pop; elsif tSpOffset=1 then tNextState := State_PopDown; else tNextState :=State_StoreSP; end if; elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then if tSpOffset = 0 then tNextState :=State_Dup; elsif tSpOffset = 1 then tNextState :=State_DupStackB; else tNextState :=State_LoadSP; end if; elsif (tOpcode(7 downto 5)=OpCode_Emulate) then tNextState :=State_Emulate; if tOpcode(5 downto 0)=OpCode_Neqbranch then tNextState :=State_Neqbranch; elsif tOpcode(5 downto 0)=OpCode_Eq then tNextState :=State_Eq; elsif tOpcode(5 downto 0)=OpCode_Lessthan then tNextState :=State_Lessthan; elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then --tNextState :=State_Lessthanorequal; elsif tOpcode(5 downto 0)=OpCode_Ulessthan then tNextState :=State_Ulessthan; elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then --tNextState :=State_Ulessthanorequal; elsif tOpcode(5 downto 0)=OpCode_Loadb then tNextState :=State_Loadb; elsif tOpcode(5 downto 0)=OpCode_Mult then tNextState :=State_Mult; elsif tOpcode(5 downto 0)=OpCode_Storeb then tNextState :=State_Storeb; elsif tOpcode(5 downto 0)=OpCode_Pushspadd then tNextState :=State_Pushspadd; elsif tOpcode(5 downto 0)=OpCode_Callpcrel then tNextState :=State_Callpcrel; elsif tOpcode(5 downto 0)=OpCode_Call then --tNextState :=State_Call; elsif tOpcode(5 downto 0)=OpCode_Sub then tNextState :=State_Sub; elsif tOpcode(5 downto 0)=OpCode_PopPCRel then --tNextState :=State_PopPCRel; end if; elsif (tOpcode(7 downto 4)=OpCode_AddSP) then if tSpOffset = 0 then tNextState := State_Shift; elsif tSpOffset = 1 then tNextState := State_AddTop; else tNextState :=State_AddSP; end if; else case tOpcode(3 downto 0) is when OpCode_Nop => tNextState :=State_Nop; when OpCode_PushSP => tNextState :=State_PushSP; when OpCode_PopPC => tNextState :=State_PopPC; when OpCode_Add => tNextState :=State_Add; when OpCode_Or => tNextState :=State_Or; when OpCode_And => tNextState :=State_And; when OpCode_Load => tNextState :=State_Load; when OpCode_Not => tNextState :=State_Not; when OpCode_Flip => tNextState :=State_Flip; when OpCode_Store => tNextState :=State_Store; when OpCode_PopSP => tNextState :=State_PopSP; when others => tNextState := State_Break; end case; end if; tDecodedOpcode(i) := tNextState; end loop; insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0))); -- once we wrap, we need to fetch tDecodedOpcode(0) := State_InsnFetch; decodedOpcode <= tDecodedOpcode; state <= State_Execute; -- Each instruction must: -- -- 1. set idim_flag -- 2. increase pc if applicable -- 3. set next state if appliable -- 4. do it's operation when State_Execute => insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0))); case insn is when State_InsnFetch => state <= State_Fetch; when State_Im => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '1'; pc <= pc + 1; if idim_flag='1' then stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0); stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); else out_mem_req <= '1'; mem_we <= '1'; mem_addr <= incSp; mem_write <= stackB; stackB <= stackA; sp <= decSp; for i in wordSize-1 downto 7 loop stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6); end loop; stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0); end if; else insn <= insn; end if; when State_StoreSP => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; state <= State_StoreSP2; out_mem_req <= '1'; mem_we <= '1'; mem_addr <= sp+spOffset; mem_write <= stackA; stackA <= stackB; sp <= incSp; else insn <= insn; end if; when State_LoadSP => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; state <= State_LoadSP2; sp <= decSp; out_mem_req <= '1'; mem_we <= '1'; mem_addr <= incSp; mem_write <= stackB; else insn <= insn; end if; when State_Emulate => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; sp <= decSp; out_mem_req <= '1'; mem_we <= '1'; mem_addr <= incSp; mem_write <= stackB; stackA <= (others => DontCareValue); stackA(maxAddrBitIncIO downto 0) <= pc + 1; stackB <= stackA; -- The emulate address is: -- 98 7654 3210 -- 0000 00aa aaa0 0000 pc <= (others => '0'); pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0); state <= State_Fetch; else insn <= insn; end if; when State_Callpcrel => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; stackA <= (others => DontCareValue); stackA(maxAddrBitIncIO downto 0) <= pc + 1; pc <= pc + stackA(maxAddrBitIncIO downto 0); state <= State_Fetch; else insn <= insn; end if; when State_Call => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; stackA <= (others => DontCareValue); stackA(maxAddrBitIncIO downto 0) <= pc + 1; pc <= stackA(maxAddrBitIncIO downto 0); state <= State_Fetch; else insn <= insn; end if; when State_AddSP => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; state <= State_AddSP2; out_mem_req <= '1'; mem_addr <= sp+spOffset; else insn <= insn; end if; when State_PushSP => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; sp <= decSp; stackA <= (others => '0'); stackA(maxAddrBitIncIO downto minAddrBit) <= sp; stackB <= stackA; out_mem_req <= '1'; mem_we <= '1'; mem_addr <= incSp; mem_write <= stackB; else insn <= insn; end if; when State_PopPC => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; pc <= stackA(maxAddrBitIncIO downto 0); sp <= incSp; out_mem_req <= '1'; mem_we <= '1'; mem_addr <= incSp; mem_write <= stackB; state <= State_Resync; else insn <= insn; end if; when State_PopPCRel => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; pc <= stackA(maxAddrBitIncIO downto 0) + pc; sp <= incSp; out_mem_req <= '1'; mem_we <= '1'; mem_addr <= incSp; mem_write <= stackB; state <= State_Resync; else insn <= insn; end if; when State_Add => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; stackA <= stackA + stackB; out_mem_req <= '1'; mem_addr <= incIncSp; sp <= incSp; state <= State_Popped; else insn <= insn; end if; when State_Sub => begin_inst <= '1'; idim_flag <= '0'; binaryOpResult <= stackB - stackA; state <= State_BinaryOpResult; when State_Pop => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; mem_addr <= incIncSp; out_mem_req <= '1'; sp <= incSp; stackA <= stackB; state <= State_Popped; else insn <= insn; end if; when State_PopDown => if mem_busy='0' then -- PopDown leaves top of stack unchanged begin_inst <= '1'; idim_flag <= '0'; mem_addr <= incIncSp; out_mem_req <= '1'; sp <= incSp; state <= State_Popped; else insn <= insn; end if; when State_Or => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; stackA <= stackA or stackB; out_mem_req <= '1'; mem_addr <= incIncSp; sp <= incSp; state <= State_Popped; else insn <= insn; end if; when State_And => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; stackA <= stackA and stackB; out_mem_req <= '1'; mem_addr <= incIncSp; sp <= incSp; state <= State_Popped; else insn <= insn; end if; when State_Eq => begin_inst <= '1'; idim_flag <= '0'; binaryOpResult <= (others => '0'); if (stackA=stackB) then binaryOpResult(0) <= '1'; end if; state <= State_BinaryOpResult; when State_Ulessthan => begin_inst <= '1'; idim_flag <= '0'; binaryOpResult <= (others => '0'); if (stackA<stackB) then binaryOpResult(0) <= '1'; end if; state <= State_BinaryOpResult; when State_Ulessthanorequal => begin_inst <= '1'; idim_flag <= '0'; binaryOpResult <= (others => '0'); if (stackA<=stackB) then binaryOpResult(0) <= '1'; end if; state <= State_BinaryOpResult; when State_Lessthan => begin_inst <= '1'; idim_flag <= '0'; binaryOpResult <= (others => '0'); if (signed(stackA)<signed(stackB)) then binaryOpResult(0) <= '1'; end if; state <= State_BinaryOpResult; when State_Lessthanorequal => begin_inst <= '1'; idim_flag <= '0'; binaryOpResult <= (others => '0'); if (signed(stackA)<=signed(stackB)) then binaryOpResult(0) <= '1'; end if; state <= State_BinaryOpResult; when State_Load => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; state <= State_Load2; mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); out_mem_req <= '1'; else insn <= insn; end if; when State_Dup => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; sp <= decSp; stackB <= stackA; mem_write <= stackB; mem_addr <= incSp; out_mem_req <= '1'; mem_we <= '1'; else insn <= insn; end if; when State_DupStackB => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; sp <= decSp; stackA <= stackB; stackB <= stackA; mem_write <= stackB; mem_addr <= incSp; out_mem_req <= '1'; mem_we <= '1'; else insn <= insn; end if; when State_Store => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); mem_write <= stackB; out_mem_req <= '1'; mem_we <= '1'; sp <= incIncSp; state <= State_Resync; else insn <= insn; end if; when State_PopSP => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; mem_write <= stackB; mem_addr <= incSp; out_mem_req <= '1'; mem_we <= '1'; sp <= stackA(maxAddrBitIncIO downto minAddrBit); state <= State_Resync; else insn <= insn; end if; when State_Nop => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; when State_Not => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; stackA <= not stackA; when State_Flip => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; for i in 0 to wordSize-1 loop stackA(i) <= stackA(wordSize-1-i); end loop; when State_AddTop => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; stackA <= stackA + stackB; when State_Shift => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0); stackA(0) <= '0'; when State_Pushspadd => begin_inst <= '1'; idim_flag <= '0'; pc <= pc + 1; stackA <= (others => '0'); stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp; when State_Neqbranch => -- branches are almost always taken as they form loops begin_inst <= '1'; idim_flag <= '0'; sp <= incIncSp; if (stackB/=0) then pc <= stackA(maxAddrBitIncIO downto 0) + pc; else pc <= pc + 1; end if; -- need to fetch stack again. state <= State_Resync; when State_Mult => begin_inst <= '1'; idim_flag <= '0'; multA <= stackA; multB <= stackB; state <= State_Mult2; when State_Break => report "Break instruction encountered" severity failure; break <= '1'; when State_Loadb => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; state <= State_Loadb2; mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); out_mem_req <= '1'; else insn <= insn; end if; when State_Storeb => if mem_busy='0' then begin_inst <= '1'; idim_flag <= '0'; state <= State_Storeb2; mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); out_mem_req <= '1'; else insn <= insn; end if; when others => -- sp <= (others => DontCareValue); report "Illegal instruction" severity failure; break <= '1'; end case; when State_StoreSP2 => if mem_busy='0' then mem_addr <= incSp; out_mem_req <= '1'; state <= State_Popped; end if; when State_LoadSP2 => if mem_busy='0' then state <= State_LoadSP3; out_mem_req <= '1'; mem_addr <= sp+spOffset+1; end if; when State_LoadSP3 => if mem_busy='0' then pc <= pc + 1; state <= State_Execute; stackB <= stackA; stackA <= mem_read; end if; when State_AddSP2 => if mem_busy='0' then pc <= pc + 1; state <= State_Execute; stackA <= stackA + mem_read; end if; when State_Load2 => if mem_busy='0' then stackA <= mem_read; pc <= pc + 1; state <= State_Execute; end if; when State_Loadb2 => if mem_busy='0' then stackA <= (others => '0'); stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8); pc <= pc + 1; state <= State_Execute; end if; when State_Storeb2 => if mem_busy='0' then mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit); mem_write <= mem_read; mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ; out_mem_req <= '1'; mem_we <= '1'; pc <= pc + 1; sp <= incIncSp; state <= State_Resync; end if; when State_Fetch => if mem_busy='0' then if interrupt='1' and inInterrupt='0' and idim_flag='0' then -- We got an interrupt inInterrupt <= '1'; sp <= decSp; out_mem_req <= '1'; mem_we <= '1'; mem_addr <= incSp; mem_write <= stackB; stackA <= (others => DontCareValue); stackA(maxAddrBitIncIO downto 0) <= pc; stackB <= stackA; pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address report "ZPU jumped to interrupt!" severity note; else mem_addr <= pc(maxAddrBitIncIO downto minAddrBit); out_mem_req <= '1'; state <= State_Decode; end if; end if; when State_Mult2 => state <= State_Mult3; when State_Mult3 => state <= State_Mult4; when State_Mult4 => state <= State_Mult5; when State_Mult5 => stackA <= multResult3; state <= State_Mult6; when State_Mult6 => if mem_busy='0' then out_mem_req <= '1'; mem_addr <= incIncSp; sp <= incSp; state <= State_Popped; end if; when State_BinaryOpResult => if mem_busy='0' then -- NB!!!! we know that the memory isn't busy at this point!!!! out_mem_req <= '1'; mem_addr <= incIncSp; sp <= incSp; stackA <= binaryOpResult; state <= State_Popped; end if; when State_Popped => if mem_busy='0' then pc <= pc + 1; stackB <= mem_read; state <= State_Execute; end if; when others => -- sp <= (others => DontCareValue); report "Illegal state" severity failure; break <= '1'; end case; end if; end process; end behave;

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Martin Zabel -- Patrick Lehmann -- -- Module: Instantiate single-port memory on Altera FPGAs. -- -- Description: -- ------------------------------------ -- Quartus synthesis does not infer this RAM type correctly. -- Instead, altsyncram is instantiated directly. -- -- For further documentation see module "ocram_sp" -- (src/mem/ocram/ocram_sp.vhdl). -- -- License: -- ============================================================================ -- Copyright 2008-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library altera_mf; use altera_mf.all; library PoC; use PoC.utils.all; use PoC.strings.all; entity ocram_sp_altera is generic ( A_BITS : positive; D_BITS : positive; FILENAME : STRING := "" ); port ( clk : in std_logic; ce : in std_logic; we : in std_logic; a : in unsigned(A_BITS-1 downto 0); d : in std_logic_vector(D_BITS-1 downto 0); q : out std_logic_vector(D_BITS-1 downto 0) ); end entity; architecture rtl of ocram_sp_altera is component altsyncram generic ( address_aclr_a : STRING; indata_aclr_a : STRING; init_file : STRING; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; numwords_a : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_reg_a : STRING; power_up_uninitialized : STRING; widthad_a : NATURAL; width_a : NATURAL; width_byteena_a : NATURAL; wrcontrol_aclr_a : STRING ); port ( clocken0 : in STD_LOGIC; wren_a : in STD_LOGIC; clock0 : in STD_LOGIC; address_a : in STD_LOGIC_VECTOR(widthad_a-1 downto 0); q_a : out STD_LOGIC_VECTOR(width_a-1 downto 0); data_a : in STD_LOGIC_VECTOR(width_a-1 downto 0) ); end component; constant DEPTH : positive := 2**A_BITS; constant INIT_FILE : STRING := ite((str_length(FILENAME) = 0), "UNUSED", FILENAME); signal a_sl : std_logic_vector(A_BITS-1 downto 0); begin a_sl <= std_logic_vector(a); mem : altsyncram generic map ( address_aclr_a => "NONE", indata_aclr_a => "NONE", init_file => INIT_FILE, intended_device_family => "Stratix", lpm_hint => "ENABLE_RUNTIME_MOD = NO", lpm_type => "altsyncram", numwords_a => DEPTH, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "UNREGISTERED", power_up_uninitialized => "FALSE", widthad_a => A_BITS, width_a => D_BITS, width_byteena_a => 1, wrcontrol_aclr_a => "NONE" ) port map ( clocken0 => ce, wren_a => we, clock0 => clk, address_a => a_sl, data_a => d, q_a => q ); end architecture;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; library work; use work.Display_Management_pkg.all; entity OSD_border is --=========================================================================== generic( enable_debug : boolean := true; resolution : string := "1920x1080@60Hz" ); port( ------globally routed signals------- pixel_Clock : in std_logic; Reset_n : in std_logic; --=========== Inputs ============== --------------- VGA ---------------- vga_in : in internal_video_type; --=========== Outputs ============== --------------- VGA ---------------- vga_out : out internal_video_type ); end OSD_border; architecture arch_OSD_border of OSD_border is --============================================ -- ============================= Parameters ====================================================== ------------ General Parameters ---------------- constant format : format_type := init_video_type(enable_debug, resolution); constant timing : timing_type := init_timing_type(format); constant shifted_border : natural := 0; -- ============================= End of the Parameters =========================================== signal visible_pixel : pixel_type; signal phase_adjust : internal_video_type; signal border_detected : boolean; signal on_border : boolean; begin --========================================================================================== -------------------------------------------------------------- -- Counter horizontal visible_pixel -------------------------------------------------------------- process (pixel_Clock) is begin if rising_edge(pixel_Clock) then if (Reset_n = '0') then visible_pixel.x <= to_unsigned(0, nbits_pixel); --Need for force the first sync signal and for not lose the first frame elsif (vga_in.H_sync = '1') then visible_pixel.x <= to_unsigned(0, nbits_pixel); elsif(vga_in.addressable_area = '1') then visible_pixel.x <= visible_pixel.x + to_unsigned(1, nbits_pixel); end if; end if; end process; -------------------------------------------------------------- -- Counter vertical visible_pixel -------------------------------------------------------------- process (pixel_Clock) is begin if rising_edge(pixel_Clock) then if (Reset_n = '0') then visible_pixel.y <= to_unsigned(0, nbits_pixel); --Need for force the first sync signal and for not lose the first frame elsif (vga_in.V_sync = '1') then visible_pixel.y <= to_unsigned(0, nbits_pixel); elsif (visible_pixel.x = (format.Hor_Addr_Time-1) ) then visible_pixel.y <= visible_pixel.y + to_unsigned(1, nbits_pixel); end if; end if; end process; -------------------------------------------------------------- -- Phase adjust -------------------------------------------------------------- --Writing Shortcut because All the signal are synchrone of the pixel_Clock ! on_border <= ( (visible_pixel.y = to_unsigned(0 + shifted_border, nbits_pixel)) or (visible_pixel.y = (format.Ver_Addr_Time-to_unsigned(1 + shifted_border, nbits_pixel)) ) -- horizontal border or (visible_pixel.x = to_unsigned(0 + shifted_border, nbits_pixel)) or (visible_pixel.x = (format.Hor_Addr_Time-to_unsigned(1 + shifted_border, nbits_pixel)) ) -- vertical border ); process (pixel_Clock) is begin if rising_edge(pixel_Clock) then phase_adjust <= vga_in; border_detected <= (on_border = true) and (vga_in.addressable_area = '1'); end if; end process; -------------------------------------------------------------- -- Color management while the Active Video periode -------------------------------------------------------------- process (pixel_Clock) is begin if rising_edge(pixel_Clock) then --When we are on the border if (border_detected = true) then vga_out.red <= (others => '0'); vga_out.green <= (others => '1'); vga_out.blue <= (others => '0'); vga_out.H_sync <= phase_adjust.H_sync; vga_out.V_sync <= phase_adjust.V_sync; vga_out.addressable_area <= phase_adjust.addressable_area; --otherwise do nothing else vga_out <= phase_adjust; end if; end if; end process; end arch_OSD_border;

-- ------------------------------------------------------------- -- -- Generated Configuration for ddrv4 -- -- Generated -- by: wig -- on: Mon Jul 18 15:56:34 2005 -- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: ddrv4-rtl-conf-c.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $ -- $Date: 2005/07/19 07:13:11 $ -- $Log: ddrv4-rtl-conf-c.vhd,v $ -- Revision 1.3 2005/07/19 07:13:11 wig -- Update testcases. Added highlow/nolowbus -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.36 , [email protected] -- (C) 2003 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/conf -- -- Start of Generated Configuration ddrv4_rtl_conf / ddrv4 -- configuration ddrv4_rtl_conf of ddrv4 is for rtl -- Generated Configuration for d_ls_hr : ddrv use configuration work.d_ls_hr_RTL_CONF; end for; for d_ls_min : ddrv use configuration work.d_ls_min_RTL_CONF; end for; for d_ms_hr : ddrv use configuration work.d_ms_hr_RTL_CONF; end for; for d_ms_min : ddrv use configuration work.d_ms_min_RTL_CONF; end for; for u_and_f : and_f use configuration work.u_and_f_RTL_CONF; end for; end for; end ddrv4_rtl_conf; -- -- End of Generated Configuration ddrv4_rtl_conf -- -- --!End of Configuration/ies -- --------------------------------------------------------------

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity cmp01 is port (l : std_logic_vector(3 downto 0); r : std_logic_vector(3 downto 0); eq : out std_logic; ne : out std_logic; lt : out std_logic; le : out std_logic; ge : out std_logic; gt : out std_logic); end cmp01; architecture behav of cmp01 is begin eq <= '1' when unsigned(l) = unsigned(r) else '0'; ne <= '1' when unsigned(l) /= unsigned(r) else '0'; lt <= '1' when unsigned(l) < unsigned(r) else '0'; le <= '1' when unsigned(l) <= unsigned(r) else '0'; gt <= '1' when unsigned(l) > unsigned(r) else '0'; ge <= '1' when unsigned(l) >= unsigned(r) else '0'; end behav;

-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.0 -- IP Revision: 7 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_0; USE floating_point_v7_0.floating_point_v7_0; ENTITY HLS_accel_ap_dmul_4_max_dsp_64 IS PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) ); END HLS_accel_ap_dmul_4_max_dsp_64; ARCHITECTURE HLS_accel_ap_dmul_4_max_dsp_64_arch OF HLS_accel_ap_dmul_4_max_dsp_64 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF HLS_accel_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_0 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF HLS_accel_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2014.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF HLS_accel_ap_dmul_4_max_dsp_64_arch : ARCHITECTURE IS "HLS_accel_ap_dmul_4_max_dsp_64,floating_point_v7_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF HLS_accel_ap_dmul_4_max_dsp_64_arch: ARCHITECTURE IS "HLS_accel_ap_dmul_4_max_dsp_64,floating_point_v7_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=4,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_0 GENERIC MAP ( C_XDEVICEFAMILY => "virtex7", C_HAS_ADD => 0, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 1, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 64, C_A_FRACTION_WIDTH => 53, C_B_WIDTH => 64, C_B_FRACTION_WIDTH => 53, C_C_WIDTH => 64, C_C_FRACTION_WIDTH => 53, C_RESULT_WIDTH => 64, C_RESULT_FRACTION_WIDTH => 53, C_COMPARE_OPERATION => 8, C_LATENCY => 4, C_OPTIMIZATION => 1, C_MULT_USAGE => 3, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 1, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 1, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 64, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 64, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 64, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 64, C_RESULT_TUSER_WIDTH => 1 ) PORT MAP ( aclk => aclk, aclken => aclken, aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => s_axis_b_tvalid, s_axis_b_tdata => s_axis_b_tdata, s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END HLS_accel_ap_dmul_4_max_dsp_64_arch;

---------------------------------------------------------------------------------- -- Engineer: Mike Field <[email protected]> -- -- Module Name: scrambler_all_channels - Behavioral -- Description: A x^16+x^5+x^4+x^3+1 LFSR scxrambler for DisplayPort -- -- Scrambler LFSR is reset when a K.28.0 passes through it, -- as per the DisplayPort spec. -- -- Verified against the table in Apprndix C of the "PCI Express Base -- Specification 2.1" which uses the same polynomial. -- -- Here are the first 32 output words when data values of "00" are scrambled: -- -- | 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F -- ---+------------------------------------------------ -- 00 | FF 17 C0 14 B2 E7 02 82 72 6E 28 A6 BE 6D BF 8D -- 10 | BE 40 A7 E6 2C D3 E2 B2 07 02 77 2A CD 34 BE E0 -- ---------------------------------------------------------------------------------- -- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort ------------------------------------------------------------------------------------ -- The MIT License (MIT) -- -- Copyright (c) 2015 Michael Alan Field <[email protected]> -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. ------------------------------------------------------------------------------------ ----- Want to say thanks? ---------------------------------------------------------- ------------------------------------------------------------------------------------ -- -- This design has taken many hours - 3 months of work. I'm more than happy -- to share it if you can make use of it. It is released under the MIT license, -- so you are not under any onus to say thanks, but.... -- -- If you what to say thanks for this design either drop me an email, or how about -- trying PayPal to my email ([email protected])? -- -- Educational use - Enough for a beer -- Hobbyist use - Enough for a pizza -- Research use - Enough to take the family out to dinner -- Commercial use - A weeks pay for an engineer (I wish!) -------------------------------------------------------------------------------------- -- Ver | Date | Change --------+------------+--------------------------------------------------------------- -- 0.1 | 2015-10-17 | Initial Version ------------------------------------------------------------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity scrambler_all_channels is Port ( clk : in STD_LOGIC; bypass0 : in STD_LOGIC; bypass1 : in STD_LOGIC; in_data : in STD_LOGIC_VECTOR (71 downto 0); out_data : out STD_LOGIC_VECTOR (71 downto 0) := (others => '0')); end scrambler_all_channels; architecture Behavioral of scrambler_all_channels is type a_delay_line is array(0 to 7) of STD_LOGIC_VECTOR (17 downto 0); signal lfsr_state : STD_LOGIC_VECTOR (15 downto 0) := (others => '1'); constant SR : STD_LOGIC_VECTOR ( 8 downto 0) := "100011100"; -- K28.0 ia used to reset the scrambler signal scramble_delay : a_delay_line := (others => (others => '0')); begin process(clk) variable s0 : STD_LOGIC_VECTOR (15 downto 0); variable s1 : STD_LOGIC_VECTOR (15 downto 0); variable flipping : STD_LOGIC_VECTOR (17 downto 0); begin if rising_edge(clk) then s0 := lfsr_state; -- generate intermediate scrambler state if in_data(8 downto 0) = SR then s1 := x"FFFF"; else s1(0) := s0(8); s1(1) := s0(9); s1(2) := s0(10); s1(3) := s0(11) xor s0(8); s1(4) := s0(12) xor s0(8) xor s0(9); s1(5) := s0(13) xor s0(8) xor s0(9) xor s0(10); s1(6) := s0(14) xor s0(9) xor s0(10) xor s0(11); s1(7) := s0(15) xor s0(10) xor s0(11) xor s0(12); s1(8) := s0(0) xor s0(11) xor s0(12) xor s0(13); s1(9) := s0(1) xor s0(12) xor s0(13) xor s0(14); s1(10) := s0(2) xor s0(13) xor s0(14) xor s0(15); s1(11) := s0(3) xor s0(14) xor s0(15); s1(12) := s0(4) xor s0(15); s1(13) := s0(5); s1(14) := s0(6); s1(15) := s0(7); end if; -- Update scrambler state if in_data(17 downto 9) = SR then lfsr_state <= x"FFFF"; else lfsr_state(0) <= s1(8); lfsr_state(1) <= s1(9); lfsr_state(2) <= s1(10); lfsr_state(3) <= s1(11) xor s1(8); lfsr_state(4) <= s1(12) xor s1(8) xor s1(9); lfsr_state(5) <= s1(13) xor s1(8) xor s1(9) xor s1(10); lfsr_state(6) <= s1(14) xor s1(9) xor s1(10) xor s1(11); lfsr_state(7) <= s1(15) xor s1(10) xor s1(11) xor s1(12); lfsr_state(8) <= s1(0) xor s1(11) xor s1(12) xor s1(13); lfsr_state(9) <= s1(1) xor s1(12) xor s1(13) xor s1(14); lfsr_state(10) <= s1(2) xor s1(13) xor s1(14) xor s1(15); lfsr_state(11) <= s1(3) xor s1(14) xor s1(15); lfsr_state(12) <= s1(4) xor s1(15); lfsr_state(13) <= s1(5); lfsr_state(14) <= s1(6); lfsr_state(15) <= s1(7); end if; -------------------------------------------- -- Calculate a vector of bits to be flipped -------------------------------------------- if in_data(8) = '0' and bypass0 = '0' then flipping(8 downto 0) := '0' & s0(8) & s0(9) & s0(10) & s0(11) & s0(12) & s0(13) & s0(14) & s0(15); else flipping(8 downto 0) := (others => '0'); end if; if in_data(17) = '0' and bypass1 = '0' then flipping(17 downto 9) := '0' & s1(8) & s1(9) & s1(10) & s1(11) & s1(12) & s1(13) & s1(14) & s1(15); else flipping(17 downto 9) := (others => '0'); end if; -------------------------------------------- -- Apply vector to channel 0 -------------------------------------------- out_data <= in_data xor (flipping & flipping & flipping & flipping ); end if; end process; end Behavioral;

library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity sub_586 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(31 downto 0) ); end sub_586; architecture augh of sub_586 is signal carry_inA : std_logic_vector(33 downto 0); signal carry_inB : std_logic_vector(33 downto 0); signal carry_res : std_logic_vector(33 downto 0); begin -- To handle the CI input, the operation is '0' - CI -- If CI is not present, the operation is '0' - '0' carry_inA <= '0' & in_a & '0'; carry_inB <= '0' & in_b & '0'; -- Compute the result carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); -- Set the outputs result <= carry_res(32 downto 1); end architecture;

library ieee; use ieee.std_logic_1164.all; entity bshift is port ( left: in std_logic; -- '1' for left, '0' for right logical: in std_logic; -- '1' for logical, '0' for arithmetic shift: in std_logic_vector(4 downto 0); -- shift count input: in std_logic_vector (31 downto 0); output: out std_logic_vector (31 downto 0) ); end entity bshift; architecture logic of bshift is signal shift1l, shift2l, shift4l, shift8l, shift16l : std_logic_vector(31 downto 0); signal shift1r, shift2r, shift4r, shift8r, shift16r : std_logic_vector(31 downto 0); signal fill : std_logic_vector(31 downto 16); begin fill <= (others => input(31)) when logical = '0' else x"0000"; shift1l <= input(30 downto 0) & '0' when shift(0) = '1' else input; shift2l <= shift1l(29 downto 0) & "00" when shift(1) = '1' else shift1l; shift4l <= shift2l(27 downto 0) & x"0" when shift(2) = '1' else shift2l; shift8l <= shift4l(23 downto 0) & x"00" when shift(3) = '1' else shift4l; shift16l <= shift8l(15 downto 0) & x"0000" when shift(4) = '1' else shift8l; shift1r <= fill(31) & input(31 downto 1) when shift(0) = '1' else input; shift2r <= fill(31 downto 30) & shift1r(31 downto 2) when shift(1) = '1' else shift1r; shift4r <= fill(31 downto 28) & shift2r(31 downto 4) when shift(2) = '1' else shift2r; shift8r <= fill(31 downto 24) & shift4r(31 downto 8) when shift(3) = '1' else shift4r; shift16r <= fill(31 downto 16) & shift8r(31 downto 16) when shift(4) = '1' else shift8r; output <= shift16r when left = '0' else shift16l; end;

-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc871.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c01s03b01x00p12n01i00871pkg is constant low_number : integer := 0; constant hi_number : integer := 3; subtype hi_to_low_range is integer range low_number to hi_number; type boolean_vector is array (natural range <>) of boolean; type severity_level_vector is array (natural range <>) of severity_level; type integer_vector is array (natural range <>) of integer; type real_vector is array (natural range <>) of real; type time_vector is array (natural range <>) of time; type natural_vector is array (natural range <>) of natural; type positive_vector is array (natural range <>) of positive; type record_std_package is record a: boolean; b: bit; c:character; d:severity_level; e:integer; f:real; g:time; h:natural; i:positive; end record; type array_rec_std is array (natural range <>) of record_std_package; type four_value is ('Z','0','1','X'); --enumerated type constant C1 : boolean := true; constant C2 : bit := '1'; constant C3 : character := 's'; constant C4 : severity_level := note; constant C5 : integer := 3; constant C6 : real := 3.0; constant C7 : time := 3 ns; constant C8 : natural := 1; constant C9 : positive := 1; signal Sin1 : bit_vector(0 to 5) ; signal Sin2 : boolean_vector(0 to 5) ; signal Sin4 : severity_level_vector(0 to 5) ; signal Sin5 : integer_vector(0 to 5) ; signal Sin6 : real_vector(0 to 5) ; signal Sin7 : time_vector(0 to 5) ; signal Sin8 : natural_vector(0 to 5) ; signal Sin9 : positive_vector(0 to 5) ; signal Sin10: array_rec_std(0 to 5) ; end c01s03b01x00p12n01i00871pkg; use work.c01s03b01x00p12n01i00871pkg.all; entity test is port( sigin1 : in boolean ; sigout1 : out boolean ; sigin2 : in bit ; sigout2 : out bit ; sigin4 : in severity_level ; sigout4 : out severity_level ; sigin5 : in integer ; sigout5 : out integer ; sigin6 : in real ; sigout6 : out real ; sigin7 : in time ; sigout7 : out time ; sigin8 : in natural ; sigout8 : out natural ; sigin9 : in positive ; sigout9 : out positive ; sigin10 : in record_std_package ; sigout10 : out record_std_package ); end; architecture test of test is begin sigout1 <= sigin1; sigout2 <= sigin2; sigout4 <= sigin4; sigout5 <= sigin5; sigout6 <= sigin6; sigout7 <= sigin7; sigout8 <= sigin8; sigout9 <= sigin9; sigout10 <= sigin10; end; configuration testbench of test is for test end for; end; use work.c01s03b01x00p12n01i00871pkg.all; entity test1 is port( sigin1 : in boolean ; sigout1 : out boolean ; sigin2 : in bit ; sigout2 : out bit ; sigin4 : in severity_level ; sigout4 : out severity_level ; sigin5 : in integer ; sigout5 : out integer ; sigin6 : in real ; sigout6 : out real ; sigin7 : in time ; sigout7 : out time ; sigin8 : in natural ; sigout8 : out natural ; sigin9 : in positive ; sigout9 : out positive ; sigin10 : in record_std_package ; sigout10 : out record_std_package ); end; architecture test1 of test1 is begin sigout1 <= false; sigout2 <= '0'; sigout4 <= error; sigout5 <= 6; sigout6 <= 6.0; sigout7 <= 6 ns; sigout8 <= 6; sigout9 <= 6; sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6); end; configuration test1bench of test1 is for test1 end for; end; use work.c01s03b01x00p12n01i00871pkg.all; ENTITY c01s03b01x00p12n01i00871ent IS generic( zero : integer := 0; one : integer := 1; two : integer := 2; three: integer := 3; four : integer := 4; five : integer := 5; six : integer := 6; seven: integer := 7; eight: integer := 8; nine : integer := 9; fifteen:integer:= 15); port( dumy : inout bit_vector(zero to three)); END c01s03b01x00p12n01i00871ent; ARCHITECTURE c01s03b01x00p12n01i00871arch OF c01s03b01x00p12n01i00871ent IS component test port( sigin1 : in boolean ; sigout1 : out boolean ; sigin2 : in bit ; sigout2 : out bit ; sigin4 : in severity_level ; sigout4 : out severity_level ; sigin5 : in integer ; sigout5 : out integer ; sigin6 : in real ; sigout6 : out real ; sigin7 : in time ; sigout7 : out time ; sigin8 : in natural ; sigout8 : out natural ; sigin9 : in positive ; sigout9 : out positive ; sigin10 : in record_std_package ; sigout10 : out record_std_package ); end component; begin Sin1(zero) <='1'; Sin2(zero) <= true; Sin4(zero) <= note; Sin5(zero) <= 3; Sin6(zero) <= 3.0; Sin7(zero) <= 3 ns; Sin8(zero) <= 1; Sin9(zero) <= 1; Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9); K:block BEGIN T5 : test port map ( Sin2(4),Sin2(5), Sin1(4),Sin1(5), Sin4(4),Sin4(5), Sin5(4),Sin5(5), Sin6(4),Sin6(5), Sin7(4),Sin7(5), Sin8(4),Sin8(5), Sin9(4),Sin9(5), Sin10(4),Sin10(5) ); G: for i in zero to three generate T1:test port map ( Sin2(i),Sin2(i+1), Sin1(i),Sin1(i+1), Sin4(i),Sin4(i+1), Sin5(i),Sin5(i+1), Sin6(i),Sin6(i+1), Sin7(i),Sin7(i+1), Sin8(i),Sin8(i+1), Sin9(i),Sin9(i+1), Sin10(i),Sin10(i+1) ); end generate; end block; TESTING: PROCESS variable dumb : bit_vector(zero to three); BEGIN wait for 1 ns; assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure; assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure; assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure; assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure; assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure; assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure; assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure; assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure; assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure; assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure; assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure; assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure; assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure; assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure; assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure; assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure; assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure; assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure; assert NOT( Sin1(0) = sin1(4) and Sin2(0) = Sin2(4) and Sin4(0) = Sin4(4) and Sin5(0) = Sin5(4) and Sin6(0) = Sin6(4) and Sin7(0) = Sin7(4) and Sin8(0) = Sin8(4) and Sin9(0) = Sin9(4) and Sin10(0)= Sin10(4) and Sin1(5) = '0' and Sin2(5) = FALSE and Sin4(5) = error and Sin5(5) = 6 and Sin6(5) = 6.0 and Sin7(5) = 6 ns and Sin8(5) = 6 and Sin9(5) = 6 and Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6)) report "***PASSED TEST: c01s03b01x00p12n01i00871" severity NOTE; assert ( Sin1(0) = sin1(4) and Sin2(0) = Sin2(4) and Sin4(0) = Sin4(4) and Sin5(0) = Sin5(4) and Sin6(0) = Sin6(4) and Sin7(0) = Sin7(4) and Sin8(0) = Sin8(4) and Sin9(0) = Sin9(4) and Sin10(0)= Sin10(4) and Sin1(5) = '0' and Sin2(5) = FALSE and Sin4(5) = error and Sin5(5) = 6 and Sin6(5) = 6.0 and Sin7(5) = 6 ns and Sin8(5) = 6 and Sin9(5) = 6 and Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6)) report "***FAILED TEST: c01s03b01x00p12n01i00871 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index." severity ERROR; wait; END PROCESS TESTING; END c01s03b01x00p12n01i00871arch; configuration c01s03b01x00p12n01i00871cfg of c01s03b01x00p12n01i00871ent is for c01s03b01x00p12n01i00871arch for K for all:test use configuration work.test1bench; end for; for G(0 to 3) for T1 :test use configuration work.testbench; end for; end for; end for; end for; end;

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:fifo_generator:12.0 -- IP Revision: 3 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY fifo_generator_v12_0; USE fifo_generator_v12_0.fifo_generator_v12_0; ENTITY DPBSCFIFO64x64WC IS PORT ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END DPBSCFIFO64x64WC; ARCHITECTURE DPBSCFIFO64x64WC_arch OF DPBSCFIFO64x64WC IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "yes"; COMPONENT fifo_generator_v12_0 IS GENERIC ( C_COMMON_CLOCK : INTEGER; C_COUNT_TYPE : INTEGER; C_DATA_COUNT_WIDTH : INTEGER; C_DEFAULT_VALUE : STRING; C_DIN_WIDTH : INTEGER; C_DOUT_RST_VAL : STRING; C_DOUT_WIDTH : INTEGER; C_ENABLE_RLOCS : INTEGER; C_FAMILY : STRING; C_FULL_FLAGS_RST_VAL : INTEGER; C_HAS_ALMOST_EMPTY : INTEGER; C_HAS_ALMOST_FULL : INTEGER; C_HAS_BACKUP : INTEGER; C_HAS_DATA_COUNT : INTEGER; C_HAS_INT_CLK : INTEGER; C_HAS_MEMINIT_FILE : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_RD_DATA_COUNT : INTEGER; C_HAS_RD_RST : INTEGER; C_HAS_RST : INTEGER; C_HAS_SRST : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_VALID : INTEGER; C_HAS_WR_ACK : INTEGER; C_HAS_WR_DATA_COUNT : INTEGER; C_HAS_WR_RST : INTEGER; C_IMPLEMENTATION_TYPE : INTEGER; C_INIT_WR_PNTR_VAL : INTEGER; C_MEMORY_TYPE : INTEGER; C_MIF_FILE_NAME : STRING; C_OPTIMIZATION_MODE : INTEGER; C_OVERFLOW_LOW : INTEGER; C_PRELOAD_LATENCY : INTEGER; C_PRELOAD_REGS : INTEGER; C_PRIM_FIFO_TYPE : STRING; C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER; C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER; C_PROG_EMPTY_TYPE : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER; C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER; C_PROG_FULL_TYPE : INTEGER; C_RD_DATA_COUNT_WIDTH : INTEGER; C_RD_DEPTH : INTEGER; C_RD_FREQ : INTEGER; C_RD_PNTR_WIDTH : INTEGER; C_UNDERFLOW_LOW : INTEGER; C_USE_DOUT_RST : INTEGER; C_USE_ECC : INTEGER; C_USE_EMBEDDED_REG : INTEGER; C_USE_PIPELINE_REG : INTEGER; C_POWER_SAVING_MODE : INTEGER; C_USE_FIFO16_FLAGS : INTEGER; C_USE_FWFT_DATA_COUNT : INTEGER; C_VALID_LOW : INTEGER; C_WR_ACK_LOW : INTEGER; C_WR_DATA_COUNT_WIDTH : INTEGER; C_WR_DEPTH : INTEGER; C_WR_FREQ : INTEGER; C_WR_PNTR_WIDTH : INTEGER; C_WR_RESPONSE_LATENCY : INTEGER; C_MSGON_VAL : INTEGER; C_ENABLE_RST_SYNC : INTEGER; C_ERROR_INJECTION_TYPE : INTEGER; C_SYNCHRONIZER_STAGE : INTEGER; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_HAS_AXI_WR_CHANNEL : INTEGER; C_HAS_AXI_RD_CHANNEL : INTEGER; C_HAS_SLAVE_CE : INTEGER; C_HAS_MASTER_CE : INTEGER; C_ADD_NGC_CONSTRAINT : INTEGER; C_USE_COMMON_OVERFLOW : INTEGER; C_USE_COMMON_UNDERFLOW : INTEGER; C_USE_DEFAULT_SETTINGS : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_AXI_ADDR_WIDTH : INTEGER; C_AXI_DATA_WIDTH : INTEGER; C_AXI_LEN_WIDTH : INTEGER; C_AXI_LOCK_WIDTH : INTEGER; C_HAS_AXI_ID : INTEGER; C_HAS_AXI_AWUSER : INTEGER; C_HAS_AXI_WUSER : INTEGER; C_HAS_AXI_BUSER : INTEGER; C_HAS_AXI_ARUSER : INTEGER; C_HAS_AXI_RUSER : INTEGER; C_AXI_ARUSER_WIDTH : INTEGER; C_AXI_AWUSER_WIDTH : INTEGER; C_AXI_WUSER_WIDTH : INTEGER; C_AXI_BUSER_WIDTH : INTEGER; C_AXI_RUSER_WIDTH : INTEGER; C_HAS_AXIS_TDATA : INTEGER; C_HAS_AXIS_TID : INTEGER; C_HAS_AXIS_TDEST : INTEGER; C_HAS_AXIS_TUSER : INTEGER; C_HAS_AXIS_TREADY : INTEGER; C_HAS_AXIS_TLAST : INTEGER; C_HAS_AXIS_TSTRB : INTEGER; C_HAS_AXIS_TKEEP : INTEGER; C_AXIS_TDATA_WIDTH : INTEGER; C_AXIS_TID_WIDTH : INTEGER; C_AXIS_TDEST_WIDTH : INTEGER; C_AXIS_TUSER_WIDTH : INTEGER; C_AXIS_TSTRB_WIDTH : INTEGER; C_AXIS_TKEEP_WIDTH : INTEGER; C_WACH_TYPE : INTEGER; C_WDCH_TYPE : INTEGER; C_WRCH_TYPE : INTEGER; C_RACH_TYPE : INTEGER; C_RDCH_TYPE : INTEGER; C_AXIS_TYPE : INTEGER; C_IMPLEMENTATION_TYPE_WACH : INTEGER; C_IMPLEMENTATION_TYPE_WDCH : INTEGER; C_IMPLEMENTATION_TYPE_WRCH : INTEGER; C_IMPLEMENTATION_TYPE_RACH : INTEGER; C_IMPLEMENTATION_TYPE_RDCH : INTEGER; C_IMPLEMENTATION_TYPE_AXIS : INTEGER; C_APPLICATION_TYPE_WACH : INTEGER; C_APPLICATION_TYPE_WDCH : INTEGER; C_APPLICATION_TYPE_WRCH : INTEGER; C_APPLICATION_TYPE_RACH : INTEGER; C_APPLICATION_TYPE_RDCH : INTEGER; C_APPLICATION_TYPE_AXIS : INTEGER; C_PRIM_FIFO_TYPE_WACH : STRING; C_PRIM_FIFO_TYPE_WDCH : STRING; C_PRIM_FIFO_TYPE_WRCH : STRING; C_PRIM_FIFO_TYPE_RACH : STRING; C_PRIM_FIFO_TYPE_RDCH : STRING; C_PRIM_FIFO_TYPE_AXIS : STRING; C_USE_ECC_WACH : INTEGER; C_USE_ECC_WDCH : INTEGER; C_USE_ECC_WRCH : INTEGER; C_USE_ECC_RACH : INTEGER; C_USE_ECC_RDCH : INTEGER; C_USE_ECC_AXIS : INTEGER; C_ERROR_INJECTION_TYPE_WACH : INTEGER; C_ERROR_INJECTION_TYPE_WDCH : INTEGER; C_ERROR_INJECTION_TYPE_WRCH : INTEGER; C_ERROR_INJECTION_TYPE_RACH : INTEGER; C_ERROR_INJECTION_TYPE_RDCH : INTEGER; C_ERROR_INJECTION_TYPE_AXIS : INTEGER; C_DIN_WIDTH_WACH : INTEGER; C_DIN_WIDTH_WDCH : INTEGER; C_DIN_WIDTH_WRCH : INTEGER; C_DIN_WIDTH_RACH : INTEGER; C_DIN_WIDTH_RDCH : INTEGER; C_DIN_WIDTH_AXIS : INTEGER; C_WR_DEPTH_WACH : INTEGER; C_WR_DEPTH_WDCH : INTEGER; C_WR_DEPTH_WRCH : INTEGER; C_WR_DEPTH_RACH : INTEGER; C_WR_DEPTH_RDCH : INTEGER; C_WR_DEPTH_AXIS : INTEGER; C_WR_PNTR_WIDTH_WACH : INTEGER; C_WR_PNTR_WIDTH_WDCH : INTEGER; C_WR_PNTR_WIDTH_WRCH : INTEGER; C_WR_PNTR_WIDTH_RACH : INTEGER; C_WR_PNTR_WIDTH_RDCH : INTEGER; C_WR_PNTR_WIDTH_AXIS : INTEGER; C_HAS_DATA_COUNTS_WACH : INTEGER; C_HAS_DATA_COUNTS_WDCH : INTEGER; C_HAS_DATA_COUNTS_WRCH : INTEGER; C_HAS_DATA_COUNTS_RACH : INTEGER; C_HAS_DATA_COUNTS_RDCH : INTEGER; C_HAS_DATA_COUNTS_AXIS : INTEGER; C_HAS_PROG_FLAGS_WACH : INTEGER; C_HAS_PROG_FLAGS_WDCH : INTEGER; C_HAS_PROG_FLAGS_WRCH : INTEGER; C_HAS_PROG_FLAGS_RACH : INTEGER; C_HAS_PROG_FLAGS_RDCH : INTEGER; C_HAS_PROG_FLAGS_AXIS : INTEGER; C_PROG_FULL_TYPE_WACH : INTEGER; C_PROG_FULL_TYPE_WDCH : INTEGER; C_PROG_FULL_TYPE_WRCH : INTEGER; C_PROG_FULL_TYPE_RACH : INTEGER; C_PROG_FULL_TYPE_RDCH : INTEGER; C_PROG_FULL_TYPE_AXIS : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER; C_PROG_EMPTY_TYPE_WACH : INTEGER; C_PROG_EMPTY_TYPE_WDCH : INTEGER; C_PROG_EMPTY_TYPE_WRCH : INTEGER; C_PROG_EMPTY_TYPE_RACH : INTEGER; C_PROG_EMPTY_TYPE_RDCH : INTEGER; C_PROG_EMPTY_TYPE_AXIS : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER; C_REG_SLICE_MODE_WACH : INTEGER; C_REG_SLICE_MODE_WDCH : INTEGER; C_REG_SLICE_MODE_WRCH : INTEGER; C_REG_SLICE_MODE_RACH : INTEGER; C_REG_SLICE_MODE_RDCH : INTEGER; C_REG_SLICE_MODE_AXIS : INTEGER ); PORT ( backup : IN STD_LOGIC; backup_marker : IN STD_LOGIC; clk : IN STD_LOGIC; rst : IN STD_LOGIC; srst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; wr_rst : IN STD_LOGIC; rd_clk : IN STD_LOGIC; rd_rst : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0); int_clk : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; injectsbiterr : IN STD_LOGIC; sleep : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); full : OUT STD_LOGIC; almost_full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; almost_empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); prog_full : OUT STD_LOGIC; prog_empty : OUT STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; wr_rst_busy : OUT STD_LOGIC; rd_rst_busy : OUT STD_LOGIC; m_aclk : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; m_aclk_en : IN STD_LOGIC; s_aclk_en : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_awvalid : OUT STD_LOGIC; m_axi_awready : IN STD_LOGIC; m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_wlast : OUT STD_LOGIC; m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_wvalid : OUT STD_LOGIC; m_axi_wready : IN STD_LOGIC; m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_bvalid : IN STD_LOGIC; m_axi_bready : OUT STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_arvalid : OUT STD_LOGIC; m_axi_arready : IN STD_LOGIC; m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0); m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); m_axi_rlast : IN STD_LOGIC; m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); m_axi_rvalid : IN STD_LOGIC; m_axi_rready : OUT STD_LOGIC; s_axis_tvalid : IN STD_LOGIC; s_axis_tready : OUT STD_LOGIC; s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tlast : IN STD_LOGIC; s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0); m_axis_tvalid : OUT STD_LOGIC; m_axis_tready : IN STD_LOGIC; m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tlast : OUT STD_LOGIC; m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_injectsbiterr : IN STD_LOGIC; axi_aw_injectdbiterr : IN STD_LOGIC; axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_aw_sbiterr : OUT STD_LOGIC; axi_aw_dbiterr : OUT STD_LOGIC; axi_aw_overflow : OUT STD_LOGIC; axi_aw_underflow : OUT STD_LOGIC; axi_aw_prog_full : OUT STD_LOGIC; axi_aw_prog_empty : OUT STD_LOGIC; axi_w_injectsbiterr : IN STD_LOGIC; axi_w_injectdbiterr : IN STD_LOGIC; axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_w_sbiterr : OUT STD_LOGIC; axi_w_dbiterr : OUT STD_LOGIC; axi_w_overflow : OUT STD_LOGIC; axi_w_underflow : OUT STD_LOGIC; axi_w_prog_full : OUT STD_LOGIC; axi_w_prog_empty : OUT STD_LOGIC; axi_b_injectsbiterr : IN STD_LOGIC; axi_b_injectdbiterr : IN STD_LOGIC; axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_b_sbiterr : OUT STD_LOGIC; axi_b_dbiterr : OUT STD_LOGIC; axi_b_overflow : OUT STD_LOGIC; axi_b_underflow : OUT STD_LOGIC; axi_b_prog_full : OUT STD_LOGIC; axi_b_prog_empty : OUT STD_LOGIC; axi_ar_injectsbiterr : IN STD_LOGIC; axi_ar_injectdbiterr : IN STD_LOGIC; axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); axi_ar_sbiterr : OUT STD_LOGIC; axi_ar_dbiterr : OUT STD_LOGIC; axi_ar_overflow : OUT STD_LOGIC; axi_ar_underflow : OUT STD_LOGIC; axi_ar_prog_full : OUT STD_LOGIC; axi_ar_prog_empty : OUT STD_LOGIC; axi_r_injectsbiterr : IN STD_LOGIC; axi_r_injectdbiterr : IN STD_LOGIC; axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axi_r_sbiterr : OUT STD_LOGIC; axi_r_dbiterr : OUT STD_LOGIC; axi_r_overflow : OUT STD_LOGIC; axi_r_underflow : OUT STD_LOGIC; axi_r_prog_full : OUT STD_LOGIC; axi_r_prog_empty : OUT STD_LOGIC; axis_injectsbiterr : IN STD_LOGIC; axis_injectdbiterr : IN STD_LOGIC; axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0); axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); axis_sbiterr : OUT STD_LOGIC; axis_dbiterr : OUT STD_LOGIC; axis_overflow : OUT STD_LOGIC; axis_underflow : OUT STD_LOGIC; axis_prog_full : OUT STD_LOGIC; axis_prog_empty : OUT STD_LOGIC ); END COMPONENT fifo_generator_v12_0; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "fifo_generator_v12_0,Vivado 2014.4.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF DPBSCFIFO64x64WC_arch : ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF DPBSCFIFO64x64WC_arch: ARCHITECTURE IS "DPBSCFIFO64x64WC,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; BEGIN U0 : fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => 6, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => 64, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => 64, C_ENABLE_RLOCS => 0, C_FAMILY => "zynq", C_FULL_FLAGS_RST_VAL => 0, C_HAS_ALMOST_EMPTY => 0, C_HAS_ALMOST_FULL => 0, C_HAS_BACKUP => 0, C_HAS_DATA_COUNT => 1, C_HAS_INT_CLK => 0, C_HAS_MEMINIT_FILE => 0, C_HAS_OVERFLOW => 0, C_HAS_RD_DATA_COUNT => 0, C_HAS_RD_RST => 0, C_HAS_RST => 0, C_HAS_SRST => 1, C_HAS_UNDERFLOW => 0, C_HAS_VALID => 0, C_HAS_WR_ACK => 0, C_HAS_WR_DATA_COUNT => 0, C_HAS_WR_RST => 0, C_IMPLEMENTATION_TYPE => 0, C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => 1, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => 1, C_PRELOAD_REGS => 0, C_PRIM_FIFO_TYPE => "512x72", C_PROG_EMPTY_THRESH_ASSERT_VAL => 2, C_PROG_EMPTY_THRESH_NEGATE_VAL => 3, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 62, C_PROG_FULL_THRESH_NEGATE_VAL => 61, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => 6, C_RD_DEPTH => 64, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => 6, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_ECC => 0, C_USE_EMBEDDED_REG => 0, C_USE_PIPELINE_REG => 0, C_POWER_SAVING_MODE => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => 0, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => 6, C_WR_DEPTH => 64, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => 6, C_WR_RESPONSE_LATENCY => 1, C_MSGON_VAL => 1, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => 2, C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_HAS_AXI_WR_CHANNEL => 1, C_HAS_AXI_RD_CHANNEL => 1, C_HAS_SLAVE_CE => 0, C_HAS_MASTER_CE => 0, C_ADD_NGC_CONSTRAINT => 0, C_USE_COMMON_OVERFLOW => 0, C_USE_COMMON_UNDERFLOW => 0, C_USE_DEFAULT_SETTINGS => 0, C_AXI_ID_WIDTH => 1, C_AXI_ADDR_WIDTH => 32, C_AXI_DATA_WIDTH => 64, C_AXI_LEN_WIDTH => 8, C_AXI_LOCK_WIDTH => 1, C_HAS_AXI_ID => 0, C_HAS_AXI_AWUSER => 0, C_HAS_AXI_WUSER => 0, C_HAS_AXI_BUSER => 0, C_HAS_AXI_ARUSER => 0, C_HAS_AXI_RUSER => 0, C_AXI_ARUSER_WIDTH => 1, C_AXI_AWUSER_WIDTH => 1, C_AXI_WUSER_WIDTH => 1, C_AXI_BUSER_WIDTH => 1, C_AXI_RUSER_WIDTH => 1, C_HAS_AXIS_TDATA => 1, C_HAS_AXIS_TID => 0, C_HAS_AXIS_TDEST => 0, C_HAS_AXIS_TUSER => 1, C_HAS_AXIS_TREADY => 1, C_HAS_AXIS_TLAST => 0, C_HAS_AXIS_TSTRB => 0, C_HAS_AXIS_TKEEP => 0, C_AXIS_TDATA_WIDTH => 8, C_AXIS_TID_WIDTH => 1, C_AXIS_TDEST_WIDTH => 1, C_AXIS_TUSER_WIDTH => 4, C_AXIS_TSTRB_WIDTH => 1, C_AXIS_TKEEP_WIDTH => 1, C_WACH_TYPE => 0, C_WDCH_TYPE => 0, C_WRCH_TYPE => 0, C_RACH_TYPE => 0, C_RDCH_TYPE => 0, C_AXIS_TYPE => 0, C_IMPLEMENTATION_TYPE_WACH => 1, C_IMPLEMENTATION_TYPE_WDCH => 1, C_IMPLEMENTATION_TYPE_WRCH => 1, C_IMPLEMENTATION_TYPE_RACH => 1, C_IMPLEMENTATION_TYPE_RDCH => 1, C_IMPLEMENTATION_TYPE_AXIS => 1, C_APPLICATION_TYPE_WACH => 0, C_APPLICATION_TYPE_WDCH => 0, C_APPLICATION_TYPE_WRCH => 0, C_APPLICATION_TYPE_RACH => 0, C_APPLICATION_TYPE_RDCH => 0, C_APPLICATION_TYPE_AXIS => 0, C_PRIM_FIFO_TYPE_WACH => "512x36", C_PRIM_FIFO_TYPE_WDCH => "1kx36", C_PRIM_FIFO_TYPE_WRCH => "512x36", C_PRIM_FIFO_TYPE_RACH => "512x36", C_PRIM_FIFO_TYPE_RDCH => "1kx36", C_PRIM_FIFO_TYPE_AXIS => "1kx18", C_USE_ECC_WACH => 0, C_USE_ECC_WDCH => 0, C_USE_ECC_WRCH => 0, C_USE_ECC_RACH => 0, C_USE_ECC_RDCH => 0, C_USE_ECC_AXIS => 0, C_ERROR_INJECTION_TYPE_WACH => 0, C_ERROR_INJECTION_TYPE_WDCH => 0, C_ERROR_INJECTION_TYPE_WRCH => 0, C_ERROR_INJECTION_TYPE_RACH => 0, C_ERROR_INJECTION_TYPE_RDCH => 0, C_ERROR_INJECTION_TYPE_AXIS => 0, C_DIN_WIDTH_WACH => 32, C_DIN_WIDTH_WDCH => 64, C_DIN_WIDTH_WRCH => 2, C_DIN_WIDTH_RACH => 32, C_DIN_WIDTH_RDCH => 64, C_DIN_WIDTH_AXIS => 1, C_WR_DEPTH_WACH => 16, C_WR_DEPTH_WDCH => 1024, C_WR_DEPTH_WRCH => 16, C_WR_DEPTH_RACH => 16, C_WR_DEPTH_RDCH => 1024, C_WR_DEPTH_AXIS => 1024, C_WR_PNTR_WIDTH_WACH => 4, C_WR_PNTR_WIDTH_WDCH => 10, C_WR_PNTR_WIDTH_WRCH => 4, C_WR_PNTR_WIDTH_RACH => 4, C_WR_PNTR_WIDTH_RDCH => 10, C_WR_PNTR_WIDTH_AXIS => 10, C_HAS_DATA_COUNTS_WACH => 0, C_HAS_DATA_COUNTS_WDCH => 0, C_HAS_DATA_COUNTS_WRCH => 0, C_HAS_DATA_COUNTS_RACH => 0, C_HAS_DATA_COUNTS_RDCH => 0, C_HAS_DATA_COUNTS_AXIS => 0, C_HAS_PROG_FLAGS_WACH => 0, C_HAS_PROG_FLAGS_WDCH => 0, C_HAS_PROG_FLAGS_WRCH => 0, C_HAS_PROG_FLAGS_RACH => 0, C_HAS_PROG_FLAGS_RDCH => 0, C_HAS_PROG_FLAGS_AXIS => 0, C_PROG_FULL_TYPE_WACH => 0, C_PROG_FULL_TYPE_WDCH => 0, C_PROG_FULL_TYPE_WRCH => 0, C_PROG_FULL_TYPE_RACH => 0, C_PROG_FULL_TYPE_RDCH => 0, C_PROG_FULL_TYPE_AXIS => 0, C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, C_PROG_EMPTY_TYPE_WACH => 0, C_PROG_EMPTY_TYPE_WDCH => 0, C_PROG_EMPTY_TYPE_WRCH => 0, C_PROG_EMPTY_TYPE_RACH => 0, C_PROG_EMPTY_TYPE_RDCH => 0, C_PROG_EMPTY_TYPE_AXIS => 0, C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, C_REG_SLICE_MODE_WACH => 0, C_REG_SLICE_MODE_WDCH => 0, C_REG_SLICE_MODE_WRCH => 0, C_REG_SLICE_MODE_RACH => 0, C_REG_SLICE_MODE_RDCH => 0, C_REG_SLICE_MODE_AXIS => 0 ) PORT MAP ( backup => '0', backup_marker => '0', clk => clk, rst => '0', srst => srst, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => din, wr_en => wr_en, rd_en => rd_en, prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)), int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', sleep => '0', dout => dout, full => full, empty => empty, data_count => data_count, m_aclk => '0', s_aclk => '0', s_aresetn => '0', m_aclk_en => '0', s_aclk_en => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awvalid => '0', s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wlast => '0', s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wvalid => '0', s_axi_bready => '0', m_axi_awready => '0', m_axi_wready => '0', m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_bvalid => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_arvalid => '0', s_axi_rready => '0', m_axi_arready => '0', m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)), m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), m_axi_rlast => '0', m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), m_axi_rvalid => '0', s_axis_tvalid => '0', s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tlast => '0', s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), m_axis_tready => '0', axi_aw_injectsbiterr => '0', axi_aw_injectdbiterr => '0', axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_w_injectsbiterr => '0', axi_w_injectdbiterr => '0', axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_b_injectsbiterr => '0', axi_b_injectdbiterr => '0', axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_injectsbiterr => '0', axi_ar_injectdbiterr => '0', axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), axi_r_injectsbiterr => '0', axi_r_injectdbiterr => '0', axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_injectsbiterr => '0', axis_injectdbiterr => '0', axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)), axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)) ); END DPBSCFIFO64x64WC_arch;

-------------------------------------------------------------------------------- -- -- Title : ctrl_game_block.vhd -- Design : Example -- Author : Kapitanov -- Company : InSys -- -- Version : 1.0 -------------------------------------------------------------------------------- -- -- Description : Main game block for minesweeper -- -- -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use work.ctrl_types_pkg.key_data; use work.ctrl_types_pkg.data8x8; use work.ctrl_types_pkg.data3x8; use work.ctrl_types_pkg.array8x8; use work.ctrl_comp_pkg.all; entity ctrl_game_block is generic( constant yend : std_logic_vector(4 downto 0); --! Y end area constant ystart : std_logic_vector(4 downto 0); --! Y start area constant xend : std_logic_vector(6 downto 0); --! X end area constant xstart : std_logic_vector(6 downto 0) --! X start area ); port( -- system signals: clk : in std_logic; --! clock reset : in std_logic; --! system reset -- keyboard: push_keys : in key_data; --! ps/2 keys -- vga XoY coordinates: display : in std_logic; --! display enable x_char : in std_logic_vector(9 downto 0); --! X line: 0:79 y_char : in std_logic_vector(8 downto 0); --! Y line: 0:29 -- out color scheme: rgb : out std_logic_vector(2 downto 0); --! RGB data leds : out std_logic_vector(8 downto 1) --! 8 LEDs ); end ctrl_game_block; architecture ctrl_game_block of ctrl_game_block is function conv8x8to64 (data_in : array8x8) return std_logic_vector is variable vector64 : std_logic_vector(63 downto 0); begin x_loop8: for jj in 0 to 7 loop y_loop8 :for ii in 0 to 7 loop vector64(ii+jj*8) := data_in(jj)(ii); end loop; end loop; return vector64; end conv8x8to64; component ctrl_8x16_rom is port( clk : in std_logic; -- clock addr : in std_logic_vector(10 downto 0); -- ROM address 2^11 data : out std_logic_vector(7 downto 0) -- ROM data 1 byte ); end component; type game_fsm is (WAIT_START, PLAY, CHECK, GAME_OVER, RST); signal game_status : game_fsm; signal addr_rnd : std_logic_vector(4 downto 0):="00000"; signal show_field, show_bad_msg, display_text: std_logic; signal x_in : std_logic_vector(6 downto 0); signal y_in : std_logic_vector(4 downto 0); signal x_inz : std_logic_vector(6 downto 0); signal x_inzz : std_logic_vector(6 downto 0); signal y_inz : std_logic_vector(4 downto 0); signal y_inzz : std_logic_vector(4 downto 0); signal cnt_yy : std_logic_vector(2 downto 0); signal cnt_xx : std_logic_vector(2 downto 0); signal comp_yy : std_logic_vector(6 downto 0); signal comp_xx : std_logic_vector(4 downto 0); signal rgb1 : std_logic_vector(2 downto 0):="000"; signal rgb2 : std_logic_vector(2 downto 0):="000"; signal rgb3 : std_logic_vector(2 downto 0):="000"; signal rgb4 : std_logic_vector(2 downto 0):="000"; signal rgb5 : std_logic_vector(2 downto 0):="000"; signal kw, ks, ka, kd : std_logic; signal kenter : std_logic; signal kspace : std_logic; signal ky, kn : std_logic; signal kesc : std_logic; signal data_box : std_logic_vector(7 downto 0); signal cnt_mines : std_logic_vector(6 downto 0); signal show_disp : array8x8; signal show_dispz : std_logic_vector(63 downto 0); signal win, lose, game : std_logic; signal cntg : std_logic; signal cnt_flash : std_logic_vector(23 downto 0); begin ---------------- SUMMARY RGB ON DISPLAY ---------------- rgb <= rgb1 or rgb2 or rgb3 or rgb4 or rgb5; ---------------- KEYBOARD ---------------- kw <= push_keys.WSAD(3) after 1 ns when rising_edge(clk); ks <= push_keys.WSAD(2) after 1 ns when rising_edge(clk); ka <= push_keys.WSAD(0) after 1 ns when rising_edge(clk); kd <= push_keys.WSAD(1) after 1 ns when rising_edge(clk); ky <= push_keys.ky after 1 ns when rising_edge(clk); kn <= push_keys.kn after 1 ns when rising_edge(clk); kspace <= push_keys.Space after 1 ns when rising_edge(clk); kenter <= push_keys.Enter after 1 ns when rising_edge(clk); kesc <= push_keys.Esc after 1 ns when rising_edge(clk); ---------------- LEDS ON DISPLAY ---------------- leds(1) <= kenter; leds(2) <= kw or ks or ka or kd; leds(3) <= ky or kn; leds(4) <= show_field; leds(5) <= display; leds(6) <= cnt_flash(23); ---------------- MOVING COUNTERS ---------------- pr_start: process(reset, clk) is begin if reset = '0' then cnt_xx <= "000"; cnt_yy <= "000"; elsif rising_edge(clk) then case game_status is when PLAY => if kw = '1' then cnt_yy <= cnt_yy - 1; elsif ks = '1' then cnt_yy <= cnt_yy + 1; else null; end if; if ka = '1' then cnt_xx <= cnt_xx + 1; elsif kd = '1' then cnt_xx <= cnt_xx - 1; else null; end if; when RST | GAME_OVER | WAIT_START => cnt_xx <= "000"; cnt_yy <= "000"; when others => null; end case; end if; end process; comp_yy <= "0000" & cnt_yy; comp_xx <= "00" & cnt_xx; ---------------- XoY COORDINATES ---------------- x_in <= x_char(9 downto 3); y_in <= y_char(8 downto 4); x_inz <= x_in after 1 ns when rising_edge(clk); y_inz <= y_in after 1 ns when rising_edge(clk); x_inzz <= x_inz after 1 ns when rising_edge(clk); y_inzz <= y_inz after 1 ns when rising_edge(clk); ---------------- GLOABAL FSM ---------------- pr_game_status: process(clk, reset) is begin if reset = '0' then game_status <= WAIT_START; show_field <= '0'; show_bad_msg <= '0'; addr_rnd <= (others => '0'); display_text <= '0'; win <= '0'; lose <= '0'; game <= '0'; cntg <= '0'; cnt_flash <= (others => '0'); elsif rising_edge(clk) then case game_status is when WAIT_START => display_text <= '1'; show_bad_msg <= '0'; win <= '0'; game <= '0'; lose <= '0'; cntg <= '0'; addr_rnd <= addr_rnd + '1'; -- UNCOMMENT LATER!! if kspace = '1' then game_status <= PLAY; show_field <= '1'; end if; when PLAY => cntg <= '1'; if kesc = '1' then game_status <= WAIT_START; else if cnt_mines = "111000" then show_bad_msg <= '0'; game_status <= GAME_OVER; else if kenter = '1' then game_status <= CHECK; else null; end if; end if; end if; when CHECK => if (x_inzz = (xstart + comp_xx)) and (y_inzz = (ystart + comp_yy)) then if data_box = x"0F" then show_bad_msg <= '1'; game_status <= GAME_OVER; else game_status <= PLAY; end if; end if; when GAME_OVER => cnt_flash <= cnt_flash + '1'; if show_bad_msg = '1' then win <= '0'; lose <= '1'; else win <= '1'; lose <= '0'; end if; game <= '1'; if ky = '1' then game_status <= WAIT_START; elsif kn = '1' then game_status <= RST; else null; end if; when RST => cntg <= '0'; game <= '0'; win <= '0'; lose <= '0'; show_field <= '0'; display_text <= '0'; show_bad_msg <= '0'; cnt_flash <= (others => '0'); addr_rnd <= (others => '0'); when others => null; end case; end if; end process; pr_display8x8: process(clk, reset) is begin if reset = '0' then show_disp <= (others=>(others=>'0')); cnt_mines <= (others => '0'); show_dispz <= (others => '0'); elsif rising_edge(clk) then case game_status is when PLAY => if kenter = '1' then show_disp(conv_integer(cnt_xx))(conv_integer(cnt_yy)) <= '1'; else null; end if; -- x_loop: for ii in 0 to 62 loop -- show_dispz(ii+1) <= show_dispz(ii); -- end loop; -- show_dispz(0) <= '0'; show_dispz(63 downto 0) <= show_dispz(62 downto 0) & '0'; if show_dispz(63) = '1' then cnt_mines <= cnt_mines + '1'; else null; end if; when CHECK => show_dispz <= conv8x8to64(show_disp); cnt_mines <= (others => '0'); when RST | GAME_OVER | WAIT_START => show_dispz <= (others => '0'); show_disp <= (others=>(others=>'0')); cnt_mines <= (others => '0'); when others => null; end case; end if; end process; ---------------- COMPONENTS MAPPING ---------------- x_check: cl_check generic map( yend => yend, ystart => ystart, xend => xend, xstart => xstart ) port map( clk => clk, reset => reset, cnt_yy => cnt_yy, cnt_xx => cnt_xx, display => show_field, x_char => x_char, y_char => y_char, rgb => rgb1 ); x_mines: cl_mines generic map( yend => yend, ystart => ystart, xend => xend, xstart => xstart ) port map( clk => clk, reset => reset, addr_rnd => addr_rnd, show_disp => show_disp, display => show_field, x_char => x_char, y_char => y_char, data_out => data_box, rgb => rgb2 ); x_square: cl_square generic map( yend => yend, ystart => ystart, xend => xend, xstart => xstart ) port map( clk => clk, reset => reset, show_disp => show_disp, display => show_field, x_char => x_char, y_char => y_char, rgb => rgb3 ); x_borders: cl_borders generic map( yend => yend, ystart => ystart, xend => xend, xstart => xstart ) port map( clk => clk, reset => reset, display => show_field, x_char => x_char, y_char => y_char, rgb => rgb4 ); x_text: cl_text generic map( yend => yend, ystart => ystart, xend => xend, xstart => xstart ) port map( clk => clk, reset => reset, addr_rnd => addr_rnd, display => display_text, cntgames => cntg, win => win, lose => lose, game => game, flash => cnt_flash(23 downto 21), x_char => x_char, y_char => y_char, rgb => rgb5 ); end ctrl_game_block;

-- ------------------------------------------------------------- -- -- Generated Architecture Declaration for rtl of inst_a_e -- -- Generated -- by: wig -- on: Wed Jul 19 05:28:20 2006 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../logic.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_a_e-rtl-a.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $ -- $Date: 2006/07/19 07:35:16 $ -- $Log: inst_a_e-rtl-a.vhd,v $ -- Revision 1.4 2006/07/19 07:35:16 wig -- Updated testcases. -- -- -- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp -- -- Generator: mix_0.pl Revision: 1.46 , [email protected] -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/arch -- -- -- Start of Generated Architecture rtl of inst_a_e -- architecture rtl of inst_a_e is -- -- Generated Constant Declarations -- -- -- Generated Components -- --__I_SIMPLE_LOGIC__ inst_a_and --__I_SIMPLE_LOGIC__ inst_a_or --__I_SIMPLE_LOGIC__ inst_a_wire component inst_aa_e -- the aa instance -- No Generated Generics port ( -- Generated Port for Entity inst_aa_e and_i1_1 : out std_ulogic; and_i2_1 : out std_ulogic_vector(15 downto 0); or_i1_1 : out std_ulogic; or_i2_1 : out std_ulogic_vector(15 downto 0) -- End of Generated Port for Entity inst_aa_e ); end component; -- --------- component inst_ab_e -- the ab instance -- No Generated Generics port ( -- Generated Port for Entity inst_ab_e and_i1_2 : out std_ulogic; and_i1_3_p : out std_ulogic; and_i2_2 : out std_ulogic_vector(15 downto 0); and_i2_3_p : out std_ulogic_vector(15 downto 0); or_i1_2 : out std_ulogic; or_i1_3_p : out std_ulogic; or_i2_2 : out std_ulogic_vector(15 downto 0); or_i2_3_p : out std_ulogic_vector(15 downto 0) -- End of Generated Port for Entity inst_ab_e ); end component; -- --------- -- -- Generated Signal List -- signal and_i1_1 : std_ulogic; signal and_i1_2 : std_ulogic; signal and_i1_3 : std_ulogic; signal and_i2_1 : std_ulogic_vector(15 downto 0); signal and_i2_2 : std_ulogic_vector(15 downto 0); signal and_i3_3 : std_ulogic_vector(15 downto 0); signal or_i1_1 : std_ulogic; signal or_i1_2 : std_ulogic; signal or_i1_3 : std_ulogic; signal or_i2_1 : std_ulogic_vector(15 downto 0); signal or_i2_2 : std_ulogic_vector(15 downto 0); signal or_i3_3 : std_ulogic_vector(15 downto 0); signal wire_bus_si : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ signal wire_bus_so : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ signal wire_si : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ signal wire_so : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ -- -- End of Generated Signal List -- begin -- -- Generated Concurrent Statements -- -- -- Generated Signal Assignments -- wire_bus_si <= wire_bus_i; -- __I_I_BUS_PORT wire_bus_o <= wire_bus_so; -- __I_O_BUS_PORT wire_si <= wire_i; -- __I_I_BIT_PORT wire_o <= wire_so; -- __I_O_BIT_PORT -- -- Generated Instances and Port Mappings -- -- Generated Logic for inst_a_and and_o1 <= and_i1_2 AND and_i1_1 AND and_i1_3; -- End of Generated Logic for inst_a_and -- Generated Logic for inst_a_and_1 and_o2 <= and_i2_2 AND and_i2_1 AND and_i3_3; -- End of Generated Logic for inst_a_and_1 -- Generated Logic for inst_a_or or_o1 <= or_i1_2 OR or_i1_3 OR or_i1_1; -- End of Generated Logic for inst_a_or -- Generated Logic for inst_a_or_1 or_o2 <= or_i2_2 OR or_i2_1 OR or_i3_3; -- End of Generated Logic for inst_a_or_1 -- Generated Logic for inst_a_wire wire_so <= wire_si; -- End of Generated Logic for inst_a_wire -- Generated Logic for inst_a_wire_1 wire_bus_so <= wire_bus_si; -- End of Generated Logic for inst_a_wire_1 -- Generated Instance Port Map for inst_aa_i inst_aa_i: inst_aa_e -- the aa instance port map ( and_i1_1 => and_i1_1, and_i2_1 => and_i2_1, or_i1_1 => or_i1_1, or_i2_1 => or_i2_1 ); -- End of Generated Instance Port Map for inst_aa_i -- Generated Instance Port Map for inst_ab_i inst_ab_i: inst_ab_e -- the ab instance port map ( and_i1_2 => and_i1_2, and_i1_3_p => and_i1_3, and_i2_2 => and_i2_2, and_i2_3_p => and_i3_3, or_i1_2 => or_i1_2, or_i1_3_p => or_i1_3, or_i2_2 => or_i2_2, or_i2_3_p => or_i3_3 ); -- End of Generated Instance Port Map for inst_ab_i end rtl; -- --!End of Architecture/s -- --------------------------------------------------------------

-- -- my_fpga_test_gates.vhdl -- library ieee; use ieee.std_logic_1164.all; use work.tbmsgs.all; entity my_fpga_test_gates is end entity; architecture sim of my_fpga_test_gates is signal clk : std_logic := '0'; signal n_rst : std_logic := '0'; signal up : std_logic := '0'; signal dn : std_logic := '0'; signal cnt : std_logic_vector(31 downto 0); signal cnt_1k : std_logic_vector(3 downto 0); signal in1 : std_logic := '0'; signal in2 : std_logic := '0'; signal out1 : std_logic; signal out2 : std_logic; begin uut : entity work.my_fpga port map ( clk => clk, n_rst => n_rst, up => up, dn => dn, cnt => cnt, cnt_1k => cnt_1k, in1 => in1, in2 => in2, out1 => out1, out2 => out2 ); test : process begin testcase("my_fpga gates", 4); wait for 1 us; check(out1 = '0', "out1 should be '0'"); check(out2 = '0', "out2 should be '0'"); tested("inputs set to 00"); in1 <= '1'; wait for 1 us; check(out1 = '1', "out1 should be '1'"); check(out2 = '0', "out2 should be '0'"); tested("inputs set to 01"); in2 <= '1'; wait for 1 us; check(out1 = '1', "out1 should be '1'"); check(out2 = '1', "out2 should be '1'"); tested("inputs set to 11"); in1 <= '0'; wait for 1 us; check(out1 = '1', "out1 should be '1'"); check(out2 = '0', "out2 should be '0'"); tested("inputs set to 10"); testcase_complete; wait; end process; end;

library IEEE; use IEEE.std_logic_1164.all; entity compara_zero_8bits is generic (N: integer := 10); port ( in_0,in_1: in std_logic_vector((N - 1) downto 0); out_0: out std_logic ); end entity; architecture circuito of compara_zero_8bits is begin compara_zero_8bits <= ( (in_0(0) xnor in_1(0)) and (in_0(1) xnor in_1(1)) and (in_0(2) xnor in_1(2)) and (in_0(3) xnor in_1(3)) and (in_0(4) xnor in_1(4)) and (in_0(5) xnor in_1(5)) and (in_0(6) xnor in_1(6)) and (in_0(7) xnor in_1(7)) ); end architecture;

----------------------------------------------------------------------------- --! @file --! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved. --! @author Sergey Khabarov --! @brief Network on Chip design top level. --! @details RISC-V "Rocket Core" based system with the AMBA AXI4 (NASTI) --! system bus and integrated peripheries. ------------------------------------------------------------------------------ --! Standard library library IEEE; use IEEE.STD_LOGIC_1164.ALL; --! Data transformation and math functions library library commonlib; use commonlib.types_common.all; --! Technology definition library. library techmap; --! Technology constants definition. use techmap.gencomp.all; --! "Virtual" PLL declaration. use techmap.types_pll.all; --! "Virtual" buffers declaration. use techmap.types_buf.all; --! AMBA system bus specific library library ambalib; --! AXI4 configuration constants. use ambalib.types_amba4.all; --! Rocket-chip specific library library rocketlib; --! SOC top-level component declaration. use rocketlib.types_rocket.all; --! Ethernet related declarations. use rocketlib.grethpkg.all; --! GNSS Sensor Ltd proprietary library library gnsslib; use gnsslib.types_gnss.all; --! Top-level implementaion library library work; --! Target dependable configuration: RTL, FPGA or ASIC. use work.config_target.all; --! Target independable configuration. use work.config_common.all; --! @brief SOC Top-level entity declaration. --! @details This module implements full SOC functionality and all IO signals --! are available on FPGA/ASIC IO pins. entity rocket_soc is port ( --! Input reset. Active High. Usually assigned to button "Center". i_rst : in std_logic; --! @name Clocks: --! @{ --! Differential clock (LVDS) positive signal. i_sclk_p : in std_logic; --! Differential clock (LVDS) negative signal. i_sclk_n : in std_logic; --! External ADC clock (default 26 MHz). i_clk_adc : in std_logic; --! @} --! @name User's IOs: --! @{ --! DIP switch. i_int_clkrf : in std_logic; i_dip : in std_logic_vector(3 downto 1); --! LEDs. o_led : out std_logic_vector(7 downto 0); --! @} --! @name UART1 signals: --! @{ i_uart1_ctsn : in std_logic; i_uart1_rd : in std_logic; o_uart1_td : out std_logic; o_uart1_rtsn : out std_logic; --! @} --! @name ADC channel A inputs (1575.4 GHz): --! @{ i_gps_I : in std_logic_vector(1 downto 0); i_gps_Q : in std_logic_vector(1 downto 0); --! @} --! @name ADC channel B inputs (1602 GHz): --! @{ i_glo_I : in std_logic_vector(1 downto 0); i_glo_Q : in std_logic_vector(1 downto 0); --! @} --! @name MAX2769 SPIs and antenna controls signals: --! @{ i_gps_ld : in std_logic; i_glo_ld : in std_logic; o_max_sclk : out std_logic; o_max_sdata : out std_logic; o_max_ncs : out std_logic_vector(1 downto 0); i_antext_stat : in std_logic; i_antext_detect : in std_logic; o_antext_ena : out std_logic; o_antint_contr : out std_logic; --! @} --! Ethernet MAC PHY interface signals --! @{ i_gmiiclk_p : in std_ulogic; i_gmiiclk_n : in std_ulogic; o_egtx_clk : out std_ulogic; i_etx_clk : in std_ulogic; i_erx_clk : in std_ulogic; i_erxd : in std_logic_vector(3 downto 0); i_erx_dv : in std_ulogic; i_erx_er : in std_ulogic; i_erx_col : in std_ulogic; i_erx_crs : in std_ulogic; i_emdint : in std_ulogic; o_etxd : out std_logic_vector(3 downto 0); o_etx_en : out std_ulogic; o_etx_er : out std_ulogic; o_emdc : out std_ulogic; io_emdio : inout std_logic; o_erstn : out std_ulogic ); --! @} end rocket_soc; --! @brief SOC top-level architecture declaration. architecture arch_rocket_soc of rocket_soc is --! @name Buffered in/out signals. --! @details All signals that are connected with in/out pads must be passed --! through the dedicated buffere modules. For FPGA they are implemented --! as an empty devices but ASIC couldn't be made without buffering. --! @{ signal ib_rst : std_logic; signal ib_sclk_p : std_logic; signal ib_sclk_n : std_logic; signal ib_clk_adc : std_logic; signal ib_dip : std_logic_vector(3 downto 0); signal ib_gmiiclk : std_logic; --! @} signal wSysReset : std_ulogic; -- Internal system reset. MUST NOT USED BY DEVICES. signal wReset : std_ulogic; -- Global reset active HIGH signal wNReset : std_ulogic; -- Global reset active LOW signal soft_rst : std_logic; -- reset from exteranl debugger signal bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW signal wClkBus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6) signal wClkAdc : std_ulogic; -- 26 MHz from the internal PLL signal wPllLocked : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked. signal uart1i : uart_in_type; signal uart1o : uart_out_type; --! Arbiter is switching only slaves output signal, data from noc --! is connected to all slaves and to the arbiter itself. signal aximi : nasti_master_in_type; signal aximo : nasti_master_out_type; signal axisi : nasti_slave_in_type; signal axiso : nasti_slave_out_type; signal slv_cfg : nasti_slave_cfg_vector; signal mst_cfg : nasti_master_cfg_vector; signal eth_i : eth_in_type; signal eth_o : eth_out_type; signal irq_pins : std_logic_vector(CFG_IRQ_TOTAL-1 downto 0); begin --! PAD buffers: irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst); iclkp0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_p, i_sclk_p); iclkn0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_sclk_n, i_sclk_n); iclk1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_clk_adc, i_clk_adc); idip0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(0), i_int_clkrf); dipx : for i in 1 to 3 generate idipz : ibuf_tech generic map(CFG_PADTECH) port map (ib_dip(i), i_dip(i)); end generate; igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map ( i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk); --! @todo all other in/out signals via buffers: ------------------------------------ -- @brief Internal PLL device instance. pll0 : SysPLL_tech generic map ( tech => CFG_FABTECH, tmode_always_ena => CFG_TESTMODE_ON ) port map ( i_reset => ib_rst, i_int_clkrf => ib_dip(0), i_clkp => ib_sclk_p, i_clkn => ib_sclk_n, i_clk_adc => ib_clk_adc, o_clk_bus => wClkBus, o_clk_adc => wClkAdc, o_locked => wPllLocked ); wSysReset <= ib_rst or not wPllLocked; ------------------------------------ --! @brief System Reset device instance. rst0 : reset_global port map ( inSysReset => wSysReset, inSysClk => wClkBus, inPllLock => wPllLocked, outReset => wReset ); wNReset <= not wReset; bus_nrst <= not (wReset or soft_rst); aximi.grant <= "1"; aximi.aw_ready <= axiso.aw_ready; aximi.w_ready <= axiso.w_ready; aximi.b_valid <= axiso.b_valid; aximi.b_resp <= axiso.b_resp; aximi.b_id <= axiso.b_id; aximi.b_user <= axiso.b_user; aximi.ar_ready <= axiso.ar_ready; aximi.r_valid <= axiso.r_valid; aximi.r_resp <= axiso.r_resp; aximi.r_data <= axiso.r_data; aximi.r_last <= axiso.r_last; aximi.r_id <= axiso.r_id; aximi.r_user <= axiso.r_user; axisi.aw_valid <= aximo.aw_valid; axisi.aw_bits <= aximo.aw_bits; axisi.aw_id <= aximo.aw_id; axisi.aw_user <= aximo.aw_user; axisi.w_valid <= aximo.w_valid; axisi.w_data <= aximo.w_data; axisi.w_last <= aximo.w_last; axisi.w_strb <= aximo.w_strb; axisi.w_user <= aximo.w_user; axisi.b_ready <= aximo.b_ready; axisi.ar_valid <= aximo.ar_valid; axisi.ar_bits <= aximo.ar_bits; axisi.ar_id <= aximo.ar_id; axisi.ar_user <= aximo.ar_user; axisi.r_ready <= aximo.r_ready; ------------------------------------ --! @brief Controller of the LEDs, DIPs and GPIO with the AXI4 interface. --! @details Map address: --! 0x80000000..0x80000fff (4 KB total) gpio0 : nasti_gpio generic map ( xindex => CFG_NASTI_SLAVE_GPIO, xaddr => 16#80000#, xmask => 16#fffff# ) port map ( clk => wClkBus, nrst => wNReset, cfg => slv_cfg(CFG_NASTI_SLAVE_GPIO), i => axisi, o => axiso, i_dip => ib_dip, o_led => o_led ); --! Gigabit clock phase rotator with buffers clkrot90 : clkp90_tech generic map ( tech => CFG_FABTECH, freq => 125000 -- KHz = 125 MHz ) port map ( i_rst => wReset, i_clk => ib_gmiiclk, o_clk => eth_i.gtx_clk, o_clkp90 => eth_i.tx_clk_90, o_clk2x => open, -- used in gbe 'io_ref' o_lock => open ); --! @brief Ethernet MAC with the AXI4 interface. --! @details Map address: --! 0x80040000..0x8007ffff (256 KB total) --! EDCL IP: 192.168.0.51 = C0.A8.00.33 eth_i.tx_clk <= i_etx_clk; eth_i.rx_clk <= i_erx_clk; eth_i.rxd <= i_erxd; eth_i.rx_dv <= i_erx_dv; eth_i.rx_er <= i_erx_er; eth_i.rx_col <= i_erx_col; eth_i.rx_crs <= i_erx_crs; eth_i.mdint <= i_emdint; mac0 : grethaxi generic map ( xslvindex => CFG_NASTI_SLAVE_ETHMAC, xmstindex => CFG_NASTI_MASTER_ETHMAC, xaddr => 16#80040#, xmask => 16#FFFC0#, xirq => CFG_IRQ_ETHMAC, memtech => CFG_MEMTECH, mdcscaler => 60, --! System Bus clock in MHz enable_mdio => 1, fifosize => 16, nsync => 1, edcl => 1, edclbufsz => 16, macaddrh => 16#20789#, macaddrl => 16#123#, ipaddrh => 16#C0A8#, ipaddrl => 16#0033#, phyrstadr => 7, enable_mdint => 1, maxsize => 1518 ) port map ( rst => wNReset, clk => wClkBus, msti => aximi, msto => aximo, mstcfg => mst_cfg(CFG_NASTI_MASTER_ETHMAC), msto2 => open, -- EDCL separate access is disabled mstcfg2 => open, -- EDCL separate access is disabled slvi => axisi, slvo => open, slvcfg => slv_cfg(CFG_NASTI_SLAVE_ETHMAC), ethi => eth_i, etho => eth_o, irq => irq_pins(CFG_IRQ_ETHMAC) ); emdio_pad : iobuf_tech generic map( CFG_PADTECH ) port map ( o => eth_i.mdio_i, io => io_emdio, i => eth_o.mdio_o, t => eth_o.mdio_oe ); o_egtx_clk <= eth_i.gtx_clk;--eth_i.tx_clk_90; o_etxd <= eth_o.txd; o_etx_en <= eth_o.tx_en; o_etx_er <= eth_o.tx_er; o_emdc <= eth_o.mdc; o_erstn <= wNReset; end arch_rocket_soc;

LIBRARY IEEE; USE IEEE.std_logic_1164.all; PACKAGE RS232_test IS ------------------------------------------------------------------------------- -- Procedure for sending one byte over the RS232 serial input ------------------------------------------------------------------------------- procedure Transmit ( signal TX : out std_logic; -- serial line constant DATA : in std_logic_vector(7 downto 0)); -- byte to be sent ------------------------------------------------------------------------------- -- Procedure for receiving one byte from the RS232 serial output ------------------------------------------------------------------------------- procedure Receive ( signal RX : in std_logic; -- serial line signal DATA : out std_logic_vector(7 downto 0)); -- byte to be received END RS232_test; PACKAGE BODY RS232_test IS ----------------------------------------------------------------------------- -- Procedure for sending one byte over the RS232 serial input ----------------------------------------------------------------------------- procedure Transmit ( signal TX : out std_logic; -- serial output constant DATA : in std_logic_vector(7 downto 0)) is begin TX <= '0'; wait for 8680.6 ns; -- about to send byte for i in 0 to 7 loop TX <= DATA(i); wait for 8680.6 ns; end loop; -- i TX <= '1'; wait for 8680.6 ns; TX <= '1'; end Transmit; ------------------------------------------------------------------------------- -- Procedure for receiving one byte from the RS232 serial output ------------------------------------------------------------------------------- procedure Receive ( signal RX : in std_logic; -- serial line signal DATA : out std_logic_vector(7 downto 0)) is variable tmp : std_logic_vector(7 downto 0); begin while TRUE loop wait until RX='0'; wait for 13021 ns; for i in 0 to 7 loop tmp(i) := RX; wait for 8680.6 ns; end loop; --wait for 4340.3 ns; DATA <= tmp; end loop; end Receive; END RS232_test;

------------------------------------------------------------------------------- -- Title : Dynamic adder/subtractor -- Project : ------------------------------------------------------------------------------- -- File : addsub.vhd -- Author : Aylons <[email protected]> -- Company : -- Created : 2014-05-03 -- Last update: 2015-10-15 -- Platform : -- Standard : VHDL'93/02/08 ------------------------------------------------------------------------------- -- Description: Depening on sub_i, result_o may be a_i + b_i or a_i - b_i. -- The three widths must all be the same. ------------------------------------------------------------------------------- -- This file is part of Concordic. -- -- Concordic is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- Concordic is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with Foobar. If not, see <http://www.gnu.org/licenses/>. -- Copyright (c) 2014 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2014-05-03 1.0 aylons Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- entity addsub is port ( a_i : in signed; b_i : in signed; sub_i : in boolean; clk_i : in std_logic; ce_i : in std_logic; rst_i : in std_logic; result_o : out signed; positive_o : out boolean; negative_o : out boolean ); end entity addsub; ------------------------------------------------------------------------------- architecture str of addsub is constant width : natural := a_i'length; signal a_1, b_1 : signed(width-1 downto 0) := (others => '0'); signal mux_result : signed (width-1 downto 0) := (others => '0'); begin -- architecture str assert a_i'length = b_i'length report "a_i and b_i have different widths" severity error; assert a_i'length = result_o'length report "invalid result_o width" severity error; process(clk_i) is variable result : signed(width-1 downto 0) := (others => '0'); begin if rising_edge(clk_i) then if rst_i = '1' then result_o <= (width-1 downto 0 => '0'); positive_o <= true; negative_o <= false; else if ce_i = '1' then result := mux_result; positive_o <= result(result'left) = '0'; negative_o <= result(result'left) = '1'; result_o <= result; end if; end if; end if; end process; mux_result <= a_i + b_i when (not sub_i) else a_i - b_i; end architecture str; -------------------------------------------------------------------------------

-- -- USB Full-Speed/Hi-Speed Device Controller core - ep1_loopback.vhdl -- -- Copyright (c) 2015 Konstantin Oblaukhov -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; library work; use work.USBCore.all; use work.USBExtra.all; entity ep1_loopback is port ( led : out std_logic; ulpi_data : inout std_logic_vector(7 downto 0); ulpi_dir : in std_logic; ulpi_nxt : in std_logic; ulpi_stp : out std_logic; ulpi_reset : out std_logic; ulpi_clk60 : in std_logic; main_clk : in std_logic ); end ep1_loopback; architecture ep1_loopback of ep1_loopback is constant USE_HIGH_SPEED: boolean := true; constant CONFIG_DESC : BYTE_ARRAY(0 to 8) := ( X"09", -- bLength = 9 X"02", -- bDescriptionType = Configuration Descriptor X"20", X"00", -- wTotalLength = 32 X"01", -- bNumInterfaces = 1 X"01", -- bConfigurationValue X"00", -- iConfiguration X"C0", -- bmAttributes = Self-powered X"32" -- bMaxPower = 100 mA ); constant INTERFACE_DESC : BYTE_ARRAY(0 to 8) := ( X"09", -- bLength = 9 X"04", -- bDescriptorType = Interface Descriptor X"00", -- bInterfaceNumber = 0 X"00", -- bAlternateSetting X"02", -- bNumEndpoints = 2 X"00", -- bInterfaceClass X"00", -- bInterfaceSubClass X"00", -- bInterfaceProtocol X"00" -- iInterface ); constant EP1_IN_DESC : BYTE_ARRAY(0 to 6) := ( X"07", -- bLength = 7 X"05", -- bDescriptorType = Endpoint Descriptor X"81", -- bEndpointAddress = IN1 B"00_00_00_10", -- bmAttributes = Bulk X"00", X"02", -- wMaxPacketSize = 512 bytes X"00" -- bInterval ); constant EP1_OUT_DESC : BYTE_ARRAY(0 to 6) := ( X"07", -- bLength = 7 X"05", -- bDescriptorType = Endpoint Descriptor X"01", -- bEndpointAddress = OUT1 B"00_00_00_10", -- bmAttributes = Bulk X"00", X"02", -- wMaxPacketSize = 512 bytes X"00" -- bInterval ); signal ulpi_data_in : std_logic_vector(7 downto 0); signal ulpi_data_out : std_logic_vector(7 downto 0); signal usb_clk : std_logic; signal usb_reset : std_logic; signal usb_idle : std_logic; signal usb_suspend : std_logic; signal usb_configured : std_logic; signal usb_crc_error : std_logic; signal usb_sof : std_logic; signal ctl_xfer_endpoint : std_logic_vector(3 downto 0); signal ctl_xfer_type : std_logic_vector(7 downto 0); signal ctl_xfer_request : std_logic_vector(7 downto 0); signal ctl_xfer_value : std_logic_vector(15 downto 0); signal ctl_xfer_index : std_logic_vector(15 downto 0); signal ctl_xfer_length : std_logic_vector(15 downto 0); signal ctl_xfer_accept : std_logic; signal ctl_xfer : std_logic; signal ctl_xfer_done : std_logic; signal ctl_xfer_data_out : std_logic_vector(7 downto 0); signal ctl_xfer_data_out_valid: std_logic; signal ctl_xfer_data_in : std_logic_vector(7 downto 0); signal ctl_xfer_data_in_valid : std_logic; signal ctl_xfer_data_in_last : std_logic; signal ctl_xfer_data_in_ready : std_logic; signal blk_xfer_endpoint : std_logic_vector(3 downto 0); signal blk_in_xfer : std_logic; signal blk_out_xfer : std_logic; signal blk_xfer_in_has_data : std_logic; signal blk_xfer_in_data : std_logic_vector(7 downto 0); signal blk_xfer_in_data_valid : std_logic; signal blk_xfer_in_data_ready : std_logic; signal blk_xfer_in_data_last : std_logic; signal blk_xfer_out_ready_read: std_logic; signal blk_xfer_out_data : std_logic_vector(7 downto 0); signal blk_xfer_out_data_valid: std_logic; signal ep1_in_axis_tdata : std_logic_vector(7 downto 0); signal ep1_in_axis_tvalid : std_logic; signal ep1_in_axis_tready : std_logic; signal ep1_in_axis_tlast : std_logic; signal ep1_out_axis_tdata : std_logic_vector(7 downto 0); signal ep1_out_axis_tvalid : std_logic; signal ep1_out_axis_tready : std_logic; signal ep1_out_axis_tlast : std_logic; signal led_counter : std_logic_vector(25 downto 0); signal ulpi_stp_int : std_logic; begin ULPI_IO: for i in 7 downto 0 generate begin ULPI_IOBUF : IOBUF port map ( O => ulpi_data_in(i), IO => ulpi_data(i), I => ulpi_data_out(i), T => ulpi_dir ); end generate; USB_CONTROLLER: usb_tlp generic map ( VENDOR_ID => X"DEAD", PRODUCT_ID => X"BEEF", MANUFACTURER => "USBCore", PRODUCT => "Endpoint 1 Loopback Device", SERIAL => "", CONFIG_DESC => CONFIG_DESC & INTERFACE_DESC & EP1_IN_DESC & EP1_OUT_DESC, HIGH_SPEED => USE_HIGH_SPEED ) port map ( ulpi_data_in => ulpi_data_in, ulpi_data_out => ulpi_data_out, ulpi_dir => ulpi_dir, ulpi_nxt => ulpi_nxt, ulpi_stp => ulpi_stp, ulpi_reset => ulpi_reset, ulpi_clk60 => ulpi_clk60, usb_clk => usb_clk, usb_reset => usb_reset, usb_idle => usb_idle, usb_suspend => usb_suspend, usb_configured => usb_configured, usb_crc_error => usb_crc_error, usb_sof => usb_sof, ctl_xfer_endpoint => ctl_xfer_endpoint, ctl_xfer_type => ctl_xfer_type, ctl_xfer_request => ctl_xfer_request, ctl_xfer_value => ctl_xfer_value, ctl_xfer_index => ctl_xfer_index, ctl_xfer_length => ctl_xfer_length, ctl_xfer_accept => ctl_xfer_accept, ctl_xfer => ctl_xfer, ctl_xfer_done => ctl_xfer_done, ctl_xfer_data_out => ctl_xfer_data_out, ctl_xfer_data_out_valid => ctl_xfer_data_out_valid, ctl_xfer_data_in => ctl_xfer_data_in, ctl_xfer_data_in_valid => ctl_xfer_data_in_valid, ctl_xfer_data_in_last => ctl_xfer_data_in_last, ctl_xfer_data_in_ready => ctl_xfer_data_in_ready, blk_xfer_endpoint => blk_xfer_endpoint, blk_in_xfer => blk_in_xfer, blk_out_xfer => blk_out_xfer, blk_xfer_in_has_data => blk_xfer_in_has_data, blk_xfer_in_data => blk_xfer_in_data, blk_xfer_in_data_valid => blk_xfer_in_data_valid, blk_xfer_in_data_ready => blk_xfer_in_data_ready, blk_xfer_in_data_last => blk_xfer_in_data_last, blk_xfer_out_ready_read => blk_xfer_out_ready_read, blk_xfer_out_data => blk_xfer_out_data, blk_xfer_out_data_valid => blk_xfer_out_data_valid ); EP1_IN_CTL: blk_ep_in_ctl generic map ( USE_ASYNC_FIFO => true ) port map ( rst => usb_reset, usb_clk => usb_clk, axis_clk => main_clk, blk_in_xfer => blk_in_xfer, blk_xfer_in_has_data => blk_xfer_in_has_data, blk_xfer_in_data => blk_xfer_in_data, blk_xfer_in_data_valid => blk_xfer_in_data_valid, blk_xfer_in_data_ready => blk_xfer_in_data_ready, blk_xfer_in_data_last => blk_xfer_in_data_last, axis_tdata => ep1_in_axis_tdata, axis_tvalid => ep1_in_axis_tvalid, axis_tready => ep1_in_axis_tready, axis_tlast => ep1_in_axis_tlast ); EP1_OUT_CTL: blk_ep_out_ctl generic map ( USE_ASYNC_FIFO => true ) port map ( rst => usb_reset, usb_clk => usb_clk, axis_clk => main_clk, blk_out_xfer => blk_out_xfer, blk_xfer_out_ready_read => blk_xfer_out_ready_read, blk_xfer_out_data => blk_xfer_out_data, blk_xfer_out_data_valid => blk_xfer_out_data_valid, axis_tdata => ep1_out_axis_tdata, axis_tvalid => ep1_out_axis_tvalid, axis_tready => ep1_out_axis_tready, axis_tlast => ep1_out_axis_tlast ); ep1_in_axis_tdata <= ep1_out_axis_tdata; ep1_in_axis_tvalid <= ep1_out_axis_tvalid; ep1_out_axis_tready <= ep1_in_axis_tready; ep1_in_axis_tlast <= ep1_out_axis_tlast; COUNT: process(usb_clk) is begin if rising_edge(usb_clk) then led_counter <= led_counter + 1; end if; end process; led <= '1' when usb_idle = '1' AND usb_configured = '1' else led_counter(led_counter'left) when usb_idle = '1' else '1' when led_counter(led_counter'left downto led_counter'left - 2) = "000" else '0'; end ep1_loopback;

------------------------------------------------------------------------------- -- Title : Testbench for design "2013_big_drive" ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2013 strongly-typed ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.bus_pkg.all; use work.spislave_pkg.all; use work.motor_control_pkg.all; use work.utils_pkg.all; use work.pwm_module_pkg.all; use work.motor_control_pkg.all; use work.encoder_module_pkg.all; use work.servo_module_pkg.all; use work.adc_ad7266_pkg.all; use work.reg_file_pkg.all; use work.utils_pkg.all; ------------------------------------------------------------------------------- entity toplevel_tb is end toplevel_tb; ------------------------------------------------------------------------------- architecture tb of toplevel_tb is component toplevel is port ( bldc0_driver_st_p : out bldc_driver_stage_st_type; bldc0_hall_p : in hall_sensor_type; bldc0_encoder_p : in encoder_type; encoder0_p : in encoder_type; bldc1_driver_st_p : out bldc_driver_stage_st_type; bldc1_hall_p : in hall_sensor_type; bldc1_encoder_p : in encoder_type; encoder1_p : in encoder_type; dc0_driver_st_p : out dc_driver_stage_st_type; dc1_driver_st_p : out dc_driver_stage_st_type; dc2_driver_st_p : out dc_driver_stage_st_type; servo_p : out std_logic_vector(3 downto 2); imotor_tx_p : out std_logic_vector(4 downto 0); imotor_rx_p : in std_logic_vector(4 downto 0); pump_p : out std_logic_vector(3 downto 0); valve_p : out std_logic_vector(3 downto 0); cs_np : in std_logic; sck_p : in std_logic; miso_p : out std_logic; mosi_p : in std_logic; adc_out_p : out adc_ad7266_spi_out_type; adc_in_p : in adc_ad7266_spi_in_type; load_p : in std_logic; clk : in std_logic); end component toplevel; -- signals for component ports signal bldc0_driver_st_p : bldc_driver_stage_st_type; signal bldc0_hall_p : hall_sensor_type; signal bldc0_encoder_p : encoder_type; signal encoder0_p : encoder_type; signal bldc1_driver_st_p : bldc_driver_stage_st_type; signal bldc1_hall_p : hall_sensor_type; signal bldc1_encoder_p : encoder_type; signal encoder1_p : encoder_type; signal dc0_driver_st_p : dc_driver_stage_st_type; signal dc1_driver_st_p : dc_driver_stage_st_type; signal dc2_driver_st_p : dc_driver_stage_st_type; signal servo_p : std_logic_vector(3 downto 2); signal imotor_tx_p : std_logic_vector(4 downto 0); signal imotor_rx_p : std_logic_vector(4 downto 0); signal pump_p : std_logic_vector(3 downto 0); signal valve_p : std_logic_vector(3 downto 0); signal adc_in_p : adc_ad7266_spi_in_type; signal adc_out_p : adc_ad7266_spi_out_type; signal cs_np : std_logic := '0'; signal sck_p : std_logic := '0'; signal miso_p : std_logic; signal mosi_p : std_logic := '0'; signal load_p : std_logic := '1'; signal clk : std_logic := '0'; begin -- tb toplevel_1 : entity work.toplevel port map ( bldc0_driver_st_p => bldc0_driver_st_p, bldc0_hall_p => bldc0_hall_p, bldc0_encoder_p => bldc0_encoder_p, encoder0_p => encoder0_p, bldc1_driver_st_p => bldc1_driver_st_p, bldc1_hall_p => bldc1_hall_p, bldc1_encoder_p => bldc1_encoder_p, encoder1_p => encoder1_p, dc0_driver_st_p => dc0_driver_st_p, dc1_driver_st_p => dc1_driver_st_p, dc2_driver_st_p => dc2_driver_st_p, servo_p => servo_p, imotor_rx_p => imotor_rx_p, imotor_tx_p => imotor_tx_p, adc_out_p => adc_out_p, adc_in_p => adc_in_p, cs_np => cs_np, sck_p => sck_p, miso_p => miso_p, mosi_p => mosi_p, load_p => load_p, clk => clk); -- clock generation Clk <= not Clk after 5.0 ns; process begin wait; end process; end tb;

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2015.4 -- Copyright (C) 2015 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity feedforward_AXILiteS_s_axi is generic ( C_S_AXI_ADDR_WIDTH : INTEGER := 5; C_S_AXI_DATA_WIDTH : INTEGER := 32); port ( -- axi4 lite slave signals ACLK :in STD_LOGIC; ARESET :in STD_LOGIC; ACLK_EN :in STD_LOGIC; AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0); AWVALID :in STD_LOGIC; AWREADY :out STD_LOGIC; WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0); WVALID :in STD_LOGIC; WREADY :out STD_LOGIC; BRESP :out STD_LOGIC_VECTOR(1 downto 0); BVALID :out STD_LOGIC; BREADY :in STD_LOGIC; ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0); ARVALID :in STD_LOGIC; ARREADY :out STD_LOGIC; RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0); RRESP :out STD_LOGIC_VECTOR(1 downto 0); RVALID :out STD_LOGIC; RREADY :in STD_LOGIC; interrupt :out STD_LOGIC; -- user signals ap_start :out STD_LOGIC; ap_done :in STD_LOGIC; ap_ready :in STD_LOGIC; ap_idle :in STD_LOGIC; ap_return :in STD_LOGIC_VECTOR(7 downto 0); P_mode_V :out STD_LOGIC_VECTOR(7 downto 0) ); end entity feedforward_AXILiteS_s_axi; -- ------------------------Address Info------------------- -- 0x00 : Control signals -- bit 0 - ap_start (Read/Write/COH) -- bit 1 - ap_done (Read/COR) -- bit 2 - ap_idle (Read) -- bit 3 - ap_ready (Read) -- bit 7 - auto_restart (Read/Write) -- others - reserved -- 0x04 : Global Interrupt Enable Register -- bit 0 - Global Interrupt Enable (Read/Write) -- others - reserved -- 0x08 : IP Interrupt Enable Register (Read/Write) -- bit 0 - Channel 0 (ap_done) -- bit 1 - Channel 1 (ap_ready) -- others - reserved -- 0x0c : IP Interrupt Status Register (Read/TOW) -- bit 0 - Channel 0 (ap_done) -- bit 1 - Channel 1 (ap_ready) -- others - reserved -- 0x10 : Data signal of ap_return -- bit 7~0 - ap_return[7:0] (Read) -- others - reserved -- 0x18 : Data signal of P_mode_V -- bit 7~0 - P_mode_V[7:0] (Read/Write) -- others - reserved -- 0x1c : reserved -- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) architecture behave of feedforward_AXILiteS_s_axi is type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states signal wstate, wnext, rstate, rnext: states; constant ADDR_AP_CTRL : INTEGER := 16#00#; constant ADDR_GIE : INTEGER := 16#04#; constant ADDR_IER : INTEGER := 16#08#; constant ADDR_ISR : INTEGER := 16#0c#; constant ADDR_AP_RETURN_0 : INTEGER := 16#10#; constant ADDR_P_MODE_V_DATA_0 : INTEGER := 16#18#; constant ADDR_P_MODE_V_CTRL : INTEGER := 16#1c#; constant ADDR_BITS : INTEGER := 5; signal waddr : UNSIGNED(ADDR_BITS-1 downto 0); signal wmask : UNSIGNED(31 downto 0); signal aw_hs : STD_LOGIC; signal w_hs : STD_LOGIC; signal rdata_data : UNSIGNED(31 downto 0); signal ar_hs : STD_LOGIC; signal raddr : UNSIGNED(ADDR_BITS-1 downto 0); signal AWREADY_t : STD_LOGIC; signal WREADY_t : STD_LOGIC; signal ARREADY_t : STD_LOGIC; signal RVALID_t : STD_LOGIC; -- internal registers signal int_ap_idle : STD_LOGIC; signal int_ap_ready : STD_LOGIC; signal int_ap_done : STD_LOGIC; signal int_ap_start : STD_LOGIC; signal int_auto_restart : STD_LOGIC; signal int_gie : STD_LOGIC; signal int_ier : UNSIGNED(1 downto 0); signal int_isr : UNSIGNED(1 downto 0); signal int_ap_return : UNSIGNED(7 downto 0); signal int_P_mode_V : UNSIGNED(7 downto 0); begin -- ----------------------- Instantiation------------------ -- ----------------------- AXI WRITE --------------------- AWREADY_t <= '1' when wstate = wridle else '0'; AWREADY <= AWREADY_t; WREADY_t <= '1' when wstate = wrdata else '0'; WREADY <= WREADY_t; BRESP <= "00"; -- OKAY BVALID <= '1' when wstate = wrresp else '0'; wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0)); aw_hs <= AWVALID and AWREADY_t; w_hs <= WVALID and WREADY_t; -- write FSM process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then wstate <= wridle; elsif (ACLK_EN = '1') then wstate <= wnext; end if; end if; end process; process (wstate, AWVALID, WVALID, BREADY) begin case (wstate) is when wridle => if (AWVALID = '1') then wnext <= wrdata; else wnext <= wridle; end if; when wrdata => if (WVALID = '1') then wnext <= wrresp; else wnext <= wrdata; end if; when wrresp => if (BREADY = '1') then wnext <= wridle; else wnext <= wrresp; end if; when others => wnext <= wridle; end case; end process; waddr_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (aw_hs = '1') then waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)); end if; end if; end process; -- ----------------------- AXI READ ---------------------- ARREADY_t <= '1' when (rstate = rdidle) else '0'; ARREADY <= ARREADY_t; RDATA <= STD_LOGIC_VECTOR(rdata_data); RRESP <= "00"; -- OKAY RVALID_t <= '1' when (rstate = rddata) else '0'; RVALID <= RVALID_t; ar_hs <= ARVALID and ARREADY_t; raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0)); -- read FSM process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then rstate <= rdidle; elsif (ACLK_EN = '1') then rstate <= rnext; end if; end if; end process; process (rstate, ARVALID, RREADY, RVALID_t) begin case (rstate) is when rdidle => if (ARVALID = '1') then rnext <= rddata; else rnext <= rdidle; end if; when rddata => if (RREADY = '1' and RVALID_t = '1') then rnext <= rdidle; else rnext <= rddata; end if; when others => rnext <= rdidle; end case; end process; rdata_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (ar_hs = '1') then case (TO_INTEGER(raddr)) is when ADDR_AP_CTRL => rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0'); when ADDR_GIE => rdata_data <= (0 => int_gie, others => '0'); when ADDR_IER => rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0'); when ADDR_ISR => rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0'); when ADDR_AP_RETURN_0 => rdata_data <= RESIZE(int_ap_return(7 downto 0), 32); when ADDR_P_MODE_V_DATA_0 => rdata_data <= RESIZE(int_P_mode_V(7 downto 0), 32); when others => rdata_data <= (others => '0'); end case; end if; end if; end process; -- ----------------------- Register logic ---------------- interrupt <= int_gie and (int_isr(0) or int_isr(1)); ap_start <= int_ap_start; int_ap_idle <= ap_idle; int_ap_ready <= ap_ready; P_mode_V <= STD_LOGIC_VECTOR(int_P_mode_V); process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_start <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then int_ap_start <= '1'; elsif (int_ap_ready = '1') then int_ap_start <= int_auto_restart; -- clear on handshake/auto restart end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_done <= '0'; elsif (ACLK_EN = '1') then if (ap_done = '1') then int_ap_done <= '1'; elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then int_ap_done <= '0'; -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_auto_restart <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then int_auto_restart <= WDATA(7); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_gie <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then int_gie <= WDATA(0); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ier <= "00"; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then int_ier <= UNSIGNED(WDATA(1 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr(0) <= '0'; elsif (ACLK_EN = '1') then if (int_ier(0) = '1' and ap_done = '1') then int_isr(0) <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr(1) <= '0'; elsif (ACLK_EN = '1') then if (int_ier(1) = '1' and ap_ready = '1') then int_isr(1) <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_return <= (others => '0'); elsif (ACLK_EN = '1') then if (ap_done = '1') then int_ap_return <= UNSIGNED(ap_return); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_P_MODE_V_DATA_0) then int_P_mode_V(7 downto 0) <= (UNSIGNED(WDATA(7 downto 0)) and wmask(7 downto 0)) or ((not wmask(7 downto 0)) and int_P_mode_V(7 downto 0)); end if; end if; end if; end process; -- ----------------------- Memory logic ------------------ end architecture behave;

entity subent is port ( a : in string(1 to 2) := "AB"; b : out string(1 to 2)); end entity subent; architecture test of subent is begin b(1) <= a(1); b(2) <= a(2); end architecture test; entity test is end entity test; architecture test of test is signal b : string(1 to 2); begin e1: entity work.subent port map ( a => open, b(1) => b(1), b(2) => open -- it's not legal to have a mix of OPEN and non-open ); end architecture test;

-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Mon Sep 16 04:56:50 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_sim_netlist.vhdl -- Design : design_1_processing_system7_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is port ( CAN0_PHY_TX : out STD_LOGIC; CAN0_PHY_RX : in STD_LOGIC; CAN1_PHY_TX : out STD_LOGIC; CAN1_PHY_RX : in STD_LOGIC; ENET0_GMII_TX_EN : out STD_LOGIC; ENET0_GMII_TX_ER : out STD_LOGIC; ENET0_MDIO_MDC : out STD_LOGIC; ENET0_MDIO_O : out STD_LOGIC; ENET0_MDIO_T : out STD_LOGIC; ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET0_SOF_RX : out STD_LOGIC; ENET0_SOF_TX : out STD_LOGIC; ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET0_GMII_COL : in STD_LOGIC; ENET0_GMII_CRS : in STD_LOGIC; ENET0_GMII_RX_CLK : in STD_LOGIC; ENET0_GMII_RX_DV : in STD_LOGIC; ENET0_GMII_RX_ER : in STD_LOGIC; ENET0_GMII_TX_CLK : in STD_LOGIC; ENET0_MDIO_I : in STD_LOGIC; ENET0_EXT_INTIN : in STD_LOGIC; ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_TX_EN : out STD_LOGIC; ENET1_GMII_TX_ER : out STD_LOGIC; ENET1_MDIO_MDC : out STD_LOGIC; ENET1_MDIO_O : out STD_LOGIC; ENET1_MDIO_T : out STD_LOGIC; ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET1_SOF_RX : out STD_LOGIC; ENET1_SOF_TX : out STD_LOGIC; ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_COL : in STD_LOGIC; ENET1_GMII_CRS : in STD_LOGIC; ENET1_GMII_RX_CLK : in STD_LOGIC; ENET1_GMII_RX_DV : in STD_LOGIC; ENET1_GMII_RX_ER : in STD_LOGIC; ENET1_GMII_TX_CLK : in STD_LOGIC; ENET1_MDIO_I : in STD_LOGIC; ENET1_EXT_INTIN : in STD_LOGIC; ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 ); I2C0_SDA_I : in STD_LOGIC; I2C0_SDA_O : out STD_LOGIC; I2C0_SDA_T : out STD_LOGIC; I2C0_SCL_I : in STD_LOGIC; I2C0_SCL_O : out STD_LOGIC; I2C0_SCL_T : out STD_LOGIC; I2C1_SDA_I : in STD_LOGIC; I2C1_SDA_O : out STD_LOGIC; I2C1_SDA_T : out STD_LOGIC; I2C1_SCL_I : in STD_LOGIC; I2C1_SCL_O : out STD_LOGIC; I2C1_SCL_T : out STD_LOGIC; PJTAG_TCK : in STD_LOGIC; PJTAG_TMS : in STD_LOGIC; PJTAG_TDI : in STD_LOGIC; PJTAG_TDO : out STD_LOGIC; SDIO0_CLK : out STD_LOGIC; SDIO0_CLK_FB : in STD_LOGIC; SDIO0_CMD_O : out STD_LOGIC; SDIO0_CMD_I : in STD_LOGIC; SDIO0_CMD_T : out STD_LOGIC; SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_LED : out STD_LOGIC; SDIO0_CDN : in STD_LOGIC; SDIO0_WP : in STD_LOGIC; SDIO0_BUSPOW : out STD_LOGIC; SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SDIO1_CLK : out STD_LOGIC; SDIO1_CLK_FB : in STD_LOGIC; SDIO1_CMD_O : out STD_LOGIC; SDIO1_CMD_I : in STD_LOGIC; SDIO1_CMD_T : out STD_LOGIC; SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_LED : out STD_LOGIC; SDIO1_CDN : in STD_LOGIC; SDIO1_WP : in STD_LOGIC; SDIO1_BUSPOW : out STD_LOGIC; SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SPI0_SCLK_I : in STD_LOGIC; SPI0_SCLK_O : out STD_LOGIC; SPI0_SCLK_T : out STD_LOGIC; SPI0_MOSI_I : in STD_LOGIC; SPI0_MOSI_O : out STD_LOGIC; SPI0_MOSI_T : out STD_LOGIC; SPI0_MISO_I : in STD_LOGIC; SPI0_MISO_O : out STD_LOGIC; SPI0_MISO_T : out STD_LOGIC; SPI0_SS_I : in STD_LOGIC; SPI0_SS_O : out STD_LOGIC; SPI0_SS1_O : out STD_LOGIC; SPI0_SS2_O : out STD_LOGIC; SPI0_SS_T : out STD_LOGIC; SPI1_SCLK_I : in STD_LOGIC; SPI1_SCLK_O : out STD_LOGIC; SPI1_SCLK_T : out STD_LOGIC; SPI1_MOSI_I : in STD_LOGIC; SPI1_MOSI_O : out STD_LOGIC; SPI1_MOSI_T : out STD_LOGIC; SPI1_MISO_I : in STD_LOGIC; SPI1_MISO_O : out STD_LOGIC; SPI1_MISO_T : out STD_LOGIC; SPI1_SS_I : in STD_LOGIC; SPI1_SS_O : out STD_LOGIC; SPI1_SS1_O : out STD_LOGIC; SPI1_SS2_O : out STD_LOGIC; SPI1_SS_T : out STD_LOGIC; UART0_DTRN : out STD_LOGIC; UART0_RTSN : out STD_LOGIC; UART0_TX : out STD_LOGIC; UART0_CTSN : in STD_LOGIC; UART0_DCDN : in STD_LOGIC; UART0_DSRN : in STD_LOGIC; UART0_RIN : in STD_LOGIC; UART0_RX : in STD_LOGIC; UART1_DTRN : out STD_LOGIC; UART1_RTSN : out STD_LOGIC; UART1_TX : out STD_LOGIC; UART1_CTSN : in STD_LOGIC; UART1_DCDN : in STD_LOGIC; UART1_DSRN : in STD_LOGIC; UART1_RIN : in STD_LOGIC; UART1_RX : in STD_LOGIC; TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; TTC0_CLK0_IN : in STD_LOGIC; TTC0_CLK1_IN : in STD_LOGIC; TTC0_CLK2_IN : in STD_LOGIC; TTC1_WAVE0_OUT : out STD_LOGIC; TTC1_WAVE1_OUT : out STD_LOGIC; TTC1_WAVE2_OUT : out STD_LOGIC; TTC1_CLK0_IN : in STD_LOGIC; TTC1_CLK1_IN : in STD_LOGIC; TTC1_CLK2_IN : in STD_LOGIC; WDT_CLK_IN : in STD_LOGIC; WDT_RST_OUT : out STD_LOGIC; TRACE_CLK : in STD_LOGIC; TRACE_CTL : out STD_LOGIC; TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 ); TRACE_CLK_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB1_VBUS_PWRSELECT : out STD_LOGIC; USB1_VBUS_PWRFAULT : in STD_LOGIC; SRAM_INTIN : in STD_LOGIC; M_AXI_GP0_ARESETN : out STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARESETN : out STD_LOGIC; M_AXI_GP1_ARVALID : out STD_LOGIC; M_AXI_GP1_AWVALID : out STD_LOGIC; M_AXI_GP1_BREADY : out STD_LOGIC; M_AXI_GP1_RREADY : out STD_LOGIC; M_AXI_GP1_WLAST : out STD_LOGIC; M_AXI_GP1_WVALID : out STD_LOGIC; M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ACLK : in STD_LOGIC; M_AXI_GP1_ARREADY : in STD_LOGIC; M_AXI_GP1_AWREADY : in STD_LOGIC; M_AXI_GP1_BVALID : in STD_LOGIC; M_AXI_GP1_RLAST : in STD_LOGIC; M_AXI_GP1_RVALID : in STD_LOGIC; M_AXI_GP1_WREADY : in STD_LOGIC; M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARESETN : out STD_LOGIC; S_AXI_GP0_ARREADY : out STD_LOGIC; S_AXI_GP0_AWREADY : out STD_LOGIC; S_AXI_GP0_BVALID : out STD_LOGIC; S_AXI_GP0_RLAST : out STD_LOGIC; S_AXI_GP0_RVALID : out STD_LOGIC; S_AXI_GP0_WREADY : out STD_LOGIC; S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_ACLK : in STD_LOGIC; S_AXI_GP0_ARVALID : in STD_LOGIC; S_AXI_GP0_AWVALID : in STD_LOGIC; S_AXI_GP0_BREADY : in STD_LOGIC; S_AXI_GP0_RREADY : in STD_LOGIC; S_AXI_GP0_WLAST : in STD_LOGIC; S_AXI_GP0_WVALID : in STD_LOGIC; S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ARESETN : out STD_LOGIC; S_AXI_GP1_ARREADY : out STD_LOGIC; S_AXI_GP1_AWREADY : out STD_LOGIC; S_AXI_GP1_BVALID : out STD_LOGIC; S_AXI_GP1_RLAST : out STD_LOGIC; S_AXI_GP1_RVALID : out STD_LOGIC; S_AXI_GP1_WREADY : out STD_LOGIC; S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ACLK : in STD_LOGIC; S_AXI_GP1_ARVALID : in STD_LOGIC; S_AXI_GP1_AWVALID : in STD_LOGIC; S_AXI_GP1_BREADY : in STD_LOGIC; S_AXI_GP1_RREADY : in STD_LOGIC; S_AXI_GP1_WLAST : in STD_LOGIC; S_AXI_GP1_WVALID : in STD_LOGIC; S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_ACP_ARESETN : out STD_LOGIC; S_AXI_ACP_ARREADY : out STD_LOGIC; S_AXI_ACP_AWREADY : out STD_LOGIC; S_AXI_ACP_BVALID : out STD_LOGIC; S_AXI_ACP_RLAST : out STD_LOGIC; S_AXI_ACP_RVALID : out STD_LOGIC; S_AXI_ACP_WREADY : out STD_LOGIC; S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_ACLK : in STD_LOGIC; S_AXI_ACP_ARVALID : in STD_LOGIC; S_AXI_ACP_AWVALID : in STD_LOGIC; S_AXI_ACP_BREADY : in STD_LOGIC; S_AXI_ACP_RREADY : in STD_LOGIC; S_AXI_ACP_WLAST : in STD_LOGIC; S_AXI_ACP_WVALID : in STD_LOGIC; S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_ARESETN : out STD_LOGIC; S_AXI_HP0_ARREADY : out STD_LOGIC; S_AXI_HP0_AWREADY : out STD_LOGIC; S_AXI_HP0_BVALID : out STD_LOGIC; S_AXI_HP0_RLAST : out STD_LOGIC; S_AXI_HP0_RVALID : out STD_LOGIC; S_AXI_HP0_WREADY : out STD_LOGIC; S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_ACLK : in STD_LOGIC; S_AXI_HP0_ARVALID : in STD_LOGIC; S_AXI_HP0_AWVALID : in STD_LOGIC; S_AXI_HP0_BREADY : in STD_LOGIC; S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_RREADY : in STD_LOGIC; S_AXI_HP0_WLAST : in STD_LOGIC; S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_WVALID : in STD_LOGIC; S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_ARESETN : out STD_LOGIC; S_AXI_HP1_ARREADY : out STD_LOGIC; S_AXI_HP1_AWREADY : out STD_LOGIC; S_AXI_HP1_BVALID : out STD_LOGIC; S_AXI_HP1_RLAST : out STD_LOGIC; S_AXI_HP1_RVALID : out STD_LOGIC; S_AXI_HP1_WREADY : out STD_LOGIC; S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_ACLK : in STD_LOGIC; S_AXI_HP1_ARVALID : in STD_LOGIC; S_AXI_HP1_AWVALID : in STD_LOGIC; S_AXI_HP1_BREADY : in STD_LOGIC; S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_RREADY : in STD_LOGIC; S_AXI_HP1_WLAST : in STD_LOGIC; S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_WVALID : in STD_LOGIC; S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_ARESETN : out STD_LOGIC; S_AXI_HP2_ARREADY : out STD_LOGIC; S_AXI_HP2_AWREADY : out STD_LOGIC; S_AXI_HP2_BVALID : out STD_LOGIC; S_AXI_HP2_RLAST : out STD_LOGIC; S_AXI_HP2_RVALID : out STD_LOGIC; S_AXI_HP2_WREADY : out STD_LOGIC; S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_ACLK : in STD_LOGIC; S_AXI_HP2_ARVALID : in STD_LOGIC; S_AXI_HP2_AWVALID : in STD_LOGIC; S_AXI_HP2_BREADY : in STD_LOGIC; S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_RREADY : in STD_LOGIC; S_AXI_HP2_WLAST : in STD_LOGIC; S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_WVALID : in STD_LOGIC; S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_ARESETN : out STD_LOGIC; S_AXI_HP3_ARREADY : out STD_LOGIC; S_AXI_HP3_AWREADY : out STD_LOGIC; S_AXI_HP3_BVALID : out STD_LOGIC; S_AXI_HP3_RLAST : out STD_LOGIC; S_AXI_HP3_RVALID : out STD_LOGIC; S_AXI_HP3_WREADY : out STD_LOGIC; S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_ACLK : in STD_LOGIC; S_AXI_HP3_ARVALID : in STD_LOGIC; S_AXI_HP3_AWVALID : in STD_LOGIC; S_AXI_HP3_BREADY : in STD_LOGIC; S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_RREADY : in STD_LOGIC; S_AXI_HP3_WLAST : in STD_LOGIC; S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_WVALID : in STD_LOGIC; S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); IRQ_P2F_DMAC_ABORT : out STD_LOGIC; IRQ_P2F_DMAC0 : out STD_LOGIC; IRQ_P2F_DMAC1 : out STD_LOGIC; IRQ_P2F_DMAC2 : out STD_LOGIC; IRQ_P2F_DMAC3 : out STD_LOGIC; IRQ_P2F_DMAC4 : out STD_LOGIC; IRQ_P2F_DMAC5 : out STD_LOGIC; IRQ_P2F_DMAC6 : out STD_LOGIC; IRQ_P2F_DMAC7 : out STD_LOGIC; IRQ_P2F_SMC : out STD_LOGIC; IRQ_P2F_QSPI : out STD_LOGIC; IRQ_P2F_CTI : out STD_LOGIC; IRQ_P2F_GPIO : out STD_LOGIC; IRQ_P2F_USB0 : out STD_LOGIC; IRQ_P2F_ENET0 : out STD_LOGIC; IRQ_P2F_ENET_WAKE0 : out STD_LOGIC; IRQ_P2F_SDIO0 : out STD_LOGIC; IRQ_P2F_I2C0 : out STD_LOGIC; IRQ_P2F_SPI0 : out STD_LOGIC; IRQ_P2F_UART0 : out STD_LOGIC; IRQ_P2F_CAN0 : out STD_LOGIC; IRQ_P2F_USB1 : out STD_LOGIC; IRQ_P2F_ENET1 : out STD_LOGIC; IRQ_P2F_ENET_WAKE1 : out STD_LOGIC; IRQ_P2F_SDIO1 : out STD_LOGIC; IRQ_P2F_I2C1 : out STD_LOGIC; IRQ_P2F_SPI1 : out STD_LOGIC; IRQ_P2F_UART1 : out STD_LOGIC; IRQ_P2F_CAN1 : out STD_LOGIC; IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 ); Core0_nFIQ : in STD_LOGIC; Core0_nIRQ : in STD_LOGIC; Core1_nFIQ : in STD_LOGIC; Core1_nIRQ : in STD_LOGIC; DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA0_DAVALID : out STD_LOGIC; DMA0_DRREADY : out STD_LOGIC; DMA0_RSTN : out STD_LOGIC; DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DAVALID : out STD_LOGIC; DMA1_DRREADY : out STD_LOGIC; DMA1_RSTN : out STD_LOGIC; DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DAVALID : out STD_LOGIC; DMA2_DRREADY : out STD_LOGIC; DMA2_RSTN : out STD_LOGIC; DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DAVALID : out STD_LOGIC; DMA3_DRREADY : out STD_LOGIC; DMA3_RSTN : out STD_LOGIC; DMA0_ACLK : in STD_LOGIC; DMA0_DAREADY : in STD_LOGIC; DMA0_DRLAST : in STD_LOGIC; DMA0_DRVALID : in STD_LOGIC; DMA1_ACLK : in STD_LOGIC; DMA1_DAREADY : in STD_LOGIC; DMA1_DRLAST : in STD_LOGIC; DMA1_DRVALID : in STD_LOGIC; DMA2_ACLK : in STD_LOGIC; DMA2_DAREADY : in STD_LOGIC; DMA2_DRLAST : in STD_LOGIC; DMA2_DRVALID : in STD_LOGIC; DMA3_ACLK : in STD_LOGIC; DMA3_DAREADY : in STD_LOGIC; DMA3_DRLAST : in STD_LOGIC; DMA3_DRVALID : in STD_LOGIC; DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); FCLK_CLK3 : out STD_LOGIC; FCLK_CLK2 : out STD_LOGIC; FCLK_CLK1 : out STD_LOGIC; FCLK_CLK0 : out STD_LOGIC; FCLK_CLKTRIG3_N : in STD_LOGIC; FCLK_CLKTRIG2_N : in STD_LOGIC; FCLK_CLKTRIG1_N : in STD_LOGIC; FCLK_CLKTRIG0_N : in STD_LOGIC; FCLK_RESET3_N : out STD_LOGIC; FCLK_RESET2_N : out STD_LOGIC; FCLK_RESET1_N : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMD_TRACEIN_VALID : in STD_LOGIC; FTMD_TRACEIN_CLK : in STD_LOGIC; FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 ); FTMT_F2P_TRIG_0 : in STD_LOGIC; FTMT_F2P_TRIGACK_0 : out STD_LOGIC; FTMT_F2P_TRIG_1 : in STD_LOGIC; FTMT_F2P_TRIGACK_1 : out STD_LOGIC; FTMT_F2P_TRIG_2 : in STD_LOGIC; FTMT_F2P_TRIGACK_2 : out STD_LOGIC; FTMT_F2P_TRIG_3 : in STD_LOGIC; FTMT_F2P_TRIGACK_3 : out STD_LOGIC; FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMT_P2F_TRIGACK_0 : in STD_LOGIC; FTMT_P2F_TRIG_0 : out STD_LOGIC; FTMT_P2F_TRIGACK_1 : in STD_LOGIC; FTMT_P2F_TRIG_1 : out STD_LOGIC; FTMT_P2F_TRIGACK_2 : in STD_LOGIC; FTMT_P2F_TRIG_2 : out STD_LOGIC; FTMT_P2F_TRIGACK_3 : in STD_LOGIC; FTMT_P2F_TRIG_3 : out STD_LOGIC; FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 ); FPGA_IDLE_N : in STD_LOGIC; EVENT_EVENTO : out STD_LOGIC; EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_EVENTI : in STD_LOGIC; DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 ); MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_GP0_EN_MODIFIABLE_TXN : integer; attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_GP1_EN_MODIFIABLE_TXN : integer; attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT"; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg400"; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION"; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8; attribute C_USE_AXI_NONSECURE : integer; attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_M_AXI_GP0 : integer; attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_USE_M_AXI_GP1 : integer; attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_ACP : integer; attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_GP0 : integer; attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_GP1 : integer; attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP0 : integer; attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP1 : integer; attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP2 : integer; attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP3 : integer; attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute HW_HANDOFF : string; attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "design_1_processing_system7_0_0.hwdef"; attribute POWER : string; attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={50} usageRate={0.5} />/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal ENET0_MDIO_T_n : STD_LOGIC; signal ENET1_MDIO_T_n : STD_LOGIC; signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 ); signal I2C0_SCL_T_n : STD_LOGIC; signal I2C0_SDA_T_n : STD_LOGIC; signal I2C1_SCL_T_n : STD_LOGIC; signal I2C1_SDA_T_n : STD_LOGIC; signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal SDIO0_CMD_T_n : STD_LOGIC; signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal SDIO1_CMD_T_n : STD_LOGIC; signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal SPI0_MISO_T_n : STD_LOGIC; signal SPI0_MOSI_T_n : STD_LOGIC; signal SPI0_SCLK_T_n : STD_LOGIC; signal SPI0_SS_T_n : STD_LOGIC; signal SPI1_MISO_T_n : STD_LOGIC; signal SPI1_MOSI_T_n : STD_LOGIC; signal SPI1_SCLK_T_n : STD_LOGIC; signal SPI1_SS_T_n : STD_LOGIC; signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true"; signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true"; signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true"; signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true"; signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true"; signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true"; signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true"; signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true"; signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true"; signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true"; signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true"; signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true"; signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true"; signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true"; signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true"; signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true"; signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 ); signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal buffered_DDR_CAS_n : STD_LOGIC; signal buffered_DDR_CKE : STD_LOGIC; signal buffered_DDR_CS_n : STD_LOGIC; signal buffered_DDR_Clk : STD_LOGIC; signal buffered_DDR_Clk_n : STD_LOGIC; signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DRSTB : STD_LOGIC; signal buffered_DDR_ODT : STD_LOGIC; signal buffered_DDR_RAS_n : STD_LOGIC; signal buffered_DDR_VRN : STD_LOGIC; signal buffered_DDR_VRP : STD_LOGIC; signal buffered_DDR_WEB : STD_LOGIC; signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); signal buffered_PS_CLK : STD_LOGIC; signal buffered_PS_PORB : STD_LOGIC; signal buffered_PS_SRSTB : STD_LOGIC; signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); attribute BOX_TYPE : string; attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS7_i : label is "PRIMITIVE"; attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; begin ENET0_GMII_TXD(7) <= \<const0>\; ENET0_GMII_TXD(6) <= \<const0>\; ENET0_GMII_TXD(5) <= \<const0>\; ENET0_GMII_TXD(4) <= \<const0>\; ENET0_GMII_TXD(3) <= \<const0>\; ENET0_GMII_TXD(2) <= \<const0>\; ENET0_GMII_TXD(1) <= \<const0>\; ENET0_GMII_TXD(0) <= \<const0>\; ENET0_GMII_TX_EN <= \<const0>\; ENET0_GMII_TX_ER <= \<const0>\; ENET1_GMII_TXD(7) <= \<const0>\; ENET1_GMII_TXD(6) <= \<const0>\; ENET1_GMII_TXD(5) <= \<const0>\; ENET1_GMII_TXD(4) <= \<const0>\; ENET1_GMII_TXD(3) <= \<const0>\; ENET1_GMII_TXD(2) <= \<const0>\; ENET1_GMII_TXD(1) <= \<const0>\; ENET1_GMII_TXD(0) <= \<const0>\; ENET1_GMII_TX_EN <= \<const0>\; ENET1_GMII_TX_ER <= \<const0>\; M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2); M_AXI_GP0_ARCACHE(1) <= \<const1>\; M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0); M_AXI_GP0_ARSIZE(2) <= \<const0>\; M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0); M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2); M_AXI_GP0_AWCACHE(1) <= \<const1>\; M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0); M_AXI_GP0_AWSIZE(2) <= \<const0>\; M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0); M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2); M_AXI_GP1_ARCACHE(1) <= \<const1>\; M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0); M_AXI_GP1_ARSIZE(2) <= \<const0>\; M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0); M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2); M_AXI_GP1_AWCACHE(1) <= \<const1>\; M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0); M_AXI_GP1_AWSIZE(2) <= \<const0>\; M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0); PJTAG_TDO <= \<const0>\; TRACE_CLK_OUT <= \<const0>\; TRACE_CTL <= \TRACE_CTL_PIPE[0]\; TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0); DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CAS_n, PAD => DDR_CAS_n ); DDR_CKE_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CKE, PAD => DDR_CKE ); DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CS_n, PAD => DDR_CS_n ); DDR_Clk_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk, PAD => DDR_Clk ); DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk_n, PAD => DDR_Clk_n ); DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DRSTB, PAD => DDR_DRSTB ); DDR_ODT_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_ODT, PAD => DDR_ODT ); DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_RAS_n, PAD => DDR_RAS_n ); DDR_VRN_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRN, PAD => DDR_VRN ); DDR_VRP_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRP, PAD => DDR_VRP ); DDR_WEB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_WEB, PAD => DDR_WEB ); ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET0_MDIO_T_n, O => ENET0_MDIO_T ); ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET1_MDIO_T_n, O => ENET1_MDIO_T ); GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(0), O => GPIO_T(0) ); \GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(10), O => GPIO_T(10) ); \GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(11), O => GPIO_T(11) ); \GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(12), O => GPIO_T(12) ); \GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(13), O => GPIO_T(13) ); \GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(14), O => GPIO_T(14) ); \GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(15), O => GPIO_T(15) ); \GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(16), O => GPIO_T(16) ); \GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(17), O => GPIO_T(17) ); \GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(18), O => GPIO_T(18) ); \GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(19), O => GPIO_T(19) ); \GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(1), O => GPIO_T(1) ); \GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(20), O => GPIO_T(20) ); \GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(21), O => GPIO_T(21) ); \GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(22), O => GPIO_T(22) ); \GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(23), O => GPIO_T(23) ); \GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(24), O => GPIO_T(24) ); \GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(25), O => GPIO_T(25) ); \GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(26), O => GPIO_T(26) ); \GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(27), O => GPIO_T(27) ); \GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(28), O => GPIO_T(28) ); \GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(29), O => GPIO_T(29) ); \GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(2), O => GPIO_T(2) ); \GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(30), O => GPIO_T(30) ); \GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(31), O => GPIO_T(31) ); \GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(32), O => GPIO_T(32) ); \GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(33), O => GPIO_T(33) ); \GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(34), O => GPIO_T(34) ); \GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(35), O => GPIO_T(35) ); \GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(36), O => GPIO_T(36) ); \GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(37), O => GPIO_T(37) ); \GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(38), O => GPIO_T(38) ); \GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(39), O => GPIO_T(39) ); \GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(3), O => GPIO_T(3) ); \GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(40), O => GPIO_T(40) ); \GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(41), O => GPIO_T(41) ); \GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(42), O => GPIO_T(42) ); \GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(43), O => GPIO_T(43) ); \GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(44), O => GPIO_T(44) ); \GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(45), O => GPIO_T(45) ); \GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(46), O => GPIO_T(46) ); \GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(47), O => GPIO_T(47) ); \GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(48), O => GPIO_T(48) ); \GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(49), O => GPIO_T(49) ); \GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(4), O => GPIO_T(4) ); \GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(50), O => GPIO_T(50) ); \GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(51), O => GPIO_T(51) ); \GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(52), O => GPIO_T(52) ); \GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(53), O => GPIO_T(53) ); \GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(54), O => GPIO_T(54) ); \GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(55), O => GPIO_T(55) ); \GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(56), O => GPIO_T(56) ); \GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(57), O => GPIO_T(57) ); \GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(58), O => GPIO_T(58) ); \GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(59), O => GPIO_T(59) ); \GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(5), O => GPIO_T(5) ); \GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(60), O => GPIO_T(60) ); \GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(61), O => GPIO_T(61) ); \GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(62), O => GPIO_T(62) ); \GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(63), O => GPIO_T(63) ); \GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(6), O => GPIO_T(6) ); \GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(7), O => GPIO_T(7) ); \GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(8), O => GPIO_T(8) ); \GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(9), O => GPIO_T(9) ); I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SCL_T_n, O => I2C0_SCL_T ); I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SDA_T_n, O => I2C0_SDA_T ); I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SCL_T_n, O => I2C1_SCL_T ); I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SDA_T_n, O => I2C1_SDA_T ); PS7_i: unisim.vcomponents.PS7 port map ( DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0), DDRARB(3 downto 0) => DDR_ARB(3 downto 0), DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0), DDRCASB => buffered_DDR_CAS_n, DDRCKE => buffered_DDR_CKE, DDRCKN => buffered_DDR_Clk_n, DDRCKP => buffered_DDR_Clk, DDRCSB => buffered_DDR_CS_n, DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0), DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0), DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0), DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0), DDRDRSTB => buffered_DDR_DRSTB, DDRODT => buffered_DDR_ODT, DDRRASB => buffered_DDR_RAS_n, DDRVRN => buffered_DDR_VRN, DDRVRP => buffered_DDR_VRP, DDRWEB => buffered_DDR_WEB, DMA0ACLK => DMA0_ACLK, DMA0DAREADY => DMA0_DAREADY, DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0), DMA0DAVALID => DMA0_DAVALID, DMA0DRLAST => DMA0_DRLAST, DMA0DRREADY => DMA0_DRREADY, DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0), DMA0DRVALID => DMA0_DRVALID, DMA0RSTN => DMA0_RSTN, DMA1ACLK => DMA1_ACLK, DMA1DAREADY => DMA1_DAREADY, DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0), DMA1DAVALID => DMA1_DAVALID, DMA1DRLAST => DMA1_DRLAST, DMA1DRREADY => DMA1_DRREADY, DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0), DMA1DRVALID => DMA1_DRVALID, DMA1RSTN => DMA1_RSTN, DMA2ACLK => DMA2_ACLK, DMA2DAREADY => DMA2_DAREADY, DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0), DMA2DAVALID => DMA2_DAVALID, DMA2DRLAST => DMA2_DRLAST, DMA2DRREADY => DMA2_DRREADY, DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0), DMA2DRVALID => DMA2_DRVALID, DMA2RSTN => DMA2_RSTN, DMA3ACLK => DMA3_ACLK, DMA3DAREADY => DMA3_DAREADY, DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0), DMA3DAVALID => DMA3_DAVALID, DMA3DRLAST => DMA3_DRLAST, DMA3DRREADY => DMA3_DRREADY, DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0), DMA3DRVALID => DMA3_DRVALID, DMA3RSTN => DMA3_RSTN, EMIOCAN0PHYRX => CAN0_PHY_RX, EMIOCAN0PHYTX => CAN0_PHY_TX, EMIOCAN1PHYRX => CAN1_PHY_RX, EMIOCAN1PHYTX => CAN1_PHY_TX, EMIOENET0EXTINTIN => ENET0_EXT_INTIN, EMIOENET0GMIICOL => '0', EMIOENET0GMIICRS => '0', EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK, EMIOENET0GMIIRXD(7 downto 0) => B"00000000", EMIOENET0GMIIRXDV => '0', EMIOENET0GMIIRXER => '0', EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK, EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0), EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED, EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED, EMIOENET0MDIOI => ENET0_MDIO_I, EMIOENET0MDIOMDC => ENET0_MDIO_MDC, EMIOENET0MDIOO => ENET0_MDIO_O, EMIOENET0MDIOTN => ENET0_MDIO_T_n, EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX, EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX, EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX, EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX, EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX, EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX, EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX, EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX, EMIOENET0SOFRX => ENET0_SOF_RX, EMIOENET0SOFTX => ENET0_SOF_TX, EMIOENET1EXTINTIN => ENET1_EXT_INTIN, EMIOENET1GMIICOL => '0', EMIOENET1GMIICRS => '0', EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK, EMIOENET1GMIIRXD(7 downto 0) => B"00000000", EMIOENET1GMIIRXDV => '0', EMIOENET1GMIIRXER => '0', EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK, EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0), EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED, EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED, EMIOENET1MDIOI => ENET1_MDIO_I, EMIOENET1MDIOMDC => ENET1_MDIO_MDC, EMIOENET1MDIOO => ENET1_MDIO_O, EMIOENET1MDIOTN => ENET1_MDIO_T_n, EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX, EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX, EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX, EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX, EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX, EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX, EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX, EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX, EMIOENET1SOFRX => ENET1_SOF_RX, EMIOENET1SOFTX => ENET1_SOF_TX, EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0), EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0), EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0), EMIOI2C0SCLI => I2C0_SCL_I, EMIOI2C0SCLO => I2C0_SCL_O, EMIOI2C0SCLTN => I2C0_SCL_T_n, EMIOI2C0SDAI => I2C0_SDA_I, EMIOI2C0SDAO => I2C0_SDA_O, EMIOI2C0SDATN => I2C0_SDA_T_n, EMIOI2C1SCLI => I2C1_SCL_I, EMIOI2C1SCLO => I2C1_SCL_O, EMIOI2C1SCLTN => I2C1_SCL_T_n, EMIOI2C1SDAI => I2C1_SDA_I, EMIOI2C1SDAO => I2C1_SDA_O, EMIOI2C1SDATN => I2C1_SDA_T_n, EMIOPJTAGTCK => PJTAG_TCK, EMIOPJTAGTDI => PJTAG_TDI, EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED, EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED, EMIOPJTAGTMS => PJTAG_TMS, EMIOSDIO0BUSPOW => SDIO0_BUSPOW, EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0), EMIOSDIO0CDN => SDIO0_CDN, EMIOSDIO0CLK => SDIO0_CLK, EMIOSDIO0CLKFB => SDIO0_CLK_FB, EMIOSDIO0CMDI => SDIO0_CMD_I, EMIOSDIO0CMDO => SDIO0_CMD_O, EMIOSDIO0CMDTN => SDIO0_CMD_T_n, EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0), EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0), EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0), EMIOSDIO0LED => SDIO0_LED, EMIOSDIO0WP => SDIO0_WP, EMIOSDIO1BUSPOW => SDIO1_BUSPOW, EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0), EMIOSDIO1CDN => SDIO1_CDN, EMIOSDIO1CLK => SDIO1_CLK, EMIOSDIO1CLKFB => SDIO1_CLK_FB, EMIOSDIO1CMDI => SDIO1_CMD_I, EMIOSDIO1CMDO => SDIO1_CMD_O, EMIOSDIO1CMDTN => SDIO1_CMD_T_n, EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0), EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0), EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0), EMIOSDIO1LED => SDIO1_LED, EMIOSDIO1WP => SDIO1_WP, EMIOSPI0MI => SPI0_MISO_I, EMIOSPI0MO => SPI0_MOSI_O, EMIOSPI0MOTN => SPI0_MOSI_T_n, EMIOSPI0SCLKI => SPI0_SCLK_I, EMIOSPI0SCLKO => SPI0_SCLK_O, EMIOSPI0SCLKTN => SPI0_SCLK_T_n, EMIOSPI0SI => SPI0_MOSI_I, EMIOSPI0SO => SPI0_MISO_O, EMIOSPI0SSIN => SPI0_SS_I, EMIOSPI0SSNTN => SPI0_SS_T_n, EMIOSPI0SSON(2) => SPI0_SS2_O, EMIOSPI0SSON(1) => SPI0_SS1_O, EMIOSPI0SSON(0) => SPI0_SS_O, EMIOSPI0STN => SPI0_MISO_T_n, EMIOSPI1MI => SPI1_MISO_I, EMIOSPI1MO => SPI1_MOSI_O, EMIOSPI1MOTN => SPI1_MOSI_T_n, EMIOSPI1SCLKI => SPI1_SCLK_I, EMIOSPI1SCLKO => SPI1_SCLK_O, EMIOSPI1SCLKTN => SPI1_SCLK_T_n, EMIOSPI1SI => SPI1_MOSI_I, EMIOSPI1SO => SPI1_MISO_O, EMIOSPI1SSIN => SPI1_SS_I, EMIOSPI1SSNTN => SPI1_SS_T_n, EMIOSPI1SSON(2) => SPI1_SS2_O, EMIOSPI1SSON(1) => SPI1_SS1_O, EMIOSPI1SSON(0) => SPI1_SS_O, EMIOSPI1STN => SPI1_MISO_T_n, EMIOSRAMINTIN => SRAM_INTIN, EMIOTRACECLK => TRACE_CLK, EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED, EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0), EMIOTTC0CLKI(2) => TTC0_CLK2_IN, EMIOTTC0CLKI(1) => TTC0_CLK1_IN, EMIOTTC0CLKI(0) => TTC0_CLK0_IN, EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT, EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT, EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT, EMIOTTC1CLKI(2) => TTC1_CLK2_IN, EMIOTTC1CLKI(1) => TTC1_CLK1_IN, EMIOTTC1CLKI(0) => TTC1_CLK0_IN, EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT, EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT, EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT, EMIOUART0CTSN => UART0_CTSN, EMIOUART0DCDN => UART0_DCDN, EMIOUART0DSRN => UART0_DSRN, EMIOUART0DTRN => UART0_DTRN, EMIOUART0RIN => UART0_RIN, EMIOUART0RTSN => UART0_RTSN, EMIOUART0RX => UART0_RX, EMIOUART0TX => UART0_TX, EMIOUART1CTSN => UART1_CTSN, EMIOUART1DCDN => UART1_DCDN, EMIOUART1DSRN => UART1_DSRN, EMIOUART1DTRN => UART1_DTRN, EMIOUART1RIN => UART1_RIN, EMIOUART1RTSN => UART1_RTSN, EMIOUART1RX => UART1_RX, EMIOUART1TX => UART1_TX, EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT, EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT, EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0), EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT, EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT, EMIOWDTCLKI => WDT_CLK_IN, EMIOWDTRSTO => WDT_RST_OUT, EVENTEVENTI => EVENT_EVENTI, EVENTEVENTO => EVENT_EVENTO, EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0), EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0), FCLKCLK(3) => FCLK_CLK3, FCLKCLK(2) => FCLK_CLK2, FCLKCLK(1) => FCLK_CLK1, FCLKCLK(0) => FCLK_CLK_unbuffered(0), FCLKCLKTRIGN(3 downto 0) => B"0000", FCLKRESETN(3) => FCLK_RESET3_N, FCLKRESETN(2) => FCLK_RESET2_N, FCLKRESETN(1) => FCLK_RESET1_N, FCLKRESETN(0) => FCLK_RESET0_N, FPGAIDLEN => FPGA_IDLE_N, FTMDTRACEINATID(3 downto 0) => B"0000", FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK, FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000", FTMDTRACEINVALID => '0', FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0), FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3, FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2, FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1, FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0, FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3, FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2, FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1, FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0, FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0), FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3, FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2, FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1, FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0, FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3, FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2, FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1, FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0, IRQF2P(19) => Core1_nFIQ, IRQF2P(18) => Core0_nFIQ, IRQF2P(17) => Core1_nIRQ, IRQF2P(16) => Core0_nIRQ, IRQF2P(15 downto 1) => B"000000000000000", IRQF2P(0) => IRQ_F2P(0), IRQP2F(28) => IRQ_P2F_DMAC_ABORT, IRQP2F(27) => IRQ_P2F_DMAC7, IRQP2F(26) => IRQ_P2F_DMAC6, IRQP2F(25) => IRQ_P2F_DMAC5, IRQP2F(24) => IRQ_P2F_DMAC4, IRQP2F(23) => IRQ_P2F_DMAC3, IRQP2F(22) => IRQ_P2F_DMAC2, IRQP2F(21) => IRQ_P2F_DMAC1, IRQP2F(20) => IRQ_P2F_DMAC0, IRQP2F(19) => IRQ_P2F_SMC, IRQP2F(18) => IRQ_P2F_QSPI, IRQP2F(17) => IRQ_P2F_CTI, IRQP2F(16) => IRQ_P2F_GPIO, IRQP2F(15) => IRQ_P2F_USB0, IRQP2F(14) => IRQ_P2F_ENET0, IRQP2F(13) => IRQ_P2F_ENET_WAKE0, IRQP2F(12) => IRQ_P2F_SDIO0, IRQP2F(11) => IRQ_P2F_I2C0, IRQP2F(10) => IRQ_P2F_SPI0, IRQP2F(9) => IRQ_P2F_UART0, IRQP2F(8) => IRQ_P2F_CAN0, IRQP2F(7) => IRQ_P2F_USB1, IRQP2F(6) => IRQ_P2F_ENET1, IRQP2F(5) => IRQ_P2F_ENET_WAKE1, IRQP2F(4) => IRQ_P2F_SDIO1, IRQP2F(3) => IRQ_P2F_I2C1, IRQP2F(2) => IRQ_P2F_SPI1, IRQP2F(1) => IRQ_P2F_UART1, IRQP2F(0) => IRQ_P2F_CAN1, MAXIGP0ACLK => M_AXI_GP0_ACLK, MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2), MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1), MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0), MAXIGP0ARESETN => M_AXI_GP0_ARESETN, MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), MAXIGP0ARREADY => M_AXI_GP0_ARREADY, MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0), MAXIGP0ARVALID => M_AXI_GP0_ARVALID, MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2), MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1), MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0), MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), MAXIGP0AWREADY => M_AXI_GP0_AWREADY, MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0), MAXIGP0AWVALID => M_AXI_GP0_AWVALID, MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), MAXIGP0BREADY => M_AXI_GP0_BREADY, MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), MAXIGP0BVALID => M_AXI_GP0_BVALID, MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), MAXIGP0RLAST => M_AXI_GP0_RLAST, MAXIGP0RREADY => M_AXI_GP0_RREADY, MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), MAXIGP0RVALID => M_AXI_GP0_RVALID, MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), MAXIGP0WLAST => M_AXI_GP0_WLAST, MAXIGP0WREADY => M_AXI_GP0_WREADY, MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), MAXIGP0WVALID => M_AXI_GP0_WVALID, MAXIGP1ACLK => M_AXI_GP1_ACLK, MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0), MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0), MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2), MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1), MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0), MAXIGP1ARESETN => M_AXI_GP1_ARESETN, MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0), MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0), MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0), MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0), MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0), MAXIGP1ARREADY => M_AXI_GP1_ARREADY, MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0), MAXIGP1ARVALID => M_AXI_GP1_ARVALID, MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0), MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0), MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2), MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1), MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0), MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0), MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0), MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0), MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0), MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0), MAXIGP1AWREADY => M_AXI_GP1_AWREADY, MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0), MAXIGP1AWVALID => M_AXI_GP1_AWVALID, MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0), MAXIGP1BREADY => M_AXI_GP1_BREADY, MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0), MAXIGP1BVALID => M_AXI_GP1_BVALID, MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0), MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0), MAXIGP1RLAST => M_AXI_GP1_RLAST, MAXIGP1RREADY => M_AXI_GP1_RREADY, MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0), MAXIGP1RVALID => M_AXI_GP1_RVALID, MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0), MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0), MAXIGP1WLAST => M_AXI_GP1_WLAST, MAXIGP1WREADY => M_AXI_GP1_WREADY, MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0), MAXIGP1WVALID => M_AXI_GP1_WVALID, MIO(53 downto 0) => buffered_MIO(53 downto 0), PSCLK => buffered_PS_CLK, PSPORB => buffered_PS_PORB, PSSRSTB => buffered_PS_SRSTB, SAXIACPACLK => S_AXI_ACP_ACLK, SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0), SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0), SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0), SAXIACPARESETN => S_AXI_ACP_ARESETN, SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0), SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0), SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0), SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0), SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0), SAXIACPARREADY => S_AXI_ACP_ARREADY, SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0), SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0), SAXIACPARVALID => S_AXI_ACP_ARVALID, SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0), SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0), SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0), SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0), SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0), SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0), SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0), SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0), SAXIACPAWREADY => S_AXI_ACP_AWREADY, SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0), SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0), SAXIACPAWVALID => S_AXI_ACP_AWVALID, SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0), SAXIACPBREADY => S_AXI_ACP_BREADY, SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0), SAXIACPBVALID => S_AXI_ACP_BVALID, SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0), SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0), SAXIACPRLAST => S_AXI_ACP_RLAST, SAXIACPRREADY => S_AXI_ACP_RREADY, SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0), SAXIACPRVALID => S_AXI_ACP_RVALID, SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0), SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0), SAXIACPWLAST => S_AXI_ACP_WLAST, SAXIACPWREADY => S_AXI_ACP_WREADY, SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0), SAXIACPWVALID => S_AXI_ACP_WVALID, SAXIGP0ACLK => S_AXI_GP0_ACLK, SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0), SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0), SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0), SAXIGP0ARESETN => S_AXI_GP0_ARESETN, SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0), SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0), SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0), SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0), SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0), SAXIGP0ARREADY => S_AXI_GP0_ARREADY, SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0), SAXIGP0ARVALID => S_AXI_GP0_ARVALID, SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0), SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0), SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0), SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0), SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0), SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0), SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0), SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0), SAXIGP0AWREADY => S_AXI_GP0_AWREADY, SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0), SAXIGP0AWVALID => S_AXI_GP0_AWVALID, SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0), SAXIGP0BREADY => S_AXI_GP0_BREADY, SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0), SAXIGP0BVALID => S_AXI_GP0_BVALID, SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0), SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0), SAXIGP0RLAST => S_AXI_GP0_RLAST, SAXIGP0RREADY => S_AXI_GP0_RREADY, SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0), SAXIGP0RVALID => S_AXI_GP0_RVALID, SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0), SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0), SAXIGP0WLAST => S_AXI_GP0_WLAST, SAXIGP0WREADY => S_AXI_GP0_WREADY, SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0), SAXIGP0WVALID => S_AXI_GP0_WVALID, SAXIGP1ACLK => S_AXI_GP1_ACLK, SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0), SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0), SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0), SAXIGP1ARESETN => S_AXI_GP1_ARESETN, SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0), SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0), SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0), SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0), SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0), SAXIGP1ARREADY => S_AXI_GP1_ARREADY, SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0), SAXIGP1ARVALID => S_AXI_GP1_ARVALID, SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0), SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0), SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0), SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0), SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0), SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0), SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0), SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0), SAXIGP1AWREADY => S_AXI_GP1_AWREADY, SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0), SAXIGP1AWVALID => S_AXI_GP1_AWVALID, SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0), SAXIGP1BREADY => S_AXI_GP1_BREADY, SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0), SAXIGP1BVALID => S_AXI_GP1_BVALID, SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0), SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0), SAXIGP1RLAST => S_AXI_GP1_RLAST, SAXIGP1RREADY => S_AXI_GP1_RREADY, SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0), SAXIGP1RVALID => S_AXI_GP1_RVALID, SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0), SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0), SAXIGP1WLAST => S_AXI_GP1_WLAST, SAXIGP1WREADY => S_AXI_GP1_WREADY, SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0), SAXIGP1WVALID => S_AXI_GP1_WVALID, SAXIHP0ACLK => S_AXI_HP0_ACLK, SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0), SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0), SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0), SAXIHP0ARESETN => S_AXI_HP0_ARESETN, SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0), SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0), SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0), SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0), SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0), SAXIHP0ARREADY => S_AXI_HP0_ARREADY, SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0), SAXIHP0ARVALID => S_AXI_HP0_ARVALID, SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0), SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0), SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0), SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0), SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0), SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0), SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0), SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0), SAXIHP0AWREADY => S_AXI_HP0_AWREADY, SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0), SAXIHP0AWVALID => S_AXI_HP0_AWVALID, SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0), SAXIHP0BREADY => S_AXI_HP0_BREADY, SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0), SAXIHP0BVALID => S_AXI_HP0_BVALID, SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0), SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0), SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0), SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN, SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0), SAXIHP0RLAST => S_AXI_HP0_RLAST, SAXIHP0RREADY => S_AXI_HP0_RREADY, SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0), SAXIHP0RVALID => S_AXI_HP0_RVALID, SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0), SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0), SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0), SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0), SAXIHP0WLAST => S_AXI_HP0_WLAST, SAXIHP0WREADY => S_AXI_HP0_WREADY, SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN, SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0), SAXIHP0WVALID => S_AXI_HP0_WVALID, SAXIHP1ACLK => S_AXI_HP1_ACLK, SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0), SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0), SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0), SAXIHP1ARESETN => S_AXI_HP1_ARESETN, SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0), SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0), SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0), SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0), SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0), SAXIHP1ARREADY => S_AXI_HP1_ARREADY, SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0), SAXIHP1ARVALID => S_AXI_HP1_ARVALID, SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0), SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0), SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0), SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0), SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0), SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0), SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0), SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0), SAXIHP1AWREADY => S_AXI_HP1_AWREADY, SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0), SAXIHP1AWVALID => S_AXI_HP1_AWVALID, SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0), SAXIHP1BREADY => S_AXI_HP1_BREADY, SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0), SAXIHP1BVALID => S_AXI_HP1_BVALID, SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0), SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0), SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0), SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN, SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0), SAXIHP1RLAST => S_AXI_HP1_RLAST, SAXIHP1RREADY => S_AXI_HP1_RREADY, SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0), SAXIHP1RVALID => S_AXI_HP1_RVALID, SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0), SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0), SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0), SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0), SAXIHP1WLAST => S_AXI_HP1_WLAST, SAXIHP1WREADY => S_AXI_HP1_WREADY, SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN, SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0), SAXIHP1WVALID => S_AXI_HP1_WVALID, SAXIHP2ACLK => S_AXI_HP2_ACLK, SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0), SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0), SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0), SAXIHP2ARESETN => S_AXI_HP2_ARESETN, SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0), SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0), SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0), SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0), SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0), SAXIHP2ARREADY => S_AXI_HP2_ARREADY, SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0), SAXIHP2ARVALID => S_AXI_HP2_ARVALID, SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0), SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0), SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0), SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0), SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0), SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0), SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0), SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0), SAXIHP2AWREADY => S_AXI_HP2_AWREADY, SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0), SAXIHP2AWVALID => S_AXI_HP2_AWVALID, SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0), SAXIHP2BREADY => S_AXI_HP2_BREADY, SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0), SAXIHP2BVALID => S_AXI_HP2_BVALID, SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0), SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0), SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0), SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN, SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0), SAXIHP2RLAST => S_AXI_HP2_RLAST, SAXIHP2RREADY => S_AXI_HP2_RREADY, SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0), SAXIHP2RVALID => S_AXI_HP2_RVALID, SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0), SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0), SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0), SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0), SAXIHP2WLAST => S_AXI_HP2_WLAST, SAXIHP2WREADY => S_AXI_HP2_WREADY, SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN, SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0), SAXIHP2WVALID => S_AXI_HP2_WVALID, SAXIHP3ACLK => S_AXI_HP3_ACLK, SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0), SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0), SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0), SAXIHP3ARESETN => S_AXI_HP3_ARESETN, SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0), SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0), SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0), SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0), SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0), SAXIHP3ARREADY => S_AXI_HP3_ARREADY, SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0), SAXIHP3ARVALID => S_AXI_HP3_ARVALID, SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0), SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0), SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0), SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0), SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0), SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0), SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0), SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0), SAXIHP3AWREADY => S_AXI_HP3_AWREADY, SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0), SAXIHP3AWVALID => S_AXI_HP3_AWVALID, SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0), SAXIHP3BREADY => S_AXI_HP3_BREADY, SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0), SAXIHP3BVALID => S_AXI_HP3_BVALID, SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0), SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0), SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0), SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN, SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0), SAXIHP3RLAST => S_AXI_HP3_RLAST, SAXIHP3RREADY => S_AXI_HP3_RREADY, SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0), SAXIHP3RVALID => S_AXI_HP3_RVALID, SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0), SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0), SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0), SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0), SAXIHP3WLAST => S_AXI_HP3_WLAST, SAXIHP3WREADY => S_AXI_HP3_WREADY, SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN, SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0), SAXIHP3WVALID => S_AXI_HP3_WVALID ); PS_CLK_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_CLK, PAD => PS_CLK ); PS_PORB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_PORB, PAD => PS_PORB ); PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_SRSTB, PAD => PS_SRSTB ); SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_CMD_T_n, O => SDIO0_CMD_T ); \SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(0), O => SDIO0_DATA_T(0) ); \SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(1), O => SDIO0_DATA_T(1) ); \SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(2), O => SDIO0_DATA_T(2) ); \SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(3), O => SDIO0_DATA_T(3) ); SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_CMD_T_n, O => SDIO1_CMD_T ); \SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(0), O => SDIO1_DATA_T(0) ); \SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(1), O => SDIO1_DATA_T(1) ); \SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(2), O => SDIO1_DATA_T(2) ); \SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(3), O => SDIO1_DATA_T(3) ); SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MISO_T_n, O => SPI0_MISO_T ); SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MOSI_T_n, O => SPI0_MOSI_T ); SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SCLK_T_n, O => SPI0_SCLK_T ); SPI0_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SS_T_n, O => SPI0_SS_T ); SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MISO_T_n, O => SPI1_MISO_T ); SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MOSI_T_n, O => SPI1_MOSI_T ); SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SCLK_T_n, O => SPI1_SCLK_T ); SPI1_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SS_T_n, O => SPI1_SS_T ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG port map ( I => FCLK_CLK_unbuffered(0), O => FCLK_CLK0 ); \genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(0), PAD => MIO(0) ); \genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(10), PAD => MIO(10) ); \genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(11), PAD => MIO(11) ); \genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(12), PAD => MIO(12) ); \genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(13), PAD => MIO(13) ); \genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(14), PAD => MIO(14) ); \genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(15), PAD => MIO(15) ); \genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(16), PAD => MIO(16) ); \genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(17), PAD => MIO(17) ); \genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(18), PAD => MIO(18) ); \genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(19), PAD => MIO(19) ); \genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(1), PAD => MIO(1) ); \genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(20), PAD => MIO(20) ); \genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(21), PAD => MIO(21) ); \genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(22), PAD => MIO(22) ); \genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(23), PAD => MIO(23) ); \genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(24), PAD => MIO(24) ); \genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(25), PAD => MIO(25) ); \genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(26), PAD => MIO(26) ); \genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(27), PAD => MIO(27) ); \genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(28), PAD => MIO(28) ); \genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(29), PAD => MIO(29) ); \genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(2), PAD => MIO(2) ); \genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(30), PAD => MIO(30) ); \genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(31), PAD => MIO(31) ); \genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(32), PAD => MIO(32) ); \genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(33), PAD => MIO(33) ); \genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(34), PAD => MIO(34) ); \genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(35), PAD => MIO(35) ); \genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(36), PAD => MIO(36) ); \genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(37), PAD => MIO(37) ); \genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(38), PAD => MIO(38) ); \genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(39), PAD => MIO(39) ); \genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(3), PAD => MIO(3) ); \genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(40), PAD => MIO(40) ); \genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(41), PAD => MIO(41) ); \genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(42), PAD => MIO(42) ); \genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(43), PAD => MIO(43) ); \genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(44), PAD => MIO(44) ); \genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(45), PAD => MIO(45) ); \genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(46), PAD => MIO(46) ); \genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(47), PAD => MIO(47) ); \genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(48), PAD => MIO(48) ); \genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(49), PAD => MIO(49) ); \genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(4), PAD => MIO(4) ); \genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(50), PAD => MIO(50) ); \genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(51), PAD => MIO(51) ); \genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(52), PAD => MIO(52) ); \genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(53), PAD => MIO(53) ); \genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(5), PAD => MIO(5) ); \genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(6), PAD => MIO(6) ); \genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(7), PAD => MIO(7) ); \genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(8), PAD => MIO(8) ); \genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(9), PAD => MIO(9) ); \genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(0), PAD => DDR_BankAddr(0) ); \genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(1), PAD => DDR_BankAddr(1) ); \genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(2), PAD => DDR_BankAddr(2) ); \genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(0), PAD => DDR_Addr(0) ); \genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(10), PAD => DDR_Addr(10) ); \genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(11), PAD => DDR_Addr(11) ); \genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(12), PAD => DDR_Addr(12) ); \genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(13), PAD => DDR_Addr(13) ); \genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(14), PAD => DDR_Addr(14) ); \genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(1), PAD => DDR_Addr(1) ); \genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(2), PAD => DDR_Addr(2) ); \genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(3), PAD => DDR_Addr(3) ); \genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(4), PAD => DDR_Addr(4) ); \genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(5), PAD => DDR_Addr(5) ); \genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(6), PAD => DDR_Addr(6) ); \genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(7), PAD => DDR_Addr(7) ); \genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(8), PAD => DDR_Addr(8) ); \genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(9), PAD => DDR_Addr(9) ); \genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(0), PAD => DDR_DM(0) ); \genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(1), PAD => DDR_DM(1) ); \genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(2), PAD => DDR_DM(2) ); \genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(3), PAD => DDR_DM(3) ); \genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(0), PAD => DDR_DQ(0) ); \genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(10), PAD => DDR_DQ(10) ); \genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(11), PAD => DDR_DQ(11) ); \genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(12), PAD => DDR_DQ(12) ); \genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(13), PAD => DDR_DQ(13) ); \genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(14), PAD => DDR_DQ(14) ); \genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(15), PAD => DDR_DQ(15) ); \genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(16), PAD => DDR_DQ(16) ); \genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(17), PAD => DDR_DQ(17) ); \genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(18), PAD => DDR_DQ(18) ); \genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(19), PAD => DDR_DQ(19) ); \genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(1), PAD => DDR_DQ(1) ); \genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(20), PAD => DDR_DQ(20) ); \genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(21), PAD => DDR_DQ(21) ); \genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(22), PAD => DDR_DQ(22) ); \genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(23), PAD => DDR_DQ(23) ); \genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(24), PAD => DDR_DQ(24) ); \genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(25), PAD => DDR_DQ(25) ); \genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(26), PAD => DDR_DQ(26) ); \genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(27), PAD => DDR_DQ(27) ); \genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(28), PAD => DDR_DQ(28) ); \genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(29), PAD => DDR_DQ(29) ); \genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(2), PAD => DDR_DQ(2) ); \genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(30), PAD => DDR_DQ(30) ); \genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(31), PAD => DDR_DQ(31) ); \genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(3), PAD => DDR_DQ(3) ); \genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(4), PAD => DDR_DQ(4) ); \genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(5), PAD => DDR_DQ(5) ); \genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(6), PAD => DDR_DQ(6) ); \genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(7), PAD => DDR_DQ(7) ); \genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(8), PAD => DDR_DQ(8) ); \genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(9), PAD => DDR_DQ(9) ); \genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(0), PAD => DDR_DQS_n(0) ); \genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(1), PAD => DDR_DQS_n(1) ); \genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(2), PAD => DDR_DQS_n(2) ); \genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(3), PAD => DDR_DQS_n(3) ); \genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(0), PAD => DDR_DQS(0) ); \genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(1), PAD => DDR_DQS(1) ); \genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(2), PAD => DDR_DQS(2) ); \genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(3), PAD => DDR_DQS(3) ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[0]\ ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[0]\(1) ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[7]\(1) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[7]\(0) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[6]\(1) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[6]\(0) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[5]\(1) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[5]\(0) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[4]\(1) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[4]\(0) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[3]\(1) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[3]\(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[0]\(0) ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[2]\(1) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[2]\(0) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[1]\(1) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[1]\(0) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[7]\ ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[6]\ ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[5]\ ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[4]\ ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[3]\ ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[2]\ ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[1]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2018.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of inst : label is 4; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of inst : label is 4; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of inst : label is 32; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of inst : label is 64; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of inst : label is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of inst : label is 0; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of inst : label is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of inst : label is 0; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of inst : label is "TRUE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of inst : label is "FALSE"; attribute C_GP0_EN_MODIFIABLE_TXN : integer; attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1; attribute C_GP1_EN_MODIFIABLE_TXN : integer; attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of inst : label is "DIRECT"; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of inst : label is 54; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of inst : label is "clg400"; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of inst : label is "PRODUCTION"; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8; attribute C_USE_AXI_NONSECURE : integer; attribute C_USE_AXI_NONSECURE of inst : label is 0; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0; attribute C_USE_M_AXI_GP0 : integer; attribute C_USE_M_AXI_GP0 of inst : label is 1; attribute C_USE_M_AXI_GP1 : integer; attribute C_USE_M_AXI_GP1 of inst : label is 0; attribute C_USE_S_AXI_ACP : integer; attribute C_USE_S_AXI_ACP of inst : label is 0; attribute C_USE_S_AXI_GP0 : integer; attribute C_USE_S_AXI_GP0 of inst : label is 0; attribute C_USE_S_AXI_GP1 : integer; attribute C_USE_S_AXI_GP1 of inst : label is 0; attribute C_USE_S_AXI_HP0 : integer; attribute C_USE_S_AXI_HP0 of inst : label is 0; attribute C_USE_S_AXI_HP1 : integer; attribute C_USE_S_AXI_HP1 of inst : label is 0; attribute C_USE_S_AXI_HP2 : integer; attribute C_USE_S_AXI_HP2 of inst : label is 0; attribute C_USE_S_AXI_HP3 : integer; attribute C_USE_S_AXI_HP3 of inst : label is 0; attribute HW_HANDOFF : string; attribute HW_HANDOFF of inst : label is "design_1_processing_system7_0_0.hwdef"; attribute POWER : string; attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={50} usageRate={0.5} />/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N"; attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE"; attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N"; attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P"; attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N"; attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N"; attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT"; attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N"; attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"; attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"; attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N"; attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0"; attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"; attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW"; attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"; attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"; attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"; attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"; attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"; attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"; attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"; attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"; attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false"; attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"; attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT"; attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT"; attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR"; attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA"; attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM"; attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ"; attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P"; attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11"; attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N"; attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"; attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"; attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"; attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"; attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"; attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"; attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"; attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"; attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"; attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"; attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL"; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 port map ( CAN0_PHY_RX => '0', CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED, CAN1_PHY_RX => '0', CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED, Core0_nFIQ => '0', Core0_nIRQ => '0', Core1_nFIQ => '0', Core1_nIRQ => '0', DDR_ARB(3 downto 0) => B"0000", DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0), DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0), DDR_CAS_n => DDR_CAS_n, DDR_CKE => DDR_CKE, DDR_CS_n => DDR_CS_n, DDR_Clk => DDR_Clk, DDR_Clk_n => DDR_Clk_n, DDR_DM(3 downto 0) => DDR_DM(3 downto 0), DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0), DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0), DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0), DDR_DRSTB => DDR_DRSTB, DDR_ODT => DDR_ODT, DDR_RAS_n => DDR_RAS_n, DDR_VRN => DDR_VRN, DDR_VRP => DDR_VRP, DDR_WEB => DDR_WEB, DMA0_ACLK => '0', DMA0_DAREADY => '0', DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0), DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED, DMA0_DRLAST => '0', DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED, DMA0_DRTYPE(1 downto 0) => B"00", DMA0_DRVALID => '0', DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED, DMA1_ACLK => '0', DMA1_DAREADY => '0', DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0), DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED, DMA1_DRLAST => '0', DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED, DMA1_DRTYPE(1 downto 0) => B"00", DMA1_DRVALID => '0', DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED, DMA2_ACLK => '0', DMA2_DAREADY => '0', DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0), DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED, DMA2_DRLAST => '0', DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED, DMA2_DRTYPE(1 downto 0) => B"00", DMA2_DRVALID => '0', DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED, DMA3_ACLK => '0', DMA3_DAREADY => '0', DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0), DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED, DMA3_DRLAST => '0', DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED, DMA3_DRTYPE(1 downto 0) => B"00", DMA3_DRVALID => '0', DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED, ENET0_EXT_INTIN => '0', ENET0_GMII_COL => '0', ENET0_GMII_CRS => '0', ENET0_GMII_RXD(7 downto 0) => B"00000000", ENET0_GMII_RX_CLK => '0', ENET0_GMII_RX_DV => '0', ENET0_GMII_RX_ER => '0', ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0), ENET0_GMII_TX_CLK => '0', ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED, ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED, ENET0_MDIO_I => '0', ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED, ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED, ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED, ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED, ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED, ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED, ENET1_EXT_INTIN => '0', ENET1_GMII_COL => '0', ENET1_GMII_CRS => '0', ENET1_GMII_RXD(7 downto 0) => B"00000000", ENET1_GMII_RX_CLK => '0', ENET1_GMII_RX_DV => '0', ENET1_GMII_RX_ER => '0', ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0), ENET1_GMII_TX_CLK => '0', ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED, ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED, ENET1_MDIO_I => '0', ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED, ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED, ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED, ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED, ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED, ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED, EVENT_EVENTI => '0', EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED, EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0), EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0), FCLK_CLK0 => FCLK_CLK0, FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED, FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED, FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED, FCLK_CLKTRIG0_N => '0', FCLK_CLKTRIG1_N => '0', FCLK_CLKTRIG2_N => '0', FCLK_CLKTRIG3_N => '0', FCLK_RESET0_N => FCLK_RESET0_N, FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED, FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED, FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED, FPGA_IDLE_N => '0', FTMD_TRACEIN_ATID(3 downto 0) => B"0000", FTMD_TRACEIN_CLK => '0', FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000", FTMD_TRACEIN_VALID => '0', FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000", FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED, FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED, FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED, FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED, FTMT_F2P_TRIG_0 => '0', FTMT_F2P_TRIG_1 => '0', FTMT_F2P_TRIG_2 => '0', FTMT_F2P_TRIG_3 => '0', FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0), FTMT_P2F_TRIGACK_0 => '0', FTMT_P2F_TRIGACK_1 => '0', FTMT_P2F_TRIGACK_2 => '0', FTMT_P2F_TRIGACK_3 => '0', FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED, FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED, FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED, FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED, GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0), GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0), I2C0_SCL_I => '0', I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED, I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED, I2C0_SDA_I => '0', I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED, I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED, I2C1_SCL_I => '0', I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED, I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED, I2C1_SDA_I => '0', I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED, I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED, IRQ_F2P(0) => '0', IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED, IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED, IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED, IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED, IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED, IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED, IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED, IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED, IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED, IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED, IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED, IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED, IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED, IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED, IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED, IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED, IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED, IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED, IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED, IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED, IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED, IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED, IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED, IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED, IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED, IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED, IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED, IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED, IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED, MIO(53 downto 0) => MIO(53 downto 0), M_AXI_GP0_ACLK => M_AXI_GP0_ACLK, M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0), M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED, M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY, M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0), M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID, M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0), M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY, M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0), M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID, M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), M_AXI_GP0_BREADY => M_AXI_GP0_BREADY, M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), M_AXI_GP0_BVALID => M_AXI_GP0_BVALID, M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), M_AXI_GP0_RLAST => M_AXI_GP0_RLAST, M_AXI_GP0_RREADY => M_AXI_GP0_RREADY, M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), M_AXI_GP0_RVALID => M_AXI_GP0_RVALID, M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), M_AXI_GP0_WLAST => M_AXI_GP0_WLAST, M_AXI_GP0_WREADY => M_AXI_GP0_WREADY, M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), M_AXI_GP0_WVALID => M_AXI_GP0_WVALID, M_AXI_GP1_ACLK => '0', M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0), M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0), M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0), M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED, M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0), M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0), M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0), M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0), M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0), M_AXI_GP1_ARREADY => '0', M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0), M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED, M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0), M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0), M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0), M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0), M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0), M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0), M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0), M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0), M_AXI_GP1_AWREADY => '0', M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0), M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED, M_AXI_GP1_BID(11 downto 0) => B"000000000000", M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED, M_AXI_GP1_BRESP(1 downto 0) => B"00", M_AXI_GP1_BVALID => '0', M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000", M_AXI_GP1_RID(11 downto 0) => B"000000000000", M_AXI_GP1_RLAST => '0', M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED, M_AXI_GP1_RRESP(1 downto 0) => B"00", M_AXI_GP1_RVALID => '0', M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0), M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0), M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED, M_AXI_GP1_WREADY => '0', M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0), M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED, PJTAG_TCK => '0', PJTAG_TDI => '0', PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED, PJTAG_TMS => '0', PS_CLK => PS_CLK, PS_PORB => PS_PORB, PS_SRSTB => PS_SRSTB, SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED, SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0), SDIO0_CDN => '0', SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED, SDIO0_CLK_FB => '0', SDIO0_CMD_I => '0', SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED, SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED, SDIO0_DATA_I(3 downto 0) => B"0000", SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0), SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0), SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED, SDIO0_WP => '0', SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED, SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0), SDIO1_CDN => '0', SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED, SDIO1_CLK_FB => '0', SDIO1_CMD_I => '0', SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED, SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED, SDIO1_DATA_I(3 downto 0) => B"0000", SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0), SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0), SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED, SDIO1_WP => '0', SPI0_MISO_I => '0', SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED, SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED, SPI0_MOSI_I => '0', SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED, SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED, SPI0_SCLK_I => '0', SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED, SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED, SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED, SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED, SPI0_SS_I => '0', SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED, SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED, SPI1_MISO_I => '0', SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED, SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED, SPI1_MOSI_I => '0', SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED, SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED, SPI1_SCLK_I => '0', SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED, SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED, SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED, SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED, SPI1_SS_I => '0', SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED, SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED, SRAM_INTIN => '0', S_AXI_ACP_ACLK => '0', S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_ACP_ARBURST(1 downto 0) => B"00", S_AXI_ACP_ARCACHE(3 downto 0) => B"0000", S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED, S_AXI_ACP_ARID(2 downto 0) => B"000", S_AXI_ACP_ARLEN(3 downto 0) => B"0000", S_AXI_ACP_ARLOCK(1 downto 0) => B"00", S_AXI_ACP_ARPROT(2 downto 0) => B"000", S_AXI_ACP_ARQOS(3 downto 0) => B"0000", S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED, S_AXI_ACP_ARSIZE(2 downto 0) => B"000", S_AXI_ACP_ARUSER(4 downto 0) => B"00000", S_AXI_ACP_ARVALID => '0', S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_ACP_AWBURST(1 downto 0) => B"00", S_AXI_ACP_AWCACHE(3 downto 0) => B"0000", S_AXI_ACP_AWID(2 downto 0) => B"000", S_AXI_ACP_AWLEN(3 downto 0) => B"0000", S_AXI_ACP_AWLOCK(1 downto 0) => B"00", S_AXI_ACP_AWPROT(2 downto 0) => B"000", S_AXI_ACP_AWQOS(3 downto 0) => B"0000", S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED, S_AXI_ACP_AWSIZE(2 downto 0) => B"000", S_AXI_ACP_AWUSER(4 downto 0) => B"00000", S_AXI_ACP_AWVALID => '0', S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0), S_AXI_ACP_BREADY => '0', S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED, S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0), S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0), S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED, S_AXI_ACP_RREADY => '0', S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED, S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_ACP_WID(2 downto 0) => B"000", S_AXI_ACP_WLAST => '0', S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED, S_AXI_ACP_WSTRB(7 downto 0) => B"00000000", S_AXI_ACP_WVALID => '0', S_AXI_GP0_ACLK => '0', S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_ARBURST(1 downto 0) => B"00", S_AXI_GP0_ARCACHE(3 downto 0) => B"0000", S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED, S_AXI_GP0_ARID(5 downto 0) => B"000000", S_AXI_GP0_ARLEN(3 downto 0) => B"0000", S_AXI_GP0_ARLOCK(1 downto 0) => B"00", S_AXI_GP0_ARPROT(2 downto 0) => B"000", S_AXI_GP0_ARQOS(3 downto 0) => B"0000", S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED, S_AXI_GP0_ARSIZE(2 downto 0) => B"000", S_AXI_GP0_ARVALID => '0', S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_AWBURST(1 downto 0) => B"00", S_AXI_GP0_AWCACHE(3 downto 0) => B"0000", S_AXI_GP0_AWID(5 downto 0) => B"000000", S_AXI_GP0_AWLEN(3 downto 0) => B"0000", S_AXI_GP0_AWLOCK(1 downto 0) => B"00", S_AXI_GP0_AWPROT(2 downto 0) => B"000", S_AXI_GP0_AWQOS(3 downto 0) => B"0000", S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED, S_AXI_GP0_AWSIZE(2 downto 0) => B"000", S_AXI_GP0_AWVALID => '0', S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0), S_AXI_GP0_BREADY => '0', S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED, S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0), S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED, S_AXI_GP0_RREADY => '0', S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED, S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_WID(5 downto 0) => B"000000", S_AXI_GP0_WLAST => '0', S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED, S_AXI_GP0_WSTRB(3 downto 0) => B"0000", S_AXI_GP0_WVALID => '0', S_AXI_GP1_ACLK => '0', S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_ARBURST(1 downto 0) => B"00", S_AXI_GP1_ARCACHE(3 downto 0) => B"0000", S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED, S_AXI_GP1_ARID(5 downto 0) => B"000000", S_AXI_GP1_ARLEN(3 downto 0) => B"0000", S_AXI_GP1_ARLOCK(1 downto 0) => B"00", S_AXI_GP1_ARPROT(2 downto 0) => B"000", S_AXI_GP1_ARQOS(3 downto 0) => B"0000", S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED, S_AXI_GP1_ARSIZE(2 downto 0) => B"000", S_AXI_GP1_ARVALID => '0', S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_AWBURST(1 downto 0) => B"00", S_AXI_GP1_AWCACHE(3 downto 0) => B"0000", S_AXI_GP1_AWID(5 downto 0) => B"000000", S_AXI_GP1_AWLEN(3 downto 0) => B"0000", S_AXI_GP1_AWLOCK(1 downto 0) => B"00", S_AXI_GP1_AWPROT(2 downto 0) => B"000", S_AXI_GP1_AWQOS(3 downto 0) => B"0000", S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED, S_AXI_GP1_AWSIZE(2 downto 0) => B"000", S_AXI_GP1_AWVALID => '0', S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0), S_AXI_GP1_BREADY => '0', S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED, S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0), S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED, S_AXI_GP1_RREADY => '0', S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED, S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_WID(5 downto 0) => B"000000", S_AXI_GP1_WLAST => '0', S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED, S_AXI_GP1_WSTRB(3 downto 0) => B"0000", S_AXI_GP1_WVALID => '0', S_AXI_HP0_ACLK => '0', S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP0_ARBURST(1 downto 0) => B"00", S_AXI_HP0_ARCACHE(3 downto 0) => B"0000", S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED, S_AXI_HP0_ARID(5 downto 0) => B"000000", S_AXI_HP0_ARLEN(3 downto 0) => B"0000", S_AXI_HP0_ARLOCK(1 downto 0) => B"00", S_AXI_HP0_ARPROT(2 downto 0) => B"000", S_AXI_HP0_ARQOS(3 downto 0) => B"0000", S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED, S_AXI_HP0_ARSIZE(2 downto 0) => B"000", S_AXI_HP0_ARVALID => '0', S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP0_AWBURST(1 downto 0) => B"00", S_AXI_HP0_AWCACHE(3 downto 0) => B"0000", S_AXI_HP0_AWID(5 downto 0) => B"000000", S_AXI_HP0_AWLEN(3 downto 0) => B"0000", S_AXI_HP0_AWLOCK(1 downto 0) => B"00", S_AXI_HP0_AWPROT(2 downto 0) => B"000", S_AXI_HP0_AWQOS(3 downto 0) => B"0000", S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED, S_AXI_HP0_AWSIZE(2 downto 0) => B"000", S_AXI_HP0_AWVALID => '0', S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0), S_AXI_HP0_BREADY => '0', S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED, S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP0_RDISSUECAP1_EN => '0', S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0), S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED, S_AXI_HP0_RREADY => '0', S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED, S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP0_WID(5 downto 0) => B"000000", S_AXI_HP0_WLAST => '0', S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED, S_AXI_HP0_WRISSUECAP1_EN => '0', S_AXI_HP0_WSTRB(7 downto 0) => B"00000000", S_AXI_HP0_WVALID => '0', S_AXI_HP1_ACLK => '0', S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP1_ARBURST(1 downto 0) => B"00", S_AXI_HP1_ARCACHE(3 downto 0) => B"0000", S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED, S_AXI_HP1_ARID(5 downto 0) => B"000000", S_AXI_HP1_ARLEN(3 downto 0) => B"0000", S_AXI_HP1_ARLOCK(1 downto 0) => B"00", S_AXI_HP1_ARPROT(2 downto 0) => B"000", S_AXI_HP1_ARQOS(3 downto 0) => B"0000", S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED, S_AXI_HP1_ARSIZE(2 downto 0) => B"000", S_AXI_HP1_ARVALID => '0', S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP1_AWBURST(1 downto 0) => B"00", S_AXI_HP1_AWCACHE(3 downto 0) => B"0000", S_AXI_HP1_AWID(5 downto 0) => B"000000", S_AXI_HP1_AWLEN(3 downto 0) => B"0000", S_AXI_HP1_AWLOCK(1 downto 0) => B"00", S_AXI_HP1_AWPROT(2 downto 0) => B"000", S_AXI_HP1_AWQOS(3 downto 0) => B"0000", S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED, S_AXI_HP1_AWSIZE(2 downto 0) => B"000", S_AXI_HP1_AWVALID => '0', S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0), S_AXI_HP1_BREADY => '0', S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED, S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP1_RDISSUECAP1_EN => '0', S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0), S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED, S_AXI_HP1_RREADY => '0', S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED, S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP1_WID(5 downto 0) => B"000000", S_AXI_HP1_WLAST => '0', S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED, S_AXI_HP1_WRISSUECAP1_EN => '0', S_AXI_HP1_WSTRB(7 downto 0) => B"00000000", S_AXI_HP1_WVALID => '0', S_AXI_HP2_ACLK => '0', S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP2_ARBURST(1 downto 0) => B"00", S_AXI_HP2_ARCACHE(3 downto 0) => B"0000", S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED, S_AXI_HP2_ARID(5 downto 0) => B"000000", S_AXI_HP2_ARLEN(3 downto 0) => B"0000", S_AXI_HP2_ARLOCK(1 downto 0) => B"00", S_AXI_HP2_ARPROT(2 downto 0) => B"000", S_AXI_HP2_ARQOS(3 downto 0) => B"0000", S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED, S_AXI_HP2_ARSIZE(2 downto 0) => B"000", S_AXI_HP2_ARVALID => '0', S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP2_AWBURST(1 downto 0) => B"00", S_AXI_HP2_AWCACHE(3 downto 0) => B"0000", S_AXI_HP2_AWID(5 downto 0) => B"000000", S_AXI_HP2_AWLEN(3 downto 0) => B"0000", S_AXI_HP2_AWLOCK(1 downto 0) => B"00", S_AXI_HP2_AWPROT(2 downto 0) => B"000", S_AXI_HP2_AWQOS(3 downto 0) => B"0000", S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED, S_AXI_HP2_AWSIZE(2 downto 0) => B"000", S_AXI_HP2_AWVALID => '0', S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0), S_AXI_HP2_BREADY => '0', S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED, S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP2_RDISSUECAP1_EN => '0', S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0), S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED, S_AXI_HP2_RREADY => '0', S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED, S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP2_WID(5 downto 0) => B"000000", S_AXI_HP2_WLAST => '0', S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED, S_AXI_HP2_WRISSUECAP1_EN => '0', S_AXI_HP2_WSTRB(7 downto 0) => B"00000000", S_AXI_HP2_WVALID => '0', S_AXI_HP3_ACLK => '0', S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP3_ARBURST(1 downto 0) => B"00", S_AXI_HP3_ARCACHE(3 downto 0) => B"0000", S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED, S_AXI_HP3_ARID(5 downto 0) => B"000000", S_AXI_HP3_ARLEN(3 downto 0) => B"0000", S_AXI_HP3_ARLOCK(1 downto 0) => B"00", S_AXI_HP3_ARPROT(2 downto 0) => B"000", S_AXI_HP3_ARQOS(3 downto 0) => B"0000", S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED, S_AXI_HP3_ARSIZE(2 downto 0) => B"000", S_AXI_HP3_ARVALID => '0', S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP3_AWBURST(1 downto 0) => B"00", S_AXI_HP3_AWCACHE(3 downto 0) => B"0000", S_AXI_HP3_AWID(5 downto 0) => B"000000", S_AXI_HP3_AWLEN(3 downto 0) => B"0000", S_AXI_HP3_AWLOCK(1 downto 0) => B"00", S_AXI_HP3_AWPROT(2 downto 0) => B"000", S_AXI_HP3_AWQOS(3 downto 0) => B"0000", S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED, S_AXI_HP3_AWSIZE(2 downto 0) => B"000", S_AXI_HP3_AWVALID => '0', S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0), S_AXI_HP3_BREADY => '0', S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED, S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP3_RDISSUECAP1_EN => '0', S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0), S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED, S_AXI_HP3_RREADY => '0', S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED, S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP3_WID(5 downto 0) => B"000000", S_AXI_HP3_WLAST => '0', S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED, S_AXI_HP3_WRISSUECAP1_EN => '0', S_AXI_HP3_WSTRB(7 downto 0) => B"00000000", S_AXI_HP3_WVALID => '0', TRACE_CLK => '0', TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED, TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED, TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0), TTC0_CLK0_IN => '0', TTC0_CLK1_IN => '0', TTC0_CLK2_IN => '0', TTC0_WAVE0_OUT => NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED, TTC0_WAVE1_OUT => NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED, TTC0_WAVE2_OUT => NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED, TTC1_CLK0_IN => '0', TTC1_CLK1_IN => '0', TTC1_CLK2_IN => '0', TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED, TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED, TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED, UART0_CTSN => '0', UART0_DCDN => '0', UART0_DSRN => '0', UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED, UART0_RIN => '0', UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED, UART0_RX => '1', UART0_TX => NLW_inst_UART0_TX_UNCONNECTED, UART1_CTSN => '0', UART1_DCDN => '0', UART1_DSRN => '0', UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED, UART1_RIN => '0', UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED, UART1_RX => '1', UART1_TX => NLW_inst_UART1_TX_UNCONNECTED, USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT, USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT, USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0), USB1_VBUS_PWRFAULT => '0', USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED, WDT_CLK_IN => '0', WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED ); end STRUCTURE;

-- NEED RESULT: ARCH00687: Allocators with dynamic composite subtype indication passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00687 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 7.3.6 (2) -- 7.3.6 (9) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00687) -- ENT00687_Test_Bench(ARCH00687_Test_Bench) -- -- REVISION HISTORY: -- -- 08-SEP-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.test_report ; architecture ARCH00687 of E00000 is procedure p1 ( constant lowb : integer := 1 ; constant highb : integer := 10 ; constant lowb_i2 : integer := 0 ; constant highb_i2 : integer := 1000 ; constant lowb_p : integer := -100 ; constant highb_p : integer := 1000 ; constant lowb_r : real := 0.0 ; constant highb_r : real := 1000.0 ; constant lowb_r2 : real := 8.0 ; constant highb_r2 : real := 80.0 -- ) is -- -- assertion: c_xxxxx_2 >= c_xxxxx_1 -- enumeration types -- predefined -- boolean constant c_boolean_1 : boolean := false ; constant c_boolean_2 : boolean := true ; -- type boolean_vector is array (integer range <>) of boolean ; subtype boolean_vector_range1 is integer range lowb to highb ; subtype st_boolean_vector is boolean_vector (boolean_vector_range1) ; constant c_st_boolean_vector_1 : st_boolean_vector := (others => c_boolean_1) ; constant c_st_boolean_vector_2 : st_boolean_vector := (others => c_boolean_2) ; -- -- bit constant c_bit_1 : bit := '0' ; constant c_bit_2 : bit := '1' ; -- constant c_bit_vector_1 : bit_vector := B"0000" ; constant c_bit_vector_2 : bit_vector := B"1111" ; subtype bit_vector_range1 is integer range lowb to highb ; subtype st_bit_vector is bit_vector (bit_vector_range1) ; constant c_st_bit_vector_1 : st_bit_vector := (others => c_bit_1) ; constant c_st_bit_vector_2 : st_bit_vector := (others => c_bit_2) ; -- severity_level constant c_severity_level_1 : severity_level := NOTE ; constant c_severity_level_2 : severity_level := WARNING ; -- type severity_level_vector is array (integer range <>) of severity_level ; subtype severity_level_vector_range1 is integer range lowb to highb ; subtype st_severity_level_vector is severity_level_vector (severity_level_vector_range1) ; constant c_st_severity_level_vector_1 : st_severity_level_vector := (others => c_severity_level_1) ; constant c_st_severity_level_vector_2 : st_severity_level_vector := (others => c_severity_level_2) ; -- -- character constant c_character_1 : character := 'A' ; constant c_character_2 : character := 'a' ; -- constant c_string_1 : string := "ABC0000" ; constant c_string_2 : string := "ABC1111" ; subtype string_range1 is integer range lowb to highb ; subtype st_string is string (string_range1) ; constant c_st_string_1 : st_string := (others => c_character_1) ; constant c_st_string_2 : st_string := (others => c_character_2) ; -- user defined enumeration type t_enum1 is (en1, en2, en3, en4) ; constant c_t_enum1_1 : t_enum1 := en1 ; constant c_t_enum1_2 : t_enum1 := en2 ; subtype st_enum1 is t_enum1 range en4 downto en1 ; constant c_st_enum1_1 : st_enum1 := en1 ; constant c_st_enum1_2 : st_enum1 := en2 ; -- type enum1_vector is array (integer range <>) of st_enum1 ; subtype enum1_vector_range1 is integer range lowb to highb ; subtype st_enum1_vector is enum1_vector (enum1_vector_range1) ; constant c_st_enum1_vector_1 : st_enum1_vector := (others => c_st_enum1_1) ; constant c_st_enum1_vector_2 : st_enum1_vector := (others => c_st_enum1_2) ; -- integer types -- predefined constant c_integer_1 : integer := lowb ; constant c_integer_2 : integer := highb ; -- type integer_vector is array (integer range <>) of integer ; subtype integer_vector_range1 is integer range lowb to highb ; subtype st_integer_vector is integer_vector (integer_vector_range1) ; constant c_st_integer_vector_1 : st_integer_vector := (others => c_integer_1) ; constant c_st_integer_vector_2 : st_integer_vector := (others => c_integer_2) ; -- -- user defined integer type type t_int1 is range 0 to 100 ; constant c_t_int1_1 : t_int1 := 0 ; constant c_t_int1_2 : t_int1 := 10 ; subtype st_int1 is t_int1 range 8 to 60 ; constant c_st_int1_1 : st_int1 := 8 ; constant c_st_int1_2 : st_int1 := 9 ; -- type int1_vector is array (integer range <>) of st_int1 ; subtype int1_vector_range1 is integer range lowb to highb ; subtype st_int1_vector is int1_vector (int1_vector_range1) ; constant c_st_int1_vector_1 : st_int1_vector := (others => c_st_int1_1) ; constant c_st_int1_vector_2 : st_int1_vector := (others => c_st_int1_2) ; -- -- physical types -- predefined constant c_time_1 : time := 1 ns ; constant c_time_2 : time := 2 ns ; -- type time_vector is array (integer range <>) of time ; subtype time_vector_range1 is integer range lowb to highb ; subtype st_time_vector is time_vector (time_vector_range1) ; constant c_st_time_vector_1 : st_time_vector := (others => c_time_1) ; constant c_st_time_vector_2 : st_time_vector := (others => c_time_2) ; -- -- user defined physical type type t_phys1 is range -100 to 1000 units phys1_1 ; phys1_2 = 10 phys1_1 ; phys1_3 = 10 phys1_2 ; phys1_4 = 10 phys1_3 ; phys1_5 = 10 phys1_4 ; end units ; -- constant c_t_phys1_1 : t_phys1 := phys1_1 ; constant c_t_phys1_2 : t_phys1 := phys1_2 ; subtype st_phys1 is t_phys1 range phys1_2 to phys1_4 ; constant c_st_phys1_1 : st_phys1 := phys1_2 ; constant c_st_phys1_2 : st_phys1 := phys1_3 ; -- type phys1_vector is array (integer range <>) of st_phys1 ; subtype phys1_vector_range1 is integer range lowb to highb ; subtype st_phys1_vector is phys1_vector (phys1_vector_range1) ; constant c_st_phys1_vector_1 : st_phys1_vector := (others => c_st_phys1_1) ; constant c_st_phys1_vector_2 : st_phys1_vector := (others => c_st_phys1_2) ; -- -- -- floating point types -- predefined constant c_real_1 : real := 0.0 ; constant c_real_2 : real := 1.0 ; -- type real_vector is array (integer range <>) of real ; subtype real_vector_range1 is integer range lowb to highb ; subtype st_real_vector is real_vector (real_vector_range1) ; constant c_st_real_vector_1 : st_real_vector := (others => c_real_1) ; constant c_st_real_vector_2 : st_real_vector := (others => c_real_2) ; -- -- user defined floating type type t_real1 is range 0.0 to 1000.0 ; constant c_t_real1_1 : t_real1 := 0.0 ; constant c_t_real1_2 : t_real1 := 1.0 ; subtype st_real1 is t_real1 range 8.0 to 80.0 ; constant c_st_real1_1 : st_real1 := 8.0 ; constant c_st_real1_2 : st_real1 := 9.0 ; -- type real1_vector is array (integer range <>) of st_real1 ; subtype real1_vector_range1 is integer range lowb to highb ; subtype st_real1_vector is real1_vector (real1_vector_range1) ; constant c_st_real1_vector_1 : st_real1_vector := (others => c_st_real1_1) ; constant c_st_real1_vector_2 : st_real1_vector := (others => c_st_real1_2) ; -- composite types -- -- simple record type t_rec1 is record f1 : integer range lowb_i2 to highb_i2 ; f2 : time ; f3 : boolean ; f4 : real ; end record ; constant c_t_rec1_1 : t_rec1 := (c_integer_1, c_time_1, c_boolean_1, c_real_1) ; constant c_t_rec1_2 : t_rec1 := (c_integer_2, c_time_2, c_boolean_2, c_real_2) ; subtype st_rec1 is t_rec1 ; constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ; constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ; -- type rec1_vector is array (integer range <>) of st_rec1 ; subtype rec1_vector_range1 is integer range lowb to highb ; subtype st_rec1_vector is rec1_vector (rec1_vector_range1) ; constant c_st_rec1_vector_1 : st_rec1_vector := (others => c_st_rec1_1) ; constant c_st_rec1_vector_2 : st_rec1_vector := (others => c_st_rec1_2) ; -- -- -- more complex record type t_rec2 is record f1 : boolean ; f2 : st_rec1 ; f3 : time ; end record ; constant c_t_rec2_1 : t_rec2 := (c_boolean_1, c_st_rec1_1, c_time_1) ; constant c_t_rec2_2 : t_rec2 := (c_boolean_2, c_st_rec1_2, c_time_2) ; subtype st_rec2 is t_rec2 ; constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ; constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ; -- type rec2_vector is array (integer range <>) of st_rec2 ; subtype rec2_vector_range1 is integer range lowb to highb ; subtype st_rec2_vector is rec2_vector (rec2_vector_range1) ; constant c_st_rec2_vector_1 : st_rec2_vector := (others => c_st_rec2_1) ; constant c_st_rec2_vector_2 : st_rec2_vector := (others => c_st_rec2_2) ; -- -- simple array type t_arr1 is array (integer range <>) of st_int1 ; subtype t_arr1_range1 is integer range lowb to highb ; subtype st_arr1 is t_arr1 (t_arr1_range1) ; constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ; constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ; constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ; constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ; -- type arr1_vector is array (integer range <>) of st_arr1 ; subtype arr1_vector_range1 is integer range lowb to highb ; subtype st_arr1_vector is arr1_vector (arr1_vector_range1) ; constant c_st_arr1_vector_1 : st_arr1_vector := (others => c_st_arr1_1) ; constant c_st_arr1_vector_2 : st_arr1_vector := (others => c_st_arr1_2) ; -- more complex array type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ; subtype t_arr2_range1 is integer range lowb to highb ; subtype t_arr2_range2 is boolean range false to true ; subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2); constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ; constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ; constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ; constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ; -- type arr2_vector is array (integer range <>) of st_arr2 ; subtype arr2_vector_range1 is integer range lowb to highb ; subtype st_arr2_vector is arr2_vector (arr2_vector_range1) ; constant c_st_arr2_vector_1 : st_arr2_vector := (others => c_st_arr2_1) ; constant c_st_arr2_vector_2 : st_arr2_vector := (others => c_st_arr2_2) ; -- -- -- most complex record type t_rec3 is record f1 : boolean ; f2 : st_rec2 ; f3 : st_arr2 ; end record ; constant c_t_rec3_1 : t_rec3 := (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ; constant c_t_rec3_2 : t_rec3 := (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ; subtype st_rec3 is t_rec3 ; constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ; constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ; -- type rec3_vector is array (integer range <>) of st_rec3 ; subtype rec3_vector_range1 is integer range lowb to highb ; subtype st_rec3_vector is rec3_vector (rec3_vector_range1) ; constant c_st_rec3_vector_1 : st_rec3_vector := (others => c_st_rec3_1) ; constant c_st_rec3_vector_2 : st_rec3_vector := (others => c_st_rec3_2) ; -- -- most complex array type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ; subtype t_arr3_range1 is integer range lowb to highb ; subtype t_arr3_range2 is boolean range true downto false ; subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ; constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ; constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ; constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ; constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ; -- type arr3_vector is array (integer range <>) of st_arr3 ; subtype arr3_vector_range1 is integer range lowb to highb ; subtype st_arr3_vector is arr3_vector (arr3_vector_range1) ; constant c_st_arr3_vector_1 : st_arr3_vector := (others => c_st_arr3_1) ; constant c_st_arr3_vector_2 : st_arr3_vector := (others => c_st_arr3_2) ; -- constant d_boolean : boolean := boolean'left ; constant d_bit : bit := bit'left ; constant d_severity_level : severity_level := severity_level'left ; constant d_character : character := character'left ; constant d_t_enum1 : t_enum1 := t_enum1'left ; constant d_st_enum1 : st_enum1 := st_enum1'left ; constant d_integer : integer := integer'left ; constant d_t_int1 : t_int1 := t_int1'left ; constant d_st_int1 : st_int1 := st_int1'left ; constant d_time : time := time'left ; constant d_t_phys1 : t_phys1 := t_phys1'left ; constant d_st_phys1 : st_phys1 := st_phys1'left ; constant d_real : real := real'left ; constant d_t_real1 : t_real1 := t_real1'left ; constant d_st_real1 : st_real1 := st_real1'left ; constant d_st_bit_vector : st_bit_vector := (others => bit'left) ; constant d_st_string : st_string := (others => character'left) ; constant d_t_rec1 : t_rec1 := (lowb_i2, time'left, boolean'left, real'left) ; constant d_st_rec1 : st_rec1 := (lowb_i2, time'left, boolean'left, real'left) ; constant d_t_rec2 : t_rec2 := (boolean'left, d_st_rec1, time'left) ; constant d_st_rec2 : st_rec2 := (boolean'left, d_st_rec1, time'left) ; constant d_st_arr1 : st_arr1 := (others => st_int1'left) ; constant d_st_arr2 : st_arr2 := (others => (others => d_st_arr1) ) ; constant d_t_rec3 : t_rec3 := (boolean'left, d_st_rec2, d_st_arr2) ; constant d_st_rec3 : st_rec3 := (boolean'left, d_st_rec2, d_st_arr2) ; constant d_st_arr3 : st_arr3 := (others => (others => d_st_rec3) ) ; -- enumeration types -- predefined -- boolean function bf_boolean(to_resolve : boolean_vector) return boolean is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return boolean'left ; else for i in to_resolve'range loop sum := sum + boolean'pos(to_resolve(i)) ; end loop ; return boolean'val(integer'pos(sum) mod (boolean'pos(boolean'high) + 1)) ; end if ; end bf_boolean ; -- -- -- bit function bf_bit(to_resolve : bit_vector) return bit is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return bit'left ; else for i in to_resolve'range loop sum := sum + bit'pos(to_resolve(i)) ; end loop ; return bit'val(integer'pos(sum) mod (bit'pos(bit'high) + 1)) ; end if ; end bf_bit ; -- -- severity_level function bf_severity_level(to_resolve : severity_level_vector) return severity_level is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return severity_level'left ; else for i in to_resolve'range loop sum := sum + severity_level'pos(to_resolve(i)) ; end loop ; return severity_level'val(integer'pos(sum) mod (severity_level'pos(severity_level'high) + 1)) ; end if ; end bf_severity_level ; -- -- character function bf_character(to_resolve : string) return character is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return character'left ; else for i in to_resolve'range loop sum := sum + character'pos(to_resolve(i)) ; end loop ; return character'val(integer'pos(sum) mod (character'pos(character'high) + 1)) ; end if ; end bf_character ; -- -- -- user defined enumeration function bf_enum1(to_resolve : enum1_vector) return st_enum1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return st_enum1'left ; else for i in to_resolve'range loop sum := sum + t_enum1'pos(to_resolve(i)) ; end loop ; return t_enum1'val(integer'pos(sum) mod (t_enum1'pos(t_enum1'high) + 1)) ; end if ; end bf_enum1 ; -- -- -- integer types -- predefined function bf_integer(to_resolve : integer_vector) return integer is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return integer'left ; else for i in to_resolve'range loop sum := sum + integer'pos(to_resolve(i)) ; end loop ; return sum ; end if ; end bf_integer ; -- -- -- user defined integer type function bf_int1(to_resolve : int1_vector) return st_int1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return st_int1'left ; else for i in to_resolve'range loop sum := sum + t_int1'pos(to_resolve(i)) ; end loop ; return t_int1'val(integer'pos(sum) mod (t_int1'pos(t_int1'high) + 1)) ; end if ; end bf_int1 ; -- -- -- physical types -- predefined function bf_time(to_resolve : time_vector) return time is variable sum : time := 0 fs; begin if to_resolve'length = 0 then return time'left ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_time ; -- -- -- user defined physical type function bf_phys1(to_resolve : phys1_vector) return st_phys1 is variable sum : integer := 0 ; begin if to_resolve'length = 0 then return c_st_phys1_1 ; else for i in to_resolve'range loop sum := sum + t_phys1'pos(to_resolve(i)) ; end loop ; return t_phys1'val(integer'pos(sum) mod (t_phys1'pos(t_phys1'high) + 1)) ; end if ; end bf_phys1 ; -- -- -- floating point types -- predefined function bf_real(to_resolve : real_vector) return real is variable sum : real := 0.0 ; begin if to_resolve'length = 0 then return real'left ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_real ; -- -- -- user defined floating type function bf_real1(to_resolve : real1_vector) return st_real1 is variable sum : t_real1 := 0.0 ; begin if to_resolve'length = 0 then return c_st_real1_1 ; else for i in to_resolve'range loop sum := sum + to_resolve(i) ; end loop ; return sum ; end if ; end bf_real1 ; -- -- -- composite types -- -- simple record function bf_rec1(to_resolve : rec1_vector) return st_rec1 is variable f1array : integer_vector (to_resolve'range) ; variable f2array : time_vector (to_resolve'range) ; variable f3array : boolean_vector (to_resolve'range) ; variable f4array : real_vector (to_resolve'range) ; variable result : st_rec1 ; begin if to_resolve'length = 0 then return c_st_rec1_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; f4array(i) := to_resolve(i).f4 ; end loop ; result.f1 := bf_integer(f1array) ; result.f2 := bf_time(f2array) ; result.f3 := bf_boolean(f3array) ; result.f4 := bf_real(f4array) ; return result ; end if ; end bf_rec1 ; -- -- -- more complex record function bf_rec2(to_resolve : rec2_vector) return st_rec2 is variable f1array : boolean_vector (to_resolve'range) ; variable f2array : rec1_vector (to_resolve'range) ; variable f3array : time_vector (to_resolve'range) ; variable result : st_rec2 ; begin if to_resolve'length = 0 then return c_st_rec2_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; end loop ; result.f1 := bf_boolean(f1array) ; result.f2 := bf_rec1(f2array) ; result.f3 := bf_time(f3array) ; return result ; end if ; end bf_rec2 ; -- -- -- simple array function bf_arr1(to_resolve : arr1_vector) return st_arr1 is variable temp : int1_vector (to_resolve'range) ; variable result : st_arr1 ; begin if to_resolve'length = 0 then return c_st_arr1_1 ; else for i in st_arr1'range loop for j in to_resolve'range(1) loop temp(j) := to_resolve(j)(i) ; end loop; result(i) := bf_int1(temp) ; end loop ; return result ; end if ; end bf_arr1 ; -- -- -- more complex array function bf_arr2(to_resolve : arr2_vector) return st_arr2 is variable temp : arr1_vector (to_resolve'range) ; variable result : st_arr2 ; begin if to_resolve'length = 0 then return c_st_arr2_1 ; else for i in st_arr2'range(1) loop for j in st_arr2'range(2) loop for k in to_resolve'range loop temp(k) := to_resolve(k)(i,j) ; end loop ; result(i, j) := bf_arr1(temp) ; end loop ; end loop ; return result ; end if ; end bf_arr2 ; -- -- -- most complex record function bf_rec3(to_resolve : rec3_vector) return st_rec3 is variable f1array : boolean_vector (to_resolve'range) ; variable f2array : rec2_vector (to_resolve'range) ; variable f3array : arr2_vector (to_resolve'range) ; variable result : st_rec3 ; begin if to_resolve'length = 0 then return c_st_rec3_1 ; else for i in to_resolve'range loop f1array(i) := to_resolve(i).f1 ; f2array(i) := to_resolve(i).f2 ; f3array(i) := to_resolve(i).f3 ; end loop ; result.f1 := bf_boolean(f1array) ; result.f2 := bf_rec2(f2array) ; result.f3 := bf_arr2(f3array) ; return result ; end if ; end bf_rec3 ; -- -- -- most complex array function bf_arr3(to_resolve : arr3_vector) return st_arr3 is variable temp : rec3_vector (to_resolve'range) ; variable result : st_arr3 ; begin if to_resolve'length = 0 then return c_st_arr3_1 ; else for i in st_arr3'range(1) loop for j in st_arr3'range(2) loop for k in to_resolve'range loop temp(k) := to_resolve(k)(i,j) ; end loop ; result(i, j) := bf_rec3(temp) ; end loop ; end loop ; return result ; end if ; end bf_arr3 ; -- variable correct : boolean := true ; type a_bit_vector is access bit_vector ; variable va_bit_vector_1, va_bit_vector_2 : a_bit_vector := new st_bit_vector ; type a_string is access string ; variable va_string_1, va_string_2 : a_string := new st_string ; type a_t_rec1 is access t_rec1 ; variable va_t_rec1_1, va_t_rec1_2 : a_t_rec1 := new st_rec1 ; type a_st_rec1 is access st_rec1 ; variable va_st_rec1_1, va_st_rec1_2 : a_st_rec1 := new st_rec1 ; type a_t_rec2 is access t_rec2 ; variable va_t_rec2_1, va_t_rec2_2 : a_t_rec2 := new st_rec2 ; type a_st_rec2 is access st_rec2 ; variable va_st_rec2_1, va_st_rec2_2 : a_st_rec2 := new st_rec2 ; type a_t_rec3 is access t_rec3 ; variable va_t_rec3_1, va_t_rec3_2 : a_t_rec3 := new st_rec3 ; type a_st_rec3 is access st_rec3 ; variable va_st_rec3_1, va_st_rec3_2 : a_st_rec3 := new st_rec3 ; type a_t_arr1 is access t_arr1 ; variable va_t_arr1_1, va_t_arr1_2 : a_t_arr1 := new st_arr1 ; type a_st_arr1 is access st_arr1 ; variable va_st_arr1_1, va_st_arr1_2 : a_st_arr1 := new st_arr1 ; type a_t_arr2 is access t_arr2 ; variable va_t_arr2_1, va_t_arr2_2 : a_t_arr2 := new st_arr2 ; type a_st_arr2 is access st_arr2 ; variable va_st_arr2_1, va_st_arr2_2 : a_st_arr2 := new st_arr2 ; type a_t_arr3 is access t_arr3 ; variable va_t_arr3_1, va_t_arr3_2 : a_t_arr3 := new st_arr3 ; type a_st_arr3 is access st_arr3 ; variable va_st_arr3_1, va_st_arr3_2 : a_st_arr3 := new st_arr3 ; begin correct := correct and va_bit_vector_1.all = d_st_bit_vector ; correct := correct and va_string_1.all = d_st_string ; correct := correct and va_t_rec1_1.all = d_st_rec1 ; correct := correct and va_st_rec1_1.all = d_st_rec1 ; correct := correct and va_t_rec2_1.all = d_st_rec2 ; correct := correct and va_st_rec2_1.all = d_st_rec2 ; correct := correct and va_t_rec3_1.all = d_st_rec3 ; correct := correct and va_st_rec3_1.all = d_st_rec3 ; correct := correct and va_t_arr1_1.all = d_st_arr1 ; correct := correct and va_st_arr1_1.all = d_st_arr1 ; correct := correct and va_t_arr2_1.all = d_st_arr2 ; correct := correct and va_st_arr2_1.all = d_st_arr2 ; correct := correct and va_t_arr3_1.all = d_st_arr3 ; correct := correct and va_st_arr3_1.all = d_st_arr3 ; test_report ( "ARCH00687" , "Allocators with dynamic composite subtype indication" , correct) ; end p1 ; begin process begin p1 ; wait ; end process ; end ARCH00687 ; -- entity ENT00687_Test_Bench is end ENT00687_Test_Bench ; -- architecture ARCH00687_Test_Bench of ENT00687_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00687 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00687_Test_Bench ;

library ieee; use ieee.std_logic_1164.all; entity clockgen is port ( ext_clk, async_resetb : in std_ulogic; clk, sync_reset : out std_ulogic ); end clockgen;

-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2580.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c13s03b01x00p02n01i02580ent IS END c13s03b01x00p02n01i02580ent; ARCHITECTURE c13s03b01x00p02n01i02580arch OF c13s03b01x00p02n01i02580ent IS BEGIN TESTING: PROCESS variable "k : integer; BEGIN assert FALSE report "***FAILED TEST: c13s03b01x00p02n01i02580 - Identifier can only begin with a letter." severity ERROR; wait; END PROCESS TESTING; END c13s03b01x00p02n01i02580arch;

------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- axi_vdma_afifo_builtin.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010, 2012-2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- LIBRARY ieee; USE ieee.std_logic_1164.ALL; library fifo_generator_v12_0; use fifo_generator_v12_0.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.all; --use proc_common_v4_0.coregen_comp_defs.all; --use proc_common_v4_0.family_support.all; library axi_vdma_v6_2; use axi_vdma_v6_2.axi_vdma_pkg.all; -- synopsys translate_off --library XilinxCoreLib; --use XilinxCoreLib.all; -- synopsys translate_on ENTITY axi_vdma_afifo_builtin IS GENERIC ( ------------------------------------------------------------------------- -- Generic Declarations ------------------------------------------------------------------------- PL_FIFO_TYPE : STRING := "BLOCK_RAM"; -- BLOCK_RAM, LUTRAM, BUILT_IN; Default: BLOCK_RAM PL_READ_MODE : STRING := "STANDARD"; -- STANDARD, FWFT; Default: STANDARD PL_FASTER_CLOCK : STRING := "WR_CLK"; -- WR_CLK, RD_CLK; Default: WR_CLK PL_FULL_FLAGS_RST_VAL : INTEGER := 1; -- 1, 0; Default: 1 PL_DATA_WIDTH : INTEGER := 16; -- 1 - 1024; Default 16 C_FAMILY : string := "virtex7"; PL_FIFO_DEPTH : INTEGER := 1024 -- 16 - 256K; Default 1K ); PORT ( -- Common signal rst : in std_logic := '0'; sleep : in std_logic := '0'; wr_rst_busy : out std_logic := '0'; rd_rst_busy : out std_logic := '0'; -- Write Domain signals wr_clk : in std_logic := '0'; din : in std_logic_vector(PL_DATA_WIDTH-1 downto 0) := (others => '0'); wr_en : in std_logic := '0'; full : out std_logic := '0'; -- Write Domain signals rd_clk : in std_logic := '0'; rd_en : in std_logic := '0'; dout : out std_logic_vector(PL_DATA_WIDTH-1 downto 0) := (others => '0'); empty : out std_logic := '1' ); END ENTITY axi_vdma_afifo_builtin; ARCHITECTURE xilinx OF axi_vdma_afifo_builtin IS attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of xilinx : architecture is "yes"; --------------------------------------------------------------------------- -- FUNCTION : log2roundup --------------------------------------------------------------------------- FUNCTION log2roundup ( data_value : integer) RETURN integer IS VARIABLE width : integer := 0; VARIABLE cnt : integer := 1; CONSTANT lower_limit : integer := 1; CONSTANT upper_limit : integer := 8; BEGIN IF (data_value <= 1) THEN width := 0; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt *2; END LOOP; END IF; RETURN width; END log2roundup; ------------------------------------------------------------------------------ -- This function is used to implement an IF..THEN when such a statement is not -- allowed. ------------------------------------------------------------------------------ FUNCTION if_then_else ( condition : boolean; true_case : integer; false_case : integer) RETURN integer IS VARIABLE retval : integer := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; ------------------------------------------------------------------------------ -- This function is used to implement an IF..THEN when such a statement is not -- allowed and returns string. ------------------------------------------------------------------------------ function if_then_else ( condition : boolean; true_case : string; false_case : string) return string is begin if not condition then return false_case; else return true_case; end if; end if_then_else; ----------------------------------------------------------------------------- -- FUNCTION: to_lower_case_char -- Returns the lower case form of char IF char is an upper case letter. -- Otherwise char is returned. ----------------------------------------------------------------------------- FUNCTION to_lower_case_char( char : character ) RETURN character IS BEGIN ------------------------------------------------------------------------- -- If char is not an upper case letter THEN return char -- -- Otherwise map char to its corresponding lower case character and -- return that ------------------------------------------------------------------------- IF char<'A' OR char>'Z' THEN RETURN char; END IF; CASE char IS WHEN 'A' => RETURN 'a'; WHEN 'B' => RETURN 'b'; WHEN 'C' => RETURN 'c'; WHEN 'D' => RETURN 'd'; WHEN 'E' => RETURN 'e'; WHEN 'F' => RETURN 'f'; WHEN 'G' => RETURN 'g'; WHEN 'H' => RETURN 'h'; WHEN 'I' => RETURN 'i'; WHEN 'J' => RETURN 'j'; WHEN 'K' => RETURN 'k'; WHEN 'L' => RETURN 'l'; WHEN 'M' => RETURN 'm'; WHEN 'N' => RETURN 'n'; WHEN 'O' => RETURN 'o'; WHEN 'P' => RETURN 'p'; WHEN 'Q' => RETURN 'q'; WHEN 'R' => RETURN 'r'; WHEN 'S' => RETURN 's'; WHEN 'T' => RETURN 't'; WHEN 'U' => RETURN 'u'; WHEN 'V' => RETURN 'v'; WHEN 'W' => RETURN 'w'; WHEN 'X' => RETURN 'x'; WHEN 'Y' => RETURN 'y'; WHEN 'Z' => RETURN 'z'; WHEN OTHERS => RETURN char; END CASE; END to_lower_case_char; ----------------------------------------------------------------------------- -- Returns true IF case insensitive string comparison determines that -- str1 and str2 are equal ----------------------------------------------------------------------------- FUNCTION equal_ignore_case( str1 : string; str2 : string ) RETURN boolean IS CONSTANT len1 : integer := str1'length; CONSTANT len2 : integer := str2'length; VARIABLE equal : boolean := TRUE; BEGIN IF NOT (len1=len2) THEN equal := FALSE; ELSE FOR i IN str2'left TO str1'right LOOP IF NOT (to_lower_case_char(str1(i)) = to_lower_case_char(str2(i))) THEN equal := FALSE; END IF; END LOOP; END IF; RETURN equal; END equal_ignore_case; --############################################################# --# --# Get the Primitive fifo type --# Description: Algorithm for Built-In FIFO implementation --# to determine which primitive is most optimal to use --# --############################################################# function get_Prim_Fifo_Type ( width : integer; depth : integer; use_ecc : integer) return string is variable prim_4kx4_used : integer := (((width-1)/4 +1)*((depth-1)/4096 +1)); variable prim_2kx9_used : integer := (((width-1)/9 +1)*((depth-1)/2048 +1)); variable prim_1kx18_used : integer := (((width-1)/18+1)*((depth-1)/1024 +1)); variable prim_512x36_used : integer := (((width-1)/36+1)*((depth-1)/512 +1)); variable prim_8kx4_used : integer := (((width-1)/4 +1)*((depth-1)/8192 +1)); variable prim_4kx9_used : integer := (((width-1)/9 +1)*((depth-1)/4096 +1)); variable prim_2kx18_used : integer := (((width-1)/18+1)*((depth-1)/2048 +1)); variable prim_1kx36_used : integer := (((width-1)/36+1)*((depth-1)/1024 +1)); variable prim_512x72_used : integer := (((width-1)/72+1)*((depth-1)/512 +1)); variable min_used : integer := prim_4kx4_used; variable min_type : string (1 to 6) := "4kx4 "; begin if (use_ecc = 0) then --########################################################## --# Rules: Primitive used should --# - generate correct full flags if depth >= 512 --# - use min number of primitives --# - use primitive that reduces latency when possible --# This creates 3 cases: --# 1) depth <= 512 --# 2) depth = 1k --# 3) depth = 2k --# 4) depth >= 4k --########################################################## if (depth <= 512) then if (min_used > prim_512x72_used) then min_used := prim_512x72_used; min_type := "512x72"; else min_used := prim_512x36_used; min_type := "512x36"; end if; elsif (depth = 1024) then min_used := prim_1kx18_used; min_type := "1kx18 "; if (min_used > prim_512x36_used) then min_used := prim_512x36_used; min_type := "512x36"; end if; if (min_used > prim_1kx36_used) then min_used := prim_1kx36_used; min_type := "1kx36 "; end if; if (min_used > prim_512x72_used) then min_used := prim_512x72_used; min_type := "512x72"; end if; elsif (depth = 2048) then min_used := prim_2kx9_used; min_type := "2kx9 "; if (min_used > prim_1kx18_used) then min_used := prim_1kx18_used; min_type := "1kx18 "; end if; if (min_used > prim_512x36_used) then min_used := prim_512x36_used; min_type := "512x36"; end if; if (min_used > prim_2kx18_used) then min_used := prim_2kx18_used; min_type := "2kx18 "; end if; if (min_used > prim_1kx36_used) then min_used := prim_1kx36_used; min_type := "1kx36 "; end if; if (min_used > prim_512x72_used) then min_used := prim_512x72_used; min_type := "512x72"; end if; else min_used := prim_4kx4_used; min_type := "4kx4 "; if (min_used > prim_2kx9_used) then min_used := prim_2kx9_used; min_type := "2kx9 "; end if; if (min_used > prim_1kx18_used) then min_used := prim_1kx18_used; min_type := "1kx18 "; end if; if (min_used > prim_512x36_used) then min_used := prim_512x36_used; min_type := "512x36"; end if; if (min_used > prim_8kx4_used) then min_used := prim_8kx4_used; min_type := "8kx4 "; end if; if (min_used > prim_4kx9_used) then min_used := prim_4kx9_used; min_type := "4kx9 "; end if; if (min_used > prim_2kx18_used) then min_used := prim_2kx18_used; min_type := "2kx18 "; end if; if (min_used > prim_1kx36_used) then min_used := prim_1kx36_used; min_type := "1kx36 "; end if; if (min_used > prim_512x72_used) then min_used := prim_512x72_used; min_type := "512x72"; end if; end if; else -- if ecc is used, always use the 512x72 primitive min_used := prim_512x72_used; min_type := "512x72"; end if; return min_type; end get_Prim_Fifo_Type; --CONSTANT GND : std_logic := '0'; CONSTANT VCC : std_logic := '1'; CONSTANT ZERO1 : std_logic_vector(0 downto 0) := (others => '0'); CONSTANT ZERO2 : std_logic_vector(1 downto 0) := (others => '0'); CONSTANT ZERO3 : std_logic_vector(2 downto 0) := (others => '0'); CONSTANT ZERO4 : std_logic_vector(3 downto 0) := (others => '0'); CONSTANT ZERO8 : std_logic_vector(7 downto 0) := (others => '0'); CONSTANT ZERO16 : std_logic_vector(15 downto 0) := (others => '0'); CONSTANT ZERO32 : std_logic_vector(31 downto 0) := (others => '0'); CONSTANT ZERO64 : std_logic_vector(63 downto 0) := (others => '0'); --CONSTANT ZERO_pntr : std_logic_vector(log2roundup(pl_fifo_depth)-1 downto 0) := (others => '0'); CONSTANT C_PRELOAD_LATENCY : integer := if_then_else((PL_READ_MODE = "FWFT"), 0, 1); CONSTANT C_PRELOAD_REGS : integer := if_then_else((PL_READ_MODE = "FWFT"), 1, 0); CONSTANT C_WR_FREQ : integer := if_then_else((PL_FASTER_CLOCK = "WR_CLK"), 10, 1); CONSTANT C_RD_FREQ : integer := if_then_else((PL_FASTER_CLOCK = "RD_CLK"), 10, 1); CONSTANT C_MEMORY_TYPE : integer := if_then_else((PL_FIFO_TYPE = "BLOCK_RAM"), 1, if_then_else((PL_FIFO_TYPE = "LUTRAM"), 2, if_then_else((PL_FIFO_TYPE = "BUILT_IN"), 4, 0))); CONSTANT C_IMPLEMENTATION_TYPE : integer := if_then_else((PL_FIFO_TYPE = "BLOCK_RAM"), 0, if_then_else((PL_FIFO_TYPE = "LUTRAM"), 0, if_then_else((PL_FIFO_TYPE = "BUILT_IN"), 6, 8))); CONSTANT PRIM_FIFO_TYPE : string := get_Prim_Fifo_Type(pl_data_width,pl_fifo_depth,0); CONSTANT C_PRIM_FIFO_TYPE : string := if_then_else(PRIM_FIFO_TYPE = "8kx4 ", "8kx4", if_then_else(PRIM_FIFO_TYPE = "4kx9 ", "4kx9", if_then_else(PRIM_FIFO_TYPE = "4kx4 ", "4kx4", if_then_else(PRIM_FIFO_TYPE = "2kx18 ", "2kx18", if_then_else(PRIM_FIFO_TYPE = "2kx9 ", "2kx9", if_then_else(PRIM_FIFO_TYPE = "1kx36 ", "1kx36", if_then_else(PRIM_FIFO_TYPE = "1kx18 ", "1kx18", if_then_else(PRIM_FIFO_TYPE = "512x72", "512x72", if_then_else(PRIM_FIFO_TYPE = "512x36", "512x36",""))))))))); CONSTANT IS_FIFO_TYPE_VLD : integer := if_then_else((PL_FIFO_TYPE = "BLOCK_RAM") or (PL_FIFO_TYPE = "LUTRAM") or (PL_FIFO_TYPE = "BUILT_IN"), 1, 0); CONSTANT IS_READ_MODE_VLD : integer := if_then_else((PL_READ_MODE = "STANDARD") or (PL_READ_MODE = "FWFT"), 1, 0); CONSTANT IS_DATA_WIDTH_VLD : integer := if_then_else(PL_DATA_WIDTH > 0 and PL_DATA_WIDTH <= 1024, 1, 0); CONSTANT IS_FIFO_DEPTH_VLD : integer := if_then_else((PL_FIFO_DEPTH = 16 or PL_FIFO_DEPTH = 32 or PL_FIFO_DEPTH = 64 or PL_FIFO_DEPTH = 128 or PL_FIFO_DEPTH = 256 or PL_FIFO_DEPTH = 512 or PL_FIFO_DEPTH = 1024 or PL_FIFO_DEPTH = 2048 or PL_FIFO_DEPTH = 4096 or PL_FIFO_DEPTH = 8192 or PL_FIFO_DEPTH = 16384 or PL_FIFO_DEPTH = 32768 or PL_FIFO_DEPTH = 65536 or PL_FIFO_DEPTH = 131072 or PL_FIFO_DEPTH = 262144),1,0); CONSTANT VLD_BI_DEPTH : integer := if_then_else((PL_FIFO_DEPTH = 512 or PL_FIFO_DEPTH = 1024 or PL_FIFO_DEPTH = 2048 or PL_FIFO_DEPTH = 4096 or PL_FIFO_DEPTH = 8192 or PL_FIFO_DEPTH = 16384 or PL_FIFO_DEPTH = 32768 or PL_FIFO_DEPTH = 65536 or PL_FIFO_DEPTH = 131072 or PL_FIFO_DEPTH = 262144),1,0); -- CONSTANT IS_BI_DEPTH_VLD : integer := if_then_else((VLD_BI_DEPTH = 1 and PL_FIFO_TYPE = "BUILT_IN"), 1, 0); CONSTANT IS_BI_DEPTH_VLD : integer := if_then_else((VLD_BI_DEPTH = 1), 1, 0); CONSTANT log2roundup_pl_fifo_depth : integer := log2roundup(pl_fifo_depth); CONSTANT PROG_FULL_THRESH_ASSERT_VAL_1 : integer := if_then_else((PL_FIFO_TYPE = "BUILT_IN"), PL_FIFO_DEPTH-150, 14); CONSTANT PROG_FULL_THRESH_NEGATE_VAL_1 : integer := if_then_else((PL_FIFO_TYPE = "BUILT_IN"), PL_FIFO_DEPTH-160, 12); CONSTANT SYNC_RST_PORT : integer := if_then_else(((C_FAMILY = "kintexu") or (C_FAMILY = "virtexu") or (C_FAMILY = "artixu")), 1, 0); -- ultra-scale CONSTANT ASYNC_RST_PORT : integer := if_then_else(((C_FAMILY /= "kintexu") and (C_FAMILY /= "virtexu") and (C_FAMILY /= "artixu")), 1, 0); -- 7-series (not ultrascale) --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal ZERO_pntr : std_logic_vector(log2roundup_pl_fifo_depth-1 downto 0) := (others => '0'); signal GND : std_logic := '0'; signal ALMOST_FULL : std_logic; signal WR_ACK : std_logic; signal OVERFLOW : std_logic; signal ALMOST_EMPTY : std_logic; signal VALID : std_logic; signal UNDERFLOW : std_logic; signal PROG_FULL : std_logic; signal PROG_EMPTY : std_logic; signal SBITERR : std_logic; signal DBITERR : std_logic; signal S_AXI_AWREADY : std_logic; signal S_AXI_WREADY : std_logic; signal S_AXI_BID : std_logic_vector(3 DOWNTO 0); signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_BUSER : std_logic_vector(0 downto 0); signal S_AXI_BVALID : std_logic; -- AXI Full/Lite Master Write Channel (Read side) signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0); signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWUSER : std_logic_vector(0 downto 0); signal M_AXI_AWVALID : std_logic; signal M_AXI_WID : std_logic_vector(3 DOWNTO 0); signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0); signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0); signal M_AXI_WLAST : std_logic; signal M_AXI_WUSER : std_logic_vector(0 downto 0); signal M_AXI_WVALID : std_logic; signal M_AXI_BREADY : std_logic; -- AXI Full/Lite Slave Read Channel (Write side) signal S_AXI_ARREADY : std_logic; signal S_AXI_RID : std_logic_vector(3 DOWNTO 0); signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0); signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_RLAST : std_logic; signal S_AXI_RUSER : std_logic_vector(0 downto 0); signal S_AXI_RVALID : std_logic; -- AXI Full/Lite Master Read Channel (Read side) signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0); signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARUSER : std_logic_vector(0 downto 0); signal M_AXI_ARVALID : std_logic; signal M_AXI_RREADY : std_logic; -- AXI Streaming Slave Signals (Write side) signal S_AXIS_TREADY : std_logic; -- AXI Streaming Master Signals (Read side) signal M_AXIS_TVALID : std_logic; signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0); signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TLAST : std_logic; signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0); signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_SBITERR : std_logic; signal AXI_AW_DBITERR : std_logic; signal AXI_AW_OVERFLOW : std_logic; signal AXI_AW_UNDERFLOW : std_logic; signal AXI_AW_PROG_FULL : STD_LOGIC; signal AXI_AW_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Data Channel Signals signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_SBITERR : std_logic; signal AXI_W_DBITERR : std_logic; signal AXI_W_OVERFLOW : std_logic; signal AXI_W_UNDERFLOW : std_logic; signal AXI_W_PROG_FULL : STD_LOGIC; signal AXI_W_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Response Channel Signals signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_SBITERR : std_logic; signal AXI_B_DBITERR : std_logic; signal AXI_B_OVERFLOW : std_logic; signal AXI_B_UNDERFLOW : std_logic; signal AXI_B_PROG_FULL : STD_LOGIC; signal AXI_B_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Address Channel Signals signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_SBITERR : std_logic; signal AXI_AR_DBITERR : std_logic; signal AXI_AR_OVERFLOW : std_logic; signal AXI_AR_UNDERFLOW : std_logic; signal AXI_AR_PROG_FULL : STD_LOGIC; signal AXI_AR_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Data Channel Signals signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_SBITERR : std_logic; signal AXI_R_DBITERR : std_logic; signal AXI_R_OVERFLOW : std_logic; signal AXI_R_UNDERFLOW : std_logic; signal AXI_R_PROG_FULL : STD_LOGIC; signal AXI_R_PROG_EMPTY : STD_LOGIC; -- AXI Streaming FIFO Related Signals signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_SBITERR : std_logic; signal AXIS_DBITERR : std_logic; signal AXIS_OVERFLOW : std_logic; signal AXIS_UNDERFLOW : std_logic; signal AXIS_PROG_FULL : STD_LOGIC; signal AXIS_PROG_EMPTY : STD_LOGIC; --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal DATA_COUNT : std_logic_vector(log2roundup_pl_fifo_depth-1 DOWNTO 0); signal RD_DATA_COUNT : std_logic_vector(log2roundup_pl_fifo_depth-1 DOWNTO 0); signal WR_DATA_COUNT : std_logic_vector(log2roundup_pl_fifo_depth-1 DOWNTO 0); signal wr_rst_busy_sig : std_logic := '0'; signal rd_rst_busy_sig : std_logic := '0'; signal rst_i : std_logic := '0'; signal srst_i : std_logic := '0'; BEGIN FAMILY_8 : if ((C_FAMILY = "kintexu") or (C_FAMILY = "virtexu") or (C_FAMILY = "artixu")) generate begin wr_rst_busy <= wr_rst_busy_sig; rd_rst_busy <= rd_rst_busy_sig; srst_i <= rst; rst_i <= '0'; end generate FAMILY_8; FAMILY_NOT_8 : if ((C_FAMILY /= "kintexu") and (C_FAMILY /= "virtexu") and (C_FAMILY /= "artixu")) generate begin wr_rst_busy <= '0'; rd_rst_busy <= '0'; srst_i <= '0'; rst_i <= rst; end generate FAMILY_NOT_8; ZERO_pntr <= (others => '0'); GND <= '0'; fg_builtin_fifo_inst : entity fifo_generator_v12_0.fifo_generator_v12_0 GENERIC MAP ( C_COMMON_CLOCK => 0, -- C_COUNT_TYPE => C_COUNT_TYPE, C_DATA_COUNT_WIDTH => log2roundup_pl_fifo_depth, -- C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_DIN_WIDTH => pl_data_width, -- C_DOUT_RST_VAL => C_DOUT_RST_VAL, C_DOUT_WIDTH => pl_data_width, -- C_ENABLE_RLOCS => C_ENABLE_RLOCS, --C_FAMILY => "virtex7", C_FAMILY => C_FAMILY, C_FULL_FLAGS_RST_VAL => pl_full_flags_rst_val, -- C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY, -- C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL, -- C_HAS_BACKUP => C_HAS_BACKUP, -- C_HAS_DATA_COUNT => C_HAS_DATA_COUNT, -- C_HAS_INT_CLK => C_HAS_INT_CLK, -- C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, -- C_HAS_OVERFLOW => C_HAS_OVERFLOW, -- C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT, -- C_HAS_RD_RST => C_HAS_RD_RST, C_HAS_RST => ASYNC_RST_PORT, C_HAS_SRST => SYNC_RST_PORT, -- C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, -- C_HAS_VALID => C_HAS_VALID, -- C_HAS_WR_ACK => C_HAS_WR_ACK, -- C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT, -- C_HAS_WR_RST => C_HAS_WR_RST, C_IMPLEMENTATION_TYPE => C_IMPLEMENTATION_TYPE, -- C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MEMORY_TYPE => C_MEMORY_TYPE, -- C_MIF_FILE_NAME => C_MIF_FILE_NAME, -- C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, -- C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, C_PRELOAD_REGS => C_PRELOAD_REGS, C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE, C_PROG_EMPTY_THRESH_ASSERT_VAL => 10, C_PROG_EMPTY_THRESH_NEGATE_VAL => 9, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL_1, C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL_1, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => log2roundup_pl_fifo_depth, C_RD_DEPTH => pl_fifo_depth, C_RD_FREQ => C_RD_FREQ, C_RD_PNTR_WIDTH => log2roundup_pl_fifo_depth, -- C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, -- C_USE_DOUT_RST => C_USE_DOUT_RST, -- C_USE_ECC => C_USE_ECC, -- C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, -- C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, -- C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT, -- C_VALID_LOW => C_VALID_LOW, -- C_WR_ACK_LOW => C_WR_ACK_LOW, C_WR_DATA_COUNT_WIDTH => log2roundup_pl_fifo_depth, C_WR_DEPTH => pl_fifo_depth, C_WR_FREQ => C_WR_FREQ, C_WR_PNTR_WIDTH => log2roundup_pl_fifo_depth, -- C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY, -- C_MSGON_VAL => C_MSGON_VAL, -- C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC, -- C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE, C_SYNCHRONIZER_STAGE => MTBF_STAGES, -- AXI Interface related parameters start here C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0; C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0; C_HAS_SLAVE_CE => 0, -- : integer := 0; C_HAS_MASTER_CE => 0, -- : integer := 0; C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0; C_USE_COMMON_OVERFLOW => 0, -- : integer := 0; C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0; C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH => 4 , -- : integer := 0; C_AXI_ADDR_WIDTH => 32, -- : integer := 0; C_AXI_DATA_WIDTH => 64, -- : integer := 0; C_AXI_LEN_WIDTH => 8, -- : integer := 8; C_AXI_LOCK_WIDTH => 2, -- : integer := 2; C_HAS_AXI_ID => 0, -- : integer := 0; C_HAS_AXI_AWUSER => 0 , -- : integer := 0; C_HAS_AXI_WUSER => 0 , -- : integer := 0; C_HAS_AXI_BUSER => 0 , -- : integer := 0; C_HAS_AXI_ARUSER => 0 , -- : integer := 0; C_HAS_AXI_RUSER => 0 , -- : integer := 0; C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0; C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0; C_AXI_WUSER_WIDTH => 1 , -- : integer := 0; C_AXI_BUSER_WIDTH => 1 , -- : integer := 0; C_AXI_RUSER_WIDTH => 1 , -- : integer := 0; -- AXI Streaming C_HAS_AXIS_TDATA => 0 , -- : integer := 0; C_HAS_AXIS_TID => 0 , -- : integer := 0; C_HAS_AXIS_TDEST => 0 , -- : integer := 0; C_HAS_AXIS_TUSER => 0 , -- : integer := 0; C_HAS_AXIS_TREADY => 1 , -- : integer := 0; C_HAS_AXIS_TLAST => 0 , -- : integer := 0; C_HAS_AXIS_TSTRB => 0 , -- : integer := 0; C_HAS_AXIS_TKEEP => 0 , -- : integer := 0; C_AXIS_TDATA_WIDTH => 64, -- : integer := 1; C_AXIS_TID_WIDTH => 8 , -- : integer := 1; C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1; C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1; C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1; C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Data FIFO C_APPLICATION_TYPE_WACH => 0, -- : integer := 0; C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0; C_APPLICATION_TYPE_RACH => 0, -- : integer := 0; C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH => 0, -- : integer := 0; C_USE_ECC_WDCH => 0, -- : integer := 0; C_USE_ECC_WRCH => 0, -- : integer := 0; C_USE_ECC_RACH => 0, -- : integer := 0; C_USE_ECC_RDCH => 0, -- : integer := 0; C_USE_ECC_AXIS => 0, -- : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH => 32, -- : integer := 1; C_DIN_WIDTH_WDCH => 64, -- : integer := 1; C_DIN_WIDTH_WRCH => 2 , -- : integer := 1; C_DIN_WIDTH_RACH => 32, -- : integer := 1; C_DIN_WIDTH_RDCH => 64, -- : integer := 1; C_DIN_WIDTH_AXIS => 1 , -- : integer := 1; C_WR_DEPTH_WACH => 16 , -- : integer := 16; C_WR_DEPTH_WDCH => 1024, -- : integer := 16; C_WR_DEPTH_WRCH => 16 , -- : integer := 16; C_WR_DEPTH_RACH => 16 , -- : integer := 16; C_WR_DEPTH_RDCH => 1024, -- : integer := 16; C_WR_DEPTH_AXIS => 1024, -- : integer := 16; C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4; C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0; C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0; C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0; C_REG_SLICE_MODE_WACH => 0, -- : integer := 0; C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0; C_REG_SLICE_MODE_RACH => 0, -- : integer := 0; C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0 ) PORT MAP ( backup => GND, backup_marker => GND, clk => GND, rst => rst_i, srst => srst_i, wr_clk => wr_clk, wr_rst => GND, rd_clk => rd_clk, rd_rst => GND, din => din, wr_en => wr_en, rd_en => rd_en, sleep => sleep, wr_rst_busy => wr_rst_busy_sig, rd_rst_busy => rd_rst_busy_sig, prog_empty_thresh => ZERO_pntr, prog_empty_thresh_assert => ZERO_pntr, prog_empty_thresh_negate => ZERO_pntr, prog_full_thresh => ZERO_pntr, prog_full_thresh_assert => ZERO_pntr, prog_full_thresh_negate => ZERO_pntr, int_clk => GND, injectdbiterr => GND, injectsbiterr => GND, dout => dout, full => full, empty => empty, almost_full => ALMOST_FULL, wr_ack => WR_ACK, overflow => OVERFLOW, almost_empty => ALMOST_EMPTY, valid => VALID, underflow => UNDERFLOW, data_count => DATA_COUNT, rd_data_count => RD_DATA_COUNT, wr_data_count => WR_DATA_COUNT, prog_full => PROG_FULL, prog_empty => PROG_EMPTY, sbiterr => SBITERR, dbiterr => DBITERR, m_aclk => '0', -- : IN std_logic := '0'; s_aclk => '0', -- : IN std_logic := '0'; s_aresetn => '0', -- : IN std_logic := '0'; m_aclk_en => '0', -- : IN std_logic := '0'; s_aclk_en => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Slave Write Channel (write side) s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awvalid => '0', -- : IN std_logic := '0'; s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic; s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wlast => '0', -- : IN std_logic := '0'; s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wvalid => '0', -- : IN std_logic := '0'; s_axi_wready => S_AXI_WREADY, -- : OUT std_logic; s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0); s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic; s_axi_bready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Write Channel (Read side) m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0); m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic; m_axi_awready => '0', -- : IN std_logic := '0'; m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0); m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic; m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0); m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic; m_axi_wready => '0', -- : IN std_logic := '0'; m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bvalid => '0', -- : IN std_logic := '0'; m_axi_bready => M_AXI_BREADY, -- : OUT std_logic; -- AXI Full/Lite Slave Read Channel (Write side) s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arvalid => '0', -- : IN std_logic := '0'; s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic; s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic; s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0); s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic; s_axi_rready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Read Channel (Read side) m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0); m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic; m_axi_arready => '0', -- : IN std_logic := '0'; m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rlast => '0', -- : IN std_logic := '0'; m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rvalid => '0', -- : IN std_logic := '0'; m_axi_rready => M_AXI_RREADY, -- : OUT std_logic; -- AXI Streaming Slave Signals (Write side) s_axis_tvalid => '0', -- : IN std_logic := '0'; s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic; s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tlast => '0', -- : IN std_logic := '0'; s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- AXI Streaming Master Signals (Read side) m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic; m_axis_tready => '0', -- : IN std_logic := '0'; m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0); m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0); m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0); m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic; m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0); m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0); m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals axi_aw_injectsbiterr => '0', -- : IN std_logic := '0'; axi_aw_injectdbiterr => '0', -- : IN std_logic := '0'; axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic; axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic; axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic; axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic; axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Data Channel Signals axi_w_injectsbiterr => '0', -- : IN std_logic := '0'; axi_w_injectdbiterr => '0', -- : IN std_logic := '0'; axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic; axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic; axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic; axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic; axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Response Channel Signals axi_b_injectsbiterr => '0', -- : IN std_logic := '0'; axi_b_injectdbiterr => '0', -- : IN std_logic := '0'; axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic; axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic; axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic; axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic; axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Address Channel Signals axi_ar_injectsbiterr => '0', -- : IN std_logic := '0'; axi_ar_injectdbiterr => '0', -- : IN std_logic := '0'; axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic; axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic; axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic; axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic; axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Data Channel Signals axi_r_injectsbiterr => '0', -- : IN std_logic := '0'; axi_r_injectdbiterr => '0', -- : IN std_logic := '0'; axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic; axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic; axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic; axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic; axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Streaming FIFO Related Signals axis_injectsbiterr => '0', -- : IN std_logic := '0'; axis_injectdbiterr => '0', -- : IN std_logic := '0'; axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic; axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic; axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic; axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0'; axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1'; ); END ARCHITECTURE xilinx;

-- **** -- T80(b) core. In an effort to merge and maintain bug fixes .... -- -- -- Ver 300 started tidyup -- MikeJ March 2005 -- Latest version from www.fpgaarcade.com (original www.opencores.org) -- -- **** -- -- Z80 compatible microprocessor core, asynchronous top level -- -- Version : 0247 -- -- Copyright (c) 2001-2002 Daniel Wallner ([email protected]) -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Please report bugs to the author, but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- -- The latest version of this file can be found at: -- http://www.opencores.org/cvsweb.shtml/t80/ -- -- Limitations : -- -- File history : -- -- 0208 : First complete release -- -- 0211 : Fixed interrupt cycle -- -- 0235 : Updated for T80 interface change -- -- 0238 : Updated for T80 interface change -- -- 0240 : Updated for T80 interface change -- -- 0242 : Updated for T80 interface change -- -- 0247 : Fixed bus req/ack cycle -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.T80_Pack.all; entity T80a is generic( Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB ); port( RESET_n : in std_logic; CLK_n : in std_logic; WAIT_n : in std_logic; INT_n : in std_logic; NMI_n : in std_logic; BUSRQ_n : in std_logic; M1_n : out std_logic; MREQ_n : out std_logic; IORQ_n : out std_logic; RD_n : out std_logic; WR_n : out std_logic; RFSH_n : out std_logic; HALT_n : out std_logic; BUSAK_n : out std_logic; A : out std_logic_vector(15 downto 0); D : inout std_logic_vector(7 downto 0); D_I : in std_logic_vector(7 downto 0); D_O : out std_logic_vector(7 downto 0); ResetPC : in std_logic_vector(15 downto 0); ResetSP : in std_logic_vector(15 downto 0) ); end T80a; architecture rtl of T80a is signal CEN : std_logic; signal Reset_s : std_logic; signal IntCycle_n : std_logic; signal IORQ : std_logic; signal NoRead : std_logic; signal Write : std_logic; signal MREQ : std_logic; signal MReq_Inhibit : std_logic; signal Req_Inhibit : std_logic; signal RD : std_logic; signal MREQ_n_i : std_logic; signal IORQ_n_i : std_logic; signal RD_n_i : std_logic; signal WR_n_i : std_logic; signal RFSH_n_i : std_logic; signal BUSAK_n_i : std_logic; signal A_i : std_logic_vector(15 downto 0); signal DO : std_logic_vector(7 downto 0); signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser signal Wait_s : std_logic; signal MCycle : std_logic_vector(2 downto 0); signal TState : std_logic_vector(2 downto 0); begin CEN <= '1'; BUSAK_n <= BUSAK_n_i; MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit); RD_n_i <= not RD or Req_Inhibit; MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z'; IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z'; RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z'; WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z'; RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z'; A <= A_i when BUSAK_n_i = '1' else (others => 'Z'); D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); D_O <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z'); process (RESET_n, CLK_n) begin if RESET_n = '0' then Reset_s <= '0'; elsif CLK_n'event and CLK_n = '1' then Reset_s <= '1'; end if; end process; u0 : T80 generic map( Mode => Mode, IOWait => 1) port map( CEN => CEN, M1_n => M1_n, IORQ => IORQ, NoRead => NoRead, Write => Write, RFSH_n => RFSH_n_i, HALT_n => HALT_n, WAIT_n => Wait_s, INT_n => INT_n, NMI_n => NMI_n, RESET_n => Reset_s, BUSRQ_n => BUSRQ_n, BUSAK_n => BUSAK_n_i, CLK_n => CLK_n, A => A_i, DInst => D_I, -- D -> D_I DI => DI_Reg, DO => DO, MC => MCycle, TS => TState, IntCycle_n => IntCycle_n, ResetPC => ResetPC, ResetSP => ResetSP ); process (CLK_n) begin if CLK_n'event and CLK_n = '0' then Wait_s <= WAIT_n; if TState = "011" and BUSAK_n_i = '1' then DI_Reg <= to_x01(D_I); -- D -> D_I end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then WR_n_i <= '1'; elsif CLK_n'event and CLK_n = '1' then WR_n_i <= '1'; if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!! WR_n_i <= not Write; end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then Req_Inhibit <= '0'; elsif CLK_n'event and CLK_n = '1' then if MCycle = "001" and TState = "010" then Req_Inhibit <= '1'; else Req_Inhibit <= '0'; end if; end if; end process; process (Reset_s,CLK_n) begin if Reset_s = '0' then MReq_Inhibit <= '0'; elsif CLK_n'event and CLK_n = '0' then if MCycle = "001" and TState = "010" then MReq_Inhibit <= '1'; else MReq_Inhibit <= '0'; end if; end if; end process; process(Reset_s,CLK_n) begin if Reset_s = '0' then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '0'; elsif CLK_n'event and CLK_n = '0' then if MCycle = "001" then if TState = "001" then RD <= IntCycle_n; MREQ <= IntCycle_n; IORQ_n_i <= IntCycle_n; end if; if TState = "011" then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '1'; end if; if TState = "100" then MREQ <= '0'; end if; else if TState = "001" and NoRead = '0' then RD <= not Write; IORQ_n_i <= not IORQ; MREQ <= not IORQ; end if; if TState = "011" then RD <= '0'; IORQ_n_i <= '1'; MREQ <= '0'; end if; end if; end if; end process; end;

-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7.1 Core - Top-level core wrapper -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: ram_16x1k_sp_exdes.vhd -- -- Description: -- This is the actual BMG core wrapper. -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: August 31, 2005 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY UNISIM; USE UNISIM.VCOMPONENTS.ALL; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- ENTITY ram_16x1k_sp_exdes IS PORT ( --Inputs - Port A ENA : IN STD_LOGIC; --opt port WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); CLKA : IN STD_LOGIC ); END ram_16x1k_sp_exdes; ARCHITECTURE xilinx OF ram_16x1k_sp_exdes IS COMPONENT BUFG IS PORT ( I : IN STD_ULOGIC; O : OUT STD_ULOGIC ); END COMPONENT; COMPONENT ram_16x1k_sp IS PORT ( --Port A ENA : IN STD_LOGIC; --opt port WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); CLKA : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA_buf : STD_LOGIC; SIGNAL CLKB_buf : STD_LOGIC; SIGNAL S_ACLK_buf : STD_LOGIC; BEGIN bufg_A : BUFG PORT MAP ( I => CLKA, O => CLKA_buf ); bmg0 : ram_16x1k_sp PORT MAP ( --Port A ENA => ENA, WEA => WEA, ADDRA => ADDRA, DINA => DINA, DOUTA => DOUTA, CLKA => CLKA_buf ); END xilinx;

------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: ahb2avl_async -- File: ahb2avl_async.vhd -- Author: Magnus Hjorth - Aeroflex Gaisler -- Description: Asynchronous AHB to Avalon-MM interface based on ddr2spa -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; library gaisler; use gaisler.ddrpkg.all; use gaisler.ddrintpkg.all; entity ahb2avl_async is generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#f00#; burstlen : integer := 8; nosync : integer := 0; ahbbits : integer := ahbdw; avldbits : integer := 32; avlabits : integer := 20 ); port ( rst_ahb : in std_ulogic; clk_ahb : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; rst_avl : in std_ulogic; clk_avl : in std_ulogic; avlsi : out ddravl_slv_in_type; avlso : in ddravl_slv_out_type ); end; architecture struct of ahb2avl_async is constant l2blen: integer := log2(burstlen)+log2(32); constant l2ddrw: integer := log2(avldbits); constant l2ahbw: integer := log2(ahbbits); -- Write buffer dimensions constant wbuf_rabits_s: integer := 1+l2blen-l2ddrw; constant wbuf_rabits_r: integer := wbuf_rabits_s; constant wbuf_rdbits: integer := avldbits; constant wbuf_wabits: integer := 1+l2blen-5; constant wbuf_wdbits: integer := ahbbits; -- Read buffer dimensions constant rbuf_rabits: integer := l2blen-l2ahbw; constant rbuf_rdbits: integer := wbuf_wdbits; constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits)); constant rbuf_wdbits: integer := avldbits; signal request : ddr_request_type; signal start_tog : std_ulogic; signal response : ddr_response_type; signal wbwaddr: std_logic_vector(wbuf_wabits-1 downto 0); signal wbwdata: std_logic_vector(wbuf_wdbits-1 downto 0); signal wbraddr: std_logic_vector(wbuf_rabits_s-1 downto 0); signal wbrdata: std_logic_vector(wbuf_rdbits-1 downto 0); signal rbwaddr: std_logic_vector(rbuf_wabits-1 downto 0); signal rbwdata: std_logic_vector(rbuf_wdbits-1 downto 0); signal rbraddr: std_logic_vector(rbuf_rabits-1 downto 0); signal rbrdata: std_logic_vector(rbuf_rdbits-1 downto 0); signal wbwrite,wbwritebig,rbwrite: std_ulogic; signal gnd: std_logic_vector(3 downto 0); signal vcc: std_ulogic; begin gnd <= (others => '0'); vcc <= '1'; fe0: ddr2spax_ahb generic map ( hindex => hindex, haddr => haddr, hmask => hmask, ioaddr => 0, iomask => 0, burstlen => burstlen, nosync => nosync, ahbbits => ahbbits, devid => GAISLER_AHB2AVLA, ddrbits => avldbits/2 ) port map ( rst => rst_ahb, clk_ahb => clk_ahb, ahbsi => ahbsi, ahbso => ahbso, request => request, start_tog => start_tog, response => response, wbwaddr => wbwaddr, wbwdata => wbwdata, wbwrite => wbwrite, wbwritebig => wbwritebig, rbraddr => rbraddr, rbrdata => rbrdata, hwidth => gnd(0), beid => gnd(3 downto 0) ); be0: ahb2avl_async_be generic map ( avldbits => avldbits, avlabits => avlabits, ahbbits => ahbbits, burstlen => burstlen, nosync => nosync ) port map ( rst => rst_avl, clk => clk_avl, avlsi => avlsi, avlso => avlso, request => request, start_tog => start_tog, response => response, wbraddr => wbraddr, wbrdata => wbrdata, rbwaddr => rbwaddr, rbwdata => rbwdata, rbwrite => rbwrite ); wbuf: ddr2buf generic map (tech => 0, wabits => wbuf_wabits, wdbits => wbuf_wdbits, rabits => wbuf_rabits_r, rdbits => wbuf_rdbits, sepclk => 1, wrfst => 0) port map ( rclk => clk_avl, renable => vcc, raddress => wbraddr(wbuf_rabits_r-1 downto 0), dataout => wbrdata, wclk => clk_ahb, write => wbwrite, writebig => wbwritebig, waddress => wbwaddr, datain => wbwdata); rbuf: ddr2buf generic map (tech => 0, wabits => rbuf_wabits, wdbits => rbuf_wdbits, rabits => rbuf_rabits, rdbits => rbuf_rdbits, sepclk => 1, wrfst => 0) port map ( rclk => clk_ahb, renable => vcc, raddress => rbraddr, dataout => rbrdata, wclk => clk_avl, write => rbwrite, writebig => '0', waddress => rbwaddr, datain => rbwdata); end;

library IEEE; use IEEE.Std_Logic_1164.all; entity C3 is port (A: in std_logic; B: in std_logic; C: in std_logic; F: out std_logic ); end C3; architecture c3_estr of C3 is begin F <= (B or C) and (not A); end c3_estr;

-- SIMON 64/128 -- feistel round function -- Inner-round pipelining using negative-edge triggered registers -- -- @Author: Jos Wetzels -- @Author: Wouter Bokslag -- -- Parameters: -- v_in: plaintext block -- v_k: subkey -- v_out: ciphertext block -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity round_f is port(clk : in std_logic; rst : in std_logic; v_in : in std_logic_vector(63 downto 0); v_k : in std_logic_vector(31 downto 0); v_out : out std_logic_vector(63 downto 0) ); end round_f; architecture Behavioral of round_f is signal op_0_s : std_logic_vector(31 downto 0); signal stage_0_out_s : std_logic_vector(31 downto 0); signal op_1_s : std_logic_vector(31 downto 0); signal op_2_s : std_logic_vector(31 downto 0); component phi is port(x_in : in std_logic_vector(31 downto 0); x_out : out std_logic_vector(31 downto 0)); end component; component gamma is port(x_in : in std_logic_vector(31 downto 0); y_in : in std_logic_vector(31 downto 0); x_out : out std_logic_vector(31 downto 0)); end component; component neg_reg_32 is port(clk : in std_logic; rst : in std_logic; data_in : in std_logic_vector(31 downto 0); data_out : out std_logic_vector(31 downto 0)); end component; begin PHI_0 : phi port map (v_in(63 downto 32), op_0_s); GAMMA_0 : gamma port map (v_in(31 downto 0), v_k, op_1_s); REG_STAGE_0 : neg_reg_32 port map (clk, rst, op_1_s, stage_0_out_s); GAMMA_1 : gamma port map (op_0_s, stage_0_out_s, op_2_s); v_out <= op_2_s & v_in(63 downto 32); end Behavioral;

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2014.4 -- Copyright (C) 2014 Xilinx Inc. All rights reserved. -- -- ============================================================== library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; entity adder_AXI_CTRL_s_axi is generic ( C_ADDR_WIDTH : INTEGER := 6; C_DATA_WIDTH : INTEGER := 32); port ( -- axi4 lite slave signals ACLK :in STD_LOGIC; ARESET :in STD_LOGIC; ACLK_EN :in STD_LOGIC; AWADDR :in STD_LOGIC_VECTOR(C_ADDR_WIDTH-1 downto 0); AWVALID :in STD_LOGIC; AWREADY :out STD_LOGIC; WDATA :in STD_LOGIC_VECTOR(C_DATA_WIDTH-1 downto 0); WSTRB :in STD_LOGIC_VECTOR(C_DATA_WIDTH/8-1 downto 0); WVALID :in STD_LOGIC; WREADY :out STD_LOGIC; BRESP :out STD_LOGIC_VECTOR(1 downto 0); BVALID :out STD_LOGIC; BREADY :in STD_LOGIC; ARADDR :in STD_LOGIC_VECTOR(C_ADDR_WIDTH-1 downto 0); ARVALID :in STD_LOGIC; ARREADY :out STD_LOGIC; RDATA :out STD_LOGIC_VECTOR(C_DATA_WIDTH-1 downto 0); RRESP :out STD_LOGIC_VECTOR(1 downto 0); RVALID :out STD_LOGIC; RREADY :in STD_LOGIC; interrupt :out STD_LOGIC; -- user signals ap_start :out STD_LOGIC; ap_done :in STD_LOGIC; ap_ready :in STD_LOGIC; ap_idle :in STD_LOGIC; a :out STD_LOGIC_VECTOR(31 downto 0); b :out STD_LOGIC_VECTOR(31 downto 0); c :in STD_LOGIC_VECTOR(31 downto 0); c_ap_vld :in STD_LOGIC); end entity adder_AXI_CTRL_s_axi; --------------------------Address Info------------------- -- 0x00 : Control signals -- bit 0 - ap_start (Read/Write/SC) -- bit 1 - ap_done (Read/COR) -- bit 2 - ap_idle (Read) -- bit 3 - ap_ready (Read) -- bit 7 - auto_restart (Read/Write) -- others - reserved -- 0x04 : Global Interrupt Enable Register -- bit 0 - Global Interrupt Enable (Read/Write) -- others - reserved -- 0x08 : IP Interrupt Enable Register (Read/Write) -- bit 0 - Channel 0 (ap_done) -- others - reserved -- 0x0c : IP Interrupt Status Register (Read/TOW) -- bit 0 - Channel 0 (ap_done) -- others - reserved -- 0x10 : Data signal of a -- bit 31~0 - a[31:0] (Read/Write) -- 0x14 : reserved -- 0x18 : Data signal of b -- bit 31~0 - b[31:0] (Read/Write) -- 0x1c : reserved -- 0x20 : Data signal of c -- bit 31~0 - c[31:0] (Read) -- 0x24 : Control signal of c -- bit 0 - c_ap_vld (Read/COR) -- others - reserved -- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) architecture behave of adder_AXI_CTRL_s_axi is constant ADDR_BITS : INTEGER := 6; constant ADDR_AP_CTRL : INTEGER :=16#00#; constant ADDR_GIE : INTEGER :=16#04#; constant ADDR_IER : INTEGER :=16#08#; constant ADDR_ISR : INTEGER :=16#0c#; constant ADDR_A_DATA_0 : INTEGER :=16#10#; constant ADDR_A_CTRL : INTEGER :=16#14#; constant ADDR_B_DATA_0 : INTEGER :=16#18#; constant ADDR_B_CTRL : INTEGER :=16#1c#; constant ADDR_C_DATA_0 : INTEGER :=16#20#; constant ADDR_C_CTRL : INTEGER :=16#24#; type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write FSM states signal wstate, wnext, rstate, rnext: states; -- Local signal signal waddr : UNSIGNED(ADDR_BITS-1 downto 0); signal wmask : UNSIGNED(31 downto 0); signal aw_hs : STD_LOGIC; signal w_hs : STD_LOGIC; signal rdata_data : UNSIGNED(31 downto 0); signal ar_hs : STD_LOGIC; signal raddr : UNSIGNED(ADDR_BITS-1 downto 0); signal AWREADY_t : STD_LOGIC; signal WREADY_t : STD_LOGIC; signal ARREADY_t : STD_LOGIC; signal RVALID_t : STD_LOGIC; -- internal registers signal int_ap_idle : STD_LOGIC; signal int_ap_ready : STD_LOGIC; signal int_ap_done : STD_LOGIC; signal int_ap_start : STD_LOGIC; signal int_auto_restart : STD_LOGIC; signal int_gie : STD_LOGIC; signal int_ier : STD_LOGIC; signal int_isr : STD_LOGIC; signal int_a : UNSIGNED(31 downto 0); signal int_b : UNSIGNED(31 downto 0); signal int_c : UNSIGNED(31 downto 0); signal int_c_ap_vld : STD_LOGIC; begin -- axi write AWREADY_t <= '1' when wstate = wridle else '0'; AWREADY <= AWREADY_t; WREADY_t <= '1' when wstate = wrdata else '0'; WREADY <= WREADY_t; BRESP <= "00"; -- OKAY BVALID <= '1' when wstate = wrresp else '0'; wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0)); aw_hs <= AWVALID and AWREADY_t; w_hs <= WVALID and WREADY_t; -- write FSM process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (ARESET = '1') then wstate <= wridle; else wstate <= wnext; end if; end if; end process; process (wstate, AWVALID, WVALID, BREADY) begin case (wstate) is when wridle => if (AWVALID = '1') then wnext <= wrdata; else wnext <= wridle; end if; when wrdata => if (WVALID = '1') then wnext <= wrresp; else wnext <= wrdata; end if; when wrresp => if (BREADY = '1') then wnext <= wridle; else wnext <= wrresp; end if; when others => wnext <= wridle; end case; end process; waddr_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (aw_hs = '1') then waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0)); end if; end if; end process; -- axi read ARREADY_t <= '1' when (rstate = rdidle) else '0'; ARREADY <= ARREADY_t; RDATA <= STD_LOGIC_VECTOR(rdata_data); RRESP <= "00"; -- OKAY RVALID_t <= '1' when (rstate = rddata) else '0'; RVALID <= RVALID_t; ar_hs <= ARVALID and ARREADY_t; raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0)); -- read FSM process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (ARESET = '1') then rstate <= rdidle; else rstate <= rnext; end if; end if; end process; process (rstate, ARVALID, RREADY, RVALID_t) begin case (rstate) is when rdidle => if (ARVALID = '1') then rnext <= rddata; else rnext <= rdidle; end if; when rddata => if (RREADY = '1' and RVALID_t = '1') then rnext <= rdidle; else rnext <= rddata; end if; when others => rnext <= rdidle; end case; end process; rdata_proc : process (ACLK) begin if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then if (ar_hs = '1') then case (TO_INTEGER(raddr)) is when ADDR_AP_CTRL => rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0'); when ADDR_GIE => rdata_data <= (1 => int_gie, others => '0'); when ADDR_IER => rdata_data <= (1 => int_ier, others => '0'); when ADDR_ISR => rdata_data <= (1 => int_isr, others => '0'); when ADDR_A_DATA_0 => rdata_data <= RESIZE(int_a(31 downto 0), 32); when ADDR_B_DATA_0 => rdata_data <= RESIZE(int_b(31 downto 0), 32); when ADDR_C_DATA_0 => rdata_data <= RESIZE(int_c(31 downto 0), 32); when ADDR_C_CTRL => rdata_data <= (0 => int_c_ap_vld, others => '0'); when others => rdata_data <= (others => '0'); end case; end if; end if; end process; -- internal registers interrupt <= int_gie and int_isr; ap_start <= int_ap_start; int_ap_idle <= ap_idle; int_ap_ready <= ap_ready; a <= STD_LOGIC_VECTOR(int_a); b <= STD_LOGIC_VECTOR(int_b); process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_start <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then int_ap_start <= '1'; elsif (ap_done = '1' and int_auto_restart = '1') then int_ap_start <= '1'; -- auto restart else int_ap_start <= '0'; -- self clear end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ap_done <= '0'; elsif (ACLK_EN = '1') then if (ap_done = '1') then int_ap_done <= '1'; elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then int_ap_done <= '0'; -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_auto_restart <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then int_auto_restart <= WDATA(7); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_gie <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then int_gie <= WDATA(0); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_ier <= '0'; elsif (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then int_ier <= WDATA(0); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_isr <= '0'; elsif (ACLK_EN = '1') then if (int_ier = '1' and ap_done = '1') then int_isr <= '1'; elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then int_isr <= int_isr xor WDATA(0); -- toggle on write end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_A_DATA_0) then int_a(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_a(31 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ACLK_EN = '1') then if (w_hs = '1' and waddr = ADDR_B_DATA_0) then int_b(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_b(31 downto 0)); end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_c <= (others => '0'); elsif (ACLK_EN = '1') then if (c_ap_vld = '1') then int_c <= UNSIGNED(c); -- clear on read end if; end if; end if; end process; process (ACLK) begin if (ACLK'event and ACLK = '1') then if (ARESET = '1') then int_c_ap_vld <= '0'; elsif (ACLK_EN = '1') then if (c_ap_vld = '1') then int_c_ap_vld <= '1'; elsif (ar_hs = '1' and raddr = ADDR_C_CTRL) then int_c_ap_vld <= '0'; -- clear on read end if; end if; end if; end process; end architecture behave;

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package cu is -- Control unit input sizes constant OPCODE_SIZE : integer := 6; -- OPCODE field size constant FUNC_SIZE : integer := 11; -- FUNC field size subtype OPCODE_TYPE is std_logic_vector(OPCODE_SIZE - 1 downto 0); -- I-Type instructions constant ITYPE_ADD : OPCODE_TYPE := "001000"; constant ITYPE_AND : OPCODE_TYPE := "001100"; constant ITYPE_OR : OPCODE_TYPE := "001101"; constant ITYPE_SUB : OPCODE_TYPE := "001010"; constant ITYPE_XOR : OPCODE_TYPE := "001110"; constant ITYPE_SLL : OPCODE_TYPE := "010100"; constant ITYPE_SRL : OPCODE_TYPE := "010110"; constant ITYPE_SRA : OPCODE_TYPE := "010111"; constant ITYPE_SEQ : OPCODE_TYPE := "011000"; constant ITYPE_SNE : OPCODE_TYPE := "011001"; constant ITYPE_SGE : OPCODE_TYPE := "011101"; constant ITYPE_SGT : OPCODE_TYPE := "011011"; constant ITYPE_SLE : OPCODE_TYPE := "011100"; constant ITYPE_SLT : OPCODE_TYPE := "011010"; constant ITYPE_SGEU : OPCODE_TYPE := "111101"; constant ITYPE_SGTU : OPCODE_TYPE := "111011"; constant ITYPE_SLEU : OPCODE_TYPE := "111100"; constant ITYPE_SLTU : OPCODE_TYPE := "111010"; constant NOP : OPCODE_TYPE := "010101"; -- Jump [ OPCODE(6) - PCOFFSET(26) ] constant JTYPE_J : OPCODE_TYPE := "000010"; constant JTYPE_JAL : OPCODE_TYPE := "000011"; constant JTYPE_JR : OPCODE_TYPE := "010010"; -- Branch [ OPCODE(6) - REG(5) - PCOFFSET(21) ] constant BTYPE_BEQZ : OPCODE_TYPE := "000100"; constant BTYPE_BNEZ : OPCODE_TYPE := "000101"; -- Memory [ OPCODE(6) - RDISPLACEMENT(5) - REG(5) - DISPLACEMENT(16) ] constant MTYPE_LW : OPCODE_TYPE := "100011"; constant MTYPE_SW : OPCODE_TYPE := "101011"; -- R-Type instruction -> OPCODE field constant RTYPE : OPCODE_TYPE := "000000"; subtype FUNC_TYPE is std_logic_vector(FUNC_SIZE - 1 downto 0); -- R-Type instruction -> FUNC field constant RTYPE_ADD : FUNC_TYPE := "00000100000"; constant RTYPE_AND : FUNC_TYPE := "00000100100"; constant RTYPE_OR : FUNC_TYPE := "00000100101"; constant RTYPE_SUB : FUNC_TYPE := "00000100010"; constant RTYPE_XOR : FUNC_TYPE := "00000100110"; constant RTYPE_SLL : FUNC_TYPE := "00000000100"; constant RTYPE_SRL : FUNC_TYPE := "00000000110"; constant RTYPE_SRA : FUNC_TYPE := "00000000111"; constant RTYPE_SEQ : FUNC_TYPE := "00000101000"; constant RTYPE_SNE : FUNC_TYPE := "00000101001"; constant RTYPE_SGE : FUNC_TYPE := "00000101101"; constant RTYPE_SGT : FUNC_TYPE := "00000101011"; constant RTYPE_SLE : FUNC_TYPE := "00000101100"; constant RTYPE_SLT : FUNC_TYPE := "00000101010"; constant RTYPE_SGEU : FUNC_TYPE := "00000111101"; constant RTYPE_SGTU : FUNC_TYPE := "00000111011"; constant RTYPE_SLEU : FUNC_TYPE := "00000111100"; constant RTYPE_SLTU : FUNC_TYPE := "00000111010"; constant RTYPE_NOP : FUNC_TYPE := "00000000000"; end cu;

package STRSYN is attribute SigDir : string; attribute SigType : string; attribute SigBias : string; end STRSYN; entity sklp is port ( terminal in1: electrical; terminal out1: electrical; terminal vbias4: electrical; terminal gnd: electrical; terminal vdd: electrical; terminal vbias2: electrical; terminal vbias1: electrical; terminal vbias3: electrical; terminal vref: electrical); end sklp; architecture simple of sklp is -- Attributes for Ports attribute SigDir of in1:terminal is "input"; attribute SigType of in1:terminal is "voltage"; attribute SigDir of out1:terminal is "output"; attribute SigType of out1:terminal is "voltage"; attribute SigDir of vbias4:terminal is "reference"; attribute SigType of vbias4:terminal is "voltage"; attribute SigDir of gnd:terminal is "reference"; attribute SigType of gnd:terminal is "current"; attribute SigBias of gnd:terminal is "negative"; attribute SigDir of vdd:terminal is "reference"; attribute SigType of vdd:terminal is "current"; attribute SigBias of vdd:terminal is "positive"; attribute SigDir of vbias2:terminal is "reference"; attribute SigType of vbias2:terminal is "voltage"; attribute SigDir of vbias1:terminal is "reference"; attribute SigType of vbias1:terminal is "voltage"; attribute SigDir of vbias3:terminal is "reference"; attribute SigType of vbias3:terminal is "voltage"; attribute SigDir of vref:terminal is "reference"; attribute SigType of vref:terminal is "current"; attribute SigBias of vref:terminal is "negative"; terminal net1: electrical; terminal net2: electrical; terminal net3: electrical; terminal net4: electrical; terminal net5: electrical; terminal net6: electrical; terminal net7: electrical; terminal net8: electrical; terminal net9: electrical; terminal net10: electrical; begin subnet0_subnet0_subnet0_m1 : entity nmos(behave) generic map( L => Ldiff_0, Ldiff_0init => 1.15e-06, W => Wdiff_0, Wdiff_0init => 3.2e-06, scope => private ) port map( D => net3, G => net1, S => net5 ); subnet0_subnet0_subnet0_m2 : entity nmos(behave) generic map( L => Ldiff_0, Ldiff_0init => 1.15e-06, W => Wdiff_0, Wdiff_0init => 3.2e-06, scope => private ) port map( D => net2, G => out1, S => net5 ); subnet0_subnet0_subnet0_m3 : entity nmos(behave) generic map( L => LBias, LBiasinit => 8e-07, W => W_0, W_0init => 6.775e-05 ) port map( D => net5, G => vbias4, S => gnd ); subnet0_subnet0_subnet0_m4 : entity nmos(behave) generic map( L => Ldiff_0, Ldiff_0init => 1.15e-06, W => Wdiff_0, Wdiff_0init => 3.2e-06, scope => private ) port map( D => net6, G => net1, S => net5 ); subnet0_subnet0_subnet0_m5 : entity nmos(behave) generic map( L => Ldiff_0, Ldiff_0init => 1.15e-06, W => Wdiff_0, Wdiff_0init => 3.2e-06, scope => private ) port map( D => net6, G => out1, S => net5 ); subnet0_subnet0_subnet0_m6 : entity pmos(behave) generic map( L => Lcmdiffp_0, Lcmdiffp_0init => 9.5e-06, W => Wcmdiffp_0, Wcmdiffp_0init => 6.45e-06, scope => private ) port map( D => net6, G => net6, S => vdd ); subnet0_subnet0_subnet0_m7 : entity pmos(behave) generic map( L => Lcmdiffp_0, Lcmdiffp_0init => 9.5e-06, W => Wcmdiffp_0, Wcmdiffp_0init => 6.45e-06, scope => private ) port map( D => net6, G => net6, S => vdd ); subnet0_subnet0_subnet0_m8 : entity pmos(behave) generic map( L => Lcmdiffp_0, Lcmdiffp_0init => 9.5e-06, W => Wcmdiffp_0, Wcmdiffp_0init => 6.45e-06, scope => private ) port map( D => net2, G => net6, S => vdd ); subnet0_subnet0_subnet0_m9 : entity pmos(behave) generic map( L => Lcmdiffp_0, Lcmdiffp_0init => 9.5e-06, W => Wcmdiffp_0, Wcmdiffp_0init => 6.45e-06, scope => private ) port map( D => net3, G => net6, S => vdd ); subnet0_subnet0_subnet1_m1 : entity nmos(behave) generic map( L => Lsrc, Lsrcinit => 2.65e-06, W => Wsrc_2, Wsrc_2init => 1.22e-05, scope => Wprivate, symmetry_scope => sym_5 ) port map( D => net4, G => net2, S => gnd ); subnet0_subnet0_subnet2_m1 : entity nmos(behave) generic map( L => Lsrc, Lsrcinit => 2.65e-06, W => Wsrc_2, Wsrc_2init => 1.22e-05, scope => Wprivate, symmetry_scope => sym_5 ) port map( D => out1, G => net3, S => gnd ); subnet0_subnet0_subnet3_m1 : entity pmos(behave) generic map( L => LBias, LBiasinit => 8e-07, W => Wcmcasc_1, Wcmcasc_1init => 3.52e-05, scope => Wprivate ) port map( D => net4, G => vbias2, S => net7 ); subnet0_subnet0_subnet3_m2 : entity pmos(behave) generic map( L => Lcm_1, Lcm_1init => 6.5e-07, W => Wcm_1, Wcm_1init => 7.3e-06, scope => private ) port map( D => net7, G => net4, S => vdd ); subnet0_subnet0_subnet3_m3 : entity pmos(behave) generic map( L => Lcm_1, Lcm_1init => 6.5e-07, W => Wcmout_1, Wcmout_1init => 5.605e-05, scope => private ) port map( D => net8, G => net4, S => vdd ); subnet0_subnet0_subnet3_m4 : entity pmos(behave) generic map( L => LBias, LBiasinit => 8e-07, W => Wcmcasc_1, Wcmcasc_1init => 3.52e-05, scope => Wprivate ) port map( D => out1, G => vbias2, S => net8 ); subnet0_subnet1_subnet0_m1 : entity pmos(behave) generic map( L => LBias, LBiasinit => 8e-07, W => (pfak)*(WBias), WBiasinit => 9.55e-06 ) port map( D => vbias1, G => vbias1, S => vdd ); subnet0_subnet1_subnet0_m2 : entity pmos(behave) generic map( L => (pfak)*(LBias), LBiasinit => 8e-07, W => (pfak)*(WBias), WBiasinit => 9.55e-06 ) port map( D => vbias2, G => vbias2, S => vbias1 ); subnet0_subnet1_subnet0_i1 : entity idc(behave) generic map( I => 1.145e-05 ) port map( P => vdd, N => vbias3 ); subnet0_subnet1_subnet0_m3 : entity nmos(behave) generic map( L => (pfak)*(LBias), LBiasinit => 8e-07, W => WBias, WBiasinit => 9.55e-06 ) port map( D => vbias3, G => vbias3, S => vbias4 ); subnet0_subnet1_subnet0_m4 : entity nmos(behave) generic map( L => LBias, LBiasinit => 8e-07, W => WBias, WBiasinit => 9.55e-06 ) port map( D => vbias2, G => vbias3, S => net9 ); subnet0_subnet1_subnet0_m5 : entity nmos(behave) generic map( L => LBias, LBiasinit => 8e-07, W => WBias, WBiasinit => 9.55e-06 ) port map( D => vbias4, G => vbias4, S => gnd ); subnet0_subnet1_subnet0_m6 : entity nmos(behave) generic map( L => LBias, LBiasinit => 8e-07, W => WBias, WBiasinit => 9.55e-06 ) port map( D => net9, G => vbias4, S => gnd ); subnet1_subnet0_r1 : entity res(behave) generic map( R => 200000 ) port map( P => net10, N => in1 ); subnet1_subnet0_r2 : entity res(behave) generic map( R => 603000 ) port map( P => net10, N => net1 ); subnet1_subnet0_c2 : entity cap(behave) generic map( C => 1.07e-11 ) port map( P => net10, N => out1 ); subnet1_subnet0_c1 : entity cap(behave) generic map( C => 4e-12 ) port map( P => net1, N => vref ); end simple;

--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.std_logic_misc.all; use work.component_pack.all; entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping generic ( DATA_WIDTH: integer := 32; current_address : integer := 0; Rxy_rst : integer := 10; Cx_rst : integer := 10; healthy_counter_threshold : integer := 8; faulty_counter_threshold: integer := 2; counter_depth: integer := 4; NoC_size: integer := 4 ); port ( reset, clk: in std_logic; RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0); credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic; valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic; valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic; credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic; TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0); Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic; Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic; -- should be connected to NI (Outputs for classified fault information) link_faults: out std_logic_vector(4 downto 0); turn_faults: out std_logic_vector(19 downto 0); Rxy_reconf_PE: in std_logic_vector(7 downto 0); Cx_reconf_PE: in std_logic_vector(3 downto 0); Reconfig_command : in std_logic; -- fault injector shift register with serial input signals TCK: in std_logic; SE: in std_logic; -- shift enable UE: in std_logic; -- update enable SI: in std_logic; -- serial Input SO: out std_logic; -- serial output ---- Outputs for non-classified fault information link_faults_async: out std_logic_vector(4 downto 0); turn_faults_async: out std_logic_vector(19 downto 0) ); end router_credit_based_PD_C_SHMU; architecture behavior of router_credit_based_PD_C_SHMU is ------------------------------- -- Added because of Checkers -- ------------------------------- --signal combined_error_signals: std_logic_vector(19 downto 0); -- Shall we only consider this for the 20 bits showing the turn faults or individual checkers ?! --signal shift_parallel_data: std_logic_vector(19 downto 0); ------------------------------- ------------------------------- signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0); -- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic; signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic; signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic; signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic; signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic; signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic; signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic; signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic; signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic; signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic; signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic; signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0); signal LBDR_Fault_N, LBDR_Fault_E, LBDR_Fault_W, LBDR_Fault_S, LBDR_Fault_L: std_logic; signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic; signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic; signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic; -- Signals related to link fault classification modules signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic; signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic; signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic; -- Signals related to Control part checkers fault classification modules signal Healthy_N2E_turn_fault, intermittent_N2E_turn_fault, faulty_N2E_turn_fault: std_logic; signal Healthy_N2W_turn_fault, intermittent_N2W_turn_fault, faulty_N2W_turn_fault: std_logic; signal Healthy_E2N_turn_fault, intermittent_E2N_turn_fault, faulty_E2N_turn_fault: std_logic; signal Healthy_E2S_turn_fault, intermittent_E2S_turn_fault, faulty_E2S_turn_fault: std_logic; signal Healthy_W2N_turn_fault, intermittent_W2N_turn_fault, faulty_W2N_turn_fault: std_logic; signal Healthy_W2S_turn_fault, intermittent_W2S_turn_fault, faulty_W2S_turn_fault: std_logic; signal Healthy_S2E_turn_fault, intermittent_S2E_turn_fault, faulty_S2E_turn_fault: std_logic; signal Healthy_S2W_turn_fault, intermittent_S2W_turn_fault, faulty_S2W_turn_fault: std_logic; signal Healthy_N2S_path_fault, intermittent_N2S_path_fault, faulty_N2S_path_fault: std_logic; signal Healthy_S2N_path_fault, intermittent_S2N_path_fault, faulty_S2N_path_fault: std_logic; signal Healthy_E2W_path_fault, intermittent_E2W_path_fault, faulty_E2W_path_fault: std_logic; signal Healthy_W2E_path_fault, intermittent_W2E_path_fault, faulty_W2E_path_fault: std_logic; signal Healthy_L2N_fault, intermittent_L2N_fault, faulty_L2N_fault: std_logic; signal Healthy_L2E_fault, intermittent_L2E_fault, faulty_L2E_fault: std_logic; signal Healthy_L2W_fault, intermittent_L2W_fault, faulty_L2W_fault: std_logic; signal Healthy_L2S_fault, intermittent_L2S_fault, faulty_L2S_fault: std_logic; signal Healthy_N2L_fault, intermittent_N2L_fault, faulty_N2L_fault: std_logic; signal Healthy_E2L_fault, intermittent_E2L_fault, faulty_E2L_fault: std_logic; signal Healthy_W2L_fault, intermittent_W2L_fault, faulty_W2L_fault: std_logic; signal Healthy_S2L_fault, intermittent_S2L_fault, faulty_S2L_fault: std_logic; -- Signals needed for control part checkers -- Signals needed for LBDR packet drop checkers -- North signal N_err_header_empty_Requests_FF_Requests_in, N_err_tail_Requests_in_all_zero, N_err_tail_empty_Requests_FF_Requests_in, N_err_tail_not_empty_not_grants_Requests_FF_Requests_in, N_err_grants_onehot, N_err_grants_mismatch, N_err_header_tail_Requests_FF_Requests_in, N_err_dst_addr_cur_addr_N1, N_err_dst_addr_cur_addr_not_N1, N_err_dst_addr_cur_addr_E1, N_err_dst_addr_cur_addr_not_E1, N_err_dst_addr_cur_addr_W1, N_err_dst_addr_cur_addr_not_W1, N_err_dst_addr_cur_addr_S1, N_err_dst_addr_cur_addr_not_S1, N_err_dst_addr_cur_addr_Req_L_in, N_err_dst_addr_cur_addr_not_Req_L_in, N_err_header_not_empty_faulty_drop_packet_in, -- added according to new design N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design N_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --N_err_header_not_empty_Req_L_in, -- added according to new design N_err_header_not_empty_Req_N_in, N_err_header_not_empty_Req_E_in, N_err_header_not_empty_Req_W_in, N_err_header_not_empty_Req_S_in, N_err_header_empty_packet_drop_in_packet_drop_equal, N_err_tail_not_empty_packet_drop_not_packet_drop_in, N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, N_err_packet_drop_order, N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- East E_err_header_empty_Requests_FF_Requests_in, E_err_tail_Requests_in_all_zero, E_err_tail_empty_Requests_FF_Requests_in, E_err_tail_not_empty_not_grants_Requests_FF_Requests_in, E_err_grants_onehot, E_err_grants_mismatch, E_err_header_tail_Requests_FF_Requests_in, E_err_dst_addr_cur_addr_N1, E_err_dst_addr_cur_addr_not_N1, E_err_dst_addr_cur_addr_E1, E_err_dst_addr_cur_addr_not_E1, E_err_dst_addr_cur_addr_W1, E_err_dst_addr_cur_addr_not_W1, E_err_dst_addr_cur_addr_S1, E_err_dst_addr_cur_addr_not_S1, E_err_dst_addr_cur_addr_Req_L_in, E_err_dst_addr_cur_addr_not_Req_L_in, E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --E_err_header_not_empty_Req_L_in, -- added according to new design E_err_header_not_empty_Req_N_in, E_err_header_not_empty_Req_E_in, E_err_header_not_empty_Req_W_in, E_err_header_not_empty_Req_S_in, E_err_header_empty_packet_drop_in_packet_drop_equal, E_err_tail_not_empty_packet_drop_not_packet_drop_in, E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, E_err_packet_drop_order, E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- West W_err_header_empty_Requests_FF_Requests_in, W_err_tail_Requests_in_all_zero, W_err_tail_empty_Requests_FF_Requests_in, W_err_tail_not_empty_not_grants_Requests_FF_Requests_in, W_err_grants_onehot, W_err_grants_mismatch, W_err_header_tail_Requests_FF_Requests_in, W_err_dst_addr_cur_addr_N1, W_err_dst_addr_cur_addr_not_N1, W_err_dst_addr_cur_addr_E1, W_err_dst_addr_cur_addr_not_E1, W_err_dst_addr_cur_addr_W1, W_err_dst_addr_cur_addr_not_W1, W_err_dst_addr_cur_addr_S1, W_err_dst_addr_cur_addr_not_S1, W_err_dst_addr_cur_addr_Req_L_in, W_err_dst_addr_cur_addr_not_Req_L_in, W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --W_err_header_not_empty_Req_L_in, -- added according to new design W_err_header_not_empty_Req_N_in, W_err_header_not_empty_Req_E_in, W_err_header_not_empty_Req_W_in, W_err_header_not_empty_Req_S_in, W_err_header_empty_packet_drop_in_packet_drop_equal, W_err_tail_not_empty_packet_drop_not_packet_drop_in, W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, W_err_packet_drop_order, W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- South S_err_header_empty_Requests_FF_Requests_in, S_err_tail_Requests_in_all_zero, S_err_tail_empty_Requests_FF_Requests_in, S_err_tail_not_empty_not_grants_Requests_FF_Requests_in, S_err_grants_onehot, S_err_grants_mismatch, S_err_header_tail_Requests_FF_Requests_in, S_err_dst_addr_cur_addr_N1, S_err_dst_addr_cur_addr_not_N1, S_err_dst_addr_cur_addr_E1, S_err_dst_addr_cur_addr_not_E1, S_err_dst_addr_cur_addr_W1, S_err_dst_addr_cur_addr_not_W1, S_err_dst_addr_cur_addr_S1, S_err_dst_addr_cur_addr_not_S1, S_err_dst_addr_cur_addr_Req_L_in, S_err_dst_addr_cur_addr_not_Req_L_in, S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --S_err_header_not_empty_Req_L_in, -- added according to new design S_err_header_not_empty_Req_N_in, S_err_header_not_empty_Req_E_in, S_err_header_not_empty_Req_W_in, S_err_header_not_empty_Req_S_in, S_err_header_empty_packet_drop_in_packet_drop_equal, S_err_tail_not_empty_packet_drop_not_packet_drop_in, S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, S_err_packet_drop_order, S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal, -- Local L_err_header_empty_Requests_FF_Requests_in, L_err_tail_Requests_in_all_zero, L_err_tail_empty_Requests_FF_Requests_in, L_err_tail_not_empty_not_grants_Requests_FF_Requests_in, L_err_grants_onehot, L_err_grants_mismatch, L_err_header_tail_Requests_FF_Requests_in, L_err_dst_addr_cur_addr_N1, L_err_dst_addr_cur_addr_not_N1, L_err_dst_addr_cur_addr_E1, L_err_dst_addr_cur_addr_not_E1, L_err_dst_addr_cur_addr_W1, L_err_dst_addr_cur_addr_not_W1, L_err_dst_addr_cur_addr_S1, L_err_dst_addr_cur_addr_not_S1, L_err_dst_addr_cur_addr_Req_L_in, L_err_dst_addr_cur_addr_not_Req_L_in, L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --L_err_header_not_empty_Req_L_in, -- added according to new design L_err_header_not_empty_Req_N_in, L_err_header_not_empty_Req_E_in, L_err_header_not_empty_Req_W_in, L_err_header_not_empty_Req_S_in, L_err_header_empty_packet_drop_in_packet_drop_equal, L_err_tail_not_empty_packet_drop_not_packet_drop_in, L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, L_err_packet_drop_order, L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, -- Added L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal: std_logic; ------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------ -- Signals needed for FIFO packet drop with fault classifier support checkers -- North -- Functional checkers signal N_err_empty_full, N_err_empty_read_en, N_err_full_write_en, N_err_state_in_onehot, N_err_read_pointer_in_onehot, N_err_write_pointer_in_onehot, -- Structural checkers N_err_write_en_write_pointer, N_err_not_write_en_write_pointer, N_err_read_pointer_write_pointer_not_empty, N_err_read_pointer_write_pointer_empty, N_err_read_pointer_write_pointer_not_full, N_err_read_pointer_write_pointer_full, N_err_read_pointer_increment, N_err_read_pointer_not_increment, N_err_write_en, N_err_not_write_en, N_err_not_write_en1, N_err_not_write_en2, N_err_read_en_mismatch, N_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! N_err_fake_credit_read_en_fake_credit_counter_in_increment, N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, N_err_fake_credit_read_en_credit_out, N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, N_err_state_out_Idle_not_fault_out_not_fake_credit, N_err_state_out_Idle_not_fault_out_not_fault_info_in, N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, N_err_state_out_Idle_fault_out_fake_credit, N_err_state_out_Idle_fault_out_state_in_Packet_drop, N_err_state_out_Idle_fault_out_fault_info_in, N_err_state_out_Idle_fault_out_faulty_packet_in, N_err_state_out_Idle_not_health_info, N_err_state_out_Idle_not_write_fake_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Header_flit_not_valid_in_not_fault_info_in, N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, N_err_state_out_Header_flit_or_Body_flit_not_fake_credit, N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, N_err_state_out_Body_flit_valid_in_not_fault_out_health_info, N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Body_flit_not_valid_in_not_fault_info_in, N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, N_err_state_out_Body_flit_valid_in_fault_out_not_health_info, N_err_state_out_Body_flit_valid_in_not_health_info, N_err_state_out_Body_flit_not_fake_credit, N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, N_err_state_out_Tail_flit_not_valid_in_state_in_Idle, N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, N_err_state_out_Tail_flit_not_valid_in_not_fake_credit, N_err_state_out_Tail_flit_not_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, N_err_fault_info_fault_info_out_equal, N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- East -- Functional checkers E_err_empty_full, E_err_empty_read_en, E_err_full_write_en, E_err_state_in_onehot, E_err_read_pointer_in_onehot, E_err_write_pointer_in_onehot, -- Structural checkers E_err_write_en_write_pointer, E_err_not_write_en_write_pointer, E_err_read_pointer_write_pointer_not_empty, E_err_read_pointer_write_pointer_empty, E_err_read_pointer_write_pointer_not_full, E_err_read_pointer_write_pointer_full, E_err_read_pointer_increment, E_err_read_pointer_not_increment, E_err_write_en, E_err_not_write_en, E_err_not_write_en1, E_err_not_write_en2, E_err_read_en_mismatch, E_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! E_err_fake_credit_read_en_fake_credit_counter_in_increment, E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, E_err_fake_credit_read_en_credit_out, E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, E_err_state_out_Idle_not_fault_out_not_fake_credit, E_err_state_out_Idle_not_fault_out_not_fault_info_in, E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, E_err_state_out_Idle_fault_out_fake_credit, E_err_state_out_Idle_fault_out_state_in_Packet_drop, E_err_state_out_Idle_fault_out_fault_info_in, E_err_state_out_Idle_fault_out_faulty_packet_in, E_err_state_out_Idle_not_health_info, E_err_state_out_Idle_not_write_fake_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Header_flit_not_valid_in_not_fault_info_in, E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, E_err_state_out_Header_flit_or_Body_flit_not_fake_credit, E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, E_err_state_out_Body_flit_valid_in_not_fault_out_health_info, E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Body_flit_not_valid_in_not_fault_info_in, E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, E_err_state_out_Body_flit_valid_in_fault_out_not_health_info, E_err_state_out_Body_flit_valid_in_not_health_info, E_err_state_out_Body_flit_not_fake_credit, E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, E_err_state_out_Tail_flit_not_valid_in_state_in_Idle, E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, E_err_state_out_Tail_flit_not_valid_in_not_fake_credit, E_err_state_out_Tail_flit_not_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, E_err_fault_info_fault_info_out_equal, E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- West -- Functional checkers W_err_empty_full, W_err_empty_read_en, W_err_full_write_en, W_err_state_in_onehot, W_err_read_pointer_in_onehot, W_err_write_pointer_in_onehot, -- Structural checkers W_err_write_en_write_pointer, W_err_not_write_en_write_pointer, W_err_read_pointer_write_pointer_not_empty, W_err_read_pointer_write_pointer_empty, W_err_read_pointer_write_pointer_not_full, W_err_read_pointer_write_pointer_full, W_err_read_pointer_increment, W_err_read_pointer_not_increment, W_err_write_en, W_err_not_write_en, W_err_not_write_en1, W_err_not_write_en2, W_err_read_en_mismatch, W_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! W_err_fake_credit_read_en_fake_credit_counter_in_increment, W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, W_err_fake_credit_read_en_credit_out, W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, W_err_state_out_Idle_not_fault_out_not_fake_credit, W_err_state_out_Idle_not_fault_out_not_fault_info_in, W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, W_err_state_out_Idle_fault_out_fake_credit, W_err_state_out_Idle_fault_out_state_in_Packet_drop, W_err_state_out_Idle_fault_out_fault_info_in, W_err_state_out_Idle_fault_out_faulty_packet_in, W_err_state_out_Idle_not_health_info, W_err_state_out_Idle_not_write_fake_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Header_flit_not_valid_in_not_fault_info_in, W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, W_err_state_out_Header_flit_or_Body_flit_not_fake_credit, W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, W_err_state_out_Body_flit_valid_in_not_fault_out_health_info, W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Body_flit_not_valid_in_not_fault_info_in, W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, W_err_state_out_Body_flit_valid_in_fault_out_not_health_info, W_err_state_out_Body_flit_valid_in_not_health_info, W_err_state_out_Body_flit_not_fake_credit, W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, W_err_state_out_Tail_flit_not_valid_in_state_in_Idle, W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, W_err_state_out_Tail_flit_not_valid_in_not_fake_credit, W_err_state_out_Tail_flit_not_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, W_err_fault_info_fault_info_out_equal, W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- South -- Functional checkers S_err_empty_full, S_err_empty_read_en, S_err_full_write_en, S_err_state_in_onehot, S_err_read_pointer_in_onehot, S_err_write_pointer_in_onehot, -- Structural checkers S_err_write_en_write_pointer, S_err_not_write_en_write_pointer, S_err_read_pointer_write_pointer_not_empty, S_err_read_pointer_write_pointer_empty, S_err_read_pointer_write_pointer_not_full, S_err_read_pointer_write_pointer_full, S_err_read_pointer_increment, S_err_read_pointer_not_increment, S_err_write_en, S_err_not_write_en, S_err_not_write_en1, S_err_not_write_en2, S_err_read_en_mismatch, S_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! S_err_fake_credit_read_en_fake_credit_counter_in_increment, S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, S_err_fake_credit_read_en_credit_out, S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, S_err_state_out_Idle_not_fault_out_not_fake_credit, S_err_state_out_Idle_not_fault_out_not_fault_info_in, S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, S_err_state_out_Idle_fault_out_fake_credit, S_err_state_out_Idle_fault_out_state_in_Packet_drop, S_err_state_out_Idle_fault_out_fault_info_in, S_err_state_out_Idle_fault_out_faulty_packet_in, S_err_state_out_Idle_not_health_info, S_err_state_out_Idle_not_write_fake_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Header_flit_not_valid_in_not_fault_info_in, S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, S_err_state_out_Header_flit_or_Body_flit_not_fake_credit, S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, S_err_state_out_Body_flit_valid_in_not_fault_out_health_info, S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Body_flit_not_valid_in_not_fault_info_in, S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, S_err_state_out_Body_flit_valid_in_fault_out_not_health_info, S_err_state_out_Body_flit_valid_in_not_health_info, S_err_state_out_Body_flit_not_fake_credit, S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, S_err_state_out_Tail_flit_not_valid_in_state_in_Idle, S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, S_err_state_out_Tail_flit_not_valid_in_not_fake_credit, S_err_state_out_Tail_flit_not_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, S_err_fault_info_fault_info_out_equal, S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in, -- Local -- Functional checkers L_err_empty_full, L_err_empty_read_en, L_err_full_write_en, L_err_state_in_onehot, L_err_read_pointer_in_onehot, L_err_write_pointer_in_onehot, -- Structural checkers L_err_write_en_write_pointer, L_err_not_write_en_write_pointer, L_err_read_pointer_write_pointer_not_empty, L_err_read_pointer_write_pointer_empty, L_err_read_pointer_write_pointer_not_full, L_err_read_pointer_write_pointer_full, L_err_read_pointer_increment, L_err_read_pointer_not_increment, L_err_write_en, L_err_not_write_en, L_err_not_write_en1, L_err_not_write_en2, L_err_read_en_mismatch, L_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! L_err_fake_credit_read_en_fake_credit_counter_in_increment, L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, L_err_fake_credit_read_en_credit_out, L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, L_err_state_out_Idle_not_fault_out_not_fake_credit, L_err_state_out_Idle_not_fault_out_not_fault_info_in, L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, L_err_state_out_Idle_fault_out_fake_credit, L_err_state_out_Idle_fault_out_state_in_Packet_drop, L_err_state_out_Idle_fault_out_fault_info_in, L_err_state_out_Idle_fault_out_faulty_packet_in, L_err_state_out_Idle_not_health_info, L_err_state_out_Idle_not_write_fake_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Header_flit_not_valid_in_not_fault_info_in, L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, L_err_state_out_Header_flit_or_Body_flit_not_fake_credit, L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, L_err_state_out_Body_flit_valid_in_not_fault_out_health_info, L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Body_flit_not_valid_in_not_fault_info_in, L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, L_err_state_out_Body_flit_valid_in_fault_out_not_health_info, L_err_state_out_Body_flit_valid_in_not_health_info, L_err_state_out_Body_flit_not_fake_credit, L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, L_err_state_out_Tail_flit_not_valid_in_state_in_Idle, L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, L_err_state_out_Tail_flit_not_valid_in_not_fake_credit, L_err_state_out_Tail_flit_not_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, L_err_fault_info_fault_info_out_equal, L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in: std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Signals needed for Allocator unit -- Allocator logic checker outputs -- Might need to be changed ?! signal err_grant_N_N_sig_not_empty_N_grant_N_N, err_not_grant_N_N_sig_or_empty_N_not_grant_N_N, err_grant_N_E_sig_not_empty_E_grant_N_E, err_not_grant_N_E_sig_or_empty_E_not_grant_N_E, err_grant_N_W_sig_not_empty_W_grant_N_W, err_not_grant_N_W_sig_or_empty_W_not_grant_N_W, err_grant_N_S_sig_not_empty_S_grant_N_S, err_not_grant_N_S_sig_or_empty_S_not_grant_N_S, err_grant_N_L_sig_not_empty_L_grant_N_L, err_not_grant_N_L_sig_or_empty_L_not_grant_N_L, err_grant_E_N_sig_not_empty_N_grant_E_N, err_not_grant_E_N_sig_or_empty_N_not_grant_E_N, err_grant_E_E_sig_not_empty_E_grant_E_E, err_not_grant_E_E_sig_or_empty_E_not_grant_E_E, err_grant_E_W_sig_not_empty_W_grant_E_W, err_not_grant_E_W_sig_or_empty_W_not_grant_E_W, err_grant_E_S_sig_not_empty_S_grant_E_S, err_not_grant_E_S_sig_or_empty_S_not_grant_E_S, err_grant_E_L_sig_not_empty_L_grant_E_L, err_not_grant_E_L_sig_or_empty_L_not_grant_E_L, err_grant_W_N_sig_not_empty_N_grant_W_N, err_not_grant_W_N_sig_or_empty_N_not_grant_W_N, err_grant_W_E_sig_not_empty_E_grant_W_E, err_not_grant_W_E_sig_or_empty_E_not_grant_W_E, err_grant_W_W_sig_not_empty_W_grant_W_W, err_not_grant_W_W_sig_or_empty_W_not_grant_W_W, err_grant_W_S_sig_not_empty_S_grant_W_S, err_not_grant_W_S_sig_or_empty_S_not_grant_W_S, err_grant_W_L_sig_not_empty_L_grant_W_L, err_not_grant_W_L_sig_or_empty_L_not_grant_W_L, err_grant_S_N_sig_not_empty_N_grant_S_N, err_not_grant_S_N_sig_or_empty_N_not_grant_S_N, err_grant_S_E_sig_not_empty_E_grant_S_E, err_not_grant_S_E_sig_or_empty_E_not_grant_S_E, err_grant_S_W_sig_not_empty_W_grant_S_W, err_not_grant_S_W_sig_or_empty_W_not_grant_S_W, err_grant_S_S_sig_not_empty_S_grant_S_S, err_not_grant_S_S_sig_or_empty_S_not_grant_S_S, err_grant_S_L_sig_not_empty_L_grant_S_L, err_not_grant_S_L_sig_or_empty_L_not_grant_S_L, err_grant_L_N_sig_not_empty_N_grant_L_N, err_not_grant_L_N_sig_or_empty_N_not_grant_L_N, err_grant_L_E_sig_not_empty_E_grant_L_E, err_not_grant_L_E_sig_or_empty_E_not_grant_L_E, err_grant_L_W_sig_not_empty_W_grant_L_W, err_not_grant_L_W_sig_or_empty_W_not_grant_L_W, err_grant_L_S_sig_not_empty_S_grant_L_S, err_not_grant_L_S_sig_or_empty_S_not_grant_L_S, err_grant_L_L_sig_not_empty_L_grant_L_L, err_not_grant_L_L_sig_or_empty_L_not_grant_L_L, err_grant_signals_not_empty_grant_N, err_not_grant_signals_empty_not_grant_N, err_grant_signals_not_empty_grant_E, err_not_grant_signals_empty_not_grant_E, err_grant_signals_not_empty_grant_W, err_not_grant_signals_empty_not_grant_W, err_grant_signals_not_empty_grant_S, err_not_grant_signals_empty_not_grant_S, err_grant_signals_not_empty_grant_L, err_not_grant_signals_empty_not_grant_L, err_grants_valid_not_match: std_logic; -- Allocator credit_counter logic checker outputs signal err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_N_credit_counter_N_out_increment, err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change, err_grant_N_credit_counter_N_out_decrement, err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change, err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal, err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_E_credit_counter_E_out_increment, err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change, err_grant_E_credit_counter_E_out_decrement, err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change, err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal, err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_W_credit_counter_W_out_increment, err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change, err_grant_W_credit_counter_W_out_decrement, err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change, err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal, err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_S_credit_counter_S_out_increment, err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change, err_grant_S_credit_counter_S_out_decrement, err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change, err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal, err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal, err_credit_in_L_credit_counter_L_out_increment, err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change, err_grant_L_credit_counter_L_out_decrement, err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change, err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Arbiter_in Checker signals (part of allocator unit) -- North Arbiter_in checker outputs signal N_err_Requests_state_in_state_not_equal, N_err_IDLE_Req_N, N_err_IDLE_grant_N,N_err_North_Req_N, N_err_North_grant_N, N_err_East_Req_E, N_err_East_grant_E, N_err_West_Req_W, N_err_West_grant_W, N_err_South_Req_S,N_err_South_grant_S,N_err_Local_Req_L, N_err_Local_grant_L, N_err_IDLE_Req_E, N_err_IDLE_grant_E, N_err_North_Req_E, N_err_North_grant_E, N_err_East_Req_W, N_err_East_grant_W, N_err_West_Req_S, N_err_West_grant_S, N_err_South_Req_L, N_err_South_grant_L, N_err_Local_Req_N, N_err_Local_grant_N, N_err_IDLE_Req_W, N_err_IDLE_grant_W, N_err_North_Req_W, N_err_North_grant_W, N_err_East_Req_S, N_err_East_grant_S, N_err_West_Req_L, N_err_West_grant_L, N_err_South_Req_N, N_err_South_grant_N, N_err_Local_Req_E, N_err_Local_grant_E, N_err_IDLE_Req_S, N_err_IDLE_grant_S, N_err_North_Req_S, N_err_North_grant_S, N_err_East_Req_L, N_err_East_grant_L, N_err_West_Req_N, N_err_West_grant_N, N_err_South_Req_E, N_err_South_grant_E, N_err_Local_Req_W, N_err_Local_grant_W, N_err_IDLE_Req_L, N_err_IDLE_grant_L, N_err_North_Req_L, N_err_North_grant_L, N_err_East_Req_N, N_err_East_grant_N, N_err_West_Req_E, N_err_West_grant_E, N_err_South_Req_W, N_err_South_grant_W, N_err_Local_Req_S, N_err_Local_grant_S, N_err_arbiter_state_in_onehot, N_err_no_request_grants, N_err_request_no_grants, N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L, -- East Arbiter_in checker outputs E_err_Requests_state_in_state_not_equal, E_err_IDLE_Req_N, E_err_IDLE_grant_N, E_err_North_Req_N, E_err_North_grant_N, E_err_East_Req_E, E_err_East_grant_E, E_err_West_Req_W, E_err_West_grant_W, E_err_South_Req_S, E_err_South_grant_S, E_err_Local_Req_L, E_err_Local_grant_L, E_err_IDLE_Req_E, E_err_IDLE_grant_E, E_err_North_Req_E, E_err_North_grant_E, E_err_East_Req_W, E_err_East_grant_W, E_err_West_Req_S, E_err_West_grant_S, E_err_South_Req_L, E_err_South_grant_L, E_err_Local_Req_N, E_err_Local_grant_N, E_err_IDLE_Req_W, E_err_IDLE_grant_W, E_err_North_Req_W, E_err_North_grant_W, E_err_East_Req_S, E_err_East_grant_S, E_err_West_Req_L, E_err_West_grant_L, E_err_South_Req_N, E_err_South_grant_N, E_err_Local_Req_E, E_err_Local_grant_E, E_err_IDLE_Req_S, E_err_IDLE_grant_S, E_err_North_Req_S, E_err_North_grant_S, E_err_East_Req_L, E_err_East_grant_L, E_err_West_Req_N, E_err_West_grant_N, E_err_South_Req_E, E_err_South_grant_E, E_err_Local_Req_W, E_err_Local_grant_W, E_err_IDLE_Req_L, E_err_IDLE_grant_L, E_err_North_Req_L, E_err_North_grant_L, E_err_East_Req_N, E_err_East_grant_N, E_err_West_Req_E, E_err_West_grant_E, E_err_South_Req_W, E_err_South_grant_W, E_err_Local_Req_S, E_err_Local_grant_S, E_err_arbiter_state_in_onehot, E_err_no_request_grants, E_err_request_no_grants, E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L, -- West Arbiter_in checker outputs W_err_Requests_state_in_state_not_equal, W_err_IDLE_Req_N, W_err_IDLE_grant_N, W_err_North_Req_N, W_err_North_grant_N, W_err_East_Req_E, W_err_East_grant_E, W_err_West_Req_W, W_err_West_grant_W, W_err_South_Req_S, W_err_South_grant_S, W_err_Local_Req_L, W_err_Local_grant_L, W_err_IDLE_Req_E, W_err_IDLE_grant_E, W_err_North_Req_E, W_err_North_grant_E, W_err_East_Req_W, W_err_East_grant_W, W_err_West_Req_S, W_err_West_grant_S, W_err_South_Req_L, W_err_South_grant_L, W_err_Local_Req_N, W_err_Local_grant_N, W_err_IDLE_Req_W, W_err_IDLE_grant_W, W_err_North_Req_W, W_err_North_grant_W, W_err_East_Req_S, W_err_East_grant_S, W_err_West_Req_L, W_err_West_grant_L, W_err_South_Req_N, W_err_South_grant_N, W_err_Local_Req_E, W_err_Local_grant_E, W_err_IDLE_Req_S, W_err_IDLE_grant_S, W_err_North_Req_S, W_err_North_grant_S, W_err_East_Req_L, W_err_East_grant_L, W_err_West_Req_N, W_err_West_grant_N, W_err_South_Req_E, W_err_South_grant_E, W_err_Local_Req_W, W_err_Local_grant_W, W_err_IDLE_Req_L, W_err_IDLE_grant_L, W_err_North_Req_L, W_err_North_grant_L, W_err_East_Req_N, W_err_East_grant_N, W_err_West_Req_E, W_err_West_grant_E, W_err_South_Req_W, W_err_South_grant_W, W_err_Local_Req_S, W_err_Local_grant_S, W_err_arbiter_state_in_onehot, W_err_no_request_grants, W_err_request_no_grants, W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L, -- South Arbiter_in checker outputs S_err_Requests_state_in_state_not_equal, S_err_IDLE_Req_N, S_err_IDLE_grant_N,S_err_North_Req_N, S_err_North_grant_N, S_err_East_Req_E, S_err_East_grant_E, S_err_West_Req_W, S_err_West_grant_W, S_err_South_Req_S,S_err_South_grant_S,S_err_Local_Req_L, S_err_Local_grant_L, S_err_IDLE_Req_E, S_err_IDLE_grant_E, S_err_North_Req_E, S_err_North_grant_E, S_err_East_Req_W, S_err_East_grant_W, S_err_West_Req_S, S_err_West_grant_S, S_err_South_Req_L, S_err_South_grant_L, S_err_Local_Req_N, S_err_Local_grant_N, S_err_IDLE_Req_W, S_err_IDLE_grant_W, S_err_North_Req_W, S_err_North_grant_W, S_err_East_Req_S, S_err_East_grant_S, S_err_West_Req_L, S_err_West_grant_L, S_err_South_Req_N, S_err_South_grant_N, S_err_Local_Req_E, S_err_Local_grant_E, S_err_IDLE_Req_S, S_err_IDLE_grant_S, S_err_North_Req_S, S_err_North_grant_S, S_err_East_Req_L, S_err_East_grant_L, S_err_West_Req_N, S_err_West_grant_N, S_err_South_Req_E, S_err_South_grant_E, S_err_Local_Req_W, S_err_Local_grant_W, S_err_IDLE_Req_L, S_err_IDLE_grant_L, S_err_North_Req_L, S_err_North_grant_L, S_err_East_Req_N, S_err_East_grant_N, S_err_West_Req_E, S_err_West_grant_E, S_err_South_Req_W, S_err_South_grant_W, S_err_Local_Req_S, S_err_Local_grant_S, S_err_arbiter_state_in_onehot, S_err_no_request_grants, S_err_request_no_grants, S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L, -- Local Arbiter_in checker outputs L_err_Requests_state_in_state_not_equal, L_err_IDLE_Req_N, L_err_IDLE_grant_N,L_err_North_Req_N, L_err_North_grant_N, L_err_East_Req_E, L_err_East_grant_E, L_err_West_Req_W, L_err_West_grant_W, L_err_South_Req_S,L_err_South_grant_S, L_err_Local_Req_L, L_err_Local_grant_L, L_err_IDLE_Req_E, L_err_IDLE_grant_E, L_err_North_Req_E, L_err_North_grant_E, L_err_East_Req_W, L_err_East_grant_W, L_err_West_Req_S, L_err_West_grant_S, L_err_South_Req_L, L_err_South_grant_L, L_err_Local_Req_N, L_err_Local_grant_N, L_err_IDLE_Req_W, L_err_IDLE_grant_W, L_err_North_Req_W, L_err_North_grant_W, L_err_East_Req_S, L_err_East_grant_S, L_err_West_Req_L, L_err_West_grant_L, L_err_South_Req_N, L_err_South_grant_N, L_err_Local_Req_E, L_err_Local_grant_E, L_err_IDLE_Req_S, L_err_IDLE_grant_S, L_err_North_Req_S, L_err_North_grant_S, L_err_East_Req_L, L_err_East_grant_L, L_err_West_Req_N, L_err_West_grant_N, L_err_South_Req_E, L_err_South_grant_E, L_err_Local_Req_W, L_err_Local_grant_W, L_err_IDLE_Req_L, L_err_IDLE_grant_L, L_err_North_Req_L, L_err_North_grant_L, L_err_East_Req_N, L_err_East_grant_N, L_err_West_Req_E, L_err_West_grant_E, L_err_South_Req_W, L_err_South_grant_W, L_err_Local_Req_S, L_err_Local_grant_S, L_err_arbiter_state_in_onehot, L_err_no_request_grants, L_err_request_no_grants, L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S, L_err_no_Req_L_grant_L : std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Arbiter_out Checker signals (part of allocator unit) -- North Arbiter_out checker outputs signal N_arbiter_out_err_Requests_state_in_state_not_equal, N_err_IDLE_req_X_N, N_err_North_req_X_N, N_err_North_credit_not_zero_req_X_N_grant_N, N_err_North_credit_zero_or_not_req_X_N_not_grant_N, N_err_East_req_X_E, N_err_East_credit_not_zero_req_X_E_grant_E, N_err_East_credit_zero_or_not_req_X_E_not_grant_E, N_err_West_req_X_W, N_err_West_credit_not_zero_req_X_W_grant_W, N_err_West_credit_zero_or_not_req_X_W_not_grant_W, N_err_South_req_X_S, N_err_South_credit_not_zero_req_X_S_grant_S, N_err_South_credit_zero_or_not_req_X_S_not_grant_S, N_err_Local_req_X_L, N_err_Local_credit_not_zero_req_X_L_grant_L, N_err_Local_credit_zero_or_not_req_X_L_not_grant_L, N_err_IDLE_req_X_E, N_err_North_req_X_E, N_err_East_req_X_W, N_err_West_req_X_S, N_err_South_req_X_L, N_err_Local_req_X_N, N_err_IDLE_req_X_W, N_err_North_req_X_W, N_err_East_req_X_S, N_err_West_req_X_L, N_err_South_req_X_N, N_err_Local_req_X_E, N_err_IDLE_req_X_S, N_err_North_req_X_S, N_err_East_req_X_L, N_err_West_req_X_N, N_err_South_req_X_E, N_err_Local_req_X_W, N_err_IDLE_req_X_L, N_err_North_req_X_L, N_err_East_req_X_N, N_err_West_req_X_E, N_err_South_req_X_W, N_err_Local_req_X_S, N_arbiter_out_err_state_in_onehot, N_arbiter_out_err_no_request_grants, N_err_request_IDLE_state, N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant, N_err_state_West_Invalid_Grant, N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant, N_err_Grants_onehot_or_all_zero, -- East Arbiter_out checker outputs E_arbiter_out_err_Requests_state_in_state_not_equal, E_err_IDLE_req_X_N, E_err_North_req_X_N, E_err_North_credit_not_zero_req_X_N_grant_N, E_err_North_credit_zero_or_not_req_X_N_not_grant_N, E_err_East_req_X_E, E_err_East_credit_not_zero_req_X_E_grant_E, E_err_East_credit_zero_or_not_req_X_E_not_grant_E, E_err_West_req_X_W, E_err_West_credit_not_zero_req_X_W_grant_W, E_err_West_credit_zero_or_not_req_X_W_not_grant_W, E_err_South_req_X_S, E_err_South_credit_not_zero_req_X_S_grant_S, E_err_South_credit_zero_or_not_req_X_S_not_grant_S, E_err_Local_req_X_L, E_err_Local_credit_not_zero_req_X_L_grant_L, E_err_Local_credit_zero_or_not_req_X_L_not_grant_L, E_err_IDLE_req_X_E, E_err_North_req_X_E, E_err_East_req_X_W, E_err_West_req_X_S, E_err_South_req_X_L, E_err_Local_req_X_N, E_err_IDLE_req_X_W, E_err_North_req_X_W, E_err_East_req_X_S, E_err_West_req_X_L, E_err_South_req_X_N, E_err_Local_req_X_E, E_err_IDLE_req_X_S, E_err_North_req_X_S, E_err_East_req_X_L, E_err_West_req_X_N, E_err_South_req_X_E, E_err_Local_req_X_W, E_err_IDLE_req_X_L, E_err_North_req_X_L, E_err_East_req_X_N, E_err_West_req_X_E, E_err_South_req_X_W, E_err_Local_req_X_S, E_arbiter_out_err_state_in_onehot, E_arbiter_out_err_no_request_grants, E_err_request_IDLE_state, E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant, E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant, E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero, -- West Arbiter_out checker outputs W_arbiter_out_err_Requests_state_in_state_not_equal, W_err_IDLE_req_X_N, W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N, W_err_North_credit_zero_or_not_req_X_N_not_grant_N, W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E, W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W, W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S, W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L, W_err_IDLE_req_X_E, W_err_North_req_X_E, W_err_East_req_X_W, W_err_West_req_X_S, W_err_South_req_X_L, W_err_Local_req_X_N, W_err_IDLE_req_X_W, W_err_North_req_X_W, W_err_East_req_X_S, W_err_West_req_X_L, W_err_South_req_X_N, W_err_Local_req_X_E, W_err_IDLE_req_X_S, W_err_North_req_X_S, W_err_East_req_X_L, W_err_West_req_X_N, W_err_South_req_X_E, W_err_Local_req_X_W, W_err_IDLE_req_X_L, W_err_North_req_X_L, W_err_East_req_X_N, W_err_West_req_X_E, W_err_South_req_X_W, W_err_Local_req_X_S, W_arbiter_out_err_state_in_onehot, W_arbiter_out_err_no_request_grants, W_err_request_IDLE_state, W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant,W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant, W_err_state_South_Invalid_Grant,W_err_state_Local_Invalid_Grant, W_err_Grants_onehot_or_all_zero, -- South Arbiter_out checker outputs S_arbiter_out_err_Requests_state_in_state_not_equal, S_err_IDLE_req_X_N, S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N, S_err_North_credit_zero_or_not_req_X_N_not_grant_N, S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E, S_err_East_credit_zero_or_not_req_X_E_not_grant_E, S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W, S_err_West_credit_zero_or_not_req_X_W_not_grant_W, S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S, S_err_South_credit_zero_or_not_req_X_S_not_grant_S, S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L, S_err_Local_credit_zero_or_not_req_X_L_not_grant_L, S_err_IDLE_req_X_E, S_err_North_req_X_E, S_err_East_req_X_W, S_err_West_req_X_S, S_err_South_req_X_L, S_err_Local_req_X_N, S_err_IDLE_req_X_W, S_err_North_req_X_W, S_err_East_req_X_S, S_err_West_req_X_L, S_err_South_req_X_N, S_err_Local_req_X_E, S_err_IDLE_req_X_S, S_err_North_req_X_S, S_err_East_req_X_L, S_err_West_req_X_N, S_err_South_req_X_E, S_err_Local_req_X_W, S_err_IDLE_req_X_L, S_err_North_req_X_L, S_err_East_req_X_N, S_err_West_req_X_E, S_err_South_req_X_W, S_err_Local_req_X_S, S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state, S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant, S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero, -- Local Arbiter_out checker outputs L_arbiter_out_err_Requests_state_in_state_not_equal, L_err_IDLE_req_X_N, L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N, L_err_North_credit_zero_or_not_req_X_N_not_grant_N, L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E, L_err_East_credit_zero_or_not_req_X_E_not_grant_E, L_err_West_req_X_W, L_err_West_credit_not_zero_req_X_W_grant_W, L_err_West_credit_zero_or_not_req_X_W_not_grant_W, L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S, L_err_South_credit_zero_or_not_req_X_S_not_grant_S, L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L, L_err_Local_credit_zero_or_not_req_X_L_not_grant_L, L_err_IDLE_req_X_E, L_err_North_req_X_E, L_err_East_req_X_W, L_err_West_req_X_S, L_err_South_req_X_L, L_err_Local_req_X_N, L_err_IDLE_req_X_W, L_err_North_req_X_W, L_err_East_req_X_S, L_err_West_req_X_L, L_err_South_req_X_N, L_err_Local_req_X_E, L_err_IDLE_req_X_S, L_err_North_req_X_S, L_err_East_req_X_L, L_err_West_req_X_N, L_err_South_req_X_E, L_err_Local_req_X_W, L_err_IDLE_req_X_L, L_err_North_req_X_L, L_err_East_req_X_N, L_err_West_req_X_E, L_err_South_req_X_W, L_err_Local_req_X_S, L_arbiter_out_err_state_in_onehot, L_arbiter_out_err_no_request_grants, L_err_request_IDLE_state, L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant,L_err_state_East_Invalid_Grant, L_err_state_West_Invalid_Grant, L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant, L_err_Grants_onehot_or_all_zero : std_logic; --------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------- -- Signals needed for grouping checkers to model turn/path faults signal N_FIFO_checkers_ORed, E_FIFO_checkers_ORed, W_FIFO_checkers_ORed, S_FIFO_checkers_ORed, L_FIFO_checkers_ORed : std_logic; signal N2E_turn_fault, N2W_turn_fault, E2N_turn_fault, E2S_turn_fault, W2N_turn_fault, W2S_turn_fault, S2E_turn_fault, S2W_turn_fault : std_logic; signal N2S_path_fault, S2N_path_fault, E2W_path_fault, W2E_path_fault : std_logic; signal not_N2E_turn_fault, not_N2W_turn_fault, not_E2N_turn_fault, not_E2S_turn_fault, not_W2N_turn_fault, not_W2S_turn_fault, not_S2E_turn_fault, not_S2W_turn_fault : std_logic; signal not_N2S_path_fault, not_S2N_path_fault, not_E2W_path_fault, not_W2E_path_fault : std_logic; signal L2N_fault, L2E_fault, L2W_fault, L2S_fault, N2L_fault, E2L_fault, W2L_fault, S2L_fault : std_logic; signal not_L2N_fault, not_L2E_fault, not_L2W_fault, not_L2S_fault, not_N2L_fault, not_E2L_fault, not_W2L_fault, not_S2L_fault : std_logic; -- Just used temporarily for debugging purposes! signal N_LBDR_checkers_ORed, E_LBDR_checkers_ORed, W_LBDR_checkers_ORed, S_LBDR_checkers_ORed, L_LBDR_checkers_ORed : std_logic; signal Allocator_checkers_ORed : std_logic; --signal turn_faults_sig : std_logic_vector(19 downto 0); ------------------------------------------------------------------------------------------------- -- Added because of the chain we make for sending faulty values --------------------------------- -- The chain is : L, N, E, W and S FIFO, then L, N, E, W and S LBDR, ---------------------------- -- then L, N, E, W and S Arbiter_in, -------------------- -- then L, N, E, W and S Arbiter_out and then Allocator's interlal logic ??!! -- ------------------------------------------------------------------------------------------------- --TODO: the chains should be fixed! --Fixed! signal fault_DO_serial_L_FIFO_to_N_FIFO, fault_DO_serial_N_FIFO_to_E_FIFO: std_logic; signal fault_DO_serial_E_FIFO_to_W_FIFO, fault_DO_serial_W_FIFO_to_S_FIFO: std_logic; signal fault_DO_serial_S_FIFO_to_L_LBDR, fault_DO_serial_L_LBDR_to_N_LBDR: std_logic; signal fault_DO_serial_N_LBDR_to_E_LBDR, fault_DO_serial_E_LBDR_to_W_LBDR: std_logic; signal fault_DO_serial_W_LBDR_to_S_LBDR, fault_DO_serial_S_LBDR_to_Allocator: std_logic; ------------------------------------------------------------------ ------------------------------------------------------------------ begin not_N2E_turn_fault <= not N2E_turn_fault; not_N2W_turn_fault <= not N2W_turn_fault; not_E2N_turn_fault <= not E2N_turn_fault; not_E2S_turn_fault <= not E2S_turn_fault; not_W2N_turn_fault <= not W2N_turn_fault; not_W2S_turn_fault <= not W2S_turn_fault; not_S2E_turn_fault <= not S2E_turn_fault; not_S2W_turn_fault <= not S2W_turn_fault; not_N2S_path_fault <= not N2S_path_fault; not_S2N_path_fault <= not S2N_path_fault; not_E2W_path_fault <= not E2W_path_fault; not_W2E_path_fault <= not W2E_path_fault; not_L2N_fault <= not L2N_fault; not_L2E_fault <= not L2E_fault; not_L2W_fault <= not L2W_fault; not_L2S_fault <= not L2S_fault; not_N2L_fault <= not N2L_fault; not_E2L_fault <= not E2L_fault; not_W2L_fault <= not W2L_fault; not_S2L_fault <= not S2L_fault; -- FIFO contributes to all turns and paths, therefore, for each turn or path (for the input direction), all the outputs of FIFO checkers -- corresponding to that input are ORed together. N_FIFO_checkers_ORed <= N_err_empty_full or N_err_empty_read_en or N_err_full_write_en or N_err_state_in_onehot or N_err_read_pointer_in_onehot or N_err_write_pointer_in_onehot or N_err_write_en_write_pointer or N_err_not_write_en_write_pointer or N_err_read_pointer_write_pointer_not_empty or N_err_read_pointer_write_pointer_empty or N_err_read_pointer_write_pointer_not_full or N_err_read_pointer_write_pointer_full or N_err_read_pointer_increment or N_err_read_pointer_not_increment or N_err_write_en or N_err_not_write_en or N_err_not_write_en1 or N_err_not_write_en2 or N_err_read_en_mismatch or N_err_read_en_mismatch1 or N_err_fake_credit_read_en_fake_credit_counter_in_increment or N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or N_err_fake_credit_read_en_credit_out or N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or N_err_state_out_Idle_not_fault_out_not_fake_credit or N_err_state_out_Idle_not_fault_out_not_fault_info_in or N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or N_err_state_out_Idle_fault_out_fake_credit or N_err_state_out_Idle_fault_out_state_in_Packet_drop or N_err_state_out_Idle_fault_out_fault_info_in or N_err_state_out_Idle_fault_out_faulty_packet_in or N_err_state_out_Idle_not_health_info or N_err_state_out_Idle_not_write_fake_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Header_flit_not_valid_in_not_fault_info_in or N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or N_err_state_out_Header_flit_or_Body_flit_not_fake_credit or N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or N_err_state_out_Body_flit_valid_in_not_fault_out_health_info or N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Body_flit_not_valid_in_not_fault_info_in or N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or N_err_state_out_Body_flit_valid_in_fault_out_not_health_info or N_err_state_out_Body_flit_valid_in_not_health_info or N_err_state_out_Body_flit_not_fake_credit or N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or N_err_state_out_Tail_flit_not_valid_in_state_in_Idle or N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or N_err_state_out_Tail_flit_not_valid_in_not_fake_credit or N_err_state_out_Tail_flit_not_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or N_err_fault_info_fault_info_out_equal or N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- East E_FIFO_checkers_ORed <= E_err_empty_full or E_err_empty_read_en or E_err_full_write_en or E_err_state_in_onehot or E_err_read_pointer_in_onehot or E_err_write_pointer_in_onehot or E_err_write_en_write_pointer or E_err_not_write_en_write_pointer or E_err_read_pointer_write_pointer_not_empty or E_err_read_pointer_write_pointer_empty or E_err_read_pointer_write_pointer_not_full or E_err_read_pointer_write_pointer_full or E_err_read_pointer_increment or E_err_read_pointer_not_increment or E_err_write_en or E_err_not_write_en or E_err_not_write_en1 or E_err_not_write_en2 or E_err_read_en_mismatch or E_err_read_en_mismatch1 or E_err_fake_credit_read_en_fake_credit_counter_in_increment or E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or E_err_fake_credit_read_en_credit_out or E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or E_err_state_out_Idle_not_fault_out_not_fake_credit or E_err_state_out_Idle_not_fault_out_not_fault_info_in or E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or E_err_state_out_Idle_fault_out_fake_credit or E_err_state_out_Idle_fault_out_state_in_Packet_drop or E_err_state_out_Idle_fault_out_fault_info_in or E_err_state_out_Idle_fault_out_faulty_packet_in or E_err_state_out_Idle_not_health_info or E_err_state_out_Idle_not_write_fake_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Header_flit_not_valid_in_not_fault_info_in or E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or E_err_state_out_Header_flit_or_Body_flit_not_fake_credit or E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or E_err_state_out_Body_flit_valid_in_not_fault_out_health_info or E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Body_flit_not_valid_in_not_fault_info_in or E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or E_err_state_out_Body_flit_valid_in_fault_out_not_health_info or E_err_state_out_Body_flit_valid_in_not_health_info or E_err_state_out_Body_flit_not_fake_credit or E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or E_err_state_out_Tail_flit_not_valid_in_state_in_Idle or E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or E_err_state_out_Tail_flit_not_valid_in_not_fake_credit or E_err_state_out_Tail_flit_not_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or E_err_fault_info_fault_info_out_equal or E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- West W_FIFO_checkers_ORed <= W_err_empty_full or W_err_empty_read_en or W_err_full_write_en or W_err_state_in_onehot or W_err_read_pointer_in_onehot or W_err_write_pointer_in_onehot or W_err_write_en_write_pointer or W_err_not_write_en_write_pointer or W_err_read_pointer_write_pointer_not_empty or W_err_read_pointer_write_pointer_empty or W_err_read_pointer_write_pointer_not_full or W_err_read_pointer_write_pointer_full or W_err_read_pointer_increment or W_err_read_pointer_not_increment or W_err_write_en or W_err_not_write_en or W_err_not_write_en1 or W_err_not_write_en2 or W_err_read_en_mismatch or W_err_read_en_mismatch1 or W_err_fake_credit_read_en_fake_credit_counter_in_increment or W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or W_err_fake_credit_read_en_credit_out or W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or W_err_state_out_Idle_not_fault_out_not_fake_credit or W_err_state_out_Idle_not_fault_out_not_fault_info_in or W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or W_err_state_out_Idle_fault_out_fake_credit or W_err_state_out_Idle_fault_out_state_in_Packet_drop or W_err_state_out_Idle_fault_out_fault_info_in or W_err_state_out_Idle_fault_out_faulty_packet_in or W_err_state_out_Idle_not_health_info or W_err_state_out_Idle_not_write_fake_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Header_flit_not_valid_in_not_fault_info_in or W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or W_err_state_out_Header_flit_or_Body_flit_not_fake_credit or W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or W_err_state_out_Body_flit_valid_in_not_fault_out_health_info or W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Body_flit_not_valid_in_not_fault_info_in or W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or W_err_state_out_Body_flit_valid_in_fault_out_not_health_info or W_err_state_out_Body_flit_valid_in_not_health_info or W_err_state_out_Body_flit_not_fake_credit or W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or W_err_state_out_Tail_flit_not_valid_in_state_in_Idle or W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or W_err_state_out_Tail_flit_not_valid_in_not_fake_credit or W_err_state_out_Tail_flit_not_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or W_err_fault_info_fault_info_out_equal or W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- South S_FIFO_checkers_ORed <= S_err_empty_full or S_err_empty_read_en or S_err_full_write_en or S_err_state_in_onehot or S_err_read_pointer_in_onehot or S_err_write_pointer_in_onehot or S_err_write_en_write_pointer or S_err_not_write_en_write_pointer or S_err_read_pointer_write_pointer_not_empty or S_err_read_pointer_write_pointer_empty or S_err_read_pointer_write_pointer_not_full or S_err_read_pointer_write_pointer_full or S_err_read_pointer_increment or S_err_read_pointer_not_increment or S_err_write_en or S_err_not_write_en or S_err_not_write_en1 or S_err_not_write_en2 or S_err_read_en_mismatch or S_err_read_en_mismatch1 or S_err_fake_credit_read_en_fake_credit_counter_in_increment or S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or S_err_fake_credit_read_en_credit_out or S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or S_err_state_out_Idle_not_fault_out_not_fake_credit or S_err_state_out_Idle_not_fault_out_not_fault_info_in or S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or S_err_state_out_Idle_fault_out_fake_credit or S_err_state_out_Idle_fault_out_state_in_Packet_drop or S_err_state_out_Idle_fault_out_fault_info_in or S_err_state_out_Idle_fault_out_faulty_packet_in or S_err_state_out_Idle_not_health_info or S_err_state_out_Idle_not_write_fake_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Header_flit_not_valid_in_not_fault_info_in or S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or S_err_state_out_Header_flit_or_Body_flit_not_fake_credit or S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or S_err_state_out_Body_flit_valid_in_not_fault_out_health_info or S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Body_flit_not_valid_in_not_fault_info_in or S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or S_err_state_out_Body_flit_valid_in_fault_out_not_health_info or S_err_state_out_Body_flit_valid_in_not_health_info or S_err_state_out_Body_flit_not_fake_credit or S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or S_err_state_out_Tail_flit_not_valid_in_state_in_Idle or S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or S_err_state_out_Tail_flit_not_valid_in_not_fake_credit or S_err_state_out_Tail_flit_not_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or S_err_fault_info_fault_info_out_equal or S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; -- Local L_FIFO_checkers_ORed <= L_err_empty_full or L_err_empty_read_en or L_err_full_write_en or L_err_state_in_onehot or L_err_read_pointer_in_onehot or L_err_write_pointer_in_onehot or L_err_write_en_write_pointer or L_err_not_write_en_write_pointer or L_err_read_pointer_write_pointer_not_empty or L_err_read_pointer_write_pointer_empty or L_err_read_pointer_write_pointer_not_full or L_err_read_pointer_write_pointer_full or L_err_read_pointer_increment or L_err_read_pointer_not_increment or L_err_write_en or L_err_not_write_en or L_err_not_write_en1 or L_err_not_write_en2 or L_err_read_en_mismatch or L_err_read_en_mismatch1 or L_err_fake_credit_read_en_fake_credit_counter_in_increment or L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement or L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change or L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change or L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change or L_err_fake_credit_read_en_credit_out or L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out or L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out or L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit or L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change or L_err_state_out_Idle_not_fault_out_not_fake_credit or L_err_state_out_Idle_not_fault_out_not_fault_info_in or L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal or L_err_state_out_Idle_fault_out_fake_credit or L_err_state_out_Idle_fault_out_state_in_Packet_drop or L_err_state_out_Idle_fault_out_fault_info_in or L_err_state_out_Idle_fault_out_faulty_packet_in or L_err_state_out_Idle_not_health_info or L_err_state_out_Idle_not_write_fake_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit or L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in or L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit or L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop or L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in or L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in or L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change or L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Header_flit_not_valid_in_not_fault_info_in or L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit or L_err_state_out_Header_flit_or_Body_flit_not_fake_credit or L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change or L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit or L_err_state_out_Body_flit_valid_in_not_fault_out_health_info or L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit or L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in or L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit or L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop or L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in or L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in or L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change or L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Body_flit_not_valid_in_not_fault_info_in or L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info or L_err_state_out_Body_flit_valid_in_fault_out_not_health_info or L_err_state_out_Body_flit_valid_in_not_health_info or L_err_state_out_Body_flit_not_fake_credit or L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit or L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit or L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit or L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in or L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit or L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop or L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in or L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in or L_err_state_out_Tail_flit_not_valid_in_state_in_Idle or L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change or L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in or L_err_state_out_Tail_flit_not_valid_in_not_fake_credit or L_err_state_out_Tail_flit_not_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit or L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change or L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change or L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit or L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change or L_err_fault_info_fault_info_out_equal or L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal or L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal or L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in or L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Just for debugging purposes of the checkers! -- LBDR checker outputs ORed -- North -- Routing part checkers N_LBDR_checkers_ORed <= N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_N1 or N_err_dst_addr_cur_addr_not_N1 or N_err_dst_addr_cur_addr_E1 or N_err_dst_addr_cur_addr_not_E1 or N_err_dst_addr_cur_addr_W1 or N_err_dst_addr_cur_addr_not_W1 or N_err_dst_addr_cur_addr_S1 or N_err_dst_addr_cur_addr_not_S1 or N_err_dst_addr_cur_addr_Req_L_in or N_err_dst_addr_cur_addr_not_Req_L_in or N_err_header_not_empty_faulty_drop_packet_in or -- added according to new design N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design N_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --N_err_header_not_empty_Req_L_in or -- added according to new design N_err_header_not_empty_Req_N_in or N_err_header_not_empty_Req_E_in or N_err_header_not_empty_Req_W_in or N_err_header_not_empty_Req_S_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or -- Cx_Reconf checkers N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- East -- Routing part checkers E_LBDR_checkers_ORed <= E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_N1 or E_err_dst_addr_cur_addr_not_N1 or E_err_dst_addr_cur_addr_E1 or E_err_dst_addr_cur_addr_not_E1 or E_err_dst_addr_cur_addr_W1 or E_err_dst_addr_cur_addr_not_W1 or E_err_dst_addr_cur_addr_S1 or E_err_dst_addr_cur_addr_not_S1 or E_err_dst_addr_cur_addr_Req_L_in or E_err_dst_addr_cur_addr_not_Req_L_in or E_err_header_not_empty_faulty_drop_packet_in or -- added according to new design E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design E_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --E_err_header_not_empty_Req_L_in or -- added according to new design E_err_header_not_empty_Req_N_in or E_err_header_not_empty_Req_E_in or E_err_header_not_empty_Req_W_in or E_err_header_not_empty_Req_S_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or -- Cx_Reconf checkers E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- West -- Routing part checkers W_LBDR_checkers_ORed <= W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_N1 or W_err_dst_addr_cur_addr_not_N1 or W_err_dst_addr_cur_addr_E1 or W_err_dst_addr_cur_addr_not_E1 or W_err_dst_addr_cur_addr_W1 or W_err_dst_addr_cur_addr_not_W1 or W_err_dst_addr_cur_addr_S1 or W_err_dst_addr_cur_addr_not_S1 or W_err_dst_addr_cur_addr_Req_L_in or W_err_dst_addr_cur_addr_not_Req_L_in or W_err_header_not_empty_faulty_drop_packet_in or -- added according to new design W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design W_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --W_err_header_not_empty_Req_L_in or -- added according to new design W_err_header_not_empty_Req_N_in or W_err_header_not_empty_Req_E_in or W_err_header_not_empty_Req_W_in or W_err_header_not_empty_Req_S_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or -- Cx_Reconf checkers W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- South -- Routing part checkers S_LBDR_checkers_ORed <= S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_N1 or S_err_dst_addr_cur_addr_not_N1 or S_err_dst_addr_cur_addr_E1 or S_err_dst_addr_cur_addr_not_E1 or S_err_dst_addr_cur_addr_W1 or S_err_dst_addr_cur_addr_not_W1 or S_err_dst_addr_cur_addr_S1 or S_err_dst_addr_cur_addr_not_S1 or S_err_dst_addr_cur_addr_Req_L_in or S_err_dst_addr_cur_addr_not_Req_L_in or S_err_header_not_empty_faulty_drop_packet_in or -- added according to new design S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design S_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --S_err_header_not_empty_Req_L_in or -- added according to new design S_err_header_not_empty_Req_N_in or S_err_header_not_empty_Req_E_in or S_err_header_not_empty_Req_W_in or S_err_header_not_empty_Req_S_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or -- Cx_Reconf checkers S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; -- Local -- Routing part checkers L_LBDR_checkers_ORed <= L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_N1 or L_err_dst_addr_cur_addr_not_N1 or L_err_dst_addr_cur_addr_E1 or L_err_dst_addr_cur_addr_not_E1 or L_err_dst_addr_cur_addr_W1 or L_err_dst_addr_cur_addr_not_W1 or L_err_dst_addr_cur_addr_S1 or L_err_dst_addr_cur_addr_not_S1 or L_err_dst_addr_cur_addr_Req_L_in or L_err_dst_addr_cur_addr_not_Req_L_in or L_err_header_not_empty_faulty_drop_packet_in or -- added according to new design L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or -- added according to new design L_err_header_not_empty_faulty_Req_in_all_zero or -- added according to new design --L_err_header_not_empty_Req_L_in or -- added according to new design L_err_header_not_empty_Req_N_in or L_err_header_not_empty_Req_E_in or L_err_header_not_empty_Req_W_in or L_err_header_not_empty_Req_S_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or -- Cx_Reconf checkers L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Rxy_Reconf checkers L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Allocator checker outputs ORed ! -- Allocator logic checker outputs Allocator_checkers_ORed <= err_grant_N_N_sig_not_empty_N_grant_N_N or err_not_grant_N_N_sig_or_empty_N_not_grant_N_N or err_grant_N_E_sig_not_empty_E_grant_N_E or err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or err_grant_N_W_sig_not_empty_W_grant_N_W or err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or err_grant_N_S_sig_not_empty_S_grant_N_S or err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or err_grant_N_L_sig_not_empty_L_grant_N_L or err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or err_grant_E_N_sig_not_empty_N_grant_E_N or err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or err_grant_E_E_sig_not_empty_E_grant_E_E or err_not_grant_E_E_sig_or_empty_E_not_grant_E_E or err_grant_E_W_sig_not_empty_W_grant_E_W or err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or err_grant_E_S_sig_not_empty_S_grant_E_S or err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or err_grant_E_L_sig_not_empty_L_grant_E_L or err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or err_grant_W_N_sig_not_empty_N_grant_W_N or err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or err_grant_W_E_sig_not_empty_E_grant_W_E or err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or err_grant_W_W_sig_not_empty_W_grant_W_W or err_not_grant_W_W_sig_or_empty_W_not_grant_W_W or err_grant_W_S_sig_not_empty_S_grant_W_S or err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or err_grant_W_L_sig_not_empty_L_grant_W_L or err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or err_grant_S_N_sig_not_empty_N_grant_S_N or err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or err_grant_S_E_sig_not_empty_E_grant_S_E or err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or err_grant_S_W_sig_not_empty_W_grant_S_W or err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or err_grant_S_S_sig_not_empty_S_grant_S_S or err_not_grant_S_S_sig_or_empty_S_not_grant_S_S or err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or err_grant_L_N_sig_not_empty_N_grant_L_N or err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or err_grant_L_E_sig_not_empty_E_grant_L_E or err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or err_grant_L_W_sig_not_empty_W_grant_L_W or err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or err_grant_L_L_sig_not_empty_L_grant_L_L or err_not_grant_L_L_sig_or_empty_L_not_grant_L_L or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or -- Allocator credit counter logic checker outputs err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal or -- Arbiter_in checker outputs -- North Arbiter_in checker outputs N_err_Requests_state_in_state_not_equal or N_err_IDLE_Req_N or N_err_IDLE_grant_N or N_err_North_Req_N or N_err_North_grant_N or N_err_East_Req_E or N_err_East_grant_E or N_err_West_Req_W or N_err_West_grant_W or N_err_South_Req_S or N_err_South_grant_S or N_err_Local_Req_L or N_err_Local_grant_L or N_err_IDLE_Req_E or N_err_IDLE_grant_E or N_err_North_Req_E or N_err_North_grant_E or N_err_East_Req_W or N_err_East_grant_W or N_err_West_Req_S or N_err_West_grant_S or N_err_South_Req_L or N_err_South_grant_L or N_err_Local_Req_N or N_err_Local_grant_N or N_err_IDLE_Req_W or N_err_IDLE_grant_W or N_err_North_Req_W or N_err_North_grant_W or N_err_East_Req_S or N_err_East_grant_S or N_err_West_Req_L or N_err_West_grant_L or N_err_South_Req_N or N_err_South_grant_N or N_err_Local_Req_E or N_err_Local_grant_E or N_err_IDLE_Req_S or N_err_IDLE_grant_S or N_err_North_Req_S or N_err_North_grant_S or N_err_East_Req_L or N_err_East_grant_L or N_err_West_Req_N or N_err_West_grant_N or N_err_South_Req_E or N_err_South_grant_E or N_err_Local_Req_W or N_err_Local_grant_W or N_err_IDLE_Req_L or N_err_IDLE_grant_L or N_err_North_Req_L or N_err_North_grant_L or N_err_East_Req_N or N_err_East_grant_N or N_err_West_Req_E or N_err_West_grant_E or N_err_South_Req_W or N_err_South_grant_W or N_err_Local_Req_S or N_err_Local_grant_S or N_err_arbiter_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_N_grant_N or N_err_no_Req_E_grant_E or N_err_no_Req_W_grant_W or N_err_no_Req_S_grant_S or N_err_no_Req_L_grant_L or -- East Arbiter_in checker outputs E_err_Requests_state_in_state_not_equal or E_err_IDLE_Req_N or E_err_IDLE_grant_N or E_err_North_Req_N or E_err_North_grant_N or E_err_East_Req_E or E_err_East_grant_E or E_err_West_Req_W or E_err_West_grant_W or E_err_South_Req_S or E_err_South_grant_S or E_err_Local_Req_L or E_err_Local_grant_L or E_err_IDLE_Req_E or E_err_IDLE_grant_E or E_err_North_Req_E or E_err_North_grant_E or E_err_East_Req_W or E_err_East_grant_W or E_err_West_Req_S or E_err_West_grant_S or E_err_South_Req_L or E_err_South_grant_L or E_err_Local_Req_N or E_err_Local_grant_N or E_err_IDLE_Req_W or E_err_IDLE_grant_W or E_err_North_Req_W or E_err_North_grant_W or E_err_East_Req_S or E_err_East_grant_S or E_err_West_Req_L or E_err_West_grant_L or E_err_South_Req_N or E_err_South_grant_N or E_err_Local_Req_E or E_err_Local_grant_E or E_err_IDLE_Req_S or E_err_IDLE_grant_S or E_err_North_Req_S or E_err_North_grant_S or E_err_East_Req_L or E_err_East_grant_L or E_err_West_Req_N or E_err_West_grant_N or E_err_South_Req_E or E_err_South_grant_E or E_err_Local_Req_W or E_err_Local_grant_W or E_err_IDLE_Req_L or E_err_IDLE_grant_L or E_err_North_Req_L or E_err_North_grant_L or E_err_East_Req_N or E_err_East_grant_N or E_err_West_Req_E or E_err_West_grant_E or E_err_South_Req_W or E_err_South_grant_W or E_err_Local_Req_S or E_err_Local_grant_S or E_err_arbiter_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_N_grant_N or E_err_no_Req_E_grant_E or E_err_no_Req_W_grant_W or E_err_no_Req_S_grant_S or E_err_no_Req_L_grant_L or -- West Arbiter_in checker outputs W_err_Requests_state_in_state_not_equal or W_err_IDLE_Req_N or W_err_IDLE_grant_N or W_err_North_Req_N or W_err_North_grant_N or W_err_East_Req_E or W_err_East_grant_E or W_err_West_Req_W or W_err_West_grant_W or W_err_South_Req_S or W_err_South_grant_S or W_err_Local_Req_L or W_err_Local_grant_L or W_err_IDLE_Req_E or W_err_IDLE_grant_E or W_err_North_Req_E or W_err_North_grant_E or W_err_East_Req_W or W_err_East_grant_W or W_err_West_Req_S or W_err_West_grant_S or W_err_South_Req_L or W_err_South_grant_L or W_err_Local_Req_N or W_err_Local_grant_N or W_err_IDLE_Req_W or W_err_IDLE_grant_W or W_err_North_Req_W or W_err_North_grant_W or W_err_East_Req_S or W_err_East_grant_S or W_err_West_Req_L or W_err_West_grant_L or W_err_South_Req_N or W_err_South_grant_N or W_err_Local_Req_E or W_err_Local_grant_E or W_err_IDLE_Req_S or W_err_IDLE_grant_S or W_err_North_Req_S or W_err_North_grant_S or W_err_East_Req_L or W_err_East_grant_L or W_err_West_Req_N or W_err_West_grant_N or W_err_South_Req_E or W_err_South_grant_E or W_err_Local_Req_W or W_err_Local_grant_W or W_err_IDLE_Req_L or W_err_IDLE_grant_L or W_err_North_Req_L or W_err_North_grant_L or W_err_East_Req_N or W_err_East_grant_N or W_err_West_Req_E or W_err_West_grant_E or W_err_South_Req_W or W_err_South_grant_W or W_err_Local_Req_S or W_err_Local_grant_S or W_err_arbiter_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_N_grant_N or W_err_no_Req_E_grant_E or W_err_no_Req_W_grant_W or W_err_no_Req_S_grant_S or W_err_no_Req_L_grant_L or -- South Arbiter_in checker outputs S_err_Requests_state_in_state_not_equal or S_err_IDLE_Req_N or S_err_IDLE_grant_N or S_err_North_Req_N or S_err_North_grant_N or S_err_East_Req_E or S_err_East_grant_E or S_err_West_Req_W or S_err_West_grant_W or S_err_South_Req_S or S_err_South_grant_S or S_err_Local_Req_L or S_err_Local_grant_L or S_err_IDLE_Req_E or S_err_IDLE_grant_E or S_err_North_Req_E or S_err_North_grant_E or S_err_East_Req_W or S_err_East_grant_W or S_err_West_Req_S or S_err_West_grant_S or S_err_South_Req_L or S_err_South_grant_L or S_err_Local_Req_N or S_err_Local_grant_N or S_err_IDLE_Req_W or S_err_IDLE_grant_W or S_err_North_Req_W or S_err_North_grant_W or S_err_East_Req_S or S_err_East_grant_S or S_err_West_Req_L or S_err_West_grant_L or S_err_South_Req_N or S_err_South_grant_N or S_err_Local_Req_E or S_err_Local_grant_E or S_err_IDLE_Req_S or S_err_IDLE_grant_S or S_err_North_Req_S or S_err_North_grant_S or S_err_East_Req_L or S_err_East_grant_L or S_err_West_Req_N or S_err_West_grant_N or S_err_South_Req_E or S_err_South_grant_E or S_err_Local_Req_W or S_err_Local_grant_W or S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or S_err_East_Req_N or S_err_East_grant_N or S_err_West_Req_E or S_err_West_grant_E or S_err_South_Req_W or S_err_South_grant_W or S_err_Local_Req_S or S_err_Local_grant_S or S_err_arbiter_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_N_grant_N or S_err_no_Req_E_grant_E or S_err_no_Req_W_grant_W or S_err_no_Req_S_grant_S or S_err_no_Req_L_grant_L or -- Local Arbiter_in checker outputs L_err_Requests_state_in_state_not_equal or L_err_IDLE_Req_N or L_err_IDLE_grant_N or L_err_North_Req_N or L_err_North_grant_N or L_err_East_Req_E or L_err_East_grant_E or L_err_West_Req_W or L_err_West_grant_W or L_err_South_Req_S or L_err_South_grant_S or L_err_Local_Req_L or L_err_Local_grant_L or L_err_IDLE_Req_E or L_err_IDLE_grant_E or L_err_North_Req_E or L_err_North_grant_E or L_err_East_Req_W or L_err_East_grant_W or L_err_West_Req_S or L_err_West_grant_S or L_err_South_Req_L or L_err_South_grant_L or L_err_Local_Req_N or L_err_Local_grant_N or L_err_IDLE_Req_W or L_err_IDLE_grant_W or L_err_North_Req_W or L_err_North_grant_W or L_err_East_Req_S or L_err_East_grant_S or L_err_West_Req_L or L_err_West_grant_L or L_err_South_Req_N or L_err_South_grant_N or L_err_Local_Req_E or L_err_Local_grant_E or L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or L_err_East_Req_L or L_err_East_grant_L or L_err_West_Req_N or L_err_West_grant_N or L_err_South_Req_E or L_err_South_grant_E or L_err_Local_Req_W or L_err_Local_grant_W or L_err_IDLE_Req_L or L_err_IDLE_grant_L or L_err_North_Req_L or L_err_North_grant_L or L_err_East_Req_N or L_err_East_grant_N or L_err_West_Req_E or L_err_West_grant_E or L_err_South_Req_W or L_err_South_grant_W or L_err_Local_Req_S or L_err_Local_grant_S or L_err_arbiter_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_N_grant_N or L_err_no_Req_E_grant_E or L_err_no_Req_W_grant_W or L_err_no_Req_S_grant_S or L_err_no_Req_L_grant_L or -- Arbiter_out checker outputs -- North Arbiter_out checker outputs N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_IDLE_req_X_N or N_err_North_req_X_N or N_err_North_credit_not_zero_req_X_N_grant_N or N_err_North_credit_zero_or_not_req_X_N_not_grant_N or N_err_East_req_X_E or N_err_East_credit_not_zero_req_X_E_grant_E or N_err_East_credit_zero_or_not_req_X_E_not_grant_E or N_err_West_req_X_W or N_err_West_credit_not_zero_req_X_W_grant_W or N_err_West_credit_zero_or_not_req_X_W_not_grant_W or N_err_South_req_X_S or N_err_South_credit_not_zero_req_X_S_grant_S or N_err_South_credit_zero_or_not_req_X_S_not_grant_S or N_err_Local_req_X_L or N_err_Local_credit_not_zero_req_X_L_grant_L or N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or N_err_IDLE_req_X_E or N_err_North_req_X_E or N_err_East_req_X_W or N_err_West_req_X_S or N_err_South_req_X_L or N_err_Local_req_X_N or N_err_IDLE_req_X_W or N_err_North_req_X_W or N_err_East_req_X_S or N_err_West_req_X_L or N_err_South_req_X_N or N_err_Local_req_X_E or N_err_IDLE_req_X_S or N_err_North_req_X_S or N_err_East_req_X_L or N_err_West_req_X_N or N_err_South_req_X_E or N_err_Local_req_X_W or N_err_IDLE_req_X_L or N_err_North_req_X_L or N_err_East_req_X_N or N_err_West_req_X_E or N_err_South_req_X_W or N_err_Local_req_X_S or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_state_North_Invalid_Grant or N_err_state_East_Invalid_Grant or N_err_state_West_Invalid_Grant or N_err_state_South_Invalid_Grant or N_err_state_Local_Invalid_Grant or N_err_Grants_onehot_or_all_zero or -- East Arbiter_out checker outputs E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_IDLE_req_X_N or E_err_North_req_X_N or E_err_North_credit_not_zero_req_X_N_grant_N or E_err_North_credit_zero_or_not_req_X_N_not_grant_N or E_err_East_req_X_E or E_err_East_credit_not_zero_req_X_E_grant_E or E_err_East_credit_zero_or_not_req_X_E_not_grant_E or E_err_West_req_X_W or E_err_West_credit_not_zero_req_X_W_grant_W or E_err_West_credit_zero_or_not_req_X_W_not_grant_W or E_err_South_req_X_S or E_err_South_credit_not_zero_req_X_S_grant_S or E_err_South_credit_zero_or_not_req_X_S_not_grant_S or E_err_Local_req_X_L or E_err_Local_credit_not_zero_req_X_L_grant_L or E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or E_err_IDLE_req_X_E or E_err_North_req_X_E or E_err_East_req_X_W or E_err_West_req_X_S or E_err_South_req_X_L or E_err_Local_req_X_N or E_err_IDLE_req_X_W or E_err_North_req_X_W or E_err_East_req_X_S or E_err_West_req_X_L or E_err_South_req_X_N or E_err_Local_req_X_E or E_err_IDLE_req_X_S or E_err_North_req_X_S or E_err_East_req_X_L or E_err_West_req_X_N or E_err_South_req_X_E or E_err_Local_req_X_W or E_err_IDLE_req_X_L or E_err_North_req_X_L or E_err_East_req_X_N or E_err_West_req_X_E or E_err_South_req_X_W or E_err_Local_req_X_S or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_state_North_Invalid_Grant or E_err_state_East_Invalid_Grant or E_err_state_West_Invalid_Grant or E_err_state_South_Invalid_Grant or E_err_state_Local_Invalid_Grant or E_err_Grants_onehot_or_all_zero or -- West Arbiter_out checker outputs W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_IDLE_req_X_N or W_err_North_req_X_N or W_err_North_credit_not_zero_req_X_N_grant_N or W_err_North_credit_zero_or_not_req_X_N_not_grant_N or W_err_East_req_X_E or W_err_East_credit_not_zero_req_X_E_grant_E or W_err_East_credit_zero_or_not_req_X_E_not_grant_E or W_err_West_req_X_W or W_err_West_credit_not_zero_req_X_W_grant_W or W_err_West_credit_zero_or_not_req_X_W_not_grant_W or W_err_South_req_X_S or W_err_South_credit_not_zero_req_X_S_grant_S or W_err_South_credit_zero_or_not_req_X_S_not_grant_S or W_err_Local_req_X_L or W_err_Local_credit_not_zero_req_X_L_grant_L or W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or W_err_IDLE_req_X_E or W_err_North_req_X_E or W_err_East_req_X_W or W_err_West_req_X_S or W_err_South_req_X_L or W_err_Local_req_X_N or W_err_IDLE_req_X_W or W_err_North_req_X_W or W_err_East_req_X_S or W_err_West_req_X_L or W_err_South_req_X_N or W_err_Local_req_X_E or W_err_IDLE_req_X_S or W_err_North_req_X_S or W_err_East_req_X_L or W_err_West_req_X_N or W_err_South_req_X_E or W_err_Local_req_X_W or W_err_IDLE_req_X_L or W_err_North_req_X_L or W_err_East_req_X_N or W_err_West_req_X_E or W_err_South_req_X_W or W_err_Local_req_X_S or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_state_North_Invalid_Grant or W_err_state_East_Invalid_Grant or W_err_state_West_Invalid_Grant or W_err_state_South_Invalid_Grant or W_err_state_Local_Invalid_Grant or W_err_Grants_onehot_or_all_zero or -- South Arbiter_out checker outputs S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_IDLE_req_X_N or S_err_North_req_X_N or S_err_North_credit_not_zero_req_X_N_grant_N or S_err_North_credit_zero_or_not_req_X_N_not_grant_N or S_err_East_req_X_E or S_err_East_credit_not_zero_req_X_E_grant_E or S_err_East_credit_zero_or_not_req_X_E_not_grant_E or S_err_West_req_X_W or S_err_West_credit_not_zero_req_X_W_grant_W or S_err_West_credit_zero_or_not_req_X_W_not_grant_W or S_err_South_req_X_S or S_err_South_credit_not_zero_req_X_S_grant_S or S_err_South_credit_zero_or_not_req_X_S_not_grant_S or S_err_Local_req_X_L or S_err_Local_credit_not_zero_req_X_L_grant_L or S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or S_err_IDLE_req_X_E or S_err_North_req_X_E or S_err_East_req_X_W or S_err_West_req_X_S or S_err_South_req_X_L or S_err_Local_req_X_N or S_err_IDLE_req_X_W or S_err_North_req_X_W or S_err_East_req_X_S or S_err_West_req_X_L or S_err_South_req_X_N or S_err_Local_req_X_E or S_err_IDLE_req_X_S or S_err_North_req_X_S or S_err_East_req_X_L or S_err_West_req_X_N or S_err_South_req_X_E or S_err_Local_req_X_W or S_err_IDLE_req_X_L or S_err_North_req_X_L or S_err_East_req_X_N or S_err_West_req_X_E or S_err_South_req_X_W or S_err_Local_req_X_S or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_state_North_Invalid_Grant or S_err_state_East_Invalid_Grant or S_err_state_West_Invalid_Grant or S_err_state_South_Invalid_Grant or S_err_state_Local_Invalid_Grant or S_err_Grants_onehot_or_all_zero or -- Local Arbiter_out checker outputs L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_IDLE_req_X_N or L_err_North_req_X_N or L_err_North_credit_not_zero_req_X_N_grant_N or L_err_North_credit_zero_or_not_req_X_N_not_grant_N or L_err_East_req_X_E or L_err_East_credit_not_zero_req_X_E_grant_E or L_err_East_credit_zero_or_not_req_X_E_not_grant_E or L_err_West_req_X_W or L_err_West_credit_not_zero_req_X_W_grant_W or L_err_West_credit_zero_or_not_req_X_W_not_grant_W or L_err_South_req_X_S or L_err_South_credit_not_zero_req_X_S_grant_S or L_err_South_credit_zero_or_not_req_X_S_not_grant_S or L_err_Local_req_X_L or L_err_Local_credit_not_zero_req_X_L_grant_L or L_err_Local_credit_zero_or_not_req_X_L_not_grant_L or L_err_IDLE_req_X_E or L_err_North_req_X_E or L_err_East_req_X_W or L_err_West_req_X_S or L_err_South_req_X_L or L_err_Local_req_X_N or L_err_IDLE_req_X_W or L_err_North_req_X_W or L_err_East_req_X_S or L_err_West_req_X_L or L_err_South_req_X_N or L_err_Local_req_X_E or L_err_IDLE_req_X_S or L_err_North_req_X_S or L_err_East_req_X_L or L_err_West_req_X_N or L_err_South_req_X_E or L_err_Local_req_X_W or L_err_IDLE_req_X_L or L_err_North_req_X_L or L_err_East_req_X_N or L_err_West_req_X_E or L_err_South_req_X_W or L_err_Local_req_X_S or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_state_North_Invalid_Grant or L_err_state_East_Invalid_Grant or L_err_state_West_Invalid_Grant or L_err_state_South_Invalid_Grant or L_err_state_Local_Invalid_Grant or L_err_Grants_onehot_or_all_zero; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Turn fault checkers -- FIFO N2E_turn_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_E1 or N_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or N_err_header_not_empty_Req_E_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_East_Req_E or N_err_East_grant_E or N_err_IDLE_Req_E or N_err_IDLE_grant_E or N_err_North_Req_E or N_err_North_grant_E or N_err_Local_Req_E or N_err_Local_grant_E or N_err_South_Req_E or N_err_South_grant_E or N_err_West_Req_E or N_err_West_grant_E or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_IDLE_req_X_N or E_err_North_req_X_N or E_err_North_credit_not_zero_req_X_N_grant_N or E_err_North_credit_zero_or_not_req_X_N_not_grant_N or E_err_Local_req_X_N or E_err_South_req_X_N or E_err_West_req_X_N or E_err_East_req_X_N or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or W_err_South_req_X_N or W_err_West_req_X_N or W_err_East_req_X_N or err_grant_E_N_sig_not_empty_N_grant_E_N or err_not_grant_E_N_sig_or_empty_N_not_grant_E_N or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- FIFO N2W_turn_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_W1 or N_err_dst_addr_cur_addr_not_W1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or N_err_header_not_empty_Req_W_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_West_Req_W or N_err_West_grant_W or N_err_East_Req_W or N_err_East_grant_W or N_err_IDLE_Req_W or N_err_IDLE_grant_W or N_err_North_Req_W or N_err_North_grant_W or N_err_Local_Req_W or N_err_Local_grant_W or N_err_South_Req_W or N_err_South_grant_W or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_IDLE_req_X_N or W_err_North_req_X_N or W_err_North_credit_not_zero_req_X_N_grant_N or W_err_North_credit_zero_or_not_req_X_N_not_grant_N or W_err_Local_req_X_N or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_N_sig_not_empty_N_grant_W_N or err_not_grant_W_N_sig_or_empty_N_not_grant_W_N or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- FIFO E2N_turn_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_N1 or E_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or E_err_header_not_empty_Req_N_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_IDLE_Req_N or E_err_IDLE_grant_N or E_err_North_Req_N or E_err_North_grant_N or E_err_Local_Req_N or E_err_Local_grant_N or E_err_South_Req_N or E_err_South_grant_N or E_err_West_Req_N or E_err_West_grant_N or E_err_East_Req_N or E_err_East_grant_N or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_East_req_X_E or N_err_East_credit_not_zero_req_X_E_grant_E or N_err_East_credit_zero_or_not_req_X_E_not_grant_E or N_err_IDLE_req_X_E or N_err_North_req_X_E or N_err_Local_req_X_E or N_err_South_req_X_E or N_err_West_req_X_E or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_Grants_onehot_or_all_zero or err_grant_N_E_sig_not_empty_E_grant_N_E or err_not_grant_N_E_sig_or_empty_E_not_grant_N_E or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO E2S_turn_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_S1 or E_err_dst_addr_cur_addr_not_S1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or E_err_header_not_empty_Req_S_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_South_Req_S or E_err_South_grant_S or E_err_West_Req_S or E_err_West_grant_S or E_err_East_Req_S or E_err_East_grant_S or E_err_IDLE_Req_S or E_err_IDLE_grant_S or E_err_North_Req_S or E_err_North_grant_S or E_err_Local_Req_S or E_err_Local_grant_S or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_East_req_X_E or S_err_East_credit_not_zero_req_X_E_grant_E or S_err_East_credit_zero_or_not_req_X_E_not_grant_E or S_err_IDLE_req_X_E or S_err_North_req_X_E or S_err_Local_req_X_E or S_err_South_req_X_E or S_err_West_req_X_E or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_E_sig_not_empty_E_grant_S_E or err_not_grant_S_E_sig_or_empty_E_not_grant_S_E or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO W2N_turn_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_N1 or W_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_N_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_IDLE_Req_N or W_err_IDLE_grant_N or W_err_North_Req_N or W_err_North_grant_N or W_err_Local_Req_N or W_err_Local_grant_N or W_err_South_Req_N or W_err_South_grant_N or W_err_West_Req_N or W_err_West_grant_N or W_err_East_Req_N or W_err_East_grant_N or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_West_req_X_W or N_err_West_credit_not_zero_req_X_W_grant_W or N_err_West_credit_zero_or_not_req_X_W_not_grant_W or N_err_East_req_X_W or N_err_IDLE_req_X_W or N_err_North_req_X_W or N_err_Local_req_X_W or N_err_South_req_X_W or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or err_grant_N_W_sig_not_empty_W_grant_N_W or err_not_grant_N_W_sig_or_empty_W_not_grant_N_W or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO W2S_turn_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_S1 or W_err_dst_addr_cur_addr_not_S1 or W_err_header_not_empty_faulty_drop_packet_in or W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or W_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_S_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_South_Req_S or W_err_South_grant_S or W_err_West_Req_S or W_err_West_grant_S or W_err_East_Req_S or W_err_East_grant_S or W_err_IDLE_Req_S or W_err_IDLE_grant_S or W_err_North_Req_S or W_err_North_grant_S or W_err_Local_Req_S or W_err_Local_grant_S or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_West_req_X_W or S_err_West_credit_not_zero_req_X_W_grant_W or S_err_West_credit_zero_or_not_req_X_W_not_grant_W or S_err_East_req_X_W or S_err_IDLE_req_X_W or S_err_North_req_X_W or S_err_Local_req_X_W or S_err_South_req_X_W or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_W_sig_not_empty_W_grant_S_W or err_not_grant_S_W_sig_or_empty_W_not_grant_S_W or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO S2E_turn_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_E1 or S_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_E_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_East_Req_E or S_err_East_grant_E or S_err_IDLE_Req_E or S_err_IDLE_grant_E or S_err_North_Req_E or S_err_North_grant_E or S_err_Local_Req_E or S_err_Local_grant_E or S_err_South_Req_E or S_err_South_grant_E or S_err_West_Req_E or S_err_West_grant_E or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_South_req_X_S or E_err_South_credit_not_zero_req_X_S_grant_S or E_err_South_credit_zero_or_not_req_X_S_not_grant_S or E_err_West_req_X_S or E_err_East_req_X_S or E_err_IDLE_req_X_S or E_err_North_req_X_S or E_err_Local_req_X_S or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or err_grant_E_S_sig_not_empty_S_grant_E_S or err_not_grant_E_S_sig_or_empty_S_not_grant_E_S or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_grants_valid_not_match or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- FIFO S2W_turn_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_W1 or S_err_dst_addr_cur_addr_not_W1 or S_err_header_not_empty_faulty_drop_packet_in or S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or S_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_W_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_West_Req_W or S_err_West_grant_W or S_err_East_Req_W or S_err_East_grant_W or S_err_IDLE_Req_W or S_err_IDLE_grant_W or S_err_North_Req_W or S_err_North_grant_W or S_err_Local_Req_W or S_err_Local_grant_W or S_err_South_Req_W or S_err_South_grant_W or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_South_req_X_S or W_err_South_credit_not_zero_req_X_S_grant_S or W_err_South_credit_zero_or_not_req_X_S_not_grant_S or W_err_West_req_X_S or W_err_East_req_X_S or W_err_IDLE_req_X_S or W_err_North_req_X_S or W_err_Local_req_X_S or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_S_sig_not_empty_S_grant_W_S or err_not_grant_W_S_sig_or_empty_S_not_grant_W_S or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- Path fault checkers -- FIFO N2S_path_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_S1 or N_err_dst_addr_cur_addr_not_S1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or N_err_header_not_empty_Req_S_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_South_Req_S or N_err_South_grant_S or N_err_West_Req_S or N_err_West_grant_S or N_err_East_Req_S or N_err_East_grant_S or N_err_IDLE_Req_S or N_err_IDLE_grant_S or N_err_North_Req_S or N_err_North_grant_S or N_err_Local_Req_S or N_err_Local_grant_S or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_IDLE_req_X_N or S_err_North_req_X_N or S_err_North_credit_not_zero_req_X_N_grant_N or S_err_North_credit_zero_or_not_req_X_N_not_grant_N or S_err_Local_req_X_N or S_err_South_req_X_N or S_err_West_req_X_N or S_err_East_req_X_N or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_N_sig_not_empty_N_grant_S_N or err_not_grant_S_N_sig_or_empty_N_not_grant_S_N or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO S2N_path_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_N1 or S_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or S_err_header_not_empty_Req_N_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_IDLE_Req_N or S_err_IDLE_grant_N or S_err_North_Req_N or S_err_North_grant_N or S_err_Local_Req_N or S_err_Local_grant_N or S_err_South_Req_N or S_err_South_grant_N or S_err_West_Req_N or S_err_West_grant_N or S_err_East_Req_N or S_err_East_grant_N or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_South_req_X_S or N_err_South_credit_not_zero_req_X_S_grant_S or N_err_South_credit_zero_or_not_req_X_S_not_grant_S or N_err_West_req_X_S or N_err_East_req_X_S or N_err_IDLE_req_X_S or N_err_North_req_X_S or N_err_Local_req_X_S or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or err_grant_N_S_sig_not_empty_S_grant_N_S or err_not_grant_N_S_sig_or_empty_S_not_grant_N_S or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO E2W_path_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_W1 or E_err_dst_addr_cur_addr_not_W1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or E_err_header_not_empty_Req_W_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_West_Req_W or E_err_West_grant_W or E_err_East_Req_W or E_err_East_grant_W or E_err_IDLE_Req_W or E_err_IDLE_grant_W or E_err_North_Req_W or E_err_North_grant_W or E_err_Local_Req_W or E_err_Local_grant_W or E_err_South_Req_W or E_err_South_grant_W or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_East_req_X_E or W_err_East_credit_not_zero_req_X_E_grant_E or W_err_East_credit_zero_or_not_req_X_E_not_grant_E or W_err_IDLE_req_X_E or W_err_North_req_X_E or W_err_Local_req_X_E or W_err_South_req_X_E or W_err_West_req_X_E or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_E_sig_not_empty_E_grant_W_E or err_not_grant_W_E_sig_or_empty_E_not_grant_W_E or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- FIFO W2E_path_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_E1 or W_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or W_err_header_not_empty_Req_E_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_East_Req_E or W_err_East_grant_E or W_err_IDLE_Req_E or W_err_IDLE_grant_E or W_err_North_Req_E or W_err_North_grant_E or W_err_Local_Req_E or W_err_Local_grant_E or W_err_South_Req_E or W_err_South_grant_E or W_err_West_Req_E or W_err_West_grant_E or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_West_req_X_W or E_err_West_credit_not_zero_req_X_W_grant_W or E_err_West_credit_zero_or_not_req_X_W_not_grant_W or E_err_East_req_X_W or E_err_IDLE_req_X_W or E_err_North_req_X_W or E_err_Local_req_X_W or E_err_South_req_X_W or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or err_grant_E_W_sig_not_empty_W_grant_E_W or err_not_grant_E_W_sig_or_empty_W_not_grant_E_W or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- Checkers for Paths/turns from/to Local port -- FIFO L2N_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_N1 or L_err_dst_addr_cur_addr_not_N1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_N_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_IDLE_Req_N or L_err_IDLE_grant_N or L_err_North_Req_N or L_err_North_grant_N or L_err_Local_Req_N or L_err_Local_grant_N or L_err_South_Req_N or L_err_South_grant_N or L_err_West_Req_N or L_err_West_grant_N or L_err_East_Req_N or L_err_East_grant_N or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_N_grant_N or N_arbiter_out_err_Requests_state_in_state_not_equal or N_err_Local_req_X_L or N_err_Local_credit_not_zero_req_X_L_grant_L or N_err_Local_credit_zero_or_not_req_X_L_not_grant_L or N_err_South_req_X_L or N_err_West_req_X_L or N_err_East_req_X_L or N_err_IDLE_req_X_L or N_err_North_req_X_L or N_arbiter_out_err_state_in_onehot or N_arbiter_out_err_no_request_grants or N_err_request_IDLE_state or N_err_request_IDLE_not_Grants or N_err_Grants_onehot_or_all_zero or err_grant_N_L_sig_not_empty_L_grant_N_L or err_not_grant_N_L_sig_or_empty_L_not_grant_N_L or err_grant_signals_not_empty_grant_N or err_not_grant_signals_empty_not_grant_N or err_grants_valid_not_match or err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal or err_credit_in_N_credit_counter_N_out_increment or err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change or err_grant_N_credit_counter_N_out_decrement or err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change or err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal; -- FIFO L2E_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_E1 or L_err_dst_addr_cur_addr_not_E1 or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_E_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_East_Req_E or L_err_East_grant_E or L_err_IDLE_Req_E or L_err_IDLE_grant_E or L_err_North_Req_E or L_err_North_grant_E or L_err_Local_Req_E or L_err_Local_grant_E or L_err_South_Req_E or L_err_South_grant_E or L_err_West_Req_E or L_err_West_grant_E or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_E_grant_E or E_arbiter_out_err_Requests_state_in_state_not_equal or E_err_Local_req_X_L or E_err_Local_credit_not_zero_req_X_L_grant_L or E_err_Local_credit_zero_or_not_req_X_L_not_grant_L or E_err_South_req_X_L or E_err_West_req_X_L or E_err_East_req_X_L or E_err_IDLE_req_X_L or E_err_North_req_X_L or E_arbiter_out_err_state_in_onehot or E_arbiter_out_err_no_request_grants or E_err_request_IDLE_state or E_err_request_IDLE_not_Grants or E_err_Grants_onehot_or_all_zero or err_grant_E_L_sig_not_empty_L_grant_E_L or err_not_grant_E_L_sig_or_empty_L_not_grant_E_L or err_grant_signals_not_empty_grant_E or err_not_grant_signals_empty_not_grant_E or err_grants_valid_not_match or err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal or err_credit_in_E_credit_counter_E_out_increment or err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change or err_grant_E_credit_counter_E_out_decrement or err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change or err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal; -- FIFO L2W_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_W1 or L_err_dst_addr_cur_addr_not_W1 or L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_W_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_West_Req_W or L_err_West_grant_W or L_err_East_Req_W or L_err_East_grant_W or L_err_IDLE_Req_W or L_err_IDLE_grant_W or L_err_North_Req_W or L_err_North_grant_W or L_err_Local_Req_W or L_err_Local_grant_W or L_err_South_Req_W or L_err_South_grant_W or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_W_grant_W or W_arbiter_out_err_Requests_state_in_state_not_equal or W_err_Local_req_X_L or W_err_Local_credit_not_zero_req_X_L_grant_L or W_err_Local_credit_zero_or_not_req_X_L_not_grant_L or W_err_South_req_X_L or W_err_West_req_X_L or W_err_East_req_X_L or W_err_IDLE_req_X_L or W_err_North_req_X_L or W_arbiter_out_err_state_in_onehot or W_arbiter_out_err_no_request_grants or W_err_request_IDLE_state or W_err_request_IDLE_not_Grants or W_err_Grants_onehot_or_all_zero or err_grant_W_L_sig_not_empty_L_grant_W_L or err_not_grant_W_L_sig_or_empty_L_not_grant_W_L or err_grant_signals_not_empty_grant_W or err_not_grant_signals_empty_not_grant_W or err_grants_valid_not_match or err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal or err_credit_in_W_credit_counter_W_out_increment or err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change or err_grant_W_credit_counter_W_out_decrement or err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change or err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal; -- FIFO L2S_fault <= L_FIFO_checkers_ORed or -- LBDR L_err_header_empty_Requests_FF_Requests_in or L_err_tail_Requests_in_all_zero or L_err_tail_empty_Requests_FF_Requests_in or L_err_tail_not_empty_not_grants_Requests_FF_Requests_in or L_err_grants_onehot or L_err_grants_mismatch or L_err_header_tail_Requests_FF_Requests_in or L_err_dst_addr_cur_addr_S1 or L_err_dst_addr_cur_addr_not_S1 or L_err_header_not_empty_faulty_drop_packet_in or L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or L_err_header_not_empty_faulty_Req_in_all_zero or L_err_header_not_empty_Req_S_in or L_err_header_empty_packet_drop_in_packet_drop_equal or L_err_tail_not_empty_packet_drop_not_packet_drop_in or L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or L_err_packet_drop_order or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator L_err_Requests_state_in_state_not_equal or L_err_South_Req_S or L_err_South_grant_S or L_err_West_Req_S or L_err_West_grant_S or L_err_East_Req_S or L_err_East_grant_S or L_err_IDLE_Req_S or L_err_IDLE_grant_S or L_err_North_Req_S or L_err_North_grant_S or L_err_Local_Req_S or L_err_Local_grant_S or L_err_state_in_onehot or L_err_no_request_grants or L_err_request_no_grants or L_err_no_Req_S_grant_S or S_arbiter_out_err_Requests_state_in_state_not_equal or S_err_Local_req_X_L or S_err_Local_credit_not_zero_req_X_L_grant_L or S_err_Local_credit_zero_or_not_req_X_L_not_grant_L or S_err_South_req_X_L or S_err_West_req_X_L or S_err_East_req_X_L or S_err_IDLE_req_X_L or S_err_North_req_X_L or S_arbiter_out_err_state_in_onehot or S_arbiter_out_err_no_request_grants or S_err_request_IDLE_state or S_err_request_IDLE_not_Grants or S_err_Grants_onehot_or_all_zero or err_grant_S_L_sig_not_empty_L_grant_S_L or err_not_grant_S_L_sig_or_empty_L_not_grant_S_L or err_grant_signals_not_empty_grant_S or err_not_grant_signals_empty_not_grant_S or err_grants_valid_not_match or err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal or err_credit_in_S_credit_counter_S_out_increment or err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change or err_grant_S_credit_counter_S_out_decrement or err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change or err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal; -- FIFO N2L_fault <= N_FIFO_checkers_ORed or -- LBDR N_err_header_empty_Requests_FF_Requests_in or N_err_tail_Requests_in_all_zero or N_err_tail_empty_Requests_FF_Requests_in or N_err_tail_not_empty_not_grants_Requests_FF_Requests_in or N_err_grants_onehot or N_err_grants_mismatch or N_err_header_tail_Requests_FF_Requests_in or N_err_dst_addr_cur_addr_Req_L_in or N_err_dst_addr_cur_addr_not_Req_L_in or N_err_header_not_empty_faulty_drop_packet_in or N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or N_err_header_not_empty_faulty_Req_in_all_zero or --N_err_header_not_empty_Req_L_in or N_err_header_empty_packet_drop_in_packet_drop_equal or N_err_tail_not_empty_packet_drop_not_packet_drop_in or N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or N_err_packet_drop_order or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator N_err_Requests_state_in_state_not_equal or N_err_Local_Req_L or N_err_Local_grant_L or N_err_South_Req_L or N_err_South_grant_L or N_err_West_Req_L or N_err_West_grant_L or N_err_East_Req_L or N_err_East_grant_L or N_err_IDLE_Req_L or N_err_IDLE_grant_L or N_err_North_Req_L or N_err_North_grant_L or N_err_state_in_onehot or N_err_no_request_grants or N_err_request_no_grants or N_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_IDLE_req_X_N or L_err_North_req_X_N or L_err_North_credit_not_zero_req_X_N_grant_N or L_err_North_credit_zero_or_not_req_X_N_not_grant_N or L_err_Local_req_X_N or L_err_South_req_X_N or L_err_West_req_X_N or L_err_East_req_X_N or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_N_sig_not_empty_N_grant_L_N or err_not_grant_L_N_sig_or_empty_N_not_grant_L_N or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; -- FIFO E2L_fault <= E_FIFO_checkers_ORed or -- LBDR E_err_header_empty_Requests_FF_Requests_in or E_err_tail_Requests_in_all_zero or E_err_tail_empty_Requests_FF_Requests_in or E_err_tail_not_empty_not_grants_Requests_FF_Requests_in or E_err_grants_onehot or E_err_grants_mismatch or E_err_header_tail_Requests_FF_Requests_in or E_err_dst_addr_cur_addr_Req_L_in or E_err_dst_addr_cur_addr_not_Req_L_in or E_err_header_not_empty_faulty_drop_packet_in or E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or E_err_header_not_empty_faulty_Req_in_all_zero or --E_err_header_not_empty_Req_L_in or E_err_header_empty_packet_drop_in_packet_drop_equal or E_err_tail_not_empty_packet_drop_not_packet_drop_in or E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or E_err_packet_drop_order or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator E_err_Requests_state_in_state_not_equal or E_err_Local_Req_L or E_err_Local_grant_L or E_err_South_Req_L or E_err_South_grant_L or E_err_West_Req_L or E_err_West_grant_L or E_err_East_Req_L or E_err_East_grant_L or E_err_IDLE_Req_L or E_err_IDLE_grant_L or E_err_North_Req_L or E_err_North_grant_L or E_err_state_in_onehot or E_err_no_request_grants or E_err_request_no_grants or E_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_East_req_X_E or L_err_East_credit_not_zero_req_X_E_grant_E or L_err_East_credit_zero_or_not_req_X_E_not_grant_E or L_err_IDLE_req_X_E or L_err_North_req_X_E or L_err_Local_req_X_E or L_err_South_req_X_E or L_err_West_req_X_E or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_E_sig_not_empty_E_grant_L_E or err_not_grant_L_E_sig_or_empty_E_not_grant_L_E or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; -- FIFO W2L_fault <= W_FIFO_checkers_ORed or -- LBDR W_err_header_empty_Requests_FF_Requests_in or W_err_tail_Requests_in_all_zero or W_err_tail_empty_Requests_FF_Requests_in or W_err_tail_not_empty_not_grants_Requests_FF_Requests_in or W_err_grants_onehot or W_err_grants_mismatch or W_err_header_tail_Requests_FF_Requests_in or W_err_dst_addr_cur_addr_Req_L_in or W_err_dst_addr_cur_addr_not_Req_L_in or W_err_header_not_empty_faulty_drop_packet_in or W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or W_err_header_not_empty_faulty_Req_in_all_zero or --W_err_header_not_empty_Req_L_in or W_err_header_empty_packet_drop_in_packet_drop_equal or W_err_tail_not_empty_packet_drop_not_packet_drop_in or W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or W_err_packet_drop_order or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator W_err_Requests_state_in_state_not_equal or W_err_Local_Req_L or W_err_Local_grant_L or W_err_South_Req_L or W_err_South_grant_L or W_err_West_Req_L or W_err_West_grant_L or W_err_East_Req_L or W_err_East_grant_L or W_err_IDLE_Req_L or W_err_IDLE_grant_L or W_err_North_Req_L or W_err_North_grant_L or W_err_state_in_onehot or W_err_no_request_grants or W_err_request_no_grants or W_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_West_req_X_W or L_err_West_credit_not_zero_req_X_W_grant_W or L_err_West_credit_zero_or_not_req_X_W_not_grant_W or L_err_East_req_X_W or L_err_IDLE_req_X_W or L_err_North_req_X_W or L_err_Local_req_X_W or L_err_South_req_X_W or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_W_sig_not_empty_W_grant_L_W or err_not_grant_L_W_sig_or_empty_W_not_grant_L_W or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; -- FIFO S2L_fault <= S_FIFO_checkers_ORed or -- LBDR S_err_header_empty_Requests_FF_Requests_in or S_err_tail_Requests_in_all_zero or S_err_tail_empty_Requests_FF_Requests_in or S_err_tail_not_empty_not_grants_Requests_FF_Requests_in or S_err_grants_onehot or S_err_grants_mismatch or S_err_header_tail_Requests_FF_Requests_in or S_err_dst_addr_cur_addr_Req_L_in or S_err_dst_addr_cur_addr_not_Req_L_in or S_err_header_not_empty_faulty_drop_packet_in or S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change or S_err_header_not_empty_faulty_Req_in_all_zero or --S_err_header_not_empty_Req_L_in or S_err_header_empty_packet_drop_in_packet_drop_equal or S_err_tail_not_empty_packet_drop_not_packet_drop_in or S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal or S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal or S_err_packet_drop_order or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp or S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal or S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in or S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal or S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal or -- Added S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal or -- Added -- Allocator S_err_Requests_state_in_state_not_equal or S_err_Local_Req_L or S_err_Local_grant_L or S_err_South_Req_L or S_err_South_grant_L or S_err_West_Req_L or S_err_West_grant_L or S_err_East_Req_L or S_err_East_grant_L or S_err_IDLE_Req_L or S_err_IDLE_grant_L or S_err_North_Req_L or S_err_North_grant_L or S_err_state_in_onehot or S_err_no_request_grants or S_err_request_no_grants or S_err_no_Req_L_grant_L or L_arbiter_out_err_Requests_state_in_state_not_equal or L_err_South_req_X_S or L_err_South_credit_not_zero_req_X_S_grant_S or L_err_South_credit_zero_or_not_req_X_S_not_grant_S or L_err_West_req_X_S or L_err_East_req_X_S or L_err_IDLE_req_X_S or L_err_North_req_X_S or L_err_Local_req_X_S or L_arbiter_out_err_state_in_onehot or L_arbiter_out_err_no_request_grants or L_err_request_IDLE_state or L_err_request_IDLE_not_Grants or L_err_Grants_onehot_or_all_zero or err_grant_L_S_sig_not_empty_S_grant_L_S or err_not_grant_L_S_sig_or_empty_S_not_grant_L_S or err_grant_signals_not_empty_grant_L or err_not_grant_signals_empty_not_grant_L or err_grants_valid_not_match or err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal or err_credit_in_L_credit_counter_L_out_increment or err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change or err_grant_L_credit_counter_L_out_decrement or err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change or err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- Link faults and turn faults -- The order of the turns/paths from left to right (MSB to LSB) -> 20 bits -- N2E, N2W, E2N, E2S, -- W2N, W2S, S2E, S2W, -- N2S, S2N, E2W, W2E, -- L2N, L2E, L2W, L2S, -- N2L, E2L, W2L, S2L ------------------------------------------------------------------------------------------------------------------------------ -- Taking classified fault information to output ------------------------------------------------------------------------------------------------------------------------------ turn_faults <= faulty_N2E_turn_fault & faulty_N2W_turn_fault & faulty_E2N_turn_fault & faulty_E2S_turn_fault & faulty_W2N_turn_fault & faulty_W2S_turn_fault & faulty_S2E_turn_fault & faulty_S2W_turn_fault & faulty_N2S_path_fault & faulty_S2N_path_fault & faulty_E2W_path_fault & faulty_W2E_path_fault & faulty_L2N_fault & faulty_L2E_fault & faulty_L2W_fault & faulty_L2S_fault & faulty_N2L_fault & faulty_E2L_fault & faulty_W2L_fault & faulty_S2L_fault; -- 20 bits because of turn/path faults --link_faults <= '0' & '0' & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L; -- sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L; link_faults <= sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L; ------------------------------------------------------------------------------------------------------------------------------ -- Taking non-classified fault information to output ------------------------------------------------------------------------------------------------------------------------------ turn_faults_async <= N2E_turn_fault & N2W_turn_fault & E2N_turn_fault & E2S_turn_fault & W2N_turn_fault & W2S_turn_fault & S2E_turn_fault & S2W_turn_fault & N2S_path_fault & S2N_path_fault & E2W_path_fault & W2E_path_fault & L2N_fault & L2E_fault & L2W_fault & L2S_fault & N2L_fault & E2L_fault & W2L_fault & S2L_fault; -- 20 bits because of turn/path faults --link_faults_async <= '0' & '0' & faulty_packet_W & faulty_packet_S & faulty_packet_L; -- faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L; link_faults_async <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L; ------------------------------------------------------------------------------------------------------------------------------ Faulty_N_out <= sig_Faulty_N_out; Faulty_E_out <= sig_Faulty_E_out; Faulty_W_out <= sig_Faulty_W_out; Faulty_S_out <= sig_Faulty_S_out; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the counter_threshold modules CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N, Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out); CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E, Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out); CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W, Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out); CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S, Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out); CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L, Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Checker Counter Threshold modules -- Turn faults CHK_CT_N2E_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2E_turn_fault, Healthy_packet => not_N2E_turn_fault, Healthy => Healthy_N2E_turn_fault, Intermittent => intermittent_N2E_turn_fault, Faulty => faulty_N2E_turn_fault); CHK_CT_N2W_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2W_turn_fault, Healthy_packet => not_N2W_turn_fault, Healthy => Healthy_N2W_turn_fault, Intermittent => intermittent_N2W_turn_fault, Faulty => faulty_N2W_turn_fault); CHK_CT_E2N_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2N_turn_fault, Healthy_packet => not_E2N_turn_fault, Healthy => Healthy_E2N_turn_fault, Intermittent => intermittent_E2N_turn_fault, Faulty => faulty_E2N_turn_fault); CHK_CT_E2S_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2S_turn_fault, Healthy_packet => not_E2S_turn_fault, Healthy => Healthy_E2S_turn_fault, Intermittent => intermittent_E2S_turn_fault, Faulty => faulty_E2S_turn_fault); CHK_CT_W2N_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2N_turn_fault, Healthy_packet => not_W2N_turn_fault, Healthy => Healthy_W2N_turn_fault, Intermittent => intermittent_W2N_turn_fault, Faulty => faulty_W2N_turn_fault); CHK_CT_W2S_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2S_turn_fault, Healthy_packet => not_W2S_turn_fault, Healthy => Healthy_W2S_turn_fault, Intermittent => intermittent_W2S_turn_fault, Faulty => faulty_W2S_turn_fault); CHK_CT_S2E_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2E_turn_fault, Healthy_packet => not_S2E_turn_fault, Healthy => Healthy_S2E_turn_fault, Intermittent => intermittent_S2E_turn_fault, Faulty => faulty_S2E_turn_fault); CHK_CT_S2W_turn_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2W_turn_fault, Healthy_packet => not_S2W_turn_fault, Healthy => Healthy_S2W_turn_fault, Intermittent => intermittent_S2W_turn_fault, Faulty => faulty_S2W_turn_fault); --Path faults CHK_CT_N2S_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2S_path_fault, Healthy_packet => not_N2S_path_fault, Healthy => Healthy_N2S_path_fault, Intermittent => intermittent_N2S_path_fault, Faulty => faulty_N2S_path_fault); CHK_CT_S2N_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2N_path_fault, Healthy_packet => not_S2N_path_fault, Healthy => Healthy_S2N_path_fault, Intermittent => intermittent_S2N_path_fault, Faulty => faulty_S2N_path_fault); CHK_CT_E2W_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2W_path_fault, Healthy_packet => not_E2W_path_fault, Healthy => Healthy_E2W_path_fault, Intermittent => intermittent_E2W_path_fault, Faulty => faulty_E2W_path_fault); CHK_CT_W2E_path_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2E_path_fault, Healthy_packet => not_W2E_path_fault, Healthy => Healthy_W2E_path_fault, Intermittent => intermittent_W2E_path_fault, Faulty => faulty_W2E_path_fault); -- Local port related faults (to/from local port) CHK_CT_L2N_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2N_fault, Healthy_packet => not_L2N_fault, Healthy => Healthy_L2N_fault, Intermittent => intermittent_L2N_fault, Faulty => faulty_L2N_fault); CHK_CT_L2E_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2E_fault, Healthy_packet => not_L2E_fault, Healthy => Healthy_L2E_fault, Intermittent => intermittent_L2E_fault, Faulty => faulty_L2E_fault); CHK_CT_L2W_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2W_fault, Healthy_packet => not_L2W_fault, Healthy => Healthy_L2W_fault, Intermittent => intermittent_L2W_fault, Faulty => faulty_L2W_fault); CHK_CT_L2S_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => L2S_fault, Healthy_packet => not_L2S_fault, Healthy => Healthy_L2S_fault, Intermittent => intermittent_L2S_fault, Faulty => faulty_L2S_fault); CHK_CT_N2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => N2L_fault, Healthy_packet => not_N2L_fault, Healthy => Healthy_N2L_fault, Intermittent => intermittent_N2L_fault, Faulty => faulty_N2L_fault); CHK_CT_E2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => E2L_fault, Healthy_packet => not_E2L_fault, Healthy => Healthy_E2L_fault, Intermittent => intermittent_E2L_fault, Faulty => faulty_E2L_fault); CHK_CT_W2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => W2L_fault, Healthy_packet => not_W2L_fault, Healthy => Healthy_W2L_fault, Intermittent => intermittent_W2L_fault, Faulty => faulty_W2L_fault); CHK_CT_S2L_fault: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold) port map(reset => reset, clk => clk, faulty_packet => S2L_fault, Healthy_packet => not_S2L_fault, Healthy => Healthy_S2L_fault, Intermittent => intermittent_S2L_fault, Faulty => faulty_S2L_fault); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- All the FIFOs FIFO_N: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N, read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN, credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_FIFO_to_N_FIFO, SO=> fault_DO_serial_N_FIFO_to_E_FIFO, -- Checker outputs -- Functional checkers err_empty_full => N_err_empty_full, err_empty_read_en => N_err_empty_read_en, err_full_write_en => N_err_full_write_en, err_state_in_onehot => N_err_state_in_onehot, err_read_pointer_in_onehot => N_err_read_pointer_in_onehot, err_write_pointer_in_onehot => N_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => N_err_write_en_write_pointer, err_not_write_en_write_pointer => N_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => N_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => N_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => N_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => N_err_read_pointer_write_pointer_full, err_read_pointer_increment => N_err_read_pointer_increment, err_read_pointer_not_increment => N_err_read_pointer_not_increment, err_write_en => N_err_write_en, err_not_write_en => N_err_not_write_en, err_not_write_en1 => N_err_not_write_en1, err_not_write_en2 => N_err_not_write_en2, err_read_en_mismatch => N_err_read_en_mismatch, err_read_en_mismatch1 => N_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => N_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => N_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => N_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => N_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => N_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => N_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => N_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => N_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => N_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => N_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => N_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => N_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => N_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => N_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => N_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => N_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => N_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => N_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => N_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => N_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => N_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => N_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => N_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => N_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => N_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => N_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => N_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => N_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => N_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => N_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => N_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => N_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => N_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => N_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => N_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => N_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => N_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => N_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => N_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => N_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => N_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => N_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => N_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => N_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => N_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => N_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => N_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => N_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => N_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => N_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => N_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => N_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => N_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => N_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_E: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E, read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE, credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_FIFO_to_E_FIFO, SO=> fault_DO_serial_E_FIFO_to_W_FIFO, -- Checker outputs -- Functional checkers err_empty_full => E_err_empty_full, err_empty_read_en => E_err_empty_read_en, err_full_write_en => E_err_full_write_en, err_state_in_onehot => E_err_state_in_onehot, err_read_pointer_in_onehot => E_err_read_pointer_in_onehot, err_write_pointer_in_onehot => E_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => E_err_write_en_write_pointer, err_not_write_en_write_pointer => E_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => E_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => E_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => E_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => E_err_read_pointer_write_pointer_full, err_read_pointer_increment => E_err_read_pointer_increment, err_read_pointer_not_increment => E_err_read_pointer_not_increment, err_write_en => E_err_write_en, err_not_write_en => E_err_not_write_en, err_not_write_en1 => E_err_not_write_en1, err_not_write_en2 => E_err_not_write_en2, err_read_en_mismatch => E_err_read_en_mismatch, err_read_en_mismatch1 => E_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => E_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => E_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => E_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => E_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => E_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => E_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => E_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => E_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => E_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => E_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => E_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => E_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => E_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => E_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => E_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => E_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => E_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => E_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => E_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => E_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => E_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => E_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => E_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => E_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => E_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => E_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => E_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => E_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => E_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => E_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => E_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => E_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => E_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => E_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => E_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => E_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => E_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => E_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => E_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => E_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => E_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => E_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_W: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W, read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW, credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_FIFO_to_W_FIFO, SO=> fault_DO_serial_W_FIFO_to_S_FIFO, -- Checker outputs -- Functional checkers err_empty_full => W_err_empty_full, err_empty_read_en => W_err_empty_read_en, err_full_write_en => W_err_full_write_en, err_state_in_onehot => W_err_state_in_onehot, err_read_pointer_in_onehot => W_err_read_pointer_in_onehot, err_write_pointer_in_onehot => W_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => W_err_write_en_write_pointer, err_not_write_en_write_pointer => W_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => W_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => W_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => W_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => W_err_read_pointer_write_pointer_full, err_read_pointer_increment => W_err_read_pointer_increment, err_read_pointer_not_increment => W_err_read_pointer_not_increment, err_write_en => W_err_write_en, err_not_write_en => W_err_not_write_en, err_not_write_en1 => W_err_not_write_en1, err_not_write_en2 => W_err_not_write_en2, err_read_en_mismatch => W_err_read_en_mismatch, err_read_en_mismatch1 => W_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => W_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => W_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => W_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => W_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => W_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => W_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => W_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => W_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => W_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => W_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => W_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => W_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => W_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => W_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => W_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => W_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => W_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => W_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => W_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => W_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => W_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => W_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => W_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => W_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => W_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => W_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => W_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => W_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => W_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => W_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => W_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => W_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => W_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => W_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => W_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => W_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => W_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => W_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => W_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => W_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => W_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => W_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_S: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S, read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS, credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_FIFO_to_S_FIFO, SO=> fault_DO_serial_S_FIFO_to_L_LBDR, -- Checker outputs -- Functional checkers err_empty_full => S_err_empty_full, err_empty_read_en => S_err_empty_read_en, err_full_write_en => S_err_full_write_en, err_state_in_onehot => S_err_state_in_onehot, err_read_pointer_in_onehot => S_err_read_pointer_in_onehot, err_write_pointer_in_onehot => S_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => S_err_write_en_write_pointer, err_not_write_en_write_pointer => S_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => S_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => S_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => S_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => S_err_read_pointer_write_pointer_full, err_read_pointer_increment => S_err_read_pointer_increment, err_read_pointer_not_increment => S_err_read_pointer_not_increment, err_write_en => S_err_write_en, err_not_write_en => S_err_not_write_en, err_not_write_en1 => S_err_not_write_en1, err_not_write_en2 => S_err_not_write_en2, err_read_en_mismatch => S_err_read_en_mismatch, err_read_en_mismatch1 => S_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => S_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => S_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => S_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => S_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => S_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => S_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => S_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => S_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => S_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => S_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => S_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => S_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => S_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => S_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => S_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => S_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => S_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => S_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => S_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => S_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => S_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => S_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => S_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => S_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => S_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => S_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => S_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => S_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => S_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => S_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => S_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => S_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => S_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => S_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => S_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => S_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => S_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => S_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => S_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => S_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => S_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => S_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); FIFO_L: FIFO_credit_based generic map ( DATA_WIDTH => DATA_WIDTH) port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L, read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L, credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L, TCK=> TCK, SE=> SE, UE=> UE, SI=> SI, SO=> fault_DO_serial_L_FIFO_to_N_FIFO, -- Checker outputs -- Functional checkers err_empty_full => L_err_empty_full, err_empty_read_en => L_err_empty_read_en, err_full_write_en => L_err_full_write_en, err_state_in_onehot => L_err_state_in_onehot, err_read_pointer_in_onehot => L_err_read_pointer_in_onehot, err_write_pointer_in_onehot => L_err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer => L_err_write_en_write_pointer, err_not_write_en_write_pointer => L_err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty => L_err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty => L_err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full => L_err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full => L_err_read_pointer_write_pointer_full, err_read_pointer_increment => L_err_read_pointer_increment, err_read_pointer_not_increment => L_err_read_pointer_not_increment, err_write_en => L_err_write_en, err_not_write_en => L_err_not_write_en, err_not_write_en1 => L_err_not_write_en1, err_not_write_en2 => L_err_not_write_en2, err_read_en_mismatch => L_err_read_en_mismatch, err_read_en_mismatch1 => L_err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment => L_err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change => L_err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change => L_err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out => L_err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => L_err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => L_err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => L_err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit => L_err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in => L_err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit => L_err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop => L_err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in => L_err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in => L_err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info => L_err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit => L_err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in => L_err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit => L_err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => L_err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => L_err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => L_err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in => L_err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => L_err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info => L_err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info => L_err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit => L_err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit => L_err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => L_err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit => L_err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => L_err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => L_err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => L_err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle => L_err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => L_err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in => L_err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit => L_err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit => L_err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => L_err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => L_err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal => L_err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => L_err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => L_err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => L_err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ parity_LBDR_N: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_N, empty_N, LBDR_Fault_N); parity_LBDR_E: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_E, empty_E, LBDR_Fault_E); parity_LBDR_W: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_W, empty_W, LBDR_Fault_W); parity_LBDR_S: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_S, empty_S, LBDR_Fault_S); parity_LBDR_L: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_L, empty_L, LBDR_Fault_L); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ --- all the LBDRs LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_N, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_N, packet_drop_order => packet_drop_order_N, grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN, Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_L_LBDR_to_N_LBDR, SO=> fault_DO_serial_N_LBDR_to_E_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => N_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => N_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => N_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => N_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => N_err_grants_onehot, err_grants_mismatch => N_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => N_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => N_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => N_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => N_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => N_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => N_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => N_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => N_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => N_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => N_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => N_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => N_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => N_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => N_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => N_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => N_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => N_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => N_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => N_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => N_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => N_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => N_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => N_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => N_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => N_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => N_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => N_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => N_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_E, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_E, packet_drop_order => packet_drop_order_E, grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE, Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, -- Needs fixing! TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_N_LBDR_to_E_LBDR, SO=> fault_DO_serial_E_LBDR_to_W_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => E_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => E_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => E_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => E_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => E_err_grants_onehot, err_grants_mismatch => E_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => E_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => E_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => E_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => E_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => E_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => E_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => E_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => E_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => E_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => E_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => E_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => E_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => E_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => E_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => E_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => E_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => E_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => E_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => E_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => E_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => E_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => E_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => E_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => E_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => E_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => E_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => E_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => E_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_W, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_W, packet_drop_order => packet_drop_order_W, grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW, Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_E_LBDR_to_W_LBDR, SO=> fault_DO_serial_W_LBDR_to_S_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => W_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => W_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => W_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => W_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => W_err_grants_onehot, err_grants_mismatch => W_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => W_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => W_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => W_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => W_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => W_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => W_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => W_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => W_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => W_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => W_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => W_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => W_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => W_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => W_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => W_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => W_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => W_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => W_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => W_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => W_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => W_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => W_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => W_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => W_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => W_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => W_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => W_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => W_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_S, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_S, packet_drop_order => packet_drop_order_S, grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS, Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_W_LBDR_to_S_LBDR, SO=> fault_DO_serial_S_LBDR_to_Allocator, -- Checker outputs err_header_empty_Requests_FF_Requests_in => S_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => S_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => S_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => S_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => S_err_grants_onehot, err_grants_mismatch => S_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => S_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => S_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => S_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => S_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => S_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => S_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => S_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => S_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => S_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => S_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => S_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => S_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => S_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => S_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => S_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => S_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => S_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => S_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => S_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => S_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => S_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => S_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => S_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => S_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => S_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => S_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => S_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => S_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size) PORT MAP (reset => reset, clk => clk, empty => empty_L, Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) , faulty => LBDR_Fault_L, packet_drop_order => packet_drop_order_L, grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0', Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL, Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_FIFO_to_L_LBDR, SO=> fault_DO_serial_L_LBDR_to_N_LBDR, -- Checker outputs err_header_empty_Requests_FF_Requests_in => L_err_header_empty_Requests_FF_Requests_in, err_tail_Requests_in_all_zero => L_err_tail_Requests_in_all_zero, err_tail_empty_Requests_FF_Requests_in => L_err_tail_empty_Requests_FF_Requests_in, err_tail_not_empty_not_grants_Requests_FF_Requests_in => L_err_tail_not_empty_not_grants_Requests_FF_Requests_in, err_grants_onehot => L_err_grants_onehot, err_grants_mismatch => L_err_grants_mismatch, err_header_tail_Requests_FF_Requests_in => L_err_header_tail_Requests_FF_Requests_in, err_dst_addr_cur_addr_N1 => L_err_dst_addr_cur_addr_N1, err_dst_addr_cur_addr_not_N1 => L_err_dst_addr_cur_addr_not_N1, err_dst_addr_cur_addr_E1 => L_err_dst_addr_cur_addr_E1, err_dst_addr_cur_addr_not_E1 => L_err_dst_addr_cur_addr_not_E1, err_dst_addr_cur_addr_W1 => L_err_dst_addr_cur_addr_W1, err_dst_addr_cur_addr_not_W1 => L_err_dst_addr_cur_addr_not_W1, err_dst_addr_cur_addr_S1 => L_err_dst_addr_cur_addr_S1, err_dst_addr_cur_addr_not_S1 => L_err_dst_addr_cur_addr_not_S1, err_dst_addr_cur_addr_Req_L_in => L_err_dst_addr_cur_addr_Req_L_in, err_dst_addr_cur_addr_not_Req_L_in => L_err_dst_addr_cur_addr_not_Req_L_in, err_header_not_empty_faulty_drop_packet_in => L_err_header_not_empty_faulty_drop_packet_in, -- added according to new design err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change => L_err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design err_header_not_empty_faulty_Req_in_all_zero => L_err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design --err_header_not_empty_Req_L_in => L_err_header_not_empty_Req_L_in, -- added according to new design err_header_not_empty_Req_N_in => L_err_header_not_empty_Req_N_in, err_header_not_empty_Req_E_in => L_err_header_not_empty_Req_E_in, err_header_not_empty_Req_W_in => L_err_header_not_empty_Req_W_in, err_header_not_empty_Req_S_in => L_err_header_not_empty_Req_S_in, err_header_empty_packet_drop_in_packet_drop_equal => L_err_header_empty_packet_drop_in_packet_drop_equal, err_tail_not_empty_packet_drop_not_packet_drop_in => L_err_tail_not_empty_packet_drop_not_packet_drop_in, err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal => L_err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal, err_invalid_or_body_flit_packet_drop_in_packet_drop_equal => L_err_invalid_or_body_flit_packet_drop_in_packet_drop_equal, err_packet_drop_order => L_err_packet_drop_order, err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal, err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Reconfig_command_reconfig_cx_in, err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal => L_err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Cx_reconf_PE_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_reconfig_cx_in_reconfig_cx_equal, err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal => L_err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_not_Reconfig_command_Temp_Cx_in_Temp_Cx_equal, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_Rxy_in_Rxy_tmp, err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in => L_err_ReConf_FF_out_flit_type_Tail_not_empty_grants_not_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Rxy_in_Rxy_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_ReConf_FF_in, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_Reconfig_command_Rxy_tmp_in_Rxy_reconf_PE_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_Rxy_tmp_in_Rxy_tmp_equal, err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal => L_err_not_ReConf_FF_out_flit_type_not_Tail_empty_not_grants_not_Reconfig_command_ReConf_FF_in_ReConf_FF_out_equal ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- switch allocator allocator_unit: allocator port map ( reset => reset, clk => clk, -- flow control credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L, -- requests from the LBDRS req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL, req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL, req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL, req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL, req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0', empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L, valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L, -- grant_X_Y means the grant for X output port towards Y input port -- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot! grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL, grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL, grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL, grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL, grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL, TCK=> TCK, SE=> SE, UE=> UE, SI=> fault_DO_serial_S_LBDR_to_Allocator, SO=> SO, -- Make sure this is correction -- Also check inside Allocator's logic -- Checker outputs -- Allocator logic checker outputs err_grant_N_N_sig_not_empty_N_grant_N_N => err_grant_N_N_sig_not_empty_N_grant_N_N , err_not_grant_N_N_sig_or_empty_N_not_grant_N_N => err_not_grant_N_N_sig_or_empty_N_not_grant_N_N , err_grant_N_E_sig_not_empty_E_grant_N_E => err_grant_N_E_sig_not_empty_E_grant_N_E , err_not_grant_N_E_sig_or_empty_E_not_grant_N_E => err_not_grant_N_E_sig_or_empty_E_not_grant_N_E , err_grant_N_W_sig_not_empty_W_grant_N_W => err_grant_N_W_sig_not_empty_W_grant_N_W , err_not_grant_N_W_sig_or_empty_W_not_grant_N_W => err_not_grant_N_W_sig_or_empty_W_not_grant_N_W , err_grant_N_S_sig_not_empty_S_grant_N_S => err_grant_N_S_sig_not_empty_S_grant_N_S , err_not_grant_N_S_sig_or_empty_S_not_grant_N_S => err_not_grant_N_S_sig_or_empty_S_not_grant_N_S , err_grant_N_L_sig_not_empty_L_grant_N_L => err_grant_N_L_sig_not_empty_L_grant_N_L , err_not_grant_N_L_sig_or_empty_L_not_grant_N_L => err_not_grant_N_L_sig_or_empty_L_not_grant_N_L , err_grant_E_N_sig_not_empty_N_grant_E_N => err_grant_E_N_sig_not_empty_N_grant_E_N , err_not_grant_E_N_sig_or_empty_N_not_grant_E_N => err_not_grant_E_N_sig_or_empty_N_not_grant_E_N , err_grant_E_E_sig_not_empty_E_grant_E_E => err_grant_E_E_sig_not_empty_E_grant_E_E , err_not_grant_E_E_sig_or_empty_E_not_grant_E_E => err_not_grant_E_E_sig_or_empty_E_not_grant_E_E , err_grant_E_W_sig_not_empty_W_grant_E_W => err_grant_E_W_sig_not_empty_W_grant_E_W , err_not_grant_E_W_sig_or_empty_W_not_grant_E_W => err_not_grant_E_W_sig_or_empty_W_not_grant_E_W , err_grant_E_S_sig_not_empty_S_grant_E_S => err_grant_E_S_sig_not_empty_S_grant_E_S , err_not_grant_E_S_sig_or_empty_S_not_grant_E_S => err_not_grant_E_S_sig_or_empty_S_not_grant_E_S , err_grant_E_L_sig_not_empty_L_grant_E_L => err_grant_E_L_sig_not_empty_L_grant_E_L , err_not_grant_E_L_sig_or_empty_L_not_grant_E_L => err_not_grant_E_L_sig_or_empty_L_not_grant_E_L , err_grant_W_N_sig_not_empty_N_grant_W_N => err_grant_W_N_sig_not_empty_N_grant_W_N , err_not_grant_W_N_sig_or_empty_N_not_grant_W_N => err_not_grant_W_N_sig_or_empty_N_not_grant_W_N , err_grant_W_E_sig_not_empty_E_grant_W_E => err_grant_W_E_sig_not_empty_E_grant_W_E , err_not_grant_W_E_sig_or_empty_E_not_grant_W_E => err_not_grant_W_E_sig_or_empty_E_not_grant_W_E , err_grant_W_W_sig_not_empty_W_grant_W_W => err_grant_W_W_sig_not_empty_W_grant_W_W , err_not_grant_W_W_sig_or_empty_W_not_grant_W_W => err_not_grant_W_W_sig_or_empty_W_not_grant_W_W , err_grant_W_S_sig_not_empty_S_grant_W_S => err_grant_W_S_sig_not_empty_S_grant_W_S , err_not_grant_W_S_sig_or_empty_S_not_grant_W_S => err_not_grant_W_S_sig_or_empty_S_not_grant_W_S , err_grant_W_L_sig_not_empty_L_grant_W_L => err_grant_W_L_sig_not_empty_L_grant_W_L , err_not_grant_W_L_sig_or_empty_L_not_grant_W_L => err_not_grant_W_L_sig_or_empty_L_not_grant_W_L , err_grant_S_N_sig_not_empty_N_grant_S_N => err_grant_S_N_sig_not_empty_N_grant_S_N , err_not_grant_S_N_sig_or_empty_N_not_grant_S_N => err_not_grant_S_N_sig_or_empty_N_not_grant_S_N , err_grant_S_E_sig_not_empty_E_grant_S_E => err_grant_S_E_sig_not_empty_E_grant_S_E , err_not_grant_S_E_sig_or_empty_E_not_grant_S_E => err_not_grant_S_E_sig_or_empty_E_not_grant_S_E , err_grant_S_W_sig_not_empty_W_grant_S_W => err_grant_S_W_sig_not_empty_W_grant_S_W , err_not_grant_S_W_sig_or_empty_W_not_grant_S_W => err_not_grant_S_W_sig_or_empty_W_not_grant_S_W , err_grant_S_S_sig_not_empty_S_grant_S_S => err_grant_S_S_sig_not_empty_S_grant_S_S , err_not_grant_S_S_sig_or_empty_S_not_grant_S_S => err_not_grant_S_S_sig_or_empty_S_not_grant_S_S , err_grant_S_L_sig_not_empty_L_grant_S_L => err_grant_S_L_sig_not_empty_L_grant_S_L , err_not_grant_S_L_sig_or_empty_L_not_grant_S_L => err_not_grant_S_L_sig_or_empty_L_not_grant_S_L , err_grant_L_N_sig_not_empty_N_grant_L_N => err_grant_L_N_sig_not_empty_N_grant_L_N , err_not_grant_L_N_sig_or_empty_N_not_grant_L_N => err_not_grant_L_N_sig_or_empty_N_not_grant_L_N , err_grant_L_E_sig_not_empty_E_grant_L_E => err_grant_L_E_sig_not_empty_E_grant_L_E , err_not_grant_L_E_sig_or_empty_E_not_grant_L_E => err_not_grant_L_E_sig_or_empty_E_not_grant_L_E , err_grant_L_W_sig_not_empty_W_grant_L_W => err_grant_L_W_sig_not_empty_W_grant_L_W , err_not_grant_L_W_sig_or_empty_W_not_grant_L_W => err_not_grant_L_W_sig_or_empty_W_not_grant_L_W , err_grant_L_S_sig_not_empty_S_grant_L_S => err_grant_L_S_sig_not_empty_S_grant_L_S , err_not_grant_L_S_sig_or_empty_S_not_grant_L_S => err_not_grant_L_S_sig_or_empty_S_not_grant_L_S , err_grant_L_L_sig_not_empty_L_grant_L_L => err_grant_L_L_sig_not_empty_L_grant_L_L , err_not_grant_L_L_sig_or_empty_L_not_grant_L_L => err_not_grant_L_L_sig_or_empty_L_not_grant_L_L , err_grant_signals_not_empty_grant_N => err_grant_signals_not_empty_grant_N , err_not_grant_signals_empty_not_grant_N => err_not_grant_signals_empty_not_grant_N , err_grant_signals_not_empty_grant_E => err_grant_signals_not_empty_grant_E , err_not_grant_signals_empty_not_grant_E => err_not_grant_signals_empty_not_grant_E , err_grant_signals_not_empty_grant_W => err_grant_signals_not_empty_grant_W , err_not_grant_signals_empty_not_grant_W => err_not_grant_signals_empty_not_grant_W , err_grant_signals_not_empty_grant_S => err_grant_signals_not_empty_grant_S , err_not_grant_signals_empty_not_grant_S => err_not_grant_signals_empty_not_grant_S , err_grant_signals_not_empty_grant_L => err_grant_signals_not_empty_grant_L , err_not_grant_signals_empty_not_grant_L => err_not_grant_signals_empty_not_grant_L , err_grants_valid_not_match => err_grants_valid_not_match , -- Allocator credit counter logic checker outputs err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal , err_credit_in_N_credit_counter_N_out_increment => err_credit_in_N_credit_counter_N_out_increment , err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change => err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change , err_grant_N_credit_counter_N_out_decrement => err_grant_N_credit_counter_N_out_decrement , err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change => err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change , err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal => err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal , err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal , err_credit_in_E_credit_counter_E_out_increment => err_credit_in_E_credit_counter_E_out_increment , err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change => err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change , err_grant_E_credit_counter_E_out_decrement => err_grant_E_credit_counter_E_out_decrement , err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change => err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change , err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal => err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal , err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal , err_credit_in_W_credit_counter_W_out_increment => err_credit_in_W_credit_counter_W_out_increment , err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change => err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change , err_grant_W_credit_counter_W_out_decrement => err_grant_W_credit_counter_W_out_decrement , err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change => err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change , err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal => err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal , err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal , err_credit_in_S_credit_counter_S_out_increment => err_credit_in_S_credit_counter_S_out_increment , err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change => err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change , err_grant_S_credit_counter_S_out_decrement => err_grant_S_credit_counter_S_out_decrement , err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change => err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change , err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal => err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal , err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal , err_credit_in_L_credit_counter_L_out_increment => err_credit_in_L_credit_counter_L_out_increment , err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change => err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change , err_grant_L_credit_counter_L_out_decrement => err_grant_L_credit_counter_L_out_decrement , err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change => err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change , err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal => err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal , -- North Arbiter_in Checker outputs N_err_Requests_state_in_state_not_equal => N_err_Requests_state_in_state_not_equal, N_err_IDLE_Req_N => N_err_IDLE_Req_N, N_err_IDLE_grant_N => N_err_IDLE_grant_N, N_err_North_Req_N => N_err_North_Req_N, N_err_North_grant_N => N_err_North_grant_N, N_err_East_Req_E => N_err_East_Req_E, N_err_East_grant_E => N_err_East_grant_E, N_err_West_Req_W => N_err_West_Req_W, N_err_West_grant_W => N_err_West_grant_W, N_err_South_Req_S => N_err_South_Req_S, N_err_South_grant_S => N_err_South_grant_S, N_err_Local_Req_L => N_err_Local_Req_L, N_err_Local_grant_L => N_err_Local_grant_L, N_err_IDLE_Req_E => N_err_IDLE_Req_E, N_err_IDLE_grant_E => N_err_IDLE_grant_E, N_err_North_Req_E => N_err_North_Req_E, N_err_North_grant_E => N_err_North_grant_E, N_err_East_Req_W => N_err_East_Req_W, N_err_East_grant_W => N_err_East_grant_W, N_err_West_Req_S => N_err_West_Req_S, N_err_West_grant_S => N_err_West_grant_S, N_err_South_Req_L => N_err_South_Req_L, N_err_South_grant_L => N_err_South_grant_L, N_err_Local_Req_N => N_err_Local_Req_N, N_err_Local_grant_N => N_err_Local_grant_N, N_err_IDLE_Req_W => N_err_IDLE_Req_W, N_err_IDLE_grant_W => N_err_IDLE_grant_W, N_err_North_Req_W => N_err_North_Req_W, N_err_North_grant_W => N_err_North_grant_W, N_err_East_Req_S => N_err_East_Req_S, N_err_East_grant_S => N_err_East_grant_S, N_err_West_Req_L => N_err_West_Req_L, N_err_West_grant_L => N_err_West_grant_L, N_err_South_Req_N => N_err_South_Req_N, N_err_South_grant_N => N_err_South_grant_N, N_err_Local_Req_E => N_err_Local_Req_E, N_err_Local_grant_E => N_err_Local_grant_E, N_err_IDLE_Req_S => N_err_IDLE_Req_S, N_err_IDLE_grant_S => N_err_IDLE_grant_S, N_err_North_Req_S => N_err_North_Req_S, N_err_North_grant_S => N_err_North_grant_S, N_err_East_Req_L => N_err_East_Req_L, N_err_East_grant_L => N_err_East_grant_L, N_err_West_Req_N => N_err_West_Req_N, N_err_West_grant_N => N_err_West_grant_N, N_err_South_Req_E => N_err_South_Req_E, N_err_South_grant_E => N_err_South_grant_E, N_err_Local_Req_W => N_err_Local_Req_W, N_err_Local_grant_W => N_err_Local_grant_W, N_err_IDLE_Req_L => N_err_IDLE_Req_L, N_err_IDLE_grant_L => N_err_IDLE_grant_L, N_err_North_Req_L => N_err_North_Req_L, N_err_North_grant_L => N_err_North_grant_L, N_err_East_Req_N => N_err_East_Req_N, N_err_East_grant_N => N_err_East_grant_N, N_err_West_Req_E => N_err_West_Req_E, N_err_West_grant_E => N_err_West_grant_E, N_err_South_Req_W => N_err_South_Req_W, N_err_South_grant_W => N_err_South_grant_W, N_err_Local_Req_S => N_err_Local_Req_S, N_err_Local_grant_S => N_err_Local_grant_S, N_err_state_in_onehot => N_err_arbiter_state_in_onehot, N_err_no_request_grants => N_err_no_request_grants, N_err_request_no_grants => N_err_request_no_grants, N_err_no_Req_N_grant_N => N_err_no_Req_N_grant_N, N_err_no_Req_E_grant_E => N_err_no_Req_E_grant_E, N_err_no_Req_W_grant_W => N_err_no_Req_W_grant_W, N_err_no_Req_S_grant_S => N_err_no_Req_S_grant_S, N_err_no_Req_L_grant_L => N_err_no_Req_L_grant_L, -- East Arbiter_in Checker outputs E_err_Requests_state_in_state_not_equal => E_err_Requests_state_in_state_not_equal, E_err_IDLE_Req_N => E_err_IDLE_Req_N, E_err_IDLE_grant_N => E_err_IDLE_grant_N, E_err_North_Req_N => E_err_North_Req_N, E_err_North_grant_N => E_err_North_grant_N, E_err_East_Req_E => E_err_East_Req_E, E_err_East_grant_E => E_err_East_grant_E, E_err_West_Req_W => E_err_West_Req_W, E_err_West_grant_W => E_err_West_grant_W, E_err_South_Req_S => E_err_South_Req_S, E_err_South_grant_S => E_err_South_grant_S, E_err_Local_Req_L => E_err_Local_Req_L, E_err_Local_grant_L => E_err_Local_grant_L, E_err_IDLE_Req_E => E_err_IDLE_Req_E, E_err_IDLE_grant_E => E_err_IDLE_grant_E, E_err_North_Req_E => E_err_North_Req_E, E_err_North_grant_E => E_err_North_grant_E, E_err_East_Req_W => E_err_East_Req_W, E_err_East_grant_W => E_err_East_grant_W, E_err_West_Req_S => E_err_West_Req_S, E_err_West_grant_S => E_err_West_grant_S, E_err_South_Req_L => E_err_South_Req_L, E_err_South_grant_L => E_err_South_grant_L, E_err_Local_Req_N => E_err_Local_Req_N, E_err_Local_grant_N => E_err_Local_grant_N, E_err_IDLE_Req_W => E_err_IDLE_Req_W, E_err_IDLE_grant_W => E_err_IDLE_grant_W, E_err_North_Req_W => E_err_North_Req_W, E_err_North_grant_W => E_err_North_grant_W, E_err_East_Req_S => E_err_East_Req_S, E_err_East_grant_S => E_err_East_grant_S, E_err_West_Req_L => E_err_West_Req_L, E_err_West_grant_L => E_err_West_grant_L, E_err_South_Req_N => E_err_South_Req_N, E_err_South_grant_N => E_err_South_grant_N, E_err_Local_Req_E => E_err_Local_Req_E, E_err_Local_grant_E => E_err_Local_grant_E, E_err_IDLE_Req_S => E_err_IDLE_Req_S, E_err_IDLE_grant_S => E_err_IDLE_grant_S, E_err_North_Req_S => E_err_North_Req_S, E_err_North_grant_S => E_err_North_grant_S, E_err_East_Req_L => E_err_East_Req_L, E_err_East_grant_L => E_err_East_grant_L, E_err_West_Req_N => E_err_West_Req_N, E_err_West_grant_N => E_err_West_grant_N, E_err_South_Req_E => E_err_South_Req_E, E_err_South_grant_E => E_err_South_grant_E, E_err_Local_Req_W => E_err_Local_Req_W, E_err_Local_grant_W => E_err_Local_grant_W, E_err_IDLE_Req_L => E_err_IDLE_Req_L, E_err_IDLE_grant_L => E_err_IDLE_grant_L, E_err_North_Req_L => E_err_North_Req_L, E_err_North_grant_L => E_err_North_grant_L, E_err_East_Req_N => E_err_East_Req_N, E_err_East_grant_N => E_err_East_grant_N, E_err_West_Req_E => E_err_West_Req_E, E_err_West_grant_E => E_err_West_grant_E, E_err_South_Req_W => E_err_South_Req_W, E_err_South_grant_W => E_err_South_grant_W, E_err_Local_Req_S => E_err_Local_Req_S, E_err_Local_grant_S => E_err_Local_grant_S, E_err_state_in_onehot => E_err_arbiter_state_in_onehot, E_err_no_request_grants => E_err_no_request_grants, E_err_request_no_grants => E_err_request_no_grants, E_err_no_Req_N_grant_N => E_err_no_Req_N_grant_N, E_err_no_Req_E_grant_E => E_err_no_Req_E_grant_E, E_err_no_Req_W_grant_W => E_err_no_Req_W_grant_W, E_err_no_Req_S_grant_S => E_err_no_Req_S_grant_S, E_err_no_Req_L_grant_L => E_err_no_Req_L_grant_L, -- West Arbiter_in Checker outputs W_err_Requests_state_in_state_not_equal => W_err_Requests_state_in_state_not_equal, W_err_IDLE_Req_N => W_err_IDLE_Req_N, W_err_IDLE_grant_N => W_err_IDLE_grant_N, W_err_North_Req_N => W_err_North_Req_N, W_err_North_grant_N => W_err_North_grant_N, W_err_East_Req_E => W_err_East_Req_E, W_err_East_grant_E => W_err_East_grant_E, W_err_West_Req_W => W_err_West_Req_W, W_err_West_grant_W => W_err_West_grant_W, W_err_South_Req_S => W_err_South_Req_S, W_err_South_grant_S => W_err_South_grant_S, W_err_Local_Req_L => W_err_Local_Req_L, W_err_Local_grant_L => W_err_Local_grant_L, W_err_IDLE_Req_E => W_err_IDLE_Req_E, W_err_IDLE_grant_E => W_err_IDLE_grant_E, W_err_North_Req_E => W_err_North_Req_E, W_err_North_grant_E => W_err_North_grant_E, W_err_East_Req_W => W_err_East_Req_W, W_err_East_grant_W => W_err_East_grant_W, W_err_West_Req_S => W_err_West_Req_S, W_err_West_grant_S => W_err_West_grant_S, W_err_South_Req_L => W_err_South_Req_L, W_err_South_grant_L => W_err_South_grant_L, W_err_Local_Req_N => W_err_Local_Req_N, W_err_Local_grant_N => W_err_Local_grant_N, W_err_IDLE_Req_W => W_err_IDLE_Req_W, W_err_IDLE_grant_W => W_err_IDLE_grant_W, W_err_North_Req_W => W_err_North_Req_W, W_err_North_grant_W => W_err_North_grant_W, W_err_East_Req_S => W_err_East_Req_S, W_err_East_grant_S => W_err_East_grant_S, W_err_West_Req_L => W_err_West_Req_L, W_err_West_grant_L => W_err_West_grant_L, W_err_South_Req_N => W_err_South_Req_N, W_err_South_grant_N => W_err_South_grant_N, W_err_Local_Req_E => W_err_Local_Req_E, W_err_Local_grant_E => W_err_Local_grant_E, W_err_IDLE_Req_S => W_err_IDLE_Req_S, W_err_IDLE_grant_S => W_err_IDLE_grant_S, W_err_North_Req_S => W_err_North_Req_S, W_err_North_grant_S => W_err_North_grant_S, W_err_East_Req_L => W_err_East_Req_L, W_err_East_grant_L => W_err_East_grant_L, W_err_West_Req_N => W_err_West_Req_N, W_err_West_grant_N => W_err_West_grant_N, W_err_South_Req_E => W_err_South_Req_E, W_err_South_grant_E => W_err_South_grant_E, W_err_Local_Req_W => W_err_Local_Req_W, W_err_Local_grant_W => W_err_Local_grant_W, W_err_IDLE_Req_L => W_err_IDLE_Req_L, W_err_IDLE_grant_L => W_err_IDLE_grant_L, W_err_North_Req_L => W_err_North_Req_L, W_err_North_grant_L => W_err_North_grant_L, W_err_East_Req_N => W_err_East_Req_N, W_err_East_grant_N => W_err_East_grant_N, W_err_West_Req_E => W_err_West_Req_E, W_err_West_grant_E => W_err_West_grant_E, W_err_South_Req_W => W_err_South_Req_W, W_err_South_grant_W => W_err_South_grant_W, W_err_Local_Req_S => W_err_Local_Req_S, W_err_Local_grant_S => W_err_Local_grant_S, W_err_state_in_onehot => W_err_arbiter_state_in_onehot, W_err_no_request_grants => W_err_no_request_grants, W_err_request_no_grants => W_err_request_no_grants, W_err_no_Req_N_grant_N => W_err_no_Req_N_grant_N, W_err_no_Req_E_grant_E => W_err_no_Req_E_grant_E, W_err_no_Req_W_grant_W => W_err_no_Req_W_grant_W, W_err_no_Req_S_grant_S => W_err_no_Req_S_grant_S, W_err_no_Req_L_grant_L => W_err_no_Req_L_grant_L, -- South Arbiter_in Checker outputs S_err_Requests_state_in_state_not_equal => S_err_Requests_state_in_state_not_equal, S_err_IDLE_Req_N => S_err_IDLE_Req_N, S_err_IDLE_grant_N => S_err_IDLE_grant_N, S_err_North_Req_N => S_err_North_Req_N, S_err_North_grant_N => S_err_North_grant_N, S_err_East_Req_E => S_err_East_Req_E, S_err_East_grant_E => S_err_East_grant_E, S_err_West_Req_W => S_err_West_Req_W, S_err_West_grant_W => S_err_West_grant_W, S_err_South_Req_S => S_err_South_Req_S, S_err_South_grant_S => S_err_South_grant_S, S_err_Local_Req_L => S_err_Local_Req_L, S_err_Local_grant_L => S_err_Local_grant_L, S_err_IDLE_Req_E => S_err_IDLE_Req_E, S_err_IDLE_grant_E => S_err_IDLE_grant_E, S_err_North_Req_E => S_err_North_Req_E, S_err_North_grant_E => S_err_North_grant_E, S_err_East_Req_W => S_err_East_Req_W, S_err_East_grant_W => S_err_East_grant_W, S_err_West_Req_S => S_err_West_Req_S, S_err_West_grant_S => S_err_West_grant_S, S_err_South_Req_L => S_err_South_Req_L, S_err_South_grant_L => S_err_South_grant_L, S_err_Local_Req_N => S_err_Local_Req_N, S_err_Local_grant_N => S_err_Local_grant_N, S_err_IDLE_Req_W => S_err_IDLE_Req_W, S_err_IDLE_grant_W => S_err_IDLE_grant_W, S_err_North_Req_W => S_err_North_Req_W, S_err_North_grant_W => S_err_North_grant_W, S_err_East_Req_S => S_err_East_Req_S, S_err_East_grant_S => S_err_East_grant_S, S_err_West_Req_L => S_err_West_Req_L, S_err_West_grant_L => S_err_West_grant_L, S_err_South_Req_N => S_err_South_Req_N, S_err_South_grant_N => S_err_South_grant_N, S_err_Local_Req_E => S_err_Local_Req_E, S_err_Local_grant_E => S_err_Local_grant_E, S_err_IDLE_Req_S => S_err_IDLE_Req_S, S_err_IDLE_grant_S => S_err_IDLE_grant_S, S_err_North_Req_S => S_err_North_Req_S, S_err_North_grant_S => S_err_North_grant_S, S_err_East_Req_L => S_err_East_Req_L, S_err_East_grant_L => S_err_East_grant_L, S_err_West_Req_N => S_err_West_Req_N, S_err_West_grant_N => S_err_West_grant_N, S_err_South_Req_E => S_err_South_Req_E, S_err_South_grant_E => S_err_South_grant_E, S_err_Local_Req_W => S_err_Local_Req_W, S_err_Local_grant_W => S_err_Local_grant_W, S_err_IDLE_Req_L => S_err_IDLE_Req_L, S_err_IDLE_grant_L => S_err_IDLE_grant_L, S_err_North_Req_L => S_err_North_Req_L, S_err_North_grant_L => S_err_North_grant_L, S_err_East_Req_N => S_err_East_Req_N, S_err_East_grant_N => S_err_East_grant_N, S_err_West_Req_E => S_err_West_Req_E, S_err_West_grant_E => S_err_West_grant_E, S_err_South_Req_W => S_err_South_Req_W, S_err_South_grant_W => S_err_South_grant_W, S_err_Local_Req_S => S_err_Local_Req_S, S_err_Local_grant_S => S_err_Local_grant_S, S_err_state_in_onehot => S_err_arbiter_state_in_onehot, S_err_no_request_grants => S_err_no_request_grants, S_err_request_no_grants => S_err_request_no_grants, S_err_no_Req_N_grant_N => S_err_no_Req_N_grant_N, S_err_no_Req_E_grant_E => S_err_no_Req_E_grant_E, S_err_no_Req_W_grant_W => S_err_no_Req_W_grant_W, S_err_no_Req_S_grant_S => S_err_no_Req_S_grant_S, S_err_no_Req_L_grant_L => S_err_no_Req_L_grant_L, -- Local Arbiter_in Checker outputs L_err_Requests_state_in_state_not_equal => L_err_Requests_state_in_state_not_equal, L_err_IDLE_Req_N => L_err_IDLE_Req_N, L_err_IDLE_grant_N => L_err_IDLE_grant_N, L_err_North_Req_N => L_err_North_Req_N, L_err_North_grant_N => L_err_North_grant_N, L_err_East_Req_E => L_err_East_Req_E, L_err_East_grant_E => L_err_East_grant_E, L_err_West_Req_W => L_err_West_Req_W, L_err_West_grant_W => L_err_West_grant_W, L_err_South_Req_S => L_err_South_Req_S, L_err_South_grant_S => L_err_South_grant_S, L_err_Local_Req_L => L_err_Local_Req_L, L_err_Local_grant_L => L_err_Local_grant_L, L_err_IDLE_Req_E => L_err_IDLE_Req_E, L_err_IDLE_grant_E => L_err_IDLE_grant_E, L_err_North_Req_E => L_err_North_Req_E, L_err_North_grant_E => L_err_North_grant_E, L_err_East_Req_W => L_err_East_Req_W, L_err_East_grant_W => L_err_East_grant_W, L_err_West_Req_S => L_err_West_Req_S, L_err_West_grant_S => L_err_West_grant_S, L_err_South_Req_L => L_err_South_Req_L, L_err_South_grant_L => L_err_South_grant_L, L_err_Local_Req_N => L_err_Local_Req_N, L_err_Local_grant_N => L_err_Local_grant_N, L_err_IDLE_Req_W => L_err_IDLE_Req_W, L_err_IDLE_grant_W => L_err_IDLE_grant_W, L_err_North_Req_W => L_err_North_Req_W, L_err_North_grant_W => L_err_North_grant_W, L_err_East_Req_S => L_err_East_Req_S, L_err_East_grant_S => L_err_East_grant_S, L_err_West_Req_L => L_err_West_Req_L, L_err_West_grant_L => L_err_West_grant_L, L_err_South_Req_N => L_err_South_Req_N, L_err_South_grant_N => L_err_South_grant_N, L_err_Local_Req_E => L_err_Local_Req_E, L_err_Local_grant_E => L_err_Local_grant_E, L_err_IDLE_Req_S => L_err_IDLE_Req_S, L_err_IDLE_grant_S => L_err_IDLE_grant_S, L_err_North_Req_S => L_err_North_Req_S, L_err_North_grant_S => L_err_North_grant_S, L_err_East_Req_L => L_err_East_Req_L, L_err_East_grant_L => L_err_East_grant_L, L_err_West_Req_N => L_err_West_Req_N, L_err_West_grant_N => L_err_West_grant_N, L_err_South_Req_E => L_err_South_Req_E, L_err_South_grant_E => L_err_South_grant_E, L_err_Local_Req_W => L_err_Local_Req_W, L_err_Local_grant_W => L_err_Local_grant_W, L_err_IDLE_Req_L => L_err_IDLE_Req_L, L_err_IDLE_grant_L => L_err_IDLE_grant_L, L_err_North_Req_L => L_err_North_Req_L, L_err_North_grant_L => L_err_North_grant_L, L_err_East_Req_N => L_err_East_Req_N, L_err_East_grant_N => L_err_East_grant_N, L_err_West_Req_E => L_err_West_Req_E, L_err_West_grant_E => L_err_West_grant_E, L_err_South_Req_W => L_err_South_Req_W, L_err_South_grant_W => L_err_South_grant_W, L_err_Local_Req_S => L_err_Local_Req_S, L_err_Local_grant_S => L_err_Local_grant_S, L_err_state_in_onehot => L_err_arbiter_state_in_onehot, L_err_no_request_grants => L_err_no_request_grants, L_err_request_no_grants => L_err_request_no_grants, L_err_no_Req_N_grant_N => L_err_no_Req_N_grant_N, L_err_no_Req_E_grant_E => L_err_no_Req_E_grant_E, L_err_no_Req_W_grant_W => L_err_no_Req_W_grant_W, L_err_no_Req_S_grant_S => L_err_no_Req_S_grant_S, L_err_no_Req_L_grant_L => L_err_no_Req_L_grant_L, -- Arbiter_out checker outputs -- North Arbiter_out checker outputs N_arbiter_out_err_Requests_state_in_state_not_equal => N_arbiter_out_err_Requests_state_in_state_not_equal, N_err_IDLE_req_X_N => N_err_IDLE_req_X_N, N_err_North_req_X_N => N_err_North_req_X_N, N_err_North_credit_not_zero_req_X_N_grant_N => N_err_North_credit_not_zero_req_X_N_grant_N, N_err_North_credit_zero_or_not_req_X_N_not_grant_N => N_err_North_credit_zero_or_not_req_X_N_not_grant_N, N_err_East_req_X_E => N_err_East_req_X_E, N_err_East_credit_not_zero_req_X_E_grant_E => N_err_East_credit_not_zero_req_X_E_grant_E, N_err_East_credit_zero_or_not_req_X_E_not_grant_E => N_err_East_credit_zero_or_not_req_X_E_not_grant_E, N_err_West_req_X_W => N_err_West_req_X_W, N_err_West_credit_not_zero_req_X_W_grant_W => N_err_West_credit_not_zero_req_X_W_grant_W, N_err_West_credit_zero_or_not_req_X_W_not_grant_W => N_err_West_credit_zero_or_not_req_X_W_not_grant_W, N_err_South_req_X_S => N_err_South_req_X_S, N_err_South_credit_not_zero_req_X_S_grant_S => N_err_South_credit_not_zero_req_X_S_grant_S, N_err_South_credit_zero_or_not_req_X_S_not_grant_S => N_err_South_credit_zero_or_not_req_X_S_not_grant_S, N_err_Local_req_X_L => N_err_Local_req_X_L, N_err_Local_credit_not_zero_req_X_L_grant_L => N_err_Local_credit_not_zero_req_X_L_grant_L, N_err_Local_credit_zero_or_not_req_X_L_not_grant_L => N_err_Local_credit_zero_or_not_req_X_L_not_grant_L, N_err_IDLE_req_X_E => N_err_IDLE_req_X_E, N_err_North_req_X_E => N_err_North_req_X_E, N_err_East_req_X_W => N_err_East_req_X_W, N_err_West_req_X_S => N_err_West_req_X_S, N_err_South_req_X_L => N_err_South_req_X_L, N_err_Local_req_X_N => N_err_Local_req_X_N, N_err_IDLE_req_X_W => N_err_IDLE_req_X_W, N_err_North_req_X_W => N_err_North_req_X_W, N_err_East_req_X_S => N_err_East_req_X_S, N_err_West_req_X_L => N_err_West_req_X_L, N_err_South_req_X_N => N_err_South_req_X_N, N_err_Local_req_X_E => N_err_Local_req_X_E, N_err_IDLE_req_X_S => N_err_IDLE_req_X_S, N_err_North_req_X_S => N_err_North_req_X_S, N_err_East_req_X_L => N_err_East_req_X_L, N_err_West_req_X_N => N_err_West_req_X_N, N_err_South_req_X_E => N_err_South_req_X_E, N_err_Local_req_X_W => N_err_Local_req_X_W, N_err_IDLE_req_X_L => N_err_IDLE_req_X_L, N_err_North_req_X_L => N_err_North_req_X_L, N_err_East_req_X_N => N_err_East_req_X_N, N_err_West_req_X_E => N_err_West_req_X_E, N_err_South_req_X_W => N_err_South_req_X_W, N_err_Local_req_X_S => N_err_Local_req_X_S, N_arbiter_out_err_state_in_onehot => N_arbiter_out_err_state_in_onehot, N_arbiter_out_err_no_request_grants => N_arbiter_out_err_no_request_grants, N_err_request_IDLE_state => N_err_request_IDLE_state, N_err_request_IDLE_not_Grants => N_err_request_IDLE_not_Grants, N_err_state_North_Invalid_Grant => N_err_state_North_Invalid_Grant, N_err_state_East_Invalid_Grant => N_err_state_East_Invalid_Grant, N_err_state_West_Invalid_Grant => N_err_state_West_Invalid_Grant, N_err_state_South_Invalid_Grant => N_err_state_South_Invalid_Grant, N_err_state_Local_Invalid_Grant => N_err_state_Local_Invalid_Grant, N_err_Grants_onehot_or_all_zero => N_err_Grants_onehot_or_all_zero, -- East Arbiter_out checker outputs E_arbiter_out_err_Requests_state_in_state_not_equal => E_arbiter_out_err_Requests_state_in_state_not_equal, E_err_IDLE_req_X_N => E_err_IDLE_req_X_N, E_err_North_req_X_N => E_err_North_req_X_N, E_err_North_credit_not_zero_req_X_N_grant_N => E_err_North_credit_not_zero_req_X_N_grant_N, E_err_North_credit_zero_or_not_req_X_N_not_grant_N => E_err_North_credit_zero_or_not_req_X_N_not_grant_N, E_err_East_req_X_E => E_err_East_req_X_E, E_err_East_credit_not_zero_req_X_E_grant_E => E_err_East_credit_not_zero_req_X_E_grant_E, E_err_East_credit_zero_or_not_req_X_E_not_grant_E => E_err_East_credit_zero_or_not_req_X_E_not_grant_E, E_err_West_req_X_W => E_err_West_req_X_W, E_err_West_credit_not_zero_req_X_W_grant_W => E_err_West_credit_not_zero_req_X_W_grant_W, E_err_West_credit_zero_or_not_req_X_W_not_grant_W => E_err_West_credit_zero_or_not_req_X_W_not_grant_W, E_err_South_req_X_S => E_err_South_req_X_S, E_err_South_credit_not_zero_req_X_S_grant_S => E_err_South_credit_not_zero_req_X_S_grant_S, E_err_South_credit_zero_or_not_req_X_S_not_grant_S => E_err_South_credit_zero_or_not_req_X_S_not_grant_S, E_err_Local_req_X_L => E_err_Local_req_X_L, E_err_Local_credit_not_zero_req_X_L_grant_L => E_err_Local_credit_not_zero_req_X_L_grant_L, E_err_Local_credit_zero_or_not_req_X_L_not_grant_L => E_err_Local_credit_zero_or_not_req_X_L_not_grant_L, E_err_IDLE_req_X_E => E_err_IDLE_req_X_E, E_err_North_req_X_E => E_err_North_req_X_E, E_err_East_req_X_W => E_err_East_req_X_W, E_err_West_req_X_S => E_err_West_req_X_S, E_err_South_req_X_L => E_err_South_req_X_L, E_err_Local_req_X_N => E_err_Local_req_X_N, E_err_IDLE_req_X_W => E_err_IDLE_req_X_W, E_err_North_req_X_W => E_err_North_req_X_W, E_err_East_req_X_S => E_err_East_req_X_S, E_err_West_req_X_L => E_err_West_req_X_L, E_err_South_req_X_N => E_err_South_req_X_N, E_err_Local_req_X_E => E_err_Local_req_X_E, E_err_IDLE_req_X_S => E_err_IDLE_req_X_S, E_err_North_req_X_S => E_err_North_req_X_S, E_err_East_req_X_L => E_err_East_req_X_L, E_err_West_req_X_N => E_err_West_req_X_N, E_err_South_req_X_E => E_err_South_req_X_E, E_err_Local_req_X_W => E_err_Local_req_X_W, E_err_IDLE_req_X_L => E_err_IDLE_req_X_L, E_err_North_req_X_L => E_err_North_req_X_L, E_err_East_req_X_N => E_err_East_req_X_N, E_err_West_req_X_E => E_err_West_req_X_E, E_err_South_req_X_W => E_err_South_req_X_W, E_err_Local_req_X_S => E_err_Local_req_X_S, E_arbiter_out_err_state_in_onehot => E_arbiter_out_err_state_in_onehot, E_arbiter_out_err_no_request_grants => E_arbiter_out_err_no_request_grants, E_err_request_IDLE_state => E_err_request_IDLE_state, E_err_request_IDLE_not_Grants => E_err_request_IDLE_not_Grants, E_err_state_North_Invalid_Grant => E_err_state_North_Invalid_Grant, E_err_state_East_Invalid_Grant => E_err_state_East_Invalid_Grant, E_err_state_West_Invalid_Grant => E_err_state_West_Invalid_Grant, E_err_state_South_Invalid_Grant => E_err_state_South_Invalid_Grant, E_err_state_Local_Invalid_Grant => E_err_state_Local_Invalid_Grant, E_err_Grants_onehot_or_all_zero => E_err_Grants_onehot_or_all_zero, -- West Arbiter_out checker outputs W_arbiter_out_err_Requests_state_in_state_not_equal => W_arbiter_out_err_Requests_state_in_state_not_equal, W_err_IDLE_req_X_N => W_err_IDLE_req_X_N, W_err_North_req_X_N => W_err_North_req_X_N, W_err_North_credit_not_zero_req_X_N_grant_N => W_err_North_credit_not_zero_req_X_N_grant_N, W_err_North_credit_zero_or_not_req_X_N_not_grant_N => W_err_North_credit_zero_or_not_req_X_N_not_grant_N, W_err_East_req_X_E => W_err_East_req_X_E, W_err_East_credit_not_zero_req_X_E_grant_E => W_err_East_credit_not_zero_req_X_E_grant_E, W_err_East_credit_zero_or_not_req_X_E_not_grant_E => W_err_East_credit_zero_or_not_req_X_E_not_grant_E, W_err_West_req_X_W => W_err_West_req_X_W, W_err_West_credit_not_zero_req_X_W_grant_W => W_err_West_credit_not_zero_req_X_W_grant_W, W_err_West_credit_zero_or_not_req_X_W_not_grant_W => W_err_West_credit_zero_or_not_req_X_W_not_grant_W, W_err_South_req_X_S => W_err_South_req_X_S, W_err_South_credit_not_zero_req_X_S_grant_S => W_err_South_credit_not_zero_req_X_S_grant_S, W_err_South_credit_zero_or_not_req_X_S_not_grant_S => W_err_South_credit_zero_or_not_req_X_S_not_grant_S, W_err_Local_req_X_L => W_err_Local_req_X_L, W_err_Local_credit_not_zero_req_X_L_grant_L => W_err_Local_credit_not_zero_req_X_L_grant_L, W_err_Local_credit_zero_or_not_req_X_L_not_grant_L => W_err_Local_credit_zero_or_not_req_X_L_not_grant_L, W_err_IDLE_req_X_E => W_err_IDLE_req_X_E, W_err_North_req_X_E => W_err_North_req_X_E, W_err_East_req_X_W => W_err_East_req_X_W, W_err_West_req_X_S => W_err_West_req_X_S, W_err_South_req_X_L => W_err_South_req_X_L, W_err_Local_req_X_N => W_err_Local_req_X_N, W_err_IDLE_req_X_W => W_err_IDLE_req_X_W, W_err_North_req_X_W => W_err_North_req_X_W, W_err_East_req_X_S => W_err_East_req_X_S, W_err_West_req_X_L => W_err_West_req_X_L, W_err_South_req_X_N => W_err_South_req_X_N, W_err_Local_req_X_E => W_err_Local_req_X_E, W_err_IDLE_req_X_S => W_err_IDLE_req_X_S, W_err_North_req_X_S => W_err_North_req_X_S, W_err_East_req_X_L => W_err_East_req_X_L, W_err_West_req_X_N => W_err_West_req_X_N, W_err_South_req_X_E => W_err_South_req_X_E, W_err_Local_req_X_W => W_err_Local_req_X_W, W_err_IDLE_req_X_L => W_err_IDLE_req_X_L, W_err_North_req_X_L => W_err_North_req_X_L, W_err_East_req_X_N => W_err_East_req_X_N, W_err_West_req_X_E => W_err_West_req_X_E, W_err_South_req_X_W => W_err_South_req_X_W, W_err_Local_req_X_S => W_err_Local_req_X_S, W_arbiter_out_err_state_in_onehot => W_arbiter_out_err_state_in_onehot, W_arbiter_out_err_no_request_grants => W_arbiter_out_err_no_request_grants, W_err_request_IDLE_state => W_err_request_IDLE_state, W_err_request_IDLE_not_Grants => W_err_request_IDLE_not_Grants, W_err_state_North_Invalid_Grant => W_err_state_North_Invalid_Grant, W_err_state_East_Invalid_Grant => W_err_state_East_Invalid_Grant, W_err_state_West_Invalid_Grant => W_err_state_West_Invalid_Grant, W_err_state_South_Invalid_Grant => W_err_state_South_Invalid_Grant, W_err_state_Local_Invalid_Grant => W_err_state_Local_Invalid_Grant, W_err_Grants_onehot_or_all_zero => W_err_Grants_onehot_or_all_zero, -- South Arbiter_out checker outputs S_arbiter_out_err_Requests_state_in_state_not_equal => S_arbiter_out_err_Requests_state_in_state_not_equal, S_err_IDLE_req_X_N => S_err_IDLE_req_X_N, S_err_North_req_X_N => S_err_North_req_X_N, S_err_North_credit_not_zero_req_X_N_grant_N => S_err_North_credit_not_zero_req_X_N_grant_N, S_err_North_credit_zero_or_not_req_X_N_not_grant_N => S_err_North_credit_zero_or_not_req_X_N_not_grant_N, S_err_East_req_X_E => S_err_East_req_X_E, S_err_East_credit_not_zero_req_X_E_grant_E => S_err_East_credit_not_zero_req_X_E_grant_E, S_err_East_credit_zero_or_not_req_X_E_not_grant_E => S_err_East_credit_zero_or_not_req_X_E_not_grant_E, S_err_West_req_X_W => S_err_West_req_X_W, S_err_West_credit_not_zero_req_X_W_grant_W => S_err_West_credit_not_zero_req_X_W_grant_W, S_err_West_credit_zero_or_not_req_X_W_not_grant_W => S_err_West_credit_zero_or_not_req_X_W_not_grant_W, S_err_South_req_X_S => S_err_South_req_X_S, S_err_South_credit_not_zero_req_X_S_grant_S => S_err_South_credit_not_zero_req_X_S_grant_S, S_err_South_credit_zero_or_not_req_X_S_not_grant_S => S_err_South_credit_zero_or_not_req_X_S_not_grant_S, S_err_Local_req_X_L => S_err_Local_req_X_L, S_err_Local_credit_not_zero_req_X_L_grant_L => S_err_Local_credit_not_zero_req_X_L_grant_L, S_err_Local_credit_zero_or_not_req_X_L_not_grant_L => S_err_Local_credit_zero_or_not_req_X_L_not_grant_L, S_err_IDLE_req_X_E => S_err_IDLE_req_X_E, S_err_North_req_X_E => S_err_North_req_X_E, S_err_East_req_X_W => S_err_East_req_X_W, S_err_West_req_X_S => S_err_West_req_X_S, S_err_South_req_X_L => S_err_South_req_X_L, S_err_Local_req_X_N => S_err_Local_req_X_N, S_err_IDLE_req_X_W => S_err_IDLE_req_X_W, S_err_North_req_X_W => S_err_North_req_X_W, S_err_East_req_X_S => S_err_East_req_X_S, S_err_West_req_X_L => S_err_West_req_X_L, S_err_South_req_X_N => S_err_South_req_X_N, S_err_Local_req_X_E => S_err_Local_req_X_E, S_err_IDLE_req_X_S => S_err_IDLE_req_X_S, S_err_North_req_X_S => S_err_North_req_X_S, S_err_East_req_X_L => S_err_East_req_X_L, S_err_West_req_X_N => S_err_West_req_X_N, S_err_South_req_X_E => S_err_South_req_X_E, S_err_Local_req_X_W => S_err_Local_req_X_W, S_err_IDLE_req_X_L => S_err_IDLE_req_X_L, S_err_North_req_X_L => S_err_North_req_X_L, S_err_East_req_X_N => S_err_East_req_X_N, S_err_West_req_X_E => S_err_West_req_X_E, S_err_South_req_X_W => S_err_South_req_X_W, S_err_Local_req_X_S => S_err_Local_req_X_S, S_arbiter_out_err_state_in_onehot => S_arbiter_out_err_state_in_onehot, S_arbiter_out_err_no_request_grants => S_arbiter_out_err_no_request_grants, S_err_request_IDLE_state => S_err_request_IDLE_state, S_err_request_IDLE_not_Grants => S_err_request_IDLE_not_Grants, S_err_state_North_Invalid_Grant => S_err_state_North_Invalid_Grant, S_err_state_East_Invalid_Grant => S_err_state_East_Invalid_Grant, S_err_state_West_Invalid_Grant => S_err_state_West_Invalid_Grant, S_err_state_South_Invalid_Grant => S_err_state_South_Invalid_Grant, S_err_state_Local_Invalid_Grant => S_err_state_Local_Invalid_Grant, S_err_Grants_onehot_or_all_zero => S_err_Grants_onehot_or_all_zero, -- Local Arbiter_out checker outputs L_arbiter_out_err_Requests_state_in_state_not_equal => L_arbiter_out_err_Requests_state_in_state_not_equal, L_err_IDLE_req_X_N => L_err_IDLE_req_X_N, L_err_North_req_X_N => L_err_North_req_X_N, L_err_North_credit_not_zero_req_X_N_grant_N => L_err_North_credit_not_zero_req_X_N_grant_N, L_err_North_credit_zero_or_not_req_X_N_not_grant_N => L_err_North_credit_zero_or_not_req_X_N_not_grant_N, L_err_East_req_X_E => L_err_East_req_X_E, L_err_East_credit_not_zero_req_X_E_grant_E => L_err_East_credit_not_zero_req_X_E_grant_E, L_err_East_credit_zero_or_not_req_X_E_not_grant_E => L_err_East_credit_zero_or_not_req_X_E_not_grant_E, L_err_West_req_X_W => L_err_West_req_X_W, L_err_West_credit_not_zero_req_X_W_grant_W => L_err_West_credit_not_zero_req_X_W_grant_W, L_err_West_credit_zero_or_not_req_X_W_not_grant_W => L_err_West_credit_zero_or_not_req_X_W_not_grant_W, L_err_South_req_X_S => L_err_South_req_X_S, L_err_South_credit_not_zero_req_X_S_grant_S => L_err_South_credit_not_zero_req_X_S_grant_S, L_err_South_credit_zero_or_not_req_X_S_not_grant_S => L_err_South_credit_zero_or_not_req_X_S_not_grant_S, L_err_Local_req_X_L => L_err_Local_req_X_L, L_err_Local_credit_not_zero_req_X_L_grant_L => L_err_Local_credit_not_zero_req_X_L_grant_L, L_err_Local_credit_zero_or_not_req_X_L_not_grant_L => L_err_Local_credit_zero_or_not_req_X_L_not_grant_L, L_err_IDLE_req_X_E => L_err_IDLE_req_X_E, L_err_North_req_X_E => L_err_North_req_X_E, L_err_East_req_X_W => L_err_East_req_X_W, L_err_West_req_X_S => L_err_West_req_X_S, L_err_South_req_X_L => L_err_South_req_X_L, L_err_Local_req_X_N => L_err_Local_req_X_N, L_err_IDLE_req_X_W => L_err_IDLE_req_X_W, L_err_North_req_X_W => L_err_North_req_X_W, L_err_East_req_X_S => L_err_East_req_X_S, L_err_West_req_X_L => L_err_West_req_X_L, L_err_South_req_X_N => L_err_South_req_X_N, L_err_Local_req_X_E => L_err_Local_req_X_E, L_err_IDLE_req_X_S => L_err_IDLE_req_X_S, L_err_North_req_X_S => L_err_North_req_X_S, L_err_East_req_X_L => L_err_East_req_X_L, L_err_West_req_X_N => L_err_West_req_X_N, L_err_South_req_X_E => L_err_South_req_X_E, L_err_Local_req_X_W => L_err_Local_req_X_W, L_err_IDLE_req_X_L => L_err_IDLE_req_X_L, L_err_North_req_X_L => L_err_North_req_X_L, L_err_East_req_X_N => L_err_East_req_X_N, L_err_West_req_X_E => L_err_West_req_X_E, L_err_South_req_X_W => L_err_South_req_X_W, L_err_Local_req_X_S => L_err_Local_req_X_S, L_arbiter_out_err_state_in_onehot => L_arbiter_out_err_state_in_onehot, L_arbiter_out_err_no_request_grants => L_arbiter_out_err_no_request_grants, L_err_request_IDLE_state => L_err_request_IDLE_state, L_err_request_IDLE_not_Grants => L_err_request_IDLE_not_Grants, L_err_state_North_Invalid_Grant => L_err_state_North_Invalid_Grant, L_err_state_East_Invalid_Grant => L_err_state_East_Invalid_Grant, L_err_state_West_Invalid_Grant => L_err_state_West_Invalid_Grant, L_err_state_South_Invalid_Grant => L_err_state_South_Invalid_Grant, L_err_state_Local_Invalid_Grant => L_err_state_Local_Invalid_Grant, L_err_Grants_onehot_or_all_zero => L_err_Grants_onehot_or_all_zero ); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Xbar select_signals Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL; Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL; Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL; Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL; Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0'; ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ -- all the Xbars -- all the Xbars XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_N, Data_out=> TX_N); XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_E, Data_out=> TX_E); XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_W, Data_out=> TX_W); XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_S, Data_out=> TX_S); XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH) PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L, sel => Xbar_sel_L, Data_out=> TX_L); ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------ end;

--############################### --# Project Name : I2C slave --# File : i2cslave.vhd --# Project : i2c slave for FPGA --# Engineer : Philippe THIRION --# Modification History --############################### library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity I2CSLAVE is generic( DEVICE : std_logic_vector(7 downto 0) := x"38" ); port( MCLK : in std_logic; nRST : in std_logic; SDA_IN : in std_logic; SCL_IN : in std_logic; SDA_OUT : out std_logic; SCL_OUT : out std_logic; ADDRESS : out std_logic_vector(7 downto 0); DATA_OUT : out std_logic_vector(7 downto 0); DATA_IN : in std_logic_vector(7 downto 0); WR : out std_logic; RD : out std_logic; READ_DONE : out std_logic ); end I2CSLAVE; architecture rtl of I2CSLAVE is type tstate is ( S_IDLE, S_START, S_SHIFTIN, S_RW, S_SENDACK, S_SENDACK2, S_SENDNACK, S_ADDRESS, S_WRITE, S_SHIFTOUT, S_READ, S_WAITACK ); type toperation is (OP_READ, OP_WRITE); signal state : tstate; signal next_state : tstate; signal operation : toperation; signal rising_scl, falling_scl : std_logic; signal address_i : std_logic_vector(7 downto 0); signal next_address : std_logic_vector(7 downto 0); signal counter : integer range 0 to 7; signal start_cond : std_logic; signal stop_cond : std_logic; signal sda_q, sda_qq, sda_qqq : std_logic; signal scl_q, scl_qq, scl_qqq : std_logic; signal shiftreg : std_logic_vector(7 downto 0); signal sda: std_logic; signal address_incr : std_logic; signal rd_d : std_logic; signal read_data_done : std_logic; begin ADDRESS <= address_i; next_address <= (others=>'0') when (address_i = x"FF") else std_logic_vector(to_unsigned(to_integer(unsigned( address_i )) + 1, 8)); S_RSY: process(MCLK,nRST) begin if (nRST = '0') then sda_q <= '1'; sda_qq <= '1'; sda_qqq <= '1'; scl_q <= '1'; scl_qq <= '1'; scl_qqq <= '1'; elsif (MCLK'event and MCLK='1') then sda_q <= SDA_IN; sda_qq <= sda_q; sda_qqq <= sda_qq; scl_q <= SCL_IN; scl_qq <= scl_q; scl_qqq <= scl_qq; end if; end process S_RSY; rising_scl <= scl_qq and not scl_qqq; falling_scl <= not scl_qq and scl_qqq; START_BIT: process(MCLK,nRST) begin if (nRST = '0') then start_cond <= '0'; elsif (MCLK'event and MCLK='1') then if (sda_qqq = '1' and sda_qq = '0' and scl_qq = '1') then start_cond <= '1'; else start_cond <= '0'; end if; end if; end process START_BIT; STOP_BIT: process(MCLK,nRST) begin if (nRST = '0') then stop_cond <= '0'; elsif (MCLK'event and MCLK='1') then if (sda_qqq = '0' and sda_qq = '1' and scl_qq = '1') then stop_cond <= '1'; else stop_cond <= '0'; end if; end if; end process STOP_BIT; sda <= sda_qq; RD_DELAY: process(MCLK, nRST) begin if (nRST = '0') then RD <= '0'; elsif (MCLK'event and MCLK='1') then RD <= rd_d; end if; end process RD_DELAY; OTO: process(MCLK, nRST) begin if (nRST = '0') then state <= S_IDLE; SDA_OUT <= '1'; SCL_OUT <= '1'; WR <= '0'; rd_d <= '0'; address_i <= (others=>'0'); DATA_OUT <= (others=>'0'); shiftreg <= (others=>'0'); read_data_done <= '0'; elsif (MCLK'event and MCLK='1') then if (stop_cond = '1') then state <= S_IDLE; SDA_OUT <= '1'; SCL_OUT <= '1'; operation <= OP_READ; WR <= '0'; rd_d <= '0'; address_incr <= '0'; elsif(start_cond = '1') then state <= S_START; SDA_OUT <= '1'; SCL_OUT <= '1'; operation <= OP_READ; WR <= '0'; rd_d <= '0'; address_incr <= '0'; elsif(state = S_IDLE) then state <= S_IDLE; SDA_OUT <= '1'; SCL_OUT <= '1'; operation <= OP_READ; WR <= '0'; rd_d <= '0'; address_incr <= '0'; elsif(state = S_START) then shiftreg <= (others=>'0'); state <= S_SHIFTIN; next_state <= S_RW; counter <= 6; elsif(state = S_SHIFTIN) then if (rising_scl = '1') then shiftreg(7 downto 1) <= shiftreg(6 downto 0); shiftreg(0) <= sda; if (counter = 0) then state <= next_state; counter <= 7; else counter <= counter - 1; end if; end if; elsif(state = S_RW) then if (rising_scl = '1') then if (shiftreg = DEVICE) then state <= S_SENDACK; if (sda = '1') then operation <= OP_READ; -- next_state <= S_READ; -- no needed rd_d <= '1'; else operation <= OP_WRITE; next_state <= S_ADDRESS; address_incr <= '0'; end if; else state <= S_SENDNACK; end if; end if; elsif(state = S_SENDACK) then WR <= '0'; rd_d <= '0'; if (falling_scl = '1') then SDA_OUT <= '0'; counter <= 7; if (operation= OP_WRITE) then state <= S_SENDACK2; else -- OP_READ state <= S_SHIFTOUT; shiftreg <= DATA_IN; read_data_done <= '1'; end if; end if; elsif(state = S_SENDACK2) then if (falling_scl = '1') then SDA_OUT <= '1'; state <= S_SHIFTIN; shiftreg <= (others=>'0'); if (address_incr = '1') then address_i <= next_address; end if; end if; elsif(state = S_SENDNACK) then if (falling_scl = '1') then SDA_OUT <= '1'; state <= S_IDLE; end if; elsif(state = S_ADDRESS) then address_i <= shiftreg; next_state <= S_WRITE; state <= S_SENDACK; address_incr <= '0'; elsif(state = S_WRITE) then DATA_OUT <= shiftreg; next_state <= S_WRITE; state <= S_SENDACK; WR <= '1'; address_incr <= '1'; elsif(state = S_SHIFTOUT) then read_data_done <= '0'; if (falling_scl = '1') then SDA_OUT <= shiftreg(7); shiftreg(7 downto 1) <= shiftreg(6 downto 0); shiftreg(0) <= '1'; if (counter = 0) then state <= S_READ; address_i <= next_address; rd_d <= '1'; else counter <= counter - 1; end if; end if; elsif(state = S_READ) then rd_d <= '0'; if (falling_scl = '1') then SDA_OUT <= '1'; state <= S_WAITACK; end if; elsif(state = S_WAITACK) then if (rising_scl = '1') then if (sda = '0') then state <= S_SHIFTOUT; counter <= 7; shiftreg <= DATA_IN; read_data_done <= '1'; else state <= S_IDLE; end if; end if; end if; end if; end process OTO; READ_DONE <= read_data_done; end rtl;

------------------------------------------------------------------------------------------------- -- Company : CNES -- Author : Mickael Carl (CNES) -- Copyright : Copyright (c) CNES. -- Licensing : GNU GPLv3 ------------------------------------------------------------------------------------------------- -- Version : V1 -- Version history : -- V1 : 2015-04-08 : Mickael Carl (CNES): Creation ------------------------------------------------------------------------------------------------- -- File name : STD_03700_good.vhd -- File Creation date : 2015-04-08 -- Project name : VHDL Handbook CNES Edition ------------------------------------------------------------------------------------------------- -- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor) ------------------------------------------------------------------------------------------------- -- Description : Handbook example: Reset assertion and deassertion: good example -- -- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at -- demonstrating good practices in VHDL and as such, its design is minimalistic. -- It is provided as is, without any warranty. -- This example is compliant with the Handbook version 1. -- ------------------------------------------------------------------------------------------------- -- Naming conventions: -- -- i_Port: Input entity port -- o_Port: Output entity port -- b_Port: Bidirectional entity port -- g_My_Generic: Generic entity port -- -- c_My_Constant: Constant definition -- t_My_Type: Custom type definition -- -- My_Signal_n: Active low signal -- v_My_Variable: Variable -- sm_My_Signal: FSM signal -- pkg_Param: Element Param coming from a package -- -- My_Signal_re: Rising edge detection of My_Signal -- My_Signal_fe: Falling edge detection of My_Signal -- My_Signal_rX: X times registered My_Signal signal -- -- P_Process_Name: Process -- ------------------------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; --CODE entity STD_03700_good is port ( i_Clock : in std_logic; -- Clock signal i_Reset_Input_n : in std_logic; -- Reset input o_Main_Reset_n : out std_logic -- Global reset signal active low ); end STD_03700_good; architecture Behavioral of STD_03700_good is signal Main_Reset_n : std_logic; -- Internal signal between FlipFlops signal Main_Reset_n_r : std_logic; -- Assertion block output begin P_Reset_Assert : process(i_Reset_Input_n, i_Clock) begin if (i_Reset_Input_n = '0') then Main_Reset_n <= '0'; -- Output reset signal is active low Main_Reset_n_r <= '0'; elsif rising_edge(i_Clock) then Main_Reset_n <= '1'; -- Reset is deasserted. Since it is active low, the inactive value is 1 Main_Reset_n_r <= Main_Reset_n; end if; end process; o_Main_Reset_n <= Main_Reset_n_r; end Behavioral; --CODE

-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Mon May 29 22:11:05 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode synth_stub -- C:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_xlconstant_0_1/system_xlconstant_0_1_stub.vhdl -- Design : system_xlconstant_0_1 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity system_xlconstant_0_1 is Port ( dout : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); end system_xlconstant_0_1; architecture stub of system_xlconstant_0_1 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "dout[31:0]"; begin end;

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 04.03.2016 11:22:26 -- Design Name: -- Module Name: rem_testbench - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity asl64_testbench is end asl64_testbench; architecture Behavioural of asl64_testbench is signal sig_i00, sig_i01, sig_i02, sig_r00, sig_r01, sig_r02, sig_FP, sig_FPout,sig_MDAT : std_logic_vector(31 DOWNTO 0); signal sig_reset, sig_CLK, sig_MWAIT : std_logic; component ASL64CoreAndMemory is PORT ( in0 : IN std_logic_vector(31 DOWNTO 0); in1 : IN std_logic_vector(31 DOWNTO 0); in2 : IN std_logic_vector(31 DOWNTO 0); out0 : OUT std_logic_vector(31 DOWNTO 0); out1 : OUT std_logic_vector(31 DOWNTO 0); out2 : OUT std_logic_vector(31 DOWNTO 0); frame_pointer : IN std_logic_vector(31 DOWNTO 0); frame_pointer_out : OUT std_logic_vector(31 DOWNTO 0); rst : IN std_logic; clck : IN std_logic; mem_wait : IN std_logic; mem_push : IN std_logic_vector(31 DOWNTO 0) ); end component; begin uut: ASL64CoreAndMemory port map ( in0 => sig_i00, in1 => sig_i01, in2 => sig_i02, out0 => sig_r00, out1 => sig_r01, out2 => sig_r02, frame_pointer => sig_FP, frame_pointer_out => sig_FPout, rst => sig_reset, clck => sig_CLK, mem_wait => sig_MWAIT, mem_push => sig_MDAT ); clock: process constant clock_period:time := 40ns; begin wait for 200ns; for I in 0 to 100 loop sig_CLK <= '0'; wait for clock_period/2; sig_CLK <= '1'; wait for clock_period/2; end loop; wait; end process clock; test: process begin sig_MWAIT <= '1'; sig_reset <= '1'; wait for 100ns; sig_reset <= '0'; wait for 100ns; sig_i00 <= "00000000000000000000000000100101"; sig_i01 <= "00000000000000000000000000000100"; sig_i02 <= "00000000000000000000000000010011"; sig_MDAT <= "00000000000000000000000000011111"; sig_FP <= "00000000000000000000000001010000"; wait; end process test; end Behavioural;

-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014 -- Date : Fri Nov 2 15:01:50 2018 -- Host : graviton running 64-bit Debian GNU/Linux 7.11 (wheezy) -- Command : write_vhdl -force -mode funcsim -- /home/guest/cae/fpga/ntpserver/sv/ip/ocxo_clk_pll/ocxo_clk_pll_funcsim.vhdl -- Design : ocxo_clk_pll -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ocxo_clk_pll_ocxo_clk_pll_clk_wiz is port ( clk_in1 : in STD_LOGIC; clk_out1 : out STD_LOGIC; resetn : in STD_LOGIC; locked : out STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of ocxo_clk_pll_ocxo_clk_pll_clk_wiz : entity is "ocxo_clk_pll_clk_wiz"; end ocxo_clk_pll_ocxo_clk_pll_clk_wiz; architecture STRUCTURE of ocxo_clk_pll_ocxo_clk_pll_clk_wiz is signal clk_in1_ocxo_clk_pll : STD_LOGIC; signal clkfbout_ocxo_clk_pll : STD_LOGIC; signal reset_high : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE"; attribute CAPACITANCE : string; attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; attribute IBUF_DELAY_VALUE : string; attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; attribute IFD_DELAY_VALUE : string; attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; begin clkin1_ibufg: unisim.vcomponents.IBUF generic map( IOSTANDARD => "DEFAULT" ) port map ( I => clk_in1, O => clk_in1_ocxo_clk_pll ); mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV generic map( BANDWIDTH => "OPTIMIZED", CLKFBOUT_MULT_F => 63.750000, CLKFBOUT_PHASE => 0.000000, CLKFBOUT_USE_FINE_PS => false, CLKIN1_PERIOD => 100.000000, CLKIN2_PERIOD => 0.000000, CLKOUT0_DIVIDE_F => 6.375000, CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT0_USE_FINE_PS => false, CLKOUT1_DIVIDE => 1, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT1_USE_FINE_PS => false, CLKOUT2_DIVIDE => 1, CLKOUT2_DUTY_CYCLE => 0.500000, CLKOUT2_PHASE => 0.000000, CLKOUT2_USE_FINE_PS => false, CLKOUT3_DIVIDE => 1, CLKOUT3_DUTY_CYCLE => 0.500000, CLKOUT3_PHASE => 0.000000, CLKOUT3_USE_FINE_PS => false, CLKOUT4_CASCADE => false, CLKOUT4_DIVIDE => 1, CLKOUT4_DUTY_CYCLE => 0.500000, CLKOUT4_PHASE => 0.000000, CLKOUT4_USE_FINE_PS => false, CLKOUT5_DIVIDE => 1, CLKOUT5_DUTY_CYCLE => 0.500000, CLKOUT5_PHASE => 0.000000, CLKOUT5_USE_FINE_PS => false, CLKOUT6_DIVIDE => 1, CLKOUT6_DUTY_CYCLE => 0.500000, CLKOUT6_PHASE => 0.000000, CLKOUT6_USE_FINE_PS => false, COMPENSATION => "INTERNAL", DIVCLK_DIVIDE => 1, IS_CLKINSEL_INVERTED => '0', IS_PSEN_INVERTED => '0', IS_PSINCDEC_INVERTED => '0', IS_PWRDWN_INVERTED => '0', IS_RST_INVERTED => '0', REF_JITTER1 => 0.010000, REF_JITTER2 => 0.010000, SS_EN => "FALSE", SS_MODE => "CENTER_HIGH", SS_MOD_PERIOD => 10000, STARTUP_WAIT => false ) port map ( CLKFBIN => clkfbout_ocxo_clk_pll, CLKFBOUT => clkfbout_ocxo_clk_pll, CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, CLKIN1 => clk_in1_ocxo_clk_pll, CLKIN2 => '0', CLKINSEL => '1', CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, CLKOUT0 => clk_out1, CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, DADDR(6) => '0', DADDR(5) => '0', DADDR(4) => '0', DADDR(3) => '0', DADDR(2) => '0', DADDR(1) => '0', DADDR(0) => '0', DCLK => '0', DEN => '0', DI(15) => '0', DI(14) => '0', DI(13) => '0', DI(12) => '0', DI(11) => '0', DI(10) => '0', DI(9) => '0', DI(8) => '0', DI(7) => '0', DI(6) => '0', DI(5) => '0', DI(4) => '0', DI(3) => '0', DI(2) => '0', DI(1) => '0', DI(0) => '0', DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, DWE => '0', LOCKED => locked, PSCLK => '0', PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, PSEN => '0', PSINCDEC => '0', PWRDWN => '0', RST => reset_high ); mmcm_adv_inst_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => resetn, O => reset_high ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ocxo_clk_pll is port ( clk_in1 : in STD_LOGIC; clk_out1 : out STD_LOGIC; resetn : in STD_LOGIC; locked : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of ocxo_clk_pll : entity is true; attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of ocxo_clk_pll : entity is "ocxo_clk_pll,clk_wiz_v5_1,{component_name=ocxo_clk_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_ONCHIP,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=100.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; end ocxo_clk_pll; architecture STRUCTURE of ocxo_clk_pll is begin inst: entity work.ocxo_clk_pll_ocxo_clk_pll_clk_wiz port map ( clk_in1 => clk_in1, clk_out1 => clk_out1, locked => locked, resetn => resetn ); end STRUCTURE;

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity biaser_tb is end entity; architecture biaser_tb_arq of biaser_tb is signal operation : std_logic := '0'; signal exp_in: std_logic_vector(2 downto 0) := (others => '0'); signal exp_out: std_logic_vector(2 downto 0) := (others => '0'); component biaser is generic( EXP_BITS: natural := 6 ); port ( operation : in std_logic; exp_in: in std_logic_vector(EXP_BITS - 1 downto 0); exp_out : out std_logic_vector(EXP_BITS - 1 downto 0) ); end component; for biaser_0: biaser use entity work.biaser; begin biaser_0: biaser generic map(EXP_BITS => 3) port map( operation => operation, exp_in => exp_in, exp_out => exp_out ); process type pattern_type is record o : std_logic; ei : std_logic_vector(2 downto 0); eo : std_logic_vector(2 downto 0); end record; -- The patterns to apply. type pattern_array is array (natural range<>) of pattern_type; constant patterns : pattern_array := ( ('1',"000","101"), ('1',"001","110"), ('0',"000","011") ); begin for i in patterns'range loop -- Set the inputs. operation <= patterns(i).o; exp_in <= patterns(i).ei; -- Wait for the results. wait for 1 ns; -- Check the outputs. assert exp_out = patterns(i).eo report "BAD EXPONENT: " & integer'image(to_integer(unsigned(exp_out))) severity error; end loop; assert false report "end of test" severity note; wait; end process; end;

-- Library Declaration library IEEE; use IEEE.std_logic_1164.all; library WORK; use WORK.globals.all; -- Component Declaration entity sbox is port ( b_in : in std_logic_vector (7 downto 0); ctrl_dec : T_ENCDEC; clock, reset : in std_logic; b_out : out std_logic_vector (7 downto 0) ); end sbox; -- Architecture of the Component architecture a_sbox of sbox is component DDR_register is generic( SIZE : integer := 8 ); port( din_hi, din_lo : in std_logic_vector( SIZE-1 downto 0 ); -- dout_hi, dout_lo : out std_logic_vector( SIZE-1 downto 0 ); rst, clk : in std_logic ); end component; component aff_trans port ( a : in std_logic_vector (7 downto 0); b_out : out std_logic_vector (7 downto 0) ); end component; component aff_trans_inv port ( a : in std_logic_vector (7 downto 0); b_out : out std_logic_vector (7 downto 0) ); end component; component gfmap port ( a : in std_logic_vector (7 downto 0); ah, al : out std_logic_vector (3 downto 0)); end component; component quadrato port ( a : in std_logic_vector (3 downto 0); d : out std_logic_vector (3 downto 0)); end component; component x_e is port ( a : in std_logic_vector (3 downto 0); d : out std_logic_vector (3 downto 0) ); end component; component gf_molt is port ( a, b: in std_logic_vector (3 downto 0); d : out std_logic_vector (3 downto 0)); end component; component gf_inv is port ( a_in : std_logic_vector (3 downto 0); d : out std_logic_vector (3 downto 0)); end component; component gfmapinv is port ( ah, al : in std_logic_vector (3 downto 0); a : out std_logic_vector (7 downto 0) ); end component; -- Internal Signal (4 std_logic) signal ah, a1h, al, a1l, o, n, m, l, i, g, f, p, p_hi, p_lo, q, d, d_hi, d_lo, r, r_hi, r_lo : std_logic_vector (3 downto 0); -- Internal Signal (8 bit) signal s, t, v, z : std_logic_vector (7 downto 0); signal s_enc_buffer : T_ENCDEC; begin -- Affine Trasnformation gen000e : if ( not C_INCLUDE_DECODING_LOGIC ) generate v <= b_in; end generate; gen000d : if ( C_INCLUDE_DECODING_LOGIC ) generate ati:aff_trans_inv port map (b_in, s); v <= s when (ctrl_dec = C_DEC) else b_in; end generate; -- Map mp:gfmap port map (v, ah, al); -- First Square qua1:quadrato port map (ah, o); -- Second Square qua2:quadrato port map (al, n); -- X [e] xe:x_e port map (o, m); -- First Moltiplicator molt1:gf_molt port map (ah, al, l); f <= ah xor al; i <= m xor n; g <= i xor l; -- Inverter --inv:gf_inv port map (q, d); inv:gf_inv port map (g, q); temp_reg_p : DDR_register generic map ( SIZE=>4 ) port map( din_hi=>ah, din_lo=>ah, --dout=>p, dout_hi=>p_hi, dout_lo=>p_lo, rst=>reset, clk=>clock ); p <= p_hi when ( clock = '1' ) else p_lo; --temp_reg_q : DDR_register generic map ( SIZE=>4 ) port map( g, q, reset, clock ); temp_reg_q : DDR_register generic map ( SIZE=>4 ) port map( din_hi=>q, din_lo=>q, --dout=>d, dout_hi=>d_hi, dout_lo=>d_lo, rst=>reset, clk=>clock ); d <= d_hi when ( clock = '1' ) else d_lo; temp_reg_r : DDR_register generic map ( SIZE=>4 ) port map( din_hi=>f, din_lo=>f, --dout=>r, dout_hi=>r_hi, dout_lo=>r_lo, rst=>reset, clk=>clock ); r <= r_hi when ( clock = '1' ) else r_lo; gen002e : if ( not C_INCLUDE_DECODING_LOGIC ) generate s_enc_buffer <= C_ENC; end generate; -- gen002e : if ( not C_INCLUDE_DECODING_LOGIC ) gen002d : if ( C_INCLUDE_DECODING_LOGIC ) generate S_ENC_PROC : process( reset, clock ) begin if ( reset=RESET_ACTIVE ) then s_enc_buffer <= C_ENC; elsif ( clock'event and clock='1' ) then s_enc_buffer <= ctrl_dec; end if; end process S_ENC_PROC; end generate; -- gen002d : if ( C_INCLUDE_DECODING_LOGIC ) -- Second Moltiplicator molt2:gf_molt port map (p, d, a1h); -- Third Moltiplicator molt3:gf_molt port map (d, r, a1l); -- Inverse Map mapinv:gfmapinv port map (a1h, a1l, z); -- Inverse Affine Transformation at:aff_trans port map (z, t); gen001e : if ( not C_INCLUDE_DECODING_LOGIC ) generate b_out <= t; end generate; gen001d : if ( C_INCLUDE_DECODING_LOGIC ) generate b_out <= z when ( s_enc_buffer=C_DEC ) else t; end generate; end a_sbox;

library IEEE, STD; use STD.textio.all; use WORK.std_logic_textio.all; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity bstest_tb is end bstest_tb; architecture tb_arch of bstest_tb is -- UUT component component bstest port ( sldsw : in std_logic_vector(3 downto 0); button : in std_logic_vector(3 downto 0); -- N-E-W-S led : out std_logic_vector(7 downto 0) ); end component; -- I/O signals signal clk : std_logic := '0'; signal sldsw : std_logic_vector(3 downto 0); signal button : std_logic_vector(3 downto 0); signal led : std_logic_vector(7 downto 0); -- Constant declarations constant CLK_PERIOD : time := 20 ns; -- Declare results file file ResultsFile: text open write_mode is "bstest_results.txt"; begin uut : bstest port map ( sldsw => sldsw, button => button, led => led ); DATA_STIM: process variable count_hi : integer range 0 to 15 := 0; variable count_lo : integer range 0 to 15 := 0; variable line_el: line; begin for i in 0 to 255 loop count_hi := i / 16; count_lo := i mod 16; sldsw <= std_logic_vector(to_unsigned(count_hi, 4)); button <= std_logic_vector(to_unsigned(count_lo, 4)); -- Write the time write(line_el, now); -- write the line write(line_el, ':'); -- write the line -- Write the sldsw signal write(line_el, ' '); write(line_el, sldsw); -- write the line -- Write the button signal write(line_el, ' '); write(line_el, button); -- write the line wait for CLK_PERIOD; -- Write the led signal write(line_el, ' '); write(line_el, led); -- write the line writeline(ResultsFile, line_el); -- write the contents into the file wait for 9*CLK_PERIOD; end loop; wait for CLK_PERIOD; end process DATA_STIM; end tb_arch;

-- cpu.vhd: Simple 8-bit CPU (BrainFuck interpreter) -- Copyright (C) 2014 Brno University of Technology, -- Faculty of Information Technology -- Author(s): Ján Jusko xjusko00 -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -- ---------------------------------------------------------------------------- -- Entity declaration -- ---------------------------------------------------------------------------- entity cpu is port ( CLK : in std_logic; -- hodinovy signal RESET : in std_logic; -- asynchronni reset procesoru EN : in std_logic; -- povoleni cinnosti procesoru -- synchronni pamet RAM DATA_ADDR : out std_logic_vector(12 downto 0); -- adresa do pameti DATA_WDATA : out std_logic_vector(7 downto 0); -- mem[DATA_ADDR] <- DATA_WDATA pokud DATA_EN='1' DATA_RDATA : in std_logic_vector(7 downto 0); -- DATA_RDATA <- ram[DATA_ADDR] pokud DATA_EN='1' DATA_RDWR : out std_logic; -- cteni (0) / zapis (1) DATA_EN : out std_logic; -- povoleni cinnosti -- vstupni port IN_DATA : in std_logic_vector(7 downto 0); -- IN_DATA <- stav klavesnice pokud IN_VLD='1' a IN_REQ='1' IN_VLD : in std_logic; -- data platna IN_REQ : out std_logic; -- pozadavek na vstup data -- vystupni port OUT_DATA : out std_logic_vector(7 downto 0); -- zapisovana data OUT_BUSY : in std_logic; -- LCD je zaneprazdnen (1), nelze zapisovat OUT_WE : out std_logic -- LCD <- OUT_DATA pokud OUT_WE='1' a OUT_BUSY='0' ); end cpu; -- ---------------------------------------------------------------------------- -- Architecture declaration -- ---------------------------------------------------------------------------- architecture behavioral of cpu is -- PROGRAM COUNTER 13b signal PC_reg : std_logic_vector(12 downto 0); signal PC_inc : std_logic; signal PC_dec : std_logic; -- MEMORY POINTER 13b signal PTR_reg : std_logic_vector(12 downto 0); signal PTR_inc : std_logic; signal PTR_dec : std_logic; -- LOOP COUNTER 8b signal CNT_reg : std_logic_vector(7 downto 0); signal CNT_inc : std_logic; signal CNT_dec : std_logic; -- MULTIPLEXORY signal sel : std_logic := '0'; signal sel2 : std_logic_vector(1 downto 0) := "01"; -- INSTRUKCIE type inst is (incPTR, decPTR, incVALUE, decVALUE, whileS, whileE, putchar, readchar, halt, skip); signal decoded_inst : inst; -- STAVY MOOROVA FSM AUTOMATU type FSM_state is (SIDLE, SFETCH, SDECODE, SHALT, SSKIP, SINCPTR, SDECPTR, -- >/< SINCVALUE, SINCVALUE2, SDECVALUE, SDECVALUE2, -- +/- SPUTCHAR, SPUTCHAR2, -- . SREADCHAR, SREADCHAR2, -- , SWHILES,SWHILES2,SWHILES3,SWHILES4,SWHILES5, -- [ SWHILEE,SWHILEE1,SWHILEE2,SWHILEE3,SWHILEE4 -- ] ); signal Present_state: FSM_state; signal Next_state : FSM_state; begin -----------------------Program Counter----------------------- ------------------------------------------------------------- PC: process (CLK,RESET) begin if (RESET = '1') then PC_reg <= (others => '0'); elsif (CLK'event) and (CLK = '1') then if (PC_inc = '1') then PC_reg <= PC_reg + "0000000000001"; end if; if (PC_dec = '1') then PC_reg <= PC_reg - "0000000000001"; end if; end if; end process PC; -----------------------Memory pointer------------------------ ------------------------------------------------------------- PTR: process (CLK,RESET) begin if (RESET = '1') then PTR_reg <= "1000000000000"; elsif (CLK'event) and (CLK = '1') then if (PTR_inc = '1') then if (PTR_reg = "1111111111111") then -- KRUHOVOST OVERFLOW PTR_reg <= "1000000000000"; else PTR_reg <= PTR_reg + "0000000000001"; end if; end if; if (PTR_dec = '1') then if (PTR_reg = "1000000000000") then -- KRUHOVOST UNDERFLOW PTR_reg <= "1111111111111"; else PTR_reg <= PTR_reg - "0000000000001"; end if; end if; end if; end process PTR; -----------------------Loop counter-------------------------- ------------------------------------------------------------- CNT: process (CLK, RESET) begin if (RESET = '1') then CNT_reg <= (others=>'0'); elsif (CLK'event) and (CLK = '1') then if (CNT_inc = '1') then CNT_reg <= CNT_reg + "00000001"; end if; if (CNT_dec = '1') then CNT_reg <= CNT_reg - "00000001"; end if; end if; end process CNT; --------------------Finite state machine--------------------- ------------------------------------------------------------- FSM_pstate: process (CLK, RESET, EN) begin if (RESET = '1') then Present_state <= SIDLE; elsif (CLK'event) and (CLK = '1') then if (EN = '1') then Present_state <= Next_state; end if; end if; end process FSM_pstate; -----------------MULTIPLEXOR PC vs. PTR---------------------- ------------------------------------------------------------- MUX1: process (sel, PTR_reg, PC_reg) begin case sel is when '1' => DATA_ADDR <= PTR_reg; when '0' => DATA_ADDR <= PC_reg; when others => end case; end process MUX1; -----------------MULTIPLEXOR WRITE DATA---------------------- ------------------------------------------------------------- MUX2: process (sel2, DATA_RDATA, IN_DATA) begin case sel2 is when "01" => DATA_WDATA <= DATA_RDATA + "00000001"; when "10" => DATA_WDATA <= DATA_RDATA - "00000001"; when "11" => DATA_WDATA <= IN_DATA; when others => end case; end process MUX2; --------------------Instruction decoder---------------------- ------------------------------------------------------------- INST_decoder: process (DATA_RDATA) begin case DATA_RDATA is when X"00" => decoded_inst <= halt; when X"3E" => decoded_inst <= incPTR; when X"3C" => decoded_inst <= decPTR; when X"2B" => decoded_inst <= incVALUE; when X"2D" => decoded_inst <= decVALUE; when X"5B" => decoded_inst <= whileS; when X"5D" => decoded_inst <= whileE; when X"2E" => decoded_inst <= putchar; when X"2C" => decoded_inst <= readchar; when others=> decoded_inst <= skip; end case; end process INST_decoder; --------------------FSM PROCESSOR---------------------------- ------------------------------------------------------------- FSMPROCESSOR: process (Present_state, decoded_inst, OUT_BUSY, DATA_RDATA, IN_VLD, CNT_reg) begin IN_REQ <='0'; OUT_WE<='0'; DATA_RDWR<='0'; DATA_EN<='0'; PC_inc<='0'; PC_dec<='0'; PTR_inc<='0'; PTR_dec<='0'; CNT_inc<='0'; CNT_dec<='0'; sel <= '0'; sel2 <= "01"; OUT_DATA <= (others => '0'); case Present_state is when SIDLE => -- zaciatok, init, pri resete Next_state <= SFETCH; when SHALT => -- koniec programu Next_state <= SHALT; when SSKIP => -- preskoc komentare PC_inc <= '1'; Next_state <= SFETCH; when SFETCH => -- nacitaj instrukciu DATA_EN <= '1'; DATA_RDWR <= '0'; sel <= '0'; Next_state <= SDECODE; when SDECODE => -- dekoduj instrukciu case decoded_inst is when halt => Next_state <= SHALT; when incPTR => Next_state <= SINCPTR; when decPTR => Next_state <= SDECPTR; when incVALUE => Next_state <= SINCVALUE; when decVALUE => Next_state <= SDECVALUE; when whileS => Next_state <= SWHILES; when whileE => Next_state <= SWHILEE; when putchar => Next_state <= SPUTCHAR; when readchar => Next_state <= SREADCHAR; when skip => Next_state <= SSKIP; end case; -- PTR inkrement (>) when SINCPTR => PC_inc <= '1'; PTR_inc <= '1'; Next_state <= SFETCH; -- PTR dekrement (<) when SDECPTR => PC_inc <= '1'; PTR_dec <= '1'; Next_state <= SFETCH; -- *PTR inkrement (+) when SINCVALUE => sel <= '1'; DATA_RDWR <= '0'; DATA_EN <= '1'; Next_state <= SINCVALUE2; when SINCVALUE2 => DATA_RDWR <= '1'; DATA_EN <= '1'; sel <= '1'; sel2 <= "01"; PC_inc <= '1'; Next_state <= SFETCH; -- *PTR dekrement (-) when SDECVALUE => sel <= '1'; DATA_RDWR <= '0'; DATA_EN <= '1'; Next_state <= SDECVALUE2; when SDECVALUE2 => DATA_RDWR <= '1'; DATA_EN <= '1'; sel <= '1'; sel2 <= "10"; PC_inc <= '1'; Next_state <= SFETCH; -- vypis znak (.) when SPUTCHAR => DATA_RDWR <= '0'; DATA_EN <= '1'; sel <= '1'; Next_state <= SPUTCHAR2; when SPUTCHAR2 => if (OUT_BUSY = '0') then OUT_WE <= '1'; OUT_DATA <= DATA_RDATA; PC_inc <= '1'; Next_state <= SFETCH; else Next_state <= SPUTCHAR2; end if; -- nacitaj znak (,) when SREADCHAR => IN_REQ <= '1'; Next_state <= SREADCHAR2; when SREADCHAR2 => if (IN_VLD = '1') then sel <= '1'; sel2 <= "11"; DATA_RDWR <= '1'; DATA_EN <= '1'; PC_inc <= '1'; Next_state <= SFETCH; else IN_REQ <= '1'; Next_state <= SREADCHAR2; end if; -- WHILE ZACIATOK -- when SWHILES => DATA_RDWR <= '0'; DATA_EN <= '1'; PC_inc <= '1'; sel <= '1'; Next_state <= SWHILES2; when SWHILES2 => if (DATA_RDATA = "00000000") then CNT_inc <= '1'; Next_state <= SWHILES3; else Next_state <= SFETCH; end if; when SWHILES3 => DATA_RDWR <= '0'; DATA_EN <= '1'; sel <= '0'; Next_state <= SWHILES4; when SWHILES4 => if (decoded_inst = whileE) then CNT_dec <= '1'; elsif (decoded_inst = whileS) then CNT_inc <= '1'; end if; PC_inc <= '1'; Next_state <= SWHILES5; when SWHILES5 => if (CNT_reg = "00000000") then Next_state <= SFETCH; else Next_state <= SWHILES3; end if; -- WHILE KONIEC -- when SWHILEE => DATA_RDWR <= '0'; DATA_EN <= '1'; sel <= '1'; Next_state <= SWHILEE1; when SWHILEE1 => if (DATA_RDATA = "00000000") then PC_inc <= '1'; Next_state <= SFETCH; else CNT_inc <= '1'; PC_dec <= '1'; Next_state <= SWHILEE2; end if; when SWHILEE2 => sel <= '0'; DATA_RDWR <= '0'; DATA_EN <= '1'; Next_state <= SWHILEE3; when SWHILEE3 => if (decoded_inst = whileS) then CNT_dec <= '1'; elsif (decoded_inst = whileE) then CNT_inc <= '1'; end if; Next_state <= SWHILEE4; when SWHILEE4 => if (CNT_reg = "00000000") then PC_inc <= '1'; Next_state <= SFETCH; else PC_dec <= '1'; Next_state <= SWHILEE2; end if; end case; end process FSMPROCESSOR; end behavioral;

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; PACKAGE rc5_pkg IS type rc5_rom_26 is array (0 to 25) of std_logic_vector(31 downto 0); type rc5_rom_4 is array (0 to 3) of std_logic_vector(31 downto 0); type rc5_key_StateType is (ST_IDLE, -- In this state RC5 key expansion is ready for input ST_KEY_IN, -- In this state key has been fully loaded ST_KEY_EXP, -- In this state key expansion is in progress ST_READY); -- In this state RC5 key expansion has completed --RC5 state machine has five key states TYPE enc_StateType IS( ST_IDLE, -- In this state RC5 is ready for input ST_PRE_ROUND, -- In this state RC5 pre-round op is performed ST_ROUND_OP, -- In this state RC5 round op is performed. -- The state machine remains in this state -- for twelve clock cycles. ST_READY -- In this state RC5 has completed encryption ); TYPE dec_StateType IS( ST_IDLE, -- In this state RC5 is ready for input ST_ROUND_OP, -- In this state RC5 round op is performed. -- The state machine remains in this state -- for twelve clock cycles. ST_POST_ROUND, -- In this state RC5 post-round op is performed ST_READY -- In this state RC5 has completed encryption ); COMPONENT rc5_key -- Key expansion module PORT( clr,clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal key : in std_logic_vector(127 downto 0); key_vld : in std_logic; skey : out rc5_rom_26; key_rdy : out std_logic); END COMPONENT; COMPONENT rc5_enc -- Encryption module PORT( clr,clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit input di_vld : IN STD_LOGIC; -- Valid Input key_rdy : IN STD_LOGIC; skey : IN rc5_rom_26; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit output do_rdy : OUT STD_LOGIC --Output is Ready ); END COMPONENT; COMPONENT rc5_dec -- Decryption module PORT( clr,clk : IN STD_LOGIC; -- Asynchronous reset and Clock Signal din : IN STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit input di_vld : IN STD_LOGIC; -- Valid Input key_rdy : IN STD_LOGIC; skey : IN rc5_rom_26; dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- 64-bit output do_rdy : OUT STD_LOGIC --Output is Ready ); END COMPONENT; END rc5_pkg;

-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc940.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c10s05b00x00p03n02i00940pkg1 is function F1(B:in integer) return integer; end c10s05b00x00p03n02i00940pkg1; package body c10s05b00x00p03n02i00940pkg1 is function F1(B:in integer) return integer is begin return 1; end; end c10s05b00x00p03n02i00940pkg1; package c10s05b00x00p03n02i00940pkg2 is function F1(B:in bit) return boolean; end c10s05b00x00p03n02i00940pkg2; package body c10s05b00x00p03n02i00940pkg2 is function F1(B:in bit) return boolean is begin return false; end; end c10s05b00x00p03n02i00940pkg2; use work.c10s05b00x00p03n02i00940pkg1.all, work.c10s05b00x00p03n02i00940pkg2.all; ENTITY c10s05b00x00p03n02i00940ent IS END c10s05b00x00p03n02i00940ent; ARCHITECTURE c10s05b00x00p03n02i00940arch OF c10s05b00x00p03n02i00940ent IS BEGIN TESTING: PROCESS BEGIN if (F1('1') = F1('0')) then -- No_Failure_here assert FALSE report "***PASSED TEST: c10s05b00x00p03n02i00940" severity NOTE; else assert FALSE report "***FAILED TEST: c10s05b00x00p03n02i00940 - A single interpretation of each constituent of the innermost complete context is not an error." severity ERROR; end if; wait; END PROCESS TESTING; END c10s05b00x00p03n02i00940arch;

library ieee; use ieee.std_logic_1164.all; entity ent is port ( clk : in std_logic; set : in std_logic; reset : in std_logic; q : out std_logic ); end; architecture a of ent is signal s : std_logic; begin process(clk, set, reset) begin if set = '1' then s <= '1'; elsif reset = '1' then s <= '0'; elsif rising_edge(clk) then s <= not s; end if; end process; q <= s; end;

-- Algoritmo CORDIC -- (Rehecho de forma iterativa) library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.MATH_REAL.all; library work; use work.cordic_lib.all; entity cordic is generic ( P : natural := 16 -- Cantidad de iteraciones, determina la precisión ); port ( clk : in std_logic; rst : in std_logic; load : in std_logic; x_in, y_in : in t_coord; angle : in t_num; x_rot, y_rot : out t_coord; rotRdy : out std_logic ); end entity cordic; architecture cordic_arq of cordic is constant N_K : natural := N_BITS / 2; constant Nrom : natural := 32; type t_angles is array(natural range <>) of std_logic_vector(N_BITS-1 downto 0); constant ANGLES : t_angles(0 to Nrom-1) := ( -- Nrom primeros valores de atan(2^-i), convertidos std_logic_vector(to_unsigned(integer(round(0.785398163397448278999490867136 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.463647609000806093515478778500 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.244978663126864143473326862477 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.124354994546761438156678991618 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.062418809995957350023054743815 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.031239833430268277442154456480 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.015623728620476831294161534913 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.007812341060101111143987306917 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.003906230131966971757390139075 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.001953122516478818758434155001 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000976562189559319459436492750 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000488281211194898289926213941 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000244140620149361771244744812 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000122070311893670207853065945 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000061035156174208772593501454 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000030517578115526095727154735 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000015258789061315761542377868 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000007629394531101969981038997 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000003814697265606496141750756 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000001907348632810186964779285 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000953674316405960844127631 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000476837158203088842281064 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000238418579101557973667688 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000119209289550780680899739 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000059604644775390552208106 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000029802322387695302573833 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000014901161193847654595639 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000007450580596923828125000 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000003725290298461914062500 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000001862645149230957031250 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000000931322574615478515625 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)), std_logic_vector(to_unsigned(integer(round(0.000000000465661287307739257812 * real(2**(N_BITS-0)) / (2.0*MATH_PI) )), N_BITS)) ); type t_kvalues is array(natural range <>) of std_logic_vector(N_K-1 downto 0); constant K_VALUES : t_kvalues(0 to Nrom-1) := ( -- Nrom primeros cumprod(1 ./ abs(1 + 1j*2.^(-(0:25)))) std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.707106781186547461715008466854)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.632455532033675771330649695301)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.613571991077896283783843500714)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.608833912517752429138795378094)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607648256256168139977091868786)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607351770141295932425862247328)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607277644093526025592666428565)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607259112298892733683430833480)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607254479332562269178197311703)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607253321089875175431416209904)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607253031529134346122589249717)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252959138944836681162087189)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252941041397154009473524638)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252936517010177830400152743)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935385913406030056194140)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935103139268591121435747)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935032445706475812130520)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935014772288191409188585)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935010353933620308453101)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935009249372733108884859)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008973260266884608427)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008904204394752923690)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008886884915568771248)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008882666068075195653)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881555845050570497)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881222778143182950)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881222778143182950)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881222778143182950)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881222778143182950)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881222778143182950)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881222778143182950)), N_K)), std_logic_vector(to_signed(integer(round( real(2**N_K) * 0.607252935008881222778143182950)), N_K)) ); signal x_in_e, x_in_n, x0, x_1, x_2, x_2_sh, x_3, x_4 : t_coord_e := (others => '0'); signal y_in_e, y_in_n, y0, y_1, y_2, y_2_sh, y_3, y_4 : t_coord_e := (others => '0'); signal x_5, y_5 : std_logic_vector((N_EXTR+N_K)-1 downto 0) := (others => '0'); signal angle0, angle_1, angle_2, angle_3 : t_num := (others => '0'); subtype natural_i is natural range 0 to 31; signal i : natural_i := P; signal cuadrante : std_logic_vector(1 downto 0) := "00"; signal angle_i : std_logic_vector(N_BITS-1 downto 0) := (others => '0'); --signal angle_i : unsigned(N_BITS-1 downto 0) := (others => '0'); signal sigma : std_logic := '0'; signal ena_reg : std_logic := '0'; signal stRdy : std_logic := '0'; type t_estado is (IDLE, LOADING, ROTA, RDY); signal estado : t_estado := IDLE; begin -- Extiendo coordenadas x_in_e <= (N_EXTR-N_BITS-1 downto 0 => x_in(N_BITS-1)) & x_in; y_in_e <= (N_EXTR-N_BITS-1 downto 0 => y_in(N_BITS-1)) & y_in; -- Versiones negativas x_in_n <= std_logic_vector(signed(not x_in_e) + 1); y_in_n <= std_logic_vector(signed(not y_in_e) + 1); -- Iterador process(clk, rst, load) begin if rst = '1' then i <= P; estado <= IDLE; elsif rising_edge(clk) then if load = '1' then -- Cargo nueva posición para rotar estado <= LOADING; i <= 0; elsif i < P-2 then -- Sigo rotando estado <= ROTA; i <= i + 1; elsif i = P-2 then -- Terminé de rotar posición estado <= RDY; i <= i + 1; else estado <= IDLE; end if; end if; end process; ena_reg <= '1' when (estado = LOADING or estado = ROTA or load = '1') else '0'; stRdy <= '1' when (estado = RDY) else '0'; -- Averiguo cuadrante con los 2 MSBs del ángulo cuadrante <= angle(N_BITS-1 downto N_BITS-2); -- Rotación inicial (pongo en el cuadrante correcto) x0 <= x_in_e when cuadrante = "00" else y_in_n when cuadrante = "01" else x_in_n when cuadrante = "10" else y_in_e when cuadrante = "11"; y0 <= y_in_e when cuadrante = "00" else x_in_e when cuadrante = "01" else y_in_n when cuadrante = "10" else x_in_n when cuadrante = "11"; angle0 <= "00" & angle(N_BITS-3 downto 0); -- Uso pos nueva si cargando o sigo rotando x_1 <= x0 when load = '1' else x_3; y_1 <= y0 when load = '1' else y_3; angle_1 <= angle0 when load = '1' else angle_3; -- ... reg_x: entity work.registroNb generic map( N => N_EXTR ) port map( clk => clk, rst => rst, ena => ena_reg, d => x_1, q => x_2 ); reg_y: entity work.registroNb generic map( N => N_EXTR ) port map( clk => clk, rst => rst, ena => ena_reg, d => y_1, q => y_2 ); reg_angle: entity work.registroNb generic map( N => N_BITS ) port map( clk => clk, rst => rst, ena => ena_reg, d => angle_1, q => angle_2 ); -- ... bshift_x: entity work.barrel_shifterNb generic map( N => N_EXTR ) port map( to_left => '0', M => i, a => x_2, o => x_2_sh ); bshift_y: entity work.barrel_shifterNb generic map( N => N_EXTR ) port map( to_left => '0', M => i, a => y_2, o => y_2_sh ); -- ... x_3 <= std_logic_vector(unsigned(x_2) + unsigned(y_2_sh)) when sigma = '1' else std_logic_vector(unsigned(x_2) - unsigned(y_2_sh)); y_3 <= std_logic_vector(unsigned(y_2) + unsigned(x_2_sh)) when sigma = '0' else std_logic_vector(unsigned(y_2) - unsigned(x_2_sh)); angle_i <= ANGLES(i); ----ANGLES_DEG(i);---- when (i < ANGLES'length) else ----(angle(ANGLES'length-1) / (2**(i - ANGLES'length + 1))); ------ Si me paso de la tabla, aproximo angle_3 <= std_logic_vector(unsigned(angle_2) + unsigned(angle_i)) when sigma = '1' else std_logic_vector(unsigned(angle_2) - unsigned(angle_i)); -- Signo del ángulo de rotación restante sigma <= angle_2(N_BITS-1) when (estado = ROTA) else '0'; -- ... pipe_reg_x: entity work.registroNb generic map( N => N_EXTR ) port map( clk => clk, rst => rst, ena => '1', d => x_3, q => x_4 ); pipe_reg_y: entity work.registroNb generic map( N => N_EXTR ) port map( clk => clk, rst => rst, ena => '1', d => y_3, q => y_4 ); -- ... delay_Rdy: entity work.ffd port map( clk => clk, rst => rst, ena => '1', d => stRdy, q => rotRdy ); -- Intermedio x_5 <= std_logic_vector( signed(x_4) * signed(K_VALUES(i)) ); y_5 <= std_logic_vector( signed(y_4) * signed(K_VALUES(i)) ); -- Salida de la rotación (si rotRdy) x_rot <= x_5(N_EXTR+N_K-3 downto N_EXTR+N_K-3-N_BITS+1); y_rot <= y_5(N_EXTR+N_K-3 downto N_EXTR+N_K-3-N_BITS+1); end cordic_arq;

-- ========== Copyright Header Begin ============================================= -- AmgPacman File: rom.vhd -- Copyright (c) 2015 Alberto Miedes Garcés -- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. -- -- The above named program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- The above named program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with Foobar. If not, see <http://www.gnu.org/licenses/>. -- ========== Copyright Header End =============================================== ---------------------------------------------------------------------------------- -- Engineer: Alberto Miedes Garcés -- Correo: [email protected] -- Create Date: January 2015 -- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent) ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tablero_rom is port ( clk: in std_logic; x : in std_logic_vector(2 downto 0); y : in std_logic_vector(2 downto 0); rgb: out std_logic_vector(2 downto 0) ); end tablero_rom; architecture arq of tablero_rom is type memory_slv is array (0 to 7) of std_logic_vector(2 downto 0); type memory_img is array (0 to 7) of memory_slv; constant rom_img : memory_img := ( ("001","001","001","001","001","001","001","001"), ("001","000","000","000","000","000","000","001"), ("001","000","001","000","000","001","000","001"), ("001","000","000","000","000","000","000","001"), ("001","000","000","000","001","000","000","001"), ("001","000","001","000","000","001","000","001"), ("001","000","000","000","000","000","000","001"), ("001","001","001","001","001","001","001","001") ); begin process(clk,x,y ) begin if clk'event and clk='1' then rgb(2 downto 0) <= rom_img(to_integer(unsigned(y)))(to_integer(unsigned(x)))(2 downto 0); end if; end process; end arq;

-- -------------------------------------------------------------------- -- -- Copyright © 2008 by IEEE. All rights reserved. -- -- This source file is an essential part of IEEE Std 1076-2008, -- IEEE Standard VHDL Language Reference Manual. This source file may not be -- copied, sold, or included with software that is sold without written -- permission from the IEEE Standards Department. This source file may be -- copied for individual use between licensed users. This source file is -- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR -- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE -- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify -- and hold IEEE harmless from any damages or liability arising out of the -- use thereof. -- -- Title : Fixed-point package (Generic package declaration) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: Accellera VHDL-TC and IEEE P1076 Working Group -- : -- Purpose : This packages defines basic binary fixed point -- : arithmetic functions -- : -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- use STD.TEXTIO.all; library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.fixed_float_types.all; package fixed_generic_pkg is generic ( -- Rounding routine to use in fixed point, fixed_round or fixed_truncate fixed_round_style : fixed_round_style_type := fixed_round; -- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap fixed_overflow_style : fixed_overflow_style_type := fixed_saturate; -- Extra bits used in divide routines fixed_guard_bits : NATURAL := 3; -- If TRUE, then turn off warnings on "X" propagation no_warning : BOOLEAN := false ); -- Author David Bishop ([email protected]) constant CopyRightNotice : STRING := "Copyright 2008 by IEEE. All rights reserved."; -- base Unsigned fixed point type, downto direction assumed type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC; -- base Signed fixed point type, downto direction assumed type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC; alias U_ufixed is UNRESOLVED_ufixed; alias U_sfixed is UNRESOLVED_sfixed; subtype ufixed is (resolved) UNRESOLVED_ufixed; subtype sfixed is (resolved) UNRESOLVED_sfixed; --=========================================================================== -- Arithmetic Operators: --=========================================================================== -- Absolute value, 2's complement -- abs sfixed(a downto b) = sfixed(a+1 downto b) function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- Negation, 2's complement -- - sfixed(a downto b) = sfixed(a+1 downto b) function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed; -- Addition -- ufixed(a downto b) + ufixed(c downto d) -- = ufixed(maximum(a,c)+1 downto minimum(b,d)) function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- sfixed(a downto b) + sfixed(c downto d) -- = sfixed(maximum(a,c)+1 downto minimum(b,d)) function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- Subtraction -- ufixed(a downto b) - ufixed(c downto d) -- = ufixed(maximum(a,c)+1 downto minimum(b,d)) function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- sfixed(a downto b) - sfixed(c downto d) -- = sfixed(maximum(a,c)+1 downto minimum(b,d)) function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- Multiplication -- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d) function "*" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d) function "*" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- Division -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1) function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c) function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- Remainder -- ufixed (a downto b) rem ufixed (c downto d) -- = ufixed (minimum(a,c) downto minimum(b,d)) function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- sfixed (a downto b) rem sfixed (c downto d) -- = sfixed (minimum(a,c) downto minimum(b,d)) function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- Modulo -- ufixed (a downto b) mod ufixed (c downto d) -- = ufixed (minimum(a,c) downto minimum(b, d)) function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- sfixed (a downto b) mod sfixed (c downto d) -- = sfixed (c downto minimum(b, d)) function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; ---------------------------------------------------------------------------- -- In these routines the "real" or "natural" (integer) -- are converted into a fixed point number and then the operation is -- performed. It is assumed that the array will be large enough. -- If the input is "real" then the real number is converted into a fixed of -- the same size as the fixed point input. If the number is an "integer" -- then it is converted into fixed with the range (l'high downto 0). ---------------------------------------------------------------------------- -- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b) function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; -- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d) function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b)) function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d)) function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b) function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; -- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d) function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b)) function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d)) function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b) function "*" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; -- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d) function "*" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b) function "*" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; -- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b) function "*" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1) function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1) function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1) function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; -- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1) function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b) function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; -- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d) function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0)) function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; -- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0)) function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b) function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; -- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d) function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0)) function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; -- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0)) function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; -- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b) function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; -- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d) function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b)) function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; -- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d)) function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b) function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; -- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d) function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b)) function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; -- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d)) function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b) function "*" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; -- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d) function "*" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b) function "*" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; -- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d) function "*" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a) function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; -- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c) function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a) function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; -- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c) function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b) function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; -- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d) function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0)) function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; -- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0)) function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b) function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; -- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d) function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0)) function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; -- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0)) function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- This version of divide gives the user more control -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1) function divide ( l, r : UNRESOLVED_ufixed; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_ufixed; -- This version of divide gives the user more control -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c) function divide ( l, r : UNRESOLVED_sfixed; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_sfixed; -- These functions return 1/X -- 1 / ufixed(a downto b) = ufixed(-b downto -a-1) function reciprocal ( arg : UNRESOLVED_ufixed; -- fixed point input constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_ufixed; -- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a) function reciprocal ( arg : UNRESOLVED_sfixed; -- fixed point input constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_sfixed; -- REM function -- ufixed (a downto b) rem ufixed (c downto d) -- = ufixed (minimum(a,c) downto minimum(b,d)) function remainder ( l, r : UNRESOLVED_ufixed; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_ufixed; -- sfixed (a downto b) rem sfixed (c downto d) -- = sfixed (minimum(a,c) downto minimum(b,d)) function remainder ( l, r : UNRESOLVED_sfixed; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_sfixed; -- mod function -- ufixed (a downto b) mod ufixed (c downto d) -- = ufixed (minimum(a,c) downto minimum(b, d)) function modulo ( l, r : UNRESOLVED_ufixed; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_ufixed; -- sfixed (a downto b) mod sfixed (c downto d) -- = sfixed (c downto minimum(b, d)) function modulo ( l, r : UNRESOLVED_sfixed; constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_sfixed; -- Procedure for those who need an "accumulator" function. -- add_carry (ufixed(a downto b), ufixed (c downto d)) -- = ufixed (maximum(a,c) downto minimum(b,d)) procedure add_carry ( L, R : in UNRESOLVED_ufixed; c_in : in STD_ULOGIC; result : out UNRESOLVED_ufixed; c_out : out STD_ULOGIC); -- add_carry (sfixed(a downto b), sfixed (c downto d)) -- = sfixed (maximum(a,c) downto minimum(b,d)) procedure add_carry ( L, R : in UNRESOLVED_sfixed; c_in : in STD_ULOGIC; result : out UNRESOLVED_sfixed; c_out : out STD_ULOGIC); -- Scales the result by a power of 2. Width of input = width of output with -- the binary point moved. function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed; function scalb (y : UNRESOLVED_ufixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_ufixed; function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed; function scalb (y : UNRESOLVED_sfixed; N : UNRESOLVED_SIGNED) return UNRESOLVED_sfixed; function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN; --=========================================================================== -- Comparison Operators --=========================================================================== function ">" (l, r : UNRESOLVED_ufixed) return BOOLEAN; function ">" (l, r : UNRESOLVED_sfixed) return BOOLEAN; function "<" (l, r : UNRESOLVED_ufixed) return BOOLEAN; function "<" (l, r : UNRESOLVED_sfixed) return BOOLEAN; function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN; function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN; function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN; function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN; function "=" (l, r : UNRESOLVED_ufixed) return BOOLEAN; function "=" (l, r : UNRESOLVED_sfixed) return BOOLEAN; function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN; function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN; function "?=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?/=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?>" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?>=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?<" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?<=" (l, r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?/=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?>" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?>=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?<" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?<=" (l, r : UNRESOLVED_sfixed) return STD_ULOGIC; function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN; function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN; -- Overloads the default "maximum" and "minimum" function function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; ---------------------------------------------------------------------------- -- In these compare functions a natural is converted into a -- fixed point number of the bounds "maximum(l'high,0) downto 0" ---------------------------------------------------------------------------- function "=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; function ">" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; function "<" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN; function "=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; function ">" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "<" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "?=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; function "?/=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; function "?>=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; function "?<=" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; function "?>" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; function "?<" (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC; function "?=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?/=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?>=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?<=" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?>" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?<" (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function maximum (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; function minimum (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed; function maximum (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function minimum (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; ---------------------------------------------------------------------------- -- In these compare functions a real is converted into a -- fixed point number of the bounds "l'high+1 downto l'low" ---------------------------------------------------------------------------- function "=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; function ">" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; function "<" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN; function "=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; function ">" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "<" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN; function "?=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; function "?/=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; function "?>=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; function "?<=" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; function "?>" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; function "?<" (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC; function "?=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?/=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?>=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?<=" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?>" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function "?<" (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC; function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed; function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; ---------------------------------------------------------------------------- -- In these compare functions an integer is converted into a -- fixed point number of the bounds "maximum(l'high,1) downto 0" ---------------------------------------------------------------------------- function "=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; function ">" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; function "<" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN; function "=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; function ">" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; function "<" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN; function "?=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; function "?/=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; function "?>=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; function "?<=" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; function "?>" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; function "?<" (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC; function "?=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?/=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?>=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?<=" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?>" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?<" (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC; function maximum (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; function maximum (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function minimum (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed; function minimum (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; ---------------------------------------------------------------------------- -- In these compare functions a real is converted into a -- fixed point number of the bounds "l'high+1 downto l'low" ---------------------------------------------------------------------------- function "=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; function ">" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; function "<" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN; function "=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; function ">" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; function "<" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN; function "?=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; function "?/=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; function "?>=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; function "?<=" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; function "?>" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; function "?<" (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC; function "?=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?/=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?>=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?<=" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?>" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; function "?<" (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC; function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed; function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; --=========================================================================== -- Shift and Rotate Functions. -- Note that sra and sla are not the same as the BIT_VECTOR version --=========================================================================== function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) return UNRESOLVED_ufixed; function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) return UNRESOLVED_ufixed; function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) return UNRESOLVED_ufixed; function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) return UNRESOLVED_ufixed; function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) return UNRESOLVED_ufixed; function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER) return UNRESOLVED_ufixed; function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) return UNRESOLVED_sfixed; function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) return UNRESOLVED_sfixed; function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) return UNRESOLVED_sfixed; function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) return UNRESOLVED_sfixed; function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) return UNRESOLVED_sfixed; function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER) return UNRESOLVED_sfixed; function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL) return UNRESOLVED_ufixed; function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL) return UNRESOLVED_ufixed; function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL) return UNRESOLVED_sfixed; function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL) return UNRESOLVED_sfixed; ---------------------------------------------------------------------------- -- logical functions ---------------------------------------------------------------------------- function "not" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "and" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "or" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "nor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "xor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "not" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "and" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "or" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "nor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "xor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- Vector and std_ulogic functions, same as functions in numeric_std function "and" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "and" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) return UNRESOLVED_ufixed; function "or" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "or" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) return UNRESOLVED_ufixed; function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) return UNRESOLVED_ufixed; function "nor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "nor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) return UNRESOLVED_ufixed; function "xor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "xor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) return UNRESOLVED_ufixed; function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC) return UNRESOLVED_ufixed; function "and" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "and" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) return UNRESOLVED_sfixed; function "or" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "or" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) return UNRESOLVED_sfixed; function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) return UNRESOLVED_sfixed; function "nor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "nor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) return UNRESOLVED_sfixed; function "xor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "xor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) return UNRESOLVED_sfixed; function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC) return UNRESOLVED_sfixed; -- Reduction operators, same as numeric_std functions function "and" (l : UNRESOLVED_ufixed) return STD_ULOGIC; function "nand" (l : UNRESOLVED_ufixed) return STD_ULOGIC; function "or" (l : UNRESOLVED_ufixed) return STD_ULOGIC; function "nor" (l : UNRESOLVED_ufixed) return STD_ULOGIC; function "xor" (l : UNRESOLVED_ufixed) return STD_ULOGIC; function "xnor" (l : UNRESOLVED_ufixed) return STD_ULOGIC; function "and" (l : UNRESOLVED_sfixed) return STD_ULOGIC; function "nand" (l : UNRESOLVED_sfixed) return STD_ULOGIC; function "or" (l : UNRESOLVED_sfixed) return STD_ULOGIC; function "nor" (l : UNRESOLVED_sfixed) return STD_ULOGIC; function "xor" (l : UNRESOLVED_sfixed) return STD_ULOGIC; function "xnor" (l : UNRESOLVED_sfixed) return STD_ULOGIC; -- returns arg'low-1 if not found function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC) return INTEGER; function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC) return INTEGER; -- returns arg'high+1 if not found function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC) return INTEGER; function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC) return INTEGER; --=========================================================================== -- RESIZE Functions --=========================================================================== -- resizes the number (larger or smaller) -- The returned result will be ufixed (left_index downto right_index) -- If "round_style" is fixed_round, then the result will be rounded. -- If the MSB of the remainder is a "1" AND the LSB of the unrounded result -- is a '1' or the lower bits of the remainder include a '1' then the result -- will be increased by the smallest representable number for that type. -- "overflow_style" can be fixed_saturate or fixed_wrap. -- In saturate mode, if the number overflows then the largest possible -- representable number is returned. If wrap mode, then the upper bits -- of the number are truncated. function resize ( arg : UNRESOLVED_ufixed; -- input constant left_index : INTEGER; -- integer portion constant right_index : INTEGER; -- size of fraction constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_ufixed; -- "size_res" functions create the size of the output from the indices -- of the "size_res" input. The actual value of "size_res" is not used. function resize ( arg : UNRESOLVED_ufixed; -- input size_res : UNRESOLVED_ufixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_ufixed; -- Note that in "wrap" mode the sign bit is not replicated. Thus the -- resize of a negative number can have a positive result in wrap mode. function resize ( arg : UNRESOLVED_sfixed; -- input constant left_index : INTEGER; -- integer portion constant right_index : INTEGER; -- size of fraction constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_sfixed; function resize ( arg : UNRESOLVED_sfixed; -- input size_res : UNRESOLVED_sfixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_sfixed; --=========================================================================== -- Conversion Functions --=========================================================================== -- integer (natural) to unsigned fixed point. -- arguments are the upper and lower bounds of the number, thus -- ufixed (7 downto -3) <= to_ufixed (int, 7, -3); function to_ufixed ( arg : NATURAL; -- integer constant left_index : INTEGER; -- left index (high index) constant right_index : INTEGER := 0; -- right index constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_ufixed; function to_ufixed ( arg : NATURAL; -- integer size_res : UNRESOLVED_ufixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_ufixed; -- real to unsigned fixed point function to_ufixed ( arg : REAL; -- real constant left_index : INTEGER; -- left index (high index) constant right_index : INTEGER; -- right index constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_ufixed; function to_ufixed ( arg : REAL; -- real size_res : UNRESOLVED_ufixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_ufixed; -- unsigned to unsigned fixed point function to_ufixed ( arg : UNRESOLVED_UNSIGNED; -- unsigned constant left_index : INTEGER; -- left index (high index) constant right_index : INTEGER := 0; -- right index constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_ufixed; function to_ufixed ( arg : UNRESOLVED_UNSIGNED; -- unsigned size_res : UNRESOLVED_ufixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_ufixed; -- Performs a conversion. ufixed (arg'range) is returned function to_ufixed ( arg : UNRESOLVED_UNSIGNED) -- unsigned return UNRESOLVED_ufixed; -- unsigned fixed point to unsigned function to_unsigned ( arg : UNRESOLVED_ufixed; -- fixed point input constant size : NATURAL; -- length of output constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_UNSIGNED; -- unsigned fixed point to unsigned function to_unsigned ( arg : UNRESOLVED_ufixed; -- fixed point input size_res : UNRESOLVED_UNSIGNED; -- used for length of output constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_UNSIGNED; -- unsigned fixed point to real function to_real ( arg : UNRESOLVED_ufixed) -- fixed point input return REAL; -- unsigned fixed point to integer function to_integer ( arg : UNRESOLVED_ufixed; -- fixed point input constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return NATURAL; -- Integer to UNRESOLVED_sfixed function to_sfixed ( arg : INTEGER; -- integer constant left_index : INTEGER; -- left index (high index) constant right_index : INTEGER := 0; -- right index constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_sfixed; function to_sfixed ( arg : INTEGER; -- integer size_res : UNRESOLVED_sfixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_sfixed; -- Real to sfixed function to_sfixed ( arg : REAL; -- real constant left_index : INTEGER; -- left index (high index) constant right_index : INTEGER; -- right index constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_sfixed; function to_sfixed ( arg : REAL; -- real size_res : UNRESOLVED_sfixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style; constant guard_bits : NATURAL := fixed_guard_bits) return UNRESOLVED_sfixed; -- signed to sfixed function to_sfixed ( arg : UNRESOLVED_SIGNED; -- signed constant left_index : INTEGER; -- left index (high index) constant right_index : INTEGER := 0; -- right index constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_sfixed; function to_sfixed ( arg : UNRESOLVED_SIGNED; -- signed size_res : UNRESOLVED_sfixed; -- for size only constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_sfixed; -- signed to sfixed (output assumed to be size of signed input) function to_sfixed ( arg : UNRESOLVED_SIGNED) -- signed return UNRESOLVED_sfixed; -- Conversion from ufixed to sfixed function to_sfixed ( arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed; -- signed fixed point to signed function to_signed ( arg : UNRESOLVED_sfixed; -- fixed point input constant size : NATURAL; -- length of output constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_SIGNED; -- signed fixed point to signed function to_signed ( arg : UNRESOLVED_sfixed; -- fixed point input size_res : UNRESOLVED_SIGNED; -- used for length of output constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return UNRESOLVED_SIGNED; -- signed fixed point to real function to_real ( arg : UNRESOLVED_sfixed) -- fixed point input return REAL; -- signed fixed point to integer function to_integer ( arg : UNRESOLVED_sfixed; -- fixed point input constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; constant round_style : fixed_round_style_type := fixed_round_style) return INTEGER; -- Because of the fairly complicated sizing rules in the fixed point -- packages these functions are provided to compute the result ranges -- Example: -- signal uf1 : ufixed (3 downto -3); -- signal uf2 : ufixed (4 downto -2); -- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto -- ufixed_low (3, -3, '*', 4, -2)); -- uf1multuf2 <= uf1 * uf2; -- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod), -- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -) function ufixed_high (left_index, right_index : INTEGER; operation : CHARACTER := 'X'; left_index2, right_index2 : INTEGER := 0) return INTEGER; function ufixed_low (left_index, right_index : INTEGER; operation : CHARACTER := 'X'; left_index2, right_index2 : INTEGER := 0) return INTEGER; function sfixed_high (left_index, right_index : INTEGER; operation : CHARACTER := 'X'; left_index2, right_index2 : INTEGER := 0) return INTEGER; function sfixed_low (left_index, right_index : INTEGER; operation : CHARACTER := 'X'; left_index2, right_index2 : INTEGER := 0) return INTEGER; -- Same as above, but using the "size_res" input only for their ranges: -- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto -- ufixed_low (uf1, '*', uf2)); -- uf1multuf2 <= uf1 * uf2; -- function ufixed_high (size_res : UNRESOLVED_ufixed; operation : CHARACTER := 'X'; size_res2 : UNRESOLVED_ufixed) return INTEGER; function ufixed_low (size_res : UNRESOLVED_ufixed; operation : CHARACTER := 'X'; size_res2 : UNRESOLVED_ufixed) return INTEGER; function sfixed_high (size_res : UNRESOLVED_sfixed; operation : CHARACTER := 'X'; size_res2 : UNRESOLVED_sfixed) return INTEGER; function sfixed_low (size_res : UNRESOLVED_sfixed; operation : CHARACTER := 'X'; size_res2 : UNRESOLVED_sfixed) return INTEGER; -- purpose: returns a saturated number function saturate ( constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_ufixed; -- purpose: returns a saturated number function saturate ( constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_sfixed; function saturate ( size_res : UNRESOLVED_ufixed) -- only the size of this is used return UNRESOLVED_ufixed; function saturate ( size_res : UNRESOLVED_sfixed) -- only the size of this is used return UNRESOLVED_sfixed; --=========================================================================== -- Translation Functions --=========================================================================== -- maps meta-logical values function to_01 ( s : UNRESOLVED_ufixed; -- fixed point input constant XMAP : STD_ULOGIC := '0') -- Map x to return UNRESOLVED_ufixed; -- maps meta-logical values function to_01 ( s : UNRESOLVED_sfixed; -- fixed point input constant XMAP : STD_ULOGIC := '0') -- Map x to return UNRESOLVED_sfixed; function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN; function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN; function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; -- straight vector conversion routines, needed for synthesis. -- These functions are here so that a std_logic_vector can be -- converted to and from sfixed and ufixed. Note that you can -- not convert these vectors because of their negative index. function to_slv ( arg : UNRESOLVED_ufixed) -- fixed point vector return STD_LOGIC_VECTOR; alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed return STD_LOGIC_VECTOR]; alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed return STD_LOGIC_VECTOR]; function to_slv ( arg : UNRESOLVED_sfixed) -- fixed point vector return STD_LOGIC_VECTOR; alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed return STD_LOGIC_VECTOR]; alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed return STD_LOGIC_VECTOR]; function to_sulv ( arg : UNRESOLVED_ufixed) -- fixed point vector return STD_ULOGIC_VECTOR; alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed return STD_ULOGIC_VECTOR]; alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed return STD_ULOGIC_VECTOR]; function to_sulv ( arg : UNRESOLVED_sfixed) -- fixed point vector return STD_ULOGIC_VECTOR; alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed return STD_ULOGIC_VECTOR]; alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed return STD_ULOGIC_VECTOR]; function to_ufixed ( arg : STD_ULOGIC_VECTOR; -- shifted vector constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_ufixed; function to_ufixed ( arg : STD_ULOGIC_VECTOR; -- shifted vector size_res : UNRESOLVED_ufixed) -- for size only return UNRESOLVED_ufixed; function to_sfixed ( arg : STD_ULOGIC_VECTOR; -- shifted vector constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_sfixed; function to_sfixed ( arg : STD_ULOGIC_VECTOR; -- shifted vector size_res : UNRESOLVED_sfixed) -- for size only return UNRESOLVED_sfixed; -- As a concession to those who use a graphical DSP environment, -- these functions take parameters in those tools format and create -- fixed point numbers. These functions are designed to convert from -- a std_logic_vector to the VHDL fixed point format using the conventions -- of these packages. In a pure VHDL environment you should use the -- "to_ufixed" and "to_sfixed" routines. -- unsigned fixed point function to_UFix ( arg : STD_ULOGIC_VECTOR; width : NATURAL; -- width of vector fraction : NATURAL) -- width of fraction return UNRESOLVED_ufixed; -- signed fixed point function to_SFix ( arg : STD_ULOGIC_VECTOR; width : NATURAL; -- width of vector fraction : NATURAL) -- width of fraction return UNRESOLVED_sfixed; -- finding the bounds of a number. These functions can be used like this: -- signal xxx : ufixed (7 downto -3); -- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))" -- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3) -- downto UFix_low(11, 3, "+", 11, 3)); -- Where "11" is the width of xxx (xxx'length), -- and 3 is the lower bound (abs (xxx'low)) -- In a pure VHDL environment use "ufixed_high" and "ufixed_low" function UFix_high (width, fraction : NATURAL; operation : CHARACTER := 'X'; width2, fraction2 : NATURAL := 0) return INTEGER; function UFix_low (width, fraction : NATURAL; operation : CHARACTER := 'X'; width2, fraction2 : NATURAL := 0) return INTEGER; -- Same as above but for signed fixed point. Note that the width -- of a signed fixed point number ignores the sign bit, thus -- width = sxxx'length-1 function SFix_high (width, fraction : NATURAL; operation : CHARACTER := 'X'; width2, fraction2 : NATURAL := 0) return INTEGER; function SFix_low (width, fraction : NATURAL; operation : CHARACTER := 'X'; width2, fraction2 : NATURAL := 0) return INTEGER; --=========================================================================== -- string and textio Functions --=========================================================================== -- purpose: writes fixed point into a line procedure WRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_ufixed; -- fixed point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); -- purpose: writes fixed point into a line procedure WRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_sfixed; -- fixed point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); procedure READ(L : inout LINE; VALUE : out UNRESOLVED_ufixed); procedure READ(L : inout LINE; VALUE : out UNRESOLVED_ufixed; GOOD : out BOOLEAN); procedure READ(L : inout LINE; VALUE : out UNRESOLVED_sfixed); procedure READ(L : inout LINE; VALUE : out UNRESOLVED_sfixed; GOOD : out BOOLEAN); alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width]; alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width]; alias bread is READ [LINE, UNRESOLVED_ufixed]; alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN]; alias bread is READ [LINE, UNRESOLVED_sfixed]; alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN]; alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width]; alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width]; alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN]; alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed]; alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN]; alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed]; -- octal read and write procedure OWRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_ufixed; -- fixed point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); procedure OWRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_sfixed; -- fixed point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_ufixed); procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_ufixed; GOOD : out BOOLEAN); procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_sfixed); procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_sfixed; GOOD : out BOOLEAN); alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN]; alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed]; alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN]; alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed]; alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH]; alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH]; -- hex read and write procedure HWRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_ufixed; -- fixed point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); -- purpose: writes fixed point into a line procedure HWRITE ( L : inout LINE; -- input line VALUE : in UNRESOLVED_sfixed; -- fixed point input JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0); procedure HREAD(L : inout LINE; VALUE : out UNRESOLVED_ufixed); procedure HREAD(L : inout LINE; VALUE : out UNRESOLVED_ufixed; GOOD : out BOOLEAN); procedure HREAD(L : inout LINE; VALUE : out UNRESOLVED_sfixed); procedure HREAD(L : inout LINE; VALUE : out UNRESOLVED_sfixed; GOOD : out BOOLEAN); alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN]; alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN]; alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed]; alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed]; alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH]; alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH]; -- returns a string, useful for: -- assert (x = y) report "error found " & to_string(x) severity error; function to_string (value : UNRESOLVED_ufixed) return STRING; alias to_bstring is to_string [UNRESOLVED_ufixed return STRING]; alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING]; function to_ostring (value : UNRESOLVED_ufixed) return STRING; alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING]; function to_hstring (value : UNRESOLVED_ufixed) return STRING; alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING]; function to_string (value : UNRESOLVED_sfixed) return STRING; alias to_bstring is to_string [UNRESOLVED_sfixed return STRING]; alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING]; function to_ostring (value : UNRESOLVED_sfixed) return STRING; alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING]; function to_hstring (value : UNRESOLVED_sfixed) return STRING; alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING]; -- From string functions allow you to convert a string into a fixed -- point number. Example: -- signal uf1 : ufixed (3 downto -3); -- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5 -- The "." is optional in this syntax, however it exist and is -- in the wrong location an error is produced. Overflow will -- result in saturation. function from_string ( bstring : STRING; -- binary string constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_ufixed; alias from_bstring is from_string [STRING, INTEGER, INTEGER return UNRESOLVED_ufixed]; alias from_binary_string is from_string [STRING, INTEGER, INTEGER return UNRESOLVED_ufixed]; -- Octal and hex conversions work as follows: -- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped) -- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped) function from_ostring ( ostring : STRING; -- Octal string constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_ufixed; alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER return UNRESOLVED_ufixed]; function from_hstring ( hstring : STRING; -- hex string constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_ufixed; alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER return UNRESOLVED_ufixed]; function from_string ( bstring : STRING; -- binary string constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_sfixed; alias from_bstring is from_string [STRING, INTEGER, INTEGER return UNRESOLVED_sfixed]; alias from_binary_string is from_string [STRING, INTEGER, INTEGER return UNRESOLVED_sfixed]; function from_ostring ( ostring : STRING; -- Octal string constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_sfixed; alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER return UNRESOLVED_sfixed]; function from_hstring ( hstring : STRING; -- hex string constant left_index : INTEGER; constant right_index : INTEGER) return UNRESOLVED_sfixed; alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER return UNRESOLVED_sfixed]; -- Same as above, "size_res" is used for it's range only. function from_string ( bstring : STRING; -- binary string size_res : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; alias from_bstring is from_string [STRING, UNRESOLVED_ufixed return UNRESOLVED_ufixed]; alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed return UNRESOLVED_ufixed]; function from_ostring ( ostring : STRING; -- Octal string size_res : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed return UNRESOLVED_ufixed]; function from_hstring ( hstring : STRING; -- hex string size_res : UNRESOLVED_ufixed) return UNRESOLVED_ufixed; alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed return UNRESOLVED_ufixed]; function from_string ( bstring : STRING; -- binary string size_res : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; alias from_bstring is from_string [STRING, UNRESOLVED_sfixed return UNRESOLVED_sfixed]; alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed return UNRESOLVED_sfixed]; function from_ostring ( ostring : STRING; -- Octal string size_res : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed return UNRESOLVED_sfixed]; function from_hstring ( hstring : STRING; -- hex string size_res : UNRESOLVED_sfixed) return UNRESOLVED_sfixed; alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed return UNRESOLVED_sfixed]; -- Direct conversion functions. Example: -- signal uf1 : ufixed (3 downto -3); -- uf1 <= from_string ("0110.100"); -- 6.5 -- In this case the "." is not optional, and the size of -- the output must match exactly. function from_string ( bstring : STRING) -- binary string return UNRESOLVED_ufixed; alias from_bstring is from_string [STRING return UNRESOLVED_ufixed]; alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed]; -- Direct octal and hex conversion functions. In this case -- the string lengths must match. Example: -- signal sf1 := sfixed (5 downto -3); -- sf1 <= from_ostring ("71.4") -- -6.5 function from_ostring ( ostring : STRING) -- Octal string return UNRESOLVED_ufixed; alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed]; function from_hstring ( hstring : STRING) -- hex string return UNRESOLVED_ufixed; alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed]; function from_string ( bstring : STRING) -- binary string return UNRESOLVED_sfixed; alias from_bstring is from_string [STRING return UNRESOLVED_sfixed]; alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed]; function from_ostring ( ostring : STRING) -- Octal string return UNRESOLVED_sfixed; alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed]; function from_hstring ( hstring : STRING) -- hex string return UNRESOLVED_sfixed; alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed]; end package fixed_generic_pkg;