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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DAEHNybjrEVUsW26KmDoefrfpZYC2mlxFbx1SHzZcX0AiRoHuHGppjuKWGydRPNqx6mrGUYQpZJP D05ZfgcUEA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Sq0+l0Drt9crUlEJxPrFd51j/DuEEftS+Ff09ljkSvjbBo37NCXQOqfBXTcpg9K4OND5zi4ewbom rrNNw5lXHr5i2cYDam8JT+knINaFKNhmqbKo7pC6i69OJ71qAPm9JFUZSTNRX3ZdaoEs6WulsVx2 soq3gEdx6s1sAX1chjw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DAEHNybjrEVUsW26KmDoefrfpZYC2mlxFbx1SHzZcX0AiRoHuHGppjuKWGydRPNqx6mrGUYQpZJP D05ZfgcUEA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Sq0+l0Drt9crUlEJxPrFd51j/DuEEftS+Ff09ljkSvjbBo37NCXQOqfBXTcpg9K4OND5zi4ewbom rrNNw5lXHr5i2cYDam8JT+knINaFKNhmqbKo7pC6i69OJ71qAPm9JFUZSTNRX3ZdaoEs6WulsVx2 soq3gEdx6s1sAX1chjw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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-- William Fan -- 02/14/2011 -- Signed Counter RTL package sgncounter is component counter is port (j,k: in std_logic; out_bin: out std_logic); end component; end package; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.sgncounter.all; entity scounter is generic (N: integer := 4); port (clk: in std_logic; out_bin,out_gray: out std_logic_vector(N-1 downto 0)); end scounter; architecture sc of scounter is signal tmp1: std_logic_vector(N-1 downto 0); signal tmp2: integer <= N-1; function g2b (input,output: std_logic_vector) return std_logic_vector is begin output(N-1) <= input(N-1); gen: For i in tmp2'RANGE generate output(i-1) <= output(i) XOR input(i-1); end generate; end function; begin process (clk) begin if (clk'event and clk='1') then end if; end process; end architecture;
library IEEE; use IEEE.std_logic_1164.all; entity inv is port(inb: in STD_logic; outb: out STD_Logic); end inv; architecture structure of inv is begin outb <= not (inb); end structure; library IEEE; use IEEE.std_logic_1164.all; entity nand2 is port(a, b: in STD_logic; outb: out STD_Logic); end nand2; architecture structure of nand2 is begin outb <= not(a and b); end structure; library IEEE; use IEEE.std_logic_1164.all; entity nand3 is port(a, b, c: in STD_logic; outb: out STD_Logic); end nand3 ; architecture structure of nand3 is begin outb <= not(a and b and c); end structure; library IEEE; use IEEE.std_logic_1164.all; entity nand4 is port(a, b, c, d: in STD_logic; outb: out STD_Logic); end nand4 ; architecture structure of nand4 is begin outb <= not(a and b and c and d); end structure; library IEEE; use IEEE.std_logic_1164.all; entity nor2 is port(a, b: in STD_logic; outb: out STD_Logic); end nor2 ; architecture structure of nor2 is begin outb <= not(a or b); end structure; library IEEE; use IEEE.std_logic_1164.all; entity nor3 is port(a, b, c: in STD_logic; outb: out STD_Logic); end nor3 ; architecture structure of nor3 is begin outb <= not(a or b or c); end structure; library IEEE; use IEEE.std_logic_1164.all; entity xor2 is port(a, b: in STD_logic; outb: out STD_Logic); end xor2 ; architecture structure of xor2 is begin outb <= (a xor b); end structure; library IEEE; use IEEE.std_logic_1164.all; entity aoi12 is port(a, b, c: in STD_logic; outb: out STD_Logic); end aoi12 ; architecture structure of aoi12 is begin outb <= not(a or (b and c)); end structure; library IEEE; use IEEE.std_logic_1164.all; entity aoi22 is port(a, b, c, d: in STD_logic; outb: out STD_Logic); end aoi22 ; architecture structure of aoi22 is begin outb <= not((a and b) or (c and d)); end structure; library IEEE; use IEEE.std_logic_1164.all; entity oai12 is port(a, b, c: in STD_logic; outb: out STD_Logic); end oai12; architecture structure of oai12 is begin outb <= not(a and (b or c)); end structure; library IEEE; use IEEE.std_logic_1164.all; entity oai22 is port(a, b, c, d: in STD_logic; outb: out STD_Logic); end oai22; architecture structure of oai22 is begin outb <= not((a or b) and (c or d)); end structure; library IEEE; use IEEE.std_logic_1164.all; entity dff is port(d, gclk, rnot: in STD_logic; q: out STD_Logic); end dff; architecture structure of dff is begin start: process(gclk,rnot) begin if ( rising_edge(gclk) or rnot = '0') then if (rnot = '0') then q <= '0'; else q <= d; end if; end if; end process; end structure;
--Copyright (c) 2005 National Center For Atmospheric Research All rights reserved; LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; entity mux is port( add_bus_hi:in std_logic; add_bus_lo:in std_logic_vector(3 downto 0); data_bus:inout std_logic_vector(7 downto 0); clkin:in std_logic; -- 24 MHz psen:in std_logic; rd:in std_logic; wr:in std_logic; reset:in std_logic; data_bit:in std_logic; Hdata: in std_logic; Shadwor: in std_logic; load512:in std_logic; tasbase:in std_logic; ram_ce:out std_logic; ram_rd:out std_logic; ram_wr:out std_logic; tas:out std_logic; bitshift:inout std_logic; unld_shift:out std_logic; porta:out std_logic; out512:out std_logic; out512not:out std_logic; Hadvance: out std_logic; Hreset: out std_logic; PA1: out std_logic; PA2: out std_logic; PA3: out std_logic; oscdiv: out std_logic; debug:out std_logic); end mux; Architecture behavior of mux is signal sreset: std_logic:='0'; signal progtas : std_logic; signal tdiv : std_logic_vector(1 downto 0); signal tcnt: std_logic_vector(1 downto 0); signal clkdiv: std_logic_vector(2 downto 0); signal clkbit: std_logic; -- 4 MHz unsymetric signal clkdiv8: std_logic_vector(3 downto 0); signal clkdiv4: std_logic_vector(2 downto 0); signal bitclk: std_logic; -- 2 MHz symetric signal unldshift: std_logic; -- one pulse per 32 bitclk signal byteread: std_logic; signal data: std_logic_vector(7 downto 0); signal unld_state: std_logic; type state_value is (s0,s1,s2,s3); signal state: state_value; signal next_state: state_value; signal porta_int: std_logic; signal bitflag: std_logic; signal byteread_state: std_logic; signal house_data: std_logic_vector(15 downto 0):=X"0000"; signal shdwor: std_logic_vector(15 downto 0):=X"0000"; signal Hdata_old2: std_logic:='0'; signal Hdata_old1: std_logic:='0'; signal h_reset: std_logic:='0'; signal shdwor_old2: std_logic:='0'; signal shdwor_old1: std_logic:='0'; signal h_advance: std_logic:='0'; signal hread0: std_logic; signal hread1: std_logic; signal sread0: std_logic; signal sread1: std_logic; signal load_old2: std_logic:='0'; signal load_old1: std_logic:='0'; signal loadflag: std_logic:='0'; signal ushift_old2: std_logic:='0'; signal ushift_old1: std_logic:='0'; signal bread_old2: std_logic:='0'; signal bread_old1: std_logic:='0'; signal bitclk_old2: std_logic:='0'; signal bitclk_old1: std_logic:='0'; signal clkunld: std_logic_vector(2 downto 0):="000"; signal flagunld: std_logic:='0'; signal h_rstflag: std_logic:='0'; signal h_advflag: std_logic:='0'; signal hcnt: std_logic_vector(3 downto 0):="0000"; -- signal clk512: std_logic_vector(2 downto 0):="000"; -- signal flag512: std_logic:='0'; begin ram_ce <= add_bus_hi; ram_rd <= rd and psen; ram_wr <= wr; PA1 <= byteread_state; PA2 <= unld_state; PA3 <= porta_int; --0x000 progtas <= psen and add_bus_hi and not add_bus_lo(3) and not add_bus_lo(2) and not add_bus_lo(1) and not add_bus_lo(0) and not wr; --0x001 unldshift <= psen and add_bus_hi and not add_bus_lo(3) and not add_bus_lo(2) and not add_bus_lo(1) and add_bus_lo(0) and not wr; --0x010 byteread <= psen and add_bus_hi and not add_bus_lo(3) and not add_bus_lo(2) and add_bus_lo(1) and not add_bus_lo(0) and not rd; --0x011 debug <= psen and add_bus_hi and not add_bus_lo(3) and not add_bus_lo(2) and add_bus_lo(1) and add_bus_lo(0) and not wr; --0x100 sreset <= psen and add_bus_hi and not add_bus_lo(3) and add_bus_lo(2) and not add_bus_lo(1) and not add_bus_lo(0) and not wr; --0x101 h_reset <= psen and add_bus_hi and not add_bus_lo(3) and add_bus_lo(2) and not add_bus_lo(1) and add_bus_lo(0) and not wr; --0x110 h_advance <= psen and add_bus_hi and not add_bus_lo(3) and add_bus_lo(2) and add_bus_lo(1) and not add_bus_lo(0) and not wr; --0x111 hread0 <= psen and add_bus_hi and not add_bus_lo(3) and add_bus_lo(2) and add_bus_lo(1) and add_bus_lo(0) and not rd; --0x1000 hread1 <= psen and add_bus_hi and add_bus_lo(3) and not add_bus_lo(2) and not add_bus_lo(1) and not add_bus_lo(0) and not rd; --0x1001 sread0 <= psen and add_bus_hi and add_bus_lo(3) and not add_bus_lo(2) and not add_bus_lo(1) and add_bus_lo(0) and not rd; --0x1010 sread1 <= psen and add_bus_hi and add_bus_lo(3) and not add_bus_lo(2) and add_bus_lo(1) and not add_bus_lo(0) and not rd; unld_shift <= flagunld and not loadflag; out512 <= load512; out512not <= not load512; porta <= porta_int; Hreset <= not h_rstflag; Hadvance <= not h_advflag; grabsig: process(clkin,reset,sreset) begin if reset = '1' or sreset = '1' then unld_state <= '0'; byteread_state <= '0'; loadflag <= '0'; else if falling_edge(clkin) then ushift_old2 <= ushift_old1; ushift_old1 <= unldshift; bread_old2 <= bread_old1; bread_old1 <= byteread; load_old2 <= load_old1; load_old1 <= load512; if load_old2 = '1' and load_old1 = '0' then loadflag <= '1'; end if; if ushift_old1 = '1' and ushift_old2 = '0' then unld_state <= '1'; byteread_state <= byteread_state; elsif bread_old1 = '1' and bread_old2 = '0' then byteread_state <= '1'; unld_state <= '0'; loadflag <= '0'; elsif porta_int = '0' then byteread_state <= '0'; unld_state <= unld_state; else byteread_state <= byteread_state; unld_state <= unld_state; loadflag <= loadflag; end if; end if; end if; end process grabsig; databus: process(reset,sreset,clkin) begin if reset = '1' or sreset = '1' then tdiv(1 downto 0) <= "00"; hcnt(3 downto 0) <= "0000"; h_rstflag <= '0'; h_advflag <= '0'; elsif rising_edge(clkin) then Hdata_old2 <= Hdata_old1; Hdata_old1 <= Hdata; shdwor_old2 <= shdwor_old1; shdwor_old1 <= Shadwor; if h_rstflag = '1' then if hcnt = "1100" then --Hold reset to probe hcnt <= "0000"; h_rstflag <= '0'; else hcnt <= hcnt + 1; h_rstflag <= h_rstflag; end if; end if; if h_advflag = '1' then if hcnt = "1100" then --Hold advance to probe hcnt <= "0000"; h_advflag <= '0'; else hcnt <= hcnt + 1; h_advflag <= h_advflag; end if; end if; if h_reset = '1' then h_rstflag <= '1'; house_data <= X"0000"; elsif h_advance = '1' then h_advflag <= '1'; house_data <= X"0000"; elsif Hdata_old2 = '0' and Hdata_old1 = '1' then house_data <= house_data + 1; elsif shdwor_old2 = '0' and shdwor_old1 = '1' then shdwor <= shdwor + 1; elsif hread0 = '1' then data_bus(7 downto 0) <= house_data(7 downto 0); elsif hread1 = '1' then data_bus(7 downto 0) <= house_data(15 downto 8); elsif sread0 = '1' then data_bus(7 downto 0) <= shdwor(7 downto 0); shdwor(15 downto 0) <= X"0000"; elsif sread1 = '1' then data_bus(7 downto 0) <= shdwor(15 downto 8); elsif progtas = '1' then tdiv(1 downto 0) <= data_bus(1 downto 0); elsif byteread = '1' then data_bus(7 downto 0) <= data(7 downto 0); else data_bus(7 downto 0) <= "ZZZZZZZZ"; tdiv(1 downto 0) <= tdiv(1 downto 0); end if; end if; end process databus; clock1: process(clkin, reset, sreset) begin if reset = '1' or sreset = '1' then clkbit <= '0'; clkdiv(2 downto 0) <= "000"; bitshift <= '0'; else if rising_edge(clkin) then clkdiv <= clkdiv + 1; if clkdiv(2 downto 0) = "101" then --sets bitshift frequency clkbit <= '1'; clkdiv(2 downto 0) <= "000"; else clkbit <= '0'; end if; end if; if bitflag = '1' then bitshift <= bitclk; else bitshift <= '0'; end if; end if; end process clock1; clock2: process(clkbit, reset, sreset) begin if reset = '1' or sreset = '1' then bitclk <= '0'; else if rising_edge(clkbit)then if bitclk = '1' then bitclk <= '0'; else bitclk <= '1'; end if; end if; end if; end process clock2; unload: process(clkin,reset,sreset) begin if reset = '1' or sreset = '1' then state <= s0; else if falling_edge(clkin) then state <= next_state; end if; end if; end process unload; machine: process(clkin,reset,sreset) begin if reset = '1' or sreset = '1' then next_state <= s0; bitflag <= '0'; clkdiv8 <= "0000"; clkdiv4 <= "000"; porta_int <= '0'; flagunld <= '0'; clkunld(2 downto 0) <= "000"; elsif rising_edge(clkin) then bitclk_old2 <= bitclk_old1; bitclk_old1 <= bitclk; case state is when s0=> -- wait for unload bitflag <= '0'; if clkunld(2 downto 0) = "111" then clkunld(2 downto 0) <= "000"; flagunld <= '0'; next_state <= s1; elsif unld_state = '1' then next_state <= s0; flagunld <= '1'; clkunld <= clkunld + 1; else next_state <= s0; end if; when s1 => -- clock 8 bits if clkdiv8 = "1000" then porta_int <= '1'; next_state <= s2; elsif bitclk_old1 = '1' and bitclk_old2 = '0' then bitflag <= '1'; clkdiv8 <= clkdiv8 + 1; next_state <= s1; else bitflag <= bitflag; next_state <= s1; end if; when s2 => --wait for microp to read byte bitflag <= '0'; clkdiv8 <= "0000"; if byteread_state = '1' and porta_int = '1' then clkdiv4 <= clkdiv4 + 1; next_state <= s3; porta_int <= '0'; else next_state <= s2; end if; when s3 => bitflag <= '0'; if clkdiv4 = "100" then clkdiv4 <= "000"; next_state <= s0; -- go wait for unldshift else next_state <= s1; end if; end case; else next_state <= next_state; porta_int <= porta_int; clkdiv8 <= clkdiv8; clkdiv4 <= clkdiv4; flagunld <= flagunld; bitflag <= bitflag; end if; end process machine; shift_in: process(bitshift,reset) begin if reset = '1' then data <= "00000000"; elsif falling_edge(bitshift) then data <= data(6 downto 0) & data_bit; --shift data in -- data <= data_bit & data(7 downto 1); --shift data in end if; end process shift_in; tascnt: process(tasbase, reset, sreset) begin if reset = '1' or sreset = '1' then tcnt <= "00"; else if rising_edge(tasbase) then tcnt <= tcnt + 1; end if; end if; end process tascnt; airspeed: process(reset,tdiv,sreset) begin if reset = '1' or sreset = '1' then tas <= '0'; oscdiv <= '0'; else case tdiv(1 downto 0) is when "00" => tas <= tasbase; oscdiv <= '0'; when "01" => tas <= tasbase; oscdiv <= 'Z'; when others => oscdiv <= '0'; tas <= '0'; end case; end if; end process airspeed; end behavior;
-- Nancy Minderman -- [email protected] -- This file makes extensive use of Altera template structures. -- This file is the top-level file for lab 1 winter 2014 for version 12.1sp1 on Windows 7 -- A library clause declares a name as a library. It -- does not create the library; it simply forward declares -- it. library ieee; -- Commonly imported packages: -- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions use ieee.std_logic_1164.all; -- SIGNED and UNSIGNED types, and relevant functions use ieee.numeric_std.all; -- Basic sequential functions and concurrent procedures use ieee.VITAL_Primitives.all; use work.DE2_CONSTANTS.all; entity sdram_circular_buffer is port ( -- Input ports and 50 MHz Clock CLOCK_50 : in std_logic; CLOCK_27 : in std_logic; SW : in std_logic_vector(0 downto 0); KEY : in std_logic_vector(0 downto 0); -- SDRAM on board --DRAM_ADDR : out std_logic_vector (11 downto 0); DRAM_ADDR : out DE2_SDRAM_ADDR_BUS; DRAM_BA_0 : out std_logic; DRAM_BA_1 : out std_logic; DRAM_CAS_N : out std_logic; DRAM_CKE : out std_logic; DRAM_CLK : out std_logic; DRAM_CS_N : out std_logic; --DRAM_DQ : inout std_logic_vector (15 downto 0); DRAM_DQ : inout DE2_SDRAM_DATA_BUS; DRAM_LDQM : out std_logic; DRAM_UDQM : out std_logic; DRAM_RAS_N : out std_logic; DRAM_WE_N : out std_logic; --Audio Signals on board --From audio appnote AUD_ADCLRCK : inout std_logic; AUD_ADCDAT : in std_logic; AUD_DACLRCK : inout std_logic; AUD_DACDAT : out std_logic; AUD_XCK : out std_logic; AUD_BCLK : inout std_logic; -- Audio/Video Config I2C interface -- From audio appnote I2C_SCLK : out std_logic; I2C_SDAT : inout std_logic; -- SRAM on board SRAM_ADDR : out DE2_SRAM_ADDR_BUS; SRAM_DQ : inout DE2_SRAM_DATA_BUS; SRAM_WE_N : out std_logic; SRAM_OE_N : out std_logic; SRAM_UB_N : out std_logic; SRAM_LB_N : out std_logic; SRAM_CE_N : out std_logic ); end sdram_circular_buffer; architecture structure of sdram_circular_buffer is -- Declarations (optional) component niosII_system is port ( clk_clk : in std_logic := 'X'; -- clk reset_reset_n : in std_logic := 'X'; -- reset_n sdram_0_wire_addr : out DE2_SDRAM_ADDR_BUS; -- addr sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba sdram_0_wire_cas_n : out std_logic; -- cas_n sdram_0_wire_cke : out std_logic; -- cke sdram_0_wire_cs_n : out std_logic; -- cs_n sdram_0_wire_dq : inout DE2_SDRAM_DATA_BUS := (others => 'X'); -- dq sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm sdram_0_wire_ras_n : out std_logic; -- ras_n sdram_0_wire_we_n : out std_logic; -- we_n sram_0_external_interface_DQ : inout DE2_SRAM_DATA_BUS := (others => 'X'); -- DQ sram_0_external_interface_ADDR : out DE2_SRAM_ADDR_BUS; -- ADDR sram_0_external_interface_LB_N : out std_logic; -- LB_N sram_0_external_interface_UB_N : out std_logic; -- UB_N sram_0_external_interface_CE_N : out std_logic; -- CE_N sram_0_external_interface_OE_N : out std_logic; -- OE_N sram_0_external_interface_WE_N : out std_logic; -- WE_N clk_0_clk : in std_logic := 'X'; -- clk reset_0_reset_n : in std_logic := 'X'; -- reset_n audio_0_external_interface_ADCDAT : in std_logic := 'X'; -- ADCDAT audio_0_external_interface_ADCLRCK : in std_logic := 'X'; -- ADCLRCK audio_0_external_interface_BCLK : in std_logic := 'X'; -- BCLK audio_0_external_interface_DACDAT : out std_logic; -- DACDAT audio_0_external_interface_DACLRCK : in std_logic := 'X'; -- DACLRCK audio_and_video_config_0_external_interface_SDAT : inout std_logic := 'X'; -- SDAT audio_and_video_config_0_external_interface_SCLK : out std_logic; -- SCLK audio_clk_clk : out std_logic; dram_clk_clk : out std_logic -- clk ); end component niosII_system; -- These signals are for matching the provided IP core to -- The specific SDRAM chip in our system signal BA : std_logic_vector (1 downto 0); signal DQM : std_logic_vector (1 downto 0); begin DRAM_BA_1 <= BA(1); DRAM_BA_0 <= BA(0); DRAM_UDQM <= DQM(1); DRAM_LDQM <= DQM(0); -- Component Instantiation Statement (optional) u0 : component niosII_system port map ( clk_clk => CLOCK_50, reset_reset_n => KEY(0), sdram_0_wire_addr => DRAM_ADDR, sdram_0_wire_ba => BA, sdram_0_wire_cas_n => DRAM_CAS_N, sdram_0_wire_cke => DRAM_CKE, sdram_0_wire_cs_n => DRAM_CS_N, sdram_0_wire_dq => DRAM_DQ, sdram_0_wire_dqm => DQM, sdram_0_wire_ras_n => DRAM_RAS_N, sdram_0_wire_we_n => DRAM_WE_N, sram_0_external_interface_DQ => SRAM_DQ, sram_0_external_interface_ADDR => SRAM_ADDR, sram_0_external_interface_LB_N => SRAM_LB_N, sram_0_external_interface_UB_N => SRAM_UB_N, sram_0_external_interface_CE_N => SRAM_CE_N, sram_0_external_interface_OE_N => SRAM_OE_N, sram_0_external_interface_WE_N => SRAM_WE_N, clk_0_clk => CLOCK_27, reset_0_reset_n => KEY(0), audio_0_external_interface_ADCDAT => AUD_ADCDAT, audio_0_external_interface_ADCLRCK => AUD_ADCLRCK, audio_0_external_interface_BCLK => AUD_BCLK, audio_0_external_interface_DACDAT => AUD_DACDAT, audio_0_external_interface_DACLRCK => AUD_DACLRCK, audio_and_video_config_0_external_interface_SDAT => I2C_SDAT, audio_and_video_config_0_external_interface_SCLK => I2C_SCLK, audio_clk_clk => AUD_XCK, dram_clk_clk => DRAM_CLK ); end structure; library ieee; -- Commonly imported packages: -- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions use ieee.std_logic_1164.all; package DE2_CONSTANTS is type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic; type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic; type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic; type DE2_LED_GREEN is array(7 downto 0) of std_logic; type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic; type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic; end DE2_CONSTANTS;
------------------------------------------------------------------------------- -- Title : Parametrizable synchronous FIFO (Generic version) -- Project : Generics RAMs and FIFOs collection ------------------------------------------------------------------------------- -- File : generic_sync_fifo_std.vhd -- Author : Tomasz Wlostowski -- Company : CERN BE-CO-HT -- Created : 2011-01-25 -- Last update: 2013-11-14 -- Platform : -- Standard : VHDL'93 ------------------------------------------------------------------------------- -- Description: Single-clock FIFO. -- - configurable data width and size -- - configurable full/empty/almost full/almost empty/word count signals ------------------------------------------------------------------------------- -- Copyright (c) 2011 CERN ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2011-01-25 1.0 twlostow Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.genram_pkg.all; entity inferred_sync_fifo is generic ( g_data_width : natural; g_size : natural; g_show_ahead : boolean := false; -- Read-side flag selection g_with_empty : boolean := true; -- with empty flag g_with_full : boolean := true; -- with full flag g_with_almost_empty : boolean := false; g_with_almost_full : boolean := false; g_with_count : boolean := false; -- with words counter g_almost_empty_threshold : integer := 0; -- threshold for almost empty flag g_almost_full_threshold : integer := 0; -- threshold for almost full flag g_register_flag_outputs : boolean := true ); port ( rst_n_i : in std_logic := '1'; clk_i : in std_logic; d_i : in std_logic_vector(g_data_width-1 downto 0); we_i : in std_logic; q_o : out std_logic_vector(g_data_width-1 downto 0); rd_i : in std_logic; empty_o : out std_logic; full_o : out std_logic; almost_empty_o : out std_logic; almost_full_o : out std_logic; count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0) ); end inferred_sync_fifo; architecture syn of inferred_sync_fifo is constant c_pointer_width : integer := f_log2_size(g_size); signal rd_ptr, wr_ptr, wr_ptr_d0, rd_ptr_muxed : unsigned(c_pointer_width-1 downto 0); signal usedw : unsigned(c_pointer_width downto 0); signal full, empty : std_logic; signal q_int : std_logic_vector(g_data_width-1 downto 0); signal we_int, rd_int : std_logic; signal guard_bit : std_logic; signal q_reg, q_comb : std_logic_vector(g_data_width-1 downto 0); begin -- syn --assert g_show_ahead = false report "Show ahead mode not implemented (yet). Sorry" severity failure; we_int <= we_i and not full; rd_int <= rd_i and not empty; U_FIFO_Ram : generic_dpram generic map ( g_data_width => g_data_width, g_size => g_size, g_with_byte_enable => false, g_addr_conflict_resolution => "read_first", g_dual_clock => false) port map ( rst_n_i => rst_n_i, clka_i => clk_i, wea_i => we_int, aa_i => std_logic_vector(wr_ptr(c_pointer_width-1 downto 0)), da_i => d_i, clkb_i => '0', ab_i => std_logic_vector(rd_ptr_muxed(c_pointer_width-1 downto 0)), qb_o => q_comb); p_output_reg : process(clk_i) begin if rising_edge(clk_i) then if rd_int = '1' then q_reg <= q_comb; end if; end if; end process; process(rd_ptr, rd_i, rd_int) begin if(rd_int = '1' and g_show_ahead) then rd_ptr_muxed <= rd_ptr + 1; elsif((rd_int = '1' and not g_show_ahead) or (g_show_ahead)) then rd_ptr_muxed <= rd_ptr; else rd_ptr_muxed <= rd_ptr - 1; end if; end process; -- q_o <= q_comb when g_show_ahead = true else q_reg; q_o <= q_comb; p_pointers : process(clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then wr_ptr <= (others => '0'); rd_ptr <= (others => '0'); else if(we_int = '1') then wr_ptr <= wr_ptr + 1; end if; if(rd_int = '1') then rd_ptr <= rd_ptr + 1; end if; end if; end if; end process; gen_comb_flags_showahead : if(g_show_ahead = true) generate process(clk_i) begin if rising_edge(clk_i) then if ((rd_ptr + 1 = wr_ptr and rd_int = '1') or (rd_ptr = wr_ptr)) then empty <= '1'; else empty <= '0'; end if; end if; end process; full <= '1' when (wr_ptr + 1 = rd_ptr) else '0'; end generate gen_comb_flags_showahead; gen_comb_flags : if(g_register_flag_outputs = false and g_show_ahead = false) generate empty <= '1' when (wr_ptr = rd_ptr and guard_bit = '0') else '0'; full <= '1' when (wr_ptr = rd_ptr and guard_bit = '1') else '0'; p_guard_bit : process(clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then guard_bit <= '0'; elsif(wr_ptr + 1 = rd_ptr and we_int = '1') then guard_bit <= '1'; elsif(rd_i = '1') then guard_bit <= '0'; end if; end if; end process; end generate gen_comb_flags; gen_registered_flags : if(g_register_flag_outputs = true and g_show_ahead = false) generate p_reg_flags : process(clk_i) begin if rising_edge(clk_i) then if(rst_n_i = '0') then full <= '0'; empty <= '1'; else if(usedw = 1 and rd_int = '1' and we_int = '0') then empty <= '1'; elsif(we_int = '1' and rd_int = '0') then empty <= '0'; end if; if(usedw = g_size-2 and we_int = '1' and rd_int = '0') then full <= '1'; elsif(usedw = g_size-1 and rd_int = '1' and we_int = '0') then full <= '0'; end if; end if; end if; end process; end generate gen_registered_flags; gen_with_word_counter : if(g_with_count or g_with_almost_empty or g_with_almost_full or g_register_flag_outputs) generate p_usedw_counter : process(clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then usedw <= (others => '0'); else if(we_int = '1' and rd_int = '0') then usedw <= usedw + 1; elsif(we_int = '0' and rd_int = '1') then usedw <= usedw - 1; end if; end if; end if; end process; count_o <= std_logic_vector(usedw(c_pointer_width-1 downto 0)); end generate gen_with_word_counter; gen_with_almost_full : if(g_with_almost_full) generate process(clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then almost_full_o <= '0'; else if(usedw = g_almost_full_threshold-1) then if(we_int = '1' and rd_int = '0') then almost_full_o <= '1'; elsif(rd_int = '1' and we_int = '0') then almost_full_o <= '0'; end if; end if; end if; end if; end process; end generate gen_with_almost_full; gen_with_almost_empty : if(g_with_almost_empty) generate process(clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then almost_empty_o <= '1'; else if(usedw = g_almost_empty_threshold+1) then if(rd_int = '1' and we_int = '0') then almost_empty_o <= '1'; elsif(we_int = '1' and rd_int = '0') then almost_empty_o <= '0'; end if; end if; end if; end if; end process; end generate gen_with_almost_empty; full_o <= full; empty_o <= empty; end syn;
-- ----------------------------------------------------------------- -- -- Copyright 2019 IEEE P1076 WG Authors -- -- See the LICENSE file distributed with this work for copyright and -- licensing information and the AUTHORS file. -- -- This file to you under the Apache License, Version 2.0 (the "License"). -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -- implied. See the License for the specific language governing -- permissions and limitations under the License. -- -- Title : Standard multivalue logic package -- : (STD_LOGIC_1164 package body) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE model standards group (PAR 1164), -- : Accellera VHDL-TC, and IEEE P1076 Working Group -- : -- Purpose : This packages defines a standard for designers -- : to use in describing the interconnection data types -- : used in vhdl modeling. -- : -- Limitation: The logic system defined in this package may -- : be insufficient for modeling switched transistors, -- : since such a requirement is out of the scope of this -- : effort. Furthermore, mathematics, primitives, -- : timing standards, etc. are considered orthogonal -- : issues as it relates to this package and are therefore -- : beyond the scope of this effort. -- : -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- package body std_logic_1164 is ------------------------------------------------------------------- -- local types ------------------------------------------------------------------- type stdlogic_1d is array (STD_ULOGIC) of STD_ULOGIC; type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC; ------------------------------------------------------------------- -- resolution function ------------------------------------------------------------------- constant resolution_table : stdlogic_table := ( -- --------------------------------------------------------- -- | U X 0 1 Z W L H - | | -- --------------------------------------------------------- ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X | ('U', 'X', '0', 'X', '0', '0', '0', '0', 'X'), -- | 0 | ('U', 'X', 'X', '1', '1', '1', '1', '1', 'X'), -- | 1 | ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X'), -- | Z | ('U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X'), -- | W | ('U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X'), -- | L | ('U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X'), -- | H | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - | ); function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC is variable result : STD_ULOGIC := 'Z'; -- weakest state default begin -- the test for a single driver is essential otherwise the -- loop would return 'X' for a single driver of '-' and that -- would conflict with the value of a single driver unresolved -- signal. if (s'length = 1) then return s(s'low); else for i in s'range loop result := resolution_table(result, s(i)); end loop; end if; return result; end resolved; ------------------------------------------------------------------- -- tables for logical operations ------------------------------------------------------------------- -- truth table for "and" function constant and_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ('U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U'), -- | U | ('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | X | ('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | 0 | ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 1 | ('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | Z | ('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | W | ('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | L | ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | H | ('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X') -- | - | ); -- truth table for "or" function constant or_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ('U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U'), -- | U | ('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | X | ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 | ('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 | ('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | Z | ('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | W | ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L | ('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | H | ('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X') -- | - | ); -- truth table for "xor" function constant xor_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X | ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 | ('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | 1 | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W | ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L | ('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | H | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - | ); -- truth table for "not" function constant not_table : stdlogic_1d := -- ------------------------------------------------- -- | U X 0 1 Z W L H - | -- ------------------------------------------------- ('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'); ------------------------------------------------------------------- -- overloaded logical operators ( with optimizing hints ) ------------------------------------------------------------------- function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is begin return (and_table(l, r)); end "and"; function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is begin return (not_table (and_table(l, r))); end "nand"; function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is begin return (or_table(l, r)); end "or"; function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is begin return (not_table (or_table(l, r))); end "nor"; function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is begin return (xor_table(l, r)); end "xor"; --START-!V87 function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is begin return not_table(xor_table(l, r)); end "xnor"; --END-!V87 function "not" (l : STD_ULOGIC) return UX01 is begin return (not_table(l)); end "not"; ------------------------------------------------------------------- -- and ------------------------------------------------------------------- function "and" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias lv : STD_LOGIC_VECTOR (1 to l'length) is l; alias rv : STD_LOGIC_VECTOR (1 to r'length) is r; variable result : STD_LOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""and"": " & "arguments of overloaded 'and' operator are not of the same length" severity failure; else for i in result'range loop result(i) := and_table (lv(i), rv(i)); end loop; end if; return result; end "and"; function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; variable result : STD_ULOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""and"": " & "arguments of overloaded 'and' operator are not of the same length" severity failure; else for i in result'range loop result(i) := and_table (lv(i), rv(i)); end loop; end if; return result; end "and"; ------------------------------------------------------------------- -- nand ------------------------------------------------------------------- function "nand" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias lv : STD_LOGIC_VECTOR (1 to l'length) is l; alias rv : STD_LOGIC_VECTOR (1 to r'length) is r; variable result : STD_LOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""nand"": " & "arguments of overloaded 'nand' operator are not of the same length" severity failure; else for i in result'range loop result(i) := not_table(and_table (lv(i), rv(i))); end loop; end if; return result; end "nand"; function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; variable result : STD_ULOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""nand"": " & "arguments of overloaded 'nand' operator are not of the same length" severity failure; else for i in result'range loop result(i) := not_table(and_table (lv(i), rv(i))); end loop; end if; return result; end "nand"; ------------------------------------------------------------------- -- or ------------------------------------------------------------------- function "or" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias lv : STD_LOGIC_VECTOR (1 to l'length) is l; alias rv : STD_LOGIC_VECTOR (1 to r'length) is r; variable result : STD_LOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""or"": " & "arguments of overloaded 'or' operator are not of the same length" severity failure; else for i in result'range loop result(i) := or_table (lv(i), rv(i)); end loop; end if; return result; end "or"; function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; variable result : STD_ULOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""or"": " & "arguments of overloaded 'or' operator are not of the same length" severity failure; else for i in result'range loop result(i) := or_table (lv(i), rv(i)); end loop; end if; return result; end "or"; ------------------------------------------------------------------- -- nor ------------------------------------------------------------------- function "nor" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias lv : STD_LOGIC_VECTOR (1 to l'length) is l; alias rv : STD_LOGIC_VECTOR (1 to r'length) is r; variable result : STD_LOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""nor"": " & "arguments of overloaded 'nor' operator are not of the same length" severity failure; else for i in result'range loop result(i) := not_table(or_table (lv(i), rv(i))); end loop; end if; return result; end "nor"; function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; variable result : STD_ULOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""nor"": " & "arguments of overloaded 'nor' operator are not of the same length" severity failure; else for i in result'range loop result(i) := not_table(or_table (lv(i), rv(i))); end loop; end if; return result; end "nor"; --------------------------------------------------------------------- -- xor ------------------------------------------------------------------- function "xor" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias lv : STD_LOGIC_VECTOR (1 to l'length) is l; alias rv : STD_LOGIC_VECTOR (1 to r'length) is r; variable result : STD_LOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""xor"": " & "arguments of overloaded 'xor' operator are not of the same length" severity failure; else for i in result'range loop result(i) := xor_table (lv(i), rv(i)); end loop; end if; return result; end "xor"; function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; variable result : STD_ULOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""xor"": " & "arguments of overloaded 'xor' operator are not of the same length" severity failure; else for i in result'range loop result(i) := xor_table (lv(i), rv(i)); end loop; end if; return result; end "xor"; ------------------------------------------------------------------- -- xnor ------------------------------------------------------------------- --START-!V87 function "xnor" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias lv : STD_LOGIC_VECTOR (1 to l'length) is l; alias rv : STD_LOGIC_VECTOR (1 to r'length) is r; variable result : STD_LOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""xnor"": " & "arguments of overloaded 'xnor' operator are not of the same length" severity failure; else for i in result'range loop result(i) := not_table(xor_table (lv(i), rv(i))); end loop; end if; return result; end "xnor"; function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; variable result : STD_ULOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""xnor"": " & "arguments of overloaded 'xnor' operator are not of the same length" severity failure; else for i in result'range loop result(i) := not_table(xor_table (lv(i), rv(i))); end loop; end if; return result; end "xnor"; --END-!V87 ------------------------------------------------------------------- -- not ------------------------------------------------------------------- function "not" (l : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias lv : STD_LOGIC_VECTOR (1 to l'length) is l; variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => 'X'); begin for i in result'range loop result(i) := not_table(lv(i)); end loop; return result; end "not"; function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => 'X'); begin for i in result'range loop result(i) := not_table(lv(i)); end loop; return result; end "not"; ------------------------------------------------------------------- -- conversion tables ------------------------------------------------------------------- type logic_x01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01; type logic_x01z_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01Z; type logic_ux01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of UX01; ---------------------------------------------------------- -- table name : cvt_to_x01 -- -- parameters : -- in : std_ulogic -- some logic value -- returns : x01 -- state value of logic value -- purpose : to convert state-strength to state only -- -- example : if (cvt_to_x01 (input_signal) = '1' ) then ... -- ---------------------------------------------------------- constant cvt_to_x01 : logic_x01_table := ( 'X', -- 'U' 'X', -- 'X' '0', -- '0' '1', -- '1' 'X', -- 'Z' 'X', -- 'W' '0', -- 'L' '1', -- 'H' 'X' -- '-' ); ---------------------------------------------------------- -- table name : cvt_to_x01z -- -- parameters : -- in : std_ulogic -- some logic value -- returns : x01z -- state value of logic value -- purpose : to convert state-strength to state only -- -- example : if (cvt_to_x01z (input_signal) = '1' ) then ... -- ---------------------------------------------------------- constant cvt_to_x01z : logic_x01z_table := ( 'X', -- 'U' 'X', -- 'X' '0', -- '0' '1', -- '1' 'Z', -- 'Z' 'X', -- 'W' '0', -- 'L' '1', -- 'H' 'X' -- '-' ); ---------------------------------------------------------- -- table name : cvt_to_ux01 -- -- parameters : -- in : std_ulogic -- some logic value -- returns : ux01 -- state value of logic value -- purpose : to convert state-strength to state only -- -- example : if (cvt_to_ux01 (input_signal) = '1' ) then ... -- ---------------------------------------------------------- constant cvt_to_ux01 : logic_ux01_table := ( 'U', -- 'U' 'X', -- 'X' '0', -- '0' '1', -- '1' 'X', -- 'Z' 'X', -- 'W' '0', -- 'L' '1', -- 'H' 'X' -- '-' ); ------------------------------------------------------------------- -- conversion functions ------------------------------------------------------------------- function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT is begin case s is when '0' | 'L' => return ('0'); when '1' | 'H' => return ('1'); when others => return xmap; end case; end To_bit; -------------------------------------------------------------------- function To_bitvector (s : STD_LOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR is alias sv : STD_LOGIC_VECTOR (s'length-1 downto 0) is s; variable result : BIT_VECTOR (s'length-1 downto 0); begin for i in result'range loop case sv(i) is when '0' | 'L' => result(i) := '0'; when '1' | 'H' => result(i) := '1'; when others => result(i) := xmap; end case; end loop; return result; end To_bitvector; function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR is alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s; variable result : BIT_VECTOR (s'length-1 downto 0); begin for i in result'range loop case sv(i) is when '0' | 'L' => result(i) := '0'; when '1' | 'H' => result(i) := '1'; when others => result(i) := xmap; end case; end loop; return result; end To_bitvector; -------------------------------------------------------------------- function To_StdULogic (b : BIT) return STD_ULOGIC is begin case b is when '0' => return '0'; when '1' => return '1'; end case; end To_StdULogic; -------------------------------------------------------------------- function To_StdLogicVector (b : BIT_VECTOR) return STD_LOGIC_VECTOR is alias bv : BIT_VECTOR (b'length-1 downto 0) is b; variable result : STD_LOGIC_VECTOR (b'length-1 downto 0); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_StdLogicVector; -------------------------------------------------------------------- function To_StdLogicVector (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s; variable result : STD_LOGIC_VECTOR (s'length-1 downto 0); begin for i in result'range loop result(i) := sv(i); end loop; return result; end To_StdLogicVector; -------------------------------------------------------------------- function To_StdULogicVector (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is alias bv : BIT_VECTOR (b'length-1 downto 0) is b; variable result : STD_ULOGIC_VECTOR (b'length-1 downto 0); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_StdULogicVector; -------------------------------------------------------------------- function To_StdULogicVector (s : STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias sv : STD_LOGIC_VECTOR (s'length-1 downto 0) is s; variable result : STD_ULOGIC_VECTOR (s'length-1 downto 0); begin for i in result'range loop result(i) := sv(i); end loop; return result; end To_StdULogicVector; ------------------------------------------------------------------- -- strength strippers and type convertors ------------------------------------------------------------------- ------------------------------------------------------------------- -- to_x01 ------------------------------------------------------------------- function To_X01 (s : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias sv : STD_LOGIC_VECTOR (1 to s'length) is s; variable result : STD_LOGIC_VECTOR (1 to s'length); begin for i in result'range loop result(i) := cvt_to_x01 (sv(i)); end loop; return result; end To_X01; function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s; variable result : STD_ULOGIC_VECTOR (1 to s'length); begin for i in result'range loop result(i) := cvt_to_x01 (sv(i)); end loop; return result; end To_X01; -------------------------------------------------------------------- function To_X01 (s : STD_ULOGIC) return X01 is begin return (cvt_to_x01(s)); end To_X01; -------------------------------------------------------------------- function To_X01 (b : BIT_VECTOR) return STD_LOGIC_VECTOR is alias bv : BIT_VECTOR (1 to b'length) is b; variable result : STD_LOGIC_VECTOR (1 to b'length); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_X01; function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is alias bv : BIT_VECTOR (1 to b'length) is b; variable result : STD_ULOGIC_VECTOR (1 to b'length); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_X01; -------------------------------------------------------------------- function To_X01 (b : BIT) return X01 is begin case b is when '0' => return('0'); when '1' => return('1'); end case; end To_X01; -------------------------------------------------------------------- -- to_x01z ------------------------------------------------------------------- function To_X01Z (s : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias sv : STD_LOGIC_VECTOR (1 to s'length) is s; variable result : STD_LOGIC_VECTOR (1 to s'length); begin for i in result'range loop result(i) := cvt_to_x01z (sv(i)); end loop; return result; end To_X01Z; function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s; variable result : STD_ULOGIC_VECTOR (1 to s'length); begin for i in result'range loop result(i) := cvt_to_x01z (sv(i)); end loop; return result; end To_X01Z; -------------------------------------------------------------------- function To_X01Z (s : STD_ULOGIC) return X01Z is begin return (cvt_to_x01z(s)); end To_X01Z; -------------------------------------------------------------------- function To_X01Z (b : BIT_VECTOR) return STD_LOGIC_VECTOR is alias bv : BIT_VECTOR (1 to b'length) is b; variable result : STD_LOGIC_VECTOR (1 to b'length); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_X01Z; function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is alias bv : BIT_VECTOR (1 to b'length) is b; variable result : STD_ULOGIC_VECTOR (1 to b'length); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_X01Z; -------------------------------------------------------------------- function To_X01Z (b : BIT) return X01Z is begin case b is when '0' => return('0'); when '1' => return('1'); end case; end To_X01Z; -------------------------------------------------------------------- -- to_ux01 ------------------------------------------------------------------- function To_UX01 (s : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias sv : STD_LOGIC_VECTOR (1 to s'length) is s; variable result : STD_LOGIC_VECTOR (1 to s'length); begin for i in result'range loop result(i) := cvt_to_ux01 (sv(i)); end loop; return result; end To_UX01; function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s; variable result : STD_ULOGIC_VECTOR (1 to s'length); begin for i in result'range loop result(i) := cvt_to_ux01 (sv(i)); end loop; return result; end To_UX01; -------------------------------------------------------------------- function To_UX01 (s : STD_ULOGIC) return UX01 is begin return (cvt_to_ux01(s)); end To_UX01; -------------------------------------------------------------------- function To_UX01 (b : BIT_VECTOR) return STD_LOGIC_VECTOR is alias bv : BIT_VECTOR (1 to b'length) is b; variable result : STD_LOGIC_VECTOR (1 to b'length); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_UX01; function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is alias bv : BIT_VECTOR (1 to b'length) is b; variable result : STD_ULOGIC_VECTOR (1 to b'length); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_UX01; -------------------------------------------------------------------- function To_UX01 (b : BIT) return UX01 is begin case b is when '0' => return('0'); when '1' => return('1'); end case; end To_UX01; ------------------------------------------------------------------- -- edge detection ------------------------------------------------------------------- function rising_edge (signal s : STD_ULOGIC) return BOOLEAN is begin return (s'event and (To_X01(s) = '1') and (To_X01(s'last_value) = '0')); end rising_edge; function falling_edge (signal s : STD_ULOGIC) return BOOLEAN is begin return (s'event and (To_X01(s) = '0') and (To_X01(s'last_value) = '1')); end falling_edge; ------------------------------------------------------------------- -- object contains an unknown ------------------------------------------------------------------- function Is_X (s : STD_LOGIC_VECTOR) return BOOLEAN is begin for i in s'range loop case s(i) is when 'U' | 'X' | 'Z' | 'W' | '-' => return true; when others => null; end case; end loop; return false; end Is_X; function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN is begin for i in s'range loop case s(i) is when 'U' | 'X' | 'Z' | 'W' | '-' => return true; when others => null; end case; end loop; return false; end Is_X; -------------------------------------------------------------------- function Is_X (s : STD_ULOGIC) return BOOLEAN is begin case s is when 'U' | 'X' | 'Z' | 'W' | '-' => return true; when others => null; end case; return false; end Is_X; end std_logic_1164;
-- ----------------------------------------------------------------- -- -- Copyright 2019 IEEE P1076 WG Authors -- -- See the LICENSE file distributed with this work for copyright and -- licensing information and the AUTHORS file. -- -- This file to you under the Apache License, Version 2.0 (the "License"). -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -- implied. See the License for the specific language governing -- permissions and limitations under the License. -- -- Title : Standard multivalue logic package -- : (STD_LOGIC_1164 package body) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE model standards group (PAR 1164), -- : Accellera VHDL-TC, and IEEE P1076 Working Group -- : -- Purpose : This packages defines a standard for designers -- : to use in describing the interconnection data types -- : used in vhdl modeling. -- : -- Limitation: The logic system defined in this package may -- : be insufficient for modeling switched transistors, -- : since such a requirement is out of the scope of this -- : effort. Furthermore, mathematics, primitives, -- : timing standards, etc. are considered orthogonal -- : issues as it relates to this package and are therefore -- : beyond the scope of this effort. -- : -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- package body std_logic_1164 is ------------------------------------------------------------------- -- local types ------------------------------------------------------------------- type stdlogic_1d is array (STD_ULOGIC) of STD_ULOGIC; type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC; ------------------------------------------------------------------- -- resolution function ------------------------------------------------------------------- constant resolution_table : stdlogic_table := ( -- --------------------------------------------------------- -- | U X 0 1 Z W L H - | | -- --------------------------------------------------------- ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X | ('U', 'X', '0', 'X', '0', '0', '0', '0', 'X'), -- | 0 | ('U', 'X', 'X', '1', '1', '1', '1', '1', 'X'), -- | 1 | ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X'), -- | Z | ('U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X'), -- | W | ('U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X'), -- | L | ('U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X'), -- | H | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - | ); function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC is variable result : STD_ULOGIC := 'Z'; -- weakest state default begin -- the test for a single driver is essential otherwise the -- loop would return 'X' for a single driver of '-' and that -- would conflict with the value of a single driver unresolved -- signal. if (s'length = 1) then return s(s'low); else for i in s'range loop result := resolution_table(result, s(i)); end loop; end if; return result; end resolved; ------------------------------------------------------------------- -- tables for logical operations ------------------------------------------------------------------- -- truth table for "and" function constant and_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ('U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U'), -- | U | ('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | X | ('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | 0 | ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 1 | ('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | Z | ('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | W | ('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | L | ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | H | ('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X') -- | - | ); -- truth table for "or" function constant or_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ('U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U'), -- | U | ('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | X | ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 | ('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 | ('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | Z | ('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | W | ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L | ('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | H | ('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X') -- | - | ); -- truth table for "xor" function constant xor_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X | ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 | ('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | 1 | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W | ('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L | ('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | H | ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - | ); -- truth table for "not" function constant not_table : stdlogic_1d := -- ------------------------------------------------- -- | U X 0 1 Z W L H - | -- ------------------------------------------------- ('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'); ------------------------------------------------------------------- -- overloaded logical operators ( with optimizing hints ) ------------------------------------------------------------------- function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is begin return (and_table(l, r)); end "and"; function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is begin return (not_table (and_table(l, r))); end "nand"; function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is begin return (or_table(l, r)); end "or"; function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is begin return (not_table (or_table(l, r))); end "nor"; function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is begin return (xor_table(l, r)); end "xor"; --START-!V87 function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is begin return not_table(xor_table(l, r)); end "xnor"; --END-!V87 function "not" (l : STD_ULOGIC) return UX01 is begin return (not_table(l)); end "not"; ------------------------------------------------------------------- -- and ------------------------------------------------------------------- function "and" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias lv : STD_LOGIC_VECTOR (1 to l'length) is l; alias rv : STD_LOGIC_VECTOR (1 to r'length) is r; variable result : STD_LOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""and"": " & "arguments of overloaded 'and' operator are not of the same length" severity failure; else for i in result'range loop result(i) := and_table (lv(i), rv(i)); end loop; end if; return result; end "and"; function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; variable result : STD_ULOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""and"": " & "arguments of overloaded 'and' operator are not of the same length" severity failure; else for i in result'range loop result(i) := and_table (lv(i), rv(i)); end loop; end if; return result; end "and"; ------------------------------------------------------------------- -- nand ------------------------------------------------------------------- function "nand" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias lv : STD_LOGIC_VECTOR (1 to l'length) is l; alias rv : STD_LOGIC_VECTOR (1 to r'length) is r; variable result : STD_LOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""nand"": " & "arguments of overloaded 'nand' operator are not of the same length" severity failure; else for i in result'range loop result(i) := not_table(and_table (lv(i), rv(i))); end loop; end if; return result; end "nand"; function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; variable result : STD_ULOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""nand"": " & "arguments of overloaded 'nand' operator are not of the same length" severity failure; else for i in result'range loop result(i) := not_table(and_table (lv(i), rv(i))); end loop; end if; return result; end "nand"; ------------------------------------------------------------------- -- or ------------------------------------------------------------------- function "or" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias lv : STD_LOGIC_VECTOR (1 to l'length) is l; alias rv : STD_LOGIC_VECTOR (1 to r'length) is r; variable result : STD_LOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""or"": " & "arguments of overloaded 'or' operator are not of the same length" severity failure; else for i in result'range loop result(i) := or_table (lv(i), rv(i)); end loop; end if; return result; end "or"; function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; variable result : STD_ULOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""or"": " & "arguments of overloaded 'or' operator are not of the same length" severity failure; else for i in result'range loop result(i) := or_table (lv(i), rv(i)); end loop; end if; return result; end "or"; ------------------------------------------------------------------- -- nor ------------------------------------------------------------------- function "nor" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias lv : STD_LOGIC_VECTOR (1 to l'length) is l; alias rv : STD_LOGIC_VECTOR (1 to r'length) is r; variable result : STD_LOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""nor"": " & "arguments of overloaded 'nor' operator are not of the same length" severity failure; else for i in result'range loop result(i) := not_table(or_table (lv(i), rv(i))); end loop; end if; return result; end "nor"; function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; variable result : STD_ULOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""nor"": " & "arguments of overloaded 'nor' operator are not of the same length" severity failure; else for i in result'range loop result(i) := not_table(or_table (lv(i), rv(i))); end loop; end if; return result; end "nor"; --------------------------------------------------------------------- -- xor ------------------------------------------------------------------- function "xor" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias lv : STD_LOGIC_VECTOR (1 to l'length) is l; alias rv : STD_LOGIC_VECTOR (1 to r'length) is r; variable result : STD_LOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""xor"": " & "arguments of overloaded 'xor' operator are not of the same length" severity failure; else for i in result'range loop result(i) := xor_table (lv(i), rv(i)); end loop; end if; return result; end "xor"; function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; variable result : STD_ULOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""xor"": " & "arguments of overloaded 'xor' operator are not of the same length" severity failure; else for i in result'range loop result(i) := xor_table (lv(i), rv(i)); end loop; end if; return result; end "xor"; ------------------------------------------------------------------- -- xnor ------------------------------------------------------------------- --START-!V87 function "xnor" (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias lv : STD_LOGIC_VECTOR (1 to l'length) is l; alias rv : STD_LOGIC_VECTOR (1 to r'length) is r; variable result : STD_LOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""xnor"": " & "arguments of overloaded 'xnor' operator are not of the same length" severity failure; else for i in result'range loop result(i) := not_table(xor_table (lv(i), rv(i))); end loop; end if; return result; end "xnor"; function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r; variable result : STD_ULOGIC_VECTOR (1 to l'length); begin if (l'length /= r'length) then assert false report "STD_LOGIC_1164.""xnor"": " & "arguments of overloaded 'xnor' operator are not of the same length" severity failure; else for i in result'range loop result(i) := not_table(xor_table (lv(i), rv(i))); end loop; end if; return result; end "xnor"; --END-!V87 ------------------------------------------------------------------- -- not ------------------------------------------------------------------- function "not" (l : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias lv : STD_LOGIC_VECTOR (1 to l'length) is l; variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => 'X'); begin for i in result'range loop result(i) := not_table(lv(i)); end loop; return result; end "not"; function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l; variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => 'X'); begin for i in result'range loop result(i) := not_table(lv(i)); end loop; return result; end "not"; ------------------------------------------------------------------- -- conversion tables ------------------------------------------------------------------- type logic_x01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01; type logic_x01z_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01Z; type logic_ux01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of UX01; ---------------------------------------------------------- -- table name : cvt_to_x01 -- -- parameters : -- in : std_ulogic -- some logic value -- returns : x01 -- state value of logic value -- purpose : to convert state-strength to state only -- -- example : if (cvt_to_x01 (input_signal) = '1' ) then ... -- ---------------------------------------------------------- constant cvt_to_x01 : logic_x01_table := ( 'X', -- 'U' 'X', -- 'X' '0', -- '0' '1', -- '1' 'X', -- 'Z' 'X', -- 'W' '0', -- 'L' '1', -- 'H' 'X' -- '-' ); ---------------------------------------------------------- -- table name : cvt_to_x01z -- -- parameters : -- in : std_ulogic -- some logic value -- returns : x01z -- state value of logic value -- purpose : to convert state-strength to state only -- -- example : if (cvt_to_x01z (input_signal) = '1' ) then ... -- ---------------------------------------------------------- constant cvt_to_x01z : logic_x01z_table := ( 'X', -- 'U' 'X', -- 'X' '0', -- '0' '1', -- '1' 'Z', -- 'Z' 'X', -- 'W' '0', -- 'L' '1', -- 'H' 'X' -- '-' ); ---------------------------------------------------------- -- table name : cvt_to_ux01 -- -- parameters : -- in : std_ulogic -- some logic value -- returns : ux01 -- state value of logic value -- purpose : to convert state-strength to state only -- -- example : if (cvt_to_ux01 (input_signal) = '1' ) then ... -- ---------------------------------------------------------- constant cvt_to_ux01 : logic_ux01_table := ( 'U', -- 'U' 'X', -- 'X' '0', -- '0' '1', -- '1' 'X', -- 'Z' 'X', -- 'W' '0', -- 'L' '1', -- 'H' 'X' -- '-' ); ------------------------------------------------------------------- -- conversion functions ------------------------------------------------------------------- function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT is begin case s is when '0' | 'L' => return ('0'); when '1' | 'H' => return ('1'); when others => return xmap; end case; end To_bit; -------------------------------------------------------------------- function To_bitvector (s : STD_LOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR is alias sv : STD_LOGIC_VECTOR (s'length-1 downto 0) is s; variable result : BIT_VECTOR (s'length-1 downto 0); begin for i in result'range loop case sv(i) is when '0' | 'L' => result(i) := '0'; when '1' | 'H' => result(i) := '1'; when others => result(i) := xmap; end case; end loop; return result; end To_bitvector; function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR is alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s; variable result : BIT_VECTOR (s'length-1 downto 0); begin for i in result'range loop case sv(i) is when '0' | 'L' => result(i) := '0'; when '1' | 'H' => result(i) := '1'; when others => result(i) := xmap; end case; end loop; return result; end To_bitvector; -------------------------------------------------------------------- function To_StdULogic (b : BIT) return STD_ULOGIC is begin case b is when '0' => return '0'; when '1' => return '1'; end case; end To_StdULogic; -------------------------------------------------------------------- function To_StdLogicVector (b : BIT_VECTOR) return STD_LOGIC_VECTOR is alias bv : BIT_VECTOR (b'length-1 downto 0) is b; variable result : STD_LOGIC_VECTOR (b'length-1 downto 0); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_StdLogicVector; -------------------------------------------------------------------- function To_StdLogicVector (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR is alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s; variable result : STD_LOGIC_VECTOR (s'length-1 downto 0); begin for i in result'range loop result(i) := sv(i); end loop; return result; end To_StdLogicVector; -------------------------------------------------------------------- function To_StdULogicVector (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is alias bv : BIT_VECTOR (b'length-1 downto 0) is b; variable result : STD_ULOGIC_VECTOR (b'length-1 downto 0); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_StdULogicVector; -------------------------------------------------------------------- function To_StdULogicVector (s : STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias sv : STD_LOGIC_VECTOR (s'length-1 downto 0) is s; variable result : STD_ULOGIC_VECTOR (s'length-1 downto 0); begin for i in result'range loop result(i) := sv(i); end loop; return result; end To_StdULogicVector; ------------------------------------------------------------------- -- strength strippers and type convertors ------------------------------------------------------------------- ------------------------------------------------------------------- -- to_x01 ------------------------------------------------------------------- function To_X01 (s : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias sv : STD_LOGIC_VECTOR (1 to s'length) is s; variable result : STD_LOGIC_VECTOR (1 to s'length); begin for i in result'range loop result(i) := cvt_to_x01 (sv(i)); end loop; return result; end To_X01; function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s; variable result : STD_ULOGIC_VECTOR (1 to s'length); begin for i in result'range loop result(i) := cvt_to_x01 (sv(i)); end loop; return result; end To_X01; -------------------------------------------------------------------- function To_X01 (s : STD_ULOGIC) return X01 is begin return (cvt_to_x01(s)); end To_X01; -------------------------------------------------------------------- function To_X01 (b : BIT_VECTOR) return STD_LOGIC_VECTOR is alias bv : BIT_VECTOR (1 to b'length) is b; variable result : STD_LOGIC_VECTOR (1 to b'length); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_X01; function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is alias bv : BIT_VECTOR (1 to b'length) is b; variable result : STD_ULOGIC_VECTOR (1 to b'length); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_X01; -------------------------------------------------------------------- function To_X01 (b : BIT) return X01 is begin case b is when '0' => return('0'); when '1' => return('1'); end case; end To_X01; -------------------------------------------------------------------- -- to_x01z ------------------------------------------------------------------- function To_X01Z (s : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias sv : STD_LOGIC_VECTOR (1 to s'length) is s; variable result : STD_LOGIC_VECTOR (1 to s'length); begin for i in result'range loop result(i) := cvt_to_x01z (sv(i)); end loop; return result; end To_X01Z; function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s; variable result : STD_ULOGIC_VECTOR (1 to s'length); begin for i in result'range loop result(i) := cvt_to_x01z (sv(i)); end loop; return result; end To_X01Z; -------------------------------------------------------------------- function To_X01Z (s : STD_ULOGIC) return X01Z is begin return (cvt_to_x01z(s)); end To_X01Z; -------------------------------------------------------------------- function To_X01Z (b : BIT_VECTOR) return STD_LOGIC_VECTOR is alias bv : BIT_VECTOR (1 to b'length) is b; variable result : STD_LOGIC_VECTOR (1 to b'length); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_X01Z; function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is alias bv : BIT_VECTOR (1 to b'length) is b; variable result : STD_ULOGIC_VECTOR (1 to b'length); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_X01Z; -------------------------------------------------------------------- function To_X01Z (b : BIT) return X01Z is begin case b is when '0' => return('0'); when '1' => return('1'); end case; end To_X01Z; -------------------------------------------------------------------- -- to_ux01 ------------------------------------------------------------------- function To_UX01 (s : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is alias sv : STD_LOGIC_VECTOR (1 to s'length) is s; variable result : STD_LOGIC_VECTOR (1 to s'length); begin for i in result'range loop result(i) := cvt_to_ux01 (sv(i)); end loop; return result; end To_UX01; function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s; variable result : STD_ULOGIC_VECTOR (1 to s'length); begin for i in result'range loop result(i) := cvt_to_ux01 (sv(i)); end loop; return result; end To_UX01; -------------------------------------------------------------------- function To_UX01 (s : STD_ULOGIC) return UX01 is begin return (cvt_to_ux01(s)); end To_UX01; -------------------------------------------------------------------- function To_UX01 (b : BIT_VECTOR) return STD_LOGIC_VECTOR is alias bv : BIT_VECTOR (1 to b'length) is b; variable result : STD_LOGIC_VECTOR (1 to b'length); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_UX01; function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is alias bv : BIT_VECTOR (1 to b'length) is b; variable result : STD_ULOGIC_VECTOR (1 to b'length); begin for i in result'range loop case bv(i) is when '0' => result(i) := '0'; when '1' => result(i) := '1'; end case; end loop; return result; end To_UX01; -------------------------------------------------------------------- function To_UX01 (b : BIT) return UX01 is begin case b is when '0' => return('0'); when '1' => return('1'); end case; end To_UX01; ------------------------------------------------------------------- -- edge detection ------------------------------------------------------------------- function rising_edge (signal s : STD_ULOGIC) return BOOLEAN is begin return (s'event and (To_X01(s) = '1') and (To_X01(s'last_value) = '0')); end rising_edge; function falling_edge (signal s : STD_ULOGIC) return BOOLEAN is begin return (s'event and (To_X01(s) = '0') and (To_X01(s'last_value) = '1')); end falling_edge; ------------------------------------------------------------------- -- object contains an unknown ------------------------------------------------------------------- function Is_X (s : STD_LOGIC_VECTOR) return BOOLEAN is begin for i in s'range loop case s(i) is when 'U' | 'X' | 'Z' | 'W' | '-' => return true; when others => null; end case; end loop; return false; end Is_X; function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN is begin for i in s'range loop case s(i) is when 'U' | 'X' | 'Z' | 'W' | '-' => return true; when others => null; end case; end loop; return false; end Is_X; -------------------------------------------------------------------- function Is_X (s : STD_ULOGIC) return BOOLEAN is begin case s is when 'U' | 'X' | 'Z' | 'W' | '-' => return true; when others => null; end case; return false; end Is_X; end std_logic_1164;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library IEEE_proposed; use IEEE_proposed.electrical_systems.all; entity tb_freq_detect is end tb_freq_detect; architecture TB_freq_detect of tb_freq_detect is terminal in_src, freq_out : electrical; -- Component declarations -- Signal declarations begin -- Signal assignments -- Component instances vio : entity work.v_sine(ideal) generic map( freq => 200.0, amplitude => 5.0 ) port map( pos => in_src, neg => ELECTRICAL_REF ); freq1 : entity work.freq_detect(threshold_crossing) port map( input => in_src, freq_out => freq_out ); end TB_freq_detect;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library IEEE_proposed; use IEEE_proposed.electrical_systems.all; entity tb_freq_detect is end tb_freq_detect; architecture TB_freq_detect of tb_freq_detect is terminal in_src, freq_out : electrical; -- Component declarations -- Signal declarations begin -- Signal assignments -- Component instances vio : entity work.v_sine(ideal) generic map( freq => 200.0, amplitude => 5.0 ) port map( pos => in_src, neg => ELECTRICAL_REF ); freq1 : entity work.freq_detect(threshold_crossing) port map( input => in_src, freq_out => freq_out ); end TB_freq_detect;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library IEEE_proposed; use IEEE_proposed.electrical_systems.all; entity tb_freq_detect is end tb_freq_detect; architecture TB_freq_detect of tb_freq_detect is terminal in_src, freq_out : electrical; -- Component declarations -- Signal declarations begin -- Signal assignments -- Component instances vio : entity work.v_sine(ideal) generic map( freq => 200.0, amplitude => 5.0 ) port map( pos => in_src, neg => ELECTRICAL_REF ); freq1 : entity work.freq_detect(threshold_crossing) port map( input => in_src, freq_out => freq_out ); end TB_freq_detect;
-- ------------------------------------------------------------- -- -- Generated Architecture Declaration for rtl of inst_ab_e -- -- Generated -- by: wig -- on: Wed Jul 19 05:28:20 2006 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../logic.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_ab_e-rtl-a.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $ -- $Date: 2006/07/19 07:35:16 $ -- $Log: inst_ab_e-rtl-a.vhd,v $ -- Revision 1.4 2006/07/19 07:35:16 wig -- Updated testcases. -- -- -- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp -- -- Generator: mix_0.pl Revision: 1.46 , [email protected] -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/arch -- -- -- Start of Generated Architecture rtl of inst_ab_e -- architecture rtl of inst_ab_e is -- -- Generated Constant Declarations -- -- -- Generated Components -- -- -- Generated Signal List -- -- -- End of Generated Signal List -- begin -- -- Generated Concurrent Statements -- -- -- Generated Signal Assignments -- -- -- Generated Instances and Port Mappings -- end rtl; -- --!End of Architecture/s -- --------------------------------------------------------------
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:02:04 10/11/2013 -- Design Name: -- Module Name: C:/Users/mblott/Desktop/SmartCAM/toe_sessionLup/SmartCamTest.vhd -- Project Name: toe_sessionLup -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: SmartCamWrap -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY SmartCamCtlArp IS generic ( keyLength : integer := 32; valueLength : integer := 48); port ( led1 : out std_logic; led0 : out std_logic; rst : in std_logic; clk : in std_logic; cam_ready : out std_logic; lup_req_valid : in std_logic; lup_req_ready : out std_logic; lup_req_din : in std_logic_vector(keyLength downto 0); lup_rsp_valid : out std_logic; lup_rsp_ready : in std_logic; lup_rsp_dout : out std_logic_vector(valueLength downto 0); upd_req_valid : in std_logic; upd_req_ready : out std_logic; upd_req_din : in std_logic_vector((keyLength + valueLength) + 1 downto 0); -- This will include the key, the value to be updated and one bit to indicate whether this is a delete op upd_rsp_valid : out std_logic; upd_rsp_ready : in std_logic; upd_rsp_dout : out std_logic_vector(valueLength + 1 downto 0); --new_id_valid : in std_logic; --new_id_ready : out std_logic; --new_id_din : in std_logic_vector(13 downto 0); --fin_id_valid : out std_logic; --fin_id_ready : in std_logic; --fin_id_dout : out std_logic_vector(13 downto 0); debug : out std_logic_vector(255 downto 0) ); END SmartCamCtlArp;
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:02:04 10/11/2013 -- Design Name: -- Module Name: C:/Users/mblott/Desktop/SmartCAM/toe_sessionLup/SmartCamTest.vhd -- Project Name: toe_sessionLup -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: SmartCamWrap -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY SmartCamCtlArp IS generic ( keyLength : integer := 32; valueLength : integer := 48); port ( led1 : out std_logic; led0 : out std_logic; rst : in std_logic; clk : in std_logic; cam_ready : out std_logic; lup_req_valid : in std_logic; lup_req_ready : out std_logic; lup_req_din : in std_logic_vector(keyLength downto 0); lup_rsp_valid : out std_logic; lup_rsp_ready : in std_logic; lup_rsp_dout : out std_logic_vector(valueLength downto 0); upd_req_valid : in std_logic; upd_req_ready : out std_logic; upd_req_din : in std_logic_vector((keyLength + valueLength) + 1 downto 0); -- This will include the key, the value to be updated and one bit to indicate whether this is a delete op upd_rsp_valid : out std_logic; upd_rsp_ready : in std_logic; upd_rsp_dout : out std_logic_vector(valueLength + 1 downto 0); --new_id_valid : in std_logic; --new_id_ready : out std_logic; --new_id_din : in std_logic_vector(13 downto 0); --fin_id_valid : out std_logic; --fin_id_ready : in std_logic; --fin_id_dout : out std_logic_vector(13 downto 0); debug : out std_logic_vector(255 downto 0) ); END SmartCamCtlArp;
-- ------------------------------------------------------------- -- -- Generated Architecture Declaration for rtl of inst_ebb_e -- -- Generated -- by: wig -- on: Mon Mar 22 13:27:43 2004 -- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_ebb_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:00 wig Exp $ -- $Date: 2004/04/06 10:50:00 $ -- $Log: inst_ebb_e-rtl-a.vhd,v $ -- Revision 1.1 2004/04/06 10:50:00 wig -- Adding result/mde_tests -- -- -- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp -- -- Generator: mix_0.pl Revision: 1.26 , [email protected] -- (C) 2003 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/arch -- -- -- Start of Generated Architecture rtl of inst_ebb_e -- architecture rtl of inst_ebb_e is -- Generated Constant Declarations -- -- Components -- -- Generated Components -- -- Nets -- -- -- Generated Signal List -- -- -- End of Generated Signal List -- begin -- -- Generated Concurrent Statements -- -- Generated Signal Assignments -- -- Generated Instances -- -- Generated Instances and Port Mappings end rtl; -- --!End of Architecture/s -- --------------------------------------------------------------
entity sub is port ( x : in integer ); end entity; entity top is end entity; architecture test of top is begin end architecture;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY CURRENT_SOURCE IS GENERIC ( N : REAL := 1.0; VT : REAL := 25.85e-6; ISS : REAL := 10.0e-14 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY CURRENT_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY CURRENT_SOURCE IS GENERIC ( N : REAL := 1.0; VT : REAL := 25.85e-6; ISS : REAL := 10.0e-14 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY CURRENT_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY CURRENT_SOURCE IS GENERIC ( N : REAL := 1.0; VT : REAL := 25.85e-6; ISS : REAL := 10.0e-14 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY CURRENT_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY CURRENT_SOURCE IS GENERIC ( N : REAL := 1.0; VT : REAL := 25.85e-6; ISS : REAL := 10.0e-14 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY CURRENT_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY CURRENT_SOURCE IS GENERIC ( N : REAL := 1.0; VT : REAL := 25.85e-6; ISS : REAL := 10.0e-14 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY CURRENT_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY CURRENT_SOURCE IS GENERIC ( N : REAL := 1.0; VT : REAL := 25.85e-6; ISS : REAL := 10.0e-14 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY CURRENT_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY CURRENT_SOURCE IS GENERIC ( N : REAL := 1.0; VT : REAL := 25.85e-6; ISS : REAL := 10.0e-14 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY CURRENT_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY CURRENT_SOURCE IS GENERIC ( N : REAL := 1.0; VT : REAL := 25.85e-6; ISS : REAL := 10.0e-14 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY CURRENT_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY CURRENT_SOURCE IS GENERIC ( N : REAL := 1.0; VT : REAL := 25.85e-6; ISS : REAL := 10.0e-14 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY CURRENT_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY CURRENT_SOURCE IS GENERIC ( N : REAL := 1.0; VT : REAL := 25.85e-6; ISS : REAL := 10.0e-14 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY CURRENT_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY CURRENT_SOURCE IS GENERIC ( N : REAL := 1.0; VT : REAL := 25.85e-6; ISS : REAL := 10.0e-14 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY CURRENT_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY CURRENT_SOURCE IS GENERIC ( N : REAL := 1.0; VT : REAL := 25.85e-6; ISS : REAL := 10.0e-14 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY CURRENT_SOURCE;
LIBRARY ieee,disciplines; USE ieee.math_real.all; USE ieee.math_real.all; USE work.electrical_system.all; USE work.all; -- Entity declaration -- ENTITY CURRENT_SOURCE IS GENERIC ( N : REAL := 1.0; VT : REAL := 25.85e-6; ISS : REAL := 10.0e-14 ); PORT ( terminal RT : electrical; terminal LT : electrical ); END ENTITY CURRENT_SOURCE;
-- Dual port Video RAM -- -- Part of MARK II project. For informations about license, please -- see file /LICENSE . -- -- author: Vladislav Mlejnecký -- email: [email protected] library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity vram is port( clk_a : in std_logic; addr_a : in unsigned(11 downto 0); data_a : in unsigned(15 downto 0); we_a : in std_logic; q_a : out unsigned(15 downto 0); clk_b : in std_logic; addr_b : in unsigned(11 downto 0); q_b : out unsigned(15 downto 0) ); end entity vram; architecture vram_arch of vram is subtype word_t is unsigned(15 downto 0); type memory_t is array(2**12-1 downto 0) of word_t; shared variable ram : memory_t; attribute ramstyle : string; attribute ramstyle of ram : variable is "no_rw_check"; begin process(clk_a) begin if(rising_edge(clk_a)) then if(we_a = '1') then ram(to_integer(addr_a)) := data_a; end if; q_a <= ram(to_integer(addr_a)); end if; end process; process(clk_b) begin if(rising_edge(clk_b)) then q_b <= ram(to_integer(addr_b)); end if; end process; end architecture vram_arch;
library verilog; use verilog.vl_types.all; entity InstruMemory is generic( DATA_WIDTH : integer := 32; DATA_LENGTH : integer := 128; ADX_LENGTH : integer := 7 ); port( clk : in vl_logic; adx : in vl_logic_vector; WrEn : in vl_logic; data : inout vl_logic_vector; rst : in vl_logic ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of DATA_WIDTH : constant is 1; attribute mti_svvh_generic_type of DATA_LENGTH : constant is 1; attribute mti_svvh_generic_type of ADX_LENGTH : constant is 1; end InstruMemory;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --use work.myTypes.all; entity mem_regs is generic ( SIZE : integer := 32 ); port ( W_i : in std_logic_vector(SIZE - 1 downto 0); D3_i : in std_logic_vector(4 downto 0); W_o : out std_logic_vector(SIZE - 1 downto 0); D3_o : out std_logic_vector(4 downto 0); clk : in std_logic; rst : in std_logic ); end mem_regs; architecture Struct of mem_regs is component ff32 generic( SIZE : integer ); port( D : in std_logic_vector(SIZE - 1 downto 0); Q : out std_logic_vector(SIZE - 1 downto 0); clk : in std_logic; rst : in std_logic ); end component; begin W: ff32 generic map( SIZE => 32 ) port map( D => W_i, Q => W_o, clk => clk, rst => rst ); D3: ff32 generic map( SIZE => 5 ) port map( D => D3_i, Q => D3_o, clk => clk, rst => rst ); end Struct;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
--Generic Help --C_CDC_TYPE : Defines the type of CDC needed -- 0 means pulse synchronizer. Used to transfer one clock pulse -- from prmry domain to scndry domain. -- 1 means level synchronizer. Used to transfer level signal. -- 2 means level synchronizer with ack. Used to transfer level -- signal. Input signal should change only when prmry_ack is detected -- --C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal -- Set to 0 when incoming signal is purely floped signal. -- --C_RESET_STATE : Generally sync flops need not have resets. However, in some cases -- it might be needed. -- 0 means reset not needed for sync flops -- 1 means reset needed for sync flops. i -- In this case prmry_resetn should be in prmry clock, -- while scndry_reset should be in scndry clock. -- --C_SINGLE_BIT : CDC should normally be done for single bit signals only. -- However, based on design buses can also be CDC'ed. -- 0 means it is a bus. In this case input be connected to prmry_vect_in. -- Output is on scndry_vect_out. -- 1 means it is a single bit. In this case input be connected to prmry_in. -- Output is on scndry_out. -- --C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1 -- --C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6. -- Value of 0, 1 is allowed only for level CDC. -- Min value for Pulse CDC is 2 -- --Whenever this file is used following XDC constraint has to be added -- set_false_path -to [get_pins -hier *cdc_to*/D] --IO Ports -- -- prmry_aclk : clock of originating domain (source domain) -- prmry_resetn : sync reset of originating clock domain (source domain) -- prmry_in : input signal bit. This should be a pure flop output without -- any combi logic. This is source. -- prmry_vect_in : bus signal. From Source domain. -- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain. -- Used only when C_CDC_TYPE = 2 -- scndry_aclk : destination clock. -- scndry_resetn : sync reset of destination domain -- scndry_out : sync'ed output in destination domain. Single bit. -- scndry_vect_out : sync'ed output in destination domain. bus. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.FDR; entity cdc_sync is generic ( C_CDC_TYPE : integer range 0 to 2 := 1 ; -- 0 is pulse synch -- 1 is level synch -- 2 is ack based level sync C_RESET_STATE : integer range 0 to 1 := 0 ; -- 0 is reset not needed -- 1 is reset needed C_SINGLE_BIT : integer range 0 to 1 := 1 ; -- 0 is bus input -- 1 is single bit input C_FLOP_INPUT : integer range 0 to 1 := 0 ; C_VECTOR_WIDTH : integer range 0 to 32 := 32 ; C_MTBF_STAGES : integer range 0 to 6 := 2 -- Vector Data witdth ); port ( prmry_aclk : in std_logic ; -- prmry_resetn : in std_logic ; -- prmry_in : in std_logic ; -- prmry_vect_in : in std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) ; -- prmry_ack : out std_logic ; -- scndry_aclk : in std_logic ; -- scndry_resetn : in std_logic ; -- -- -- Primary to Secondary Clock Crossing -- scndry_out : out std_logic ; -- -- scndry_vect_out : out std_logic_vector -- (C_VECTOR_WIDTH - 1 downto 0) -- ); end cdc_sync; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of cdc_sync is attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; --attribute DONT_TOUCH : STRING; --attribute KEEP : STRING; --attribute DONT_TOUCH of implementation : architecture is "yes"; signal prmry_resetn1 : std_logic := '0'; signal scndry_resetn1 : std_logic := '0'; signal prmry_reset2 : std_logic := '0'; signal scndry_reset2 : std_logic := '0'; --attribute KEEP of prmry_resetn1 : signal is "true"; --attribute KEEP of scndry_resetn1 : signal is "true"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin HAS_RESET : if C_RESET_STATE = 1 generate begin prmry_resetn1 <= prmry_resetn; scndry_resetn1 <= scndry_resetn; end generate HAS_RESET; HAS_NO_RESET : if C_RESET_STATE = 0 generate begin prmry_resetn1 <= '1'; scndry_resetn1 <= '1'; end generate HAS_NO_RESET; prmry_reset2 <= not prmry_resetn1; scndry_reset2 <= not scndry_resetn1; -- Generate PULSE clock domain crossing GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate -- Primary to Secondary signal s_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true"; signal s_out_d2 : std_logic := '0'; signal s_out_d3 : std_logic := '0'; signal s_out_d4 : std_logic := '0'; signal s_out_d5 : std_logic := '0'; signal s_out_d6 : std_logic := '0'; signal s_out_d7 : std_logic := '0'; signal s_out_re : std_logic := '0'; signal prmry_in_xored : std_logic := '0'; signal p_in_d1_cdc_from : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true"; ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Pulse Clock Crossing ** --** PRIMARY TO SECONDARY OPEN-ENDED ** --***************************************************************************** scndry_vect_out <= (others => '0'); prmry_ack <= '0'; prmry_in_xored <= prmry_in xor p_in_d1_cdc_from; --------------------------------------REG_P_IN : process(prmry_aclk) -------------------------------------- begin -------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then -------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then -------------------------------------- p_in_d1_cdc_from <= '0'; -------------------------------------- else -------------------------------------- p_in_d1_cdc_from <= prmry_in_xored; -------------------------------------- end if; -------------------------------------- end if; -------------------------------------- end process REG_P_IN; REG_P_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_in_d1_cdc_from, C => prmry_aclk, D => prmry_in_xored, R => prmry_reset2 ); REG_P_IN2_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_out_d1_cdc_to, C => scndry_aclk, D => p_in_d1_cdc_from, R => scndry_reset2 ); ------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk) ------------------------------------ begin ------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------ s_out_d2 <= '0'; ------------------------------------ s_out_d3 <= '0'; ------------------------------------ s_out_d4 <= '0'; ------------------------------------ s_out_d5 <= '0'; ------------------------------------ s_out_d6 <= '0'; ------------------------------------ s_out_d7 <= '0'; ------------------------------------ scndry_out <= '0'; ------------------------------------ else ------------------------------------ s_out_d2 <= s_out_d1_cdc_to; ------------------------------------ s_out_d3 <= s_out_d2; ------------------------------------ s_out_d4 <= s_out_d3; ------------------------------------ s_out_d5 <= s_out_d4; ------------------------------------ s_out_d6 <= s_out_d5; ------------------------------------ s_out_d7 <= s_out_d6; ------------------------------------ scndry_out <= s_out_re; ------------------------------------ end if; ------------------------------------ end if; ------------------------------------ end process P_IN_CROSS2SCNDRY; P_IN_CROSS2SCNDRY_s_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d2, C => scndry_aclk, D => s_out_d1_cdc_to, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d3, C => scndry_aclk, D => s_out_d2, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d4, C => scndry_aclk, D => s_out_d3, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d5, C => scndry_aclk, D => s_out_d4, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d6, C => scndry_aclk, D => s_out_d5, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_s_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => s_out_d7, C => scndry_aclk, D => s_out_d6, R => scndry_reset2 ); P_IN_CROSS2SCNDRY_scndry_out : component FDR generic map(INIT => '0' )port map ( Q => scndry_out, C => scndry_aclk, D => s_out_re, R => scndry_reset2 ); MTBF_2 : if C_MTBF_STAGES = 2 generate begin s_out_re <= s_out_d2 xor s_out_d3; end generate MTBF_2; MTBF_3 : if C_MTBF_STAGES = 3 generate begin s_out_re <= s_out_d3 xor s_out_d4; end generate MTBF_3; MTBF_4 : if C_MTBF_STAGES = 4 generate begin s_out_re <= s_out_d4 xor s_out_d5; end generate MTBF_4; MTBF_5 : if C_MTBF_STAGES = 5 generate begin s_out_re <= s_out_d5 xor s_out_d6; end generate MTBF_5; MTBF_6 : if C_MTBF_STAGES = 6 generate begin s_out_re <= s_out_d6 xor s_out_d7; end generate MTBF_6; -- Feed secondary pulse out end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED; -- Generate LEVEL clock domain crossing with reset state = 0 GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate begin -- Primary to Secondary SINGLE_BIT : if C_SINGLE_BIT = 1 generate signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); prmry_ack <= '0'; INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ---------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ---------------------------------- begin ---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ---------------------------------- p_level_in_d1_cdc_from <= '0'; ---------------------------------- else ---------------------------------- p_level_in_d1_cdc_from <= prmry_in; ---------------------------------- end if; ---------------------------------- end if; ---------------------------------- end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------ begin ------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------ s_level_out_d2 <= '0'; ------------------------------ s_level_out_d3 <= '0'; ------------------------------ s_level_out_d4 <= '0'; ------------------------------ s_level_out_d5 <= '0'; ------------------------------ s_level_out_d6 <= '0'; ------------------------------ else ------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------ end if; ------------------------------ end if; ------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_out <= s_level_out_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_out <= s_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out <= s_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out <= s_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out <= s_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out <= s_level_out_d6; end generate MTBF_L6; end generate SINGLE_BIT; MULTI_BIT : if C_SINGLE_BIT = 0 generate signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0); signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); --attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true"; signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0); ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true"; -----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_out <= '0'; prmry_ack <= '0'; INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate begin ----------------------------------- REG_PLEVEL_IN : process(prmry_aclk) ----------------------------------- begin ----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then ----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0'); ----------------------------------- else ----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in; ----------------------------------- end if; ----------------------------------- end if; ----------------------------------- end process REG_PLEVEL_IN; FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate begin REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_bus_d1_cdc_from (i), C => prmry_aclk, D => prmry_vect_in (i), R => prmry_reset2 ); end generate FOR_REG_PLEVEL_IN; p_level_in_bus_int <= p_level_in_bus_d1_cdc_from; end generate INPUT_FLOP_BUS; NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate begin p_level_in_bus_int <= prmry_vect_in; end generate NO_INPUT_FLOP_BUS; FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d1_cdc_to (i), C => scndry_aclk, D => p_level_in_bus_int (i), R => scndry_reset2 ); end generate FOR_IN_cdc_to; ----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ----------------------------------------- begin ----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then ----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ----------------------------------------- s_level_out_bus_d2 <= (others => '0'); ----------------------------------------- s_level_out_bus_d3 <= (others => '0'); ----------------------------------------- s_level_out_bus_d4 <= (others => '0'); ----------------------------------------- s_level_out_bus_d5 <= (others => '0'); ----------------------------------------- s_level_out_bus_d6 <= (others => '0'); ----------------------------------------- else ----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to; ----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2; ----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3; ----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4; ----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5; ----------------------------------------- end if; ----------------------------------------- end if; ----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d2 (i), C => scndry_aclk, D => s_level_out_bus_d1_cdc_to (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d3 (i), C => scndry_aclk, D => s_level_out_bus_d2 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d4 (i), C => scndry_aclk, D => s_level_out_bus_d3 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d5 (i), C => scndry_aclk, D => s_level_out_bus_d4 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5; FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true"; begin CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_bus_d6 (i), C => scndry_aclk, D => s_level_out_bus_d5 (i), R => scndry_reset2 ); end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6; MTBF_L1 : if C_MTBF_STAGES = 1 generate begin scndry_vect_out <= s_level_out_bus_d1_cdc_to; end generate MTBF_L1; MTBF_L2 : if C_MTBF_STAGES = 2 generate begin scndry_vect_out <= s_level_out_bus_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_vect_out <= s_level_out_bus_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_vect_out <= s_level_out_bus_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_vect_out <= s_level_out_bus_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_vect_out <= s_level_out_bus_d6; end generate MTBF_L6; end generate MULTI_BIT; end generate GENERATE_LEVEL_P_S_CDC; GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate -- Primary to Secondary signal p_level_in_d1_cdc_from : std_logic := '0'; signal p_level_in_int : std_logic := '0'; signal s_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true"; signal s_level_out_d2 : std_logic := '0'; signal s_level_out_d3 : std_logic := '0'; signal s_level_out_d4 : std_logic := '0'; signal s_level_out_d5 : std_logic := '0'; signal s_level_out_d6 : std_logic := '0'; signal p_level_out_d1_cdc_to : std_logic := '0'; --attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true"; signal p_level_out_d2 : std_logic := '0'; signal p_level_out_d3 : std_logic := '0'; signal p_level_out_d4 : std_logic := '0'; signal p_level_out_d5 : std_logic := '0'; signal p_level_out_d6 : std_logic := '0'; signal p_level_out_d7 : std_logic := '0'; signal scndry_out_int : std_logic := '0'; signal prmry_pulse_ack : std_logic := '0'; ----------------------------------------------------------------------------- -- ATTRIBUTE Declarations ----------------------------------------------------------------------------- -- Prevent x-propagation on clock-domain crossing register ATTRIBUTE async_reg : STRING; ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true"; ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true"; begin --***************************************************************************** --** Asynchronous Level Clock Crossing ** --** PRIMARY TO SECONDARY ** --***************************************************************************** -- register is scndry to provide clean ff output to clock crossing logic scndry_vect_out <= (others => '0'); INPUT_FLOP : if C_FLOP_INPUT = 1 generate begin ------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk) ------------------------------------------ begin ------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then ------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------ p_level_in_d1_cdc_from <= '0'; ------------------------------------------ else ------------------------------------------ p_level_in_d1_cdc_from <= prmry_in; ------------------------------------------ end if; ------------------------------------------ end if; ------------------------------------------ end process REG_PLEVEL_IN; REG_PLEVEL_IN_cdc_from : component FDR generic map(INIT => '0' )port map ( Q => p_level_in_d1_cdc_from, C => prmry_aclk, D => prmry_in, R => prmry_reset2 ); p_level_in_int <= p_level_in_d1_cdc_from; end generate INPUT_FLOP; NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate begin p_level_in_int <= prmry_in; end generate NO_INPUT_FLOP; CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d1_cdc_to, C => scndry_aclk, D => p_level_in_int, R => scndry_reset2 ); ------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk) ------------------------------------------------ begin ------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then ------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then ------------------------------------------------ s_level_out_d2 <= '0'; ------------------------------------------------ s_level_out_d3 <= '0'; ------------------------------------------------ s_level_out_d4 <= '0'; ------------------------------------------------ s_level_out_d5 <= '0'; ------------------------------------------------ s_level_out_d6 <= '0'; ------------------------------------------------ else ------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to; ------------------------------------------------ s_level_out_d3 <= s_level_out_d2; ------------------------------------------------ s_level_out_d4 <= s_level_out_d3; ------------------------------------------------ s_level_out_d5 <= s_level_out_d4; ------------------------------------------------ s_level_out_d6 <= s_level_out_d5; ------------------------------------------------ end if; ------------------------------------------------ end if; ------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY; CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d2, C => scndry_aclk, D => s_level_out_d1_cdc_to, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d3, C => scndry_aclk, D => s_level_out_d2, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d4, C => scndry_aclk, D => s_level_out_d3, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d5, C => scndry_aclk, D => s_level_out_d4, R => scndry_reset2 ); CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => s_level_out_d6, C => scndry_aclk, D => s_level_out_d5, R => scndry_reset2 ); --------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk) --------------------------------------------------- begin --------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then --------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then --------------------------------------------------- p_level_out_d1_cdc_to <= '0'; --------------------------------------------------- p_level_out_d2 <= '0'; --------------------------------------------------- p_level_out_d3 <= '0'; --------------------------------------------------- p_level_out_d4 <= '0'; --------------------------------------------------- p_level_out_d5 <= '0'; --------------------------------------------------- p_level_out_d6 <= '0'; --------------------------------------------------- p_level_out_d7 <= '0'; --------------------------------------------------- prmry_ack <= '0'; --------------------------------------------------- else --------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int; --------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to; --------------------------------------------------- p_level_out_d3 <= p_level_out_d2; --------------------------------------------------- p_level_out_d4 <= p_level_out_d3; --------------------------------------------------- p_level_out_d5 <= p_level_out_d4; --------------------------------------------------- p_level_out_d6 <= p_level_out_d5; --------------------------------------------------- p_level_out_d7 <= p_level_out_d6; --------------------------------------------------- prmry_ack <= prmry_pulse_ack; --------------------------------------------------- end if; --------------------------------------------------- end if; --------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY; CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d1_cdc_to, C => prmry_aclk, D => scndry_out_int, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d2, C => prmry_aclk, D => p_level_out_d1_cdc_to, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d3, C => prmry_aclk, D => p_level_out_d2, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d4, C => prmry_aclk, D => p_level_out_d3, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d5, C => prmry_aclk, D => p_level_out_d4, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d6, C => prmry_aclk, D => p_level_out_d5, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR generic map(INIT => '0' )port map ( Q => p_level_out_d7, C => prmry_aclk, D => p_level_out_d6, R => prmry_reset2 ); CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR generic map(INIT => '0' )port map ( Q => prmry_ack, C => prmry_aclk, D => prmry_pulse_ack, R => prmry_reset2 ); MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate begin scndry_out_int <= s_level_out_d2; --prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2; prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2; end generate MTBF_L2; MTBF_L3 : if C_MTBF_STAGES = 3 generate begin scndry_out_int <= s_level_out_d3; --prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3; prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3; end generate MTBF_L3; MTBF_L4 : if C_MTBF_STAGES = 4 generate begin scndry_out_int <= s_level_out_d4; --prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4; prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4; end generate MTBF_L4; MTBF_L5 : if C_MTBF_STAGES = 5 generate begin scndry_out_int <= s_level_out_d5; --prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5; prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5; end generate MTBF_L5; MTBF_L6 : if C_MTBF_STAGES = 6 generate begin scndry_out_int <= s_level_out_d6; --prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6; prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6; end generate MTBF_L6; scndry_out <= scndry_out_int; end generate GENERATE_LEVEL_ACK_P_S_CDC; end implementation;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- analyze into resource library graphics package graphics_pkg is attribute graphic_symbol : string; attribute graphic_style : string; end package graphics_pkg; -- code from book library ieee; use ieee.std_logic_1164.all; library graphics; package gate_components is use graphics.graphics_pkg.graphic_symbol, graphics.graphics_pkg.graphic_style; component and2 is generic ( prop_delay : delay_length ); port ( a, b : in std_logic; y : out std_logic ); end component and2; attribute graphic_symbol of and2 : component is "and2"; attribute graphic_style of and2 : component is "color:default, weight:bold"; -- . . . end package gate_components; -- end code from book
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- analyze into resource library graphics package graphics_pkg is attribute graphic_symbol : string; attribute graphic_style : string; end package graphics_pkg; -- code from book library ieee; use ieee.std_logic_1164.all; library graphics; package gate_components is use graphics.graphics_pkg.graphic_symbol, graphics.graphics_pkg.graphic_style; component and2 is generic ( prop_delay : delay_length ); port ( a, b : in std_logic; y : out std_logic ); end component and2; attribute graphic_symbol of and2 : component is "and2"; attribute graphic_style of and2 : component is "color:default, weight:bold"; -- . . . end package gate_components; -- end code from book
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- analyze into resource library graphics package graphics_pkg is attribute graphic_symbol : string; attribute graphic_style : string; end package graphics_pkg; -- code from book library ieee; use ieee.std_logic_1164.all; library graphics; package gate_components is use graphics.graphics_pkg.graphic_symbol, graphics.graphics_pkg.graphic_style; component and2 is generic ( prop_delay : delay_length ); port ( a, b : in std_logic; y : out std_logic ); end component and2; attribute graphic_symbol of and2 : component is "and2"; attribute graphic_style of and2 : component is "color:default, weight:bold"; -- . . . end package gate_components; -- end code from book
-------------------------------------------------------------------------------- -- -- FileName: debounce.vhd -- Dependencies: none -- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version -- -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. -- -- Version History -- Version 1.0 3/26/2012 Scott Larson -- Initial Public Release -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY debounce IS GENERIC( counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock) PORT( clk : IN STD_LOGIC; --input clock button : IN STD_LOGIC; --input signal to be debounced result : OUT STD_LOGIC); --debounced signal END debounce; ARCHITECTURE logic OF debounce IS SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops SIGNAL counter_set : STD_LOGIC; --sync reset to zero SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output BEGIN counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter PROCESS(clk) BEGIN IF(clk'EVENT and clk = '1') THEN flipflops(0) <= button; flipflops(1) <= flipflops(0); If(counter_set = '1') THEN --reset counter because input is changing counter_out <= (OTHERS => '0'); ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met counter_out <= counter_out + 1; ELSE --stable input time is met result <= flipflops(1); END IF; END IF; END PROCESS; END logic;
-------------------------------------------------------------------------------- -- -- FileName: debounce.vhd -- Dependencies: none -- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version -- -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. -- -- Version History -- Version 1.0 3/26/2012 Scott Larson -- Initial Public Release -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY debounce IS GENERIC( counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock) PORT( clk : IN STD_LOGIC; --input clock button : IN STD_LOGIC; --input signal to be debounced result : OUT STD_LOGIC); --debounced signal END debounce; ARCHITECTURE logic OF debounce IS SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops SIGNAL counter_set : STD_LOGIC; --sync reset to zero SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output BEGIN counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter PROCESS(clk) BEGIN IF(clk'EVENT and clk = '1') THEN flipflops(0) <= button; flipflops(1) <= flipflops(0); If(counter_set = '1') THEN --reset counter because input is changing counter_out <= (OTHERS => '0'); ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met counter_out <= counter_out + 1; ELSE --stable input time is met result <= flipflops(1); END IF; END IF; END PROCESS; END logic;
-------------------------------------------------------------------------------- -- -- FileName: debounce.vhd -- Dependencies: none -- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version -- -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. -- -- Version History -- Version 1.0 3/26/2012 Scott Larson -- Initial Public Release -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY debounce IS GENERIC( counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock) PORT( clk : IN STD_LOGIC; --input clock button : IN STD_LOGIC; --input signal to be debounced result : OUT STD_LOGIC); --debounced signal END debounce; ARCHITECTURE logic OF debounce IS SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops SIGNAL counter_set : STD_LOGIC; --sync reset to zero SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output BEGIN counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter PROCESS(clk) BEGIN IF(clk'EVENT and clk = '1') THEN flipflops(0) <= button; flipflops(1) <= flipflops(0); If(counter_set = '1') THEN --reset counter because input is changing counter_out <= (OTHERS => '0'); ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met counter_out <= counter_out + 1; ELSE --stable input time is met result <= flipflops(1); END IF; END IF; END PROCESS; END logic;
-------------------------------------------------------------------------------- -- -- FileName: debounce.vhd -- Dependencies: none -- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version -- -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. -- -- Version History -- Version 1.0 3/26/2012 Scott Larson -- Initial Public Release -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY debounce IS GENERIC( counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock) PORT( clk : IN STD_LOGIC; --input clock button : IN STD_LOGIC; --input signal to be debounced result : OUT STD_LOGIC); --debounced signal END debounce; ARCHITECTURE logic OF debounce IS SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops SIGNAL counter_set : STD_LOGIC; --sync reset to zero SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output BEGIN counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter PROCESS(clk) BEGIN IF(clk'EVENT and clk = '1') THEN flipflops(0) <= button; flipflops(1) <= flipflops(0); If(counter_set = '1') THEN --reset counter because input is changing counter_out <= (OTHERS => '0'); ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met counter_out <= counter_out + 1; ELSE --stable input time is met result <= flipflops(1); END IF; END IF; END PROCESS; END logic;
-------------------------------------------------------------------------------- -- -- FileName: debounce.vhd -- Dependencies: none -- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version -- -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. -- -- Version History -- Version 1.0 3/26/2012 Scott Larson -- Initial Public Release -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY debounce IS GENERIC( counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock) PORT( clk : IN STD_LOGIC; --input clock button : IN STD_LOGIC; --input signal to be debounced result : OUT STD_LOGIC); --debounced signal END debounce; ARCHITECTURE logic OF debounce IS SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops SIGNAL counter_set : STD_LOGIC; --sync reset to zero SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output BEGIN counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter PROCESS(clk) BEGIN IF(clk'EVENT and clk = '1') THEN flipflops(0) <= button; flipflops(1) <= flipflops(0); If(counter_set = '1') THEN --reset counter because input is changing counter_out <= (OTHERS => '0'); ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met counter_out <= counter_out + 1; ELSE --stable input time is met result <= flipflops(1); END IF; END IF; END PROCESS; END logic;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc130.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s03b02x01p04n02i00130ent IS END c04s03b02x01p04n02i00130ent; ARCHITECTURE c04s03b02x01p04n02i00130arch OF c04s03b02x01p04n02i00130ent IS component A3 port (variable PT3: BOOLEAN); -- Failure_here -- ERROR: the only object class allowed in a local port list is signal. end component ; BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c04s03b02x01p04n02i00130 - The only object class allowed is signal." severity ERROR; wait; END PROCESS TESTING; END c04s03b02x01p04n02i00130arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc130.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s03b02x01p04n02i00130ent IS END c04s03b02x01p04n02i00130ent; ARCHITECTURE c04s03b02x01p04n02i00130arch OF c04s03b02x01p04n02i00130ent IS component A3 port (variable PT3: BOOLEAN); -- Failure_here -- ERROR: the only object class allowed in a local port list is signal. end component ; BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c04s03b02x01p04n02i00130 - The only object class allowed is signal." severity ERROR; wait; END PROCESS TESTING; END c04s03b02x01p04n02i00130arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc130.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c04s03b02x01p04n02i00130ent IS END c04s03b02x01p04n02i00130ent; ARCHITECTURE c04s03b02x01p04n02i00130arch OF c04s03b02x01p04n02i00130ent IS component A3 port (variable PT3: BOOLEAN); -- Failure_here -- ERROR: the only object class allowed in a local port list is signal. end component ; BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c04s03b02x01p04n02i00130 - The only object class allowed is signal." severity ERROR; wait; END PROCESS TESTING; END c04s03b02x01p04n02i00130arch;
------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2012, Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : Small Synchronous Stack Using Single Port Distributed RAM ------------------------------------------------------------------------------- -- File : distributed_stack.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This implementation makes use of the RAMX1 properties, -- implementing a 16-deep synchronous stack in only one LUT per -- bit. The value to be popped is always visible. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity distributed_stack is generic ( Width : integer := 32; simultaneous_pushpop : boolean := false ); port ( clock : in std_logic; reset : in std_logic; pop : in std_logic; push : in std_logic; flush : in std_logic; data_in : in std_logic_vector(Width-1 downto 0); data_out : out std_logic_vector(Width-1 downto 0); full : out std_logic; data_valid : out std_logic ); end distributed_stack; architecture Gideon of distributed_stack is signal pointer : unsigned(3 downto 0); signal address : unsigned(3 downto 0); signal we : std_logic; signal data_valid_i : std_logic; signal full_i : std_logic; signal filtered_pop : std_logic; signal filtered_push : std_logic; signal ram_data : std_logic_vector(Width-1 downto 0); begin filtered_pop <= data_valid_i and pop; filtered_push <= not full_i and push; full <= full_i; process(filtered_push, pop, pointer, ram_data, data_in) begin we <= filtered_push; data_out <= ram_data; data_valid <= data_valid_i; if filtered_push='1' then address <= pointer + 1; else address <= pointer; end if; if simultaneous_pushpop then if filtered_push='1' and pop='1' then data_out <= data_in; we <= '0'; data_valid <= '1'; end if; end if; end process; process(clock) variable new_pointer : unsigned(3 downto 0);--integer range 0 to Depth; begin if rising_edge(clock) then if flush='1' then new_pointer := X"F"; elsif (filtered_pop='1') and (filtered_push='0') then new_pointer := pointer - 1; elsif (filtered_pop='0') and (filtered_push='1') then new_pointer := pointer + 1; else new_pointer := pointer; end if; pointer <= new_pointer; if (new_pointer = X"F") then data_valid_i <= '0'; else data_valid_i <= '1'; end if; if (new_pointer /= X"E") then full_i <= '0'; else full_i <= '1'; end if; if reset='1' then pointer <= X"F"; full_i <= '0'; data_valid_i <= '0'; end if; end if; end process; RAMs : for ram2 in 0 to Width-1 generate i_ram : RAM16X1S port map ( WCLK => clock, WE => we, D => data_in(ram2), A3 => address(3), A2 => address(2), A1 => address(1), A0 => address(0), O => ram_data(ram2) ); end generate; end Gideon;
------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2012, Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : Small Synchronous Stack Using Single Port Distributed RAM ------------------------------------------------------------------------------- -- File : distributed_stack.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This implementation makes use of the RAMX1 properties, -- implementing a 16-deep synchronous stack in only one LUT per -- bit. The value to be popped is always visible. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity distributed_stack is generic ( Width : integer := 32; simultaneous_pushpop : boolean := false ); port ( clock : in std_logic; reset : in std_logic; pop : in std_logic; push : in std_logic; flush : in std_logic; data_in : in std_logic_vector(Width-1 downto 0); data_out : out std_logic_vector(Width-1 downto 0); full : out std_logic; data_valid : out std_logic ); end distributed_stack; architecture Gideon of distributed_stack is signal pointer : unsigned(3 downto 0); signal address : unsigned(3 downto 0); signal we : std_logic; signal data_valid_i : std_logic; signal full_i : std_logic; signal filtered_pop : std_logic; signal filtered_push : std_logic; signal ram_data : std_logic_vector(Width-1 downto 0); begin filtered_pop <= data_valid_i and pop; filtered_push <= not full_i and push; full <= full_i; process(filtered_push, pop, pointer, ram_data, data_in) begin we <= filtered_push; data_out <= ram_data; data_valid <= data_valid_i; if filtered_push='1' then address <= pointer + 1; else address <= pointer; end if; if simultaneous_pushpop then if filtered_push='1' and pop='1' then data_out <= data_in; we <= '0'; data_valid <= '1'; end if; end if; end process; process(clock) variable new_pointer : unsigned(3 downto 0);--integer range 0 to Depth; begin if rising_edge(clock) then if flush='1' then new_pointer := X"F"; elsif (filtered_pop='1') and (filtered_push='0') then new_pointer := pointer - 1; elsif (filtered_pop='0') and (filtered_push='1') then new_pointer := pointer + 1; else new_pointer := pointer; end if; pointer <= new_pointer; if (new_pointer = X"F") then data_valid_i <= '0'; else data_valid_i <= '1'; end if; if (new_pointer /= X"E") then full_i <= '0'; else full_i <= '1'; end if; if reset='1' then pointer <= X"F"; full_i <= '0'; data_valid_i <= '0'; end if; end if; end process; RAMs : for ram2 in 0 to Width-1 generate i_ram : RAM16X1S port map ( WCLK => clock, WE => we, D => data_in(ram2), A3 => address(3), A2 => address(2), A1 => address(1), A0 => address(0), O => ram_data(ram2) ); end generate; end Gideon;
------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2012, Gideon's Logic Architectures -- ------------------------------------------------------------------------------- -- Title : Small Synchronous Stack Using Single Port Distributed RAM ------------------------------------------------------------------------------- -- File : distributed_stack.vhd -- Author : Gideon Zweijtzer <[email protected]> ------------------------------------------------------------------------------- -- Description: This implementation makes use of the RAMX1 properties, -- implementing a 16-deep synchronous stack in only one LUT per -- bit. The value to be popped is always visible. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity distributed_stack is generic ( Width : integer := 32; simultaneous_pushpop : boolean := false ); port ( clock : in std_logic; reset : in std_logic; pop : in std_logic; push : in std_logic; flush : in std_logic; data_in : in std_logic_vector(Width-1 downto 0); data_out : out std_logic_vector(Width-1 downto 0); full : out std_logic; data_valid : out std_logic ); end distributed_stack; architecture Gideon of distributed_stack is signal pointer : unsigned(3 downto 0); signal address : unsigned(3 downto 0); signal we : std_logic; signal data_valid_i : std_logic; signal full_i : std_logic; signal filtered_pop : std_logic; signal filtered_push : std_logic; signal ram_data : std_logic_vector(Width-1 downto 0); begin filtered_pop <= data_valid_i and pop; filtered_push <= not full_i and push; full <= full_i; process(filtered_push, pop, pointer, ram_data, data_in) begin we <= filtered_push; data_out <= ram_data; data_valid <= data_valid_i; if filtered_push='1' then address <= pointer + 1; else address <= pointer; end if; if simultaneous_pushpop then if filtered_push='1' and pop='1' then data_out <= data_in; we <= '0'; data_valid <= '1'; end if; end if; end process; process(clock) variable new_pointer : unsigned(3 downto 0);--integer range 0 to Depth; begin if rising_edge(clock) then if flush='1' then new_pointer := X"F"; elsif (filtered_pop='1') and (filtered_push='0') then new_pointer := pointer - 1; elsif (filtered_pop='0') and (filtered_push='1') then new_pointer := pointer + 1; else new_pointer := pointer; end if; pointer <= new_pointer; if (new_pointer = X"F") then data_valid_i <= '0'; else data_valid_i <= '1'; end if; if (new_pointer /= X"E") then full_i <= '0'; else full_i <= '1'; end if; if reset='1' then pointer <= X"F"; full_i <= '0'; data_valid_i <= '0'; end if; end if; end process; RAMs : for ram2 in 0 to Width-1 generate i_ram : RAM16X1S port map ( WCLK => clock, WE => we, D => data_in(ram2), A3 => address(3), A2 => address(2), A1 => address(1), A0 => address(0), O => ram_data(ram2) ); end generate; end Gideon;
-- ------------------------------------------------------------- -- -- Entity Declaration for inst_eaa_e -- -- Generated -- by: wig -- on: Mon Mar 22 13:27:43 2004 -- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_eaa_e-e.vhd,v 1.1 2004/04/06 10:49:56 wig Exp $ -- $Date: 2004/04/06 10:49:56 $ -- $Log: inst_eaa_e-e.vhd,v $ -- Revision 1.1 2004/04/06 10:49:56 wig -- Adding result/mde_tests -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp -- -- Generator: mix_0.pl Version: Revision: 1.26 , [email protected] -- (C) 2003 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_eaa_e -- entity inst_eaa_e is -- Generics: -- No Generated Generics for Entity inst_eaa_e -- Generated Port Declaration: port( -- Generated Port for Entity inst_eaa_e mbist_clut_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL mbist_fifo_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL reset_n : in std_ulogic; reset_n_s : in std_ulogic -- End of Generated Port for Entity inst_eaa_e ); end inst_eaa_e; -- -- End of Generated Entity inst_eaa_e -- -- --!End of Entity/ies -- --------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity dpram is generic ( g_width_bits : positive := 16; g_depth_bits : positive := 9; g_read_first_a : boolean := false; g_read_first_b : boolean := false; g_storage : string := "auto" -- can also be "block" or "distributed" ); port ( a_clock : in std_logic; a_address : in unsigned(g_depth_bits-1 downto 0); a_rdata : out std_logic_vector(g_width_bits-1 downto 0); a_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); a_en : in std_logic := '1'; a_we : in std_logic := '0'; b_clock : in std_logic := '0'; b_address : in unsigned(g_depth_bits-1 downto 0) := (others => '0'); b_rdata : out std_logic_vector(g_width_bits-1 downto 0); b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); b_en : in std_logic := '1'; b_we : in std_logic := '0' ); attribute keep_hierarchy : string; attribute keep_hierarchy of dpram : entity is "yes"; end entity; architecture xilinx of dpram is type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0); shared variable ram : t_ram := (others => (others => '0')); -- Xilinx and Altera attributes attribute ram_style : string; attribute ram_style of ram : variable is g_storage; begin ----------------------------------------------------------------------- -- PORT A ----------------------------------------------------------------------- p_port_a: process(a_clock) begin if rising_edge(a_clock) then if a_en = '1' then if g_read_first_a then a_rdata <= ram(to_integer(a_address)); end if; if a_we = '1' then ram(to_integer(a_address)) := a_wdata; end if; if not g_read_first_a then a_rdata <= ram(to_integer(a_address)); end if; end if; end if; end process; ----------------------------------------------------------------------- -- PORT B ----------------------------------------------------------------------- p_port_b: process(b_clock) begin if rising_edge(b_clock) then if b_en = '1' then if g_read_first_b then b_rdata <= ram(to_integer(b_address)); end if; if b_we = '1' then ram(to_integer(b_address)) := b_wdata; end if; if not g_read_first_b then b_rdata <= ram(to_integer(b_address)); end if; end if; end if; end process; end architecture;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity dpram is generic ( g_width_bits : positive := 16; g_depth_bits : positive := 9; g_read_first_a : boolean := false; g_read_first_b : boolean := false; g_storage : string := "auto" -- can also be "block" or "distributed" ); port ( a_clock : in std_logic; a_address : in unsigned(g_depth_bits-1 downto 0); a_rdata : out std_logic_vector(g_width_bits-1 downto 0); a_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); a_en : in std_logic := '1'; a_we : in std_logic := '0'; b_clock : in std_logic := '0'; b_address : in unsigned(g_depth_bits-1 downto 0) := (others => '0'); b_rdata : out std_logic_vector(g_width_bits-1 downto 0); b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); b_en : in std_logic := '1'; b_we : in std_logic := '0' ); attribute keep_hierarchy : string; attribute keep_hierarchy of dpram : entity is "yes"; end entity; architecture xilinx of dpram is type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0); shared variable ram : t_ram := (others => (others => '0')); -- Xilinx and Altera attributes attribute ram_style : string; attribute ram_style of ram : variable is g_storage; begin ----------------------------------------------------------------------- -- PORT A ----------------------------------------------------------------------- p_port_a: process(a_clock) begin if rising_edge(a_clock) then if a_en = '1' then if g_read_first_a then a_rdata <= ram(to_integer(a_address)); end if; if a_we = '1' then ram(to_integer(a_address)) := a_wdata; end if; if not g_read_first_a then a_rdata <= ram(to_integer(a_address)); end if; end if; end if; end process; ----------------------------------------------------------------------- -- PORT B ----------------------------------------------------------------------- p_port_b: process(b_clock) begin if rising_edge(b_clock) then if b_en = '1' then if g_read_first_b then b_rdata <= ram(to_integer(b_address)); end if; if b_we = '1' then ram(to_integer(b_address)) := b_wdata; end if; if not g_read_first_b then b_rdata <= ram(to_integer(b_address)); end if; end if; end if; end process; end architecture;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity dpram is generic ( g_width_bits : positive := 16; g_depth_bits : positive := 9; g_read_first_a : boolean := false; g_read_first_b : boolean := false; g_storage : string := "auto" -- can also be "block" or "distributed" ); port ( a_clock : in std_logic; a_address : in unsigned(g_depth_bits-1 downto 0); a_rdata : out std_logic_vector(g_width_bits-1 downto 0); a_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); a_en : in std_logic := '1'; a_we : in std_logic := '0'; b_clock : in std_logic := '0'; b_address : in unsigned(g_depth_bits-1 downto 0) := (others => '0'); b_rdata : out std_logic_vector(g_width_bits-1 downto 0); b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); b_en : in std_logic := '1'; b_we : in std_logic := '0' ); attribute keep_hierarchy : string; attribute keep_hierarchy of dpram : entity is "yes"; end entity; architecture xilinx of dpram is type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0); shared variable ram : t_ram := (others => (others => '0')); -- Xilinx and Altera attributes attribute ram_style : string; attribute ram_style of ram : variable is g_storage; begin ----------------------------------------------------------------------- -- PORT A ----------------------------------------------------------------------- p_port_a: process(a_clock) begin if rising_edge(a_clock) then if a_en = '1' then if g_read_first_a then a_rdata <= ram(to_integer(a_address)); end if; if a_we = '1' then ram(to_integer(a_address)) := a_wdata; end if; if not g_read_first_a then a_rdata <= ram(to_integer(a_address)); end if; end if; end if; end process; ----------------------------------------------------------------------- -- PORT B ----------------------------------------------------------------------- p_port_b: process(b_clock) begin if rising_edge(b_clock) then if b_en = '1' then if g_read_first_b then b_rdata <= ram(to_integer(b_address)); end if; if b_we = '1' then ram(to_integer(b_address)) := b_wdata; end if; if not g_read_first_b then b_rdata <= ram(to_integer(b_address)); end if; end if; end if; end process; end architecture;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity dpram is generic ( g_width_bits : positive := 16; g_depth_bits : positive := 9; g_read_first_a : boolean := false; g_read_first_b : boolean := false; g_storage : string := "auto" -- can also be "block" or "distributed" ); port ( a_clock : in std_logic; a_address : in unsigned(g_depth_bits-1 downto 0); a_rdata : out std_logic_vector(g_width_bits-1 downto 0); a_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); a_en : in std_logic := '1'; a_we : in std_logic := '0'; b_clock : in std_logic := '0'; b_address : in unsigned(g_depth_bits-1 downto 0) := (others => '0'); b_rdata : out std_logic_vector(g_width_bits-1 downto 0); b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); b_en : in std_logic := '1'; b_we : in std_logic := '0' ); attribute keep_hierarchy : string; attribute keep_hierarchy of dpram : entity is "yes"; end entity; architecture xilinx of dpram is type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0); shared variable ram : t_ram := (others => (others => '0')); -- Xilinx and Altera attributes attribute ram_style : string; attribute ram_style of ram : variable is g_storage; begin ----------------------------------------------------------------------- -- PORT A ----------------------------------------------------------------------- p_port_a: process(a_clock) begin if rising_edge(a_clock) then if a_en = '1' then if g_read_first_a then a_rdata <= ram(to_integer(a_address)); end if; if a_we = '1' then ram(to_integer(a_address)) := a_wdata; end if; if not g_read_first_a then a_rdata <= ram(to_integer(a_address)); end if; end if; end if; end process; ----------------------------------------------------------------------- -- PORT B ----------------------------------------------------------------------- p_port_b: process(b_clock) begin if rising_edge(b_clock) then if b_en = '1' then if g_read_first_b then b_rdata <= ram(to_integer(b_address)); end if; if b_we = '1' then ram(to_integer(b_address)) := b_wdata; end if; if not g_read_first_b then b_rdata <= ram(to_integer(b_address)); end if; end if; end if; end process; end architecture;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity dpram is generic ( g_width_bits : positive := 16; g_depth_bits : positive := 9; g_read_first_a : boolean := false; g_read_first_b : boolean := false; g_storage : string := "auto" -- can also be "block" or "distributed" ); port ( a_clock : in std_logic; a_address : in unsigned(g_depth_bits-1 downto 0); a_rdata : out std_logic_vector(g_width_bits-1 downto 0); a_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); a_en : in std_logic := '1'; a_we : in std_logic := '0'; b_clock : in std_logic := '0'; b_address : in unsigned(g_depth_bits-1 downto 0) := (others => '0'); b_rdata : out std_logic_vector(g_width_bits-1 downto 0); b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0'); b_en : in std_logic := '1'; b_we : in std_logic := '0' ); attribute keep_hierarchy : string; attribute keep_hierarchy of dpram : entity is "yes"; end entity; architecture xilinx of dpram is type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0); shared variable ram : t_ram := (others => (others => '0')); -- Xilinx and Altera attributes attribute ram_style : string; attribute ram_style of ram : variable is g_storage; begin ----------------------------------------------------------------------- -- PORT A ----------------------------------------------------------------------- p_port_a: process(a_clock) begin if rising_edge(a_clock) then if a_en = '1' then if g_read_first_a then a_rdata <= ram(to_integer(a_address)); end if; if a_we = '1' then ram(to_integer(a_address)) := a_wdata; end if; if not g_read_first_a then a_rdata <= ram(to_integer(a_address)); end if; end if; end if; end process; ----------------------------------------------------------------------- -- PORT B ----------------------------------------------------------------------- p_port_b: process(b_clock) begin if rising_edge(b_clock) then if b_en = '1' then if g_read_first_b then b_rdata <= ram(to_integer(b_address)); end if; if b_we = '1' then ram(to_integer(b_address)) := b_wdata; end if; if not g_read_first_b then b_rdata <= ram(to_integer(b_address)); end if; end if; end if; end process; end architecture;
library ieee; use ieee.std_logic_1164.all; entity clkgen is generic (period : time := 10 ns); port (signal clk : out std_logic := '0'); end clkgen; architecture behav of clkgen is begin process begin "xxx" . null; end process; end behav;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library std; entity conv_slave is generic ( CLK_PROC_FREQ : integer ); port ( clk_proc : in std_logic; reset_n : in std_logic; ---------------- dynamic parameters ports --------------- status_reg_enable_bit : out std_logic; widthimg_reg_width : out std_logic_vector(15 downto 0); w00_reg_m00 : out std_logic_vector(7 downto 0); w01_reg_m01 : out std_logic_vector(7 downto 0); w02_reg_m02 : out std_logic_vector(7 downto 0); w10_reg_m10 : out std_logic_vector(7 downto 0); w11_reg_m11 : out std_logic_vector(7 downto 0); w12_reg_m12 : out std_logic_vector(7 downto 0); w20_reg_m20 : out std_logic_vector(7 downto 0); w21_reg_m21 : out std_logic_vector(7 downto 0); w22_reg_m22 : out std_logic_vector(7 downto 0); norm_reg_norm : out std_logic_vector(3 downto 0); --======================= Slaves ======================== ------------------------- bus_sl ------------------------ addr_rel_i : in std_logic_vector(3 downto 0); wr_i : in std_logic; rd_i : in std_logic; datawr_i : in std_logic_vector(31 downto 0); datard_o : out std_logic_vector(31 downto 0) ); end conv_slave; architecture rtl of conv_slave is -- Registers address constant STATUS_REG_REG_ADDR : natural := 0; constant WIDTHIMG_REG_REG_ADDR : natural := 1; constant W00_REG_REG_ADDR : natural := 2; constant W01_REG_REG_ADDR : natural := 3; constant W02_REG_REG_ADDR : natural := 4; constant W10_REG_REG_ADDR : natural := 5; constant W11_REG_REG_ADDR : natural := 6; constant W12_REG_REG_ADDR : natural := 7; constant W20_REG_REG_ADDR : natural := 8; constant W21_REG_REG_ADDR : natural := 9; constant W22_REG_REG_ADDR : natural := 10; constant NORM_REG_REG_ADDR : natural := 11; -- Internal registers signal status_reg_enable_bit_reg : std_logic; signal widthimg_reg_width_reg : std_logic_vector (15 downto 0); signal w00_reg_m00_reg : std_logic_vector (7 downto 0); signal w01_reg_m01_reg : std_logic_vector (7 downto 0); signal w02_reg_m02_reg : std_logic_vector (7 downto 0); signal w10_reg_m10_reg : std_logic_vector (7 downto 0); signal w11_reg_m11_reg : std_logic_vector (7 downto 0); signal w12_reg_m12_reg : std_logic_vector (7 downto 0); signal w20_reg_m20_reg : std_logic_vector (7 downto 0); signal w21_reg_m21_reg : std_logic_vector (7 downto 0); signal w22_reg_m22_reg : std_logic_vector (7 downto 0); signal norm_reg_norm_reg : std_logic_vector (3 downto 0); begin write_reg : process (clk_proc, reset_n) begin if(reset_n='0') then status_reg_enable_bit_reg <= '0'; widthimg_reg_width_reg <= "0000000000000000"; w00_reg_m00_reg <= "00000000"; w01_reg_m01_reg <= "00000000"; w02_reg_m02_reg <= "00000000"; w10_reg_m10_reg <= "00000000"; w11_reg_m11_reg <= "00000000"; w12_reg_m12_reg <= "00000000"; w20_reg_m20_reg <= "00000000"; w21_reg_m21_reg <= "00000000"; w22_reg_m22_reg <= "00000000"; norm_reg_norm_reg <= "0000"; elsif(rising_edge(clk_proc)) then if(wr_i='1') then case to_integer(unsigned(addr_rel_i)) is when STATUS_REG_REG_ADDR => status_reg_enable_bit_reg <= datawr_i(0); when WIDTHIMG_REG_REG_ADDR => widthimg_reg_width_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0); when W00_REG_REG_ADDR => w00_reg_m00_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0); when W01_REG_REG_ADDR => w01_reg_m01_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0); when W02_REG_REG_ADDR => w02_reg_m02_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0); when W10_REG_REG_ADDR => w10_reg_m10_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0); when W11_REG_REG_ADDR => w11_reg_m11_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0); when W12_REG_REG_ADDR => w12_reg_m12_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0); when W20_REG_REG_ADDR => w20_reg_m20_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0); when W21_REG_REG_ADDR => w21_reg_m21_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0); when W22_REG_REG_ADDR => w22_reg_m22_reg <= datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0); when NORM_REG_REG_ADDR => norm_reg_norm_reg <= datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0); when others=> end case; end if; end if; end process; read_reg : process (clk_proc, reset_n) begin if(reset_n='0') then datard_o <= (others => '0'); elsif(rising_edge(clk_proc)) then if(rd_i='1') then case to_integer(unsigned(addr_rel_i)) is when STATUS_REG_REG_ADDR => datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg; when WIDTHIMG_REG_REG_ADDR => datard_o <= "0000000000000000" & widthimg_reg_width_reg(15) & widthimg_reg_width_reg(14) & widthimg_reg_width_reg(13) & widthimg_reg_width_reg(12) & widthimg_reg_width_reg(11) & widthimg_reg_width_reg(10) & widthimg_reg_width_reg(9) & widthimg_reg_width_reg(8) & widthimg_reg_width_reg(7) & widthimg_reg_width_reg(6) & widthimg_reg_width_reg(5) & widthimg_reg_width_reg(4) & widthimg_reg_width_reg(3) & widthimg_reg_width_reg(2) & widthimg_reg_width_reg(1) & widthimg_reg_width_reg(0); when W00_REG_REG_ADDR => datard_o <= "000000000000000000000000" & w00_reg_m00_reg(7) & w00_reg_m00_reg(6) & w00_reg_m00_reg(5) & w00_reg_m00_reg(4) & w00_reg_m00_reg(3) & w00_reg_m00_reg(2) & w00_reg_m00_reg(1) & w00_reg_m00_reg(0); when W01_REG_REG_ADDR => datard_o <= "000000000000000000000000" & w01_reg_m01_reg(7) & w01_reg_m01_reg(6) & w01_reg_m01_reg(5) & w01_reg_m01_reg(4) & w01_reg_m01_reg(3) & w01_reg_m01_reg(2) & w01_reg_m01_reg(1) & w01_reg_m01_reg(0); when W02_REG_REG_ADDR => datard_o <= "000000000000000000000000" & w02_reg_m02_reg(7) & w02_reg_m02_reg(6) & w02_reg_m02_reg(5) & w02_reg_m02_reg(4) & w02_reg_m02_reg(3) & w02_reg_m02_reg(2) & w02_reg_m02_reg(1) & w02_reg_m02_reg(0); when W10_REG_REG_ADDR => datard_o <= "000000000000000000000000" & w10_reg_m10_reg(7) & w10_reg_m10_reg(6) & w10_reg_m10_reg(5) & w10_reg_m10_reg(4) & w10_reg_m10_reg(3) & w10_reg_m10_reg(2) & w10_reg_m10_reg(1) & w10_reg_m10_reg(0); when W11_REG_REG_ADDR => datard_o <= "000000000000000000000000" & w11_reg_m11_reg(7) & w11_reg_m11_reg(6) & w11_reg_m11_reg(5) & w11_reg_m11_reg(4) & w11_reg_m11_reg(3) & w11_reg_m11_reg(2) & w11_reg_m11_reg(1) & w11_reg_m11_reg(0); when W12_REG_REG_ADDR => datard_o <= "000000000000000000000000" & w12_reg_m12_reg(7) & w12_reg_m12_reg(6) & w12_reg_m12_reg(5) & w12_reg_m12_reg(4) & w12_reg_m12_reg(3) & w12_reg_m12_reg(2) & w12_reg_m12_reg(1) & w12_reg_m12_reg(0); when W20_REG_REG_ADDR => datard_o <= "000000000000000000000000" & w20_reg_m20_reg(7) & w20_reg_m20_reg(6) & w20_reg_m20_reg(5) & w20_reg_m20_reg(4) & w20_reg_m20_reg(3) & w20_reg_m20_reg(2) & w20_reg_m20_reg(1) & w20_reg_m20_reg(0); when W21_REG_REG_ADDR => datard_o <= "000000000000000000000000" & w21_reg_m21_reg(7) & w21_reg_m21_reg(6) & w21_reg_m21_reg(5) & w21_reg_m21_reg(4) & w21_reg_m21_reg(3) & w21_reg_m21_reg(2) & w21_reg_m21_reg(1) & w21_reg_m21_reg(0); when W22_REG_REG_ADDR => datard_o <= "000000000000000000000000" & w22_reg_m22_reg(7) & w22_reg_m22_reg(6) & w22_reg_m22_reg(5) & w22_reg_m22_reg(4) & w22_reg_m22_reg(3) & w22_reg_m22_reg(2) & w22_reg_m22_reg(1) & w22_reg_m22_reg(0); when NORM_REG_REG_ADDR => datard_o <= "0000000000000000000000000000" & norm_reg_norm_reg(3) & norm_reg_norm_reg(2) & norm_reg_norm_reg(1) & norm_reg_norm_reg(0); when others=> datard_o <= (others => '0'); end case; end if; end if; end process; status_reg_enable_bit <= status_reg_enable_bit_reg; widthimg_reg_width <= widthimg_reg_width_reg; w00_reg_m00 <= w00_reg_m00_reg; w01_reg_m01 <= w01_reg_m01_reg; w02_reg_m02 <= w02_reg_m02_reg; w10_reg_m10 <= w10_reg_m10_reg; w11_reg_m11 <= w11_reg_m11_reg; w12_reg_m12 <= w12_reg_m12_reg; w20_reg_m20 <= w20_reg_m20_reg; w21_reg_m21 <= w21_reg_m21_reg; w22_reg_m22 <= w22_reg_m22_reg; norm_reg_norm <= norm_reg_norm_reg; end rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_misc.all; -- ****************************************************************************** -- * License Agreement * -- * * -- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. * -- * All rights reserved. * -- * * -- * Any megafunction design, and related net list (encrypted or decrypted), * -- * support information, device programming or simulation file, and any other * -- * associated documentation or information provided by Altera or a partner * -- * under Altera's Megafunction Partnership Program may be used only to * -- * program PLD devices (but not masked PLD devices) from Altera. Any other * -- * use of such megafunction design, net list, support information, device * -- * programming or simulation file, or any other related documentation or * -- * information is prohibited for any other purpose, including, but not * -- * limited to modification, reverse engineering, de-compiling, or use with * -- * any other silicon devices, unless such use is explicitly licensed under * -- * a separate agreement with Altera or a megafunction partner. Title to * -- * the intellectual property, including patents, copyrights, trademarks, * -- * trade secrets, or maskworks, embodied in any such megafunction design, * -- * net list, support information, device programming or simulation file, or * -- * any other related documentation or information provided by Altera or a * -- * megafunction partner, remains with Altera, the megafunction partner, or * -- * their respective licensors. No other licenses, including any licenses * -- * needed under any third party's intellectual property, are provided herein.* -- * Copying or modifying any file, or portion thereof, to which this notice * -- * is attached violates this copyright. * -- * * -- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * -- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS * -- * IN THIS FILE. * -- * * -- * This agreement shall be governed in all respects by the laws of the State * -- * of California and by the laws of the United States of America. * -- * * -- ****************************************************************************** -- ****************************************************************************** -- * * -- * This module scales video streams on the DE boards. * -- * * -- ****************************************************************************** ENTITY Video_System_Pixel_Scaler IS -- ***************************************************************************** -- * Generic Declarations * -- ***************************************************************************** GENERIC ( DW :INTEGER := 29; -- Frame's Data Width EW :INTEGER := 1; -- Frame's Empty Width WIW :INTEGER := 8; -- Incoming frame's width's address width HIW :INTEGER := 7; -- Incoming frame's height's address width WIDTH_IN :INTEGER := 320; WIDTH_DROP_MASK :STD_LOGIC_VECTOR( 3 DOWNTO 0) := B"0000"; HEIGHT_DROP_MASK :STD_LOGIC_VECTOR( 3 DOWNTO 0) := B"0000"; MH_WW :INTEGER := 8; -- Multiply height's incoming width's address width MH_WIDTH_IN :INTEGER := 320; -- Multiply height's incoming width MH_CW :INTEGER := 0; -- Multiply height's counter width MW_CW :INTEGER := 0 -- Multiply width's counter width ); -- ***************************************************************************** -- * Port Declarations * -- ***************************************************************************** PORT ( -- Inputs clk :IN STD_LOGIC; reset :IN STD_LOGIC; stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0); stream_in_startofpacket :IN STD_LOGIC; stream_in_endofpacket :IN STD_LOGIC; stream_in_empty :IN STD_LOGIC_VECTOR(EW DOWNTO 0); stream_in_valid :IN STD_LOGIC; stream_out_ready :IN STD_LOGIC; -- Bidirectional -- Outputs stream_in_ready :BUFFER STD_LOGIC; stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0); stream_out_startofpacket :BUFFER STD_LOGIC; stream_out_endofpacket :BUFFER STD_LOGIC; stream_out_empty :BUFFER STD_LOGIC_VECTOR(EW DOWNTO 0); stream_out_valid :BUFFER STD_LOGIC ); END Video_System_Pixel_Scaler; ARCHITECTURE Behaviour OF Video_System_Pixel_Scaler IS -- ***************************************************************************** -- * Constant Declarations * -- ***************************************************************************** -- ***************************************************************************** -- * Internal Signals Declarations * -- ***************************************************************************** -- Internal Wires SIGNAL internal_data :STD_LOGIC_VECTOR(DW DOWNTO 0); SIGNAL internal_startofpacket :STD_LOGIC; SIGNAL internal_endofpacket :STD_LOGIC; SIGNAL internal_valid :STD_LOGIC; SIGNAL internal_ready :STD_LOGIC; -- Internal Registers -- State Machine Registers -- Integers -- ***************************************************************************** -- * Component Declarations * -- ***************************************************************************** COMPONENT altera_up_video_scaler_multiply_height GENERIC ( DW :INTEGER; WW :INTEGER; WIDTH :INTEGER; CW :INTEGER ); PORT ( -- Inputs clk :IN STD_LOGIC; reset :IN STD_LOGIC; stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0); stream_in_startofpacket :IN STD_LOGIC; stream_in_endofpacket :IN STD_LOGIC; stream_in_valid :IN STD_LOGIC; stream_out_ready :IN STD_LOGIC; -- Bi-Directional -- Outputs stream_in_ready :BUFFER STD_LOGIC; stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0); stream_out_startofpacket :BUFFER STD_LOGIC; stream_out_endofpacket :BUFFER STD_LOGIC; stream_out_valid :BUFFER STD_LOGIC ); END COMPONENT; COMPONENT altera_up_video_scaler_multiply_width GENERIC ( DW :INTEGER; CW :INTEGER ); PORT ( -- Inputs clk :IN STD_LOGIC; reset :IN STD_LOGIC; stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0); stream_in_startofpacket :IN STD_LOGIC; stream_in_endofpacket :IN STD_LOGIC; stream_in_valid :IN STD_LOGIC; stream_out_ready :IN STD_LOGIC; -- Bi-Directional -- Outputs stream_in_ready :BUFFER STD_LOGIC; stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0); stream_out_startofpacket :BUFFER STD_LOGIC; stream_out_endofpacket :BUFFER STD_LOGIC; stream_out_valid :BUFFER STD_LOGIC ); END COMPONENT; BEGIN -- ***************************************************************************** -- * Finite State Machine(s) * -- ***************************************************************************** -- ***************************************************************************** -- * Sequential Logic * -- ***************************************************************************** -- Output Registers -- Internal Registers -- ***************************************************************************** -- * Combinational Logic * -- ***************************************************************************** -- Output Assignments stream_out_empty <= (OTHERS => '0'); -- Internal Assignments -- ***************************************************************************** -- * Component Instantiations * -- ***************************************************************************** Multiply_Height : altera_up_video_scaler_multiply_height GENERIC MAP ( DW => DW, WW => MH_WW, WIDTH => MH_WIDTH_IN, CW => MH_CW ) PORT MAP ( -- Inputs clk => clk, reset => reset, stream_in_data => stream_in_data, stream_in_startofpacket => stream_in_startofpacket, stream_in_endofpacket => stream_in_endofpacket, stream_in_valid => stream_in_valid, stream_out_ready => internal_ready, -- Bi-Directional -- Outputs stream_in_ready => stream_in_ready, stream_out_data => internal_data, stream_out_startofpacket => internal_startofpacket, stream_out_endofpacket => internal_endofpacket, stream_out_valid => internal_valid ); Multiply_Width : altera_up_video_scaler_multiply_width GENERIC MAP ( DW => DW, CW => MW_CW ) PORT MAP ( -- Inputs clk => clk, reset => reset, stream_in_data => internal_data, stream_in_startofpacket => internal_startofpacket, stream_in_endofpacket => internal_endofpacket, stream_in_valid => internal_valid, stream_out_ready => stream_out_ready, -- Bi-Directional -- Outputs stream_in_ready => internal_ready, stream_out_data => stream_out_data, stream_out_startofpacket => stream_out_startofpacket, stream_out_endofpacket => stream_out_endofpacket, stream_out_valid => stream_out_valid ); END Behaviour;
-- The order of design units in the file is significant package pack1 is type SharedCounter is protected procedure increment (N: Integer := 1); procedure decrement (N: Integer := 1); impure function value return Integer; end protected SharedCounter; end package; ------------------------------------------------------------------------------- use work.pack1.all; package pack2 is shared variable sv : SharedCounter; end package; ------------------------------------------------------------------------------- entity protected5 is end entity; use work.pack2.all; architecture test of protected5 is begin p1: process is begin sv.increment; sv.increment; wait for 0 ns; assert sv.value = 3; wait; end process; p2: process is begin sv.increment; wait; end process; end architecture; ------------------------------------------------------------------------------- package body pack1 is type SharedCounter is protected body variable counter: Integer := 0; procedure increment (N: Integer := 1) is begin counter := counter + N; end procedure increment; procedure decrement (N: Integer := 1) is begin counter := counter - N; end procedure decrement; impure function value return Integer is begin return counter; end function value; end protected body; end package body;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity DoubleSingleWordVoter is port( clk : in STD_LOGIC; rst : in STD_LOGIC; inputReady : in STD_LOGIC; outputReady : out STD_LOGIC; done : out STD_LOGIC; stall : in STD_LOGIC; error : out STD_LOGIC; val0_in : in STD_LOGIC_VECTOR(31 downto 0); val1_in : in STD_LOGIC_VECTOR(31 downto 0); val2_in : in STD_LOGIC_VECTOR(31 downto 0); val0_out : out STD_LOGIC_VECTOR(31 downto 0); val1_out : out STD_LOGIC_VECTOR(31 downto 0); val2_out : out STD_LOGIC_VECTOR(31 downto 0) ); end DoubleSingleWordVoter; architecture Behavioral of DoubleSingleWordVoter is begin process(clk, rst) begin if( rst = '1' ) then elsif( clk'event and clk = '1' ) then val0_out <= (others=>'0'); val1_out <= (others=>'0'); val2_out <= (others=>'0'); error <= '1'; if( val0_in = val1_in ) then val0_out <= val0_in; val1_out <= val0_in; val2_out <= val0_in; error <= '0'; end if; end if; end process; end Behavioral;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015 - 2016, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- -- Entity: eth_edcl_ahb_mst -- File: eth_edcl_ahb_mst.vhd -- Author: Marko Isomaki - Gaisler Research -- Description: Ethernet EDCL MAC AHB master interface ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.stdlib.all; library eth; use eth.grethpkg.all; entity eth_edcl_ahb_mst is port( rst : in std_ulogic; clk : in std_ulogic; ahbmi : in ahbc_mst_in_type; ahbmo : out ahbc_mst_out_type; tmsti : in eth_tx_ahb_in_type; tmsto : out eth_tx_ahb_out_type ); attribute sync_set_reset of rst : signal is "true"; end entity; architecture rtl of eth_edcl_ahb_mst is type reg_type is record bg : std_ulogic; --bus granted ba : std_ulogic; --bus active bb : std_ulogic; --1kB burst boundary detected retry : std_ulogic; end record; signal r, rin : reg_type; begin comb : process(rst, r, tmsti, ahbmi) is variable v : reg_type; variable htrans : std_logic_vector(1 downto 0); variable hbusreq : std_ulogic; variable hwrite : std_ulogic; variable haddr : std_logic_vector(31 downto 0); variable hwdata : std_logic_vector(31 downto 0); variable tretry : std_ulogic; variable tready : std_ulogic; variable terror : std_ulogic; variable tgrant : std_ulogic; variable hsize : std_logic_vector(2 downto 0); begin v := r; htrans := HTRANS_IDLE; tready := '0'; tretry := '0'; terror := '0'; tgrant := '0'; hsize := HSIZE_WORD; hwdata := tmsti.data; hbusreq := tmsti.req; if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if; haddr := tmsti.addr; hwrite := tmsti.write; if (tmsti.req and r.ba and not r.retry) = '1' then htrans := HTRANS_SEQ; end if; if (tmsti.req and r.bg and ahbmi.hready and not r.retry) = '1' then tgrant := '1'; end if; --1 kB burst boundary if ahbmi.hready = '1' then if haddr(9 downto 2) = "11111111" then v.bb := '1'; else v.bb := '0'; end if; end if; if (r.bb = '1') and (htrans /= HTRANS_IDLE) then htrans := HTRANS_NONSEQ; end if; if r.ba = '1' then if ahbmi.hready = '1' then case ahbmi.hresp is when HRESP_OKAY => tready := '1'; when HRESP_SPLIT | HRESP_RETRY => tretry := '1'; when HRESP_ERROR => terror := '1'; when others => null; end case; end if; end if; if (r.ba = '1') and ((ahbmi.hresp = HRESP_RETRY) or (ahbmi.hresp = HRESP_SPLIT)) then v.retry := not ahbmi.hready; else v.retry := '0'; end if; if r.retry = '1' then htrans := HTRANS_IDLE; end if; if ahbmi.hready = '1' then v.bg := ahbmi.hgrant; if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then v.ba := r.bg; else v.ba := '0'; end if; end if; if rst = '0' then v.bg := '0'; v.ba := '0'; v.bb := '0'; end if; rin <= v; tmsto.data <= ahbmi.hrdata; tmsto.error <= terror; tmsto.retry <= tretry; tmsto.ready <= tready; tmsto.grant <= tgrant; ahbmo.htrans <= htrans; ahbmo.hsize <= hsize; ahbmo.hbusreq <= hbusreq; ahbmo.haddr <= haddr; ahbmo.hwrite <= hwrite; ahbmo.hwdata <= hwdata; end process; regs : process(clk) begin if rising_edge(clk) then r <= rin; end if; end process; ahbmo.hlock <= '0'; ahbmo.hburst <= HBURST_INCR; ahbmo.hprot <= "0011"; end architecture;
----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library gaisler; use gaisler.libdcom.all; use gaisler.sim.all; use work.debug.all; library techmap; use techmap.gencomp.all; library micron; use micron.components.all; use work.config.all; -- configuration entity testbench is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; clkperiod : integer := 16; -- system clock period comboard : integer := 1 -- Comms. adapter board attached ); port ( pci_rst : out std_logic; pci_clk : in std_logic; pci_gnt : in std_logic; pci_idsel : in std_logic; pci_lock : inout std_logic; pci_ad : inout std_logic_vector(31 downto 0); pci_cbe : inout std_logic_vector(3 downto 0); pci_frame : inout std_logic; pci_irdy : inout std_logic; pci_trdy : inout std_logic; pci_devsel : inout std_logic; pci_stop : inout std_logic; pci_perr : inout std_logic; pci_par : inout std_logic; pci_req : inout std_logic; pci_serr : inout std_logic; pci_host : in std_logic; pci_66 : in std_logic ); end; architecture behav of testbench is constant promfile : string := "prom.srec"; -- rom contents constant sramfile : string := "ram.srec"; -- ram contents constant sdramfile : string := "ram.srec"; -- sdram contents component leon3mp generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; mezz : integer := CFG_ADS_DAU_MEZZ ); port ( clk_66mhz : in std_logic; clk_socket : in std_logic; leds : out std_logic_vector(7 downto 0); switches : in std_logic_vector(5 downto 0); sram_a : out std_logic_vector(24 downto 0); sram_ben_l : out std_logic_vector(0 to 3); sram_cs_l : out std_logic_vector(1 downto 0); sram_oe_l : out std_logic; sram_we_l : out std_logic; sram_dq : inout std_logic_vector(31 downto 0); flash_cs_l : out std_logic; flash_rst_l : out std_logic; iosn : out std_logic; sdclk : out std_logic; rasn : out std_logic; casn : out std_logic; sdcke : out std_logic; sdcsn : out std_logic; tx : out std_logic; rx : in std_logic; can_txd : out std_logic; can_rxd : in std_logic; phy_txck : in std_logic; phy_rxck : in std_logic; phy_rxd : in std_logic_vector(3 downto 0); phy_rxdv : in std_logic; phy_rxer : in std_logic; phy_col : in std_logic; phy_crs : in std_logic; phy_txd : out std_logic_vector(3 downto 0); phy_txen : out std_logic; phy_txer : out std_logic; phy_mdc : out std_logic; phy_mdio : inout std_logic; -- ethernet PHY interface phy_reset_l : inout std_logic; video_clk : in std_logic; comp_sync : out std_logic; blank : out std_logic; video_out : out std_logic_vector(23 downto 0); msclk : inout std_logic; msdata : inout std_logic; kbclk : inout std_logic; kbdata : inout std_logic; disp_seg1 : out std_logic_vector(7 downto 0); disp_seg2 : out std_logic_vector(7 downto 0); pci_clk : in std_logic; pci_gnt : in std_logic; pci_idsel : in std_logic; pci_lock : inout std_logic; pci_ad : inout std_logic_vector(31 downto 0); pci_cbe : inout std_logic_vector(3 downto 0); pci_frame : inout std_logic; pci_irdy : inout std_logic; pci_trdy : inout std_logic; pci_devsel : inout std_logic; pci_stop : inout std_logic; pci_perr : inout std_logic; pci_par : inout std_logic; pci_req : inout std_logic; pci_serr : inout std_logic; pci_host : in std_logic; pci_66 : in std_logic ); end component; signal clk : std_logic := '0'; constant ct : integer := clkperiod/2; signal gnd : std_logic := '0'; signal vcc : std_logic := '1'; signal sdcke : std_logic; signal sdcsn : std_logic; signal sdwen : std_logic; -- write en signal sdrasn : std_logic; -- row addr stb signal sdcasn : std_logic; -- col addr stb signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask signal sdclk : std_logic; signal plllock : std_logic; signal tx, rx : std_logic; signal dsutx, dsurx : std_logic; signal leds : std_logic_vector(7 downto 0); signal switches : std_logic_vector(5 downto 0); constant lresp : boolean := false; signal sram_oe_l, sram_we_l : std_logic; signal sram_cs_l : std_logic_vector(1 downto 0); signal sram_ben_l : std_logic_vector(0 to 3); signal sram_dq : std_logic_vector(31 downto 0); signal flash_cs_l, flash_rst_l : std_logic; signal iosn : std_logic; signal phy_txck : std_logic; signal phy_rxck : std_logic; signal phy_rxd : std_logic_vector(3 downto 0); signal phy_rxdt : std_logic_vector(7 downto 0); signal phy_rxdv : std_logic; signal phy_rxer : std_logic; signal phy_col : std_logic; signal phy_crs : std_logic; signal phy_txd : std_logic_vector(3 downto 0); signal phy_txdt : std_logic_vector(7 downto 0); signal phy_txen : std_logic; signal phy_txer : std_logic; signal phy_mdc : std_logic; signal phy_mdio : std_logic; signal phy_reset_l : std_logic; signal phy_gtx_clk : std_logic := '0'; signal video_clk : std_logic := '0'; signal comp_sync : std_logic; signal blank : std_logic; signal video_out : std_logic_vector(23 downto 0); signal msclk : std_logic; signal msdata : std_logic; signal kbclk : std_logic; signal kbdata : std_logic; signal dsurst : std_logic; signal disp_seg1 : std_logic_vector(7 downto 0); signal disp_seg2 : std_logic_vector(7 downto 0); signal baddr : std_logic_vector(27 downto 0) := (others => '0'); signal can_txd : std_logic; signal can_rxd : std_logic; begin -- clock and reset clk <= not clk after ct * 1 ns; switches(0) <= '1'; -- DSUEN switches(4) <= not dsurst; -- reset switches(5) <= '0'; -- DSUBRE dsutx <= tx; rx <= dsurx; pci_rst <= phy_reset_l; phy_reset_l <= 'H'; video_clk <= not video_clk after 20 ns; can_rxd <= can_txd; sddqm(3) <= sram_ben_l(0); sddqm(2) <= sram_ben_l(1); sddqm(1) <= sram_ben_l(2); sddqm(0) <= sram_ben_l(3); cpu : leon3mp generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow ) port map (clk, sdclk, leds, switches, baddr(24 downto 0), sram_ben_l, sram_cs_l, sram_oe_l, sram_we_l, sram_dq, flash_cs_l, flash_rst_l, iosn, sdclk, sdrasn, sdcasn, sdcke, sdcsn, tx, rx, can_txd, can_rxd, phy_txck, phy_rxck, phy_rxd, phy_rxdv, phy_rxer, phy_col, phy_crs, phy_txd, phy_txen, phy_txer, phy_mdc, phy_mdio, phy_reset_l, video_clk, comp_sync, blank, video_out, msclk, msdata, kbclk, kbdata, disp_seg1, disp_seg2, pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par, pci_req, pci_serr, pci_host, pci_66); -- One 32-bit SRAM bank on main board sram0 : for i in 0 to 1 generate sr0 : sram16 generic map (index => i*2, abits => 18, fname => sramfile) port map (baddr(17 downto 0), sram_dq(31-i*16 downto 16-i*16), sram_ben_l(i*2), sram_ben_l(i*2+1), sram_cs_l(0), sram_we_l, sram_oe_l); end generate; phy_mdio <= 'H'; phy_rxd <= phy_rxdt(3 downto 0); phy_txdt <= "0000" & phy_txd; p0: phy generic map(base1000_t_fd => 0, base1000_t_hd => 0) port map(dsurst, phy_mdio, phy_txck, phy_rxck, phy_rxdt, phy_rxdv, phy_rxer, phy_col, phy_crs, phy_txdt, phy_txen, phy_txer, phy_mdc, phy_gtx_clk); -- optional communications adapter comms : if (comboard = 1) generate -- 32-bit flash prom flash0 : for i in 0 to 1 generate sr0 : sram16 generic map (index => i*2, abits => 18, fname => promfile) port map (baddr(19 downto 2), sram_dq(31-i*16 downto 16-i*16), flash_cs_l, flash_cs_l, flash_cs_l, sram_we_l, sram_oe_l); end generate; -- second SRAM bank sram1 : for i in 0 to 1 generate sr0 : sram16 generic map (index => i*2, abits => 18, fname => sramfile) port map (baddr(19 downto 2), sram_dq(31-i*16 downto 16-i*16), sram_ben_l(i*2), sram_ben_l(i*2+1), sram_cs_l(1), sram_we_l, sram_oe_l); end generate; sdwen <= sram_we_l; u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile) PORT MAP( Dq => sram_dq(31 downto 16), Addr => baddr(14 downto 2), Ba => baddr(16 downto 15), Clk => sdclk, Cke => sdcke, Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(3 downto 2)); u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile) PORT MAP( Dq => sram_dq(15 downto 0), Addr => baddr(14 downto 2), Ba => baddr(16 downto 15), Clk => sdclk, Cke => sdcke, Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen, Dqm => sddqm(1 downto 0)); end generate; test0 : grtestmod port map ( dsurst, clk, leds(0), baddr(21 downto 2), sram_dq, iosn, sram_oe_l, sram_we_l, open); leds(0) <= 'H'; -- ERROR pull-up iuerr : process begin wait for 2000 ns; if to_x01(leds(0)) = '0' then wait on leds; end if; assert (to_x01(leds(0)) = '0') report "*** IU in error mode, simulation halted ***" severity failure ; end process; sram_dq <= buskeep(sram_dq), (others => 'H') after 250 ns; dsucom : process procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is variable w32 : std_logic_vector(31 downto 0); variable c8 : std_logic_vector(7 downto 0); constant txp : time := 160 * 1 ns; begin dsutx <= '1'; dsurst <= '0'; wait for 500 ns; dsurst <= '1'; wait; wait for 5000 ns; txc(dsutx, 16#55#, txp); -- sync uart txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp); txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp); txc(dsutx, 16#c0#, txp); txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp); txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp); txc(dsutx, 16#80#, txp); txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); rxi(dsurx, w32, txp, lresp); txc(dsutx, 16#a0#, txp); txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp); rxi(dsurx, w32, txp, lresp); end; begin dsucfg(dsutx, dsurx); wait; end process; end ;
library verilog; use verilog.vl_types.all; entity Control_unit is port( IRset : in vl_logic_vector(0 to 8); IRin : out vl_logic; Riout : out vl_logic_vector(0 to 7); Gout : out vl_logic; DINout : out vl_logic; Rin : out vl_logic_vector(0 to 7); Ain : out vl_logic; Gin : out vl_logic; AddSub : out vl_logic; Tstep_Q : in vl_logic_vector(1 downto 0); Clear : out vl_logic; Run : in vl_logic; Resetn : in vl_logic; Done : out vl_logic ); end Control_unit;
-- NEED RESULT: ARCH00138.P1: Multi inertial transactions occurred on signal asg with indexed name on LHS passed -- NEED RESULT: ARCH00138.P2: Multi inertial transactions occurred on signal asg with indexed name on LHS passed -- NEED RESULT: ARCH00138.P3: Multi inertial transactions occurred on signal asg with indexed name on LHS passed -- NEED RESULT: ARCH00138: One inertial transaction occurred on signal asg with indexed name on LHS passed -- NEED RESULT: ARCH00138: One inertial transaction occurred on signal asg with indexed name on LHS passed -- NEED RESULT: ARCH00138: One inertial transaction occurred on signal asg with indexed name on LHS passed -- NEED RESULT: ARCH00138: Old transactions were removed on signal asg with indexed name on LHS passed -- NEED RESULT: ARCH00138: Old transactions were removed on signal asg with indexed name on LHS passed -- NEED RESULT: ARCH00138: Old transactions were removed on signal asg with indexed name on LHS passed -- NEED RESULT: ARCH00138: One inertial transaction occurred on signal asg with indexed name on LHS passed -- NEED RESULT: ARCH00138: One inertial transaction occurred on signal asg with indexed name on LHS passed -- NEED RESULT: ARCH00138: One inertial transaction occurred on signal asg with indexed name on LHS passed -- NEED RESULT: ARCH00138: Inertial semantics check on a signal asg with indexed name on LHS passed -- NEED RESULT: ARCH00138: Inertial semantics check on a signal asg with indexed name on LHS passed -- NEED RESULT: ARCH00138: Inertial semantics check on a signal asg with indexed name on LHS passed -- NEED RESULT: P3: Inertial transactions entirely completed passed -- NEED RESULT: P2: Inertial transactions entirely completed passed -- NEED RESULT: P1: Inertial transactions entirely completed passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00138 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 8.3 (1) -- 8.3 (2) -- 8.3 (4) -- 8.3 (5) -- 8.3.1 (4) -- -- DESIGN UNIT ORDERING: -- -- E00000(ARCH00138) -- ENT00138_Test_Bench(ARCH00138_Test_Bench) -- -- REVISION HISTORY: -- -- 08-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; architecture ARCH00138 of E00000 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_st_arr1 : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; signal chk_st_arr3 : chk_sig_type := -1 ; -- signal s_st_arr1 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3 : st_arr3 := c_st_arr3_1 ; -- begin P1 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_arr1 (st_arr1'Left) <= c_st_arr1_2 (st_arr1'Right) after 10 ns, c_st_arr1_1 (st_arr1'Right) after 20 ns ; -- when 1 => correct := s_st_arr1 (st_arr1'Left) = c_st_arr1_2 (st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1 (st_arr1'Left) = c_st_arr1_1 (st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00138.P1" , "Multi inertial transactions occurred on signal " & "asg with indexed name on LHS", correct ) ; s_st_arr1 (st_arr1'Left) <= c_st_arr1_2 (st_arr1'Right) after 10 ns, c_st_arr1_1 (st_arr1'Right) after 20 ns, c_st_arr1_2 (st_arr1'Right) after 30 ns, c_st_arr1_1 (st_arr1'Right) after 40 ns ; -- when 3 => correct := s_st_arr1 (st_arr1'Left) = c_st_arr1_2 (st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr1 (st_arr1'Left) <= c_st_arr1_1 (st_arr1'Right) after 5 ns; -- when 4 => correct := correct and s_st_arr1 (st_arr1'Left) = c_st_arr1_1 (st_arr1'Right) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00138" , "One inertial transaction occurred on signal " & "asg with indexed name on LHS", correct ) ; s_st_arr1 (st_arr1'Left) <= transport c_st_arr1_1 (st_arr1'Right) after 100 ns; -- when 5 => correct := s_st_arr1 (st_arr1'Left) = c_st_arr1_1 (st_arr1'Right) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00138" , "Old transactions were removed on signal " & "asg with indexed name on LHS", correct ) ; s_st_arr1 (st_arr1'Left) <= c_st_arr1_2 (st_arr1'Right) after 10 ns, c_st_arr1_1 (st_arr1'Right) after 20 ns, c_st_arr1_2 (st_arr1'Right) after 30 ns, c_st_arr1_1 (st_arr1'Right) after 40 ns ; -- when 6 => correct := s_st_arr1 (st_arr1'Left) = c_st_arr1_2 (st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00138" , "One inertial transaction occurred on signal " & "asg with indexed name on LHS", correct ) ; -- The following will mark last transaction above s_st_arr1 (st_arr1'Left) <= c_st_arr1_1 (st_arr1'Right) after 40 ns; -- when 7 => correct := s_st_arr1 (st_arr1'Left) = c_st_arr1_1 (st_arr1'Right) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr1 (st_arr1'Left) = c_st_arr1_1 (st_arr1'Right) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00138" , "Inertial semantics check on a signal " & "asg with indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00138" , "Inertial semantics check on a signal " & "asg with indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr1 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_arr1'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P1 ; -- PGEN_CHKP_1 : process ( chk_st_arr1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions entirely completed", chk_st_arr1 = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- P2 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_arr2 ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_2 ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_1 ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns ; -- when 1 => correct := s_st_arr2 ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_2 ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2 ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_1 ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00138.P2" , "Multi inertial transactions occurred on signal " & "asg with indexed name on LHS", correct ) ; s_st_arr2 ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_2 ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_1 ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns, c_st_arr2_2 ( st_arr2'Right(1),st_arr2'Right(2)) after 30 ns, c_st_arr2_1 ( st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ; -- when 3 => correct := s_st_arr2 ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_2 ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr2 ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_1 ( st_arr2'Right(1),st_arr2'Right(2)) after 5 ns; -- when 4 => correct := correct and s_st_arr2 ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_1 ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00138" , "One inertial transaction occurred on signal " & "asg with indexed name on LHS", correct ) ; s_st_arr2 ( st_arr2'Left(1),st_arr2'Left(2)) <= transport c_st_arr2_1 ( st_arr2'Right(1),st_arr2'Right(2)) after 100 ns; -- when 5 => correct := s_st_arr2 ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_1 ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00138" , "Old transactions were removed on signal " & "asg with indexed name on LHS", correct ) ; s_st_arr2 ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_2 ( st_arr2'Right(1),st_arr2'Right(2)) after 10 ns, c_st_arr2_1 ( st_arr2'Right(1),st_arr2'Right(2)) after 20 ns, c_st_arr2_2 ( st_arr2'Right(1),st_arr2'Right(2)) after 30 ns, c_st_arr2_1 ( st_arr2'Right(1),st_arr2'Right(2)) after 40 ns ; -- when 6 => correct := s_st_arr2 ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_2 ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00138" , "One inertial transaction occurred on signal " & "asg with indexed name on LHS", correct ) ; -- The following will mark last transaction above s_st_arr2 ( st_arr2'Left(1),st_arr2'Left(2)) <= c_st_arr2_1 ( st_arr2'Right(1),st_arr2'Right(2)) after 40 ns; -- when 7 => correct := s_st_arr2 ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_1 ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr2 ( st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr2_1 ( st_arr2'Right(1),st_arr2'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00138" , "Inertial semantics check on a signal " & "asg with indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00138" , "Inertial semantics check on a signal " & "asg with indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr2 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_arr2'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P2 ; -- PGEN_CHKP_2 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions entirely completed", chk_st_arr2 = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- P3 : process variable correct : boolean ; variable counter : integer := 0 ; variable savtime : time ; -- procedure Proc1 is begin case counter is when 0 => s_st_arr3 ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_2 ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_1 ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns ; -- when 1 => correct := s_st_arr3 ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_2 ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3 ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_1 ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00138.P3" , "Multi inertial transactions occurred on signal " & "asg with indexed name on LHS", correct ) ; s_st_arr3 ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_2 ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_1 ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns, c_st_arr3_2 ( st_arr3'Right(1),st_arr3'Right(2)) after 30 ns, c_st_arr3_1 ( st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ; -- when 3 => correct := s_st_arr3 ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_2 ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; s_st_arr3 ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_1 ( st_arr3'Right(1),st_arr3'Right(2)) after 5 ns; -- when 4 => correct := correct and s_st_arr3 ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_1 ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00138" , "One inertial transaction occurred on signal " & "asg with indexed name on LHS", correct ) ; s_st_arr3 ( st_arr3'Left(1),st_arr3'Left(2)) <= transport c_st_arr3_1 ( st_arr3'Right(1),st_arr3'Right(2)) after 100 ns; -- when 5 => correct := s_st_arr3 ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_1 ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00138" , "Old transactions were removed on signal " & "asg with indexed name on LHS", correct ) ; s_st_arr3 ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_2 ( st_arr3'Right(1),st_arr3'Right(2)) after 10 ns, c_st_arr3_1 ( st_arr3'Right(1),st_arr3'Right(2)) after 20 ns, c_st_arr3_2 ( st_arr3'Right(1),st_arr3'Right(2)) after 30 ns, c_st_arr3_1 ( st_arr3'Right(1),st_arr3'Right(2)) after 40 ns ; -- when 6 => correct := s_st_arr3 ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_2 ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00138" , "One inertial transaction occurred on signal " & "asg with indexed name on LHS", correct ) ; -- The following will mark last transaction above s_st_arr3 ( st_arr3'Left(1),st_arr3'Left(2)) <= c_st_arr3_1 ( st_arr3'Right(1),st_arr3'Right(2)) after 40 ns; -- when 7 => correct := s_st_arr3 ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_1 ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr3 ( st_arr3'Left(1),st_arr3'Left(2)) = c_st_arr3_1 ( st_arr3'Right(1),st_arr3'Right(2)) and (savtime + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00138" , "Inertial semantics check on a signal " & "asg with indexed name on LHS", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00138" , "Inertial semantics check on a signal " & "asg with indexed name on LHS", false ) ; -- end case ; -- savtime := Std.Standard.Now ; chk_st_arr3 <= transport counter after (1 us - savtime) ; counter := counter + 1; -- end Proc1 ; -- begin Proc1 ; wait until (not s_st_arr3'Quiet) and (savtime /= Std.Standard.Now) ; -- end process P3 ; -- PGEN_CHKP_3 : process ( chk_st_arr3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions entirely completed", chk_st_arr3 = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- -- end ARCH00138 ; -- entity ENT00138_Test_Bench is end ENT00138_Test_Bench ; -- architecture ARCH00138_Test_Bench of ENT00138_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.E00000 ( ARCH00138 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00138_Test_Bench ;
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Mon Sep 16 04:58:12 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top design_1_auto_pc_0 -prefix -- design_1_auto_pc_0_ design_1_auto_pc_0_sim_netlist.vhdl -- Design : design_1_auto_pc_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd is port ( next_pending_r_reg_0 : out STD_LOGIC; \axaddr_incr_reg[0]_0\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[2]_0\ : out STD_LOGIC; \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); \m_axi_awaddr[11]\ : out STD_LOGIC; \m_axi_awaddr[5]\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 3 downto 0 ); incr_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; sel_first_reg_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \next\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[0]_rep\ : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd is signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \axaddr_incr[0]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[10]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr[1]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[2]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[4]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[5]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[6]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[7]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[8]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[9]_i_1_n_0\ : STD_LOGIC; signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC; signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 ); signal \axaddr_incr_reg[11]_i_4_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_7\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_2_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[5]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[6]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_2_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \^axlen_cnt_reg[2]_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC; signal next_pending_r_i_5_n_0 : STD_LOGIC; signal \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \m_axi_awaddr[11]_INST_0_i_1\ : label is "soft_lutpair113"; attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_1\ : label is "soft_lutpair113"; begin Q(0) <= \^q\(0); \axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\; \axaddr_incr_reg[11]_0\(10 downto 0) <= \^axaddr_incr_reg[11]_0\(10 downto 0); \axlen_cnt_reg[2]_0\ <= \^axlen_cnt_reg[2]_0\; \axaddr_incr[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_7\, O => \axaddr_incr[0]_i_1_n_0\ ); \axaddr_incr[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(10), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_5\, O => \axaddr_incr[10]_i_1_n_0\ ); \axaddr_incr[11]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \next\, O => \axaddr_incr[11]_i_1_n_0\ ); \axaddr_incr[11]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(11), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_4\, O => \axaddr_incr[11]_i_2_n_0\ ); \axaddr_incr[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_6\, O => \axaddr_incr[1]_i_1_n_0\ ); \axaddr_incr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_5\, O => \axaddr_incr[2]_i_1_n_0\ ); \axaddr_incr[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_4\, O => \axaddr_incr[3]_i_1_n_0\ ); \axaddr_incr[3]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"0102" ) port map ( I0 => \m_payload_i_reg[46]\(0), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(0) ); \axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(3), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_11_n_0\ ); \axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(2), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_12_n_0\ ); \axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(1), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), O => \axaddr_incr[3]_i_13_n_0\ ); \axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(0), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \m_payload_i_reg[46]\(3), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(3) ); \axaddr_incr[3]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"262A" ) port map ( I0 => \m_payload_i_reg[46]\(2), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(2) ); \axaddr_incr[3]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"060A" ) port map ( I0 => \m_payload_i_reg[46]\(1), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), I3 => \next\, O => S(1) ); \axaddr_incr[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(4), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_7\, O => \axaddr_incr[4]_i_1_n_0\ ); \axaddr_incr[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(5), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_6\, O => \axaddr_incr[5]_i_1_n_0\ ); \axaddr_incr[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(6), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_5\, O => \axaddr_incr[6]_i_1_n_0\ ); \axaddr_incr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(7), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_4\, O => \axaddr_incr[7]_i_1_n_0\ ); \axaddr_incr[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(8), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_7\, O => \axaddr_incr[8]_i_1_n_0\ ); \axaddr_incr[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(9), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_6\, O => \axaddr_incr[9]_i_1_n_0\ ); \axaddr_incr_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[0]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(0), R => '0' ); \axaddr_incr_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[10]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(9), R => '0' ); \axaddr_incr_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[11]_i_2_n_0\, Q => \^axaddr_incr_reg[11]_0\(10), R => '0' ); \axaddr_incr_reg[11]_i_4\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_3_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_4_n_1\, CO(1) => \axaddr_incr_reg[11]_i_4_n_2\, CO(0) => \axaddr_incr_reg[11]_i_4_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[11]_i_4_n_4\, O(2) => \axaddr_incr_reg[11]_i_4_n_5\, O(1) => \axaddr_incr_reg[11]_i_4_n_6\, O(0) => \axaddr_incr_reg[11]_i_4_n_7\, S(3 downto 0) => \^axaddr_incr_reg[11]_0\(10 downto 7) ); \axaddr_incr_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[1]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(1), R => '0' ); \axaddr_incr_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[2]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(2), R => '0' ); \axaddr_incr_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[3]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(3), R => '0' ); \axaddr_incr_reg[3]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_3_n_0\, CO(2) => \axaddr_incr_reg[3]_i_3_n_1\, CO(1) => \axaddr_incr_reg[3]_i_3_n_2\, CO(0) => \axaddr_incr_reg[3]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => \^axaddr_incr_reg[11]_0\(3 downto 0), O(3) => \axaddr_incr_reg[3]_i_3_n_4\, O(2) => \axaddr_incr_reg[3]_i_3_n_5\, O(1) => \axaddr_incr_reg[3]_i_3_n_6\, O(0) => \axaddr_incr_reg[3]_i_3_n_7\, S(3) => \axaddr_incr[3]_i_11_n_0\, S(2) => \axaddr_incr[3]_i_12_n_0\, S(1) => \axaddr_incr[3]_i_13_n_0\, S(0) => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[4]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(4), R => '0' ); \axaddr_incr_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[5]_i_1_n_0\, Q => \axaddr_incr_reg_n_0_[5]\, R => '0' ); \axaddr_incr_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[6]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(5), R => '0' ); \axaddr_incr_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[7]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(6), R => '0' ); \axaddr_incr_reg[7]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_3_n_0\, CO(3) => \axaddr_incr_reg[7]_i_3_n_0\, CO(2) => \axaddr_incr_reg[7]_i_3_n_1\, CO(1) => \axaddr_incr_reg[7]_i_3_n_2\, CO(0) => \axaddr_incr_reg[7]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[7]_i_3_n_4\, O(2) => \axaddr_incr_reg[7]_i_3_n_5\, O(1) => \axaddr_incr_reg[7]_i_3_n_6\, O(0) => \axaddr_incr_reg[7]_i_3_n_7\, S(3 downto 2) => \^axaddr_incr_reg[11]_0\(6 downto 5), S(1) => \axaddr_incr_reg_n_0_[5]\, S(0) => \^axaddr_incr_reg[11]_0\(4) ); \axaddr_incr_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[8]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(7), R => '0' ); \axaddr_incr_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[9]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(8), R => '0' ); \axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => \m_payload_i_reg[46]\(8), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^q\(0), I4 => \^axlen_cnt_reg[2]_0\, O => \axlen_cnt[1]_i_1__0_n_0\ ); \axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA900A900A900" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \^q\(0), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^axlen_cnt_reg[2]_0\, I4 => E(0), I5 => \m_payload_i_reg[46]\(9), O => \axlen_cnt[2]_i_1_n_0\ ); \axlen_cnt[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEEBAAAAAAAA" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^q\(0), I5 => \^axlen_cnt_reg[2]_0\, O => \axlen_cnt[3]_i_2_n_0\ ); \axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^q\(0), O => \axlen_cnt[4]_i_1_n_0\ ); \axlen_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[5]\, I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \^q\(0), I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[3]\, O => \axlen_cnt[5]_i_1_n_0\ ); \axlen_cnt[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axlen_cnt_reg_n_0_[6]\, I1 => \axlen_cnt_reg_n_0_[5]\, I2 => \axlen_cnt[7]_i_3_n_0\, O => \axlen_cnt[6]_i_1_n_0\ ); \axlen_cnt[7]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"A9AA" ) port map ( I0 => \axlen_cnt_reg_n_0_[7]\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt[7]_i_3_n_0\, O => \axlen_cnt[7]_i_2_n_0\ ); \axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \axlen_cnt_reg_n_0_[3]\, I1 => \axlen_cnt_reg_n_0_[2]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^q\(0), I4 => \axlen_cnt_reg_n_0_[4]\, O => \axlen_cnt[7]_i_3_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \state_reg[1]\(0), Q => \^q\(0), R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[1]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[2]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[3]_i_2_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[4]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[5]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[5]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[6]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[6]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[7]_i_2_n_0\, Q => \axlen_cnt_reg_n_0_[7]\, R => \state_reg[0]_rep\ ); \m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \m_payload_i_reg[46]\(7), O => \m_axi_awaddr[11]\ ); \m_axi_awaddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[5]\, I2 => \m_payload_i_reg[46]\(7), I3 => \m_payload_i_reg[46]\(4), O => \m_axi_awaddr[5]\ ); \next_pending_r_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"55545555" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[7]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[6]\, I4 => next_pending_r_i_5_n_0, O => \^axlen_cnt_reg[2]_0\ ); next_pending_r_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \axlen_cnt_reg_n_0_[1]\, I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[3]\, O => next_pending_r_i_5_n_0 ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => incr_next_pending, Q => next_pending_r_reg_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_0, Q => \^axaddr_incr_reg[0]_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is port ( incr_next_pending : out STD_LOGIC; \axaddr_incr_reg[0]_0\ : out STD_LOGIC; \axlen_cnt_reg[0]_0\ : out STD_LOGIC; \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \m_axi_araddr[11]\ : out STD_LOGIC; \m_axi_araddr[5]\ : out STD_LOGIC; \m_axi_araddr[3]\ : out STD_LOGIC; \m_axi_araddr[2]\ : out STD_LOGIC; \m_axi_araddr[1]\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 10 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; \m_payload_i_reg[47]_0\ : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); si_rs_arvalid : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]\ : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arready : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_17_b2s_incr_cmd"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is signal \axaddr_incr[0]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[10]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr[1]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[2]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[4]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[5]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[6]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[7]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[8]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[9]_i_1__0_n_0\ : STD_LOGIC; signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC; signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \axaddr_incr_reg[11]_i_4__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[1]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[2]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[3]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_2__0_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC; signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC; signal \^incr_next_pending\ : STD_LOGIC; signal \next_pending_r_i_2__0_n_0\ : STD_LOGIC; signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1__0\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1__0\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1__0\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1__0\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_4\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1__0\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1__0\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2__0\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3__0\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \m_axi_araddr[11]_INST_0_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \next_pending_r_i_2__0\ : label is "soft_lutpair7"; begin \axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\; \axaddr_incr_reg[11]_0\(7 downto 0) <= \^axaddr_incr_reg[11]_0\(7 downto 0); \axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\; incr_next_pending <= \^incr_next_pending\; \axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_7\, O => \axaddr_incr[0]_i_1__0_n_0\ ); \axaddr_incr[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_5\, O => \axaddr_incr[10]_i_1__0_n_0\ ); \axaddr_incr[11]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_4\, O => \axaddr_incr[11]_i_2__0_n_0\ ); \axaddr_incr[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_6\, O => \axaddr_incr[1]_i_1__0_n_0\ ); \axaddr_incr[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_5\, O => \axaddr_incr[2]_i_1__0_n_0\ ); \axaddr_incr[3]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"0201020202020202" ) port map ( I0 => Q(0), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(0) ); \axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \axaddr_incr_reg_n_0_[3]\, I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_11_n_0\ ); \axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_incr_reg_n_0_[2]\, I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_12_n_0\ ); \axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_incr_reg_n_0_[1]\, I1 => Q(6), I2 => Q(5), O => \axaddr_incr[3]_i_13_n_0\ ); \axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(0), I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_4\, O => \axaddr_incr[3]_i_1__0_n_0\ ); \axaddr_incr[3]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"AA6AAAAAAAAAAAAA" ) port map ( I0 => Q(3), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(3) ); \axaddr_incr[3]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"2A262A2A2A2A2A2A" ) port map ( I0 => Q(2), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(2) ); \axaddr_incr[3]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"0A060A0A0A0A0A0A" ) port map ( I0 => Q(1), I1 => Q(5), I2 => Q(6), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(1) ); \axaddr_incr[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_7\, O => \axaddr_incr[4]_i_1__0_n_0\ ); \axaddr_incr[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_6\, O => \axaddr_incr[5]_i_1__0_n_0\ ); \axaddr_incr[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_5\, O => \axaddr_incr[6]_i_1__0_n_0\ ); \axaddr_incr[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_4\, O => \axaddr_incr[7]_i_1__0_n_0\ ); \axaddr_incr[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_7\, O => \axaddr_incr[8]_i_1__0_n_0\ ); \axaddr_incr[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_6\, O => \axaddr_incr[9]_i_1__0_n_0\ ); \axaddr_incr_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[0]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(0), R => '0' ); \axaddr_incr_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[10]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(6), R => '0' ); \axaddr_incr_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[11]_i_2__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(7), R => '0' ); \axaddr_incr_reg[11]_i_4__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_3__0_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_4__0_n_1\, CO(1) => \axaddr_incr_reg[11]_i_4__0_n_2\, CO(0) => \axaddr_incr_reg[11]_i_4__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[11]_i_4__0_n_4\, O(2) => \axaddr_incr_reg[11]_i_4__0_n_5\, O(1) => \axaddr_incr_reg[11]_i_4__0_n_6\, O(0) => \axaddr_incr_reg[11]_i_4__0_n_7\, S(3 downto 0) => \^axaddr_incr_reg[11]_0\(7 downto 4) ); \axaddr_incr_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[1]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[1]\, R => '0' ); \axaddr_incr_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[2]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[2]\, R => '0' ); \axaddr_incr_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[3]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[3]\, R => '0' ); \axaddr_incr_reg[3]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_3__0_n_0\, CO(2) => \axaddr_incr_reg[3]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[3]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[3]_i_3__0_n_3\, CYINIT => '0', DI(3) => \axaddr_incr_reg_n_0_[3]\, DI(2) => \axaddr_incr_reg_n_0_[2]\, DI(1) => \axaddr_incr_reg_n_0_[1]\, DI(0) => \^axaddr_incr_reg[11]_0\(0), O(3) => \axaddr_incr_reg[3]_i_3__0_n_4\, O(2) => \axaddr_incr_reg[3]_i_3__0_n_5\, O(1) => \axaddr_incr_reg[3]_i_3__0_n_6\, O(0) => \axaddr_incr_reg[3]_i_3__0_n_7\, S(3) => \axaddr_incr[3]_i_11_n_0\, S(2) => \axaddr_incr[3]_i_12_n_0\, S(1) => \axaddr_incr[3]_i_13_n_0\, S(0) => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[4]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(1), R => '0' ); \axaddr_incr_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[5]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[5]\, R => '0' ); \axaddr_incr_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[6]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(2), R => '0' ); \axaddr_incr_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[7]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(3), R => '0' ); \axaddr_incr_reg[7]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_3__0_n_0\, CO(3) => \axaddr_incr_reg[7]_i_3__0_n_0\, CO(2) => \axaddr_incr_reg[7]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[7]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[7]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[7]_i_3__0_n_4\, O(2) => \axaddr_incr_reg[7]_i_3__0_n_5\, O(1) => \axaddr_incr_reg[7]_i_3__0_n_6\, O(0) => \axaddr_incr_reg[7]_i_3__0_n_7\, S(3 downto 2) => \^axaddr_incr_reg[11]_0\(3 downto 2), S(1) => \axaddr_incr_reg_n_0_[5]\, S(0) => \^axaddr_incr_reg[11]_0\(1) ); \axaddr_incr_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[8]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(4), R => '0' ); \axaddr_incr_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[9]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(5), R => '0' ); \axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"20FF2020" ) port map ( I0 => si_rs_arvalid, I1 => \state_reg[0]_rep\, I2 => Q(8), I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[0]_i_1__2_n_0\ ); \axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => Q(9), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[1]_i_1__1_n_0\ ); \axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA900A900A900" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^axlen_cnt_reg[0]_0\, I4 => E(0), I5 => Q(10), O => \axlen_cnt[2]_i_1__1_n_0\ ); \axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEEBAAAAAAAA" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[3]_i_2__0_n_0\ ); \axlen_cnt[3]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"55545555" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[7]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[6]\, I4 => \next_pending_r_i_4__0_n_0\, O => \^axlen_cnt_reg[0]_0\ ); \axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[4]_i_1__0_n_0\ ); \axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[5]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \axlen_cnt_reg_n_0_[4]\, O => \axlen_cnt[5]_i_1__0_n_0\ ); \axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axlen_cnt_reg_n_0_[6]\, I1 => \axlen_cnt_reg_n_0_[5]\, I2 => \axlen_cnt[7]_i_3__0_n_0\, O => \axlen_cnt[6]_i_1__0_n_0\ ); \axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A9AA" ) port map ( I0 => \axlen_cnt_reg_n_0_[7]\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt[7]_i_3__0_n_0\, O => \axlen_cnt[7]_i_2__0_n_0\ ); \axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[3]\, I3 => \axlen_cnt_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[0]\, O => \axlen_cnt[7]_i_3__0_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[0]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[1]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[2]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[3]_i_2__0_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[4]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => \state_reg[1]\ ); \axlen_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[5]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[5]\, R => \state_reg[1]\ ); \axlen_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[6]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[6]\, R => \state_reg[1]\ ); \axlen_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[7]_i_2__0_n_0\, Q => \axlen_cnt_reg_n_0_[7]\, R => \state_reg[1]\ ); \m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => Q(7), O => \m_axi_araddr[11]\ ); \m_axi_araddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[1]\, I2 => Q(7), I3 => Q(1), O => \m_axi_araddr[1]\ ); \m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[2]\, I2 => Q(7), I3 => Q(2), O => \m_axi_araddr[2]\ ); \m_axi_araddr[3]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[3]\, I2 => Q(7), I3 => Q(3), O => \m_axi_araddr[3]\ ); \m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[5]\, I2 => Q(7), I3 => Q(4), O => \m_axi_araddr[5]\ ); \next_pending_r_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF505C" ) port map ( I0 => \next_pending_r_i_2__0_n_0\, I1 => next_pending_r_reg_n_0, I2 => \state_reg[1]_rep\, I3 => E(0), I4 => \m_payload_i_reg[47]_0\, O => \^incr_next_pending\ ); \next_pending_r_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \next_pending_r_i_4__0_n_0\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[7]\, O => \next_pending_r_i_2__0_n_0\ ); \next_pending_r_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[4]\, O => \next_pending_r_i_4__0_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \^incr_next_pending\, Q => next_pending_r_reg_n_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_0, Q => \^axaddr_incr_reg[0]_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is port ( \axlen_cnt_reg[7]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC; \m_payload_i_reg[0]_0\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; sel_first_i : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_incr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_valid_i0 : out STD_LOGIC; s_ready_i0 : out STD_LOGIC; \m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC; si_rs_arvalid : in STD_LOGIC; \axlen_cnt_reg[7]_0\ : in STD_LOGIC; s_axburst_eq1_reg : in STD_LOGIC; \cnt_read_reg[2]_rep__0\ : in STD_LOGIC; \wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg_1 : in STD_LOGIC; areset_d1 : in STD_LOGIC; sel_first : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[5]\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; aclk : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_payload_i_reg[0]\ : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal \next_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_1__0\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__2\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \s_ready_i_i_1__0\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair2"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \state_reg[0]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute KEEP : string; attribute KEEP of \state_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]"; attribute FSM_ENCODED_STATES of \state_reg[0]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1; attribute KEEP of \state_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]"; attribute FSM_ENCODED_STATES of \state_reg[1]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute KEEP of \state_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]"; attribute FSM_ENCODED_STATES of \state_reg[1]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1; attribute KEEP of \state_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4__0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6__0\ : label is "soft_lutpair4"; begin Q(1 downto 0) <= \^q\(1 downto 0); \m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\; \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; \axaddr_incr[11]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AAEA" ) port map ( I0 => sel_first, I1 => m_axi_arready, I2 => \^m_payload_i_reg[0]_0\, I3 => \^m_payload_i_reg[0]\, O => \axaddr_incr_reg[0]\(0) ); \axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAACAAAAAAA0AA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \m_payload_i_reg[46]\(0), I2 => \^m_payload_i_reg[0]_0\, I3 => si_rs_arvalid, I4 => \^m_payload_i_reg[0]\, I5 => \m_payload_i_reg[5]\, O => \axaddr_offset_r_reg[2]\(0) ); \axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"00CA" ) port map ( I0 => si_rs_arvalid, I1 => m_axi_arready, I2 => \^q\(0), I3 => \^q\(1), O => E(0) ); \axlen_cnt[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00005140" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => m_axi_arready, I3 => si_rs_arvalid, I4 => \axlen_cnt_reg[7]_0\, O => \axlen_cnt_reg[7]\ ); m_axi_arvalid_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, O => m_axi_arvalid ); \m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"D5" ) port map ( I0 => si_rs_arvalid, I1 => \^m_payload_i_reg[0]\, I2 => \^m_payload_i_reg[0]_0\, O => \m_payload_i_reg[0]_1\(0) ); \m_valid_i_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"FF70FFFF" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, I2 => si_rs_arvalid, I3 => s_axi_arvalid, I4 => s_ready_i_reg, O => m_valid_i0 ); r_push_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^m_payload_i_reg[0]\, I1 => \^m_payload_i_reg[0]_0\, I2 => m_axi_arready, O => r_push_r_reg ); \s_ready_i_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"8FFF8F8F" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, I2 => si_rs_arvalid, I3 => s_axi_arvalid, I4 => s_ready_i_reg, O => s_ready_i0 ); \sel_first_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFC4C4CFCC" ) port map ( I0 => m_axi_arready, I1 => sel_first_reg_1, I2 => \^q\(1), I3 => si_rs_arvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg ); \sel_first_i_1__3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFC4C4CFCC" ) port map ( I0 => m_axi_arready, I1 => sel_first, I2 => \^m_payload_i_reg[0]\, I3 => si_rs_arvalid, I4 => \^m_payload_i_reg[0]_0\, I5 => areset_d1, O => sel_first_reg_0 ); \sel_first_i_1__4\: unisim.vcomponents.LUT6 generic map( INIT => X"FCFFFFFFCCCECCCE" ) port map ( I0 => si_rs_arvalid, I1 => areset_d1, I2 => \^m_payload_i_reg[0]\, I3 => \^m_payload_i_reg[0]_0\, I4 => m_axi_arready, I5 => sel_first_reg_2, O => sel_first_i ); \state[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"003030303E3E3E3E" ) port map ( I0 => si_rs_arvalid, I1 => \^q\(1), I2 => \^q\(0), I3 => m_axi_arready, I4 => s_axburst_eq1_reg, I5 => \cnt_read_reg[2]_rep__0\, O => \next_state__0\(0) ); \state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00AAB000" ) port map ( I0 => \cnt_read_reg[2]_rep__0\, I1 => s_axburst_eq1_reg, I2 => m_axi_arready, I3 => \^m_payload_i_reg[0]_0\, I4 => \^m_payload_i_reg[0]\, O => \next_state__0\(1) ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(0), Q => \^q\(0), R => areset_d1 ); \state_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(0), Q => \^m_payload_i_reg[0]_0\, R => areset_d1 ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(1), Q => \^q\(1), R => areset_d1 ); \state_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(1), Q => \^m_payload_i_reg[0]\, R => areset_d1 ); \wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \^m_payload_i_reg[0]\, I1 => si_rs_arvalid, I2 => \^m_payload_i_reg[0]_0\, O => \wrap_boundary_axaddr_r_reg[11]\(0) ); \wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8A5575AA8A5545" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_arvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => D(0) ); \wrap_cnt_r[3]_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(1), I1 => \^m_payload_i_reg[0]_0\, I2 => si_rs_arvalid, I3 => \^m_payload_i_reg[0]\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_6__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \^m_payload_i_reg[0]_0\, I2 => si_rs_arvalid, I3 => \^m_payload_i_reg[0]\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8AAA8AAA8AAABA" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_arvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => \wrap_second_len_r_reg[0]\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo is port ( \cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC; \cnt_read_reg[1]_rep__0_0\ : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); D : out STD_LOGIC_VECTOR ( 0 to 0 ); bresp_push : out STD_LOGIC; bvalid_i_reg : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); b_push : in STD_LOGIC; shandshake_r : in STD_LOGIC; areset_d1 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); mhandshake_r : in STD_LOGIC; si_rs_bready : in STD_LOGIC; bvalid_i_reg_0 : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); aclk : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo is signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \bresp_cnt[7]_i_4_n_0\ : STD_LOGIC; signal \bresp_cnt[7]_i_5_n_0\ : STD_LOGIC; signal \^bresp_push\ : STD_LOGIC; signal bvalid_i_i_2_n_0 : STD_LOGIC; signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC; signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \^cnt_read_reg[1]_rep__0_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair121"; attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair121"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name : string; attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 "; attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 "; attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 "; attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 "; attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 "; attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 "; attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 "; attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 "; attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 "; attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 "; attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 "; attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 "; attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 "; attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 "; attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 "; attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 "; begin bresp_push <= \^bresp_push\; \cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\; \cnt_read_reg[1]_rep__0_0\ <= \^cnt_read_reg[1]_rep__0_0\; \bresp_cnt[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"ABAA" ) port map ( I0 => areset_d1, I1 => \bresp_cnt[7]_i_3_n_0\, I2 => \bresp_cnt[7]_i_4_n_0\, I3 => \bresp_cnt[7]_i_5_n_0\, O => SR(0) ); \bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"EEFEFFFFFFFFEEFE" ) port map ( I0 => \bresp_cnt_reg[7]\(7), I1 => \bresp_cnt_reg[7]\(6), I2 => \bresp_cnt_reg[7]\(0), I3 => \memory_reg[3][0]_srl4_n_0\, I4 => \bresp_cnt_reg[7]\(3), I5 => \memory_reg[3][3]_srl4_n_0\, O => \bresp_cnt[7]_i_3_n_0\ ); \bresp_cnt[7]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"FFF6FFFF" ) port map ( I0 => \bresp_cnt_reg[7]\(1), I1 => \memory_reg[3][1]_srl4_n_0\, I2 => \bresp_cnt_reg[7]\(4), I3 => \bresp_cnt_reg[7]\(5), I4 => mhandshake_r, O => \bresp_cnt[7]_i_4_n_0\ ); \bresp_cnt[7]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"0000D00DD00DD00D" ) port map ( I0 => \memory_reg[3][0]_srl4_n_0\, I1 => \bresp_cnt_reg[7]\(0), I2 => \bresp_cnt_reg[7]\(2), I3 => \memory_reg[3][2]_srl4_n_0\, I4 => \^cnt_read_reg[1]_rep__0_0\, I5 => \^cnt_read_reg[0]_rep__0_0\, O => \bresp_cnt[7]_i_5_n_0\ ); bvalid_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0444" ) port map ( I0 => areset_d1, I1 => bvalid_i_i_2_n_0, I2 => si_rs_bready, I3 => bvalid_i_reg_0, O => bvalid_i_reg ); bvalid_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00070707" ) port map ( I0 => \^cnt_read_reg[1]_rep__0_0\, I1 => \^cnt_read_reg[0]_rep__0_0\, I2 => shandshake_r, I3 => Q(1), I4 => Q(0), I5 => bvalid_i_reg_0, O => bvalid_i_i_2_n_0 ); \cnt_read[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^bresp_push\, I1 => shandshake_r, I2 => Q(0), O => D(0) ); \cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => b_push, I2 => shandshake_r, O => \cnt_read[0]_i_1__2_n_0\ ); \cnt_read[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"E718" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => b_push, I2 => shandshake_r, I3 => \^cnt_read_reg[1]_rep__0_0\, O => \cnt_read[1]_i_1_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => \^cnt_read_reg[0]_rep__0_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => \^cnt_read_reg[1]_rep__0_0\, S => areset_d1 ); \memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(0), Q => \memory_reg[3][0]_srl4_n_0\ ); \memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000041004141" ) port map ( I0 => \memory_reg[3][0]_srl4_i_2__0_n_0\, I1 => \memory_reg[3][2]_srl4_n_0\, I2 => \bresp_cnt_reg[7]\(2), I3 => \bresp_cnt_reg[7]\(0), I4 => \memory_reg[3][0]_srl4_n_0\, I5 => \memory_reg[3][0]_srl4_i_3_n_0\, O => \^bresp_push\ ); \memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^cnt_read_reg[1]_rep__0_0\, I1 => \^cnt_read_reg[0]_rep__0_0\, O => \memory_reg[3][0]_srl4_i_2__0_n_0\ ); \memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFBFFFFFFFFFFFB" ) port map ( I0 => \bresp_cnt[7]_i_3_n_0\, I1 => mhandshake_r, I2 => \bresp_cnt_reg[7]\(5), I3 => \bresp_cnt_reg[7]\(4), I4 => \memory_reg[3][1]_srl4_n_0\, I5 => \bresp_cnt_reg[7]\(1), O => \memory_reg[3][0]_srl4_i_3_n_0\ ); \memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(6), Q => \out\(2) ); \memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(7), Q => \out\(3) ); \memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(8), Q => \out\(4) ); \memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(9), Q => \out\(5) ); \memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(10), Q => \out\(6) ); \memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(11), Q => \out\(7) ); \memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(12), Q => \out\(8) ); \memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(13), Q => \out\(9) ); \memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(14), Q => \out\(10) ); \memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(15), Q => \out\(11) ); \memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(1), Q => \memory_reg[3][1]_srl4_n_0\ ); \memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(2), Q => \memory_reg[3][2]_srl4_n_0\ ); \memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(3), Q => \memory_reg[3][3]_srl4_n_0\ ); \memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(4), Q => \out\(0) ); \memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(5), Q => \out\(1) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is port ( Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); mhandshake : out STD_LOGIC; m_axi_bready : out STD_LOGIC; \skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); shandshake_r : in STD_LOGIC; sel : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; mhandshake_r : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\; architecture STRUCTURE of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair122"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair122"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; attribute srl_name : string; attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 "; attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 "; begin Q(1 downto 0) <= \^q\(1 downto 0); \cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A69A" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => shandshake_r, I3 => sel, O => \cnt_read[1]_i_1__0_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => D(0), Q => \^q\(0), S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__0_n_0\, Q => \^q\(1), S => areset_d1 ); m_axi_bready_INST_0: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => mhandshake_r, O => m_axi_bready ); \memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \^q\(0), A1 => \^q\(1), A2 => '0', A3 => '0', CE => sel, CLK => aclk, D => \in\(0), Q => \skid_buffer_reg[1]\(0) ); \memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \^q\(0), A1 => \^q\(1), A2 => '0', A3 => '0', CE => sel, CLK => aclk, D => \in\(1), Q => \skid_buffer_reg[1]\(1) ); mhandshake_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"2000" ) port map ( I0 => m_axi_bvalid, I1 => mhandshake_r, I2 => \^q\(0), I3 => \^q\(1), O => mhandshake ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is port ( \cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC; \cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC; \cnt_read_reg[4]_rep__2_2\ : out STD_LOGIC; m_axi_rready : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); s_ready_i_reg : in STD_LOGIC; \cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC; si_rs_rready : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\; architecture STRUCTURE of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC; signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_5_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__3_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_2\ : STD_LOGIC; signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC; signal wr_en0 : STD_LOGIC; signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair18"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__3\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__3\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__3\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]"; attribute KEEP of \cnt_read_reg[2]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]"; attribute KEEP of \cnt_read_reg[3]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]"; attribute KEEP of \cnt_read_reg[4]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]"; attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair19"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name : string; attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 "; attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 "; attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 "; attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 "; attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 "; attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 "; attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 "; attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 "; attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 "; attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 "; attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 "; attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 "; attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 "; attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 "; attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 "; attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 "; attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 "; attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 "; attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 "; attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 "; attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 "; attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 "; attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 "; attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 "; attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 "; attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 "; attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 "; attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 "; attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 "; attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 "; attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 "; attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 "; attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 "; attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 "; attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair19"; begin \cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\; \cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\; \cnt_read_reg[4]_rep__2_2\ <= \^cnt_read_reg[4]_rep__2_2\; \cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => \cnt_read_reg[0]_rep__2_n_0\, I1 => s_ready_i_reg, I2 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[0]_i_1__1_n_0\ ); \cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"9AA6" ) port map ( I0 => \cnt_read_reg[1]_rep__2_n_0\, I1 => \cnt_read_reg[0]_rep__2_n_0\, I2 => s_ready_i_reg, I3 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[1]_i_1__2_n_0\ ); \cnt_read[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"A9AAAA6A" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read_reg[0]_rep__2_n_0\, I3 => \cnt_read[4]_i_5_n_0\, I4 => s_ready_i_reg, O => \cnt_read[2]_i_1_n_0\ ); \cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAA6AA9AAAAAA" ) port map ( I0 => \^cnt_read_reg[4]_rep__2_0\, I1 => \cnt_read_reg[2]_rep__2_n_0\, I2 => \cnt_read_reg[1]_rep__2_n_0\, I3 => \cnt_read[4]_i_5_n_0\, I4 => s_ready_i_reg, I5 => \cnt_read_reg[0]_rep__2_n_0\, O => \cnt_read[3]_i_1__0_n_0\ ); \cnt_read[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"99AA99AA99AA55A6" ) port map ( I0 => \^cnt_read_reg[4]_rep__2_1\, I1 => \^cnt_read_reg[4]_rep__2_0\, I2 => \^cnt_read_reg[4]_rep__2_2\, I3 => \cnt_read[4]_i_3__0_n_0\, I4 => s_ready_i_reg, I5 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[4]_i_1_n_0\ ); \cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \cnt_read_reg[0]_rep__3_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read_reg[2]_rep__2_n_0\, O => \^cnt_read_reg[4]_rep__2_2\ ); \cnt_read[4]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000100000" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read[4]_i_5_n_0\, I3 => \cnt_read_reg[4]_rep__0_0\, I4 => si_rs_rready, I5 => \cnt_read_reg[0]_rep__2_n_0\, O => \cnt_read[4]_i_3__0_n_0\ ); \cnt_read[4]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"6000E000FFFFFFFF" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \^cnt_read_reg[4]_rep__2_0\, I4 => \cnt_read_reg[0]_rep__3_n_0\, I5 => m_axi_rvalid, O => \cnt_read[4]_i_5_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__3\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__3_n_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => cnt_read(2), S => areset_d1 ); \cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => cnt_read(3), S => areset_d1 ); \cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \^cnt_read_reg[4]_rep__2_0\, S => areset_d1 ); \cnt_read_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => cnt_read(4), S => areset_d1 ); \cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \^cnt_read_reg[4]_rep__2_1\, S => areset_d1 ); m_axi_rready_INST_0: unisim.vcomponents.LUT5 generic map( INIT => X"9FFF1FFF" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \^cnt_read_reg[4]_rep__2_0\, I4 => \cnt_read_reg[0]_rep__3_n_0\, O => m_axi_rready ); \memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(0), Q => \out\(0), Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"8AAA0AAA0AAAAAAA" ) port map ( I0 => m_axi_rvalid, I1 => \cnt_read_reg[0]_rep__3_n_0\, I2 => \^cnt_read_reg[4]_rep__2_0\, I3 => \^cnt_read_reg[4]_rep__2_1\, I4 => \cnt_read_reg[1]_rep__2_n_0\, I5 => \cnt_read_reg[2]_rep__2_n_0\, O => wr_en0 ); \memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(10), Q => \out\(10), Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(11), Q => \out\(11), Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(12), Q => \out\(12), Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(13), Q => \out\(13), Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(14), Q => \out\(14), Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(15), Q => \out\(15), Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(16), Q => \out\(16), Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(17), Q => \out\(17), Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(18), Q => \out\(18), Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(19), Q => \out\(19), Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(1), Q => \out\(1), Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(20), Q => \out\(20), Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(21), Q => \out\(21), Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(22), Q => \out\(22), Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(23), Q => \out\(23), Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(24), Q => \out\(24), Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(25), Q => \out\(25), Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(26), Q => \out\(26), Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(27), Q => \out\(27), Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(28), Q => \out\(28), Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(29), Q => \out\(29), Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(2), Q => \out\(2), Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(30), Q => \out\(30), Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(31), Q => \out\(31), Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(32), Q => \out\(32), Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(33), Q => \out\(33), Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(3), Q => \out\(3), Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(4), Q => \out\(4), Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(5), Q => \out\(5), Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(6), Q => \out\(6), Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(7), Q => \out\(7), Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(8), Q => \out\(8), Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(9), Q => \out\(9), Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ ); \state[1]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"40C0C000" ) port map ( I0 => \cnt_read_reg[0]_rep__3_n_0\, I1 => \^cnt_read_reg[4]_rep__2_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \cnt_read_reg[1]_rep__2_n_0\, I4 => \cnt_read_reg[2]_rep__2_n_0\, O => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is port ( m_valid_i_reg : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; \skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); s_ready_i_reg : in STD_LOGIC; r_push_r : in STD_LOGIC; si_rs_rready : in STD_LOGIC; \cnt_read_reg[3]_rep__2\ : in STD_LOGIC; \cnt_read_reg[4]_rep__2\ : in STD_LOGIC; \cnt_read_reg[0]_rep__3\ : in STD_LOGIC; \cnt_read_reg[0]_rep__3_0\ : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\; architecture STRUCTURE of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC; signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC; signal m_valid_i_i_3_n_0 : STD_LOGIC; signal \^m_valid_i_reg\ : STD_LOGIC; signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair20"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute KEEP of \cnt_read_reg[2]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]"; attribute KEEP of \cnt_read_reg[3]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]"; attribute KEEP of \cnt_read_reg[4]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name : string; attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 "; attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 "; attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 "; attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 "; attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 "; attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 "; attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 "; attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 "; attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 "; attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 "; attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 "; attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 "; attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 "; begin m_valid_i_reg <= \^m_valid_i_reg\; \cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cnt_read_reg[0]_rep__0_n_0\, I1 => r_push_r, I2 => s_ready_i_reg, O => \cnt_read[0]_i_1__0_n_0\ ); \cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"DB24" ) port map ( I0 => \cnt_read_reg[0]_rep__0_n_0\, I1 => s_ready_i_reg, I2 => r_push_r, I3 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[1]_i_1__1_n_0\ ); \cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => s_ready_i_reg, I2 => r_push_r, I3 => \cnt_read_reg[0]_rep__0_n_0\, I4 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[2]_i_1__0_n_0\ ); \cnt_read[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF7F0080FEFF0100" ) port map ( I0 => \cnt_read_reg[1]_rep__0_n_0\, I1 => \cnt_read_reg[0]_rep__0_n_0\, I2 => r_push_r, I3 => s_ready_i_reg, I4 => \cnt_read_reg[3]_rep__0_n_0\, I5 => \cnt_read_reg[2]_rep__0_n_0\, O => \cnt_read[3]_i_1_n_0\ ); \cnt_read[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9A999AAA" ) port map ( I0 => \cnt_read_reg[4]_rep__0_n_0\, I1 => \cnt_read[4]_i_2_n_0\, I2 => \cnt_read_reg[2]_rep__0_n_0\, I3 => \cnt_read_reg[3]_rep__0_n_0\, I4 => \cnt_read[4]_i_3_n_0\, O => \cnt_read[4]_i_1__0_n_0\ ); \cnt_read[4]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"2AAAAAAA2AAA2AAA" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => \cnt_read_reg[1]_rep__0_n_0\, I2 => \cnt_read_reg[0]_rep__1_n_0\, I3 => r_push_r, I4 => \^m_valid_i_reg\, I5 => si_rs_rready, O => \cnt_read[4]_i_2_n_0\ ); \cnt_read[4]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000004" ) port map ( I0 => r_push_r, I1 => si_rs_rready, I2 => \^m_valid_i_reg\, I3 => \cnt_read_reg[0]_rep__1_n_0\, I4 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[4]_i_3_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => \cnt_read_reg[1]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => cnt_read(2), S => areset_d1 ); \cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => \cnt_read_reg[2]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => \cnt_read_reg[2]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => cnt_read(3), S => areset_d1 ); \cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => \cnt_read_reg[3]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => \cnt_read_reg[3]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => cnt_read(4), S => areset_d1 ); \cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => \cnt_read_reg[4]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => \cnt_read_reg[4]_rep__0_n_0\, S => areset_d1 ); m_valid_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"80808080FF808080" ) port map ( I0 => \cnt_read_reg[4]_rep__0_n_0\, I1 => \cnt_read_reg[3]_rep__0_n_0\, I2 => m_valid_i_i_3_n_0, I3 => \cnt_read_reg[3]_rep__2\, I4 => \cnt_read_reg[4]_rep__2\, I5 => \cnt_read_reg[0]_rep__3\, O => \^m_valid_i_reg\ ); m_valid_i_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => \cnt_read_reg[0]_rep__1_n_0\, I2 => \cnt_read_reg[1]_rep__0_n_0\, O => m_valid_i_i_3_n_0 ); \memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(0), Q => \skid_buffer_reg[46]\(0), Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(10), Q => \skid_buffer_reg[46]\(10), Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(11), Q => \skid_buffer_reg[46]\(11), Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(12), Q => \skid_buffer_reg[46]\(12), Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(1), Q => \skid_buffer_reg[46]\(1), Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(2), Q => \skid_buffer_reg[46]\(2), Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(3), Q => \skid_buffer_reg[46]\(3), Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(4), Q => \skid_buffer_reg[46]\(4), Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(5), Q => \skid_buffer_reg[46]\(5), Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(6), Q => \skid_buffer_reg[46]\(6), Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(7), Q => \skid_buffer_reg[46]\(7), Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(8), Q => \skid_buffer_reg[46]\(8), Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(9), Q => \skid_buffer_reg[46]\(9), Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ ); \state[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"BFEEAAAAAAAAAAAA" ) port map ( I0 => \cnt_read_reg[0]_rep__3_0\, I1 => \cnt_read_reg[2]_rep__0_n_0\, I2 => \cnt_read_reg[0]_rep__1_n_0\, I3 => \cnt_read_reg[1]_rep__0_n_0\, I4 => \cnt_read_reg[3]_rep__0_n_0\, I5 => \cnt_read_reg[4]_rep__0_n_0\, O => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is port ( \axlen_cnt_reg[7]\ : out STD_LOGIC; \axlen_cnt_reg[7]_0\ : out STD_LOGIC; \axlen_cnt_reg[7]_1\ : out STD_LOGIC; \next\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); D : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axburst_eq0_reg : out STD_LOGIC; incr_next_pending : out STD_LOGIC; sel_first_i : out STD_LOGIC; s_axburst_eq1_reg : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); b_push : out STD_LOGIC; m_axi_awvalid : out STD_LOGIC; s_axburst_eq1_reg_0 : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; \cnt_read_reg[0]_rep__0\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC; si_rs_awvalid : in STD_LOGIC; \axlen_cnt_reg[7]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axlen_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); wrap_next_pending : in STD_LOGIC; next_pending_r_reg : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; sel_first : in STD_LOGIC; areset_d1 : in STD_LOGIC; sel_first_0 : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[5]\ : in STD_LOGIC; aclk : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^axlen_cnt_reg[7]\ : STD_LOGIC; signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC; signal \^b_push\ : STD_LOGIC; signal \^incr_next_pending\ : STD_LOGIC; signal \^next\ : STD_LOGIC; signal \^sel_first_i\ : STD_LOGIC; signal \state[0]_i_1_n_0\ : STD_LOGIC; signal \state[0]_i_2_n_0\ : STD_LOGIC; signal \state[1]_i_1__0_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__0\ : label is "soft_lutpair109"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair110"; attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair110"; attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair109"; attribute KEEP : string; attribute KEEP of \state_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1; attribute KEEP of \state_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]"; attribute KEEP of \state_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1; attribute KEEP of \state_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4\ : label is "soft_lutpair111"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6\ : label is "soft_lutpair111"; begin E(0) <= \^e\(0); Q(1 downto 0) <= \^q\(1 downto 0); \axlen_cnt_reg[7]\ <= \^axlen_cnt_reg[7]\; \axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\; b_push <= \^b_push\; incr_next_pending <= \^incr_next_pending\; \next\ <= \^next\; sel_first_i <= \^sel_first_i\; \axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAACAAAAAAA0AA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \m_payload_i_reg[46]\(2), I2 => \^axlen_cnt_reg[7]_0\, I3 => si_rs_awvalid, I4 => \^axlen_cnt_reg[7]\, I5 => \m_payload_i_reg[5]\, O => \axaddr_offset_r_reg[2]\(0) ); \axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0400FFFF04000400" ) port map ( I0 => \^q\(1), I1 => si_rs_awvalid, I2 => \^q\(0), I3 => \m_payload_i_reg[46]\(1), I4 => \axlen_cnt_reg[0]_0\(0), I5 => \axlen_cnt_reg[7]_2\, O => \axlen_cnt_reg[0]\(0) ); \axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FF04" ) port map ( I0 => \^q\(0), I1 => si_rs_awvalid, I2 => \^q\(1), I3 => \^next\, O => \axaddr_wrap_reg[11]\(0) ); \axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF04" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]\, I3 => \^next\, I4 => \axlen_cnt_reg[7]_2\, O => \axlen_cnt_reg[7]_1\ ); m_axi_awvalid_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => \^axlen_cnt_reg[7]\, O => m_axi_awvalid ); \m_payload_i[31]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^b_push\, I1 => si_rs_awvalid, O => \m_payload_i_reg[0]\(0) ); \memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"88008888A800A8A8" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => \^axlen_cnt_reg[7]\, I2 => m_axi_awready, I3 => \cnt_read_reg[0]_rep__0\, I4 => \cnt_read_reg[1]_rep__0\, I5 => s_axburst_eq1_reg_0, O => \^b_push\ ); next_pending_r_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF404" ) port map ( I0 => \^e\(0), I1 => next_pending_r_reg, I2 => \^next\, I3 => \axlen_cnt_reg[7]_2\, I4 => \m_payload_i_reg[47]\, O => \^incr_next_pending\ ); next_pending_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"F3F3FFFF51000000" ) port map ( I0 => s_axburst_eq1_reg_0, I1 => \cnt_read_reg[1]_rep__0\, I2 => \cnt_read_reg[0]_rep__0\, I3 => m_axi_awready, I4 => \^axlen_cnt_reg[7]_0\, I5 => \^axlen_cnt_reg[7]\, O => \^next\ ); s_axburst_eq0_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"BA8A" ) port map ( I0 => \^incr_next_pending\, I1 => \^sel_first_i\, I2 => \m_payload_i_reg[46]\(0), I3 => wrap_next_pending, O => s_axburst_eq0_reg ); s_axburst_eq1_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FE02" ) port map ( I0 => \^incr_next_pending\, I1 => \m_payload_i_reg[46]\(0), I2 => \^sel_first_i\, I3 => wrap_next_pending, O => s_axburst_eq1_reg ); sel_first_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF44444F44" ) port map ( I0 => \^next\, I1 => sel_first, I2 => \^q\(1), I3 => si_rs_awvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg ); \sel_first_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF44444F44" ) port map ( I0 => \^next\, I1 => sel_first_0, I2 => \^q\(1), I3 => si_rs_awvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg_0 ); \sel_first_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF04FFFFFF04FF04" ) port map ( I0 => \^axlen_cnt_reg[7]\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]_0\, I3 => areset_d1, I4 => \^next\, I5 => sel_first_reg_1, O => \^sel_first_i\ ); \state[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BBBA" ) port map ( I0 => \state[0]_i_2_n_0\, I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), O => \state[0]_i_1_n_0\ ); \state[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00F000F055750000" ) port map ( I0 => m_axi_awready, I1 => s_axburst_eq1_reg_0, I2 => \cnt_read_reg[1]_rep__0\, I3 => \cnt_read_reg[0]_rep__0\, I4 => \^axlen_cnt_reg[7]_0\, I5 => \^axlen_cnt_reg[7]\, O => \state[0]_i_2_n_0\ ); \state[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0C0CAE0000000000" ) port map ( I0 => s_axburst_eq1_reg_0, I1 => \cnt_read_reg[1]_rep__0\, I2 => \cnt_read_reg[0]_rep__0\, I3 => m_axi_awready, I4 => \^axlen_cnt_reg[7]\, I5 => \^axlen_cnt_reg[7]_0\, O => \state[1]_i_1__0_n_0\ ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[0]_i_1_n_0\, Q => \^q\(0), R => areset_d1 ); \state_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[0]_i_1_n_0\, Q => \^axlen_cnt_reg[7]_0\, R => areset_d1 ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[1]_i_1__0_n_0\, Q => \^q\(1), R => areset_d1 ); \state_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[1]_i_1__0_n_0\, Q => \^axlen_cnt_reg[7]\, R => areset_d1 ); \wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \^axlen_cnt_reg[7]\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]_0\, O => \^e\(0) ); \wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8A5575AA8A5545" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => D(0) ); \wrap_cnt_r[3]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(1), I1 => \^axlen_cnt_reg[7]_0\, I2 => si_rs_awvalid, I3 => \^axlen_cnt_reg[7]\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \^axlen_cnt_reg[7]_0\, I2 => si_rs_awvalid, I3 => \^axlen_cnt_reg[7]\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8AAA8AAA8AAABA" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => \wrap_second_len_r_reg[0]\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is port ( wrap_next_pending : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_awvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \next\ : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 10 downto 0 ); sel_first_reg_3 : in STD_LOGIC; \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 ); signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC; signal \axlen_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \next_pending_r_i_2__1_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \^sel_first_reg_0\ : STD_LOGIC; signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 1 to 1 ); signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^wrap_next_pending\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); begin sel_first_reg_0 <= \^sel_first_reg_0\; wrap_next_pending <= \^wrap_next_pending\; \wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0); \axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => \axaddr_offset_r_reg[3]_0\(0), R => '0' ); \axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => \axaddr_offset_r_reg[3]_0\(1), R => '0' ); \axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => \axaddr_offset_r_reg[3]_0\(2), R => '0' ); \axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => \axaddr_offset_r_reg[3]_0\(3), R => '0' ); \axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(0), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(0), I3 => \next\, I4 => \m_payload_i_reg[47]\(0), O => \axaddr_wrap[0]_i_1_n_0\ ); \axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(10), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(10), I3 => \next\, I4 => \m_payload_i_reg[47]\(10), O => \axaddr_wrap[10]_i_1_n_0\ ); \axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(11), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(11), I3 => \next\, I4 => \m_payload_i_reg[47]\(11), O => \axaddr_wrap[11]_i_1_n_0\ ); \axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"41" ) port map ( I0 => \axaddr_wrap[11]_i_4_n_0\, I1 => wrap_cnt_r(3), I2 => \axlen_cnt_reg_n_0_[3]\, O => \axaddr_wrap[11]_i_2_n_0\ ); \axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"6FF6FFFFFFFF6FF6" ) port map ( I0 => wrap_cnt_r(0), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => wrap_cnt_r(1), I4 => \axlen_cnt_reg_n_0_[2]\, I5 => wrap_cnt_r(2), O => \axaddr_wrap[11]_i_4_n_0\ ); \axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(1), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(1), I3 => \next\, I4 => \m_payload_i_reg[47]\(1), O => \axaddr_wrap[1]_i_1_n_0\ ); \axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(2), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(2), I3 => \next\, I4 => \m_payload_i_reg[47]\(2), O => \axaddr_wrap[2]_i_1_n_0\ ); \axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(3), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(3), I3 => \next\, I4 => \m_payload_i_reg[47]\(3), O => \axaddr_wrap[3]_i_1_n_0\ ); \axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => axaddr_wrap(3), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_3_n_0\ ); \axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => axaddr_wrap(2), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_4_n_0\ ); \axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => axaddr_wrap(1), I1 => \m_payload_i_reg[47]\(13), I2 => \m_payload_i_reg[47]\(12), O => \axaddr_wrap[3]_i_5_n_0\ ); \axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => axaddr_wrap(0), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(4), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(4), I3 => \next\, I4 => \m_payload_i_reg[47]\(4), O => \axaddr_wrap[4]_i_1_n_0\ ); \axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(5), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(5), I3 => \next\, I4 => \m_payload_i_reg[47]\(5), O => \axaddr_wrap[5]_i_1_n_0\ ); \axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(6), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(6), I3 => \next\, I4 => \m_payload_i_reg[47]\(6), O => \axaddr_wrap[6]_i_1_n_0\ ); \axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(7), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(7), I3 => \next\, I4 => \m_payload_i_reg[47]\(7), O => \axaddr_wrap[7]_i_1_n_0\ ); \axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(8), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(8), I3 => \next\, I4 => \m_payload_i_reg[47]\(8), O => \axaddr_wrap[8]_i_1_n_0\ ); \axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(9), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(9), I3 => \next\, I4 => \m_payload_i_reg[47]\(9), O => \axaddr_wrap[9]_i_1_n_0\ ); \axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[0]_i_1_n_0\, Q => axaddr_wrap(0), R => '0' ); \axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[10]_i_1_n_0\, Q => axaddr_wrap(10), R => '0' ); \axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[11]_i_1_n_0\, Q => axaddr_wrap(11), R => '0' ); \axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[7]_i_2_n_0\, CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3), CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\, CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\, CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_wrap0(11 downto 8), S(3 downto 0) => axaddr_wrap(11 downto 8) ); \axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[1]_i_1_n_0\, Q => axaddr_wrap(1), R => '0' ); \axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[2]_i_1_n_0\, Q => axaddr_wrap(2), R => '0' ); \axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[3]_i_1_n_0\, Q => axaddr_wrap(3), R => '0' ); \axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\, CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\, CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\, CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => axaddr_wrap(3 downto 0), O(3 downto 0) => axaddr_wrap0(3 downto 0), S(3) => \axaddr_wrap[3]_i_3_n_0\, S(2) => \axaddr_wrap[3]_i_4_n_0\, S(1) => \axaddr_wrap[3]_i_5_n_0\, S(0) => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[4]_i_1_n_0\, Q => axaddr_wrap(4), R => '0' ); \axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[5]_i_1_n_0\, Q => axaddr_wrap(5), R => '0' ); \axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[6]_i_1_n_0\, Q => axaddr_wrap(6), R => '0' ); \axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[7]_i_1_n_0\, Q => axaddr_wrap(7), R => '0' ); \axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[3]_i_2_n_0\, CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\, CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\, CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\, CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_wrap0(7 downto 4), S(3 downto 0) => axaddr_wrap(7 downto 4) ); \axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[8]_i_1_n_0\, Q => axaddr_wrap(8), R => '0' ); \axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[9]_i_1_n_0\, Q => axaddr_wrap(9), R => '0' ); \axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"A3A3A3A3A3A3A3A0" ) port map ( I0 => \m_payload_i_reg[47]\(15), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => E(0), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \axlen_cnt[0]_i_1_n_0\ ); \axlen_cnt[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAC3AAC3AAC3AAC0" ) port map ( I0 => \m_payload_i_reg[47]\(16), I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => E(0), I4 => \axlen_cnt_reg_n_0_[3]\, I5 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[1]_i_1_n_0\ ); \axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA9A80000A9A8" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => E(0), I5 => \m_payload_i_reg[47]\(17), O => \axlen_cnt[2]_i_1__0_n_0\ ); \axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAACCCCCCC0" ) port map ( I0 => \m_payload_i_reg[47]\(18), I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[0]\, I5 => E(0), O => \axlen_cnt[3]_i_1_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[0]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[1]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[2]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[3]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(0), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(0), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(0), O => m_axi_awaddr(0) ); \m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(10), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(10), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(9), O => m_axi_awaddr(10) ); \m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(11), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(11), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(10), O => m_axi_awaddr(11) ); \m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(1), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(1), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(1), O => m_axi_awaddr(1) ); \m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(2), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(2), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(2), O => m_axi_awaddr(2) ); \m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(3), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(3), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(3), O => m_axi_awaddr(3) ); \m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(4), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(4), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(4), O => m_axi_awaddr(4) ); \m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \m_payload_i_reg[47]\(5), I1 => \^sel_first_reg_0\, I2 => axaddr_wrap(5), I3 => \m_payload_i_reg[47]\(14), I4 => sel_first_reg_3, O => m_axi_awaddr(5) ); \m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(6), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(6), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(5), O => m_axi_awaddr(6) ); \m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(7), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(7), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(6), O => m_axi_awaddr(7) ); \m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(8), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(8), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(7), O => m_axi_awaddr(8) ); \m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(9), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(9), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(8), O => m_axi_awaddr(9) ); \next_pending_r_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FEAAFEAE" ) port map ( I0 => \m_payload_i_reg[47]_0\, I1 => next_pending_r_reg_n_0, I2 => \next\, I3 => \next_pending_r_i_2__1_n_0\, I4 => E(0), O => \^wrap_next_pending\ ); \next_pending_r_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBFBFBFBFBFB00" ) port map ( I0 => \state_reg[1]\(0), I1 => si_rs_awvalid, I2 => \state_reg[1]\(1), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \next_pending_r_i_2__1_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \^wrap_next_pending\, Q => next_pending_r_reg_n_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_1, Q => \^sel_first_reg_0\, R => '0' ); \wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(0), Q => wrap_boundary_axaddr_r(0), R => '0' ); \wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(10), Q => wrap_boundary_axaddr_r(10), R => '0' ); \wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(11), Q => wrap_boundary_axaddr_r(11), R => '0' ); \wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(1), Q => wrap_boundary_axaddr_r(1), R => '0' ); \wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(2), Q => wrap_boundary_axaddr_r(2), R => '0' ); \wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(3), Q => wrap_boundary_axaddr_r(3), R => '0' ); \wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(4), Q => wrap_boundary_axaddr_r(4), R => '0' ); \wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(5), Q => wrap_boundary_axaddr_r(5), R => '0' ); \wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(6), Q => wrap_boundary_axaddr_r(6), R => '0' ); \wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(7), Q => wrap_boundary_axaddr_r(7), R => '0' ); \wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(8), Q => wrap_boundary_axaddr_r(8), R => '0' ); \wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(9), Q => wrap_boundary_axaddr_r(9), R => '0' ); \wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"3D310E02" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(0), I1 => E(0), I2 => \axaddr_offset_r_reg[3]_2\, I3 => D(1), I4 => \^wrap_second_len_r_reg[3]_0\(1), O => wrap_cnt(1) ); \wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"000CAAA8000C0000" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(1), I1 => \axaddr_offset_r_reg[3]_1\, I2 => D(1), I3 => D(0), I4 => E(0), I5 => \^wrap_second_len_r_reg[3]_0\(0), O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(0), Q => wrap_cnt_r(0), R => '0' ); \wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cnt(1), Q => wrap_cnt_r(1), R => '0' ); \wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(1), Q => wrap_cnt_r(2), R => '0' ); \wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(2), Q => wrap_cnt_r(3), R => '0' ); \wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(0), Q => \^wrap_second_len_r_reg[3]_0\(0), R => '0' ); \wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(1), Q => \^wrap_second_len_r_reg[3]_0\(1), R => '0' ); \wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(2), Q => \^wrap_second_len_r_reg[3]_0\(2), R => '0' ); \wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(3), Q => \^wrap_second_len_r_reg[3]_0\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is port ( sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axburst_eq0_reg : out STD_LOGIC; s_axburst_eq1_reg : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 18 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_arvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); sel_first_i : in STD_LOGIC; incr_next_pending : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); sel_first_reg_3 : in STD_LOGIC; sel_first_reg_4 : in STD_LOGIC; sel_first_reg_5 : in STD_LOGIC; sel_first_reg_6 : in STD_LOGIC; \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_17_b2s_wrap_cmd"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC; signal \axlen_cnt[0]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \next_pending_r_i_2__2_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \^sel_first_reg_0\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC; signal wrap_next_pending : STD_LOGIC; signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair16"; begin sel_first_reg_0 <= \^sel_first_reg_0\; \wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0); \axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => \axaddr_offset_r_reg[3]_0\(0), R => '0' ); \axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => \axaddr_offset_r_reg[3]_0\(1), R => '0' ); \axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => \axaddr_offset_r_reg[3]_0\(2), R => '0' ); \axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => \axaddr_offset_r_reg[3]_0\(3), R => '0' ); \axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(0), O => \axaddr_wrap[0]_i_1__0_n_0\ ); \axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(10), O => \axaddr_wrap[10]_i_1__0_n_0\ ); \axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(11), O => \axaddr_wrap[11]_i_1__0_n_0\ ); \axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"41" ) port map ( I0 => \axaddr_wrap[11]_i_4__0_n_0\, I1 => \wrap_cnt_r_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[3]\, O => \axaddr_wrap[11]_i_2__0_n_0\ ); \axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"6FF6FFFFFFFF6FF6" ) port map ( I0 => \wrap_cnt_r_reg_n_0_[0]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \wrap_cnt_r_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \wrap_cnt_r_reg_n_0_[1]\, O => \axaddr_wrap[11]_i_4__0_n_0\ ); \axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(1), O => \axaddr_wrap[1]_i_1__0_n_0\ ); \axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(2), O => \axaddr_wrap[2]_i_1__0_n_0\ ); \axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(3), O => \axaddr_wrap[3]_i_1__0_n_0\ ); \axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[3]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_3_n_0\ ); \axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[2]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_4_n_0\ ); \axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[1]\, I1 => Q(13), I2 => Q(12), O => \axaddr_wrap[3]_i_5_n_0\ ); \axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \axaddr_wrap_reg_n_0_[0]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(4), O => \axaddr_wrap[4]_i_1__0_n_0\ ); \axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(5), O => \axaddr_wrap[5]_i_1__0_n_0\ ); \axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(6), O => \axaddr_wrap[6]_i_1__0_n_0\ ); \axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(7), O => \axaddr_wrap[7]_i_1__0_n_0\ ); \axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(8), O => \axaddr_wrap[8]_i_1__0_n_0\ ); \axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(9), O => \axaddr_wrap[9]_i_1__0_n_0\ ); \axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[0]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[0]\, R => '0' ); \axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[10]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[10]\, R => '0' ); \axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[11]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[11]\, R => '0' ); \axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[7]_i_2__0_n_0\, CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\, CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\, CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\, O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\, O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\, O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\, S(3) => \axaddr_wrap_reg_n_0_[11]\, S(2) => \axaddr_wrap_reg_n_0_[10]\, S(1) => \axaddr_wrap_reg_n_0_[9]\, S(0) => \axaddr_wrap_reg_n_0_[8]\ ); \axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[1]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[1]\, R => '0' ); \axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[2]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[2]\, R => '0' ); \axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[3]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[3]\, R => '0' ); \axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\, CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\, CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\, CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\, CYINIT => '0', DI(3) => \axaddr_wrap_reg_n_0_[3]\, DI(2) => \axaddr_wrap_reg_n_0_[2]\, DI(1) => \axaddr_wrap_reg_n_0_[1]\, DI(0) => \axaddr_wrap_reg_n_0_[0]\, O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\, O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\, O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\, O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\, S(3) => \axaddr_wrap[3]_i_3_n_0\, S(2) => \axaddr_wrap[3]_i_4_n_0\, S(1) => \axaddr_wrap[3]_i_5_n_0\, S(0) => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[4]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[4]\, R => '0' ); \axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[5]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[5]\, R => '0' ); \axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[6]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[6]\, R => '0' ); \axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[7]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[7]\, R => '0' ); \axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[3]_i_2__0_n_0\, CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\, CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\, CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\, CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\, O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\, O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\, O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\, S(3) => \axaddr_wrap_reg_n_0_[7]\, S(2) => \axaddr_wrap_reg_n_0_[6]\, S(1) => \axaddr_wrap_reg_n_0_[5]\, S(0) => \axaddr_wrap_reg_n_0_[4]\ ); \axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[8]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[8]\, R => '0' ); \axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[9]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[9]\, R => '0' ); \axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"A3A3A3A3A3A3A3A0" ) port map ( I0 => Q(15), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => E(0), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \axlen_cnt[0]_i_1__1_n_0\ ); \axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"AAC3AAC3AAC3AAC0" ) port map ( I0 => Q(16), I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => E(0), I4 => \axlen_cnt_reg_n_0_[3]\, I5 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[1]_i_1__2_n_0\ ); \axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA9A80000A9A8" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => E(0), I5 => Q(17), O => \axlen_cnt[2]_i_1__2_n_0\ ); \axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAACCCCCCC0" ) port map ( I0 => Q(18), I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[0]\, I5 => E(0), O => \axlen_cnt[3]_i_1__1_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[0]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[1]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[2]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[3]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[0]\, I2 => Q(14), I3 => Q(0), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(0), O => m_axi_araddr(0) ); \m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[10]\, I2 => Q(14), I3 => Q(10), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(6), O => m_axi_araddr(10) ); \m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[11]\, I2 => Q(14), I3 => Q(11), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(7), O => m_axi_araddr(11) ); \m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(1), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[1]\, I3 => Q(14), I4 => sel_first_reg_6, O => m_axi_araddr(1) ); \m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(2), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[2]\, I3 => Q(14), I4 => sel_first_reg_5, O => m_axi_araddr(2) ); \m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(3), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[3]\, I3 => Q(14), I4 => sel_first_reg_4, O => m_axi_araddr(3) ); \m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[4]\, I2 => Q(14), I3 => Q(4), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(1), O => m_axi_araddr(4) ); \m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(5), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[5]\, I3 => Q(14), I4 => sel_first_reg_3, O => m_axi_araddr(5) ); \m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[6]\, I2 => Q(14), I3 => Q(6), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(2), O => m_axi_araddr(6) ); \m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[7]\, I2 => Q(14), I3 => Q(7), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(3), O => m_axi_araddr(7) ); \m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[8]\, I2 => Q(14), I3 => Q(8), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(4), O => m_axi_araddr(8) ); \m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[9]\, I2 => Q(14), I3 => Q(9), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(5), O => m_axi_araddr(9) ); \next_pending_r_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"FEAAFEAE" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => next_pending_r_reg_n_0, I2 => \state_reg[1]_rep\, I3 => \next_pending_r_i_2__2_n_0\, I4 => E(0), O => wrap_next_pending ); \next_pending_r_i_2__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBFBFBFBFBFB00" ) port map ( I0 => \state_reg[1]\(0), I1 => si_rs_arvalid, I2 => \state_reg[1]\(1), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \next_pending_r_i_2__2_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_next_pending, Q => next_pending_r_reg_n_0, R => '0' ); \s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => wrap_next_pending, I1 => Q(14), I2 => sel_first_i, I3 => incr_next_pending, O => s_axburst_eq0_reg ); \s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"ABA8" ) port map ( I0 => wrap_next_pending, I1 => Q(14), I2 => sel_first_i, I3 => incr_next_pending, O => s_axburst_eq1_reg ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_1, Q => \^sel_first_reg_0\, R => '0' ); \wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(0), Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\, R => '0' ); \wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(10), Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\, R => '0' ); \wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(11), Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\, R => '0' ); \wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(1), Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\, R => '0' ); \wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(2), Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\, R => '0' ); \wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(3), Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\, R => '0' ); \wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(4), Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\, R => '0' ); \wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(5), Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\, R => '0' ); \wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(6), Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\, R => '0' ); \wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(7), Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\, R => '0' ); \wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(8), Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\, R => '0' ); \wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(9), Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\, R => '0' ); \wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"3D310E02" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(0), I1 => E(0), I2 => \axaddr_offset_r_reg[3]_2\, I3 => D(1), I4 => \^wrap_second_len_r_reg[3]_0\(1), O => \wrap_cnt_r[1]_i_1__0_n_0\ ); \wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"000CAAA8000C0000" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(1), I1 => \axaddr_offset_r_reg[3]_1\, I2 => D(1), I3 => D(0), I4 => E(0), I5 => \^wrap_second_len_r_reg[3]_0\(0), O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(0), Q => \wrap_cnt_r_reg_n_0_[0]\, R => '0' ); \wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_cnt_r[1]_i_1__0_n_0\, Q => \wrap_cnt_r_reg_n_0_[1]\, R => '0' ); \wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(1), Q => \wrap_cnt_r_reg_n_0_[2]\, R => '0' ); \wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(2), Q => \wrap_cnt_r_reg_n_0_[3]\, R => '0' ); \wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(0), Q => \^wrap_second_len_r_reg[3]_0\(0), R => '0' ); \wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(1), Q => \^wrap_second_len_r_reg[3]_0\(1), R => '0' ); \wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(2), Q => \^wrap_second_len_r_reg[3]_0\(2), R => '0' ); \wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(3), Q => \^wrap_second_len_r_reg[3]_0\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice is port ( s_axi_arready : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC; m_valid_i_reg_0 : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); O : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; \axaddr_offset_r_reg[0]\ : out STD_LOGIC; axaddr_offset_0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \aresetn_d_reg[0]\ : in STD_LOGIC; s_ready_i0 : in STD_LOGIC; aclk : in STD_LOGIC; m_valid_i0 : in STD_LOGIC; \aresetn_d_reg[0]_0\ : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice; architecture STRUCTURE of design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice is signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 ); signal \axaddr_incr[3]_i_4__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_5__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_6__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_3\ : STD_LOGIC; signal \^axaddr_offset_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_offset_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC; signal \^axlen_cnt_reg[3]\ : STD_LOGIC; signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC; signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[52]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal \^s_axi_arready\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \wrap_cnt_r[3]_i_5__0_n_0\ : STD_LOGIC; signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_3__0_n_0\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[52]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair21"; begin Q(54 downto 0) <= \^q\(54 downto 0); axaddr_offset_0(1 downto 0) <= \^axaddr_offset_0\(1 downto 0); \axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\; \axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\; \axaddr_offset_r_reg[3]\ <= \^axaddr_offset_r_reg[3]\; \axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; s_axi_arready <= \^s_axi_arready\; \wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\; \wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0); \aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \aresetn_d_reg[0]_0\, Q => \^m_valid_i_reg_0\, R => '0' ); \axaddr_incr[3]_i_4__0\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => \^q\(2), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_4__0_n_0\ ); \axaddr_incr[3]_i_5__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(1), I1 => \^q\(36), O => \axaddr_incr[3]_i_5__0_n_0\ ); \axaddr_incr[3]_i_6__0\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_6__0_n_0\ ); \axaddr_incr_reg[11]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_2__0_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[11]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[11]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => O(3 downto 0), S(3 downto 0) => \^q\(11 downto 8) ); \axaddr_incr_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_2__0_n_0\, CO(2) => \axaddr_incr_reg[3]_i_2__0_n_1\, CO(1) => \axaddr_incr_reg[3]_i_2__0_n_2\, CO(0) => \axaddr_incr_reg[3]_i_2__0_n_3\, CYINIT => '0', DI(3) => \^q\(3), DI(2) => \axaddr_incr[3]_i_4__0_n_0\, DI(1) => \axaddr_incr[3]_i_5__0_n_0\, DI(0) => \axaddr_incr[3]_i_6__0_n_0\, O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0) ); \axaddr_incr_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_2__0_n_0\, CO(3) => \axaddr_incr_reg[7]_i_2__0_n_0\, CO(2) => \axaddr_incr_reg[7]_i_2__0_n_1\, CO(1) => \axaddr_incr_reg[7]_i_2__0_n_2\, CO(0) => \axaddr_incr_reg[7]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), S(3 downto 0) => \^q\(7 downto 4) ); \axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[0]_i_2__0_n_0\, I1 => \^q\(39), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(0), O => \^axaddr_offset_r_reg[0]\ ); \axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(3), I1 => \^q\(2), I2 => \^q\(36), I3 => \^q\(1), I4 => \^q\(35), I5 => \^q\(0), O => \axaddr_offset_r[0]_i_2__0_n_0\ ); \axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[1]_i_2__0_n_0\, I1 => \^q\(40), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(1), O => \^axaddr_offset_0\(0) ); \axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(4), I1 => \^q\(3), I2 => \^q\(36), I3 => \^q\(2), I4 => \^q\(35), I5 => \^q\(1), O => \axaddr_offset_r[1]_i_2__0_n_0\ ); \axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(5), I1 => \^q\(4), I2 => \^q\(36), I3 => \^q\(3), I4 => \^q\(35), I5 => \^q\(2), O => \^axaddr_offset_r_reg[2]\ ); \axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[3]_i_2__0_n_0\, I1 => \^q\(42), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(2), O => \^axaddr_offset_0\(1) ); \axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(6), I1 => \^q\(5), I2 => \^q\(36), I3 => \^q\(4), I4 => \^q\(35), I5 => \^q\(3), O => \axaddr_offset_r[3]_i_2__0_n_0\ ); \axlen_cnt[3]_i_3__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0020" ) port map ( I0 => \^q\(42), I1 => \state_reg[1]\(0), I2 => \^axaddr_offset_r_reg[3]\, I3 => \state_reg[1]\(1), O => \^axlen_cnt_reg[3]\ ); \m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__0_n_0\ ); \m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(10), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__0_n_0\ ); \m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(11), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__0_n_0\ ); \m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(12), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__0_n_0\ ); \m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(13), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_1__1_n_0\ ); \m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(14), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[14]\, O => \m_payload_i[14]_i_1__0_n_0\ ); \m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(15), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[15]\, O => \m_payload_i[15]_i_1__0_n_0\ ); \m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(16), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[16]\, O => \m_payload_i[16]_i_1__0_n_0\ ); \m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(17), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[17]\, O => \m_payload_i[17]_i_1__0_n_0\ ); \m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(18), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[18]\, O => \m_payload_i[18]_i_1__0_n_0\ ); \m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(19), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[19]\, O => \m_payload_i[19]_i_1__0_n_0\ ); \m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__0_n_0\ ); \m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(20), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[20]\, O => \m_payload_i[20]_i_1__0_n_0\ ); \m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(21), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[21]\, O => \m_payload_i[21]_i_1__0_n_0\ ); \m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(22), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[22]\, O => \m_payload_i[22]_i_1__0_n_0\ ); \m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(23), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[23]\, O => \m_payload_i[23]_i_1__0_n_0\ ); \m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(24), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[24]\, O => \m_payload_i[24]_i_1__0_n_0\ ); \m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(25), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[25]\, O => \m_payload_i[25]_i_1__0_n_0\ ); \m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(26), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[26]\, O => \m_payload_i[26]_i_1__0_n_0\ ); \m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(27), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[27]\, O => \m_payload_i[27]_i_1__0_n_0\ ); \m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(28), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[28]\, O => \m_payload_i[28]_i_1__0_n_0\ ); \m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(29), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[29]\, O => \m_payload_i[29]_i_1__0_n_0\ ); \m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__0_n_0\ ); \m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(30), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[30]\, O => \m_payload_i[30]_i_1__0_n_0\ ); \m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(31), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[31]\, O => \m_payload_i[31]_i_2__0_n_0\ ); \m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[32]\, O => \m_payload_i[32]_i_1__0_n_0\ ); \m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[33]\, O => \m_payload_i[33]_i_1__0_n_0\ ); \m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[34]\, O => \m_payload_i[34]_i_1__0_n_0\ ); \m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arsize(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[35]\, O => \m_payload_i[35]_i_1__0_n_0\ ); \m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arsize(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[36]\, O => \m_payload_i[36]_i_1__0_n_0\ ); \m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arburst(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[38]\, O => \m_payload_i[38]_i_1__0_n_0\ ); \m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arburst(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[39]\, O => \m_payload_i[39]_i_1__0_n_0\ ); \m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__0_n_0\ ); \m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[44]\, O => \m_payload_i[44]_i_1__0_n_0\ ); \m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[45]\, O => \m_payload_i[45]_i_1__0_n_0\ ); \m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[46]\, O => \m_payload_i[46]_i_1__1_n_0\ ); \m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[47]\, O => \m_payload_i[47]_i_1__0_n_0\ ); \m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(4), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__0_n_0\ ); \m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[50]\, O => \m_payload_i[50]_i_1__0_n_0\ ); \m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[51]\, O => \m_payload_i[51]_i_1__0_n_0\ ); \m_payload_i[52]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[52]\, O => \m_payload_i[52]_i_1__0_n_0\ ); \m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[53]\, O => \m_payload_i[53]_i_1__0_n_0\ ); \m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(4), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[54]\, O => \m_payload_i[54]_i_1__0_n_0\ ); \m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(5), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[55]\, O => \m_payload_i[55]_i_1__0_n_0\ ); \m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(6), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[56]\, O => \m_payload_i[56]_i_1__0_n_0\ ); \m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(7), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[57]\, O => \m_payload_i[57]_i_1__0_n_0\ ); \m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(8), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[58]\, O => \m_payload_i[58]_i_1__0_n_0\ ); \m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(9), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[59]\, O => \m_payload_i[59]_i_1__0_n_0\ ); \m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(5), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__0_n_0\ ); \m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(10), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[60]\, O => \m_payload_i[60]_i_1__0_n_0\ ); \m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(11), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[61]\, O => \m_payload_i[61]_i_1__0_n_0\ ); \m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(6), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__0_n_0\ ); \m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(7), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__0_n_0\ ); \m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(8), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__0_n_0\ ); \m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(9), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__0_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[0]_i_1__0_n_0\, Q => \^q\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[10]_i_1__0_n_0\, Q => \^q\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[11]_i_1__0_n_0\, Q => \^q\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[12]_i_1__0_n_0\, Q => \^q\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[13]_i_1__1_n_0\, Q => \^q\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[14]_i_1__0_n_0\, Q => \^q\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[15]_i_1__0_n_0\, Q => \^q\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[16]_i_1__0_n_0\, Q => \^q\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[17]_i_1__0_n_0\, Q => \^q\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[18]_i_1__0_n_0\, Q => \^q\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[19]_i_1__0_n_0\, Q => \^q\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[1]_i_1__0_n_0\, Q => \^q\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[20]_i_1__0_n_0\, Q => \^q\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[21]_i_1__0_n_0\, Q => \^q\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[22]_i_1__0_n_0\, Q => \^q\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[23]_i_1__0_n_0\, Q => \^q\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[24]_i_1__0_n_0\, Q => \^q\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[25]_i_1__0_n_0\, Q => \^q\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[26]_i_1__0_n_0\, Q => \^q\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[27]_i_1__0_n_0\, Q => \^q\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[28]_i_1__0_n_0\, Q => \^q\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[29]_i_1__0_n_0\, Q => \^q\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[2]_i_1__0_n_0\, Q => \^q\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[30]_i_1__0_n_0\, Q => \^q\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[31]_i_2__0_n_0\, Q => \^q\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[32]_i_1__0_n_0\, Q => \^q\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[33]_i_1__0_n_0\, Q => \^q\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[34]_i_1__0_n_0\, Q => \^q\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[35]_i_1__0_n_0\, Q => \^q\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[36]_i_1__0_n_0\, Q => \^q\(36), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[38]_i_1__0_n_0\, Q => \^q\(37), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[39]_i_1__0_n_0\, Q => \^q\(38), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[3]_i_1__0_n_0\, Q => \^q\(3), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[44]_i_1__0_n_0\, Q => \^q\(39), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[45]_i_1__0_n_0\, Q => \^q\(40), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[46]_i_1__1_n_0\, Q => \^q\(41), R => '0' ); \m_payload_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[47]_i_1__0_n_0\, Q => \^q\(42), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[4]_i_1__0_n_0\, Q => \^q\(4), R => '0' ); \m_payload_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[50]_i_1__0_n_0\, Q => \^q\(43), R => '0' ); \m_payload_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[51]_i_1__0_n_0\, Q => \^q\(44), R => '0' ); \m_payload_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[52]_i_1__0_n_0\, Q => \^q\(45), R => '0' ); \m_payload_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[53]_i_1__0_n_0\, Q => \^q\(46), R => '0' ); \m_payload_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[54]_i_1__0_n_0\, Q => \^q\(47), R => '0' ); \m_payload_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[55]_i_1__0_n_0\, Q => \^q\(48), R => '0' ); \m_payload_i_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[56]_i_1__0_n_0\, Q => \^q\(49), R => '0' ); \m_payload_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[57]_i_1__0_n_0\, Q => \^q\(50), R => '0' ); \m_payload_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[58]_i_1__0_n_0\, Q => \^q\(51), R => '0' ); \m_payload_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[59]_i_1__0_n_0\, Q => \^q\(52), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[5]_i_1__0_n_0\, Q => \^q\(5), R => '0' ); \m_payload_i_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[60]_i_1__0_n_0\, Q => \^q\(53), R => '0' ); \m_payload_i_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[61]_i_1__0_n_0\, Q => \^q\(54), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[6]_i_1__0_n_0\, Q => \^q\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[7]_i_1__0_n_0\, Q => \^q\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[8]_i_1__0_n_0\, Q => \^q\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[9]_i_1__0_n_0\, Q => \^q\(9), R => '0' ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^axaddr_offset_r_reg[3]\, R => \^m_valid_i_reg_0\ ); next_pending_r_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => \state_reg[1]_rep\, I1 => \^q\(42), I2 => \^q\(40), I3 => \^q\(39), I4 => \^q\(41), O => next_pending_r_reg ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^s_axi_arready\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(2), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arsize(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arsize(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arburst(0), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arburst(1), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(0), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(1), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(2), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(3), Q => \skid_buffer_reg_n_0_[47]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(0), Q => \skid_buffer_reg_n_0_[50]\, R => '0' ); \skid_buffer_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(1), Q => \skid_buffer_reg_n_0_[51]\, R => '0' ); \skid_buffer_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(2), Q => \skid_buffer_reg_n_0_[52]\, R => '0' ); \skid_buffer_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(3), Q => \skid_buffer_reg_n_0_[53]\, R => '0' ); \skid_buffer_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(4), Q => \skid_buffer_reg_n_0_[54]\, R => '0' ); \skid_buffer_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(5), Q => \skid_buffer_reg_n_0_[55]\, R => '0' ); \skid_buffer_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(6), Q => \skid_buffer_reg_n_0_[56]\, R => '0' ); \skid_buffer_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(7), Q => \skid_buffer_reg_n_0_[57]\, R => '0' ); \skid_buffer_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(8), Q => \skid_buffer_reg_n_0_[58]\, R => '0' ); \skid_buffer_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(9), Q => \skid_buffer_reg_n_0_[59]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(10), Q => \skid_buffer_reg_n_0_[60]\, R => '0' ); \skid_buffer_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(11), Q => \skid_buffer_reg_n_0_[61]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); \wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(39), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(0) ); \wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"8A888AAA" ) port map ( I0 => \^q\(1), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(40), O => \wrap_boundary_axaddr_r_reg[6]\(1) ); \wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0F553300000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(36), I5 => \^q\(2), O => \wrap_boundary_axaddr_r_reg[6]\(2) ); \wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"020202A2A2A202A2" ) port map ( I0 => \^q\(3), I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\, I2 => \^q\(36), I3 => \^q\(40), I4 => \^q\(35), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(3) ); \wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(41), I1 => \^q\(35), I2 => \^q\(42), O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ ); \wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"503F5F3F00000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(36), I3 => \^q\(35), I4 => \^q\(42), I5 => \^q\(4), O => \wrap_boundary_axaddr_r_reg[6]\(4) ); \wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"2A222AAA" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(41), I3 => \^q\(35), I4 => \^q\(42), O => \wrap_boundary_axaddr_r_reg[6]\(5) ); \wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"2AAA" ) port map ( I0 => \^q\(6), I1 => \^q\(42), I2 => \^q\(35), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(6) ); \wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA6AA56AAAAAAAA" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(1), I1 => \wrap_second_len_r_reg[3]_0\(0), I2 => \state_reg[1]_rep\, I3 => \^wrap_cnt_r_reg[2]\, I4 => \^axaddr_offset_r_reg[0]\, I5 => \^wrap_second_len_r_reg[3]\(0), O => \wrap_cnt_r_reg[3]\(0) ); \wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(2), I1 => \wrap_second_len_r_reg[1]\, I2 => \^wrap_second_len_r_reg[3]\(1), O => \wrap_cnt_r_reg[3]\(1) ); \wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFEAEAFFEA" ) port map ( I0 => \axaddr_offset_r_reg[3]_1\, I1 => \^axlen_cnt_reg[3]\, I2 => \axaddr_offset_r[3]_i_2__0_n_0\, I3 => \^axaddr_offset_r_reg[2]\, I4 => \wrap_cnt_r[3]_i_5__0_n_0\, I5 => \axaddr_offset_r_reg[2]_1\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r[3]_i_5__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \^q\(41), I1 => \state_reg[0]_rep\, I2 => \^axaddr_offset_r_reg[3]\, I3 => \state_reg[1]_rep_0\, O => \wrap_cnt_r[3]_i_5__0_n_0\ ); \wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0001000000010001" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset_0\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2__0_n_0\, I4 => \state_reg[1]_rep\, I5 => \axaddr_offset_r_reg[3]_0\(2), O => \^wrap_cnt_r_reg[2]\ ); \wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"F00EFFFFF00E0000" ) port map ( I0 => \^axaddr_offset_0\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_r_reg[0]\, I3 => \^axaddr_offset_0\(0), I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(1), O => \^wrap_second_len_r_reg[3]\(0) ); \wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"CCC2FFFFCCC20000" ) port map ( I0 => \^axaddr_offset_0\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_0\(0), I3 => \^axaddr_offset_r_reg[0]\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(2), O => \^wrap_second_len_r_reg[3]\(1) ); \wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FE00FFFFFE00FE00" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset_0\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2__0_n_0\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(3), O => \^wrap_second_len_r_reg[3]\(2) ); \wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"A8A8A8080808A808" ) port map ( I0 => \^axlen_cnt_reg[3]\, I1 => \wrap_second_len_r[3]_i_3__0_n_0\, I2 => \^q\(36), I3 => \^q\(5), I4 => \^q\(35), I5 => \^q\(6), O => \wrap_second_len_r[3]_i_2__0_n_0\ ); \wrap_second_len_r[3]_i_3__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(4), I1 => \^q\(35), I2 => \^q\(3), O => \wrap_second_len_r[3]_i_3__0_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 is port ( s_axi_awready : out STD_LOGIC; s_ready_i_reg_0 : out STD_LOGIC; m_valid_i_reg_0 : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; \axaddr_offset_r_reg[0]\ : out STD_LOGIC; axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \aresetn_d_reg[1]_inv\ : out STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[1]_inv_0\ : in STD_LOGIC; aresetn : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); S : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; b_push : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0; architecture STRUCTURE of design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 is signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 ); signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC; signal \axaddr_incr[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_3\ : STD_LOGIC; signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC; signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC; signal \axaddr_offset_r[3]_i_2_n_0\ : STD_LOGIC; signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC; signal \^axlen_cnt_reg[3]\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal \^s_axi_awready\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^s_ready_i_reg_0\ : STD_LOGIC; signal skid_buffer : STD_LOGIC_VECTOR ( 61 downto 0 ); signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC; signal \wrap_cnt_r[3]_i_5_n_0\ : STD_LOGIC; signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_3_n_0\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair49"; begin Q(54 downto 0) <= \^q\(54 downto 0); axaddr_offset(1 downto 0) <= \^axaddr_offset\(1 downto 0); \axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\; \axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\; \axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; s_axi_awready <= \^s_axi_awready\; s_ready_i_reg_0 <= \^s_ready_i_reg_0\; \wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\; \wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0); \aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \aresetn_d_reg_n_0_[0]\, I1 => aresetn, O => \aresetn_d_reg[1]_inv\ ); \aresetn_d_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => aresetn, Q => \aresetn_d_reg_n_0_[0]\, R => '0' ); \axaddr_incr[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => \^q\(2), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_4_n_0\ ); \axaddr_incr[3]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(1), I1 => \^q\(36), O => \axaddr_incr[3]_i_5_n_0\ ); \axaddr_incr[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_6_n_0\ ); \axaddr_incr_reg[11]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_2_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_3_n_1\, CO(1) => \axaddr_incr_reg[11]_i_3_n_2\, CO(0) => \axaddr_incr_reg[11]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_incr(11 downto 8), S(3 downto 0) => \^q\(11 downto 8) ); \axaddr_incr_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_2_n_0\, CO(2) => \axaddr_incr_reg[3]_i_2_n_1\, CO(1) => \axaddr_incr_reg[3]_i_2_n_2\, CO(0) => \axaddr_incr_reg[3]_i_2_n_3\, CYINIT => '0', DI(3) => \^q\(3), DI(2) => \axaddr_incr[3]_i_4_n_0\, DI(1) => \axaddr_incr[3]_i_5_n_0\, DI(0) => \axaddr_incr[3]_i_6_n_0\, O(3 downto 0) => axaddr_incr(3 downto 0), S(3 downto 0) => S(3 downto 0) ); \axaddr_incr_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_2_n_0\, CO(3) => \axaddr_incr_reg[7]_i_2_n_0\, CO(2) => \axaddr_incr_reg[7]_i_2_n_1\, CO(1) => \axaddr_incr_reg[7]_i_2_n_2\, CO(0) => \axaddr_incr_reg[7]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_incr(7 downto 4), S(3 downto 0) => \^q\(7 downto 4) ); \axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[0]_i_2_n_0\, I1 => \^q\(39), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(0), O => \^axaddr_offset_r_reg[0]\ ); \axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(3), I1 => \^q\(2), I2 => \^q\(36), I3 => \^q\(1), I4 => \^q\(35), I5 => \^q\(0), O => \axaddr_offset_r[0]_i_2_n_0\ ); \axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[1]_i_2_n_0\, I1 => \^q\(40), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(1), O => \^axaddr_offset\(0) ); \axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(4), I1 => \^q\(3), I2 => \^q\(36), I3 => \^q\(2), I4 => \^q\(35), I5 => \^q\(1), O => \axaddr_offset_r[1]_i_2_n_0\ ); \axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(5), I1 => \^q\(4), I2 => \^q\(36), I3 => \^q\(3), I4 => \^q\(35), I5 => \^q\(2), O => \^axaddr_offset_r_reg[2]\ ); \axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[3]_i_2_n_0\, I1 => \^q\(42), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(2), O => \^axaddr_offset\(1) ); \axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(6), I1 => \^q\(5), I2 => \^q\(36), I3 => \^q\(4), I4 => \^q\(35), I5 => \^q\(3), O => \axaddr_offset_r[3]_i_2_n_0\ ); \axlen_cnt[3]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0020" ) port map ( I0 => \^q\(42), I1 => \state_reg[1]\(0), I2 => \^m_valid_i_reg_0\, I3 => \state_reg[1]\(1), O => \^axlen_cnt_reg[3]\ ); \m_payload_i[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[0]\, O => skid_buffer(0) ); \m_payload_i[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(10), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[10]\, O => skid_buffer(10) ); \m_payload_i[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(11), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[11]\, O => skid_buffer(11) ); \m_payload_i[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(12), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[12]\, O => skid_buffer(12) ); \m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(13), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[13]\, O => skid_buffer(13) ); \m_payload_i[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(14), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[14]\, O => skid_buffer(14) ); \m_payload_i[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(15), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[15]\, O => skid_buffer(15) ); \m_payload_i[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(16), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[16]\, O => skid_buffer(16) ); \m_payload_i[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(17), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[17]\, O => skid_buffer(17) ); \m_payload_i[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(18), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[18]\, O => skid_buffer(18) ); \m_payload_i[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(19), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[19]\, O => skid_buffer(19) ); \m_payload_i[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[1]\, O => skid_buffer(1) ); \m_payload_i[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(20), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[20]\, O => skid_buffer(20) ); \m_payload_i[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(21), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[21]\, O => skid_buffer(21) ); \m_payload_i[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(22), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[22]\, O => skid_buffer(22) ); \m_payload_i[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(23), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[23]\, O => skid_buffer(23) ); \m_payload_i[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(24), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[24]\, O => skid_buffer(24) ); \m_payload_i[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(25), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[25]\, O => skid_buffer(25) ); \m_payload_i[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(26), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[26]\, O => skid_buffer(26) ); \m_payload_i[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(27), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[27]\, O => skid_buffer(27) ); \m_payload_i[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(28), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[28]\, O => skid_buffer(28) ); \m_payload_i[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(29), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[29]\, O => skid_buffer(29) ); \m_payload_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[2]\, O => skid_buffer(2) ); \m_payload_i[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(30), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[30]\, O => skid_buffer(30) ); \m_payload_i[31]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(31), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[31]\, O => skid_buffer(31) ); \m_payload_i[32]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[32]\, O => skid_buffer(32) ); \m_payload_i[33]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[33]\, O => skid_buffer(33) ); \m_payload_i[34]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[34]\, O => skid_buffer(34) ); \m_payload_i[35]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awsize(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[35]\, O => skid_buffer(35) ); \m_payload_i[36]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awsize(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[36]\, O => skid_buffer(36) ); \m_payload_i[38]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awburst(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[38]\, O => skid_buffer(38) ); \m_payload_i[39]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awburst(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[39]\, O => skid_buffer(39) ); \m_payload_i[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[3]\, O => skid_buffer(3) ); \m_payload_i[44]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[44]\, O => skid_buffer(44) ); \m_payload_i[45]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[45]\, O => skid_buffer(45) ); \m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[46]\, O => skid_buffer(46) ); \m_payload_i[47]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[47]\, O => skid_buffer(47) ); \m_payload_i[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(4), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[4]\, O => skid_buffer(4) ); \m_payload_i[50]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[50]\, O => skid_buffer(50) ); \m_payload_i[51]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[51]\, O => skid_buffer(51) ); \m_payload_i[52]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[52]\, O => skid_buffer(52) ); \m_payload_i[53]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[53]\, O => skid_buffer(53) ); \m_payload_i[54]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(4), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[54]\, O => skid_buffer(54) ); \m_payload_i[55]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(5), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[55]\, O => skid_buffer(55) ); \m_payload_i[56]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(6), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[56]\, O => skid_buffer(56) ); \m_payload_i[57]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(7), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[57]\, O => skid_buffer(57) ); \m_payload_i[58]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(8), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[58]\, O => skid_buffer(58) ); \m_payload_i[59]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(9), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[59]\, O => skid_buffer(59) ); \m_payload_i[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(5), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[5]\, O => skid_buffer(5) ); \m_payload_i[60]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(10), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[60]\, O => skid_buffer(60) ); \m_payload_i[61]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(11), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[61]\, O => skid_buffer(61) ); \m_payload_i[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(6), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[6]\, O => skid_buffer(6) ); \m_payload_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(7), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[7]\, O => skid_buffer(7) ); \m_payload_i[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(8), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[8]\, O => skid_buffer(8) ); \m_payload_i[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(9), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[9]\, O => skid_buffer(9) ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(0), Q => \^q\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(10), Q => \^q\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(11), Q => \^q\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(12), Q => \^q\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(13), Q => \^q\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(14), Q => \^q\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(15), Q => \^q\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(16), Q => \^q\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(17), Q => \^q\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(18), Q => \^q\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(19), Q => \^q\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(1), Q => \^q\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(20), Q => \^q\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(21), Q => \^q\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(22), Q => \^q\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(23), Q => \^q\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(24), Q => \^q\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(25), Q => \^q\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(26), Q => \^q\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(27), Q => \^q\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(28), Q => \^q\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(29), Q => \^q\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(2), Q => \^q\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(30), Q => \^q\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(31), Q => \^q\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(32), Q => \^q\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(33), Q => \^q\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(34), Q => \^q\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(35), Q => \^q\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(36), Q => \^q\(36), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(38), Q => \^q\(37), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(39), Q => \^q\(38), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(3), Q => \^q\(3), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(44), Q => \^q\(39), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(45), Q => \^q\(40), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(46), Q => \^q\(41), R => '0' ); \m_payload_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(47), Q => \^q\(42), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(4), Q => \^q\(4), R => '0' ); \m_payload_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(50), Q => \^q\(43), R => '0' ); \m_payload_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(51), Q => \^q\(44), R => '0' ); \m_payload_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(52), Q => \^q\(45), R => '0' ); \m_payload_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(53), Q => \^q\(46), R => '0' ); \m_payload_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(54), Q => \^q\(47), R => '0' ); \m_payload_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(55), Q => \^q\(48), R => '0' ); \m_payload_i_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(56), Q => \^q\(49), R => '0' ); \m_payload_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(57), Q => \^q\(50), R => '0' ); \m_payload_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(58), Q => \^q\(51), R => '0' ); \m_payload_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(59), Q => \^q\(52), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(5), Q => \^q\(5), R => '0' ); \m_payload_i_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(60), Q => \^q\(53), R => '0' ); \m_payload_i_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(61), Q => \^q\(54), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(6), Q => \^q\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(7), Q => \^q\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(8), Q => \^q\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(9), Q => \^q\(9), R => '0' ); m_valid_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => b_push, I1 => \^m_valid_i_reg_0\, I2 => s_axi_awvalid, I3 => \^s_axi_awready\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^m_valid_i_reg_0\, R => \aresetn_d_reg[1]_inv_0\ ); next_pending_r_i_4: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => \state_reg[1]_rep\, I1 => \^q\(42), I2 => \^q\(40), I3 => \^q\(39), I4 => \^q\(41), O => next_pending_r_reg ); \s_ready_i_i_1__1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \aresetn_d_reg_n_0_[0]\, O => \^s_ready_i_reg_0\ ); s_ready_i_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => s_axi_awvalid, I1 => \^s_axi_awready\, I2 => b_push, I3 => \^m_valid_i_reg_0\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^s_axi_awready\, R => \^s_ready_i_reg_0\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(2), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awsize(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awsize(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awburst(0), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awburst(1), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(0), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(1), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(2), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(3), Q => \skid_buffer_reg_n_0_[47]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(0), Q => \skid_buffer_reg_n_0_[50]\, R => '0' ); \skid_buffer_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(1), Q => \skid_buffer_reg_n_0_[51]\, R => '0' ); \skid_buffer_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(2), Q => \skid_buffer_reg_n_0_[52]\, R => '0' ); \skid_buffer_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(3), Q => \skid_buffer_reg_n_0_[53]\, R => '0' ); \skid_buffer_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(4), Q => \skid_buffer_reg_n_0_[54]\, R => '0' ); \skid_buffer_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(5), Q => \skid_buffer_reg_n_0_[55]\, R => '0' ); \skid_buffer_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(6), Q => \skid_buffer_reg_n_0_[56]\, R => '0' ); \skid_buffer_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(7), Q => \skid_buffer_reg_n_0_[57]\, R => '0' ); \skid_buffer_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(8), Q => \skid_buffer_reg_n_0_[58]\, R => '0' ); \skid_buffer_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(9), Q => \skid_buffer_reg_n_0_[59]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(10), Q => \skid_buffer_reg_n_0_[60]\, R => '0' ); \skid_buffer_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(11), Q => \skid_buffer_reg_n_0_[61]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); \wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(39), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(0) ); \wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"8A888AAA" ) port map ( I0 => \^q\(1), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(40), O => \wrap_boundary_axaddr_r_reg[6]\(1) ); \wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0F553300000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(36), I5 => \^q\(2), O => \wrap_boundary_axaddr_r_reg[6]\(2) ); \wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"020202A2A2A202A2" ) port map ( I0 => \^q\(3), I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\, I2 => \^q\(36), I3 => \^q\(40), I4 => \^q\(35), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(3) ); \wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(41), I1 => \^q\(35), I2 => \^q\(42), O => \wrap_boundary_axaddr_r[3]_i_2_n_0\ ); \wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"503F5F3F00000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(36), I3 => \^q\(35), I4 => \^q\(42), I5 => \^q\(4), O => \wrap_boundary_axaddr_r_reg[6]\(4) ); \wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"2A222AAA" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(41), I3 => \^q\(35), I4 => \^q\(42), O => \wrap_boundary_axaddr_r_reg[6]\(5) ); \wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2AAA" ) port map ( I0 => \^q\(6), I1 => \^q\(42), I2 => \^q\(35), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(6) ); \wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA6AA56AAAAAAAA" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(1), I1 => \wrap_second_len_r_reg[3]_0\(0), I2 => \state_reg[1]_rep\, I3 => \^wrap_cnt_r_reg[2]\, I4 => \^axaddr_offset_r_reg[0]\, I5 => \^wrap_second_len_r_reg[3]\(0), O => D(0) ); \wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(2), I1 => \wrap_second_len_r_reg[1]\, I2 => \^wrap_second_len_r_reg[3]\(1), O => D(1) ); \wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFEAEAFFEA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\, I1 => \^axlen_cnt_reg[3]\, I2 => \axaddr_offset_r[3]_i_2_n_0\, I3 => \^axaddr_offset_r_reg[2]\, I4 => \wrap_cnt_r[3]_i_5_n_0\, I5 => \axaddr_offset_r_reg[2]_1\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \^q\(41), I1 => \state_reg[0]_rep\, I2 => \^m_valid_i_reg_0\, I3 => \state_reg[1]_rep_0\, O => \wrap_cnt_r[3]_i_5_n_0\ ); \wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0001000000010001" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2_n_0\, I4 => \state_reg[1]_rep\, I5 => \axaddr_offset_r_reg[3]\(2), O => \^wrap_cnt_r_reg[2]\ ); \wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F00EFFFFF00E0000" ) port map ( I0 => \^axaddr_offset\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_r_reg[0]\, I3 => \^axaddr_offset\(0), I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(1), O => \^wrap_second_len_r_reg[3]\(0) ); \wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"CCC2FFFFCCC20000" ) port map ( I0 => \^axaddr_offset\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset\(0), I3 => \^axaddr_offset_r_reg[0]\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(2), O => \^wrap_second_len_r_reg[3]\(1) ); \wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FE00FFFFFE00FE00" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2_n_0\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(3), O => \^wrap_second_len_r_reg[3]\(2) ); \wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"A8A8A8080808A808" ) port map ( I0 => \^axlen_cnt_reg[3]\, I1 => \wrap_second_len_r[3]_i_3_n_0\, I2 => \^q\(36), I3 => \^q\(5), I4 => \^q\(35), I5 => \^q\(6), O => \wrap_second_len_r[3]_i_2_n_0\ ); \wrap_second_len_r[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(4), I1 => \^q\(35), I2 => \^q\(3), O => \wrap_second_len_r[3]_i_3_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is port ( s_axi_bvalid : out STD_LOGIC; \skid_buffer_reg[0]_0\ : out STD_LOGIC; \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \aresetn_d_reg[1]_inv\ : in STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; si_rs_bvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\; architecture STRUCTURE of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^s_axi_bvalid\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^skid_buffer_reg[0]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair79"; begin s_axi_bvalid <= \^s_axi_bvalid\; \skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\; \m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \s_bresp_acc_reg[1]\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__1_n_0\ ); \m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__1_n_0\ ); \m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__1_n_0\ ); \m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__1_n_0\ ); \m_payload_i[13]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, O => p_1_in ); \m_payload_i[13]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_2_n_0\ ); \m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \s_bresp_acc_reg[1]\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__1_n_0\ ); \m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__1_n_0\ ); \m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__1_n_0\ ); \m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__1_n_0\ ); \m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__1_n_0\ ); \m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__1_n_0\ ); \m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__1_n_0\ ); \m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__1_n_0\ ); \m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__1_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[0]_i_1__1_n_0\, Q => \s_axi_bid[11]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[10]_i_1__1_n_0\, Q => \s_axi_bid[11]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[11]_i_1__1_n_0\, Q => \s_axi_bid[11]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[12]_i_1__1_n_0\, Q => \s_axi_bid[11]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[13]_i_2_n_0\, Q => \s_axi_bid[11]\(13), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[1]_i_1__1_n_0\, Q => \s_axi_bid[11]\(1), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[2]_i_1__1_n_0\, Q => \s_axi_bid[11]\(2), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[3]_i_1__1_n_0\, Q => \s_axi_bid[11]\(3), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[4]_i_1__1_n_0\, Q => \s_axi_bid[11]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[5]_i_1__1_n_0\, Q => \s_axi_bid[11]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[6]_i_1__1_n_0\, Q => \s_axi_bid[11]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[7]_i_1__1_n_0\, Q => \s_axi_bid[11]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[8]_i_1__1_n_0\, Q => \s_axi_bid[11]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[9]_i_1__1_n_0\, Q => \s_axi_bid[11]\(9), R => '0' ); \m_valid_i_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, I2 => si_rs_bvalid, I3 => \^skid_buffer_reg[0]_0\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^s_axi_bvalid\, R => \aresetn_d_reg[1]_inv\ ); s_ready_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => si_rs_bvalid, I1 => \^skid_buffer_reg[0]_0\, I2 => s_axi_bready, I3 => \^s_axi_bvalid\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^skid_buffer_reg[0]_0\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \s_bresp_acc_reg[1]\(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(8), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(9), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(10), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(11), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \s_bresp_acc_reg[1]\(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(0), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(1), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(2), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(3), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(4), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(5), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(6), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(7), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is port ( s_axi_rvalid : out STD_LOGIC; \skid_buffer_reg[0]_0\ : out STD_LOGIC; \cnt_read_reg[2]_rep__0\ : out STD_LOGIC; \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); \aresetn_d_reg[1]_inv\ : in STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; \cnt_read_reg[4]_rep__0\ : in STD_LOGIC; s_axi_rready : in STD_LOGIC; r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 ); \cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\; architecture STRUCTURE of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC; signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^s_axi_rvalid\ : STD_LOGIC; signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC; signal \^skid_buffer_reg[0]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[4]_i_4\ : label is "soft_lutpair84"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \s_ready_i_i_1__2\ : label is "soft_lutpair84"; begin s_axi_rvalid <= \^s_axi_rvalid\; \skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\; \cnt_read[4]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^skid_buffer_reg[0]_0\, I1 => \cnt_read_reg[4]_rep__0\, O => \cnt_read_reg[2]_rep__0\ ); \m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__2_n_0\ ); \m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__2_n_0\ ); \m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__2_n_0\ ); \m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(12), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__2_n_0\ ); \m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(13), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_1__2_n_0\ ); \m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(14), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[14]\, O => \m_payload_i[14]_i_1__1_n_0\ ); \m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(15), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[15]\, O => \m_payload_i[15]_i_1__1_n_0\ ); \m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(16), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[16]\, O => \m_payload_i[16]_i_1__1_n_0\ ); \m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(17), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[17]\, O => \m_payload_i[17]_i_1__1_n_0\ ); \m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(18), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[18]\, O => \m_payload_i[18]_i_1__1_n_0\ ); \m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(19), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[19]\, O => \m_payload_i[19]_i_1__1_n_0\ ); \m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__2_n_0\ ); \m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(20), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[20]\, O => \m_payload_i[20]_i_1__1_n_0\ ); \m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(21), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[21]\, O => \m_payload_i[21]_i_1__1_n_0\ ); \m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(22), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[22]\, O => \m_payload_i[22]_i_1__1_n_0\ ); \m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(23), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[23]\, O => \m_payload_i[23]_i_1__1_n_0\ ); \m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(24), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[24]\, O => \m_payload_i[24]_i_1__1_n_0\ ); \m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(25), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[25]\, O => \m_payload_i[25]_i_1__1_n_0\ ); \m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(26), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[26]\, O => \m_payload_i[26]_i_1__1_n_0\ ); \m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(27), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[27]\, O => \m_payload_i[27]_i_1__1_n_0\ ); \m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(28), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[28]\, O => \m_payload_i[28]_i_1__1_n_0\ ); \m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(29), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[29]\, O => \m_payload_i[29]_i_1__1_n_0\ ); \m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__2_n_0\ ); \m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(30), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[30]\, O => \m_payload_i[30]_i_1__1_n_0\ ); \m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(31), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[31]\, O => \m_payload_i[31]_i_1__1_n_0\ ); \m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(32), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[32]\, O => \m_payload_i[32]_i_1__1_n_0\ ); \m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(33), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[33]\, O => \m_payload_i[33]_i_1__1_n_0\ ); \m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[34]\, O => \m_payload_i[34]_i_1__1_n_0\ ); \m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[35]\, O => \m_payload_i[35]_i_1__1_n_0\ ); \m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[36]\, O => \m_payload_i[36]_i_1__1_n_0\ ); \m_payload_i[37]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[37]\, O => \m_payload_i[37]_i_1_n_0\ ); \m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[38]\, O => \m_payload_i[38]_i_1__1_n_0\ ); \m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[39]\, O => \m_payload_i[39]_i_1__1_n_0\ ); \m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__2_n_0\ ); \m_payload_i[40]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[40]\, O => \m_payload_i[40]_i_1_n_0\ ); \m_payload_i[41]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[41]\, O => \m_payload_i[41]_i_1_n_0\ ); \m_payload_i[42]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[42]\, O => \m_payload_i[42]_i_1_n_0\ ); \m_payload_i[43]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[43]\, O => \m_payload_i[43]_i_1_n_0\ ); \m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[44]\, O => \m_payload_i[44]_i_1__1_n_0\ ); \m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[45]\, O => \m_payload_i[45]_i_1__1_n_0\ ); \m_payload_i[46]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, O => p_1_in ); \m_payload_i[46]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(12), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[46]\, O => \m_payload_i[46]_i_2_n_0\ ); \m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__2_n_0\ ); \m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__2_n_0\ ); \m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__2_n_0\ ); \m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__2_n_0\ ); \m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__2_n_0\ ); \m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__2_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[0]_i_1__2_n_0\, Q => \s_axi_rid[11]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[10]_i_1__2_n_0\, Q => \s_axi_rid[11]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[11]_i_1__2_n_0\, Q => \s_axi_rid[11]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[12]_i_1__2_n_0\, Q => \s_axi_rid[11]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[13]_i_1__2_n_0\, Q => \s_axi_rid[11]\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[14]_i_1__1_n_0\, Q => \s_axi_rid[11]\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[15]_i_1__1_n_0\, Q => \s_axi_rid[11]\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[16]_i_1__1_n_0\, Q => \s_axi_rid[11]\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[17]_i_1__1_n_0\, Q => \s_axi_rid[11]\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[18]_i_1__1_n_0\, Q => \s_axi_rid[11]\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[19]_i_1__1_n_0\, Q => \s_axi_rid[11]\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[1]_i_1__2_n_0\, Q => \s_axi_rid[11]\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[20]_i_1__1_n_0\, Q => \s_axi_rid[11]\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[21]_i_1__1_n_0\, Q => \s_axi_rid[11]\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[22]_i_1__1_n_0\, Q => \s_axi_rid[11]\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[23]_i_1__1_n_0\, Q => \s_axi_rid[11]\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[24]_i_1__1_n_0\, Q => \s_axi_rid[11]\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[25]_i_1__1_n_0\, Q => \s_axi_rid[11]\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[26]_i_1__1_n_0\, Q => \s_axi_rid[11]\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[27]_i_1__1_n_0\, Q => \s_axi_rid[11]\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[28]_i_1__1_n_0\, Q => \s_axi_rid[11]\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[29]_i_1__1_n_0\, Q => \s_axi_rid[11]\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[2]_i_1__2_n_0\, Q => \s_axi_rid[11]\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[30]_i_1__1_n_0\, Q => \s_axi_rid[11]\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[31]_i_1__1_n_0\, Q => \s_axi_rid[11]\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[32]_i_1__1_n_0\, Q => \s_axi_rid[11]\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[33]_i_1__1_n_0\, Q => \s_axi_rid[11]\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[34]_i_1__1_n_0\, Q => \s_axi_rid[11]\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[35]_i_1__1_n_0\, Q => \s_axi_rid[11]\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[36]_i_1__1_n_0\, Q => \s_axi_rid[11]\(36), R => '0' ); \m_payload_i_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[37]_i_1_n_0\, Q => \s_axi_rid[11]\(37), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[38]_i_1__1_n_0\, Q => \s_axi_rid[11]\(38), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[39]_i_1__1_n_0\, Q => \s_axi_rid[11]\(39), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[3]_i_1__2_n_0\, Q => \s_axi_rid[11]\(3), R => '0' ); \m_payload_i_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[40]_i_1_n_0\, Q => \s_axi_rid[11]\(40), R => '0' ); \m_payload_i_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[41]_i_1_n_0\, Q => \s_axi_rid[11]\(41), R => '0' ); \m_payload_i_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[42]_i_1_n_0\, Q => \s_axi_rid[11]\(42), R => '0' ); \m_payload_i_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[43]_i_1_n_0\, Q => \s_axi_rid[11]\(43), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[44]_i_1__1_n_0\, Q => \s_axi_rid[11]\(44), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[45]_i_1__1_n_0\, Q => \s_axi_rid[11]\(45), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[46]_i_2_n_0\, Q => \s_axi_rid[11]\(46), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[4]_i_1__2_n_0\, Q => \s_axi_rid[11]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[5]_i_1__2_n_0\, Q => \s_axi_rid[11]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[6]_i_1__2_n_0\, Q => \s_axi_rid[11]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[7]_i_1__2_n_0\, Q => \s_axi_rid[11]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[8]_i_1__2_n_0\, Q => \s_axi_rid[11]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[9]_i_1__2_n_0\, Q => \s_axi_rid[11]\(9), R => '0' ); \m_valid_i_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"4FFF" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, I2 => \cnt_read_reg[4]_rep__0\, I3 => \^skid_buffer_reg[0]_0\, O => \m_valid_i_i_1__2_n_0\ ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \m_valid_i_i_1__2_n_0\, Q => \^s_axi_rvalid\, R => \aresetn_d_reg[1]_inv\ ); \s_ready_i_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"F8FF" ) port map ( I0 => \cnt_read_reg[4]_rep__0\, I1 => \^skid_buffer_reg[0]_0\, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, O => \s_ready_i_i_1__2_n_0\ ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \s_ready_i_i_1__2_n_0\, Q => \^skid_buffer_reg[0]_0\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(32), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(33), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(0), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(1), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(2), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(3), Q => \skid_buffer_reg_n_0_[37]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(4), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(5), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(6), Q => \skid_buffer_reg_n_0_[40]\, R => '0' ); \skid_buffer_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(7), Q => \skid_buffer_reg_n_0_[41]\, R => '0' ); \skid_buffer_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(8), Q => \skid_buffer_reg_n_0_[42]\, R => '0' ); \skid_buffer_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(9), Q => \skid_buffer_reg_n_0_[43]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(10), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(11), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(12), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel is port ( si_rs_bvalid : out STD_LOGIC; \cnt_read_reg[0]_rep__0\ : out STD_LOGIC; \cnt_read_reg[1]_rep__0\ : out STD_LOGIC; m_axi_bready : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); \skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); areset_d1 : in STD_LOGIC; aclk : in STD_LOGIC; b_push : in STD_LOGIC; si_rs_bready : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel is signal bid_fifo_0_n_3 : STD_LOGIC; signal bid_fifo_0_n_5 : STD_LOGIC; signal \bresp_cnt[7]_i_6_n_0\ : STD_LOGIC; signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal bresp_push : STD_LOGIC; signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 ); signal mhandshake : STD_LOGIC; signal mhandshake_r : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s_bresp_acc0 : STD_LOGIC; signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC; signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC; signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC; signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC; signal shandshake : STD_LOGIC; signal shandshake_r : STD_LOGIC; signal \^si_rs_bvalid\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair124"; attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair124"; begin si_rs_bvalid <= \^si_rs_bvalid\; bid_fifo_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo port map ( D(0) => bid_fifo_0_n_3, Q(1 downto 0) => cnt_read(1 downto 0), SR(0) => s_bresp_acc0, aclk => aclk, areset_d1 => areset_d1, b_push => b_push, \bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0), bresp_push => bresp_push, bvalid_i_reg => bid_fifo_0_n_5, bvalid_i_reg_0 => \^si_rs_bvalid\, \cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\, \cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0\, \in\(15 downto 0) => \in\(15 downto 0), mhandshake_r => mhandshake_r, \out\(11 downto 0) => \out\(11 downto 0), shandshake_r => shandshake_r, si_rs_bready => si_rs_bready ); \bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \bresp_cnt_reg__0\(0), O => p_0_in(0) ); \bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bresp_cnt_reg__0\(1), I1 => \bresp_cnt_reg__0\(0), O => p_0_in(1) ); \bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \bresp_cnt_reg__0\(2), I1 => \bresp_cnt_reg__0\(0), I2 => \bresp_cnt_reg__0\(1), O => p_0_in(2) ); \bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \bresp_cnt_reg__0\(3), I1 => \bresp_cnt_reg__0\(1), I2 => \bresp_cnt_reg__0\(0), I3 => \bresp_cnt_reg__0\(2), O => p_0_in(3) ); \bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \bresp_cnt_reg__0\(4), I1 => \bresp_cnt_reg__0\(2), I2 => \bresp_cnt_reg__0\(0), I3 => \bresp_cnt_reg__0\(1), I4 => \bresp_cnt_reg__0\(3), O => p_0_in(4) ); \bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => \bresp_cnt_reg__0\(5), I1 => \bresp_cnt_reg__0\(3), I2 => \bresp_cnt_reg__0\(1), I3 => \bresp_cnt_reg__0\(0), I4 => \bresp_cnt_reg__0\(2), I5 => \bresp_cnt_reg__0\(4), O => p_0_in(5) ); \bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bresp_cnt_reg__0\(6), I1 => \bresp_cnt[7]_i_6_n_0\, O => p_0_in(6) ); \bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \bresp_cnt_reg__0\(7), I1 => \bresp_cnt[7]_i_6_n_0\, I2 => \bresp_cnt_reg__0\(6), O => p_0_in(7) ); \bresp_cnt[7]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \bresp_cnt_reg__0\(5), I1 => \bresp_cnt_reg__0\(3), I2 => \bresp_cnt_reg__0\(1), I3 => \bresp_cnt_reg__0\(0), I4 => \bresp_cnt_reg__0\(2), I5 => \bresp_cnt_reg__0\(4), O => \bresp_cnt[7]_i_6_n_0\ ); \bresp_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(0), Q => \bresp_cnt_reg__0\(0), R => s_bresp_acc0 ); \bresp_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(1), Q => \bresp_cnt_reg__0\(1), R => s_bresp_acc0 ); \bresp_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(2), Q => \bresp_cnt_reg__0\(2), R => s_bresp_acc0 ); \bresp_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(3), Q => \bresp_cnt_reg__0\(3), R => s_bresp_acc0 ); \bresp_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(4), Q => \bresp_cnt_reg__0\(4), R => s_bresp_acc0 ); \bresp_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(5), Q => \bresp_cnt_reg__0\(5), R => s_bresp_acc0 ); \bresp_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(6), Q => \bresp_cnt_reg__0\(6), R => s_bresp_acc0 ); \bresp_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(7), Q => \bresp_cnt_reg__0\(7), R => s_bresp_acc0 ); bresp_fifo_0: entity work.\design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ port map ( D(0) => bid_fifo_0_n_3, Q(1 downto 0) => cnt_read(1 downto 0), aclk => aclk, areset_d1 => areset_d1, \in\(1) => \s_bresp_acc_reg_n_0_[1]\, \in\(0) => \s_bresp_acc_reg_n_0_[0]\, m_axi_bready => m_axi_bready, m_axi_bvalid => m_axi_bvalid, mhandshake => mhandshake, mhandshake_r => mhandshake_r, sel => bresp_push, shandshake_r => shandshake_r, \skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0) ); bvalid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => bid_fifo_0_n_5, Q => \^si_rs_bvalid\, R => '0' ); mhandshake_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => mhandshake, Q => mhandshake_r, R => areset_d1 ); \s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000EACEAAAA" ) port map ( I0 => \s_bresp_acc_reg_n_0_[0]\, I1 => m_axi_bresp(0), I2 => m_axi_bresp(1), I3 => \s_bresp_acc_reg_n_0_[1]\, I4 => mhandshake, I5 => s_bresp_acc0, O => \s_bresp_acc[0]_i_1_n_0\ ); \s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"00EC" ) port map ( I0 => m_axi_bresp(1), I1 => \s_bresp_acc_reg_n_0_[1]\, I2 => mhandshake, I3 => s_bresp_acc0, O => \s_bresp_acc[1]_i_1_n_0\ ); \s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \s_bresp_acc[0]_i_1_n_0\, Q => \s_bresp_acc_reg_n_0_[0]\, R => '0' ); \s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \s_bresp_acc[1]_i_1_n_0\, Q => \s_bresp_acc_reg_n_0_[1]\, R => '0' ); shandshake_r_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^si_rs_bvalid\, I1 => si_rs_bready, O => shandshake ); shandshake_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => shandshake, Q => shandshake_r, R => areset_d1 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator is port ( next_pending_r_reg : out STD_LOGIC; wrap_next_pending : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; sel_first_0 : out STD_LOGIC; sel_first : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[2]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); incr_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; sel_first_i : in STD_LOGIC; \m_payload_i_reg[39]\ : in STD_LOGIC; \m_payload_i_reg[39]_0\ : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 19 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_awvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \m_payload_i_reg[47]_1\ : in STD_LOGIC; \next\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[0]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator is signal incr_cmd_0_n_10 : STD_LOGIC; signal incr_cmd_0_n_11 : STD_LOGIC; signal incr_cmd_0_n_12 : STD_LOGIC; signal incr_cmd_0_n_13 : STD_LOGIC; signal incr_cmd_0_n_14 : STD_LOGIC; signal incr_cmd_0_n_15 : STD_LOGIC; signal incr_cmd_0_n_16 : STD_LOGIC; signal incr_cmd_0_n_4 : STD_LOGIC; signal incr_cmd_0_n_5 : STD_LOGIC; signal incr_cmd_0_n_6 : STD_LOGIC; signal incr_cmd_0_n_7 : STD_LOGIC; signal incr_cmd_0_n_8 : STD_LOGIC; signal incr_cmd_0_n_9 : STD_LOGIC; signal s_axburst_eq0 : STD_LOGIC; signal s_axburst_eq1 : STD_LOGIC; begin incr_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd port map ( E(0) => E(0), Q(0) => Q(0), S(3 downto 0) => S(3 downto 0), aclk => aclk, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_incr_reg[0]_0\ => sel_first_0, \axaddr_incr_reg[11]_0\(10) => incr_cmd_0_n_4, \axaddr_incr_reg[11]_0\(9) => incr_cmd_0_n_5, \axaddr_incr_reg[11]_0\(8) => incr_cmd_0_n_6, \axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_7, \axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_8, \axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_9, \axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_10, \axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_11, \axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_12, \axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_13, \axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_14, \axlen_cnt_reg[2]_0\ => \axlen_cnt_reg[2]\, incr_next_pending => incr_next_pending, \m_axi_awaddr[11]\ => incr_cmd_0_n_15, \m_axi_awaddr[5]\ => incr_cmd_0_n_16, \m_payload_i_reg[46]\(9 downto 8) => \m_payload_i_reg[47]\(18 downto 17), \m_payload_i_reg[46]\(7 downto 5) => \m_payload_i_reg[47]\(14 downto 12), \m_payload_i_reg[46]\(4) => \m_payload_i_reg[47]\(5), \m_payload_i_reg[46]\(3 downto 0) => \m_payload_i_reg[47]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \next\ => \next\, next_pending_r_reg_0 => next_pending_r_reg, sel_first_reg_0 => sel_first_reg_1, \state_reg[0]\(0) => \state_reg[0]\(0), \state_reg[0]_rep\ => \state_reg[0]_rep\, \state_reg[1]\(0) => \state_reg[1]_0\(0) ); \memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axburst_eq1, I1 => \m_payload_i_reg[47]\(15), I2 => s_axburst_eq0, O => \state_reg[1]_rep\ ); s_axburst_eq0_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]\, Q => s_axburst_eq0, R => '0' ); s_axburst_eq1_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]_0\, Q => s_axburst_eq1, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_i, Q => sel_first_reg_0, R => '0' ); wrap_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd port map ( D(3 downto 0) => D(3 downto 0), E(0) => E(0), aclk => aclk, \axaddr_incr_reg[11]\(10) => incr_cmd_0_n_4, \axaddr_incr_reg[11]\(9) => incr_cmd_0_n_5, \axaddr_incr_reg[11]\(8) => incr_cmd_0_n_6, \axaddr_incr_reg[11]\(7) => incr_cmd_0_n_7, \axaddr_incr_reg[11]\(6) => incr_cmd_0_n_8, \axaddr_incr_reg[11]\(5) => incr_cmd_0_n_9, \axaddr_incr_reg[11]\(4) => incr_cmd_0_n_10, \axaddr_incr_reg[11]\(3) => incr_cmd_0_n_11, \axaddr_incr_reg[11]\(2) => incr_cmd_0_n_12, \axaddr_incr_reg[11]\(1) => incr_cmd_0_n_13, \axaddr_incr_reg[11]\(0) => incr_cmd_0_n_14, \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), \m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[47]\(19 downto 15), \m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[47]\(13 downto 0), \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_1\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \next\ => \next\, sel_first_reg_0 => sel_first, sel_first_reg_1 => sel_first_reg_2, sel_first_reg_2 => incr_cmd_0_n_15, sel_first_reg_3 => incr_cmd_0_n_16, si_rs_awvalid => si_rs_awvalid, \state_reg[0]\(0) => \state_reg[0]\(0), \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0), \wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is port ( sel_first_reg_0 : out STD_LOGIC; sel_first : out STD_LOGIC; sel_first_reg_1 : out STD_LOGIC; \axlen_cnt_reg[0]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); r_rlast : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_i : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; sel_first_reg_3 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 19 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_arvalid : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[0]_rep_0\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); sel_first_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_17_b2s_cmd_translator"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is signal incr_cmd_0_n_10 : STD_LOGIC; signal incr_cmd_0_n_11 : STD_LOGIC; signal incr_cmd_0_n_12 : STD_LOGIC; signal incr_cmd_0_n_13 : STD_LOGIC; signal incr_cmd_0_n_14 : STD_LOGIC; signal incr_cmd_0_n_15 : STD_LOGIC; signal incr_cmd_0_n_3 : STD_LOGIC; signal incr_cmd_0_n_4 : STD_LOGIC; signal incr_cmd_0_n_5 : STD_LOGIC; signal incr_cmd_0_n_6 : STD_LOGIC; signal incr_cmd_0_n_7 : STD_LOGIC; signal incr_cmd_0_n_8 : STD_LOGIC; signal incr_cmd_0_n_9 : STD_LOGIC; signal incr_next_pending : STD_LOGIC; signal s_axburst_eq0 : STD_LOGIC; signal s_axburst_eq1 : STD_LOGIC; signal wrap_cmd_0_n_6 : STD_LOGIC; signal wrap_cmd_0_n_7 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair17"; begin incr_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 port map ( E(0) => E(0), O(3 downto 0) => O(3 downto 0), Q(10 downto 8) => Q(18 downto 16), Q(7 downto 5) => Q(14 downto 12), Q(4) => Q(5), Q(3 downto 0) => Q(3 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, \axaddr_incr_reg[0]_0\ => sel_first, \axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_3, \axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_4, \axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_5, \axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_6, \axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_7, \axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_8, \axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_9, \axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_10, \axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\, incr_next_pending => incr_next_pending, \m_axi_araddr[11]\ => incr_cmd_0_n_11, \m_axi_araddr[1]\ => incr_cmd_0_n_15, \m_axi_araddr[2]\ => incr_cmd_0_n_14, \m_axi_araddr[3]\ => incr_cmd_0_n_13, \m_axi_araddr[5]\ => incr_cmd_0_n_12, m_axi_arready => m_axi_arready, \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0), m_valid_i_reg(0) => m_valid_i_reg(0), sel_first_reg_0 => sel_first_reg_2, sel_first_reg_1(0) => sel_first_reg_4(0), si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\ => \state_reg[0]_rep_0\, \state_reg[1]\ => \state_reg[1]_0\, \state_reg[1]_0\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\ ); r_rlast_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => s_axburst_eq0, I1 => Q(15), I2 => s_axburst_eq1, O => r_rlast ); s_axburst_eq0_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cmd_0_n_6, Q => s_axburst_eq0, R => '0' ); s_axburst_eq1_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cmd_0_n_7, Q => s_axburst_eq1, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_i, Q => sel_first_reg_0, R => '0' ); \state[1]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axburst_eq1, I1 => Q(15), I2 => s_axburst_eq0, O => \state_reg[0]_rep\ ); wrap_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 port map ( D(3 downto 0) => D(3 downto 0), E(0) => E(0), Q(18 downto 14) => Q(19 downto 15), Q(13 downto 0) => Q(13 downto 0), aclk => aclk, \axaddr_incr_reg[11]\(7) => incr_cmd_0_n_3, \axaddr_incr_reg[11]\(6) => incr_cmd_0_n_4, \axaddr_incr_reg[11]\(5) => incr_cmd_0_n_5, \axaddr_incr_reg[11]\(4) => incr_cmd_0_n_6, \axaddr_incr_reg[11]\(3) => incr_cmd_0_n_7, \axaddr_incr_reg[11]\(2) => incr_cmd_0_n_8, \axaddr_incr_reg[11]\(1) => incr_cmd_0_n_9, \axaddr_incr_reg[11]\(0) => incr_cmd_0_n_10, \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\, incr_next_pending => incr_next_pending, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), m_valid_i_reg(0) => m_valid_i_reg(0), s_axburst_eq0_reg => wrap_cmd_0_n_6, s_axburst_eq1_reg => wrap_cmd_0_n_7, sel_first_i => sel_first_i, sel_first_reg_0 => sel_first_reg_1, sel_first_reg_1 => sel_first_reg_3, sel_first_reg_2 => incr_cmd_0_n_11, sel_first_reg_3 => incr_cmd_0_n_12, sel_first_reg_4 => incr_cmd_0_n_13, sel_first_reg_5 => incr_cmd_0_n_14, sel_first_reg_6 => incr_cmd_0_n_15, si_rs_arvalid => si_rs_arvalid, \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0), \wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel is port ( m_valid_i_reg : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; m_axi_rready : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); \skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); \state_reg[1]_rep_0\ : in STD_LOGIC; aclk : in STD_LOGIC; r_rlast : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; si_rs_rready : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); areset_d1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 11 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel is signal \^m_valid_i_reg\ : STD_LOGIC; signal r_push_r : STD_LOGIC; signal rd_data_fifo_0_n_0 : STD_LOGIC; signal rd_data_fifo_0_n_1 : STD_LOGIC; signal rd_data_fifo_0_n_2 : STD_LOGIC; signal rd_data_fifo_0_n_4 : STD_LOGIC; signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 ); begin m_valid_i_reg <= \^m_valid_i_reg\; \r_arid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => trans_in(1), R => '0' ); \r_arid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(10), Q => trans_in(11), R => '0' ); \r_arid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(11), Q => trans_in(12), R => '0' ); \r_arid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => trans_in(2), R => '0' ); \r_arid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => trans_in(3), R => '0' ); \r_arid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => trans_in(4), R => '0' ); \r_arid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(4), Q => trans_in(5), R => '0' ); \r_arid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(5), Q => trans_in(6), R => '0' ); \r_arid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(6), Q => trans_in(7), R => '0' ); \r_arid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(7), Q => trans_in(8), R => '0' ); \r_arid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(8), Q => trans_in(9), R => '0' ); \r_arid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(9), Q => trans_in(10), R => '0' ); r_push_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \state_reg[1]_rep_0\, Q => r_push_r, R => '0' ); r_rlast_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => r_rlast, Q => trans_in(0), R => '0' ); rd_data_fifo_0: entity work.\design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ port map ( aclk => aclk, areset_d1 => areset_d1, \cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\, \cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_0, \cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_1, \cnt_read_reg[4]_rep__2_2\ => rd_data_fifo_0_n_2, \in\(33 downto 0) => \in\(33 downto 0), m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, \out\(33 downto 0) => \out\(33 downto 0), s_ready_i_reg => s_ready_i_reg, si_rs_rready => si_rs_rready, \state_reg[1]_rep\ => rd_data_fifo_0_n_4 ); transaction_fifo_0: entity work.\design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ port map ( aclk => aclk, areset_d1 => areset_d1, \cnt_read_reg[0]_rep__3\ => rd_data_fifo_0_n_2, \cnt_read_reg[0]_rep__3_0\ => rd_data_fifo_0_n_4, \cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0, \cnt_read_reg[4]_rep__2\ => rd_data_fifo_0_n_1, \in\(12 downto 0) => trans_in(12 downto 0), m_valid_i_reg => \^m_valid_i_reg\, r_push_r => r_push_r, s_ready_i_reg => s_ready_i_reg, si_rs_rready => si_rs_rready, \skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice is port ( s_axi_awready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; si_rs_awvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; si_rs_bready : out STD_LOGIC; si_rs_arvalid : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; si_rs_rready : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); \axlen_cnt_reg[3]_0\ : out STD_LOGIC; \s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 54 downto 0 ); axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); O : out STD_LOGIC_VECTOR ( 3 downto 0 ); D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]_0\ : out STD_LOGIC; axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : out STD_LOGIC; next_pending_r_reg_0 : out STD_LOGIC; \cnt_read_reg[2]_rep__0\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); aclk : in STD_LOGIC; s_ready_i0 : in STD_LOGIC; m_valid_i0 : in STD_LOGIC; aresetn : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \cnt_read_reg[4]_rep__0\ : in STD_LOGIC; s_axi_rready : in STD_LOGIC; S : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_2\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; b_push : in STD_LOGIC; \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep_1\ : in STD_LOGIC; \wrap_second_len_r_reg[1]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_4\ : in STD_LOGIC; \state_reg[0]_rep_0\ : in STD_LOGIC; \state_reg[1]_rep_2\ : in STD_LOGIC; si_rs_bvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 ); \cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice; architecture STRUCTURE of design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice is signal \ar.ar_pipe_n_2\ : STD_LOGIC; signal \aw.aw_pipe_n_1\ : STD_LOGIC; signal \aw.aw_pipe_n_90\ : STD_LOGIC; begin \ar.ar_pipe\: entity work.design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice port map ( O(3 downto 0) => O(3 downto 0), Q(54 downto 0) => \s_arid_r_reg[11]\(54 downto 0), aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[0]_0\ => \aw.aw_pipe_n_90\, \axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), \axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), axaddr_offset_0(1 downto 0) => axaddr_offset_0(2 downto 1), \axaddr_offset_r_reg[0]\ => axaddr_offset_0(0), \axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]_0\, \axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_3\(0), \axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_4\, \axaddr_offset_r_reg[3]\ => si_rs_arvalid, \axaddr_offset_r_reg[3]_0\(2 downto 0) => \axaddr_offset_r_reg[3]_1\(2 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_2\, \axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\, \m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), m_valid_i0 => m_valid_i0, m_valid_i_reg_0 => \ar.ar_pipe_n_2\, m_valid_i_reg_1(0) => m_valid_i_reg(0), next_pending_r_reg => next_pending_r_reg_0, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_ready_i0 => s_ready_i0, \state_reg[0]_rep\ => \state_reg[0]_rep_0\, \state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep_1\, \state_reg[1]_rep_0\ => \state_reg[1]_rep_2\, \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0), \wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]_0\, \wrap_cnt_r_reg[3]\(1 downto 0) => \wrap_cnt_r_reg[3]_0\(1 downto 0), \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, \wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]_0\, \wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_2\(3 downto 0) ); \aw.aw_pipe\: entity work.design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 port map ( D(1 downto 0) => D(1 downto 0), E(0) => E(0), Q(54 downto 0) => Q(54 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, aresetn => aresetn, \aresetn_d_reg[1]_inv\ => \aw.aw_pipe_n_90\, \aresetn_d_reg[1]_inv_0\ => \ar.ar_pipe_n_2\, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), axaddr_offset(1 downto 0) => axaddr_offset(2 downto 1), \axaddr_offset_r_reg[0]\ => axaddr_offset(0), \axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]\, \axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_1\(0), \axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_2\, \axaddr_offset_r_reg[3]\(2 downto 0) => \axaddr_offset_r_reg[3]\(2 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\, b_push => b_push, m_valid_i_reg_0 => si_rs_awvalid, next_pending_r_reg => next_pending_r_reg, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, s_ready_i_reg_0 => \aw.aw_pipe_n_1\, \state_reg[0]_rep\ => \state_reg[0]_rep\, \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\, \state_reg[1]_rep_0\ => \state_reg[1]_rep_0\, \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0), \wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]\, \wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0) ); \b.b_pipe\: entity work.\design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ port map ( aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\, \out\(11 downto 0) => \out\(11 downto 0), \s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0), si_rs_bvalid => si_rs_bvalid, \skid_buffer_reg[0]_0\ => si_rs_bready ); \r.r_pipe\: entity work.\design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ port map ( aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\, \cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\, \cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0), \cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\, r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0), \s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, \skid_buffer_reg[0]_0\ => si_rs_rready ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel is port ( \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC; \m_payload_i_reg[0]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; m_valid_i0 : out STD_LOGIC; s_ready_i0 : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); r_rlast : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arready : in STD_LOGIC; si_rs_arvalid : in STD_LOGIC; \cnt_read_reg[2]_rep__0\ : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; areset_d1 : in STD_LOGIC; \m_payload_i_reg[5]\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel is signal ar_cmd_fsm_0_n_0 : STD_LOGIC; signal ar_cmd_fsm_0_n_10 : STD_LOGIC; signal ar_cmd_fsm_0_n_16 : STD_LOGIC; signal ar_cmd_fsm_0_n_6 : STD_LOGIC; signal ar_cmd_fsm_0_n_8 : STD_LOGIC; signal ar_cmd_fsm_0_n_9 : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal cmd_translator_0_n_0 : STD_LOGIC; signal cmd_translator_0_n_10 : STD_LOGIC; signal cmd_translator_0_n_2 : STD_LOGIC; signal cmd_translator_0_n_3 : STD_LOGIC; signal \incr_cmd_0/sel_first\ : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal \^r_push_r_reg\ : STD_LOGIC; signal sel_first_i : STD_LOGIC; signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC; signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 ); begin \axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0); \axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0); \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; r_push_r_reg <= \^r_push_r_reg\; \state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0); \wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\; \wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0); ar_cmd_fsm_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm port map ( D(0) => ar_cmd_fsm_0_n_6, E(0) => ar_cmd_fsm_0_n_8, Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), aclk => aclk, areset_d1 => areset_d1, \axaddr_incr_reg[0]\(0) => ar_cmd_fsm_0_n_16, axaddr_offset(0) => axaddr_offset(0), \axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0), \axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2), \axlen_cnt_reg[7]\ => ar_cmd_fsm_0_n_0, \axlen_cnt_reg[7]_0\ => cmd_translator_0_n_3, \cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\, m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, \m_payload_i_reg[0]\ => \m_payload_i_reg[0]\, \m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]_0\, \m_payload_i_reg[0]_1\(0) => E(0), \m_payload_i_reg[46]\(0) => Q(18), \m_payload_i_reg[5]\ => \m_payload_i_reg[5]\, m_valid_i0 => m_valid_i0, r_push_r_reg => \^r_push_r_reg\, s_axburst_eq1_reg => cmd_translator_0_n_10, s_axi_arvalid => s_axi_arvalid, s_ready_i0 => s_ready_i0, s_ready_i_reg => s_ready_i_reg, sel_first => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg => ar_cmd_fsm_0_n_9, sel_first_reg_0 => ar_cmd_fsm_0_n_10, sel_first_reg_1 => cmd_translator_0_n_2, sel_first_reg_2 => cmd_translator_0_n_0, si_rs_arvalid => si_rs_arvalid, \wrap_boundary_axaddr_r_reg[11]\(0) => \^wrap_boundary_axaddr_r_reg[11]\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, \wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0) ); cmd_translator_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 port map ( D(3) => axaddr_offset(2), D(2) => \^axaddr_offset_r_reg[2]\(0), D(1 downto 0) => axaddr_offset(1 downto 0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, O(3 downto 0) => O(3 downto 0), Q(19 downto 0) => Q(19 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, \axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\, \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[0]\ => cmd_translator_0_n_3, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), m_axi_arready => m_axi_arready, \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0), m_valid_i_reg(0) => ar_cmd_fsm_0_n_8, r_rlast => r_rlast, sel_first => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg_0 => cmd_translator_0_n_0, sel_first_reg_1 => cmd_translator_0_n_2, sel_first_reg_2 => ar_cmd_fsm_0_n_10, sel_first_reg_3 => ar_cmd_fsm_0_n_9, sel_first_reg_4(0) => ar_cmd_fsm_0_n_16, si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\ => cmd_translator_0_n_10, \state_reg[0]_rep_0\ => \^m_payload_i_reg[0]_0\, \state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), \state_reg[1]_0\ => ar_cmd_fsm_0_n_0, \state_reg[1]_rep\ => \^r_push_r_reg\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 1) => D(2 downto 0), \wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[3]_1\(2 downto 1) => \wrap_second_len_r_reg[3]_0\(1 downto 0), \wrap_second_len_r_reg[3]_1\(0) => ar_cmd_fsm_0_n_6 ); \s_arid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(20), Q => \r_arid_r_reg[11]\(0), R => '0' ); \s_arid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(30), Q => \r_arid_r_reg[11]\(10), R => '0' ); \s_arid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(31), Q => \r_arid_r_reg[11]\(11), R => '0' ); \s_arid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(21), Q => \r_arid_r_reg[11]\(1), R => '0' ); \s_arid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(22), Q => \r_arid_r_reg[11]\(2), R => '0' ); \s_arid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(23), Q => \r_arid_r_reg[11]\(3), R => '0' ); \s_arid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(24), Q => \r_arid_r_reg[11]\(4), R => '0' ); \s_arid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(25), Q => \r_arid_r_reg[11]\(5), R => '0' ); \s_arid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(26), Q => \r_arid_r_reg[11]\(6), R => '0' ); \s_arid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(27), Q => \r_arid_r_reg[11]\(7), R => '0' ); \s_arid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(28), Q => \r_arid_r_reg[11]\(8), R => '0' ); \s_arid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(29), Q => \r_arid_r_reg[11]\(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel is port ( \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \axlen_cnt_reg[7]\ : out STD_LOGIC; \axlen_cnt_reg[7]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); b_push : out STD_LOGIC; m_axi_awvalid : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \in\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); si_rs_awvalid : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; \cnt_read_reg[0]_rep__0\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 1 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \m_payload_i_reg[47]_0\ : in STD_LOGIC; areset_d1 : in STD_LOGIC; \m_payload_i_reg[5]\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel is signal aw_cmd_fsm_0_n_12 : STD_LOGIC; signal aw_cmd_fsm_0_n_14 : STD_LOGIC; signal aw_cmd_fsm_0_n_15 : STD_LOGIC; signal aw_cmd_fsm_0_n_16 : STD_LOGIC; signal aw_cmd_fsm_0_n_2 : STD_LOGIC; signal aw_cmd_fsm_0_n_8 : STD_LOGIC; signal aw_cmd_fsm_0_n_9 : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal cmd_translator_0_n_0 : STD_LOGIC; signal cmd_translator_0_n_12 : STD_LOGIC; signal cmd_translator_0_n_2 : STD_LOGIC; signal cmd_translator_0_n_5 : STD_LOGIC; signal cmd_translator_0_n_6 : STD_LOGIC; signal \incr_cmd_0/sel_first\ : STD_LOGIC; signal incr_next_pending : STD_LOGIC; signal \next\ : STD_LOGIC; signal sel_first : STD_LOGIC; signal sel_first_i : STD_LOGIC; signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC; signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 0 to 0 ); signal wrap_next_pending : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 ); begin \axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0); \axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0); \state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0); \wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\; \wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0); aw_cmd_fsm_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm port map ( D(0) => wrap_cnt(0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), aclk => aclk, areset_d1 => areset_d1, axaddr_offset(0) => axaddr_offset(0), \axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0), \axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_wrap_reg[11]\(0) => aw_cmd_fsm_0_n_14, \axlen_cnt_reg[0]\(0) => aw_cmd_fsm_0_n_8, \axlen_cnt_reg[0]_0\(0) => cmd_translator_0_n_5, \axlen_cnt_reg[7]\ => \axlen_cnt_reg[7]\, \axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]_0\, \axlen_cnt_reg[7]_1\ => aw_cmd_fsm_0_n_2, \axlen_cnt_reg[7]_2\ => cmd_translator_0_n_6, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\, \cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\, incr_next_pending => incr_next_pending, m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, \m_payload_i_reg[0]\(0) => E(0), \m_payload_i_reg[46]\(2) => Q(18), \m_payload_i_reg[46]\(1 downto 0) => Q(16 downto 15), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[5]\ => \m_payload_i_reg[5]\, \next\ => \next\, next_pending_r_reg => cmd_translator_0_n_0, s_axburst_eq0_reg => aw_cmd_fsm_0_n_9, s_axburst_eq1_reg => aw_cmd_fsm_0_n_12, s_axburst_eq1_reg_0 => cmd_translator_0_n_12, sel_first => sel_first, sel_first_0 => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg => aw_cmd_fsm_0_n_15, sel_first_reg_0 => aw_cmd_fsm_0_n_16, sel_first_reg_1 => cmd_translator_0_n_2, si_rs_awvalid => si_rs_awvalid, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0) ); cmd_translator_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator port map ( D(3) => axaddr_offset(2), D(2) => \^axaddr_offset_r_reg[2]\(0), D(1 downto 0) => axaddr_offset(1 downto 0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, Q(0) => cmd_translator_0_n_5, S(3 downto 0) => S(3 downto 0), aclk => aclk, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\, \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[2]\ => cmd_translator_0_n_6, incr_next_pending => incr_next_pending, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), \m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_9, \m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_12, \m_payload_i_reg[47]\(19 downto 0) => Q(19 downto 0), \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_1\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \next\ => \next\, next_pending_r_reg => cmd_translator_0_n_0, sel_first => sel_first, sel_first_0 => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg_0 => cmd_translator_0_n_2, sel_first_reg_1 => aw_cmd_fsm_0_n_16, sel_first_reg_2 => aw_cmd_fsm_0_n_15, si_rs_awvalid => si_rs_awvalid, \state_reg[0]\(0) => aw_cmd_fsm_0_n_14, \state_reg[0]_rep\ => aw_cmd_fsm_0_n_2, \state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), \state_reg[1]_0\(0) => aw_cmd_fsm_0_n_8, \state_reg[1]_rep\ => cmd_translator_0_n_12, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_0\(2 downto 1) => D(1 downto 0), \wrap_second_len_r_reg[3]_0\(0) => wrap_cnt(0), \wrap_second_len_r_reg[3]_1\(3 downto 1) => \wrap_second_len_r_reg[3]_0\(2 downto 0), \wrap_second_len_r_reg[3]_1\(0) => \wrap_cmd_0/wrap_second_len\(0) ); \s_awid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(20), Q => \in\(4), R => '0' ); \s_awid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(30), Q => \in\(14), R => '0' ); \s_awid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(31), Q => \in\(15), R => '0' ); \s_awid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(21), Q => \in\(5), R => '0' ); \s_awid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(22), Q => \in\(6), R => '0' ); \s_awid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(23), Q => \in\(7), R => '0' ); \s_awid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(24), Q => \in\(8), R => '0' ); \s_awid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(25), Q => \in\(9), R => '0' ); \s_awid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(26), Q => \in\(10), R => '0' ); \s_awid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(27), Q => \in\(11), R => '0' ); \s_awid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(28), Q => \in\(12), R => '0' ); \s_awid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(29), Q => \in\(13), R => '0' ); \s_awlen_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(16), Q => \in\(0), R => '0' ); \s_awlen_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(17), Q => \in\(1), R => '0' ); \s_awlen_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(18), Q => \in\(2), R => '0' ); \s_awlen_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(19), Q => \in\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s is port ( s_axi_rvalid : out STD_LOGIC; s_axi_awready : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 22 downto 0 ); s_axi_arready : out STD_LOGIC; \m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 ); s_axi_bvalid : out STD_LOGIC; \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; m_axi_rready : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awready : in STD_LOGIC; m_axi_arready : in STD_LOGIC; s_axi_rready : in STD_LOGIC; aclk : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awvalid : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; aresetn : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s is signal \RD.ar_channel_0_n_0\ : STD_LOGIC; signal \RD.ar_channel_0_n_10\ : STD_LOGIC; signal \RD.ar_channel_0_n_11\ : STD_LOGIC; signal \RD.ar_channel_0_n_16\ : STD_LOGIC; signal \RD.ar_channel_0_n_3\ : STD_LOGIC; signal \RD.ar_channel_0_n_4\ : STD_LOGIC; signal \RD.ar_channel_0_n_46\ : STD_LOGIC; signal \RD.ar_channel_0_n_47\ : STD_LOGIC; signal \RD.ar_channel_0_n_48\ : STD_LOGIC; signal \RD.ar_channel_0_n_49\ : STD_LOGIC; signal \RD.ar_channel_0_n_5\ : STD_LOGIC; signal \RD.r_channel_0_n_0\ : STD_LOGIC; signal \RD.r_channel_0_n_1\ : STD_LOGIC; signal SI_REG_n_132 : STD_LOGIC; signal SI_REG_n_133 : STD_LOGIC; signal SI_REG_n_134 : STD_LOGIC; signal SI_REG_n_135 : STD_LOGIC; signal SI_REG_n_136 : STD_LOGIC; signal SI_REG_n_137 : STD_LOGIC; signal SI_REG_n_138 : STD_LOGIC; signal SI_REG_n_139 : STD_LOGIC; signal SI_REG_n_140 : STD_LOGIC; signal SI_REG_n_141 : STD_LOGIC; signal SI_REG_n_142 : STD_LOGIC; signal SI_REG_n_143 : STD_LOGIC; signal SI_REG_n_149 : STD_LOGIC; signal SI_REG_n_153 : STD_LOGIC; signal SI_REG_n_154 : STD_LOGIC; signal SI_REG_n_155 : STD_LOGIC; signal SI_REG_n_156 : STD_LOGIC; signal SI_REG_n_157 : STD_LOGIC; signal SI_REG_n_161 : STD_LOGIC; signal SI_REG_n_165 : STD_LOGIC; signal SI_REG_n_166 : STD_LOGIC; signal SI_REG_n_167 : STD_LOGIC; signal SI_REG_n_168 : STD_LOGIC; signal SI_REG_n_169 : STD_LOGIC; signal SI_REG_n_170 : STD_LOGIC; signal SI_REG_n_171 : STD_LOGIC; signal SI_REG_n_172 : STD_LOGIC; signal SI_REG_n_173 : STD_LOGIC; signal SI_REG_n_174 : STD_LOGIC; signal SI_REG_n_175 : STD_LOGIC; signal SI_REG_n_176 : STD_LOGIC; signal SI_REG_n_177 : STD_LOGIC; signal SI_REG_n_178 : STD_LOGIC; signal SI_REG_n_179 : STD_LOGIC; signal SI_REG_n_180 : STD_LOGIC; signal SI_REG_n_181 : STD_LOGIC; signal SI_REG_n_182 : STD_LOGIC; signal SI_REG_n_26 : STD_LOGIC; signal SI_REG_n_64 : STD_LOGIC; signal SI_REG_n_8 : STD_LOGIC; signal SI_REG_n_82 : STD_LOGIC; signal \WR.aw_channel_0_n_0\ : STD_LOGIC; signal \WR.aw_channel_0_n_10\ : STD_LOGIC; signal \WR.aw_channel_0_n_15\ : STD_LOGIC; signal \WR.aw_channel_0_n_3\ : STD_LOGIC; signal \WR.aw_channel_0_n_4\ : STD_LOGIC; signal \WR.aw_channel_0_n_47\ : STD_LOGIC; signal \WR.aw_channel_0_n_48\ : STD_LOGIC; signal \WR.aw_channel_0_n_49\ : STD_LOGIC; signal \WR.aw_channel_0_n_50\ : STD_LOGIC; signal \WR.aw_channel_0_n_9\ : STD_LOGIC; signal \WR.b_channel_0_n_1\ : STD_LOGIC; signal \WR.b_channel_0_n_2\ : STD_LOGIC; signal \ar.ar_pipe/m_valid_i0\ : STD_LOGIC; signal \ar.ar_pipe/p_1_in\ : STD_LOGIC; signal \ar.ar_pipe/s_ready_i0\ : STD_LOGIC; signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal areset_d1 : STD_LOGIC; signal areset_d1_i_1_n_0 : STD_LOGIC; signal \aw.aw_pipe/p_1_in\ : STD_LOGIC; signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axaddr_incr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal b_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal b_push : STD_LOGIC; signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal r_rlast : STD_LOGIC; signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \^s_axi_arready\ : STD_LOGIC; signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 ); signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_arvalid : STD_LOGIC; signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 ); signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_awvalid : STD_LOGIC; signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_bready : STD_LOGIC; signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_bvalid : STD_LOGIC; signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 ); signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_rlast : STD_LOGIC; signal si_rs_rready : STD_LOGIC; signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 2 ); begin s_axi_arready <= \^s_axi_arready\; \RD.ar_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel port map ( D(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1), E(0) => \ar.ar_pipe/p_1_in\, O(3) => SI_REG_n_140, O(2) => SI_REG_n_141, O(1) => SI_REG_n_142, O(0) => SI_REG_n_143, Q(31 downto 20) => s_arid(11 downto 0), Q(19 downto 16) => si_rs_arlen(3 downto 0), Q(15) => si_rs_arburst(1), Q(14) => SI_REG_n_82, Q(13 downto 12) => si_rs_arsize(1 downto 0), Q(11 downto 0) => si_rs_araddr(11 downto 0), S(3) => \RD.ar_channel_0_n_46\, S(2) => \RD.ar_channel_0_n_47\, S(1) => \RD.ar_channel_0_n_48\, S(0) => \RD.ar_channel_0_n_49\, aclk => aclk, areset_d1 => areset_d1, axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0), \axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2), \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => SI_REG_n_161, \axaddr_offset_r_reg[3]_1\ => SI_REG_n_165, \cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_1\, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, \m_payload_i_reg[0]\ => \RD.ar_channel_0_n_4\, \m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_5\, \m_payload_i_reg[3]\(3) => SI_REG_n_132, \m_payload_i_reg[3]\(2) => SI_REG_n_133, \m_payload_i_reg[3]\(1) => SI_REG_n_134, \m_payload_i_reg[3]\(0) => SI_REG_n_135, \m_payload_i_reg[47]\ => SI_REG_n_64, \m_payload_i_reg[47]_0\ => SI_REG_n_167, \m_payload_i_reg[5]\ => SI_REG_n_166, \m_payload_i_reg[6]\(6) => SI_REG_n_176, \m_payload_i_reg[6]\(5) => SI_REG_n_177, \m_payload_i_reg[6]\(4) => SI_REG_n_178, \m_payload_i_reg[6]\(3) => SI_REG_n_179, \m_payload_i_reg[6]\(2) => SI_REG_n_180, \m_payload_i_reg[6]\(1) => SI_REG_n_181, \m_payload_i_reg[6]\(0) => SI_REG_n_182, \m_payload_i_reg[7]\(3) => SI_REG_n_136, \m_payload_i_reg[7]\(2) => SI_REG_n_137, \m_payload_i_reg[7]\(1) => SI_REG_n_138, \m_payload_i_reg[7]\(0) => SI_REG_n_139, m_valid_i0 => \ar.ar_pipe/m_valid_i0\, \r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0), r_push_r_reg => \RD.ar_channel_0_n_3\, r_rlast => r_rlast, s_axi_arvalid => s_axi_arvalid, s_ready_i0 => \ar.ar_pipe/s_ready_i0\, s_ready_i_reg => \^s_axi_arready\, si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0), \wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_0\, \wrap_cnt_r_reg[3]\ => \RD.ar_channel_0_n_10\, \wrap_cnt_r_reg[3]_0\ => \RD.ar_channel_0_n_11\, \wrap_cnt_r_reg[3]_1\ => \RD.ar_channel_0_n_16\, \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0), \wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_156, \wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_157 ); \RD.r_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel port map ( D(11 downto 0) => s_arid_r(11 downto 0), aclk => aclk, areset_d1 => areset_d1, \in\(33 downto 0) => \in\(33 downto 0), m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, m_valid_i_reg => \RD.r_channel_0_n_0\, \out\(33 downto 32) => si_rs_rresp(1 downto 0), \out\(31 downto 0) => si_rs_rdata(31 downto 0), r_rlast => r_rlast, s_ready_i_reg => SI_REG_n_168, si_rs_rready => si_rs_rready, \skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0), \skid_buffer_reg[46]\(0) => si_rs_rlast, \state_reg[1]_rep\ => \RD.r_channel_0_n_1\, \state_reg[1]_rep_0\ => \RD.ar_channel_0_n_3\ ); SI_REG: entity work.design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice port map ( D(1 downto 0) => wrap_cnt(3 downto 2), E(0) => \aw.aw_pipe/p_1_in\, O(3) => SI_REG_n_140, O(2) => SI_REG_n_141, O(1) => SI_REG_n_142, O(0) => SI_REG_n_143, Q(54 downto 43) => s_awid(11 downto 0), Q(42 downto 39) => si_rs_awlen(3 downto 0), Q(38) => si_rs_awburst(1), Q(37) => SI_REG_n_26, Q(36 downto 35) => si_rs_awsize(1 downto 0), Q(34 downto 12) => Q(22 downto 0), Q(11 downto 0) => si_rs_awaddr(11 downto 0), S(3) => \WR.aw_channel_0_n_47\, S(2) => \WR.aw_channel_0_n_48\, S(1) => \WR.aw_channel_0_n_49\, S(0) => \WR.aw_channel_0_n_50\, aclk => aclk, aresetn => aresetn, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_incr_reg[3]\(3) => SI_REG_n_132, \axaddr_incr_reg[3]\(2) => SI_REG_n_133, \axaddr_incr_reg[3]\(1) => SI_REG_n_134, \axaddr_incr_reg[3]\(0) => SI_REG_n_135, \axaddr_incr_reg[7]\(3) => SI_REG_n_136, \axaddr_incr_reg[7]\(2) => SI_REG_n_137, \axaddr_incr_reg[7]\(1) => SI_REG_n_138, \axaddr_incr_reg[7]\(0) => SI_REG_n_139, axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0), axaddr_offset_0(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3), axaddr_offset_0(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0), \axaddr_offset_r_reg[2]\ => SI_REG_n_154, \axaddr_offset_r_reg[2]_0\ => SI_REG_n_166, \axaddr_offset_r_reg[2]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2), \axaddr_offset_r_reg[2]_2\ => \WR.aw_channel_0_n_15\, \axaddr_offset_r_reg[2]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2), \axaddr_offset_r_reg[2]_4\ => \RD.ar_channel_0_n_16\, \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \WR.aw_channel_0_n_10\, \axaddr_offset_r_reg[3]_1\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3), \axaddr_offset_r_reg[3]_1\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0), \axaddr_offset_r_reg[3]_2\ => \RD.ar_channel_0_n_11\, \axlen_cnt_reg[3]\ => SI_REG_n_8, \axlen_cnt_reg[3]_0\ => SI_REG_n_64, b_push => b_push, \cnt_read_reg[2]_rep__0\ => SI_REG_n_168, \cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0), \cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0), \cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_0\, \m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_46\, \m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_47\, \m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_48\, \m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_49\, m_valid_i0 => \ar.ar_pipe/m_valid_i0\, m_valid_i_reg(0) => \ar.ar_pipe/p_1_in\, next_pending_r_reg => SI_REG_n_155, next_pending_r_reg_0 => SI_REG_n_167, \out\(11 downto 0) => si_rs_bid(11 downto 0), r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0), r_push_r_reg(0) => si_rs_rlast, \s_arid_r_reg[11]\(54 downto 43) => s_arid(11 downto 0), \s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0), \s_arid_r_reg[11]\(38) => si_rs_arburst(1), \s_arid_r_reg[11]\(37) => SI_REG_n_82, \s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0), \s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0), \s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0), s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => \^s_axi_arready\, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, \s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, \s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0), s_ready_i0 => \ar.ar_pipe/s_ready_i0\, si_rs_arvalid => si_rs_arvalid, si_rs_awvalid => si_rs_awvalid, si_rs_bready => si_rs_bready, si_rs_bvalid => si_rs_bvalid, si_rs_rready => si_rs_rready, \state_reg[0]_rep\ => \WR.aw_channel_0_n_4\, \state_reg[0]_rep_0\ => \RD.ar_channel_0_n_5\, \state_reg[1]\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0), \state_reg[1]_0\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0), \state_reg[1]_rep\ => \WR.aw_channel_0_n_0\, \state_reg[1]_rep_0\ => \WR.aw_channel_0_n_3\, \state_reg[1]_rep_1\ => \RD.ar_channel_0_n_0\, \state_reg[1]_rep_2\ => \RD.ar_channel_0_n_4\, \wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_169, \wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_170, \wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_171, \wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_172, \wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_173, \wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_174, \wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_175, \wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_176, \wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_177, \wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_178, \wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_179, \wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_180, \wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_181, \wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_182, \wrap_cnt_r_reg[2]\ => SI_REG_n_149, \wrap_cnt_r_reg[2]_0\ => SI_REG_n_161, \wrap_cnt_r_reg[3]\ => SI_REG_n_153, \wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_156, \wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_157, \wrap_cnt_r_reg[3]_1\ => SI_REG_n_165, \wrap_second_len_r_reg[1]\ => \WR.aw_channel_0_n_9\, \wrap_second_len_r_reg[1]_0\ => \RD.ar_channel_0_n_10\, \wrap_second_len_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1), \wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0), \wrap_second_len_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0) ); \WR.aw_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel port map ( D(1 downto 0) => wrap_cnt(3 downto 2), E(0) => \aw.aw_pipe/p_1_in\, Q(31 downto 20) => s_awid(11 downto 0), Q(19 downto 16) => si_rs_awlen(3 downto 0), Q(15) => si_rs_awburst(1), Q(14) => SI_REG_n_26, Q(13 downto 12) => si_rs_awsize(1 downto 0), Q(11 downto 0) => si_rs_awaddr(11 downto 0), S(3) => \WR.aw_channel_0_n_47\, S(2) => \WR.aw_channel_0_n_48\, S(1) => \WR.aw_channel_0_n_49\, S(0) => \WR.aw_channel_0_n_50\, aclk => aclk, areset_d1 => areset_d1, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0), \axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2), \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => SI_REG_n_149, \axaddr_offset_r_reg[3]_1\ => SI_REG_n_153, \axlen_cnt_reg[7]\ => \WR.aw_channel_0_n_3\, \axlen_cnt_reg[7]_0\ => \WR.aw_channel_0_n_4\, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\, \cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\, \in\(15 downto 4) => b_awid(11 downto 0), \in\(3 downto 0) => b_awlen(3 downto 0), m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, \m_payload_i_reg[47]\ => SI_REG_n_8, \m_payload_i_reg[47]_0\ => SI_REG_n_155, \m_payload_i_reg[5]\ => SI_REG_n_154, \m_payload_i_reg[6]\(6) => SI_REG_n_169, \m_payload_i_reg[6]\(5) => SI_REG_n_170, \m_payload_i_reg[6]\(4) => SI_REG_n_171, \m_payload_i_reg[6]\(3) => SI_REG_n_172, \m_payload_i_reg[6]\(2) => SI_REG_n_173, \m_payload_i_reg[6]\(1) => SI_REG_n_174, \m_payload_i_reg[6]\(0) => SI_REG_n_175, si_rs_awvalid => si_rs_awvalid, \state_reg[0]_rep\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0), \wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_0\, \wrap_cnt_r_reg[3]\ => \WR.aw_channel_0_n_9\, \wrap_cnt_r_reg[3]_0\ => \WR.aw_channel_0_n_10\, \wrap_cnt_r_reg[3]_1\ => \WR.aw_channel_0_n_15\, \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0), \wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1) ); \WR.b_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel port map ( aclk => aclk, areset_d1 => areset_d1, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\, \cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\, \in\(15 downto 4) => b_awid(11 downto 0), \in\(3 downto 0) => b_awlen(3 downto 0), m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_bvalid => m_axi_bvalid, \out\(11 downto 0) => si_rs_bid(11 downto 0), si_rs_bready => si_rs_bready, si_rs_bvalid => si_rs_bvalid, \skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0) ); areset_d1_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aresetn, O => areset_d1_i_1_n_0 ); areset_d1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => areset_d1_i_1_n_0, Q => areset_d1, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_FAMILY : string; attribute C_FAMILY of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute P_AXI4 : integer; attribute P_AXI4 of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute P_AXILITE : integer; attribute P_AXILITE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute P_DECERR : string; attribute P_DECERR of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b11"; attribute P_INCR : string; attribute P_INCR of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute P_SLVERR : string; attribute P_SLVERR of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b10"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal \^m_axi_wready\ : STD_LOGIC; signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_wvalid\ : STD_LOGIC; begin \^m_axi_wready\ <= m_axi_wready; \^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0); \^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0); \^s_axi_wvalid\ <= s_axi_wvalid; m_axi_arburst(1) <= \<const0>\; m_axi_arburst(0) <= \<const1>\; m_axi_arcache(3) <= \<const0>\; m_axi_arcache(2) <= \<const0>\; m_axi_arcache(1) <= \<const0>\; m_axi_arcache(0) <= \<const0>\; m_axi_arid(11) <= \<const0>\; m_axi_arid(10) <= \<const0>\; m_axi_arid(9) <= \<const0>\; m_axi_arid(8) <= \<const0>\; m_axi_arid(7) <= \<const0>\; m_axi_arid(6) <= \<const0>\; m_axi_arid(5) <= \<const0>\; m_axi_arid(4) <= \<const0>\; m_axi_arid(3) <= \<const0>\; m_axi_arid(2) <= \<const0>\; m_axi_arid(1) <= \<const0>\; m_axi_arid(0) <= \<const0>\; m_axi_arlen(7) <= \<const0>\; m_axi_arlen(6) <= \<const0>\; m_axi_arlen(5) <= \<const0>\; m_axi_arlen(4) <= \<const0>\; m_axi_arlen(3) <= \<const0>\; m_axi_arlen(2) <= \<const0>\; m_axi_arlen(1) <= \<const0>\; m_axi_arlen(0) <= \<const0>\; m_axi_arlock(0) <= \<const0>\; m_axi_arqos(3) <= \<const0>\; m_axi_arqos(2) <= \<const0>\; m_axi_arqos(1) <= \<const0>\; m_axi_arqos(0) <= \<const0>\; m_axi_arregion(3) <= \<const0>\; m_axi_arregion(2) <= \<const0>\; m_axi_arregion(1) <= \<const0>\; m_axi_arregion(0) <= \<const0>\; m_axi_arsize(2) <= \<const0>\; m_axi_arsize(1) <= \<const1>\; m_axi_arsize(0) <= \<const0>\; m_axi_aruser(0) <= \<const0>\; m_axi_awburst(1) <= \<const0>\; m_axi_awburst(0) <= \<const1>\; m_axi_awcache(3) <= \<const0>\; m_axi_awcache(2) <= \<const0>\; m_axi_awcache(1) <= \<const0>\; m_axi_awcache(0) <= \<const0>\; m_axi_awid(11) <= \<const0>\; m_axi_awid(10) <= \<const0>\; m_axi_awid(9) <= \<const0>\; m_axi_awid(8) <= \<const0>\; m_axi_awid(7) <= \<const0>\; m_axi_awid(6) <= \<const0>\; m_axi_awid(5) <= \<const0>\; m_axi_awid(4) <= \<const0>\; m_axi_awid(3) <= \<const0>\; m_axi_awid(2) <= \<const0>\; m_axi_awid(1) <= \<const0>\; m_axi_awid(0) <= \<const0>\; m_axi_awlen(7) <= \<const0>\; m_axi_awlen(6) <= \<const0>\; m_axi_awlen(5) <= \<const0>\; m_axi_awlen(4) <= \<const0>\; m_axi_awlen(3) <= \<const0>\; m_axi_awlen(2) <= \<const0>\; m_axi_awlen(1) <= \<const0>\; m_axi_awlen(0) <= \<const0>\; m_axi_awlock(0) <= \<const0>\; m_axi_awqos(3) <= \<const0>\; m_axi_awqos(2) <= \<const0>\; m_axi_awqos(1) <= \<const0>\; m_axi_awqos(0) <= \<const0>\; m_axi_awregion(3) <= \<const0>\; m_axi_awregion(2) <= \<const0>\; m_axi_awregion(1) <= \<const0>\; m_axi_awregion(0) <= \<const0>\; m_axi_awsize(2) <= \<const0>\; m_axi_awsize(1) <= \<const1>\; m_axi_awsize(0) <= \<const0>\; m_axi_awuser(0) <= \<const0>\; m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0); m_axi_wid(11) <= \<const0>\; m_axi_wid(10) <= \<const0>\; m_axi_wid(9) <= \<const0>\; m_axi_wid(8) <= \<const0>\; m_axi_wid(7) <= \<const0>\; m_axi_wid(6) <= \<const0>\; m_axi_wid(5) <= \<const0>\; m_axi_wid(4) <= \<const0>\; m_axi_wid(3) <= \<const0>\; m_axi_wid(2) <= \<const0>\; m_axi_wid(1) <= \<const0>\; m_axi_wid(0) <= \<const0>\; m_axi_wlast <= \<const1>\; m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0); m_axi_wuser(0) <= \<const0>\; m_axi_wvalid <= \^s_axi_wvalid\; s_axi_buser(0) <= \<const0>\; s_axi_ruser(0) <= \<const0>\; s_axi_wready <= \^m_axi_wready\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s port map ( Q(22 downto 20) => m_axi_awprot(2 downto 0), Q(19 downto 0) => m_axi_awaddr(31 downto 12), aclk => aclk, aresetn => aresetn, \in\(33 downto 32) => m_axi_rresp(1 downto 0), \in\(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), \m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0), \m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12), m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_bvalid => m_axi_bvalid, m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, \s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0), \s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0), \s_axi_rid[11]\(34) => s_axi_rlast, \s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0), \s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of design_1_auto_pc_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of design_1_auto_pc_0 : entity is "design_1_auto_pc_0,axi_protocol_converter_v2_1_17_axi_protocol_converter,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of design_1_auto_pc_0 : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of design_1_auto_pc_0 : entity is "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2"; end design_1_auto_pc_0; architecture STRUCTURE of design_1_auto_pc_0 is signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC; signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of inst : label is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of inst : label is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of inst : label is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of inst : label is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of inst : label is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of inst : label is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of inst : label is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of inst : label is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of inst : label is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of inst : label is 1; attribute C_FAMILY : string; attribute C_FAMILY of inst : label is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of inst : label is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of inst : label is 2; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of inst : label is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of inst : label is 2; attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of inst : label is 1; attribute P_AXI4 : integer; attribute P_AXI4 of inst : label is 0; attribute P_AXILITE : integer; attribute P_AXILITE of inst : label is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of inst : label is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of inst : label is 2; attribute P_DECERR : string; attribute P_DECERR of inst : label is "2'b11"; attribute P_INCR : string; attribute P_INCR of inst : label is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of inst : label is 1; attribute P_SLVERR : string; attribute P_SLVERR of inst : label is "2'b10"; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN"; attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST RST"; attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY"; attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID"; attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY"; attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID"; attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY"; attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID"; attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY"; attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID"; attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY"; attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID"; attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST"; attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST"; attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR"; attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT"; attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR"; attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT"; attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP"; attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA"; attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP"; attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA"; attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB"; attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST"; attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"; attribute X_INTERFACE_INFO of s_axi_arid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARID"; attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN"; attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"; attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT"; attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARQOS"; attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"; attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST"; attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"; attribute X_INTERFACE_INFO of s_axi_awid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWID"; attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN"; attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"; attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT"; attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWQOS"; attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"; attribute X_INTERFACE_INFO of s_axi_bid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BID"; attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; attribute X_INTERFACE_INFO of s_axi_rid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RID"; attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; attribute X_INTERFACE_INFO of s_axi_wid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WID"; attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; begin inst: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter port map ( aclk => aclk, aresetn => aresetn, m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0), m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0), m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0), m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0), m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0), m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0), m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0), m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0), m_axi_arready => m_axi_arready, m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0), m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0), m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0), m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0), m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0), m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0), m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0), m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0), m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0), m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0), m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0), m_axi_awready => m_axi_awready, m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0), m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0), m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0), m_axi_awvalid => m_axi_awvalid, m_axi_bid(11 downto 0) => B"000000000000", m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_buser(0) => '0', m_axi_bvalid => m_axi_bvalid, m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_rid(11 downto 0) => B"000000000000", m_axi_rlast => '1', m_axi_rready => m_axi_rready, m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), m_axi_ruser(0) => '0', m_axi_rvalid => m_axi_rvalid, m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0), m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0), m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED, m_axi_wready => m_axi_wready, m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0), m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0), m_axi_wvalid => m_axi_wvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0), s_axi_arready => s_axi_arready, s_axi_arregion(3 downto 0) => B"0000", s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0), s_axi_aruser(0) => '0', s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0), s_axi_awready => s_axi_awready, s_axi_awregion(3 downto 0) => B"0000", s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0), s_axi_awuser(0) => '0', s_axi_awvalid => s_axi_awvalid, s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0), s_axi_bready => s_axi_bready, s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0), s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0), s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wuser(0) => '0', s_axi_wvalid => s_axi_wvalid ); end STRUCTURE;
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Mon Sep 16 04:58:12 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top design_1_auto_pc_0 -prefix -- design_1_auto_pc_0_ design_1_auto_pc_0_sim_netlist.vhdl -- Design : design_1_auto_pc_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd is port ( next_pending_r_reg_0 : out STD_LOGIC; \axaddr_incr_reg[0]_0\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[2]_0\ : out STD_LOGIC; \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); \m_axi_awaddr[11]\ : out STD_LOGIC; \m_axi_awaddr[5]\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 3 downto 0 ); incr_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; sel_first_reg_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \next\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[0]_rep\ : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd is signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \axaddr_incr[0]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[10]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr[1]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[2]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[4]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[5]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[6]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[7]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[8]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[9]_i_1_n_0\ : STD_LOGIC; signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC; signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 ); signal \axaddr_incr_reg[11]_i_4_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_7\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_2_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[5]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[6]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_2_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \^axlen_cnt_reg[2]_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC; signal next_pending_r_i_5_n_0 : STD_LOGIC; signal \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \m_axi_awaddr[11]_INST_0_i_1\ : label is "soft_lutpair113"; attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_1\ : label is "soft_lutpair113"; begin Q(0) <= \^q\(0); \axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\; \axaddr_incr_reg[11]_0\(10 downto 0) <= \^axaddr_incr_reg[11]_0\(10 downto 0); \axlen_cnt_reg[2]_0\ <= \^axlen_cnt_reg[2]_0\; \axaddr_incr[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_7\, O => \axaddr_incr[0]_i_1_n_0\ ); \axaddr_incr[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(10), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_5\, O => \axaddr_incr[10]_i_1_n_0\ ); \axaddr_incr[11]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \next\, O => \axaddr_incr[11]_i_1_n_0\ ); \axaddr_incr[11]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(11), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_4\, O => \axaddr_incr[11]_i_2_n_0\ ); \axaddr_incr[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_6\, O => \axaddr_incr[1]_i_1_n_0\ ); \axaddr_incr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_5\, O => \axaddr_incr[2]_i_1_n_0\ ); \axaddr_incr[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_4\, O => \axaddr_incr[3]_i_1_n_0\ ); \axaddr_incr[3]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"0102" ) port map ( I0 => \m_payload_i_reg[46]\(0), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(0) ); \axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(3), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_11_n_0\ ); \axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(2), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_12_n_0\ ); \axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(1), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), O => \axaddr_incr[3]_i_13_n_0\ ); \axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(0), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \m_payload_i_reg[46]\(3), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(3) ); \axaddr_incr[3]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"262A" ) port map ( I0 => \m_payload_i_reg[46]\(2), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(2) ); \axaddr_incr[3]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"060A" ) port map ( I0 => \m_payload_i_reg[46]\(1), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), I3 => \next\, O => S(1) ); \axaddr_incr[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(4), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_7\, O => \axaddr_incr[4]_i_1_n_0\ ); \axaddr_incr[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(5), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_6\, O => \axaddr_incr[5]_i_1_n_0\ ); \axaddr_incr[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(6), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_5\, O => \axaddr_incr[6]_i_1_n_0\ ); \axaddr_incr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(7), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_4\, O => \axaddr_incr[7]_i_1_n_0\ ); \axaddr_incr[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(8), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_7\, O => \axaddr_incr[8]_i_1_n_0\ ); \axaddr_incr[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(9), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_6\, O => \axaddr_incr[9]_i_1_n_0\ ); \axaddr_incr_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[0]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(0), R => '0' ); \axaddr_incr_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[10]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(9), R => '0' ); \axaddr_incr_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[11]_i_2_n_0\, Q => \^axaddr_incr_reg[11]_0\(10), R => '0' ); \axaddr_incr_reg[11]_i_4\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_3_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_4_n_1\, CO(1) => \axaddr_incr_reg[11]_i_4_n_2\, CO(0) => \axaddr_incr_reg[11]_i_4_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[11]_i_4_n_4\, O(2) => \axaddr_incr_reg[11]_i_4_n_5\, O(1) => \axaddr_incr_reg[11]_i_4_n_6\, O(0) => \axaddr_incr_reg[11]_i_4_n_7\, S(3 downto 0) => \^axaddr_incr_reg[11]_0\(10 downto 7) ); \axaddr_incr_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[1]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(1), R => '0' ); \axaddr_incr_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[2]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(2), R => '0' ); \axaddr_incr_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[3]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(3), R => '0' ); \axaddr_incr_reg[3]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_3_n_0\, CO(2) => \axaddr_incr_reg[3]_i_3_n_1\, CO(1) => \axaddr_incr_reg[3]_i_3_n_2\, CO(0) => \axaddr_incr_reg[3]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => \^axaddr_incr_reg[11]_0\(3 downto 0), O(3) => \axaddr_incr_reg[3]_i_3_n_4\, O(2) => \axaddr_incr_reg[3]_i_3_n_5\, O(1) => \axaddr_incr_reg[3]_i_3_n_6\, O(0) => \axaddr_incr_reg[3]_i_3_n_7\, S(3) => \axaddr_incr[3]_i_11_n_0\, S(2) => \axaddr_incr[3]_i_12_n_0\, S(1) => \axaddr_incr[3]_i_13_n_0\, S(0) => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[4]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(4), R => '0' ); \axaddr_incr_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[5]_i_1_n_0\, Q => \axaddr_incr_reg_n_0_[5]\, R => '0' ); \axaddr_incr_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[6]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(5), R => '0' ); \axaddr_incr_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[7]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(6), R => '0' ); \axaddr_incr_reg[7]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_3_n_0\, CO(3) => \axaddr_incr_reg[7]_i_3_n_0\, CO(2) => \axaddr_incr_reg[7]_i_3_n_1\, CO(1) => \axaddr_incr_reg[7]_i_3_n_2\, CO(0) => \axaddr_incr_reg[7]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[7]_i_3_n_4\, O(2) => \axaddr_incr_reg[7]_i_3_n_5\, O(1) => \axaddr_incr_reg[7]_i_3_n_6\, O(0) => \axaddr_incr_reg[7]_i_3_n_7\, S(3 downto 2) => \^axaddr_incr_reg[11]_0\(6 downto 5), S(1) => \axaddr_incr_reg_n_0_[5]\, S(0) => \^axaddr_incr_reg[11]_0\(4) ); \axaddr_incr_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[8]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(7), R => '0' ); \axaddr_incr_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[9]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(8), R => '0' ); \axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => \m_payload_i_reg[46]\(8), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^q\(0), I4 => \^axlen_cnt_reg[2]_0\, O => \axlen_cnt[1]_i_1__0_n_0\ ); \axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA900A900A900" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \^q\(0), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^axlen_cnt_reg[2]_0\, I4 => E(0), I5 => \m_payload_i_reg[46]\(9), O => \axlen_cnt[2]_i_1_n_0\ ); \axlen_cnt[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEEBAAAAAAAA" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^q\(0), I5 => \^axlen_cnt_reg[2]_0\, O => \axlen_cnt[3]_i_2_n_0\ ); \axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^q\(0), O => \axlen_cnt[4]_i_1_n_0\ ); \axlen_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[5]\, I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \^q\(0), I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[3]\, O => \axlen_cnt[5]_i_1_n_0\ ); \axlen_cnt[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axlen_cnt_reg_n_0_[6]\, I1 => \axlen_cnt_reg_n_0_[5]\, I2 => \axlen_cnt[7]_i_3_n_0\, O => \axlen_cnt[6]_i_1_n_0\ ); \axlen_cnt[7]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"A9AA" ) port map ( I0 => \axlen_cnt_reg_n_0_[7]\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt[7]_i_3_n_0\, O => \axlen_cnt[7]_i_2_n_0\ ); \axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \axlen_cnt_reg_n_0_[3]\, I1 => \axlen_cnt_reg_n_0_[2]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^q\(0), I4 => \axlen_cnt_reg_n_0_[4]\, O => \axlen_cnt[7]_i_3_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \state_reg[1]\(0), Q => \^q\(0), R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[1]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[2]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[3]_i_2_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[4]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[5]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[5]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[6]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[6]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[7]_i_2_n_0\, Q => \axlen_cnt_reg_n_0_[7]\, R => \state_reg[0]_rep\ ); \m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \m_payload_i_reg[46]\(7), O => \m_axi_awaddr[11]\ ); \m_axi_awaddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[5]\, I2 => \m_payload_i_reg[46]\(7), I3 => \m_payload_i_reg[46]\(4), O => \m_axi_awaddr[5]\ ); \next_pending_r_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"55545555" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[7]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[6]\, I4 => next_pending_r_i_5_n_0, O => \^axlen_cnt_reg[2]_0\ ); next_pending_r_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \axlen_cnt_reg_n_0_[1]\, I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[3]\, O => next_pending_r_i_5_n_0 ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => incr_next_pending, Q => next_pending_r_reg_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_0, Q => \^axaddr_incr_reg[0]_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is port ( incr_next_pending : out STD_LOGIC; \axaddr_incr_reg[0]_0\ : out STD_LOGIC; \axlen_cnt_reg[0]_0\ : out STD_LOGIC; \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \m_axi_araddr[11]\ : out STD_LOGIC; \m_axi_araddr[5]\ : out STD_LOGIC; \m_axi_araddr[3]\ : out STD_LOGIC; \m_axi_araddr[2]\ : out STD_LOGIC; \m_axi_araddr[1]\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 10 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; \m_payload_i_reg[47]_0\ : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); si_rs_arvalid : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]\ : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arready : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_17_b2s_incr_cmd"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is signal \axaddr_incr[0]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[10]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr[1]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[2]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[4]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[5]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[6]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[7]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[8]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[9]_i_1__0_n_0\ : STD_LOGIC; signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC; signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \axaddr_incr_reg[11]_i_4__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[1]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[2]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[3]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_2__0_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC; signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC; signal \^incr_next_pending\ : STD_LOGIC; signal \next_pending_r_i_2__0_n_0\ : STD_LOGIC; signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1__0\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1__0\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1__0\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1__0\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_4\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1__0\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1__0\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2__0\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3__0\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \m_axi_araddr[11]_INST_0_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \next_pending_r_i_2__0\ : label is "soft_lutpair7"; begin \axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\; \axaddr_incr_reg[11]_0\(7 downto 0) <= \^axaddr_incr_reg[11]_0\(7 downto 0); \axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\; incr_next_pending <= \^incr_next_pending\; \axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_7\, O => \axaddr_incr[0]_i_1__0_n_0\ ); \axaddr_incr[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_5\, O => \axaddr_incr[10]_i_1__0_n_0\ ); \axaddr_incr[11]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_4\, O => \axaddr_incr[11]_i_2__0_n_0\ ); \axaddr_incr[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_6\, O => \axaddr_incr[1]_i_1__0_n_0\ ); \axaddr_incr[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_5\, O => \axaddr_incr[2]_i_1__0_n_0\ ); \axaddr_incr[3]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"0201020202020202" ) port map ( I0 => Q(0), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(0) ); \axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \axaddr_incr_reg_n_0_[3]\, I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_11_n_0\ ); \axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_incr_reg_n_0_[2]\, I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_12_n_0\ ); \axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_incr_reg_n_0_[1]\, I1 => Q(6), I2 => Q(5), O => \axaddr_incr[3]_i_13_n_0\ ); \axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(0), I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_4\, O => \axaddr_incr[3]_i_1__0_n_0\ ); \axaddr_incr[3]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"AA6AAAAAAAAAAAAA" ) port map ( I0 => Q(3), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(3) ); \axaddr_incr[3]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"2A262A2A2A2A2A2A" ) port map ( I0 => Q(2), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(2) ); \axaddr_incr[3]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"0A060A0A0A0A0A0A" ) port map ( I0 => Q(1), I1 => Q(5), I2 => Q(6), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(1) ); \axaddr_incr[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_7\, O => \axaddr_incr[4]_i_1__0_n_0\ ); \axaddr_incr[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_6\, O => \axaddr_incr[5]_i_1__0_n_0\ ); \axaddr_incr[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_5\, O => \axaddr_incr[6]_i_1__0_n_0\ ); \axaddr_incr[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_4\, O => \axaddr_incr[7]_i_1__0_n_0\ ); \axaddr_incr[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_7\, O => \axaddr_incr[8]_i_1__0_n_0\ ); \axaddr_incr[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_6\, O => \axaddr_incr[9]_i_1__0_n_0\ ); \axaddr_incr_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[0]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(0), R => '0' ); \axaddr_incr_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[10]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(6), R => '0' ); \axaddr_incr_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[11]_i_2__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(7), R => '0' ); \axaddr_incr_reg[11]_i_4__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_3__0_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_4__0_n_1\, CO(1) => \axaddr_incr_reg[11]_i_4__0_n_2\, CO(0) => \axaddr_incr_reg[11]_i_4__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[11]_i_4__0_n_4\, O(2) => \axaddr_incr_reg[11]_i_4__0_n_5\, O(1) => \axaddr_incr_reg[11]_i_4__0_n_6\, O(0) => \axaddr_incr_reg[11]_i_4__0_n_7\, S(3 downto 0) => \^axaddr_incr_reg[11]_0\(7 downto 4) ); \axaddr_incr_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[1]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[1]\, R => '0' ); \axaddr_incr_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[2]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[2]\, R => '0' ); \axaddr_incr_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[3]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[3]\, R => '0' ); \axaddr_incr_reg[3]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_3__0_n_0\, CO(2) => \axaddr_incr_reg[3]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[3]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[3]_i_3__0_n_3\, CYINIT => '0', DI(3) => \axaddr_incr_reg_n_0_[3]\, DI(2) => \axaddr_incr_reg_n_0_[2]\, DI(1) => \axaddr_incr_reg_n_0_[1]\, DI(0) => \^axaddr_incr_reg[11]_0\(0), O(3) => \axaddr_incr_reg[3]_i_3__0_n_4\, O(2) => \axaddr_incr_reg[3]_i_3__0_n_5\, O(1) => \axaddr_incr_reg[3]_i_3__0_n_6\, O(0) => \axaddr_incr_reg[3]_i_3__0_n_7\, S(3) => \axaddr_incr[3]_i_11_n_0\, S(2) => \axaddr_incr[3]_i_12_n_0\, S(1) => \axaddr_incr[3]_i_13_n_0\, S(0) => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[4]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(1), R => '0' ); \axaddr_incr_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[5]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[5]\, R => '0' ); \axaddr_incr_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[6]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(2), R => '0' ); \axaddr_incr_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[7]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(3), R => '0' ); \axaddr_incr_reg[7]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_3__0_n_0\, CO(3) => \axaddr_incr_reg[7]_i_3__0_n_0\, CO(2) => \axaddr_incr_reg[7]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[7]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[7]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[7]_i_3__0_n_4\, O(2) => \axaddr_incr_reg[7]_i_3__0_n_5\, O(1) => \axaddr_incr_reg[7]_i_3__0_n_6\, O(0) => \axaddr_incr_reg[7]_i_3__0_n_7\, S(3 downto 2) => \^axaddr_incr_reg[11]_0\(3 downto 2), S(1) => \axaddr_incr_reg_n_0_[5]\, S(0) => \^axaddr_incr_reg[11]_0\(1) ); \axaddr_incr_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[8]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(4), R => '0' ); \axaddr_incr_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[9]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(5), R => '0' ); \axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"20FF2020" ) port map ( I0 => si_rs_arvalid, I1 => \state_reg[0]_rep\, I2 => Q(8), I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[0]_i_1__2_n_0\ ); \axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => Q(9), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[1]_i_1__1_n_0\ ); \axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA900A900A900" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^axlen_cnt_reg[0]_0\, I4 => E(0), I5 => Q(10), O => \axlen_cnt[2]_i_1__1_n_0\ ); \axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEEBAAAAAAAA" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[3]_i_2__0_n_0\ ); \axlen_cnt[3]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"55545555" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[7]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[6]\, I4 => \next_pending_r_i_4__0_n_0\, O => \^axlen_cnt_reg[0]_0\ ); \axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[4]_i_1__0_n_0\ ); \axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[5]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \axlen_cnt_reg_n_0_[4]\, O => \axlen_cnt[5]_i_1__0_n_0\ ); \axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axlen_cnt_reg_n_0_[6]\, I1 => \axlen_cnt_reg_n_0_[5]\, I2 => \axlen_cnt[7]_i_3__0_n_0\, O => \axlen_cnt[6]_i_1__0_n_0\ ); \axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A9AA" ) port map ( I0 => \axlen_cnt_reg_n_0_[7]\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt[7]_i_3__0_n_0\, O => \axlen_cnt[7]_i_2__0_n_0\ ); \axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[3]\, I3 => \axlen_cnt_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[0]\, O => \axlen_cnt[7]_i_3__0_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[0]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[1]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[2]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[3]_i_2__0_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[4]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => \state_reg[1]\ ); \axlen_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[5]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[5]\, R => \state_reg[1]\ ); \axlen_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[6]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[6]\, R => \state_reg[1]\ ); \axlen_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[7]_i_2__0_n_0\, Q => \axlen_cnt_reg_n_0_[7]\, R => \state_reg[1]\ ); \m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => Q(7), O => \m_axi_araddr[11]\ ); \m_axi_araddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[1]\, I2 => Q(7), I3 => Q(1), O => \m_axi_araddr[1]\ ); \m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[2]\, I2 => Q(7), I3 => Q(2), O => \m_axi_araddr[2]\ ); \m_axi_araddr[3]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[3]\, I2 => Q(7), I3 => Q(3), O => \m_axi_araddr[3]\ ); \m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[5]\, I2 => Q(7), I3 => Q(4), O => \m_axi_araddr[5]\ ); \next_pending_r_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF505C" ) port map ( I0 => \next_pending_r_i_2__0_n_0\, I1 => next_pending_r_reg_n_0, I2 => \state_reg[1]_rep\, I3 => E(0), I4 => \m_payload_i_reg[47]_0\, O => \^incr_next_pending\ ); \next_pending_r_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \next_pending_r_i_4__0_n_0\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[7]\, O => \next_pending_r_i_2__0_n_0\ ); \next_pending_r_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[4]\, O => \next_pending_r_i_4__0_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \^incr_next_pending\, Q => next_pending_r_reg_n_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_0, Q => \^axaddr_incr_reg[0]_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is port ( \axlen_cnt_reg[7]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC; \m_payload_i_reg[0]_0\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; sel_first_i : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_incr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_valid_i0 : out STD_LOGIC; s_ready_i0 : out STD_LOGIC; \m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC; si_rs_arvalid : in STD_LOGIC; \axlen_cnt_reg[7]_0\ : in STD_LOGIC; s_axburst_eq1_reg : in STD_LOGIC; \cnt_read_reg[2]_rep__0\ : in STD_LOGIC; \wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg_1 : in STD_LOGIC; areset_d1 : in STD_LOGIC; sel_first : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[5]\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; aclk : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_payload_i_reg[0]\ : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal \next_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_1__0\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__2\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \s_ready_i_i_1__0\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair2"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \state_reg[0]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute KEEP : string; attribute KEEP of \state_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]"; attribute FSM_ENCODED_STATES of \state_reg[0]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1; attribute KEEP of \state_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]"; attribute FSM_ENCODED_STATES of \state_reg[1]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute KEEP of \state_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]"; attribute FSM_ENCODED_STATES of \state_reg[1]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1; attribute KEEP of \state_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4__0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6__0\ : label is "soft_lutpair4"; begin Q(1 downto 0) <= \^q\(1 downto 0); \m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\; \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; \axaddr_incr[11]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AAEA" ) port map ( I0 => sel_first, I1 => m_axi_arready, I2 => \^m_payload_i_reg[0]_0\, I3 => \^m_payload_i_reg[0]\, O => \axaddr_incr_reg[0]\(0) ); \axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAACAAAAAAA0AA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \m_payload_i_reg[46]\(0), I2 => \^m_payload_i_reg[0]_0\, I3 => si_rs_arvalid, I4 => \^m_payload_i_reg[0]\, I5 => \m_payload_i_reg[5]\, O => \axaddr_offset_r_reg[2]\(0) ); \axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"00CA" ) port map ( I0 => si_rs_arvalid, I1 => m_axi_arready, I2 => \^q\(0), I3 => \^q\(1), O => E(0) ); \axlen_cnt[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00005140" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => m_axi_arready, I3 => si_rs_arvalid, I4 => \axlen_cnt_reg[7]_0\, O => \axlen_cnt_reg[7]\ ); m_axi_arvalid_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, O => m_axi_arvalid ); \m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"D5" ) port map ( I0 => si_rs_arvalid, I1 => \^m_payload_i_reg[0]\, I2 => \^m_payload_i_reg[0]_0\, O => \m_payload_i_reg[0]_1\(0) ); \m_valid_i_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"FF70FFFF" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, I2 => si_rs_arvalid, I3 => s_axi_arvalid, I4 => s_ready_i_reg, O => m_valid_i0 ); r_push_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^m_payload_i_reg[0]\, I1 => \^m_payload_i_reg[0]_0\, I2 => m_axi_arready, O => r_push_r_reg ); \s_ready_i_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"8FFF8F8F" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, I2 => si_rs_arvalid, I3 => s_axi_arvalid, I4 => s_ready_i_reg, O => s_ready_i0 ); \sel_first_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFC4C4CFCC" ) port map ( I0 => m_axi_arready, I1 => sel_first_reg_1, I2 => \^q\(1), I3 => si_rs_arvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg ); \sel_first_i_1__3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFC4C4CFCC" ) port map ( I0 => m_axi_arready, I1 => sel_first, I2 => \^m_payload_i_reg[0]\, I3 => si_rs_arvalid, I4 => \^m_payload_i_reg[0]_0\, I5 => areset_d1, O => sel_first_reg_0 ); \sel_first_i_1__4\: unisim.vcomponents.LUT6 generic map( INIT => X"FCFFFFFFCCCECCCE" ) port map ( I0 => si_rs_arvalid, I1 => areset_d1, I2 => \^m_payload_i_reg[0]\, I3 => \^m_payload_i_reg[0]_0\, I4 => m_axi_arready, I5 => sel_first_reg_2, O => sel_first_i ); \state[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"003030303E3E3E3E" ) port map ( I0 => si_rs_arvalid, I1 => \^q\(1), I2 => \^q\(0), I3 => m_axi_arready, I4 => s_axburst_eq1_reg, I5 => \cnt_read_reg[2]_rep__0\, O => \next_state__0\(0) ); \state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00AAB000" ) port map ( I0 => \cnt_read_reg[2]_rep__0\, I1 => s_axburst_eq1_reg, I2 => m_axi_arready, I3 => \^m_payload_i_reg[0]_0\, I4 => \^m_payload_i_reg[0]\, O => \next_state__0\(1) ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(0), Q => \^q\(0), R => areset_d1 ); \state_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(0), Q => \^m_payload_i_reg[0]_0\, R => areset_d1 ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(1), Q => \^q\(1), R => areset_d1 ); \state_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(1), Q => \^m_payload_i_reg[0]\, R => areset_d1 ); \wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \^m_payload_i_reg[0]\, I1 => si_rs_arvalid, I2 => \^m_payload_i_reg[0]_0\, O => \wrap_boundary_axaddr_r_reg[11]\(0) ); \wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8A5575AA8A5545" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_arvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => D(0) ); \wrap_cnt_r[3]_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(1), I1 => \^m_payload_i_reg[0]_0\, I2 => si_rs_arvalid, I3 => \^m_payload_i_reg[0]\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_6__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \^m_payload_i_reg[0]_0\, I2 => si_rs_arvalid, I3 => \^m_payload_i_reg[0]\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8AAA8AAA8AAABA" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_arvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => \wrap_second_len_r_reg[0]\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo is port ( \cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC; \cnt_read_reg[1]_rep__0_0\ : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); D : out STD_LOGIC_VECTOR ( 0 to 0 ); bresp_push : out STD_LOGIC; bvalid_i_reg : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); b_push : in STD_LOGIC; shandshake_r : in STD_LOGIC; areset_d1 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); mhandshake_r : in STD_LOGIC; si_rs_bready : in STD_LOGIC; bvalid_i_reg_0 : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); aclk : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo is signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \bresp_cnt[7]_i_4_n_0\ : STD_LOGIC; signal \bresp_cnt[7]_i_5_n_0\ : STD_LOGIC; signal \^bresp_push\ : STD_LOGIC; signal bvalid_i_i_2_n_0 : STD_LOGIC; signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC; signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \^cnt_read_reg[1]_rep__0_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair121"; attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair121"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name : string; attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 "; attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 "; attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 "; attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 "; attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 "; attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 "; attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 "; attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 "; attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 "; attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 "; attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 "; attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 "; attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 "; attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 "; attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 "; attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 "; begin bresp_push <= \^bresp_push\; \cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\; \cnt_read_reg[1]_rep__0_0\ <= \^cnt_read_reg[1]_rep__0_0\; \bresp_cnt[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"ABAA" ) port map ( I0 => areset_d1, I1 => \bresp_cnt[7]_i_3_n_0\, I2 => \bresp_cnt[7]_i_4_n_0\, I3 => \bresp_cnt[7]_i_5_n_0\, O => SR(0) ); \bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"EEFEFFFFFFFFEEFE" ) port map ( I0 => \bresp_cnt_reg[7]\(7), I1 => \bresp_cnt_reg[7]\(6), I2 => \bresp_cnt_reg[7]\(0), I3 => \memory_reg[3][0]_srl4_n_0\, I4 => \bresp_cnt_reg[7]\(3), I5 => \memory_reg[3][3]_srl4_n_0\, O => \bresp_cnt[7]_i_3_n_0\ ); \bresp_cnt[7]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"FFF6FFFF" ) port map ( I0 => \bresp_cnt_reg[7]\(1), I1 => \memory_reg[3][1]_srl4_n_0\, I2 => \bresp_cnt_reg[7]\(4), I3 => \bresp_cnt_reg[7]\(5), I4 => mhandshake_r, O => \bresp_cnt[7]_i_4_n_0\ ); \bresp_cnt[7]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"0000D00DD00DD00D" ) port map ( I0 => \memory_reg[3][0]_srl4_n_0\, I1 => \bresp_cnt_reg[7]\(0), I2 => \bresp_cnt_reg[7]\(2), I3 => \memory_reg[3][2]_srl4_n_0\, I4 => \^cnt_read_reg[1]_rep__0_0\, I5 => \^cnt_read_reg[0]_rep__0_0\, O => \bresp_cnt[7]_i_5_n_0\ ); bvalid_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0444" ) port map ( I0 => areset_d1, I1 => bvalid_i_i_2_n_0, I2 => si_rs_bready, I3 => bvalid_i_reg_0, O => bvalid_i_reg ); bvalid_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00070707" ) port map ( I0 => \^cnt_read_reg[1]_rep__0_0\, I1 => \^cnt_read_reg[0]_rep__0_0\, I2 => shandshake_r, I3 => Q(1), I4 => Q(0), I5 => bvalid_i_reg_0, O => bvalid_i_i_2_n_0 ); \cnt_read[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^bresp_push\, I1 => shandshake_r, I2 => Q(0), O => D(0) ); \cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => b_push, I2 => shandshake_r, O => \cnt_read[0]_i_1__2_n_0\ ); \cnt_read[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"E718" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => b_push, I2 => shandshake_r, I3 => \^cnt_read_reg[1]_rep__0_0\, O => \cnt_read[1]_i_1_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => \^cnt_read_reg[0]_rep__0_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => \^cnt_read_reg[1]_rep__0_0\, S => areset_d1 ); \memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(0), Q => \memory_reg[3][0]_srl4_n_0\ ); \memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000041004141" ) port map ( I0 => \memory_reg[3][0]_srl4_i_2__0_n_0\, I1 => \memory_reg[3][2]_srl4_n_0\, I2 => \bresp_cnt_reg[7]\(2), I3 => \bresp_cnt_reg[7]\(0), I4 => \memory_reg[3][0]_srl4_n_0\, I5 => \memory_reg[3][0]_srl4_i_3_n_0\, O => \^bresp_push\ ); \memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^cnt_read_reg[1]_rep__0_0\, I1 => \^cnt_read_reg[0]_rep__0_0\, O => \memory_reg[3][0]_srl4_i_2__0_n_0\ ); \memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFBFFFFFFFFFFFB" ) port map ( I0 => \bresp_cnt[7]_i_3_n_0\, I1 => mhandshake_r, I2 => \bresp_cnt_reg[7]\(5), I3 => \bresp_cnt_reg[7]\(4), I4 => \memory_reg[3][1]_srl4_n_0\, I5 => \bresp_cnt_reg[7]\(1), O => \memory_reg[3][0]_srl4_i_3_n_0\ ); \memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(6), Q => \out\(2) ); \memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(7), Q => \out\(3) ); \memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(8), Q => \out\(4) ); \memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(9), Q => \out\(5) ); \memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(10), Q => \out\(6) ); \memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(11), Q => \out\(7) ); \memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(12), Q => \out\(8) ); \memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(13), Q => \out\(9) ); \memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(14), Q => \out\(10) ); \memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(15), Q => \out\(11) ); \memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(1), Q => \memory_reg[3][1]_srl4_n_0\ ); \memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(2), Q => \memory_reg[3][2]_srl4_n_0\ ); \memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(3), Q => \memory_reg[3][3]_srl4_n_0\ ); \memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(4), Q => \out\(0) ); \memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(5), Q => \out\(1) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is port ( Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); mhandshake : out STD_LOGIC; m_axi_bready : out STD_LOGIC; \skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); shandshake_r : in STD_LOGIC; sel : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; mhandshake_r : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\; architecture STRUCTURE of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair122"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair122"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; attribute srl_name : string; attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 "; attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 "; begin Q(1 downto 0) <= \^q\(1 downto 0); \cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A69A" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => shandshake_r, I3 => sel, O => \cnt_read[1]_i_1__0_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => D(0), Q => \^q\(0), S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__0_n_0\, Q => \^q\(1), S => areset_d1 ); m_axi_bready_INST_0: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => mhandshake_r, O => m_axi_bready ); \memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \^q\(0), A1 => \^q\(1), A2 => '0', A3 => '0', CE => sel, CLK => aclk, D => \in\(0), Q => \skid_buffer_reg[1]\(0) ); \memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \^q\(0), A1 => \^q\(1), A2 => '0', A3 => '0', CE => sel, CLK => aclk, D => \in\(1), Q => \skid_buffer_reg[1]\(1) ); mhandshake_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"2000" ) port map ( I0 => m_axi_bvalid, I1 => mhandshake_r, I2 => \^q\(0), I3 => \^q\(1), O => mhandshake ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is port ( \cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC; \cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC; \cnt_read_reg[4]_rep__2_2\ : out STD_LOGIC; m_axi_rready : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); s_ready_i_reg : in STD_LOGIC; \cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC; si_rs_rready : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\; architecture STRUCTURE of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC; signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_5_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__3_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_2\ : STD_LOGIC; signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC; signal wr_en0 : STD_LOGIC; signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair18"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__3\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__3\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__3\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]"; attribute KEEP of \cnt_read_reg[2]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]"; attribute KEEP of \cnt_read_reg[3]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]"; attribute KEEP of \cnt_read_reg[4]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]"; attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair19"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name : string; attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 "; attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 "; attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 "; attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 "; attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 "; attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 "; attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 "; attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 "; attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 "; attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 "; attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 "; attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 "; attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 "; attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 "; attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 "; attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 "; attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 "; attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 "; attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 "; attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 "; attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 "; attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 "; attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 "; attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 "; attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 "; attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 "; attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 "; attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 "; attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 "; attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 "; attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 "; attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 "; attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 "; attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 "; attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair19"; begin \cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\; \cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\; \cnt_read_reg[4]_rep__2_2\ <= \^cnt_read_reg[4]_rep__2_2\; \cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => \cnt_read_reg[0]_rep__2_n_0\, I1 => s_ready_i_reg, I2 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[0]_i_1__1_n_0\ ); \cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"9AA6" ) port map ( I0 => \cnt_read_reg[1]_rep__2_n_0\, I1 => \cnt_read_reg[0]_rep__2_n_0\, I2 => s_ready_i_reg, I3 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[1]_i_1__2_n_0\ ); \cnt_read[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"A9AAAA6A" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read_reg[0]_rep__2_n_0\, I3 => \cnt_read[4]_i_5_n_0\, I4 => s_ready_i_reg, O => \cnt_read[2]_i_1_n_0\ ); \cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAA6AA9AAAAAA" ) port map ( I0 => \^cnt_read_reg[4]_rep__2_0\, I1 => \cnt_read_reg[2]_rep__2_n_0\, I2 => \cnt_read_reg[1]_rep__2_n_0\, I3 => \cnt_read[4]_i_5_n_0\, I4 => s_ready_i_reg, I5 => \cnt_read_reg[0]_rep__2_n_0\, O => \cnt_read[3]_i_1__0_n_0\ ); \cnt_read[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"99AA99AA99AA55A6" ) port map ( I0 => \^cnt_read_reg[4]_rep__2_1\, I1 => \^cnt_read_reg[4]_rep__2_0\, I2 => \^cnt_read_reg[4]_rep__2_2\, I3 => \cnt_read[4]_i_3__0_n_0\, I4 => s_ready_i_reg, I5 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[4]_i_1_n_0\ ); \cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \cnt_read_reg[0]_rep__3_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read_reg[2]_rep__2_n_0\, O => \^cnt_read_reg[4]_rep__2_2\ ); \cnt_read[4]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000100000" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read[4]_i_5_n_0\, I3 => \cnt_read_reg[4]_rep__0_0\, I4 => si_rs_rready, I5 => \cnt_read_reg[0]_rep__2_n_0\, O => \cnt_read[4]_i_3__0_n_0\ ); \cnt_read[4]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"6000E000FFFFFFFF" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \^cnt_read_reg[4]_rep__2_0\, I4 => \cnt_read_reg[0]_rep__3_n_0\, I5 => m_axi_rvalid, O => \cnt_read[4]_i_5_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__3\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__3_n_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => cnt_read(2), S => areset_d1 ); \cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => cnt_read(3), S => areset_d1 ); \cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \^cnt_read_reg[4]_rep__2_0\, S => areset_d1 ); \cnt_read_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => cnt_read(4), S => areset_d1 ); \cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \^cnt_read_reg[4]_rep__2_1\, S => areset_d1 ); m_axi_rready_INST_0: unisim.vcomponents.LUT5 generic map( INIT => X"9FFF1FFF" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \^cnt_read_reg[4]_rep__2_0\, I4 => \cnt_read_reg[0]_rep__3_n_0\, O => m_axi_rready ); \memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(0), Q => \out\(0), Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"8AAA0AAA0AAAAAAA" ) port map ( I0 => m_axi_rvalid, I1 => \cnt_read_reg[0]_rep__3_n_0\, I2 => \^cnt_read_reg[4]_rep__2_0\, I3 => \^cnt_read_reg[4]_rep__2_1\, I4 => \cnt_read_reg[1]_rep__2_n_0\, I5 => \cnt_read_reg[2]_rep__2_n_0\, O => wr_en0 ); \memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(10), Q => \out\(10), Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(11), Q => \out\(11), Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(12), Q => \out\(12), Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(13), Q => \out\(13), Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(14), Q => \out\(14), Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(15), Q => \out\(15), Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(16), Q => \out\(16), Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(17), Q => \out\(17), Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(18), Q => \out\(18), Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(19), Q => \out\(19), Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(1), Q => \out\(1), Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(20), Q => \out\(20), Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(21), Q => \out\(21), Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(22), Q => \out\(22), Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(23), Q => \out\(23), Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(24), Q => \out\(24), Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(25), Q => \out\(25), Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(26), Q => \out\(26), Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(27), Q => \out\(27), Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(28), Q => \out\(28), Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(29), Q => \out\(29), Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(2), Q => \out\(2), Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(30), Q => \out\(30), Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(31), Q => \out\(31), Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(32), Q => \out\(32), Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(33), Q => \out\(33), Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(3), Q => \out\(3), Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(4), Q => \out\(4), Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(5), Q => \out\(5), Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(6), Q => \out\(6), Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(7), Q => \out\(7), Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(8), Q => \out\(8), Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(9), Q => \out\(9), Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ ); \state[1]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"40C0C000" ) port map ( I0 => \cnt_read_reg[0]_rep__3_n_0\, I1 => \^cnt_read_reg[4]_rep__2_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \cnt_read_reg[1]_rep__2_n_0\, I4 => \cnt_read_reg[2]_rep__2_n_0\, O => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is port ( m_valid_i_reg : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; \skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); s_ready_i_reg : in STD_LOGIC; r_push_r : in STD_LOGIC; si_rs_rready : in STD_LOGIC; \cnt_read_reg[3]_rep__2\ : in STD_LOGIC; \cnt_read_reg[4]_rep__2\ : in STD_LOGIC; \cnt_read_reg[0]_rep__3\ : in STD_LOGIC; \cnt_read_reg[0]_rep__3_0\ : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\; architecture STRUCTURE of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC; signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC; signal m_valid_i_i_3_n_0 : STD_LOGIC; signal \^m_valid_i_reg\ : STD_LOGIC; signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair20"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute KEEP of \cnt_read_reg[2]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]"; attribute KEEP of \cnt_read_reg[3]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]"; attribute KEEP of \cnt_read_reg[4]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name : string; attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 "; attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 "; attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 "; attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 "; attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 "; attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 "; attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 "; attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 "; attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 "; attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 "; attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 "; attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 "; attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 "; begin m_valid_i_reg <= \^m_valid_i_reg\; \cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cnt_read_reg[0]_rep__0_n_0\, I1 => r_push_r, I2 => s_ready_i_reg, O => \cnt_read[0]_i_1__0_n_0\ ); \cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"DB24" ) port map ( I0 => \cnt_read_reg[0]_rep__0_n_0\, I1 => s_ready_i_reg, I2 => r_push_r, I3 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[1]_i_1__1_n_0\ ); \cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => s_ready_i_reg, I2 => r_push_r, I3 => \cnt_read_reg[0]_rep__0_n_0\, I4 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[2]_i_1__0_n_0\ ); \cnt_read[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF7F0080FEFF0100" ) port map ( I0 => \cnt_read_reg[1]_rep__0_n_0\, I1 => \cnt_read_reg[0]_rep__0_n_0\, I2 => r_push_r, I3 => s_ready_i_reg, I4 => \cnt_read_reg[3]_rep__0_n_0\, I5 => \cnt_read_reg[2]_rep__0_n_0\, O => \cnt_read[3]_i_1_n_0\ ); \cnt_read[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9A999AAA" ) port map ( I0 => \cnt_read_reg[4]_rep__0_n_0\, I1 => \cnt_read[4]_i_2_n_0\, I2 => \cnt_read_reg[2]_rep__0_n_0\, I3 => \cnt_read_reg[3]_rep__0_n_0\, I4 => \cnt_read[4]_i_3_n_0\, O => \cnt_read[4]_i_1__0_n_0\ ); \cnt_read[4]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"2AAAAAAA2AAA2AAA" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => \cnt_read_reg[1]_rep__0_n_0\, I2 => \cnt_read_reg[0]_rep__1_n_0\, I3 => r_push_r, I4 => \^m_valid_i_reg\, I5 => si_rs_rready, O => \cnt_read[4]_i_2_n_0\ ); \cnt_read[4]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000004" ) port map ( I0 => r_push_r, I1 => si_rs_rready, I2 => \^m_valid_i_reg\, I3 => \cnt_read_reg[0]_rep__1_n_0\, I4 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[4]_i_3_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => \cnt_read_reg[1]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => cnt_read(2), S => areset_d1 ); \cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => \cnt_read_reg[2]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => \cnt_read_reg[2]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => cnt_read(3), S => areset_d1 ); \cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => \cnt_read_reg[3]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => \cnt_read_reg[3]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => cnt_read(4), S => areset_d1 ); \cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => \cnt_read_reg[4]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => \cnt_read_reg[4]_rep__0_n_0\, S => areset_d1 ); m_valid_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"80808080FF808080" ) port map ( I0 => \cnt_read_reg[4]_rep__0_n_0\, I1 => \cnt_read_reg[3]_rep__0_n_0\, I2 => m_valid_i_i_3_n_0, I3 => \cnt_read_reg[3]_rep__2\, I4 => \cnt_read_reg[4]_rep__2\, I5 => \cnt_read_reg[0]_rep__3\, O => \^m_valid_i_reg\ ); m_valid_i_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => \cnt_read_reg[0]_rep__1_n_0\, I2 => \cnt_read_reg[1]_rep__0_n_0\, O => m_valid_i_i_3_n_0 ); \memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(0), Q => \skid_buffer_reg[46]\(0), Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(10), Q => \skid_buffer_reg[46]\(10), Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(11), Q => \skid_buffer_reg[46]\(11), Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(12), Q => \skid_buffer_reg[46]\(12), Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(1), Q => \skid_buffer_reg[46]\(1), Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(2), Q => \skid_buffer_reg[46]\(2), Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(3), Q => \skid_buffer_reg[46]\(3), Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(4), Q => \skid_buffer_reg[46]\(4), Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(5), Q => \skid_buffer_reg[46]\(5), Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(6), Q => \skid_buffer_reg[46]\(6), Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(7), Q => \skid_buffer_reg[46]\(7), Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(8), Q => \skid_buffer_reg[46]\(8), Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(9), Q => \skid_buffer_reg[46]\(9), Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ ); \state[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"BFEEAAAAAAAAAAAA" ) port map ( I0 => \cnt_read_reg[0]_rep__3_0\, I1 => \cnt_read_reg[2]_rep__0_n_0\, I2 => \cnt_read_reg[0]_rep__1_n_0\, I3 => \cnt_read_reg[1]_rep__0_n_0\, I4 => \cnt_read_reg[3]_rep__0_n_0\, I5 => \cnt_read_reg[4]_rep__0_n_0\, O => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is port ( \axlen_cnt_reg[7]\ : out STD_LOGIC; \axlen_cnt_reg[7]_0\ : out STD_LOGIC; \axlen_cnt_reg[7]_1\ : out STD_LOGIC; \next\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); D : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axburst_eq0_reg : out STD_LOGIC; incr_next_pending : out STD_LOGIC; sel_first_i : out STD_LOGIC; s_axburst_eq1_reg : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); b_push : out STD_LOGIC; m_axi_awvalid : out STD_LOGIC; s_axburst_eq1_reg_0 : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; \cnt_read_reg[0]_rep__0\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC; si_rs_awvalid : in STD_LOGIC; \axlen_cnt_reg[7]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axlen_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); wrap_next_pending : in STD_LOGIC; next_pending_r_reg : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; sel_first : in STD_LOGIC; areset_d1 : in STD_LOGIC; sel_first_0 : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[5]\ : in STD_LOGIC; aclk : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^axlen_cnt_reg[7]\ : STD_LOGIC; signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC; signal \^b_push\ : STD_LOGIC; signal \^incr_next_pending\ : STD_LOGIC; signal \^next\ : STD_LOGIC; signal \^sel_first_i\ : STD_LOGIC; signal \state[0]_i_1_n_0\ : STD_LOGIC; signal \state[0]_i_2_n_0\ : STD_LOGIC; signal \state[1]_i_1__0_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__0\ : label is "soft_lutpair109"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair110"; attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair110"; attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair109"; attribute KEEP : string; attribute KEEP of \state_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1; attribute KEEP of \state_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]"; attribute KEEP of \state_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1; attribute KEEP of \state_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4\ : label is "soft_lutpair111"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6\ : label is "soft_lutpair111"; begin E(0) <= \^e\(0); Q(1 downto 0) <= \^q\(1 downto 0); \axlen_cnt_reg[7]\ <= \^axlen_cnt_reg[7]\; \axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\; b_push <= \^b_push\; incr_next_pending <= \^incr_next_pending\; \next\ <= \^next\; sel_first_i <= \^sel_first_i\; \axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAACAAAAAAA0AA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \m_payload_i_reg[46]\(2), I2 => \^axlen_cnt_reg[7]_0\, I3 => si_rs_awvalid, I4 => \^axlen_cnt_reg[7]\, I5 => \m_payload_i_reg[5]\, O => \axaddr_offset_r_reg[2]\(0) ); \axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0400FFFF04000400" ) port map ( I0 => \^q\(1), I1 => si_rs_awvalid, I2 => \^q\(0), I3 => \m_payload_i_reg[46]\(1), I4 => \axlen_cnt_reg[0]_0\(0), I5 => \axlen_cnt_reg[7]_2\, O => \axlen_cnt_reg[0]\(0) ); \axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FF04" ) port map ( I0 => \^q\(0), I1 => si_rs_awvalid, I2 => \^q\(1), I3 => \^next\, O => \axaddr_wrap_reg[11]\(0) ); \axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF04" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]\, I3 => \^next\, I4 => \axlen_cnt_reg[7]_2\, O => \axlen_cnt_reg[7]_1\ ); m_axi_awvalid_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => \^axlen_cnt_reg[7]\, O => m_axi_awvalid ); \m_payload_i[31]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^b_push\, I1 => si_rs_awvalid, O => \m_payload_i_reg[0]\(0) ); \memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"88008888A800A8A8" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => \^axlen_cnt_reg[7]\, I2 => m_axi_awready, I3 => \cnt_read_reg[0]_rep__0\, I4 => \cnt_read_reg[1]_rep__0\, I5 => s_axburst_eq1_reg_0, O => \^b_push\ ); next_pending_r_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF404" ) port map ( I0 => \^e\(0), I1 => next_pending_r_reg, I2 => \^next\, I3 => \axlen_cnt_reg[7]_2\, I4 => \m_payload_i_reg[47]\, O => \^incr_next_pending\ ); next_pending_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"F3F3FFFF51000000" ) port map ( I0 => s_axburst_eq1_reg_0, I1 => \cnt_read_reg[1]_rep__0\, I2 => \cnt_read_reg[0]_rep__0\, I3 => m_axi_awready, I4 => \^axlen_cnt_reg[7]_0\, I5 => \^axlen_cnt_reg[7]\, O => \^next\ ); s_axburst_eq0_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"BA8A" ) port map ( I0 => \^incr_next_pending\, I1 => \^sel_first_i\, I2 => \m_payload_i_reg[46]\(0), I3 => wrap_next_pending, O => s_axburst_eq0_reg ); s_axburst_eq1_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FE02" ) port map ( I0 => \^incr_next_pending\, I1 => \m_payload_i_reg[46]\(0), I2 => \^sel_first_i\, I3 => wrap_next_pending, O => s_axburst_eq1_reg ); sel_first_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF44444F44" ) port map ( I0 => \^next\, I1 => sel_first, I2 => \^q\(1), I3 => si_rs_awvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg ); \sel_first_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF44444F44" ) port map ( I0 => \^next\, I1 => sel_first_0, I2 => \^q\(1), I3 => si_rs_awvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg_0 ); \sel_first_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF04FFFFFF04FF04" ) port map ( I0 => \^axlen_cnt_reg[7]\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]_0\, I3 => areset_d1, I4 => \^next\, I5 => sel_first_reg_1, O => \^sel_first_i\ ); \state[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BBBA" ) port map ( I0 => \state[0]_i_2_n_0\, I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), O => \state[0]_i_1_n_0\ ); \state[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00F000F055750000" ) port map ( I0 => m_axi_awready, I1 => s_axburst_eq1_reg_0, I2 => \cnt_read_reg[1]_rep__0\, I3 => \cnt_read_reg[0]_rep__0\, I4 => \^axlen_cnt_reg[7]_0\, I5 => \^axlen_cnt_reg[7]\, O => \state[0]_i_2_n_0\ ); \state[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0C0CAE0000000000" ) port map ( I0 => s_axburst_eq1_reg_0, I1 => \cnt_read_reg[1]_rep__0\, I2 => \cnt_read_reg[0]_rep__0\, I3 => m_axi_awready, I4 => \^axlen_cnt_reg[7]\, I5 => \^axlen_cnt_reg[7]_0\, O => \state[1]_i_1__0_n_0\ ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[0]_i_1_n_0\, Q => \^q\(0), R => areset_d1 ); \state_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[0]_i_1_n_0\, Q => \^axlen_cnt_reg[7]_0\, R => areset_d1 ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[1]_i_1__0_n_0\, Q => \^q\(1), R => areset_d1 ); \state_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[1]_i_1__0_n_0\, Q => \^axlen_cnt_reg[7]\, R => areset_d1 ); \wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \^axlen_cnt_reg[7]\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]_0\, O => \^e\(0) ); \wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8A5575AA8A5545" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => D(0) ); \wrap_cnt_r[3]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(1), I1 => \^axlen_cnt_reg[7]_0\, I2 => si_rs_awvalid, I3 => \^axlen_cnt_reg[7]\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \^axlen_cnt_reg[7]_0\, I2 => si_rs_awvalid, I3 => \^axlen_cnt_reg[7]\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8AAA8AAA8AAABA" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => \wrap_second_len_r_reg[0]\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is port ( wrap_next_pending : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_awvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \next\ : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 10 downto 0 ); sel_first_reg_3 : in STD_LOGIC; \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 ); signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC; signal \axlen_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \next_pending_r_i_2__1_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \^sel_first_reg_0\ : STD_LOGIC; signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 1 to 1 ); signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^wrap_next_pending\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); begin sel_first_reg_0 <= \^sel_first_reg_0\; wrap_next_pending <= \^wrap_next_pending\; \wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0); \axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => \axaddr_offset_r_reg[3]_0\(0), R => '0' ); \axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => \axaddr_offset_r_reg[3]_0\(1), R => '0' ); \axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => \axaddr_offset_r_reg[3]_0\(2), R => '0' ); \axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => \axaddr_offset_r_reg[3]_0\(3), R => '0' ); \axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(0), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(0), I3 => \next\, I4 => \m_payload_i_reg[47]\(0), O => \axaddr_wrap[0]_i_1_n_0\ ); \axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(10), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(10), I3 => \next\, I4 => \m_payload_i_reg[47]\(10), O => \axaddr_wrap[10]_i_1_n_0\ ); \axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(11), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(11), I3 => \next\, I4 => \m_payload_i_reg[47]\(11), O => \axaddr_wrap[11]_i_1_n_0\ ); \axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"41" ) port map ( I0 => \axaddr_wrap[11]_i_4_n_0\, I1 => wrap_cnt_r(3), I2 => \axlen_cnt_reg_n_0_[3]\, O => \axaddr_wrap[11]_i_2_n_0\ ); \axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"6FF6FFFFFFFF6FF6" ) port map ( I0 => wrap_cnt_r(0), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => wrap_cnt_r(1), I4 => \axlen_cnt_reg_n_0_[2]\, I5 => wrap_cnt_r(2), O => \axaddr_wrap[11]_i_4_n_0\ ); \axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(1), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(1), I3 => \next\, I4 => \m_payload_i_reg[47]\(1), O => \axaddr_wrap[1]_i_1_n_0\ ); \axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(2), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(2), I3 => \next\, I4 => \m_payload_i_reg[47]\(2), O => \axaddr_wrap[2]_i_1_n_0\ ); \axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(3), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(3), I3 => \next\, I4 => \m_payload_i_reg[47]\(3), O => \axaddr_wrap[3]_i_1_n_0\ ); \axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => axaddr_wrap(3), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_3_n_0\ ); \axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => axaddr_wrap(2), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_4_n_0\ ); \axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => axaddr_wrap(1), I1 => \m_payload_i_reg[47]\(13), I2 => \m_payload_i_reg[47]\(12), O => \axaddr_wrap[3]_i_5_n_0\ ); \axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => axaddr_wrap(0), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(4), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(4), I3 => \next\, I4 => \m_payload_i_reg[47]\(4), O => \axaddr_wrap[4]_i_1_n_0\ ); \axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(5), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(5), I3 => \next\, I4 => \m_payload_i_reg[47]\(5), O => \axaddr_wrap[5]_i_1_n_0\ ); \axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(6), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(6), I3 => \next\, I4 => \m_payload_i_reg[47]\(6), O => \axaddr_wrap[6]_i_1_n_0\ ); \axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(7), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(7), I3 => \next\, I4 => \m_payload_i_reg[47]\(7), O => \axaddr_wrap[7]_i_1_n_0\ ); \axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(8), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(8), I3 => \next\, I4 => \m_payload_i_reg[47]\(8), O => \axaddr_wrap[8]_i_1_n_0\ ); \axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(9), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(9), I3 => \next\, I4 => \m_payload_i_reg[47]\(9), O => \axaddr_wrap[9]_i_1_n_0\ ); \axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[0]_i_1_n_0\, Q => axaddr_wrap(0), R => '0' ); \axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[10]_i_1_n_0\, Q => axaddr_wrap(10), R => '0' ); \axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[11]_i_1_n_0\, Q => axaddr_wrap(11), R => '0' ); \axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[7]_i_2_n_0\, CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3), CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\, CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\, CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_wrap0(11 downto 8), S(3 downto 0) => axaddr_wrap(11 downto 8) ); \axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[1]_i_1_n_0\, Q => axaddr_wrap(1), R => '0' ); \axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[2]_i_1_n_0\, Q => axaddr_wrap(2), R => '0' ); \axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[3]_i_1_n_0\, Q => axaddr_wrap(3), R => '0' ); \axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\, CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\, CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\, CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => axaddr_wrap(3 downto 0), O(3 downto 0) => axaddr_wrap0(3 downto 0), S(3) => \axaddr_wrap[3]_i_3_n_0\, S(2) => \axaddr_wrap[3]_i_4_n_0\, S(1) => \axaddr_wrap[3]_i_5_n_0\, S(0) => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[4]_i_1_n_0\, Q => axaddr_wrap(4), R => '0' ); \axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[5]_i_1_n_0\, Q => axaddr_wrap(5), R => '0' ); \axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[6]_i_1_n_0\, Q => axaddr_wrap(6), R => '0' ); \axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[7]_i_1_n_0\, Q => axaddr_wrap(7), R => '0' ); \axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[3]_i_2_n_0\, CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\, CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\, CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\, CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_wrap0(7 downto 4), S(3 downto 0) => axaddr_wrap(7 downto 4) ); \axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[8]_i_1_n_0\, Q => axaddr_wrap(8), R => '0' ); \axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[9]_i_1_n_0\, Q => axaddr_wrap(9), R => '0' ); \axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"A3A3A3A3A3A3A3A0" ) port map ( I0 => \m_payload_i_reg[47]\(15), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => E(0), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \axlen_cnt[0]_i_1_n_0\ ); \axlen_cnt[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAC3AAC3AAC3AAC0" ) port map ( I0 => \m_payload_i_reg[47]\(16), I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => E(0), I4 => \axlen_cnt_reg_n_0_[3]\, I5 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[1]_i_1_n_0\ ); \axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA9A80000A9A8" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => E(0), I5 => \m_payload_i_reg[47]\(17), O => \axlen_cnt[2]_i_1__0_n_0\ ); \axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAACCCCCCC0" ) port map ( I0 => \m_payload_i_reg[47]\(18), I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[0]\, I5 => E(0), O => \axlen_cnt[3]_i_1_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[0]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[1]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[2]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[3]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(0), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(0), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(0), O => m_axi_awaddr(0) ); \m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(10), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(10), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(9), O => m_axi_awaddr(10) ); \m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(11), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(11), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(10), O => m_axi_awaddr(11) ); \m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(1), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(1), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(1), O => m_axi_awaddr(1) ); \m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(2), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(2), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(2), O => m_axi_awaddr(2) ); \m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(3), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(3), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(3), O => m_axi_awaddr(3) ); \m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(4), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(4), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(4), O => m_axi_awaddr(4) ); \m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \m_payload_i_reg[47]\(5), I1 => \^sel_first_reg_0\, I2 => axaddr_wrap(5), I3 => \m_payload_i_reg[47]\(14), I4 => sel_first_reg_3, O => m_axi_awaddr(5) ); \m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(6), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(6), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(5), O => m_axi_awaddr(6) ); \m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(7), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(7), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(6), O => m_axi_awaddr(7) ); \m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(8), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(8), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(7), O => m_axi_awaddr(8) ); \m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(9), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(9), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(8), O => m_axi_awaddr(9) ); \next_pending_r_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FEAAFEAE" ) port map ( I0 => \m_payload_i_reg[47]_0\, I1 => next_pending_r_reg_n_0, I2 => \next\, I3 => \next_pending_r_i_2__1_n_0\, I4 => E(0), O => \^wrap_next_pending\ ); \next_pending_r_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBFBFBFBFBFB00" ) port map ( I0 => \state_reg[1]\(0), I1 => si_rs_awvalid, I2 => \state_reg[1]\(1), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \next_pending_r_i_2__1_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \^wrap_next_pending\, Q => next_pending_r_reg_n_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_1, Q => \^sel_first_reg_0\, R => '0' ); \wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(0), Q => wrap_boundary_axaddr_r(0), R => '0' ); \wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(10), Q => wrap_boundary_axaddr_r(10), R => '0' ); \wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(11), Q => wrap_boundary_axaddr_r(11), R => '0' ); \wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(1), Q => wrap_boundary_axaddr_r(1), R => '0' ); \wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(2), Q => wrap_boundary_axaddr_r(2), R => '0' ); \wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(3), Q => wrap_boundary_axaddr_r(3), R => '0' ); \wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(4), Q => wrap_boundary_axaddr_r(4), R => '0' ); \wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(5), Q => wrap_boundary_axaddr_r(5), R => '0' ); \wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(6), Q => wrap_boundary_axaddr_r(6), R => '0' ); \wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(7), Q => wrap_boundary_axaddr_r(7), R => '0' ); \wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(8), Q => wrap_boundary_axaddr_r(8), R => '0' ); \wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(9), Q => wrap_boundary_axaddr_r(9), R => '0' ); \wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"3D310E02" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(0), I1 => E(0), I2 => \axaddr_offset_r_reg[3]_2\, I3 => D(1), I4 => \^wrap_second_len_r_reg[3]_0\(1), O => wrap_cnt(1) ); \wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"000CAAA8000C0000" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(1), I1 => \axaddr_offset_r_reg[3]_1\, I2 => D(1), I3 => D(0), I4 => E(0), I5 => \^wrap_second_len_r_reg[3]_0\(0), O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(0), Q => wrap_cnt_r(0), R => '0' ); \wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cnt(1), Q => wrap_cnt_r(1), R => '0' ); \wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(1), Q => wrap_cnt_r(2), R => '0' ); \wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(2), Q => wrap_cnt_r(3), R => '0' ); \wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(0), Q => \^wrap_second_len_r_reg[3]_0\(0), R => '0' ); \wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(1), Q => \^wrap_second_len_r_reg[3]_0\(1), R => '0' ); \wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(2), Q => \^wrap_second_len_r_reg[3]_0\(2), R => '0' ); \wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(3), Q => \^wrap_second_len_r_reg[3]_0\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is port ( sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axburst_eq0_reg : out STD_LOGIC; s_axburst_eq1_reg : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 18 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_arvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); sel_first_i : in STD_LOGIC; incr_next_pending : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); sel_first_reg_3 : in STD_LOGIC; sel_first_reg_4 : in STD_LOGIC; sel_first_reg_5 : in STD_LOGIC; sel_first_reg_6 : in STD_LOGIC; \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_17_b2s_wrap_cmd"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC; signal \axlen_cnt[0]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \next_pending_r_i_2__2_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \^sel_first_reg_0\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC; signal wrap_next_pending : STD_LOGIC; signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair16"; begin sel_first_reg_0 <= \^sel_first_reg_0\; \wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0); \axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => \axaddr_offset_r_reg[3]_0\(0), R => '0' ); \axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => \axaddr_offset_r_reg[3]_0\(1), R => '0' ); \axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => \axaddr_offset_r_reg[3]_0\(2), R => '0' ); \axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => \axaddr_offset_r_reg[3]_0\(3), R => '0' ); \axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(0), O => \axaddr_wrap[0]_i_1__0_n_0\ ); \axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(10), O => \axaddr_wrap[10]_i_1__0_n_0\ ); \axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(11), O => \axaddr_wrap[11]_i_1__0_n_0\ ); \axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"41" ) port map ( I0 => \axaddr_wrap[11]_i_4__0_n_0\, I1 => \wrap_cnt_r_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[3]\, O => \axaddr_wrap[11]_i_2__0_n_0\ ); \axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"6FF6FFFFFFFF6FF6" ) port map ( I0 => \wrap_cnt_r_reg_n_0_[0]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \wrap_cnt_r_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \wrap_cnt_r_reg_n_0_[1]\, O => \axaddr_wrap[11]_i_4__0_n_0\ ); \axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(1), O => \axaddr_wrap[1]_i_1__0_n_0\ ); \axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(2), O => \axaddr_wrap[2]_i_1__0_n_0\ ); \axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(3), O => \axaddr_wrap[3]_i_1__0_n_0\ ); \axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[3]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_3_n_0\ ); \axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[2]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_4_n_0\ ); \axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[1]\, I1 => Q(13), I2 => Q(12), O => \axaddr_wrap[3]_i_5_n_0\ ); \axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \axaddr_wrap_reg_n_0_[0]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(4), O => \axaddr_wrap[4]_i_1__0_n_0\ ); \axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(5), O => \axaddr_wrap[5]_i_1__0_n_0\ ); \axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(6), O => \axaddr_wrap[6]_i_1__0_n_0\ ); \axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(7), O => \axaddr_wrap[7]_i_1__0_n_0\ ); \axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(8), O => \axaddr_wrap[8]_i_1__0_n_0\ ); \axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(9), O => \axaddr_wrap[9]_i_1__0_n_0\ ); \axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[0]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[0]\, R => '0' ); \axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[10]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[10]\, R => '0' ); \axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[11]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[11]\, R => '0' ); \axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[7]_i_2__0_n_0\, CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\, CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\, CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\, O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\, O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\, O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\, S(3) => \axaddr_wrap_reg_n_0_[11]\, S(2) => \axaddr_wrap_reg_n_0_[10]\, S(1) => \axaddr_wrap_reg_n_0_[9]\, S(0) => \axaddr_wrap_reg_n_0_[8]\ ); \axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[1]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[1]\, R => '0' ); \axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[2]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[2]\, R => '0' ); \axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[3]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[3]\, R => '0' ); \axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\, CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\, CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\, CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\, CYINIT => '0', DI(3) => \axaddr_wrap_reg_n_0_[3]\, DI(2) => \axaddr_wrap_reg_n_0_[2]\, DI(1) => \axaddr_wrap_reg_n_0_[1]\, DI(0) => \axaddr_wrap_reg_n_0_[0]\, O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\, O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\, O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\, O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\, S(3) => \axaddr_wrap[3]_i_3_n_0\, S(2) => \axaddr_wrap[3]_i_4_n_0\, S(1) => \axaddr_wrap[3]_i_5_n_0\, S(0) => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[4]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[4]\, R => '0' ); \axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[5]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[5]\, R => '0' ); \axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[6]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[6]\, R => '0' ); \axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[7]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[7]\, R => '0' ); \axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[3]_i_2__0_n_0\, CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\, CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\, CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\, CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\, O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\, O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\, O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\, S(3) => \axaddr_wrap_reg_n_0_[7]\, S(2) => \axaddr_wrap_reg_n_0_[6]\, S(1) => \axaddr_wrap_reg_n_0_[5]\, S(0) => \axaddr_wrap_reg_n_0_[4]\ ); \axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[8]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[8]\, R => '0' ); \axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[9]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[9]\, R => '0' ); \axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"A3A3A3A3A3A3A3A0" ) port map ( I0 => Q(15), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => E(0), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \axlen_cnt[0]_i_1__1_n_0\ ); \axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"AAC3AAC3AAC3AAC0" ) port map ( I0 => Q(16), I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => E(0), I4 => \axlen_cnt_reg_n_0_[3]\, I5 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[1]_i_1__2_n_0\ ); \axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA9A80000A9A8" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => E(0), I5 => Q(17), O => \axlen_cnt[2]_i_1__2_n_0\ ); \axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAACCCCCCC0" ) port map ( I0 => Q(18), I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[0]\, I5 => E(0), O => \axlen_cnt[3]_i_1__1_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[0]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[1]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[2]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[3]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[0]\, I2 => Q(14), I3 => Q(0), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(0), O => m_axi_araddr(0) ); \m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[10]\, I2 => Q(14), I3 => Q(10), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(6), O => m_axi_araddr(10) ); \m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[11]\, I2 => Q(14), I3 => Q(11), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(7), O => m_axi_araddr(11) ); \m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(1), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[1]\, I3 => Q(14), I4 => sel_first_reg_6, O => m_axi_araddr(1) ); \m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(2), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[2]\, I3 => Q(14), I4 => sel_first_reg_5, O => m_axi_araddr(2) ); \m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(3), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[3]\, I3 => Q(14), I4 => sel_first_reg_4, O => m_axi_araddr(3) ); \m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[4]\, I2 => Q(14), I3 => Q(4), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(1), O => m_axi_araddr(4) ); \m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(5), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[5]\, I3 => Q(14), I4 => sel_first_reg_3, O => m_axi_araddr(5) ); \m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[6]\, I2 => Q(14), I3 => Q(6), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(2), O => m_axi_araddr(6) ); \m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[7]\, I2 => Q(14), I3 => Q(7), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(3), O => m_axi_araddr(7) ); \m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[8]\, I2 => Q(14), I3 => Q(8), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(4), O => m_axi_araddr(8) ); \m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[9]\, I2 => Q(14), I3 => Q(9), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(5), O => m_axi_araddr(9) ); \next_pending_r_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"FEAAFEAE" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => next_pending_r_reg_n_0, I2 => \state_reg[1]_rep\, I3 => \next_pending_r_i_2__2_n_0\, I4 => E(0), O => wrap_next_pending ); \next_pending_r_i_2__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBFBFBFBFBFB00" ) port map ( I0 => \state_reg[1]\(0), I1 => si_rs_arvalid, I2 => \state_reg[1]\(1), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \next_pending_r_i_2__2_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_next_pending, Q => next_pending_r_reg_n_0, R => '0' ); \s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => wrap_next_pending, I1 => Q(14), I2 => sel_first_i, I3 => incr_next_pending, O => s_axburst_eq0_reg ); \s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"ABA8" ) port map ( I0 => wrap_next_pending, I1 => Q(14), I2 => sel_first_i, I3 => incr_next_pending, O => s_axburst_eq1_reg ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_1, Q => \^sel_first_reg_0\, R => '0' ); \wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(0), Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\, R => '0' ); \wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(10), Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\, R => '0' ); \wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(11), Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\, R => '0' ); \wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(1), Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\, R => '0' ); \wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(2), Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\, R => '0' ); \wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(3), Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\, R => '0' ); \wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(4), Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\, R => '0' ); \wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(5), Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\, R => '0' ); \wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(6), Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\, R => '0' ); \wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(7), Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\, R => '0' ); \wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(8), Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\, R => '0' ); \wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(9), Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\, R => '0' ); \wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"3D310E02" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(0), I1 => E(0), I2 => \axaddr_offset_r_reg[3]_2\, I3 => D(1), I4 => \^wrap_second_len_r_reg[3]_0\(1), O => \wrap_cnt_r[1]_i_1__0_n_0\ ); \wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"000CAAA8000C0000" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(1), I1 => \axaddr_offset_r_reg[3]_1\, I2 => D(1), I3 => D(0), I4 => E(0), I5 => \^wrap_second_len_r_reg[3]_0\(0), O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(0), Q => \wrap_cnt_r_reg_n_0_[0]\, R => '0' ); \wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_cnt_r[1]_i_1__0_n_0\, Q => \wrap_cnt_r_reg_n_0_[1]\, R => '0' ); \wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(1), Q => \wrap_cnt_r_reg_n_0_[2]\, R => '0' ); \wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(2), Q => \wrap_cnt_r_reg_n_0_[3]\, R => '0' ); \wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(0), Q => \^wrap_second_len_r_reg[3]_0\(0), R => '0' ); \wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(1), Q => \^wrap_second_len_r_reg[3]_0\(1), R => '0' ); \wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(2), Q => \^wrap_second_len_r_reg[3]_0\(2), R => '0' ); \wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(3), Q => \^wrap_second_len_r_reg[3]_0\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice is port ( s_axi_arready : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC; m_valid_i_reg_0 : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); O : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; \axaddr_offset_r_reg[0]\ : out STD_LOGIC; axaddr_offset_0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \aresetn_d_reg[0]\ : in STD_LOGIC; s_ready_i0 : in STD_LOGIC; aclk : in STD_LOGIC; m_valid_i0 : in STD_LOGIC; \aresetn_d_reg[0]_0\ : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice; architecture STRUCTURE of design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice is signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 ); signal \axaddr_incr[3]_i_4__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_5__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_6__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_3\ : STD_LOGIC; signal \^axaddr_offset_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_offset_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC; signal \^axlen_cnt_reg[3]\ : STD_LOGIC; signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC; signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[52]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal \^s_axi_arready\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \wrap_cnt_r[3]_i_5__0_n_0\ : STD_LOGIC; signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_3__0_n_0\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[52]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair21"; begin Q(54 downto 0) <= \^q\(54 downto 0); axaddr_offset_0(1 downto 0) <= \^axaddr_offset_0\(1 downto 0); \axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\; \axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\; \axaddr_offset_r_reg[3]\ <= \^axaddr_offset_r_reg[3]\; \axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; s_axi_arready <= \^s_axi_arready\; \wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\; \wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0); \aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \aresetn_d_reg[0]_0\, Q => \^m_valid_i_reg_0\, R => '0' ); \axaddr_incr[3]_i_4__0\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => \^q\(2), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_4__0_n_0\ ); \axaddr_incr[3]_i_5__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(1), I1 => \^q\(36), O => \axaddr_incr[3]_i_5__0_n_0\ ); \axaddr_incr[3]_i_6__0\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_6__0_n_0\ ); \axaddr_incr_reg[11]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_2__0_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[11]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[11]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => O(3 downto 0), S(3 downto 0) => \^q\(11 downto 8) ); \axaddr_incr_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_2__0_n_0\, CO(2) => \axaddr_incr_reg[3]_i_2__0_n_1\, CO(1) => \axaddr_incr_reg[3]_i_2__0_n_2\, CO(0) => \axaddr_incr_reg[3]_i_2__0_n_3\, CYINIT => '0', DI(3) => \^q\(3), DI(2) => \axaddr_incr[3]_i_4__0_n_0\, DI(1) => \axaddr_incr[3]_i_5__0_n_0\, DI(0) => \axaddr_incr[3]_i_6__0_n_0\, O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0) ); \axaddr_incr_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_2__0_n_0\, CO(3) => \axaddr_incr_reg[7]_i_2__0_n_0\, CO(2) => \axaddr_incr_reg[7]_i_2__0_n_1\, CO(1) => \axaddr_incr_reg[7]_i_2__0_n_2\, CO(0) => \axaddr_incr_reg[7]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), S(3 downto 0) => \^q\(7 downto 4) ); \axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[0]_i_2__0_n_0\, I1 => \^q\(39), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(0), O => \^axaddr_offset_r_reg[0]\ ); \axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(3), I1 => \^q\(2), I2 => \^q\(36), I3 => \^q\(1), I4 => \^q\(35), I5 => \^q\(0), O => \axaddr_offset_r[0]_i_2__0_n_0\ ); \axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[1]_i_2__0_n_0\, I1 => \^q\(40), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(1), O => \^axaddr_offset_0\(0) ); \axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(4), I1 => \^q\(3), I2 => \^q\(36), I3 => \^q\(2), I4 => \^q\(35), I5 => \^q\(1), O => \axaddr_offset_r[1]_i_2__0_n_0\ ); \axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(5), I1 => \^q\(4), I2 => \^q\(36), I3 => \^q\(3), I4 => \^q\(35), I5 => \^q\(2), O => \^axaddr_offset_r_reg[2]\ ); \axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[3]_i_2__0_n_0\, I1 => \^q\(42), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(2), O => \^axaddr_offset_0\(1) ); \axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(6), I1 => \^q\(5), I2 => \^q\(36), I3 => \^q\(4), I4 => \^q\(35), I5 => \^q\(3), O => \axaddr_offset_r[3]_i_2__0_n_0\ ); \axlen_cnt[3]_i_3__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0020" ) port map ( I0 => \^q\(42), I1 => \state_reg[1]\(0), I2 => \^axaddr_offset_r_reg[3]\, I3 => \state_reg[1]\(1), O => \^axlen_cnt_reg[3]\ ); \m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__0_n_0\ ); \m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(10), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__0_n_0\ ); \m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(11), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__0_n_0\ ); \m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(12), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__0_n_0\ ); \m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(13), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_1__1_n_0\ ); \m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(14), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[14]\, O => \m_payload_i[14]_i_1__0_n_0\ ); \m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(15), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[15]\, O => \m_payload_i[15]_i_1__0_n_0\ ); \m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(16), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[16]\, O => \m_payload_i[16]_i_1__0_n_0\ ); \m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(17), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[17]\, O => \m_payload_i[17]_i_1__0_n_0\ ); \m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(18), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[18]\, O => \m_payload_i[18]_i_1__0_n_0\ ); \m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(19), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[19]\, O => \m_payload_i[19]_i_1__0_n_0\ ); \m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__0_n_0\ ); \m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(20), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[20]\, O => \m_payload_i[20]_i_1__0_n_0\ ); \m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(21), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[21]\, O => \m_payload_i[21]_i_1__0_n_0\ ); \m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(22), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[22]\, O => \m_payload_i[22]_i_1__0_n_0\ ); \m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(23), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[23]\, O => \m_payload_i[23]_i_1__0_n_0\ ); \m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(24), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[24]\, O => \m_payload_i[24]_i_1__0_n_0\ ); \m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(25), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[25]\, O => \m_payload_i[25]_i_1__0_n_0\ ); \m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(26), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[26]\, O => \m_payload_i[26]_i_1__0_n_0\ ); \m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(27), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[27]\, O => \m_payload_i[27]_i_1__0_n_0\ ); \m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(28), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[28]\, O => \m_payload_i[28]_i_1__0_n_0\ ); \m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(29), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[29]\, O => \m_payload_i[29]_i_1__0_n_0\ ); \m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__0_n_0\ ); \m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(30), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[30]\, O => \m_payload_i[30]_i_1__0_n_0\ ); \m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(31), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[31]\, O => \m_payload_i[31]_i_2__0_n_0\ ); \m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[32]\, O => \m_payload_i[32]_i_1__0_n_0\ ); \m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[33]\, O => \m_payload_i[33]_i_1__0_n_0\ ); \m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[34]\, O => \m_payload_i[34]_i_1__0_n_0\ ); \m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arsize(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[35]\, O => \m_payload_i[35]_i_1__0_n_0\ ); \m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arsize(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[36]\, O => \m_payload_i[36]_i_1__0_n_0\ ); \m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arburst(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[38]\, O => \m_payload_i[38]_i_1__0_n_0\ ); \m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arburst(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[39]\, O => \m_payload_i[39]_i_1__0_n_0\ ); \m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__0_n_0\ ); \m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[44]\, O => \m_payload_i[44]_i_1__0_n_0\ ); \m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[45]\, O => \m_payload_i[45]_i_1__0_n_0\ ); \m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[46]\, O => \m_payload_i[46]_i_1__1_n_0\ ); \m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[47]\, O => \m_payload_i[47]_i_1__0_n_0\ ); \m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(4), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__0_n_0\ ); \m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[50]\, O => \m_payload_i[50]_i_1__0_n_0\ ); \m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[51]\, O => \m_payload_i[51]_i_1__0_n_0\ ); \m_payload_i[52]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[52]\, O => \m_payload_i[52]_i_1__0_n_0\ ); \m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[53]\, O => \m_payload_i[53]_i_1__0_n_0\ ); \m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(4), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[54]\, O => \m_payload_i[54]_i_1__0_n_0\ ); \m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(5), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[55]\, O => \m_payload_i[55]_i_1__0_n_0\ ); \m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(6), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[56]\, O => \m_payload_i[56]_i_1__0_n_0\ ); \m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(7), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[57]\, O => \m_payload_i[57]_i_1__0_n_0\ ); \m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(8), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[58]\, O => \m_payload_i[58]_i_1__0_n_0\ ); \m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(9), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[59]\, O => \m_payload_i[59]_i_1__0_n_0\ ); \m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(5), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__0_n_0\ ); \m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(10), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[60]\, O => \m_payload_i[60]_i_1__0_n_0\ ); \m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(11), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[61]\, O => \m_payload_i[61]_i_1__0_n_0\ ); \m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(6), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__0_n_0\ ); \m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(7), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__0_n_0\ ); \m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(8), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__0_n_0\ ); \m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(9), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__0_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[0]_i_1__0_n_0\, Q => \^q\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[10]_i_1__0_n_0\, Q => \^q\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[11]_i_1__0_n_0\, Q => \^q\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[12]_i_1__0_n_0\, Q => \^q\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[13]_i_1__1_n_0\, Q => \^q\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[14]_i_1__0_n_0\, Q => \^q\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[15]_i_1__0_n_0\, Q => \^q\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[16]_i_1__0_n_0\, Q => \^q\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[17]_i_1__0_n_0\, Q => \^q\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[18]_i_1__0_n_0\, Q => \^q\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[19]_i_1__0_n_0\, Q => \^q\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[1]_i_1__0_n_0\, Q => \^q\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[20]_i_1__0_n_0\, Q => \^q\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[21]_i_1__0_n_0\, Q => \^q\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[22]_i_1__0_n_0\, Q => \^q\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[23]_i_1__0_n_0\, Q => \^q\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[24]_i_1__0_n_0\, Q => \^q\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[25]_i_1__0_n_0\, Q => \^q\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[26]_i_1__0_n_0\, Q => \^q\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[27]_i_1__0_n_0\, Q => \^q\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[28]_i_1__0_n_0\, Q => \^q\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[29]_i_1__0_n_0\, Q => \^q\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[2]_i_1__0_n_0\, Q => \^q\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[30]_i_1__0_n_0\, Q => \^q\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[31]_i_2__0_n_0\, Q => \^q\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[32]_i_1__0_n_0\, Q => \^q\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[33]_i_1__0_n_0\, Q => \^q\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[34]_i_1__0_n_0\, Q => \^q\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[35]_i_1__0_n_0\, Q => \^q\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[36]_i_1__0_n_0\, Q => \^q\(36), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[38]_i_1__0_n_0\, Q => \^q\(37), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[39]_i_1__0_n_0\, Q => \^q\(38), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[3]_i_1__0_n_0\, Q => \^q\(3), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[44]_i_1__0_n_0\, Q => \^q\(39), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[45]_i_1__0_n_0\, Q => \^q\(40), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[46]_i_1__1_n_0\, Q => \^q\(41), R => '0' ); \m_payload_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[47]_i_1__0_n_0\, Q => \^q\(42), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[4]_i_1__0_n_0\, Q => \^q\(4), R => '0' ); \m_payload_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[50]_i_1__0_n_0\, Q => \^q\(43), R => '0' ); \m_payload_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[51]_i_1__0_n_0\, Q => \^q\(44), R => '0' ); \m_payload_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[52]_i_1__0_n_0\, Q => \^q\(45), R => '0' ); \m_payload_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[53]_i_1__0_n_0\, Q => \^q\(46), R => '0' ); \m_payload_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[54]_i_1__0_n_0\, Q => \^q\(47), R => '0' ); \m_payload_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[55]_i_1__0_n_0\, Q => \^q\(48), R => '0' ); \m_payload_i_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[56]_i_1__0_n_0\, Q => \^q\(49), R => '0' ); \m_payload_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[57]_i_1__0_n_0\, Q => \^q\(50), R => '0' ); \m_payload_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[58]_i_1__0_n_0\, Q => \^q\(51), R => '0' ); \m_payload_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[59]_i_1__0_n_0\, Q => \^q\(52), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[5]_i_1__0_n_0\, Q => \^q\(5), R => '0' ); \m_payload_i_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[60]_i_1__0_n_0\, Q => \^q\(53), R => '0' ); \m_payload_i_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[61]_i_1__0_n_0\, Q => \^q\(54), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[6]_i_1__0_n_0\, Q => \^q\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[7]_i_1__0_n_0\, Q => \^q\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[8]_i_1__0_n_0\, Q => \^q\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[9]_i_1__0_n_0\, Q => \^q\(9), R => '0' ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^axaddr_offset_r_reg[3]\, R => \^m_valid_i_reg_0\ ); next_pending_r_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => \state_reg[1]_rep\, I1 => \^q\(42), I2 => \^q\(40), I3 => \^q\(39), I4 => \^q\(41), O => next_pending_r_reg ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^s_axi_arready\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(2), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arsize(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arsize(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arburst(0), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arburst(1), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(0), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(1), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(2), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(3), Q => \skid_buffer_reg_n_0_[47]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(0), Q => \skid_buffer_reg_n_0_[50]\, R => '0' ); \skid_buffer_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(1), Q => \skid_buffer_reg_n_0_[51]\, R => '0' ); \skid_buffer_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(2), Q => \skid_buffer_reg_n_0_[52]\, R => '0' ); \skid_buffer_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(3), Q => \skid_buffer_reg_n_0_[53]\, R => '0' ); \skid_buffer_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(4), Q => \skid_buffer_reg_n_0_[54]\, R => '0' ); \skid_buffer_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(5), Q => \skid_buffer_reg_n_0_[55]\, R => '0' ); \skid_buffer_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(6), Q => \skid_buffer_reg_n_0_[56]\, R => '0' ); \skid_buffer_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(7), Q => \skid_buffer_reg_n_0_[57]\, R => '0' ); \skid_buffer_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(8), Q => \skid_buffer_reg_n_0_[58]\, R => '0' ); \skid_buffer_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(9), Q => \skid_buffer_reg_n_0_[59]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(10), Q => \skid_buffer_reg_n_0_[60]\, R => '0' ); \skid_buffer_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(11), Q => \skid_buffer_reg_n_0_[61]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); \wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(39), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(0) ); \wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"8A888AAA" ) port map ( I0 => \^q\(1), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(40), O => \wrap_boundary_axaddr_r_reg[6]\(1) ); \wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0F553300000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(36), I5 => \^q\(2), O => \wrap_boundary_axaddr_r_reg[6]\(2) ); \wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"020202A2A2A202A2" ) port map ( I0 => \^q\(3), I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\, I2 => \^q\(36), I3 => \^q\(40), I4 => \^q\(35), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(3) ); \wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(41), I1 => \^q\(35), I2 => \^q\(42), O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ ); \wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"503F5F3F00000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(36), I3 => \^q\(35), I4 => \^q\(42), I5 => \^q\(4), O => \wrap_boundary_axaddr_r_reg[6]\(4) ); \wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"2A222AAA" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(41), I3 => \^q\(35), I4 => \^q\(42), O => \wrap_boundary_axaddr_r_reg[6]\(5) ); \wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"2AAA" ) port map ( I0 => \^q\(6), I1 => \^q\(42), I2 => \^q\(35), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(6) ); \wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA6AA56AAAAAAAA" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(1), I1 => \wrap_second_len_r_reg[3]_0\(0), I2 => \state_reg[1]_rep\, I3 => \^wrap_cnt_r_reg[2]\, I4 => \^axaddr_offset_r_reg[0]\, I5 => \^wrap_second_len_r_reg[3]\(0), O => \wrap_cnt_r_reg[3]\(0) ); \wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(2), I1 => \wrap_second_len_r_reg[1]\, I2 => \^wrap_second_len_r_reg[3]\(1), O => \wrap_cnt_r_reg[3]\(1) ); \wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFEAEAFFEA" ) port map ( I0 => \axaddr_offset_r_reg[3]_1\, I1 => \^axlen_cnt_reg[3]\, I2 => \axaddr_offset_r[3]_i_2__0_n_0\, I3 => \^axaddr_offset_r_reg[2]\, I4 => \wrap_cnt_r[3]_i_5__0_n_0\, I5 => \axaddr_offset_r_reg[2]_1\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r[3]_i_5__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \^q\(41), I1 => \state_reg[0]_rep\, I2 => \^axaddr_offset_r_reg[3]\, I3 => \state_reg[1]_rep_0\, O => \wrap_cnt_r[3]_i_5__0_n_0\ ); \wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0001000000010001" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset_0\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2__0_n_0\, I4 => \state_reg[1]_rep\, I5 => \axaddr_offset_r_reg[3]_0\(2), O => \^wrap_cnt_r_reg[2]\ ); \wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"F00EFFFFF00E0000" ) port map ( I0 => \^axaddr_offset_0\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_r_reg[0]\, I3 => \^axaddr_offset_0\(0), I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(1), O => \^wrap_second_len_r_reg[3]\(0) ); \wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"CCC2FFFFCCC20000" ) port map ( I0 => \^axaddr_offset_0\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_0\(0), I3 => \^axaddr_offset_r_reg[0]\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(2), O => \^wrap_second_len_r_reg[3]\(1) ); \wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FE00FFFFFE00FE00" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset_0\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2__0_n_0\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(3), O => \^wrap_second_len_r_reg[3]\(2) ); \wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"A8A8A8080808A808" ) port map ( I0 => \^axlen_cnt_reg[3]\, I1 => \wrap_second_len_r[3]_i_3__0_n_0\, I2 => \^q\(36), I3 => \^q\(5), I4 => \^q\(35), I5 => \^q\(6), O => \wrap_second_len_r[3]_i_2__0_n_0\ ); \wrap_second_len_r[3]_i_3__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(4), I1 => \^q\(35), I2 => \^q\(3), O => \wrap_second_len_r[3]_i_3__0_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 is port ( s_axi_awready : out STD_LOGIC; s_ready_i_reg_0 : out STD_LOGIC; m_valid_i_reg_0 : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; \axaddr_offset_r_reg[0]\ : out STD_LOGIC; axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \aresetn_d_reg[1]_inv\ : out STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[1]_inv_0\ : in STD_LOGIC; aresetn : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); S : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; b_push : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0; architecture STRUCTURE of design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 is signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 ); signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC; signal \axaddr_incr[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_3\ : STD_LOGIC; signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC; signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC; signal \axaddr_offset_r[3]_i_2_n_0\ : STD_LOGIC; signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC; signal \^axlen_cnt_reg[3]\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal \^s_axi_awready\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^s_ready_i_reg_0\ : STD_LOGIC; signal skid_buffer : STD_LOGIC_VECTOR ( 61 downto 0 ); signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC; signal \wrap_cnt_r[3]_i_5_n_0\ : STD_LOGIC; signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_3_n_0\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair49"; begin Q(54 downto 0) <= \^q\(54 downto 0); axaddr_offset(1 downto 0) <= \^axaddr_offset\(1 downto 0); \axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\; \axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\; \axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; s_axi_awready <= \^s_axi_awready\; s_ready_i_reg_0 <= \^s_ready_i_reg_0\; \wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\; \wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0); \aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \aresetn_d_reg_n_0_[0]\, I1 => aresetn, O => \aresetn_d_reg[1]_inv\ ); \aresetn_d_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => aresetn, Q => \aresetn_d_reg_n_0_[0]\, R => '0' ); \axaddr_incr[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => \^q\(2), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_4_n_0\ ); \axaddr_incr[3]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(1), I1 => \^q\(36), O => \axaddr_incr[3]_i_5_n_0\ ); \axaddr_incr[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_6_n_0\ ); \axaddr_incr_reg[11]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_2_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_3_n_1\, CO(1) => \axaddr_incr_reg[11]_i_3_n_2\, CO(0) => \axaddr_incr_reg[11]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_incr(11 downto 8), S(3 downto 0) => \^q\(11 downto 8) ); \axaddr_incr_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_2_n_0\, CO(2) => \axaddr_incr_reg[3]_i_2_n_1\, CO(1) => \axaddr_incr_reg[3]_i_2_n_2\, CO(0) => \axaddr_incr_reg[3]_i_2_n_3\, CYINIT => '0', DI(3) => \^q\(3), DI(2) => \axaddr_incr[3]_i_4_n_0\, DI(1) => \axaddr_incr[3]_i_5_n_0\, DI(0) => \axaddr_incr[3]_i_6_n_0\, O(3 downto 0) => axaddr_incr(3 downto 0), S(3 downto 0) => S(3 downto 0) ); \axaddr_incr_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_2_n_0\, CO(3) => \axaddr_incr_reg[7]_i_2_n_0\, CO(2) => \axaddr_incr_reg[7]_i_2_n_1\, CO(1) => \axaddr_incr_reg[7]_i_2_n_2\, CO(0) => \axaddr_incr_reg[7]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_incr(7 downto 4), S(3 downto 0) => \^q\(7 downto 4) ); \axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[0]_i_2_n_0\, I1 => \^q\(39), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(0), O => \^axaddr_offset_r_reg[0]\ ); \axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(3), I1 => \^q\(2), I2 => \^q\(36), I3 => \^q\(1), I4 => \^q\(35), I5 => \^q\(0), O => \axaddr_offset_r[0]_i_2_n_0\ ); \axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[1]_i_2_n_0\, I1 => \^q\(40), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(1), O => \^axaddr_offset\(0) ); \axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(4), I1 => \^q\(3), I2 => \^q\(36), I3 => \^q\(2), I4 => \^q\(35), I5 => \^q\(1), O => \axaddr_offset_r[1]_i_2_n_0\ ); \axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(5), I1 => \^q\(4), I2 => \^q\(36), I3 => \^q\(3), I4 => \^q\(35), I5 => \^q\(2), O => \^axaddr_offset_r_reg[2]\ ); \axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[3]_i_2_n_0\, I1 => \^q\(42), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(2), O => \^axaddr_offset\(1) ); \axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(6), I1 => \^q\(5), I2 => \^q\(36), I3 => \^q\(4), I4 => \^q\(35), I5 => \^q\(3), O => \axaddr_offset_r[3]_i_2_n_0\ ); \axlen_cnt[3]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0020" ) port map ( I0 => \^q\(42), I1 => \state_reg[1]\(0), I2 => \^m_valid_i_reg_0\, I3 => \state_reg[1]\(1), O => \^axlen_cnt_reg[3]\ ); \m_payload_i[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[0]\, O => skid_buffer(0) ); \m_payload_i[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(10), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[10]\, O => skid_buffer(10) ); \m_payload_i[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(11), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[11]\, O => skid_buffer(11) ); \m_payload_i[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(12), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[12]\, O => skid_buffer(12) ); \m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(13), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[13]\, O => skid_buffer(13) ); \m_payload_i[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(14), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[14]\, O => skid_buffer(14) ); \m_payload_i[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(15), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[15]\, O => skid_buffer(15) ); \m_payload_i[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(16), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[16]\, O => skid_buffer(16) ); \m_payload_i[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(17), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[17]\, O => skid_buffer(17) ); \m_payload_i[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(18), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[18]\, O => skid_buffer(18) ); \m_payload_i[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(19), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[19]\, O => skid_buffer(19) ); \m_payload_i[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[1]\, O => skid_buffer(1) ); \m_payload_i[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(20), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[20]\, O => skid_buffer(20) ); \m_payload_i[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(21), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[21]\, O => skid_buffer(21) ); \m_payload_i[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(22), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[22]\, O => skid_buffer(22) ); \m_payload_i[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(23), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[23]\, O => skid_buffer(23) ); \m_payload_i[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(24), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[24]\, O => skid_buffer(24) ); \m_payload_i[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(25), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[25]\, O => skid_buffer(25) ); \m_payload_i[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(26), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[26]\, O => skid_buffer(26) ); \m_payload_i[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(27), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[27]\, O => skid_buffer(27) ); \m_payload_i[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(28), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[28]\, O => skid_buffer(28) ); \m_payload_i[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(29), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[29]\, O => skid_buffer(29) ); \m_payload_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[2]\, O => skid_buffer(2) ); \m_payload_i[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(30), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[30]\, O => skid_buffer(30) ); \m_payload_i[31]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(31), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[31]\, O => skid_buffer(31) ); \m_payload_i[32]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[32]\, O => skid_buffer(32) ); \m_payload_i[33]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[33]\, O => skid_buffer(33) ); \m_payload_i[34]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[34]\, O => skid_buffer(34) ); \m_payload_i[35]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awsize(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[35]\, O => skid_buffer(35) ); \m_payload_i[36]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awsize(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[36]\, O => skid_buffer(36) ); \m_payload_i[38]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awburst(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[38]\, O => skid_buffer(38) ); \m_payload_i[39]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awburst(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[39]\, O => skid_buffer(39) ); \m_payload_i[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[3]\, O => skid_buffer(3) ); \m_payload_i[44]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[44]\, O => skid_buffer(44) ); \m_payload_i[45]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[45]\, O => skid_buffer(45) ); \m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[46]\, O => skid_buffer(46) ); \m_payload_i[47]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[47]\, O => skid_buffer(47) ); \m_payload_i[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(4), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[4]\, O => skid_buffer(4) ); \m_payload_i[50]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[50]\, O => skid_buffer(50) ); \m_payload_i[51]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[51]\, O => skid_buffer(51) ); \m_payload_i[52]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[52]\, O => skid_buffer(52) ); \m_payload_i[53]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[53]\, O => skid_buffer(53) ); \m_payload_i[54]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(4), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[54]\, O => skid_buffer(54) ); \m_payload_i[55]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(5), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[55]\, O => skid_buffer(55) ); \m_payload_i[56]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(6), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[56]\, O => skid_buffer(56) ); \m_payload_i[57]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(7), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[57]\, O => skid_buffer(57) ); \m_payload_i[58]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(8), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[58]\, O => skid_buffer(58) ); \m_payload_i[59]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(9), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[59]\, O => skid_buffer(59) ); \m_payload_i[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(5), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[5]\, O => skid_buffer(5) ); \m_payload_i[60]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(10), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[60]\, O => skid_buffer(60) ); \m_payload_i[61]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(11), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[61]\, O => skid_buffer(61) ); \m_payload_i[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(6), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[6]\, O => skid_buffer(6) ); \m_payload_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(7), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[7]\, O => skid_buffer(7) ); \m_payload_i[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(8), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[8]\, O => skid_buffer(8) ); \m_payload_i[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(9), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[9]\, O => skid_buffer(9) ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(0), Q => \^q\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(10), Q => \^q\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(11), Q => \^q\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(12), Q => \^q\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(13), Q => \^q\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(14), Q => \^q\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(15), Q => \^q\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(16), Q => \^q\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(17), Q => \^q\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(18), Q => \^q\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(19), Q => \^q\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(1), Q => \^q\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(20), Q => \^q\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(21), Q => \^q\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(22), Q => \^q\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(23), Q => \^q\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(24), Q => \^q\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(25), Q => \^q\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(26), Q => \^q\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(27), Q => \^q\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(28), Q => \^q\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(29), Q => \^q\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(2), Q => \^q\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(30), Q => \^q\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(31), Q => \^q\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(32), Q => \^q\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(33), Q => \^q\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(34), Q => \^q\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(35), Q => \^q\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(36), Q => \^q\(36), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(38), Q => \^q\(37), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(39), Q => \^q\(38), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(3), Q => \^q\(3), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(44), Q => \^q\(39), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(45), Q => \^q\(40), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(46), Q => \^q\(41), R => '0' ); \m_payload_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(47), Q => \^q\(42), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(4), Q => \^q\(4), R => '0' ); \m_payload_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(50), Q => \^q\(43), R => '0' ); \m_payload_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(51), Q => \^q\(44), R => '0' ); \m_payload_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(52), Q => \^q\(45), R => '0' ); \m_payload_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(53), Q => \^q\(46), R => '0' ); \m_payload_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(54), Q => \^q\(47), R => '0' ); \m_payload_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(55), Q => \^q\(48), R => '0' ); \m_payload_i_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(56), Q => \^q\(49), R => '0' ); \m_payload_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(57), Q => \^q\(50), R => '0' ); \m_payload_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(58), Q => \^q\(51), R => '0' ); \m_payload_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(59), Q => \^q\(52), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(5), Q => \^q\(5), R => '0' ); \m_payload_i_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(60), Q => \^q\(53), R => '0' ); \m_payload_i_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(61), Q => \^q\(54), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(6), Q => \^q\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(7), Q => \^q\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(8), Q => \^q\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(9), Q => \^q\(9), R => '0' ); m_valid_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => b_push, I1 => \^m_valid_i_reg_0\, I2 => s_axi_awvalid, I3 => \^s_axi_awready\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^m_valid_i_reg_0\, R => \aresetn_d_reg[1]_inv_0\ ); next_pending_r_i_4: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => \state_reg[1]_rep\, I1 => \^q\(42), I2 => \^q\(40), I3 => \^q\(39), I4 => \^q\(41), O => next_pending_r_reg ); \s_ready_i_i_1__1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \aresetn_d_reg_n_0_[0]\, O => \^s_ready_i_reg_0\ ); s_ready_i_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => s_axi_awvalid, I1 => \^s_axi_awready\, I2 => b_push, I3 => \^m_valid_i_reg_0\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^s_axi_awready\, R => \^s_ready_i_reg_0\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(2), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awsize(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awsize(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awburst(0), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awburst(1), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(0), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(1), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(2), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(3), Q => \skid_buffer_reg_n_0_[47]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(0), Q => \skid_buffer_reg_n_0_[50]\, R => '0' ); \skid_buffer_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(1), Q => \skid_buffer_reg_n_0_[51]\, R => '0' ); \skid_buffer_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(2), Q => \skid_buffer_reg_n_0_[52]\, R => '0' ); \skid_buffer_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(3), Q => \skid_buffer_reg_n_0_[53]\, R => '0' ); \skid_buffer_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(4), Q => \skid_buffer_reg_n_0_[54]\, R => '0' ); \skid_buffer_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(5), Q => \skid_buffer_reg_n_0_[55]\, R => '0' ); \skid_buffer_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(6), Q => \skid_buffer_reg_n_0_[56]\, R => '0' ); \skid_buffer_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(7), Q => \skid_buffer_reg_n_0_[57]\, R => '0' ); \skid_buffer_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(8), Q => \skid_buffer_reg_n_0_[58]\, R => '0' ); \skid_buffer_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(9), Q => \skid_buffer_reg_n_0_[59]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(10), Q => \skid_buffer_reg_n_0_[60]\, R => '0' ); \skid_buffer_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(11), Q => \skid_buffer_reg_n_0_[61]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); \wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(39), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(0) ); \wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"8A888AAA" ) port map ( I0 => \^q\(1), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(40), O => \wrap_boundary_axaddr_r_reg[6]\(1) ); \wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0F553300000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(36), I5 => \^q\(2), O => \wrap_boundary_axaddr_r_reg[6]\(2) ); \wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"020202A2A2A202A2" ) port map ( I0 => \^q\(3), I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\, I2 => \^q\(36), I3 => \^q\(40), I4 => \^q\(35), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(3) ); \wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(41), I1 => \^q\(35), I2 => \^q\(42), O => \wrap_boundary_axaddr_r[3]_i_2_n_0\ ); \wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"503F5F3F00000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(36), I3 => \^q\(35), I4 => \^q\(42), I5 => \^q\(4), O => \wrap_boundary_axaddr_r_reg[6]\(4) ); \wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"2A222AAA" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(41), I3 => \^q\(35), I4 => \^q\(42), O => \wrap_boundary_axaddr_r_reg[6]\(5) ); \wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2AAA" ) port map ( I0 => \^q\(6), I1 => \^q\(42), I2 => \^q\(35), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(6) ); \wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA6AA56AAAAAAAA" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(1), I1 => \wrap_second_len_r_reg[3]_0\(0), I2 => \state_reg[1]_rep\, I3 => \^wrap_cnt_r_reg[2]\, I4 => \^axaddr_offset_r_reg[0]\, I5 => \^wrap_second_len_r_reg[3]\(0), O => D(0) ); \wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(2), I1 => \wrap_second_len_r_reg[1]\, I2 => \^wrap_second_len_r_reg[3]\(1), O => D(1) ); \wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFEAEAFFEA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\, I1 => \^axlen_cnt_reg[3]\, I2 => \axaddr_offset_r[3]_i_2_n_0\, I3 => \^axaddr_offset_r_reg[2]\, I4 => \wrap_cnt_r[3]_i_5_n_0\, I5 => \axaddr_offset_r_reg[2]_1\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \^q\(41), I1 => \state_reg[0]_rep\, I2 => \^m_valid_i_reg_0\, I3 => \state_reg[1]_rep_0\, O => \wrap_cnt_r[3]_i_5_n_0\ ); \wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0001000000010001" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2_n_0\, I4 => \state_reg[1]_rep\, I5 => \axaddr_offset_r_reg[3]\(2), O => \^wrap_cnt_r_reg[2]\ ); \wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F00EFFFFF00E0000" ) port map ( I0 => \^axaddr_offset\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_r_reg[0]\, I3 => \^axaddr_offset\(0), I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(1), O => \^wrap_second_len_r_reg[3]\(0) ); \wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"CCC2FFFFCCC20000" ) port map ( I0 => \^axaddr_offset\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset\(0), I3 => \^axaddr_offset_r_reg[0]\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(2), O => \^wrap_second_len_r_reg[3]\(1) ); \wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FE00FFFFFE00FE00" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2_n_0\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(3), O => \^wrap_second_len_r_reg[3]\(2) ); \wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"A8A8A8080808A808" ) port map ( I0 => \^axlen_cnt_reg[3]\, I1 => \wrap_second_len_r[3]_i_3_n_0\, I2 => \^q\(36), I3 => \^q\(5), I4 => \^q\(35), I5 => \^q\(6), O => \wrap_second_len_r[3]_i_2_n_0\ ); \wrap_second_len_r[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(4), I1 => \^q\(35), I2 => \^q\(3), O => \wrap_second_len_r[3]_i_3_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is port ( s_axi_bvalid : out STD_LOGIC; \skid_buffer_reg[0]_0\ : out STD_LOGIC; \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \aresetn_d_reg[1]_inv\ : in STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; si_rs_bvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\; architecture STRUCTURE of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^s_axi_bvalid\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^skid_buffer_reg[0]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair79"; begin s_axi_bvalid <= \^s_axi_bvalid\; \skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\; \m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \s_bresp_acc_reg[1]\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__1_n_0\ ); \m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__1_n_0\ ); \m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__1_n_0\ ); \m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__1_n_0\ ); \m_payload_i[13]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, O => p_1_in ); \m_payload_i[13]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_2_n_0\ ); \m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \s_bresp_acc_reg[1]\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__1_n_0\ ); \m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__1_n_0\ ); \m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__1_n_0\ ); \m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__1_n_0\ ); \m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__1_n_0\ ); \m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__1_n_0\ ); \m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__1_n_0\ ); \m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__1_n_0\ ); \m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__1_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[0]_i_1__1_n_0\, Q => \s_axi_bid[11]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[10]_i_1__1_n_0\, Q => \s_axi_bid[11]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[11]_i_1__1_n_0\, Q => \s_axi_bid[11]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[12]_i_1__1_n_0\, Q => \s_axi_bid[11]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[13]_i_2_n_0\, Q => \s_axi_bid[11]\(13), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[1]_i_1__1_n_0\, Q => \s_axi_bid[11]\(1), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[2]_i_1__1_n_0\, Q => \s_axi_bid[11]\(2), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[3]_i_1__1_n_0\, Q => \s_axi_bid[11]\(3), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[4]_i_1__1_n_0\, Q => \s_axi_bid[11]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[5]_i_1__1_n_0\, Q => \s_axi_bid[11]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[6]_i_1__1_n_0\, Q => \s_axi_bid[11]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[7]_i_1__1_n_0\, Q => \s_axi_bid[11]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[8]_i_1__1_n_0\, Q => \s_axi_bid[11]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[9]_i_1__1_n_0\, Q => \s_axi_bid[11]\(9), R => '0' ); \m_valid_i_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, I2 => si_rs_bvalid, I3 => \^skid_buffer_reg[0]_0\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^s_axi_bvalid\, R => \aresetn_d_reg[1]_inv\ ); s_ready_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => si_rs_bvalid, I1 => \^skid_buffer_reg[0]_0\, I2 => s_axi_bready, I3 => \^s_axi_bvalid\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^skid_buffer_reg[0]_0\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \s_bresp_acc_reg[1]\(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(8), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(9), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(10), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(11), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \s_bresp_acc_reg[1]\(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(0), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(1), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(2), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(3), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(4), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(5), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(6), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(7), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is port ( s_axi_rvalid : out STD_LOGIC; \skid_buffer_reg[0]_0\ : out STD_LOGIC; \cnt_read_reg[2]_rep__0\ : out STD_LOGIC; \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); \aresetn_d_reg[1]_inv\ : in STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; \cnt_read_reg[4]_rep__0\ : in STD_LOGIC; s_axi_rready : in STD_LOGIC; r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 ); \cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\; architecture STRUCTURE of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC; signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^s_axi_rvalid\ : STD_LOGIC; signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC; signal \^skid_buffer_reg[0]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[4]_i_4\ : label is "soft_lutpair84"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \s_ready_i_i_1__2\ : label is "soft_lutpair84"; begin s_axi_rvalid <= \^s_axi_rvalid\; \skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\; \cnt_read[4]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^skid_buffer_reg[0]_0\, I1 => \cnt_read_reg[4]_rep__0\, O => \cnt_read_reg[2]_rep__0\ ); \m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__2_n_0\ ); \m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__2_n_0\ ); \m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__2_n_0\ ); \m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(12), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__2_n_0\ ); \m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(13), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_1__2_n_0\ ); \m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(14), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[14]\, O => \m_payload_i[14]_i_1__1_n_0\ ); \m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(15), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[15]\, O => \m_payload_i[15]_i_1__1_n_0\ ); \m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(16), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[16]\, O => \m_payload_i[16]_i_1__1_n_0\ ); \m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(17), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[17]\, O => \m_payload_i[17]_i_1__1_n_0\ ); \m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(18), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[18]\, O => \m_payload_i[18]_i_1__1_n_0\ ); \m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(19), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[19]\, O => \m_payload_i[19]_i_1__1_n_0\ ); \m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__2_n_0\ ); \m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(20), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[20]\, O => \m_payload_i[20]_i_1__1_n_0\ ); \m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(21), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[21]\, O => \m_payload_i[21]_i_1__1_n_0\ ); \m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(22), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[22]\, O => \m_payload_i[22]_i_1__1_n_0\ ); \m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(23), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[23]\, O => \m_payload_i[23]_i_1__1_n_0\ ); \m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(24), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[24]\, O => \m_payload_i[24]_i_1__1_n_0\ ); \m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(25), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[25]\, O => \m_payload_i[25]_i_1__1_n_0\ ); \m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(26), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[26]\, O => \m_payload_i[26]_i_1__1_n_0\ ); \m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(27), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[27]\, O => \m_payload_i[27]_i_1__1_n_0\ ); \m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(28), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[28]\, O => \m_payload_i[28]_i_1__1_n_0\ ); \m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(29), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[29]\, O => \m_payload_i[29]_i_1__1_n_0\ ); \m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__2_n_0\ ); \m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(30), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[30]\, O => \m_payload_i[30]_i_1__1_n_0\ ); \m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(31), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[31]\, O => \m_payload_i[31]_i_1__1_n_0\ ); \m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(32), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[32]\, O => \m_payload_i[32]_i_1__1_n_0\ ); \m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(33), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[33]\, O => \m_payload_i[33]_i_1__1_n_0\ ); \m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[34]\, O => \m_payload_i[34]_i_1__1_n_0\ ); \m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[35]\, O => \m_payload_i[35]_i_1__1_n_0\ ); \m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[36]\, O => \m_payload_i[36]_i_1__1_n_0\ ); \m_payload_i[37]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[37]\, O => \m_payload_i[37]_i_1_n_0\ ); \m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[38]\, O => \m_payload_i[38]_i_1__1_n_0\ ); \m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[39]\, O => \m_payload_i[39]_i_1__1_n_0\ ); \m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__2_n_0\ ); \m_payload_i[40]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[40]\, O => \m_payload_i[40]_i_1_n_0\ ); \m_payload_i[41]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[41]\, O => \m_payload_i[41]_i_1_n_0\ ); \m_payload_i[42]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[42]\, O => \m_payload_i[42]_i_1_n_0\ ); \m_payload_i[43]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[43]\, O => \m_payload_i[43]_i_1_n_0\ ); \m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[44]\, O => \m_payload_i[44]_i_1__1_n_0\ ); \m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[45]\, O => \m_payload_i[45]_i_1__1_n_0\ ); \m_payload_i[46]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, O => p_1_in ); \m_payload_i[46]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(12), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[46]\, O => \m_payload_i[46]_i_2_n_0\ ); \m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__2_n_0\ ); \m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__2_n_0\ ); \m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__2_n_0\ ); \m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__2_n_0\ ); \m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__2_n_0\ ); \m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__2_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[0]_i_1__2_n_0\, Q => \s_axi_rid[11]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[10]_i_1__2_n_0\, Q => \s_axi_rid[11]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[11]_i_1__2_n_0\, Q => \s_axi_rid[11]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[12]_i_1__2_n_0\, Q => \s_axi_rid[11]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[13]_i_1__2_n_0\, Q => \s_axi_rid[11]\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[14]_i_1__1_n_0\, Q => \s_axi_rid[11]\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[15]_i_1__1_n_0\, Q => \s_axi_rid[11]\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[16]_i_1__1_n_0\, Q => \s_axi_rid[11]\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[17]_i_1__1_n_0\, Q => \s_axi_rid[11]\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[18]_i_1__1_n_0\, Q => \s_axi_rid[11]\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[19]_i_1__1_n_0\, Q => \s_axi_rid[11]\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[1]_i_1__2_n_0\, Q => \s_axi_rid[11]\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[20]_i_1__1_n_0\, Q => \s_axi_rid[11]\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[21]_i_1__1_n_0\, Q => \s_axi_rid[11]\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[22]_i_1__1_n_0\, Q => \s_axi_rid[11]\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[23]_i_1__1_n_0\, Q => \s_axi_rid[11]\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[24]_i_1__1_n_0\, Q => \s_axi_rid[11]\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[25]_i_1__1_n_0\, Q => \s_axi_rid[11]\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[26]_i_1__1_n_0\, Q => \s_axi_rid[11]\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[27]_i_1__1_n_0\, Q => \s_axi_rid[11]\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[28]_i_1__1_n_0\, Q => \s_axi_rid[11]\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[29]_i_1__1_n_0\, Q => \s_axi_rid[11]\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[2]_i_1__2_n_0\, Q => \s_axi_rid[11]\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[30]_i_1__1_n_0\, Q => \s_axi_rid[11]\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[31]_i_1__1_n_0\, Q => \s_axi_rid[11]\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[32]_i_1__1_n_0\, Q => \s_axi_rid[11]\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[33]_i_1__1_n_0\, Q => \s_axi_rid[11]\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[34]_i_1__1_n_0\, Q => \s_axi_rid[11]\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[35]_i_1__1_n_0\, Q => \s_axi_rid[11]\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[36]_i_1__1_n_0\, Q => \s_axi_rid[11]\(36), R => '0' ); \m_payload_i_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[37]_i_1_n_0\, Q => \s_axi_rid[11]\(37), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[38]_i_1__1_n_0\, Q => \s_axi_rid[11]\(38), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[39]_i_1__1_n_0\, Q => \s_axi_rid[11]\(39), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[3]_i_1__2_n_0\, Q => \s_axi_rid[11]\(3), R => '0' ); \m_payload_i_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[40]_i_1_n_0\, Q => \s_axi_rid[11]\(40), R => '0' ); \m_payload_i_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[41]_i_1_n_0\, Q => \s_axi_rid[11]\(41), R => '0' ); \m_payload_i_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[42]_i_1_n_0\, Q => \s_axi_rid[11]\(42), R => '0' ); \m_payload_i_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[43]_i_1_n_0\, Q => \s_axi_rid[11]\(43), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[44]_i_1__1_n_0\, Q => \s_axi_rid[11]\(44), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[45]_i_1__1_n_0\, Q => \s_axi_rid[11]\(45), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[46]_i_2_n_0\, Q => \s_axi_rid[11]\(46), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[4]_i_1__2_n_0\, Q => \s_axi_rid[11]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[5]_i_1__2_n_0\, Q => \s_axi_rid[11]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[6]_i_1__2_n_0\, Q => \s_axi_rid[11]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[7]_i_1__2_n_0\, Q => \s_axi_rid[11]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[8]_i_1__2_n_0\, Q => \s_axi_rid[11]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[9]_i_1__2_n_0\, Q => \s_axi_rid[11]\(9), R => '0' ); \m_valid_i_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"4FFF" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, I2 => \cnt_read_reg[4]_rep__0\, I3 => \^skid_buffer_reg[0]_0\, O => \m_valid_i_i_1__2_n_0\ ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \m_valid_i_i_1__2_n_0\, Q => \^s_axi_rvalid\, R => \aresetn_d_reg[1]_inv\ ); \s_ready_i_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"F8FF" ) port map ( I0 => \cnt_read_reg[4]_rep__0\, I1 => \^skid_buffer_reg[0]_0\, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, O => \s_ready_i_i_1__2_n_0\ ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \s_ready_i_i_1__2_n_0\, Q => \^skid_buffer_reg[0]_0\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(32), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(33), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(0), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(1), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(2), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(3), Q => \skid_buffer_reg_n_0_[37]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(4), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(5), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(6), Q => \skid_buffer_reg_n_0_[40]\, R => '0' ); \skid_buffer_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(7), Q => \skid_buffer_reg_n_0_[41]\, R => '0' ); \skid_buffer_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(8), Q => \skid_buffer_reg_n_0_[42]\, R => '0' ); \skid_buffer_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(9), Q => \skid_buffer_reg_n_0_[43]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(10), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(11), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(12), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel is port ( si_rs_bvalid : out STD_LOGIC; \cnt_read_reg[0]_rep__0\ : out STD_LOGIC; \cnt_read_reg[1]_rep__0\ : out STD_LOGIC; m_axi_bready : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); \skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); areset_d1 : in STD_LOGIC; aclk : in STD_LOGIC; b_push : in STD_LOGIC; si_rs_bready : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel is signal bid_fifo_0_n_3 : STD_LOGIC; signal bid_fifo_0_n_5 : STD_LOGIC; signal \bresp_cnt[7]_i_6_n_0\ : STD_LOGIC; signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal bresp_push : STD_LOGIC; signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 ); signal mhandshake : STD_LOGIC; signal mhandshake_r : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s_bresp_acc0 : STD_LOGIC; signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC; signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC; signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC; signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC; signal shandshake : STD_LOGIC; signal shandshake_r : STD_LOGIC; signal \^si_rs_bvalid\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair124"; attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair124"; begin si_rs_bvalid <= \^si_rs_bvalid\; bid_fifo_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo port map ( D(0) => bid_fifo_0_n_3, Q(1 downto 0) => cnt_read(1 downto 0), SR(0) => s_bresp_acc0, aclk => aclk, areset_d1 => areset_d1, b_push => b_push, \bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0), bresp_push => bresp_push, bvalid_i_reg => bid_fifo_0_n_5, bvalid_i_reg_0 => \^si_rs_bvalid\, \cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\, \cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0\, \in\(15 downto 0) => \in\(15 downto 0), mhandshake_r => mhandshake_r, \out\(11 downto 0) => \out\(11 downto 0), shandshake_r => shandshake_r, si_rs_bready => si_rs_bready ); \bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \bresp_cnt_reg__0\(0), O => p_0_in(0) ); \bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bresp_cnt_reg__0\(1), I1 => \bresp_cnt_reg__0\(0), O => p_0_in(1) ); \bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \bresp_cnt_reg__0\(2), I1 => \bresp_cnt_reg__0\(0), I2 => \bresp_cnt_reg__0\(1), O => p_0_in(2) ); \bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \bresp_cnt_reg__0\(3), I1 => \bresp_cnt_reg__0\(1), I2 => \bresp_cnt_reg__0\(0), I3 => \bresp_cnt_reg__0\(2), O => p_0_in(3) ); \bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \bresp_cnt_reg__0\(4), I1 => \bresp_cnt_reg__0\(2), I2 => \bresp_cnt_reg__0\(0), I3 => \bresp_cnt_reg__0\(1), I4 => \bresp_cnt_reg__0\(3), O => p_0_in(4) ); \bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => \bresp_cnt_reg__0\(5), I1 => \bresp_cnt_reg__0\(3), I2 => \bresp_cnt_reg__0\(1), I3 => \bresp_cnt_reg__0\(0), I4 => \bresp_cnt_reg__0\(2), I5 => \bresp_cnt_reg__0\(4), O => p_0_in(5) ); \bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bresp_cnt_reg__0\(6), I1 => \bresp_cnt[7]_i_6_n_0\, O => p_0_in(6) ); \bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \bresp_cnt_reg__0\(7), I1 => \bresp_cnt[7]_i_6_n_0\, I2 => \bresp_cnt_reg__0\(6), O => p_0_in(7) ); \bresp_cnt[7]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \bresp_cnt_reg__0\(5), I1 => \bresp_cnt_reg__0\(3), I2 => \bresp_cnt_reg__0\(1), I3 => \bresp_cnt_reg__0\(0), I4 => \bresp_cnt_reg__0\(2), I5 => \bresp_cnt_reg__0\(4), O => \bresp_cnt[7]_i_6_n_0\ ); \bresp_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(0), Q => \bresp_cnt_reg__0\(0), R => s_bresp_acc0 ); \bresp_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(1), Q => \bresp_cnt_reg__0\(1), R => s_bresp_acc0 ); \bresp_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(2), Q => \bresp_cnt_reg__0\(2), R => s_bresp_acc0 ); \bresp_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(3), Q => \bresp_cnt_reg__0\(3), R => s_bresp_acc0 ); \bresp_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(4), Q => \bresp_cnt_reg__0\(4), R => s_bresp_acc0 ); \bresp_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(5), Q => \bresp_cnt_reg__0\(5), R => s_bresp_acc0 ); \bresp_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(6), Q => \bresp_cnt_reg__0\(6), R => s_bresp_acc0 ); \bresp_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(7), Q => \bresp_cnt_reg__0\(7), R => s_bresp_acc0 ); bresp_fifo_0: entity work.\design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ port map ( D(0) => bid_fifo_0_n_3, Q(1 downto 0) => cnt_read(1 downto 0), aclk => aclk, areset_d1 => areset_d1, \in\(1) => \s_bresp_acc_reg_n_0_[1]\, \in\(0) => \s_bresp_acc_reg_n_0_[0]\, m_axi_bready => m_axi_bready, m_axi_bvalid => m_axi_bvalid, mhandshake => mhandshake, mhandshake_r => mhandshake_r, sel => bresp_push, shandshake_r => shandshake_r, \skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0) ); bvalid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => bid_fifo_0_n_5, Q => \^si_rs_bvalid\, R => '0' ); mhandshake_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => mhandshake, Q => mhandshake_r, R => areset_d1 ); \s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000EACEAAAA" ) port map ( I0 => \s_bresp_acc_reg_n_0_[0]\, I1 => m_axi_bresp(0), I2 => m_axi_bresp(1), I3 => \s_bresp_acc_reg_n_0_[1]\, I4 => mhandshake, I5 => s_bresp_acc0, O => \s_bresp_acc[0]_i_1_n_0\ ); \s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"00EC" ) port map ( I0 => m_axi_bresp(1), I1 => \s_bresp_acc_reg_n_0_[1]\, I2 => mhandshake, I3 => s_bresp_acc0, O => \s_bresp_acc[1]_i_1_n_0\ ); \s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \s_bresp_acc[0]_i_1_n_0\, Q => \s_bresp_acc_reg_n_0_[0]\, R => '0' ); \s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \s_bresp_acc[1]_i_1_n_0\, Q => \s_bresp_acc_reg_n_0_[1]\, R => '0' ); shandshake_r_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^si_rs_bvalid\, I1 => si_rs_bready, O => shandshake ); shandshake_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => shandshake, Q => shandshake_r, R => areset_d1 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator is port ( next_pending_r_reg : out STD_LOGIC; wrap_next_pending : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; sel_first_0 : out STD_LOGIC; sel_first : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[2]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); incr_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; sel_first_i : in STD_LOGIC; \m_payload_i_reg[39]\ : in STD_LOGIC; \m_payload_i_reg[39]_0\ : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 19 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_awvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \m_payload_i_reg[47]_1\ : in STD_LOGIC; \next\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[0]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator is signal incr_cmd_0_n_10 : STD_LOGIC; signal incr_cmd_0_n_11 : STD_LOGIC; signal incr_cmd_0_n_12 : STD_LOGIC; signal incr_cmd_0_n_13 : STD_LOGIC; signal incr_cmd_0_n_14 : STD_LOGIC; signal incr_cmd_0_n_15 : STD_LOGIC; signal incr_cmd_0_n_16 : STD_LOGIC; signal incr_cmd_0_n_4 : STD_LOGIC; signal incr_cmd_0_n_5 : STD_LOGIC; signal incr_cmd_0_n_6 : STD_LOGIC; signal incr_cmd_0_n_7 : STD_LOGIC; signal incr_cmd_0_n_8 : STD_LOGIC; signal incr_cmd_0_n_9 : STD_LOGIC; signal s_axburst_eq0 : STD_LOGIC; signal s_axburst_eq1 : STD_LOGIC; begin incr_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd port map ( E(0) => E(0), Q(0) => Q(0), S(3 downto 0) => S(3 downto 0), aclk => aclk, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_incr_reg[0]_0\ => sel_first_0, \axaddr_incr_reg[11]_0\(10) => incr_cmd_0_n_4, \axaddr_incr_reg[11]_0\(9) => incr_cmd_0_n_5, \axaddr_incr_reg[11]_0\(8) => incr_cmd_0_n_6, \axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_7, \axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_8, \axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_9, \axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_10, \axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_11, \axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_12, \axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_13, \axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_14, \axlen_cnt_reg[2]_0\ => \axlen_cnt_reg[2]\, incr_next_pending => incr_next_pending, \m_axi_awaddr[11]\ => incr_cmd_0_n_15, \m_axi_awaddr[5]\ => incr_cmd_0_n_16, \m_payload_i_reg[46]\(9 downto 8) => \m_payload_i_reg[47]\(18 downto 17), \m_payload_i_reg[46]\(7 downto 5) => \m_payload_i_reg[47]\(14 downto 12), \m_payload_i_reg[46]\(4) => \m_payload_i_reg[47]\(5), \m_payload_i_reg[46]\(3 downto 0) => \m_payload_i_reg[47]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \next\ => \next\, next_pending_r_reg_0 => next_pending_r_reg, sel_first_reg_0 => sel_first_reg_1, \state_reg[0]\(0) => \state_reg[0]\(0), \state_reg[0]_rep\ => \state_reg[0]_rep\, \state_reg[1]\(0) => \state_reg[1]_0\(0) ); \memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axburst_eq1, I1 => \m_payload_i_reg[47]\(15), I2 => s_axburst_eq0, O => \state_reg[1]_rep\ ); s_axburst_eq0_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]\, Q => s_axburst_eq0, R => '0' ); s_axburst_eq1_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]_0\, Q => s_axburst_eq1, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_i, Q => sel_first_reg_0, R => '0' ); wrap_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd port map ( D(3 downto 0) => D(3 downto 0), E(0) => E(0), aclk => aclk, \axaddr_incr_reg[11]\(10) => incr_cmd_0_n_4, \axaddr_incr_reg[11]\(9) => incr_cmd_0_n_5, \axaddr_incr_reg[11]\(8) => incr_cmd_0_n_6, \axaddr_incr_reg[11]\(7) => incr_cmd_0_n_7, \axaddr_incr_reg[11]\(6) => incr_cmd_0_n_8, \axaddr_incr_reg[11]\(5) => incr_cmd_0_n_9, \axaddr_incr_reg[11]\(4) => incr_cmd_0_n_10, \axaddr_incr_reg[11]\(3) => incr_cmd_0_n_11, \axaddr_incr_reg[11]\(2) => incr_cmd_0_n_12, \axaddr_incr_reg[11]\(1) => incr_cmd_0_n_13, \axaddr_incr_reg[11]\(0) => incr_cmd_0_n_14, \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), \m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[47]\(19 downto 15), \m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[47]\(13 downto 0), \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_1\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \next\ => \next\, sel_first_reg_0 => sel_first, sel_first_reg_1 => sel_first_reg_2, sel_first_reg_2 => incr_cmd_0_n_15, sel_first_reg_3 => incr_cmd_0_n_16, si_rs_awvalid => si_rs_awvalid, \state_reg[0]\(0) => \state_reg[0]\(0), \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0), \wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is port ( sel_first_reg_0 : out STD_LOGIC; sel_first : out STD_LOGIC; sel_first_reg_1 : out STD_LOGIC; \axlen_cnt_reg[0]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); r_rlast : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_i : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; sel_first_reg_3 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 19 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_arvalid : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[0]_rep_0\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); sel_first_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_17_b2s_cmd_translator"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is signal incr_cmd_0_n_10 : STD_LOGIC; signal incr_cmd_0_n_11 : STD_LOGIC; signal incr_cmd_0_n_12 : STD_LOGIC; signal incr_cmd_0_n_13 : STD_LOGIC; signal incr_cmd_0_n_14 : STD_LOGIC; signal incr_cmd_0_n_15 : STD_LOGIC; signal incr_cmd_0_n_3 : STD_LOGIC; signal incr_cmd_0_n_4 : STD_LOGIC; signal incr_cmd_0_n_5 : STD_LOGIC; signal incr_cmd_0_n_6 : STD_LOGIC; signal incr_cmd_0_n_7 : STD_LOGIC; signal incr_cmd_0_n_8 : STD_LOGIC; signal incr_cmd_0_n_9 : STD_LOGIC; signal incr_next_pending : STD_LOGIC; signal s_axburst_eq0 : STD_LOGIC; signal s_axburst_eq1 : STD_LOGIC; signal wrap_cmd_0_n_6 : STD_LOGIC; signal wrap_cmd_0_n_7 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair17"; begin incr_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 port map ( E(0) => E(0), O(3 downto 0) => O(3 downto 0), Q(10 downto 8) => Q(18 downto 16), Q(7 downto 5) => Q(14 downto 12), Q(4) => Q(5), Q(3 downto 0) => Q(3 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, \axaddr_incr_reg[0]_0\ => sel_first, \axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_3, \axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_4, \axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_5, \axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_6, \axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_7, \axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_8, \axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_9, \axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_10, \axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\, incr_next_pending => incr_next_pending, \m_axi_araddr[11]\ => incr_cmd_0_n_11, \m_axi_araddr[1]\ => incr_cmd_0_n_15, \m_axi_araddr[2]\ => incr_cmd_0_n_14, \m_axi_araddr[3]\ => incr_cmd_0_n_13, \m_axi_araddr[5]\ => incr_cmd_0_n_12, m_axi_arready => m_axi_arready, \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0), m_valid_i_reg(0) => m_valid_i_reg(0), sel_first_reg_0 => sel_first_reg_2, sel_first_reg_1(0) => sel_first_reg_4(0), si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\ => \state_reg[0]_rep_0\, \state_reg[1]\ => \state_reg[1]_0\, \state_reg[1]_0\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\ ); r_rlast_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => s_axburst_eq0, I1 => Q(15), I2 => s_axburst_eq1, O => r_rlast ); s_axburst_eq0_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cmd_0_n_6, Q => s_axburst_eq0, R => '0' ); s_axburst_eq1_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cmd_0_n_7, Q => s_axburst_eq1, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_i, Q => sel_first_reg_0, R => '0' ); \state[1]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axburst_eq1, I1 => Q(15), I2 => s_axburst_eq0, O => \state_reg[0]_rep\ ); wrap_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 port map ( D(3 downto 0) => D(3 downto 0), E(0) => E(0), Q(18 downto 14) => Q(19 downto 15), Q(13 downto 0) => Q(13 downto 0), aclk => aclk, \axaddr_incr_reg[11]\(7) => incr_cmd_0_n_3, \axaddr_incr_reg[11]\(6) => incr_cmd_0_n_4, \axaddr_incr_reg[11]\(5) => incr_cmd_0_n_5, \axaddr_incr_reg[11]\(4) => incr_cmd_0_n_6, \axaddr_incr_reg[11]\(3) => incr_cmd_0_n_7, \axaddr_incr_reg[11]\(2) => incr_cmd_0_n_8, \axaddr_incr_reg[11]\(1) => incr_cmd_0_n_9, \axaddr_incr_reg[11]\(0) => incr_cmd_0_n_10, \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\, incr_next_pending => incr_next_pending, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), m_valid_i_reg(0) => m_valid_i_reg(0), s_axburst_eq0_reg => wrap_cmd_0_n_6, s_axburst_eq1_reg => wrap_cmd_0_n_7, sel_first_i => sel_first_i, sel_first_reg_0 => sel_first_reg_1, sel_first_reg_1 => sel_first_reg_3, sel_first_reg_2 => incr_cmd_0_n_11, sel_first_reg_3 => incr_cmd_0_n_12, sel_first_reg_4 => incr_cmd_0_n_13, sel_first_reg_5 => incr_cmd_0_n_14, sel_first_reg_6 => incr_cmd_0_n_15, si_rs_arvalid => si_rs_arvalid, \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0), \wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel is port ( m_valid_i_reg : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; m_axi_rready : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); \skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); \state_reg[1]_rep_0\ : in STD_LOGIC; aclk : in STD_LOGIC; r_rlast : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; si_rs_rready : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); areset_d1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 11 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel is signal \^m_valid_i_reg\ : STD_LOGIC; signal r_push_r : STD_LOGIC; signal rd_data_fifo_0_n_0 : STD_LOGIC; signal rd_data_fifo_0_n_1 : STD_LOGIC; signal rd_data_fifo_0_n_2 : STD_LOGIC; signal rd_data_fifo_0_n_4 : STD_LOGIC; signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 ); begin m_valid_i_reg <= \^m_valid_i_reg\; \r_arid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => trans_in(1), R => '0' ); \r_arid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(10), Q => trans_in(11), R => '0' ); \r_arid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(11), Q => trans_in(12), R => '0' ); \r_arid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => trans_in(2), R => '0' ); \r_arid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => trans_in(3), R => '0' ); \r_arid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => trans_in(4), R => '0' ); \r_arid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(4), Q => trans_in(5), R => '0' ); \r_arid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(5), Q => trans_in(6), R => '0' ); \r_arid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(6), Q => trans_in(7), R => '0' ); \r_arid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(7), Q => trans_in(8), R => '0' ); \r_arid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(8), Q => trans_in(9), R => '0' ); \r_arid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(9), Q => trans_in(10), R => '0' ); r_push_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \state_reg[1]_rep_0\, Q => r_push_r, R => '0' ); r_rlast_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => r_rlast, Q => trans_in(0), R => '0' ); rd_data_fifo_0: entity work.\design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ port map ( aclk => aclk, areset_d1 => areset_d1, \cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\, \cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_0, \cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_1, \cnt_read_reg[4]_rep__2_2\ => rd_data_fifo_0_n_2, \in\(33 downto 0) => \in\(33 downto 0), m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, \out\(33 downto 0) => \out\(33 downto 0), s_ready_i_reg => s_ready_i_reg, si_rs_rready => si_rs_rready, \state_reg[1]_rep\ => rd_data_fifo_0_n_4 ); transaction_fifo_0: entity work.\design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ port map ( aclk => aclk, areset_d1 => areset_d1, \cnt_read_reg[0]_rep__3\ => rd_data_fifo_0_n_2, \cnt_read_reg[0]_rep__3_0\ => rd_data_fifo_0_n_4, \cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0, \cnt_read_reg[4]_rep__2\ => rd_data_fifo_0_n_1, \in\(12 downto 0) => trans_in(12 downto 0), m_valid_i_reg => \^m_valid_i_reg\, r_push_r => r_push_r, s_ready_i_reg => s_ready_i_reg, si_rs_rready => si_rs_rready, \skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice is port ( s_axi_awready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; si_rs_awvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; si_rs_bready : out STD_LOGIC; si_rs_arvalid : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; si_rs_rready : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); \axlen_cnt_reg[3]_0\ : out STD_LOGIC; \s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 54 downto 0 ); axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); O : out STD_LOGIC_VECTOR ( 3 downto 0 ); D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]_0\ : out STD_LOGIC; axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : out STD_LOGIC; next_pending_r_reg_0 : out STD_LOGIC; \cnt_read_reg[2]_rep__0\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); aclk : in STD_LOGIC; s_ready_i0 : in STD_LOGIC; m_valid_i0 : in STD_LOGIC; aresetn : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \cnt_read_reg[4]_rep__0\ : in STD_LOGIC; s_axi_rready : in STD_LOGIC; S : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_2\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; b_push : in STD_LOGIC; \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep_1\ : in STD_LOGIC; \wrap_second_len_r_reg[1]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_4\ : in STD_LOGIC; \state_reg[0]_rep_0\ : in STD_LOGIC; \state_reg[1]_rep_2\ : in STD_LOGIC; si_rs_bvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 ); \cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice; architecture STRUCTURE of design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice is signal \ar.ar_pipe_n_2\ : STD_LOGIC; signal \aw.aw_pipe_n_1\ : STD_LOGIC; signal \aw.aw_pipe_n_90\ : STD_LOGIC; begin \ar.ar_pipe\: entity work.design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice port map ( O(3 downto 0) => O(3 downto 0), Q(54 downto 0) => \s_arid_r_reg[11]\(54 downto 0), aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[0]_0\ => \aw.aw_pipe_n_90\, \axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), \axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), axaddr_offset_0(1 downto 0) => axaddr_offset_0(2 downto 1), \axaddr_offset_r_reg[0]\ => axaddr_offset_0(0), \axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]_0\, \axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_3\(0), \axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_4\, \axaddr_offset_r_reg[3]\ => si_rs_arvalid, \axaddr_offset_r_reg[3]_0\(2 downto 0) => \axaddr_offset_r_reg[3]_1\(2 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_2\, \axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\, \m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), m_valid_i0 => m_valid_i0, m_valid_i_reg_0 => \ar.ar_pipe_n_2\, m_valid_i_reg_1(0) => m_valid_i_reg(0), next_pending_r_reg => next_pending_r_reg_0, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_ready_i0 => s_ready_i0, \state_reg[0]_rep\ => \state_reg[0]_rep_0\, \state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep_1\, \state_reg[1]_rep_0\ => \state_reg[1]_rep_2\, \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0), \wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]_0\, \wrap_cnt_r_reg[3]\(1 downto 0) => \wrap_cnt_r_reg[3]_0\(1 downto 0), \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, \wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]_0\, \wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_2\(3 downto 0) ); \aw.aw_pipe\: entity work.design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 port map ( D(1 downto 0) => D(1 downto 0), E(0) => E(0), Q(54 downto 0) => Q(54 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, aresetn => aresetn, \aresetn_d_reg[1]_inv\ => \aw.aw_pipe_n_90\, \aresetn_d_reg[1]_inv_0\ => \ar.ar_pipe_n_2\, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), axaddr_offset(1 downto 0) => axaddr_offset(2 downto 1), \axaddr_offset_r_reg[0]\ => axaddr_offset(0), \axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]\, \axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_1\(0), \axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_2\, \axaddr_offset_r_reg[3]\(2 downto 0) => \axaddr_offset_r_reg[3]\(2 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\, b_push => b_push, m_valid_i_reg_0 => si_rs_awvalid, next_pending_r_reg => next_pending_r_reg, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, s_ready_i_reg_0 => \aw.aw_pipe_n_1\, \state_reg[0]_rep\ => \state_reg[0]_rep\, \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\, \state_reg[1]_rep_0\ => \state_reg[1]_rep_0\, \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0), \wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]\, \wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0) ); \b.b_pipe\: entity work.\design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ port map ( aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\, \out\(11 downto 0) => \out\(11 downto 0), \s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0), si_rs_bvalid => si_rs_bvalid, \skid_buffer_reg[0]_0\ => si_rs_bready ); \r.r_pipe\: entity work.\design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ port map ( aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\, \cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\, \cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0), \cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\, r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0), \s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, \skid_buffer_reg[0]_0\ => si_rs_rready ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel is port ( \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC; \m_payload_i_reg[0]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; m_valid_i0 : out STD_LOGIC; s_ready_i0 : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); r_rlast : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arready : in STD_LOGIC; si_rs_arvalid : in STD_LOGIC; \cnt_read_reg[2]_rep__0\ : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; areset_d1 : in STD_LOGIC; \m_payload_i_reg[5]\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel is signal ar_cmd_fsm_0_n_0 : STD_LOGIC; signal ar_cmd_fsm_0_n_10 : STD_LOGIC; signal ar_cmd_fsm_0_n_16 : STD_LOGIC; signal ar_cmd_fsm_0_n_6 : STD_LOGIC; signal ar_cmd_fsm_0_n_8 : STD_LOGIC; signal ar_cmd_fsm_0_n_9 : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal cmd_translator_0_n_0 : STD_LOGIC; signal cmd_translator_0_n_10 : STD_LOGIC; signal cmd_translator_0_n_2 : STD_LOGIC; signal cmd_translator_0_n_3 : STD_LOGIC; signal \incr_cmd_0/sel_first\ : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal \^r_push_r_reg\ : STD_LOGIC; signal sel_first_i : STD_LOGIC; signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC; signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 ); begin \axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0); \axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0); \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; r_push_r_reg <= \^r_push_r_reg\; \state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0); \wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\; \wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0); ar_cmd_fsm_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm port map ( D(0) => ar_cmd_fsm_0_n_6, E(0) => ar_cmd_fsm_0_n_8, Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), aclk => aclk, areset_d1 => areset_d1, \axaddr_incr_reg[0]\(0) => ar_cmd_fsm_0_n_16, axaddr_offset(0) => axaddr_offset(0), \axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0), \axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2), \axlen_cnt_reg[7]\ => ar_cmd_fsm_0_n_0, \axlen_cnt_reg[7]_0\ => cmd_translator_0_n_3, \cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\, m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, \m_payload_i_reg[0]\ => \m_payload_i_reg[0]\, \m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]_0\, \m_payload_i_reg[0]_1\(0) => E(0), \m_payload_i_reg[46]\(0) => Q(18), \m_payload_i_reg[5]\ => \m_payload_i_reg[5]\, m_valid_i0 => m_valid_i0, r_push_r_reg => \^r_push_r_reg\, s_axburst_eq1_reg => cmd_translator_0_n_10, s_axi_arvalid => s_axi_arvalid, s_ready_i0 => s_ready_i0, s_ready_i_reg => s_ready_i_reg, sel_first => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg => ar_cmd_fsm_0_n_9, sel_first_reg_0 => ar_cmd_fsm_0_n_10, sel_first_reg_1 => cmd_translator_0_n_2, sel_first_reg_2 => cmd_translator_0_n_0, si_rs_arvalid => si_rs_arvalid, \wrap_boundary_axaddr_r_reg[11]\(0) => \^wrap_boundary_axaddr_r_reg[11]\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, \wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0) ); cmd_translator_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 port map ( D(3) => axaddr_offset(2), D(2) => \^axaddr_offset_r_reg[2]\(0), D(1 downto 0) => axaddr_offset(1 downto 0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, O(3 downto 0) => O(3 downto 0), Q(19 downto 0) => Q(19 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, \axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\, \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[0]\ => cmd_translator_0_n_3, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), m_axi_arready => m_axi_arready, \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0), m_valid_i_reg(0) => ar_cmd_fsm_0_n_8, r_rlast => r_rlast, sel_first => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg_0 => cmd_translator_0_n_0, sel_first_reg_1 => cmd_translator_0_n_2, sel_first_reg_2 => ar_cmd_fsm_0_n_10, sel_first_reg_3 => ar_cmd_fsm_0_n_9, sel_first_reg_4(0) => ar_cmd_fsm_0_n_16, si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\ => cmd_translator_0_n_10, \state_reg[0]_rep_0\ => \^m_payload_i_reg[0]_0\, \state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), \state_reg[1]_0\ => ar_cmd_fsm_0_n_0, \state_reg[1]_rep\ => \^r_push_r_reg\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 1) => D(2 downto 0), \wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[3]_1\(2 downto 1) => \wrap_second_len_r_reg[3]_0\(1 downto 0), \wrap_second_len_r_reg[3]_1\(0) => ar_cmd_fsm_0_n_6 ); \s_arid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(20), Q => \r_arid_r_reg[11]\(0), R => '0' ); \s_arid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(30), Q => \r_arid_r_reg[11]\(10), R => '0' ); \s_arid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(31), Q => \r_arid_r_reg[11]\(11), R => '0' ); \s_arid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(21), Q => \r_arid_r_reg[11]\(1), R => '0' ); \s_arid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(22), Q => \r_arid_r_reg[11]\(2), R => '0' ); \s_arid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(23), Q => \r_arid_r_reg[11]\(3), R => '0' ); \s_arid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(24), Q => \r_arid_r_reg[11]\(4), R => '0' ); \s_arid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(25), Q => \r_arid_r_reg[11]\(5), R => '0' ); \s_arid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(26), Q => \r_arid_r_reg[11]\(6), R => '0' ); \s_arid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(27), Q => \r_arid_r_reg[11]\(7), R => '0' ); \s_arid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(28), Q => \r_arid_r_reg[11]\(8), R => '0' ); \s_arid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(29), Q => \r_arid_r_reg[11]\(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel is port ( \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \axlen_cnt_reg[7]\ : out STD_LOGIC; \axlen_cnt_reg[7]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); b_push : out STD_LOGIC; m_axi_awvalid : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \in\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); si_rs_awvalid : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; \cnt_read_reg[0]_rep__0\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 1 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \m_payload_i_reg[47]_0\ : in STD_LOGIC; areset_d1 : in STD_LOGIC; \m_payload_i_reg[5]\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel is signal aw_cmd_fsm_0_n_12 : STD_LOGIC; signal aw_cmd_fsm_0_n_14 : STD_LOGIC; signal aw_cmd_fsm_0_n_15 : STD_LOGIC; signal aw_cmd_fsm_0_n_16 : STD_LOGIC; signal aw_cmd_fsm_0_n_2 : STD_LOGIC; signal aw_cmd_fsm_0_n_8 : STD_LOGIC; signal aw_cmd_fsm_0_n_9 : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal cmd_translator_0_n_0 : STD_LOGIC; signal cmd_translator_0_n_12 : STD_LOGIC; signal cmd_translator_0_n_2 : STD_LOGIC; signal cmd_translator_0_n_5 : STD_LOGIC; signal cmd_translator_0_n_6 : STD_LOGIC; signal \incr_cmd_0/sel_first\ : STD_LOGIC; signal incr_next_pending : STD_LOGIC; signal \next\ : STD_LOGIC; signal sel_first : STD_LOGIC; signal sel_first_i : STD_LOGIC; signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC; signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 0 to 0 ); signal wrap_next_pending : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 ); begin \axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0); \axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0); \state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0); \wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\; \wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0); aw_cmd_fsm_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm port map ( D(0) => wrap_cnt(0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), aclk => aclk, areset_d1 => areset_d1, axaddr_offset(0) => axaddr_offset(0), \axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0), \axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_wrap_reg[11]\(0) => aw_cmd_fsm_0_n_14, \axlen_cnt_reg[0]\(0) => aw_cmd_fsm_0_n_8, \axlen_cnt_reg[0]_0\(0) => cmd_translator_0_n_5, \axlen_cnt_reg[7]\ => \axlen_cnt_reg[7]\, \axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]_0\, \axlen_cnt_reg[7]_1\ => aw_cmd_fsm_0_n_2, \axlen_cnt_reg[7]_2\ => cmd_translator_0_n_6, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\, \cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\, incr_next_pending => incr_next_pending, m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, \m_payload_i_reg[0]\(0) => E(0), \m_payload_i_reg[46]\(2) => Q(18), \m_payload_i_reg[46]\(1 downto 0) => Q(16 downto 15), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[5]\ => \m_payload_i_reg[5]\, \next\ => \next\, next_pending_r_reg => cmd_translator_0_n_0, s_axburst_eq0_reg => aw_cmd_fsm_0_n_9, s_axburst_eq1_reg => aw_cmd_fsm_0_n_12, s_axburst_eq1_reg_0 => cmd_translator_0_n_12, sel_first => sel_first, sel_first_0 => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg => aw_cmd_fsm_0_n_15, sel_first_reg_0 => aw_cmd_fsm_0_n_16, sel_first_reg_1 => cmd_translator_0_n_2, si_rs_awvalid => si_rs_awvalid, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0) ); cmd_translator_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator port map ( D(3) => axaddr_offset(2), D(2) => \^axaddr_offset_r_reg[2]\(0), D(1 downto 0) => axaddr_offset(1 downto 0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, Q(0) => cmd_translator_0_n_5, S(3 downto 0) => S(3 downto 0), aclk => aclk, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\, \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[2]\ => cmd_translator_0_n_6, incr_next_pending => incr_next_pending, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), \m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_9, \m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_12, \m_payload_i_reg[47]\(19 downto 0) => Q(19 downto 0), \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_1\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \next\ => \next\, next_pending_r_reg => cmd_translator_0_n_0, sel_first => sel_first, sel_first_0 => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg_0 => cmd_translator_0_n_2, sel_first_reg_1 => aw_cmd_fsm_0_n_16, sel_first_reg_2 => aw_cmd_fsm_0_n_15, si_rs_awvalid => si_rs_awvalid, \state_reg[0]\(0) => aw_cmd_fsm_0_n_14, \state_reg[0]_rep\ => aw_cmd_fsm_0_n_2, \state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), \state_reg[1]_0\(0) => aw_cmd_fsm_0_n_8, \state_reg[1]_rep\ => cmd_translator_0_n_12, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_0\(2 downto 1) => D(1 downto 0), \wrap_second_len_r_reg[3]_0\(0) => wrap_cnt(0), \wrap_second_len_r_reg[3]_1\(3 downto 1) => \wrap_second_len_r_reg[3]_0\(2 downto 0), \wrap_second_len_r_reg[3]_1\(0) => \wrap_cmd_0/wrap_second_len\(0) ); \s_awid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(20), Q => \in\(4), R => '0' ); \s_awid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(30), Q => \in\(14), R => '0' ); \s_awid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(31), Q => \in\(15), R => '0' ); \s_awid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(21), Q => \in\(5), R => '0' ); \s_awid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(22), Q => \in\(6), R => '0' ); \s_awid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(23), Q => \in\(7), R => '0' ); \s_awid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(24), Q => \in\(8), R => '0' ); \s_awid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(25), Q => \in\(9), R => '0' ); \s_awid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(26), Q => \in\(10), R => '0' ); \s_awid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(27), Q => \in\(11), R => '0' ); \s_awid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(28), Q => \in\(12), R => '0' ); \s_awid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(29), Q => \in\(13), R => '0' ); \s_awlen_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(16), Q => \in\(0), R => '0' ); \s_awlen_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(17), Q => \in\(1), R => '0' ); \s_awlen_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(18), Q => \in\(2), R => '0' ); \s_awlen_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(19), Q => \in\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s is port ( s_axi_rvalid : out STD_LOGIC; s_axi_awready : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 22 downto 0 ); s_axi_arready : out STD_LOGIC; \m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 ); s_axi_bvalid : out STD_LOGIC; \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; m_axi_rready : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awready : in STD_LOGIC; m_axi_arready : in STD_LOGIC; s_axi_rready : in STD_LOGIC; aclk : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awvalid : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; aresetn : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s is signal \RD.ar_channel_0_n_0\ : STD_LOGIC; signal \RD.ar_channel_0_n_10\ : STD_LOGIC; signal \RD.ar_channel_0_n_11\ : STD_LOGIC; signal \RD.ar_channel_0_n_16\ : STD_LOGIC; signal \RD.ar_channel_0_n_3\ : STD_LOGIC; signal \RD.ar_channel_0_n_4\ : STD_LOGIC; signal \RD.ar_channel_0_n_46\ : STD_LOGIC; signal \RD.ar_channel_0_n_47\ : STD_LOGIC; signal \RD.ar_channel_0_n_48\ : STD_LOGIC; signal \RD.ar_channel_0_n_49\ : STD_LOGIC; signal \RD.ar_channel_0_n_5\ : STD_LOGIC; signal \RD.r_channel_0_n_0\ : STD_LOGIC; signal \RD.r_channel_0_n_1\ : STD_LOGIC; signal SI_REG_n_132 : STD_LOGIC; signal SI_REG_n_133 : STD_LOGIC; signal SI_REG_n_134 : STD_LOGIC; signal SI_REG_n_135 : STD_LOGIC; signal SI_REG_n_136 : STD_LOGIC; signal SI_REG_n_137 : STD_LOGIC; signal SI_REG_n_138 : STD_LOGIC; signal SI_REG_n_139 : STD_LOGIC; signal SI_REG_n_140 : STD_LOGIC; signal SI_REG_n_141 : STD_LOGIC; signal SI_REG_n_142 : STD_LOGIC; signal SI_REG_n_143 : STD_LOGIC; signal SI_REG_n_149 : STD_LOGIC; signal SI_REG_n_153 : STD_LOGIC; signal SI_REG_n_154 : STD_LOGIC; signal SI_REG_n_155 : STD_LOGIC; signal SI_REG_n_156 : STD_LOGIC; signal SI_REG_n_157 : STD_LOGIC; signal SI_REG_n_161 : STD_LOGIC; signal SI_REG_n_165 : STD_LOGIC; signal SI_REG_n_166 : STD_LOGIC; signal SI_REG_n_167 : STD_LOGIC; signal SI_REG_n_168 : STD_LOGIC; signal SI_REG_n_169 : STD_LOGIC; signal SI_REG_n_170 : STD_LOGIC; signal SI_REG_n_171 : STD_LOGIC; signal SI_REG_n_172 : STD_LOGIC; signal SI_REG_n_173 : STD_LOGIC; signal SI_REG_n_174 : STD_LOGIC; signal SI_REG_n_175 : STD_LOGIC; signal SI_REG_n_176 : STD_LOGIC; signal SI_REG_n_177 : STD_LOGIC; signal SI_REG_n_178 : STD_LOGIC; signal SI_REG_n_179 : STD_LOGIC; signal SI_REG_n_180 : STD_LOGIC; signal SI_REG_n_181 : STD_LOGIC; signal SI_REG_n_182 : STD_LOGIC; signal SI_REG_n_26 : STD_LOGIC; signal SI_REG_n_64 : STD_LOGIC; signal SI_REG_n_8 : STD_LOGIC; signal SI_REG_n_82 : STD_LOGIC; signal \WR.aw_channel_0_n_0\ : STD_LOGIC; signal \WR.aw_channel_0_n_10\ : STD_LOGIC; signal \WR.aw_channel_0_n_15\ : STD_LOGIC; signal \WR.aw_channel_0_n_3\ : STD_LOGIC; signal \WR.aw_channel_0_n_4\ : STD_LOGIC; signal \WR.aw_channel_0_n_47\ : STD_LOGIC; signal \WR.aw_channel_0_n_48\ : STD_LOGIC; signal \WR.aw_channel_0_n_49\ : STD_LOGIC; signal \WR.aw_channel_0_n_50\ : STD_LOGIC; signal \WR.aw_channel_0_n_9\ : STD_LOGIC; signal \WR.b_channel_0_n_1\ : STD_LOGIC; signal \WR.b_channel_0_n_2\ : STD_LOGIC; signal \ar.ar_pipe/m_valid_i0\ : STD_LOGIC; signal \ar.ar_pipe/p_1_in\ : STD_LOGIC; signal \ar.ar_pipe/s_ready_i0\ : STD_LOGIC; signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal areset_d1 : STD_LOGIC; signal areset_d1_i_1_n_0 : STD_LOGIC; signal \aw.aw_pipe/p_1_in\ : STD_LOGIC; signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axaddr_incr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal b_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal b_push : STD_LOGIC; signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal r_rlast : STD_LOGIC; signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \^s_axi_arready\ : STD_LOGIC; signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 ); signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_arvalid : STD_LOGIC; signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 ); signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_awvalid : STD_LOGIC; signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_bready : STD_LOGIC; signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_bvalid : STD_LOGIC; signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 ); signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_rlast : STD_LOGIC; signal si_rs_rready : STD_LOGIC; signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 2 ); begin s_axi_arready <= \^s_axi_arready\; \RD.ar_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel port map ( D(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1), E(0) => \ar.ar_pipe/p_1_in\, O(3) => SI_REG_n_140, O(2) => SI_REG_n_141, O(1) => SI_REG_n_142, O(0) => SI_REG_n_143, Q(31 downto 20) => s_arid(11 downto 0), Q(19 downto 16) => si_rs_arlen(3 downto 0), Q(15) => si_rs_arburst(1), Q(14) => SI_REG_n_82, Q(13 downto 12) => si_rs_arsize(1 downto 0), Q(11 downto 0) => si_rs_araddr(11 downto 0), S(3) => \RD.ar_channel_0_n_46\, S(2) => \RD.ar_channel_0_n_47\, S(1) => \RD.ar_channel_0_n_48\, S(0) => \RD.ar_channel_0_n_49\, aclk => aclk, areset_d1 => areset_d1, axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0), \axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2), \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => SI_REG_n_161, \axaddr_offset_r_reg[3]_1\ => SI_REG_n_165, \cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_1\, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, \m_payload_i_reg[0]\ => \RD.ar_channel_0_n_4\, \m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_5\, \m_payload_i_reg[3]\(3) => SI_REG_n_132, \m_payload_i_reg[3]\(2) => SI_REG_n_133, \m_payload_i_reg[3]\(1) => SI_REG_n_134, \m_payload_i_reg[3]\(0) => SI_REG_n_135, \m_payload_i_reg[47]\ => SI_REG_n_64, \m_payload_i_reg[47]_0\ => SI_REG_n_167, \m_payload_i_reg[5]\ => SI_REG_n_166, \m_payload_i_reg[6]\(6) => SI_REG_n_176, \m_payload_i_reg[6]\(5) => SI_REG_n_177, \m_payload_i_reg[6]\(4) => SI_REG_n_178, \m_payload_i_reg[6]\(3) => SI_REG_n_179, \m_payload_i_reg[6]\(2) => SI_REG_n_180, \m_payload_i_reg[6]\(1) => SI_REG_n_181, \m_payload_i_reg[6]\(0) => SI_REG_n_182, \m_payload_i_reg[7]\(3) => SI_REG_n_136, \m_payload_i_reg[7]\(2) => SI_REG_n_137, \m_payload_i_reg[7]\(1) => SI_REG_n_138, \m_payload_i_reg[7]\(0) => SI_REG_n_139, m_valid_i0 => \ar.ar_pipe/m_valid_i0\, \r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0), r_push_r_reg => \RD.ar_channel_0_n_3\, r_rlast => r_rlast, s_axi_arvalid => s_axi_arvalid, s_ready_i0 => \ar.ar_pipe/s_ready_i0\, s_ready_i_reg => \^s_axi_arready\, si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0), \wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_0\, \wrap_cnt_r_reg[3]\ => \RD.ar_channel_0_n_10\, \wrap_cnt_r_reg[3]_0\ => \RD.ar_channel_0_n_11\, \wrap_cnt_r_reg[3]_1\ => \RD.ar_channel_0_n_16\, \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0), \wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_156, \wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_157 ); \RD.r_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel port map ( D(11 downto 0) => s_arid_r(11 downto 0), aclk => aclk, areset_d1 => areset_d1, \in\(33 downto 0) => \in\(33 downto 0), m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, m_valid_i_reg => \RD.r_channel_0_n_0\, \out\(33 downto 32) => si_rs_rresp(1 downto 0), \out\(31 downto 0) => si_rs_rdata(31 downto 0), r_rlast => r_rlast, s_ready_i_reg => SI_REG_n_168, si_rs_rready => si_rs_rready, \skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0), \skid_buffer_reg[46]\(0) => si_rs_rlast, \state_reg[1]_rep\ => \RD.r_channel_0_n_1\, \state_reg[1]_rep_0\ => \RD.ar_channel_0_n_3\ ); SI_REG: entity work.design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice port map ( D(1 downto 0) => wrap_cnt(3 downto 2), E(0) => \aw.aw_pipe/p_1_in\, O(3) => SI_REG_n_140, O(2) => SI_REG_n_141, O(1) => SI_REG_n_142, O(0) => SI_REG_n_143, Q(54 downto 43) => s_awid(11 downto 0), Q(42 downto 39) => si_rs_awlen(3 downto 0), Q(38) => si_rs_awburst(1), Q(37) => SI_REG_n_26, Q(36 downto 35) => si_rs_awsize(1 downto 0), Q(34 downto 12) => Q(22 downto 0), Q(11 downto 0) => si_rs_awaddr(11 downto 0), S(3) => \WR.aw_channel_0_n_47\, S(2) => \WR.aw_channel_0_n_48\, S(1) => \WR.aw_channel_0_n_49\, S(0) => \WR.aw_channel_0_n_50\, aclk => aclk, aresetn => aresetn, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_incr_reg[3]\(3) => SI_REG_n_132, \axaddr_incr_reg[3]\(2) => SI_REG_n_133, \axaddr_incr_reg[3]\(1) => SI_REG_n_134, \axaddr_incr_reg[3]\(0) => SI_REG_n_135, \axaddr_incr_reg[7]\(3) => SI_REG_n_136, \axaddr_incr_reg[7]\(2) => SI_REG_n_137, \axaddr_incr_reg[7]\(1) => SI_REG_n_138, \axaddr_incr_reg[7]\(0) => SI_REG_n_139, axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0), axaddr_offset_0(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3), axaddr_offset_0(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0), \axaddr_offset_r_reg[2]\ => SI_REG_n_154, \axaddr_offset_r_reg[2]_0\ => SI_REG_n_166, \axaddr_offset_r_reg[2]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2), \axaddr_offset_r_reg[2]_2\ => \WR.aw_channel_0_n_15\, \axaddr_offset_r_reg[2]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2), \axaddr_offset_r_reg[2]_4\ => \RD.ar_channel_0_n_16\, \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \WR.aw_channel_0_n_10\, \axaddr_offset_r_reg[3]_1\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3), \axaddr_offset_r_reg[3]_1\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0), \axaddr_offset_r_reg[3]_2\ => \RD.ar_channel_0_n_11\, \axlen_cnt_reg[3]\ => SI_REG_n_8, \axlen_cnt_reg[3]_0\ => SI_REG_n_64, b_push => b_push, \cnt_read_reg[2]_rep__0\ => SI_REG_n_168, \cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0), \cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0), \cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_0\, \m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_46\, \m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_47\, \m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_48\, \m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_49\, m_valid_i0 => \ar.ar_pipe/m_valid_i0\, m_valid_i_reg(0) => \ar.ar_pipe/p_1_in\, next_pending_r_reg => SI_REG_n_155, next_pending_r_reg_0 => SI_REG_n_167, \out\(11 downto 0) => si_rs_bid(11 downto 0), r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0), r_push_r_reg(0) => si_rs_rlast, \s_arid_r_reg[11]\(54 downto 43) => s_arid(11 downto 0), \s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0), \s_arid_r_reg[11]\(38) => si_rs_arburst(1), \s_arid_r_reg[11]\(37) => SI_REG_n_82, \s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0), \s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0), \s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0), s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => \^s_axi_arready\, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, \s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, \s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0), s_ready_i0 => \ar.ar_pipe/s_ready_i0\, si_rs_arvalid => si_rs_arvalid, si_rs_awvalid => si_rs_awvalid, si_rs_bready => si_rs_bready, si_rs_bvalid => si_rs_bvalid, si_rs_rready => si_rs_rready, \state_reg[0]_rep\ => \WR.aw_channel_0_n_4\, \state_reg[0]_rep_0\ => \RD.ar_channel_0_n_5\, \state_reg[1]\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0), \state_reg[1]_0\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0), \state_reg[1]_rep\ => \WR.aw_channel_0_n_0\, \state_reg[1]_rep_0\ => \WR.aw_channel_0_n_3\, \state_reg[1]_rep_1\ => \RD.ar_channel_0_n_0\, \state_reg[1]_rep_2\ => \RD.ar_channel_0_n_4\, \wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_169, \wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_170, \wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_171, \wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_172, \wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_173, \wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_174, \wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_175, \wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_176, \wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_177, \wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_178, \wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_179, \wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_180, \wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_181, \wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_182, \wrap_cnt_r_reg[2]\ => SI_REG_n_149, \wrap_cnt_r_reg[2]_0\ => SI_REG_n_161, \wrap_cnt_r_reg[3]\ => SI_REG_n_153, \wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_156, \wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_157, \wrap_cnt_r_reg[3]_1\ => SI_REG_n_165, \wrap_second_len_r_reg[1]\ => \WR.aw_channel_0_n_9\, \wrap_second_len_r_reg[1]_0\ => \RD.ar_channel_0_n_10\, \wrap_second_len_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1), \wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0), \wrap_second_len_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0) ); \WR.aw_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel port map ( D(1 downto 0) => wrap_cnt(3 downto 2), E(0) => \aw.aw_pipe/p_1_in\, Q(31 downto 20) => s_awid(11 downto 0), Q(19 downto 16) => si_rs_awlen(3 downto 0), Q(15) => si_rs_awburst(1), Q(14) => SI_REG_n_26, Q(13 downto 12) => si_rs_awsize(1 downto 0), Q(11 downto 0) => si_rs_awaddr(11 downto 0), S(3) => \WR.aw_channel_0_n_47\, S(2) => \WR.aw_channel_0_n_48\, S(1) => \WR.aw_channel_0_n_49\, S(0) => \WR.aw_channel_0_n_50\, aclk => aclk, areset_d1 => areset_d1, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0), \axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2), \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => SI_REG_n_149, \axaddr_offset_r_reg[3]_1\ => SI_REG_n_153, \axlen_cnt_reg[7]\ => \WR.aw_channel_0_n_3\, \axlen_cnt_reg[7]_0\ => \WR.aw_channel_0_n_4\, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\, \cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\, \in\(15 downto 4) => b_awid(11 downto 0), \in\(3 downto 0) => b_awlen(3 downto 0), m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, \m_payload_i_reg[47]\ => SI_REG_n_8, \m_payload_i_reg[47]_0\ => SI_REG_n_155, \m_payload_i_reg[5]\ => SI_REG_n_154, \m_payload_i_reg[6]\(6) => SI_REG_n_169, \m_payload_i_reg[6]\(5) => SI_REG_n_170, \m_payload_i_reg[6]\(4) => SI_REG_n_171, \m_payload_i_reg[6]\(3) => SI_REG_n_172, \m_payload_i_reg[6]\(2) => SI_REG_n_173, \m_payload_i_reg[6]\(1) => SI_REG_n_174, \m_payload_i_reg[6]\(0) => SI_REG_n_175, si_rs_awvalid => si_rs_awvalid, \state_reg[0]_rep\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0), \wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_0\, \wrap_cnt_r_reg[3]\ => \WR.aw_channel_0_n_9\, \wrap_cnt_r_reg[3]_0\ => \WR.aw_channel_0_n_10\, \wrap_cnt_r_reg[3]_1\ => \WR.aw_channel_0_n_15\, \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0), \wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1) ); \WR.b_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel port map ( aclk => aclk, areset_d1 => areset_d1, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\, \cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\, \in\(15 downto 4) => b_awid(11 downto 0), \in\(3 downto 0) => b_awlen(3 downto 0), m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_bvalid => m_axi_bvalid, \out\(11 downto 0) => si_rs_bid(11 downto 0), si_rs_bready => si_rs_bready, si_rs_bvalid => si_rs_bvalid, \skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0) ); areset_d1_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aresetn, O => areset_d1_i_1_n_0 ); areset_d1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => areset_d1_i_1_n_0, Q => areset_d1, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_FAMILY : string; attribute C_FAMILY of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute P_AXI4 : integer; attribute P_AXI4 of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute P_AXILITE : integer; attribute P_AXILITE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute P_DECERR : string; attribute P_DECERR of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b11"; attribute P_INCR : string; attribute P_INCR of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute P_SLVERR : string; attribute P_SLVERR of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b10"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal \^m_axi_wready\ : STD_LOGIC; signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_wvalid\ : STD_LOGIC; begin \^m_axi_wready\ <= m_axi_wready; \^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0); \^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0); \^s_axi_wvalid\ <= s_axi_wvalid; m_axi_arburst(1) <= \<const0>\; m_axi_arburst(0) <= \<const1>\; m_axi_arcache(3) <= \<const0>\; m_axi_arcache(2) <= \<const0>\; m_axi_arcache(1) <= \<const0>\; m_axi_arcache(0) <= \<const0>\; m_axi_arid(11) <= \<const0>\; m_axi_arid(10) <= \<const0>\; m_axi_arid(9) <= \<const0>\; m_axi_arid(8) <= \<const0>\; m_axi_arid(7) <= \<const0>\; m_axi_arid(6) <= \<const0>\; m_axi_arid(5) <= \<const0>\; m_axi_arid(4) <= \<const0>\; m_axi_arid(3) <= \<const0>\; m_axi_arid(2) <= \<const0>\; m_axi_arid(1) <= \<const0>\; m_axi_arid(0) <= \<const0>\; m_axi_arlen(7) <= \<const0>\; m_axi_arlen(6) <= \<const0>\; m_axi_arlen(5) <= \<const0>\; m_axi_arlen(4) <= \<const0>\; m_axi_arlen(3) <= \<const0>\; m_axi_arlen(2) <= \<const0>\; m_axi_arlen(1) <= \<const0>\; m_axi_arlen(0) <= \<const0>\; m_axi_arlock(0) <= \<const0>\; m_axi_arqos(3) <= \<const0>\; m_axi_arqos(2) <= \<const0>\; m_axi_arqos(1) <= \<const0>\; m_axi_arqos(0) <= \<const0>\; m_axi_arregion(3) <= \<const0>\; m_axi_arregion(2) <= \<const0>\; m_axi_arregion(1) <= \<const0>\; m_axi_arregion(0) <= \<const0>\; m_axi_arsize(2) <= \<const0>\; m_axi_arsize(1) <= \<const1>\; m_axi_arsize(0) <= \<const0>\; m_axi_aruser(0) <= \<const0>\; m_axi_awburst(1) <= \<const0>\; m_axi_awburst(0) <= \<const1>\; m_axi_awcache(3) <= \<const0>\; m_axi_awcache(2) <= \<const0>\; m_axi_awcache(1) <= \<const0>\; m_axi_awcache(0) <= \<const0>\; m_axi_awid(11) <= \<const0>\; m_axi_awid(10) <= \<const0>\; m_axi_awid(9) <= \<const0>\; m_axi_awid(8) <= \<const0>\; m_axi_awid(7) <= \<const0>\; m_axi_awid(6) <= \<const0>\; m_axi_awid(5) <= \<const0>\; m_axi_awid(4) <= \<const0>\; m_axi_awid(3) <= \<const0>\; m_axi_awid(2) <= \<const0>\; m_axi_awid(1) <= \<const0>\; m_axi_awid(0) <= \<const0>\; m_axi_awlen(7) <= \<const0>\; m_axi_awlen(6) <= \<const0>\; m_axi_awlen(5) <= \<const0>\; m_axi_awlen(4) <= \<const0>\; m_axi_awlen(3) <= \<const0>\; m_axi_awlen(2) <= \<const0>\; m_axi_awlen(1) <= \<const0>\; m_axi_awlen(0) <= \<const0>\; m_axi_awlock(0) <= \<const0>\; m_axi_awqos(3) <= \<const0>\; m_axi_awqos(2) <= \<const0>\; m_axi_awqos(1) <= \<const0>\; m_axi_awqos(0) <= \<const0>\; m_axi_awregion(3) <= \<const0>\; m_axi_awregion(2) <= \<const0>\; m_axi_awregion(1) <= \<const0>\; m_axi_awregion(0) <= \<const0>\; m_axi_awsize(2) <= \<const0>\; m_axi_awsize(1) <= \<const1>\; m_axi_awsize(0) <= \<const0>\; m_axi_awuser(0) <= \<const0>\; m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0); m_axi_wid(11) <= \<const0>\; m_axi_wid(10) <= \<const0>\; m_axi_wid(9) <= \<const0>\; m_axi_wid(8) <= \<const0>\; m_axi_wid(7) <= \<const0>\; m_axi_wid(6) <= \<const0>\; m_axi_wid(5) <= \<const0>\; m_axi_wid(4) <= \<const0>\; m_axi_wid(3) <= \<const0>\; m_axi_wid(2) <= \<const0>\; m_axi_wid(1) <= \<const0>\; m_axi_wid(0) <= \<const0>\; m_axi_wlast <= \<const1>\; m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0); m_axi_wuser(0) <= \<const0>\; m_axi_wvalid <= \^s_axi_wvalid\; s_axi_buser(0) <= \<const0>\; s_axi_ruser(0) <= \<const0>\; s_axi_wready <= \^m_axi_wready\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s port map ( Q(22 downto 20) => m_axi_awprot(2 downto 0), Q(19 downto 0) => m_axi_awaddr(31 downto 12), aclk => aclk, aresetn => aresetn, \in\(33 downto 32) => m_axi_rresp(1 downto 0), \in\(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), \m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0), \m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12), m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_bvalid => m_axi_bvalid, m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, \s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0), \s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0), \s_axi_rid[11]\(34) => s_axi_rlast, \s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0), \s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of design_1_auto_pc_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of design_1_auto_pc_0 : entity is "design_1_auto_pc_0,axi_protocol_converter_v2_1_17_axi_protocol_converter,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of design_1_auto_pc_0 : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of design_1_auto_pc_0 : entity is "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2"; end design_1_auto_pc_0; architecture STRUCTURE of design_1_auto_pc_0 is signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC; signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of inst : label is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of inst : label is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of inst : label is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of inst : label is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of inst : label is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of inst : label is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of inst : label is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of inst : label is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of inst : label is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of inst : label is 1; attribute C_FAMILY : string; attribute C_FAMILY of inst : label is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of inst : label is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of inst : label is 2; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of inst : label is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of inst : label is 2; attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of inst : label is 1; attribute P_AXI4 : integer; attribute P_AXI4 of inst : label is 0; attribute P_AXILITE : integer; attribute P_AXILITE of inst : label is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of inst : label is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of inst : label is 2; attribute P_DECERR : string; attribute P_DECERR of inst : label is "2'b11"; attribute P_INCR : string; attribute P_INCR of inst : label is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of inst : label is 1; attribute P_SLVERR : string; attribute P_SLVERR of inst : label is "2'b10"; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN"; attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST RST"; attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY"; attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID"; attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY"; attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID"; attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY"; attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID"; attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY"; attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID"; attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY"; attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID"; attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST"; attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST"; attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR"; attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT"; attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR"; attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT"; attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP"; attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA"; attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP"; attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA"; attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB"; attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST"; attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"; attribute X_INTERFACE_INFO of s_axi_arid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARID"; attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN"; attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"; attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT"; attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARQOS"; attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"; attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST"; attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"; attribute X_INTERFACE_INFO of s_axi_awid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWID"; attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN"; attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"; attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT"; attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWQOS"; attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"; attribute X_INTERFACE_INFO of s_axi_bid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BID"; attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; attribute X_INTERFACE_INFO of s_axi_rid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RID"; attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; attribute X_INTERFACE_INFO of s_axi_wid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WID"; attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; begin inst: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter port map ( aclk => aclk, aresetn => aresetn, m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0), m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0), m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0), m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0), m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0), m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0), m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0), m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0), m_axi_arready => m_axi_arready, m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0), m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0), m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0), m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0), m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0), m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0), m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0), m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0), m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0), m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0), m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0), m_axi_awready => m_axi_awready, m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0), m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0), m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0), m_axi_awvalid => m_axi_awvalid, m_axi_bid(11 downto 0) => B"000000000000", m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_buser(0) => '0', m_axi_bvalid => m_axi_bvalid, m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_rid(11 downto 0) => B"000000000000", m_axi_rlast => '1', m_axi_rready => m_axi_rready, m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), m_axi_ruser(0) => '0', m_axi_rvalid => m_axi_rvalid, m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0), m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0), m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED, m_axi_wready => m_axi_wready, m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0), m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0), m_axi_wvalid => m_axi_wvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0), s_axi_arready => s_axi_arready, s_axi_arregion(3 downto 0) => B"0000", s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0), s_axi_aruser(0) => '0', s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0), s_axi_awready => s_axi_awready, s_axi_awregion(3 downto 0) => B"0000", s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0), s_axi_awuser(0) => '0', s_axi_awvalid => s_axi_awvalid, s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0), s_axi_bready => s_axi_bready, s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0), s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0), s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wuser(0) => '0', s_axi_wvalid => s_axi_wvalid ); end STRUCTURE;
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 -- Date : Mon Sep 16 04:58:12 2019 -- Host : varun-laptop running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -rename_top design_1_auto_pc_0 -prefix -- design_1_auto_pc_0_ design_1_auto_pc_0_sim_netlist.vhdl -- Design : design_1_auto_pc_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd is port ( next_pending_r_reg_0 : out STD_LOGIC; \axaddr_incr_reg[0]_0\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[2]_0\ : out STD_LOGIC; \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 10 downto 0 ); \m_axi_awaddr[11]\ : out STD_LOGIC; \m_axi_awaddr[5]\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 3 downto 0 ); incr_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; sel_first_reg_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \next\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[0]_rep\ : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd is signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \axaddr_incr[0]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[10]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr[1]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[2]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[4]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[5]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[6]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[7]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[8]_i_1_n_0\ : STD_LOGIC; signal \axaddr_incr[9]_i_1_n_0\ : STD_LOGIC; signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC; signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 10 downto 0 ); signal \axaddr_incr_reg[11]_i_4_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3_n_7\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_2_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[5]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[6]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_2_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \^axlen_cnt_reg[2]_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC; signal next_pending_r_i_5_n_0 : STD_LOGIC; signal \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2\ : label is "soft_lutpair116"; attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1\ : label is "soft_lutpair117"; attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1\ : label is "soft_lutpair119"; attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1\ : label is "soft_lutpair120"; attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1\ : label is "soft_lutpair118"; attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1\ : label is "soft_lutpair115"; attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2\ : label is "soft_lutpair114"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair112"; attribute SOFT_HLUTNM of \m_axi_awaddr[11]_INST_0_i_1\ : label is "soft_lutpair113"; attribute SOFT_HLUTNM of \m_axi_awaddr[5]_INST_0_i_1\ : label is "soft_lutpair113"; begin Q(0) <= \^q\(0); \axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\; \axaddr_incr_reg[11]_0\(10 downto 0) <= \^axaddr_incr_reg[11]_0\(10 downto 0); \axlen_cnt_reg[2]_0\ <= \^axlen_cnt_reg[2]_0\; \axaddr_incr[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_7\, O => \axaddr_incr[0]_i_1_n_0\ ); \axaddr_incr[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(10), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_5\, O => \axaddr_incr[10]_i_1_n_0\ ); \axaddr_incr[11]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \next\, O => \axaddr_incr[11]_i_1_n_0\ ); \axaddr_incr[11]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(11), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_4\, O => \axaddr_incr[11]_i_2_n_0\ ); \axaddr_incr[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_6\, O => \axaddr_incr[1]_i_1_n_0\ ); \axaddr_incr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_5\, O => \axaddr_incr[2]_i_1_n_0\ ); \axaddr_incr[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3_n_4\, O => \axaddr_incr[3]_i_1_n_0\ ); \axaddr_incr[3]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"0102" ) port map ( I0 => \m_payload_i_reg[46]\(0), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(0) ); \axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(3), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_11_n_0\ ); \axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(2), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_12_n_0\ ); \axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(1), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), O => \axaddr_incr[3]_i_13_n_0\ ); \axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(0), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), O => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \m_payload_i_reg[46]\(3), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(3) ); \axaddr_incr[3]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"262A" ) port map ( I0 => \m_payload_i_reg[46]\(2), I1 => \m_payload_i_reg[46]\(6), I2 => \m_payload_i_reg[46]\(5), I3 => \next\, O => S(2) ); \axaddr_incr[3]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"060A" ) port map ( I0 => \m_payload_i_reg[46]\(1), I1 => \m_payload_i_reg[46]\(5), I2 => \m_payload_i_reg[46]\(6), I3 => \next\, O => S(1) ); \axaddr_incr[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(4), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_7\, O => \axaddr_incr[4]_i_1_n_0\ ); \axaddr_incr[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(5), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_6\, O => \axaddr_incr[5]_i_1_n_0\ ); \axaddr_incr[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(6), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_5\, O => \axaddr_incr[6]_i_1_n_0\ ); \axaddr_incr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(7), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3_n_4\, O => \axaddr_incr[7]_i_1_n_0\ ); \axaddr_incr[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(8), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_7\, O => \axaddr_incr[8]_i_1_n_0\ ); \axaddr_incr[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axaddr_incr(9), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4_n_6\, O => \axaddr_incr[9]_i_1_n_0\ ); \axaddr_incr_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[0]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(0), R => '0' ); \axaddr_incr_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[10]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(9), R => '0' ); \axaddr_incr_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[11]_i_2_n_0\, Q => \^axaddr_incr_reg[11]_0\(10), R => '0' ); \axaddr_incr_reg[11]_i_4\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_3_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_4_n_1\, CO(1) => \axaddr_incr_reg[11]_i_4_n_2\, CO(0) => \axaddr_incr_reg[11]_i_4_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[11]_i_4_n_4\, O(2) => \axaddr_incr_reg[11]_i_4_n_5\, O(1) => \axaddr_incr_reg[11]_i_4_n_6\, O(0) => \axaddr_incr_reg[11]_i_4_n_7\, S(3 downto 0) => \^axaddr_incr_reg[11]_0\(10 downto 7) ); \axaddr_incr_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[1]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(1), R => '0' ); \axaddr_incr_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[2]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(2), R => '0' ); \axaddr_incr_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[3]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(3), R => '0' ); \axaddr_incr_reg[3]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_3_n_0\, CO(2) => \axaddr_incr_reg[3]_i_3_n_1\, CO(1) => \axaddr_incr_reg[3]_i_3_n_2\, CO(0) => \axaddr_incr_reg[3]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => \^axaddr_incr_reg[11]_0\(3 downto 0), O(3) => \axaddr_incr_reg[3]_i_3_n_4\, O(2) => \axaddr_incr_reg[3]_i_3_n_5\, O(1) => \axaddr_incr_reg[3]_i_3_n_6\, O(0) => \axaddr_incr_reg[3]_i_3_n_7\, S(3) => \axaddr_incr[3]_i_11_n_0\, S(2) => \axaddr_incr[3]_i_12_n_0\, S(1) => \axaddr_incr[3]_i_13_n_0\, S(0) => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[4]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(4), R => '0' ); \axaddr_incr_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[5]_i_1_n_0\, Q => \axaddr_incr_reg_n_0_[5]\, R => '0' ); \axaddr_incr_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[6]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(5), R => '0' ); \axaddr_incr_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[7]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(6), R => '0' ); \axaddr_incr_reg[7]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_3_n_0\, CO(3) => \axaddr_incr_reg[7]_i_3_n_0\, CO(2) => \axaddr_incr_reg[7]_i_3_n_1\, CO(1) => \axaddr_incr_reg[7]_i_3_n_2\, CO(0) => \axaddr_incr_reg[7]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[7]_i_3_n_4\, O(2) => \axaddr_incr_reg[7]_i_3_n_5\, O(1) => \axaddr_incr_reg[7]_i_3_n_6\, O(0) => \axaddr_incr_reg[7]_i_3_n_7\, S(3 downto 2) => \^axaddr_incr_reg[11]_0\(6 downto 5), S(1) => \axaddr_incr_reg_n_0_[5]\, S(0) => \^axaddr_incr_reg[11]_0\(4) ); \axaddr_incr_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[8]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(7), R => '0' ); \axaddr_incr_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \axaddr_incr[11]_i_1_n_0\, D => \axaddr_incr[9]_i_1_n_0\, Q => \^axaddr_incr_reg[11]_0\(8), R => '0' ); \axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => \m_payload_i_reg[46]\(8), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^q\(0), I4 => \^axlen_cnt_reg[2]_0\, O => \axlen_cnt[1]_i_1__0_n_0\ ); \axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA900A900A900" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \^q\(0), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^axlen_cnt_reg[2]_0\, I4 => E(0), I5 => \m_payload_i_reg[46]\(9), O => \axlen_cnt[2]_i_1_n_0\ ); \axlen_cnt[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEEBAAAAAAAA" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^q\(0), I5 => \^axlen_cnt_reg[2]_0\, O => \axlen_cnt[3]_i_2_n_0\ ); \axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \^q\(0), O => \axlen_cnt[4]_i_1_n_0\ ); \axlen_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[5]\, I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \^q\(0), I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[3]\, O => \axlen_cnt[5]_i_1_n_0\ ); \axlen_cnt[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axlen_cnt_reg_n_0_[6]\, I1 => \axlen_cnt_reg_n_0_[5]\, I2 => \axlen_cnt[7]_i_3_n_0\, O => \axlen_cnt[6]_i_1_n_0\ ); \axlen_cnt[7]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"A9AA" ) port map ( I0 => \axlen_cnt_reg_n_0_[7]\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt[7]_i_3_n_0\, O => \axlen_cnt[7]_i_2_n_0\ ); \axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \axlen_cnt_reg_n_0_[3]\, I1 => \axlen_cnt_reg_n_0_[2]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^q\(0), I4 => \axlen_cnt_reg_n_0_[4]\, O => \axlen_cnt[7]_i_3_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \state_reg[1]\(0), Q => \^q\(0), R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[1]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[2]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[3]_i_2_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[4]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[5]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[5]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[6]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[6]\, R => \state_reg[0]_rep\ ); \axlen_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[7]_i_2_n_0\, Q => \axlen_cnt_reg_n_0_[7]\, R => \state_reg[0]_rep\ ); \m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \m_payload_i_reg[46]\(7), O => \m_axi_awaddr[11]\ ); \m_axi_awaddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[5]\, I2 => \m_payload_i_reg[46]\(7), I3 => \m_payload_i_reg[46]\(4), O => \m_axi_awaddr[5]\ ); \next_pending_r_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"55545555" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[7]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[6]\, I4 => next_pending_r_i_5_n_0, O => \^axlen_cnt_reg[2]_0\ ); next_pending_r_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \axlen_cnt_reg_n_0_[1]\, I1 => \axlen_cnt_reg_n_0_[4]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[3]\, O => next_pending_r_i_5_n_0 ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => incr_next_pending, Q => next_pending_r_reg_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_0, Q => \^axaddr_incr_reg[0]_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is port ( incr_next_pending : out STD_LOGIC; \axaddr_incr_reg[0]_0\ : out STD_LOGIC; \axlen_cnt_reg[0]_0\ : out STD_LOGIC; \axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \m_axi_araddr[11]\ : out STD_LOGIC; \m_axi_araddr[5]\ : out STD_LOGIC; \m_axi_araddr[3]\ : out STD_LOGIC; \m_axi_araddr[2]\ : out STD_LOGIC; \m_axi_araddr[1]\ : out STD_LOGIC; S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_0 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 10 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; \m_payload_i_reg[47]_0\ : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); si_rs_arvalid : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]\ : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arready : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_17_b2s_incr_cmd"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 is signal \axaddr_incr[0]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[10]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[11]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr[1]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[2]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_11_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_12_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_13_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_14_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[4]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[5]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[6]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[7]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[8]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_incr[9]_i_1__0_n_0\ : STD_LOGIC; signal \^axaddr_incr_reg[0]_0\ : STD_LOGIC; signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \axaddr_incr_reg[11]_i_4__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_4__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[1]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[2]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[3]\ : STD_LOGIC; signal \axaddr_incr_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_2__0_n_0\ : STD_LOGIC; signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC; signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC; signal \^axlen_cnt_reg[0]_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC; signal \^incr_next_pending\ : STD_LOGIC; signal \next_pending_r_i_2__0_n_0\ : STD_LOGIC; signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \axaddr_incr[10]_i_1__0\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_2__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \axaddr_incr[1]_i_1__0\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \axaddr_incr[2]_i_1__0\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \axaddr_incr[3]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \axaddr_incr[4]_i_1__0\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \axaddr_incr[5]_i_1__0\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \axaddr_incr[6]_i_1__0\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \axaddr_incr[7]_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \axaddr_incr[8]_i_1__0\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \axaddr_incr[9]_i_1__0\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_4\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \axlen_cnt[4]_i_1__0\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \axlen_cnt[6]_i_1__0\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_2__0\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3__0\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \m_axi_araddr[11]_INST_0_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \m_axi_araddr[1]_INST_0_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \next_pending_r_i_2__0\ : label is "soft_lutpair7"; begin \axaddr_incr_reg[0]_0\ <= \^axaddr_incr_reg[0]_0\; \axaddr_incr_reg[11]_0\(7 downto 0) <= \^axaddr_incr_reg[11]_0\(7 downto 0); \axlen_cnt_reg[0]_0\ <= \^axlen_cnt_reg[0]_0\; incr_next_pending <= \^incr_next_pending\; \axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_7\, O => \axaddr_incr[0]_i_1__0_n_0\ ); \axaddr_incr[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_5\, O => \axaddr_incr[10]_i_1__0_n_0\ ); \axaddr_incr[11]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_4\, O => \axaddr_incr[11]_i_2__0_n_0\ ); \axaddr_incr[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_6\, O => \axaddr_incr[1]_i_1__0_n_0\ ); \axaddr_incr[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_5\, O => \axaddr_incr[2]_i_1__0_n_0\ ); \axaddr_incr[3]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"0201020202020202" ) port map ( I0 => Q(0), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(0) ); \axaddr_incr[3]_i_11\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \axaddr_incr_reg_n_0_[3]\, I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_11_n_0\ ); \axaddr_incr[3]_i_12\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_incr_reg_n_0_[2]\, I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_12_n_0\ ); \axaddr_incr[3]_i_13\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_incr_reg_n_0_[1]\, I1 => Q(6), I2 => Q(5), O => \axaddr_incr[3]_i_13_n_0\ ); \axaddr_incr[3]_i_14\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \^axaddr_incr_reg[11]_0\(0), I1 => Q(5), I2 => Q(6), O => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[3]\(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[3]_i_3__0_n_4\, O => \axaddr_incr[3]_i_1__0_n_0\ ); \axaddr_incr[3]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"AA6AAAAAAAAAAAAA" ) port map ( I0 => Q(3), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(3) ); \axaddr_incr[3]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"2A262A2A2A2A2A2A" ) port map ( I0 => Q(2), I1 => Q(6), I2 => Q(5), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(2) ); \axaddr_incr[3]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"0A060A0A0A0A0A0A" ) port map ( I0 => Q(1), I1 => Q(5), I2 => Q(6), I3 => \state_reg[1]_0\(1), I4 => \state_reg[1]_0\(0), I5 => m_axi_arready, O => S(1) ); \axaddr_incr[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_7\, O => \axaddr_incr[4]_i_1__0_n_0\ ); \axaddr_incr[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_6\, O => \axaddr_incr[5]_i_1__0_n_0\ ); \axaddr_incr[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(2), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_5\, O => \axaddr_incr[6]_i_1__0_n_0\ ); \axaddr_incr[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \m_payload_i_reg[7]\(3), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[7]_i_3__0_n_4\, O => \axaddr_incr[7]_i_1__0_n_0\ ); \axaddr_incr[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(0), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_7\, O => \axaddr_incr[8]_i_1__0_n_0\ ); \axaddr_incr[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => O(1), I1 => \^axaddr_incr_reg[0]_0\, I2 => \axaddr_incr_reg[11]_i_4__0_n_6\, O => \axaddr_incr[9]_i_1__0_n_0\ ); \axaddr_incr_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[0]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(0), R => '0' ); \axaddr_incr_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[10]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(6), R => '0' ); \axaddr_incr_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[11]_i_2__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(7), R => '0' ); \axaddr_incr_reg[11]_i_4__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_3__0_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_4__0_n_1\, CO(1) => \axaddr_incr_reg[11]_i_4__0_n_2\, CO(0) => \axaddr_incr_reg[11]_i_4__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[11]_i_4__0_n_4\, O(2) => \axaddr_incr_reg[11]_i_4__0_n_5\, O(1) => \axaddr_incr_reg[11]_i_4__0_n_6\, O(0) => \axaddr_incr_reg[11]_i_4__0_n_7\, S(3 downto 0) => \^axaddr_incr_reg[11]_0\(7 downto 4) ); \axaddr_incr_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[1]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[1]\, R => '0' ); \axaddr_incr_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[2]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[2]\, R => '0' ); \axaddr_incr_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[3]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[3]\, R => '0' ); \axaddr_incr_reg[3]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_3__0_n_0\, CO(2) => \axaddr_incr_reg[3]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[3]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[3]_i_3__0_n_3\, CYINIT => '0', DI(3) => \axaddr_incr_reg_n_0_[3]\, DI(2) => \axaddr_incr_reg_n_0_[2]\, DI(1) => \axaddr_incr_reg_n_0_[1]\, DI(0) => \^axaddr_incr_reg[11]_0\(0), O(3) => \axaddr_incr_reg[3]_i_3__0_n_4\, O(2) => \axaddr_incr_reg[3]_i_3__0_n_5\, O(1) => \axaddr_incr_reg[3]_i_3__0_n_6\, O(0) => \axaddr_incr_reg[3]_i_3__0_n_7\, S(3) => \axaddr_incr[3]_i_11_n_0\, S(2) => \axaddr_incr[3]_i_12_n_0\, S(1) => \axaddr_incr[3]_i_13_n_0\, S(0) => \axaddr_incr[3]_i_14_n_0\ ); \axaddr_incr_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[4]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(1), R => '0' ); \axaddr_incr_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[5]_i_1__0_n_0\, Q => \axaddr_incr_reg_n_0_[5]\, R => '0' ); \axaddr_incr_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[6]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(2), R => '0' ); \axaddr_incr_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[7]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(3), R => '0' ); \axaddr_incr_reg[7]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_3__0_n_0\, CO(3) => \axaddr_incr_reg[7]_i_3__0_n_0\, CO(2) => \axaddr_incr_reg[7]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[7]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[7]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_incr_reg[7]_i_3__0_n_4\, O(2) => \axaddr_incr_reg[7]_i_3__0_n_5\, O(1) => \axaddr_incr_reg[7]_i_3__0_n_6\, O(0) => \axaddr_incr_reg[7]_i_3__0_n_7\, S(3 downto 2) => \^axaddr_incr_reg[11]_0\(3 downto 2), S(1) => \axaddr_incr_reg_n_0_[5]\, S(0) => \^axaddr_incr_reg[11]_0\(1) ); \axaddr_incr_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[8]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(4), R => '0' ); \axaddr_incr_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => sel_first_reg_1(0), D => \axaddr_incr[9]_i_1__0_n_0\, Q => \^axaddr_incr_reg[11]_0\(5), R => '0' ); \axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"20FF2020" ) port map ( I0 => si_rs_arvalid, I1 => \state_reg[0]_rep\, I2 => Q(8), I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[0]_i_1__2_n_0\ ); \axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"F88F8888" ) port map ( I0 => E(0), I1 => Q(9), I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[1]_i_1__1_n_0\ ); \axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA900A900A900" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \^axlen_cnt_reg[0]_0\, I4 => E(0), I5 => Q(10), O => \axlen_cnt[2]_i_1__1_n_0\ ); \axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEEBAAAAAAAA" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[0]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \^axlen_cnt_reg[0]_0\, O => \axlen_cnt[3]_i_2__0_n_0\ ); \axlen_cnt[3]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"55545555" ) port map ( I0 => E(0), I1 => \axlen_cnt_reg_n_0_[7]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[6]\, I4 => \next_pending_r_i_4__0_n_0\, O => \^axlen_cnt_reg[0]_0\ ); \axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[4]_i_1__0_n_0\ ); \axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAA9" ) port map ( I0 => \axlen_cnt_reg_n_0_[5]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \axlen_cnt_reg_n_0_[4]\, O => \axlen_cnt[5]_i_1__0_n_0\ ); \axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axlen_cnt_reg_n_0_[6]\, I1 => \axlen_cnt_reg_n_0_[5]\, I2 => \axlen_cnt[7]_i_3__0_n_0\, O => \axlen_cnt[6]_i_1__0_n_0\ ); \axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A9AA" ) port map ( I0 => \axlen_cnt_reg_n_0_[7]\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt[7]_i_3__0_n_0\, O => \axlen_cnt[7]_i_2__0_n_0\ ); \axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \axlen_cnt_reg_n_0_[4]\, I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[3]\, I3 => \axlen_cnt_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[0]\, O => \axlen_cnt[7]_i_3__0_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[0]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[1]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[2]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[3]_i_2__0_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \axlen_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[4]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[4]\, R => \state_reg[1]\ ); \axlen_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[5]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[5]\, R => \state_reg[1]\ ); \axlen_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[6]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[6]\, R => \state_reg[1]\ ); \axlen_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[7]_i_2__0_n_0\, Q => \axlen_cnt_reg_n_0_[7]\, R => \state_reg[1]\ ); \m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => Q(7), O => \m_axi_araddr[11]\ ); \m_axi_araddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[1]\, I2 => Q(7), I3 => Q(1), O => \m_axi_araddr[1]\ ); \m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[2]\, I2 => Q(7), I3 => Q(2), O => \m_axi_araddr[2]\ ); \m_axi_araddr[3]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[3]\, I2 => Q(7), I3 => Q(3), O => \m_axi_araddr[3]\ ); \m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"EF40" ) port map ( I0 => \^axaddr_incr_reg[0]_0\, I1 => \axaddr_incr_reg_n_0_[5]\, I2 => Q(7), I3 => Q(4), O => \m_axi_araddr[5]\ ); \next_pending_r_i_1__2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF505C" ) port map ( I0 => \next_pending_r_i_2__0_n_0\, I1 => next_pending_r_reg_n_0, I2 => \state_reg[1]_rep\, I3 => E(0), I4 => \m_payload_i_reg[47]_0\, O => \^incr_next_pending\ ); \next_pending_r_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \next_pending_r_i_4__0_n_0\, I1 => \axlen_cnt_reg_n_0_[6]\, I2 => \axlen_cnt_reg_n_0_[5]\, I3 => \axlen_cnt_reg_n_0_[7]\, O => \next_pending_r_i_2__0_n_0\ ); \next_pending_r_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[4]\, O => \next_pending_r_i_4__0_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \^incr_next_pending\, Q => next_pending_r_reg_n_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_0, Q => \^axaddr_incr_reg[0]_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is port ( \axlen_cnt_reg[7]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC; \m_payload_i_reg[0]_0\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; sel_first_i : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_incr_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_valid_i0 : out STD_LOGIC; s_ready_i0 : out STD_LOGIC; \m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC; si_rs_arvalid : in STD_LOGIC; \axlen_cnt_reg[7]_0\ : in STD_LOGIC; s_axburst_eq1_reg : in STD_LOGIC; \cnt_read_reg[2]_rep__0\ : in STD_LOGIC; \wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg_1 : in STD_LOGIC; areset_d1 : in STD_LOGIC; sel_first : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[5]\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; aclk : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_payload_i_reg[0]\ : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal \next_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axaddr_incr[11]_i_1__0\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__2\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of m_axi_arvalid_INST_0 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \s_ready_i_i_1__0\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair2"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \state_reg[0]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute KEEP : string; attribute KEEP of \state_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]"; attribute FSM_ENCODED_STATES of \state_reg[0]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1; attribute KEEP of \state_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]"; attribute FSM_ENCODED_STATES of \state_reg[1]\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute KEEP of \state_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]"; attribute FSM_ENCODED_STATES of \state_reg[1]_rep\ : label is "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11"; attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1; attribute KEEP of \state_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4__0\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6__0\ : label is "soft_lutpair4"; begin Q(1 downto 0) <= \^q\(1 downto 0); \m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\; \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; \axaddr_incr[11]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AAEA" ) port map ( I0 => sel_first, I1 => m_axi_arready, I2 => \^m_payload_i_reg[0]_0\, I3 => \^m_payload_i_reg[0]\, O => \axaddr_incr_reg[0]\(0) ); \axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAACAAAAAAA0AA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \m_payload_i_reg[46]\(0), I2 => \^m_payload_i_reg[0]_0\, I3 => si_rs_arvalid, I4 => \^m_payload_i_reg[0]\, I5 => \m_payload_i_reg[5]\, O => \axaddr_offset_r_reg[2]\(0) ); \axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"00CA" ) port map ( I0 => si_rs_arvalid, I1 => m_axi_arready, I2 => \^q\(0), I3 => \^q\(1), O => E(0) ); \axlen_cnt[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00005140" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => m_axi_arready, I3 => si_rs_arvalid, I4 => \axlen_cnt_reg[7]_0\, O => \axlen_cnt_reg[7]\ ); m_axi_arvalid_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, O => m_axi_arvalid ); \m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"D5" ) port map ( I0 => si_rs_arvalid, I1 => \^m_payload_i_reg[0]\, I2 => \^m_payload_i_reg[0]_0\, O => \m_payload_i_reg[0]_1\(0) ); \m_valid_i_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"FF70FFFF" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, I2 => si_rs_arvalid, I3 => s_axi_arvalid, I4 => s_ready_i_reg, O => m_valid_i0 ); r_push_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^m_payload_i_reg[0]\, I1 => \^m_payload_i_reg[0]_0\, I2 => m_axi_arready, O => r_push_r_reg ); \s_ready_i_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"8FFF8F8F" ) port map ( I0 => \^m_payload_i_reg[0]_0\, I1 => \^m_payload_i_reg[0]\, I2 => si_rs_arvalid, I3 => s_axi_arvalid, I4 => s_ready_i_reg, O => s_ready_i0 ); \sel_first_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFC4C4CFCC" ) port map ( I0 => m_axi_arready, I1 => sel_first_reg_1, I2 => \^q\(1), I3 => si_rs_arvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg ); \sel_first_i_1__3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFC4C4CFCC" ) port map ( I0 => m_axi_arready, I1 => sel_first, I2 => \^m_payload_i_reg[0]\, I3 => si_rs_arvalid, I4 => \^m_payload_i_reg[0]_0\, I5 => areset_d1, O => sel_first_reg_0 ); \sel_first_i_1__4\: unisim.vcomponents.LUT6 generic map( INIT => X"FCFFFFFFCCCECCCE" ) port map ( I0 => si_rs_arvalid, I1 => areset_d1, I2 => \^m_payload_i_reg[0]\, I3 => \^m_payload_i_reg[0]_0\, I4 => m_axi_arready, I5 => sel_first_reg_2, O => sel_first_i ); \state[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"003030303E3E3E3E" ) port map ( I0 => si_rs_arvalid, I1 => \^q\(1), I2 => \^q\(0), I3 => m_axi_arready, I4 => s_axburst_eq1_reg, I5 => \cnt_read_reg[2]_rep__0\, O => \next_state__0\(0) ); \state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00AAB000" ) port map ( I0 => \cnt_read_reg[2]_rep__0\, I1 => s_axburst_eq1_reg, I2 => m_axi_arready, I3 => \^m_payload_i_reg[0]_0\, I4 => \^m_payload_i_reg[0]\, O => \next_state__0\(1) ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(0), Q => \^q\(0), R => areset_d1 ); \state_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(0), Q => \^m_payload_i_reg[0]_0\, R => areset_d1 ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(1), Q => \^q\(1), R => areset_d1 ); \state_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \next_state__0\(1), Q => \^m_payload_i_reg[0]\, R => areset_d1 ); \wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \^m_payload_i_reg[0]\, I1 => si_rs_arvalid, I2 => \^m_payload_i_reg[0]_0\, O => \wrap_boundary_axaddr_r_reg[11]\(0) ); \wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8A5575AA8A5545" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_arvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => D(0) ); \wrap_cnt_r[3]_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(1), I1 => \^m_payload_i_reg[0]_0\, I2 => si_rs_arvalid, I3 => \^m_payload_i_reg[0]\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_6__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \^m_payload_i_reg[0]_0\, I2 => si_rs_arvalid, I3 => \^m_payload_i_reg[0]\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8AAA8AAA8AAABA" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_arvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => \wrap_second_len_r_reg[0]\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo is port ( \cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC; \cnt_read_reg[1]_rep__0_0\ : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); D : out STD_LOGIC_VECTOR ( 0 to 0 ); bresp_push : out STD_LOGIC; bvalid_i_reg : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); b_push : in STD_LOGIC; shandshake_r : in STD_LOGIC; areset_d1 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); mhandshake_r : in STD_LOGIC; si_rs_bready : in STD_LOGIC; bvalid_i_reg_0 : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); aclk : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo is signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \bresp_cnt[7]_i_4_n_0\ : STD_LOGIC; signal \bresp_cnt[7]_i_5_n_0\ : STD_LOGIC; signal \^bresp_push\ : STD_LOGIC; signal bvalid_i_i_2_n_0 : STD_LOGIC; signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC; signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \^cnt_read_reg[1]_rep__0_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC; signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC; signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair121"; attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair121"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name : string; attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 "; attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 "; attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 "; attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 "; attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 "; attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 "; attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 "; attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 "; attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 "; attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 "; attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 "; attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 "; attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 "; attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 "; attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 "; attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 "; begin bresp_push <= \^bresp_push\; \cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\; \cnt_read_reg[1]_rep__0_0\ <= \^cnt_read_reg[1]_rep__0_0\; \bresp_cnt[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"ABAA" ) port map ( I0 => areset_d1, I1 => \bresp_cnt[7]_i_3_n_0\, I2 => \bresp_cnt[7]_i_4_n_0\, I3 => \bresp_cnt[7]_i_5_n_0\, O => SR(0) ); \bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"EEFEFFFFFFFFEEFE" ) port map ( I0 => \bresp_cnt_reg[7]\(7), I1 => \bresp_cnt_reg[7]\(6), I2 => \bresp_cnt_reg[7]\(0), I3 => \memory_reg[3][0]_srl4_n_0\, I4 => \bresp_cnt_reg[7]\(3), I5 => \memory_reg[3][3]_srl4_n_0\, O => \bresp_cnt[7]_i_3_n_0\ ); \bresp_cnt[7]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"FFF6FFFF" ) port map ( I0 => \bresp_cnt_reg[7]\(1), I1 => \memory_reg[3][1]_srl4_n_0\, I2 => \bresp_cnt_reg[7]\(4), I3 => \bresp_cnt_reg[7]\(5), I4 => mhandshake_r, O => \bresp_cnt[7]_i_4_n_0\ ); \bresp_cnt[7]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"0000D00DD00DD00D" ) port map ( I0 => \memory_reg[3][0]_srl4_n_0\, I1 => \bresp_cnt_reg[7]\(0), I2 => \bresp_cnt_reg[7]\(2), I3 => \memory_reg[3][2]_srl4_n_0\, I4 => \^cnt_read_reg[1]_rep__0_0\, I5 => \^cnt_read_reg[0]_rep__0_0\, O => \bresp_cnt[7]_i_5_n_0\ ); bvalid_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0444" ) port map ( I0 => areset_d1, I1 => bvalid_i_i_2_n_0, I2 => si_rs_bready, I3 => bvalid_i_reg_0, O => bvalid_i_reg ); bvalid_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00070707" ) port map ( I0 => \^cnt_read_reg[1]_rep__0_0\, I1 => \^cnt_read_reg[0]_rep__0_0\, I2 => shandshake_r, I3 => Q(1), I4 => Q(0), I5 => bvalid_i_reg_0, O => bvalid_i_i_2_n_0 ); \cnt_read[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^bresp_push\, I1 => shandshake_r, I2 => Q(0), O => D(0) ); \cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => b_push, I2 => shandshake_r, O => \cnt_read[0]_i_1__2_n_0\ ); \cnt_read[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"E718" ) port map ( I0 => \^cnt_read_reg[0]_rep__0_0\, I1 => b_push, I2 => shandshake_r, I3 => \^cnt_read_reg[1]_rep__0_0\, O => \cnt_read[1]_i_1_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__2_n_0\, Q => \^cnt_read_reg[0]_rep__0_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1_n_0\, Q => \^cnt_read_reg[1]_rep__0_0\, S => areset_d1 ); \memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(0), Q => \memory_reg[3][0]_srl4_n_0\ ); \memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000041004141" ) port map ( I0 => \memory_reg[3][0]_srl4_i_2__0_n_0\, I1 => \memory_reg[3][2]_srl4_n_0\, I2 => \bresp_cnt_reg[7]\(2), I3 => \bresp_cnt_reg[7]\(0), I4 => \memory_reg[3][0]_srl4_n_0\, I5 => \memory_reg[3][0]_srl4_i_3_n_0\, O => \^bresp_push\ ); \memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^cnt_read_reg[1]_rep__0_0\, I1 => \^cnt_read_reg[0]_rep__0_0\, O => \memory_reg[3][0]_srl4_i_2__0_n_0\ ); \memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFBFFFFFFFFFFFB" ) port map ( I0 => \bresp_cnt[7]_i_3_n_0\, I1 => mhandshake_r, I2 => \bresp_cnt_reg[7]\(5), I3 => \bresp_cnt_reg[7]\(4), I4 => \memory_reg[3][1]_srl4_n_0\, I5 => \bresp_cnt_reg[7]\(1), O => \memory_reg[3][0]_srl4_i_3_n_0\ ); \memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(6), Q => \out\(2) ); \memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(7), Q => \out\(3) ); \memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(8), Q => \out\(4) ); \memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(9), Q => \out\(5) ); \memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(10), Q => \out\(6) ); \memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(11), Q => \out\(7) ); \memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(12), Q => \out\(8) ); \memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(13), Q => \out\(9) ); \memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(14), Q => \out\(10) ); \memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => cnt_read(0), A1 => cnt_read(1), A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(15), Q => \out\(11) ); \memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(1), Q => \memory_reg[3][1]_srl4_n_0\ ); \memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(2), Q => \memory_reg[3][2]_srl4_n_0\ ); \memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(3), Q => \memory_reg[3][3]_srl4_n_0\ ); \memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(4), Q => \out\(0) ); \memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \cnt_read_reg[0]_rep_n_0\, A1 => \cnt_read_reg[1]_rep_n_0\, A2 => '0', A3 => '0', CE => b_push, CLK => aclk, D => \in\(5), Q => \out\(1) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is port ( Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); mhandshake : out STD_LOGIC; m_axi_bready : out STD_LOGIC; \skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); shandshake_r : in STD_LOGIC; sel : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; mhandshake_r : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\; architecture STRUCTURE of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ is signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair122"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair122"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; attribute srl_name : string; attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 "; attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] "; attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 "; begin Q(1 downto 0) <= \^q\(1 downto 0); \cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A69A" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => shandshake_r, I3 => sel, O => \cnt_read[1]_i_1__0_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => D(0), Q => \^q\(0), S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__0_n_0\, Q => \^q\(1), S => areset_d1 ); m_axi_bready_INST_0: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => mhandshake_r, O => m_axi_bready ); \memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \^q\(0), A1 => \^q\(1), A2 => '0', A3 => '0', CE => sel, CLK => aclk, D => \in\(0), Q => \skid_buffer_reg[1]\(0) ); \memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => \^q\(0), A1 => \^q\(1), A2 => '0', A3 => '0', CE => sel, CLK => aclk, D => \in\(1), Q => \skid_buffer_reg[1]\(1) ); mhandshake_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"2000" ) port map ( I0 => m_axi_bvalid, I1 => mhandshake_r, I2 => \^q\(0), I3 => \^q\(1), O => mhandshake ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is port ( \cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC; \cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC; \cnt_read_reg[4]_rep__2_2\ : out STD_LOGIC; m_axi_rready : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); s_ready_i_reg : in STD_LOGIC; \cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC; si_rs_rready : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\; architecture STRUCTURE of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ is signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC; signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_5_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__3_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC; signal \^cnt_read_reg[4]_rep__2_2\ : STD_LOGIC; signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC; signal wr_en0 : STD_LOGIC; signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair18"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__3\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__3\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__3\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]"; attribute KEEP of \cnt_read_reg[2]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]"; attribute KEEP of \cnt_read_reg[3]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]"; attribute KEEP of \cnt_read_reg[4]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]"; attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair19"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name : string; attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 "; attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 "; attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 "; attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 "; attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 "; attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 "; attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 "; attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 "; attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 "; attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 "; attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 "; attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 "; attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 "; attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 "; attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 "; attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 "; attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 "; attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 "; attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 "; attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 "; attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 "; attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 "; attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 "; attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 "; attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 "; attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 "; attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 "; attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 "; attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 "; attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 "; attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 "; attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 "; attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 "; attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 "; attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair19"; begin \cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\; \cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\; \cnt_read_reg[4]_rep__2_2\ <= \^cnt_read_reg[4]_rep__2_2\; \cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"69" ) port map ( I0 => \cnt_read_reg[0]_rep__2_n_0\, I1 => s_ready_i_reg, I2 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[0]_i_1__1_n_0\ ); \cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"9AA6" ) port map ( I0 => \cnt_read_reg[1]_rep__2_n_0\, I1 => \cnt_read_reg[0]_rep__2_n_0\, I2 => s_ready_i_reg, I3 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[1]_i_1__2_n_0\ ); \cnt_read[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"A9AAAA6A" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read_reg[0]_rep__2_n_0\, I3 => \cnt_read[4]_i_5_n_0\, I4 => s_ready_i_reg, O => \cnt_read[2]_i_1_n_0\ ); \cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAA6AA9AAAAAA" ) port map ( I0 => \^cnt_read_reg[4]_rep__2_0\, I1 => \cnt_read_reg[2]_rep__2_n_0\, I2 => \cnt_read_reg[1]_rep__2_n_0\, I3 => \cnt_read[4]_i_5_n_0\, I4 => s_ready_i_reg, I5 => \cnt_read_reg[0]_rep__2_n_0\, O => \cnt_read[3]_i_1__0_n_0\ ); \cnt_read[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"99AA99AA99AA55A6" ) port map ( I0 => \^cnt_read_reg[4]_rep__2_1\, I1 => \^cnt_read_reg[4]_rep__2_0\, I2 => \^cnt_read_reg[4]_rep__2_2\, I3 => \cnt_read[4]_i_3__0_n_0\, I4 => s_ready_i_reg, I5 => \cnt_read[4]_i_5_n_0\, O => \cnt_read[4]_i_1_n_0\ ); \cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \cnt_read_reg[0]_rep__3_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read_reg[2]_rep__2_n_0\, O => \^cnt_read_reg[4]_rep__2_2\ ); \cnt_read[4]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000100000" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \cnt_read[4]_i_5_n_0\, I3 => \cnt_read_reg[4]_rep__0_0\, I4 => si_rs_rready, I5 => \cnt_read_reg[0]_rep__2_n_0\, O => \cnt_read[4]_i_3__0_n_0\ ); \cnt_read[4]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"6000E000FFFFFFFF" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \^cnt_read_reg[4]_rep__2_0\, I4 => \cnt_read_reg[0]_rep__3_n_0\, I5 => m_axi_rvalid, O => \cnt_read[4]_i_5_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__3\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__1_n_0\, Q => \cnt_read_reg[0]_rep__3_n_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__2_n_0\, Q => \cnt_read_reg[1]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => cnt_read(2), S => areset_d1 ); \cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1_n_0\, Q => \cnt_read_reg[2]_rep__2_n_0\, S => areset_d1 ); \cnt_read_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => cnt_read(3), S => areset_d1 ); \cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \cnt_read_reg[3]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1__0_n_0\, Q => \^cnt_read_reg[4]_rep__2_0\, S => areset_d1 ); \cnt_read_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => cnt_read(4), S => areset_d1 ); \cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \cnt_read_reg[4]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1_n_0\, Q => \^cnt_read_reg[4]_rep__2_1\, S => areset_d1 ); m_axi_rready_INST_0: unisim.vcomponents.LUT5 generic map( INIT => X"9FFF1FFF" ) port map ( I0 => \cnt_read_reg[2]_rep__2_n_0\, I1 => \cnt_read_reg[1]_rep__2_n_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \^cnt_read_reg[4]_rep__2_0\, I4 => \cnt_read_reg[0]_rep__3_n_0\, O => m_axi_rready ); \memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(0), Q => \out\(0), Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"8AAA0AAA0AAAAAAA" ) port map ( I0 => m_axi_rvalid, I1 => \cnt_read_reg[0]_rep__3_n_0\, I2 => \^cnt_read_reg[4]_rep__2_0\, I3 => \^cnt_read_reg[4]_rep__2_1\, I4 => \cnt_read_reg[1]_rep__2_n_0\, I5 => \cnt_read_reg[2]_rep__2_n_0\, O => wr_en0 ); \memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(10), Q => \out\(10), Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(11), Q => \out\(11), Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(12), Q => \out\(12), Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(13), Q => \out\(13), Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(14), Q => \out\(14), Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(15), Q => \out\(15), Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(16), Q => \out\(16), Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(17), Q => \out\(17), Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(18), Q => \out\(18), Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(19), Q => \out\(19), Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(1), Q => \out\(1), Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(20), Q => \out\(20), Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(21), Q => \out\(21), Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(22), Q => \out\(22), Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(23), Q => \out\(23), Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => wr_en0, CLK => aclk, D => \in\(24), Q => \out\(24), Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(25), Q => \out\(25), Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(26), Q => \out\(26), Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(27), Q => \out\(27), Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(28), Q => \out\(28), Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(29), Q => \out\(29), Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(2), Q => \out\(2), Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(30), Q => \out\(30), Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(31), Q => \out\(31), Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(32), Q => \out\(32), Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => wr_en0, CLK => aclk, D => \in\(33), Q => \out\(33), Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(3), Q => \out\(3), Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(4), Q => \out\(4), Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(5), Q => \out\(5), Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__1_n_0\, A(3) => \cnt_read_reg[3]_rep__1_n_0\, A(2) => \cnt_read_reg[2]_rep__1_n_0\, A(1) => \cnt_read_reg[1]_rep__1_n_0\, A(0) => \cnt_read_reg[0]_rep__1_n_0\, CE => wr_en0, CLK => aclk, D => \in\(6), Q => \out\(6), Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(7), Q => \out\(7), Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(8), Q => \out\(8), Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep__0_n_0\, A(3) => \cnt_read_reg[3]_rep__0_n_0\, A(2) => \cnt_read_reg[2]_rep__0_n_0\, A(1) => \cnt_read_reg[1]_rep__0_n_0\, A(0) => \cnt_read_reg[0]_rep__0_n_0\, CE => wr_en0, CLK => aclk, D => \in\(9), Q => \out\(9), Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ ); \state[1]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"40C0C000" ) port map ( I0 => \cnt_read_reg[0]_rep__3_n_0\, I1 => \^cnt_read_reg[4]_rep__2_0\, I2 => \^cnt_read_reg[4]_rep__2_1\, I3 => \cnt_read_reg[1]_rep__2_n_0\, I4 => \cnt_read_reg[2]_rep__2_n_0\, O => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is port ( m_valid_i_reg : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; \skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); s_ready_i_reg : in STD_LOGIC; r_push_r : in STD_LOGIC; si_rs_rready : in STD_LOGIC; \cnt_read_reg[3]_rep__2\ : in STD_LOGIC; \cnt_read_reg[4]_rep__2\ : in STD_LOGIC; \cnt_read_reg[0]_rep__3\ : in STD_LOGIC; \cnt_read_reg[0]_rep__3_0\ : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 12 downto 0 ); aclk : in STD_LOGIC; areset_d1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_17_b2s_simple_fifo"; end \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\; architecture STRUCTURE of \design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ is signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC; signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC; signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC; signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC; signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC; signal m_valid_i_i_3_n_0 : STD_LOGIC; signal \^m_valid_i_reg\ : STD_LOGIC; signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair20"; attribute KEEP : string; attribute KEEP of \cnt_read_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1; attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]"; attribute KEEP of \cnt_read_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]"; attribute KEEP of \cnt_read_reg[2]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]"; attribute KEEP of \cnt_read_reg[3]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]"; attribute KEEP of \cnt_read_reg[4]\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]"; attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1; attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes"; attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]"; attribute srl_bus_name : string; attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name : string; attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 "; attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 "; attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 "; attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 "; attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 "; attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 "; attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 "; attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 "; attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 "; attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 "; attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 "; attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 "; attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] "; attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 "; begin m_valid_i_reg <= \^m_valid_i_reg\; \cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \cnt_read_reg[0]_rep__0_n_0\, I1 => r_push_r, I2 => s_ready_i_reg, O => \cnt_read[0]_i_1__0_n_0\ ); \cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4 generic map( INIT => X"DB24" ) port map ( I0 => \cnt_read_reg[0]_rep__0_n_0\, I1 => s_ready_i_reg, I2 => r_push_r, I3 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[1]_i_1__1_n_0\ ); \cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAA6" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => s_ready_i_reg, I2 => r_push_r, I3 => \cnt_read_reg[0]_rep__0_n_0\, I4 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[2]_i_1__0_n_0\ ); \cnt_read[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF7F0080FEFF0100" ) port map ( I0 => \cnt_read_reg[1]_rep__0_n_0\, I1 => \cnt_read_reg[0]_rep__0_n_0\, I2 => r_push_r, I3 => s_ready_i_reg, I4 => \cnt_read_reg[3]_rep__0_n_0\, I5 => \cnt_read_reg[2]_rep__0_n_0\, O => \cnt_read[3]_i_1_n_0\ ); \cnt_read[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9A999AAA" ) port map ( I0 => \cnt_read_reg[4]_rep__0_n_0\, I1 => \cnt_read[4]_i_2_n_0\, I2 => \cnt_read_reg[2]_rep__0_n_0\, I3 => \cnt_read_reg[3]_rep__0_n_0\, I4 => \cnt_read[4]_i_3_n_0\, O => \cnt_read[4]_i_1__0_n_0\ ); \cnt_read[4]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"2AAAAAAA2AAA2AAA" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => \cnt_read_reg[1]_rep__0_n_0\, I2 => \cnt_read_reg[0]_rep__1_n_0\, I3 => r_push_r, I4 => \^m_valid_i_reg\, I5 => si_rs_rready, O => \cnt_read[4]_i_2_n_0\ ); \cnt_read[4]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000004" ) port map ( I0 => r_push_r, I1 => si_rs_rready, I2 => \^m_valid_i_reg\, I3 => \cnt_read_reg[0]_rep__1_n_0\, I4 => \cnt_read_reg[1]_rep__0_n_0\, O => \cnt_read[4]_i_3_n_0\ ); \cnt_read_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => cnt_read(0), S => areset_d1 ); \cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[0]_i_1__0_n_0\, Q => \cnt_read_reg[0]_rep__1_n_0\, S => areset_d1 ); \cnt_read_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => cnt_read(1), S => areset_d1 ); \cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => \cnt_read_reg[1]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[1]_i_1__1_n_0\, Q => \cnt_read_reg[1]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => cnt_read(2), S => areset_d1 ); \cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => \cnt_read_reg[2]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[2]_i_1__0_n_0\, Q => \cnt_read_reg[2]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => cnt_read(3), S => areset_d1 ); \cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => \cnt_read_reg[3]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[3]_i_1_n_0\, Q => \cnt_read_reg[3]_rep__0_n_0\, S => areset_d1 ); \cnt_read_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => cnt_read(4), S => areset_d1 ); \cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => \cnt_read_reg[4]_rep_n_0\, S => areset_d1 ); \cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \cnt_read[4]_i_1__0_n_0\, Q => \cnt_read_reg[4]_rep__0_n_0\, S => areset_d1 ); m_valid_i_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"80808080FF808080" ) port map ( I0 => \cnt_read_reg[4]_rep__0_n_0\, I1 => \cnt_read_reg[3]_rep__0_n_0\, I2 => m_valid_i_i_3_n_0, I3 => \cnt_read_reg[3]_rep__2\, I4 => \cnt_read_reg[4]_rep__2\, I5 => \cnt_read_reg[0]_rep__3\, O => \^m_valid_i_reg\ ); m_valid_i_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => \cnt_read_reg[2]_rep__0_n_0\, I1 => \cnt_read_reg[0]_rep__1_n_0\, I2 => \cnt_read_reg[1]_rep__0_n_0\, O => m_valid_i_i_3_n_0 ); \memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(0), Q => \skid_buffer_reg[46]\(0), Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(10), Q => \skid_buffer_reg[46]\(10), Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(11), Q => \skid_buffer_reg[46]\(11), Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(12), Q => \skid_buffer_reg[46]\(12), Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(1), Q => \skid_buffer_reg[46]\(1), Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(2), Q => \skid_buffer_reg[46]\(2), Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(3), Q => \skid_buffer_reg[46]\(3), Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(4), Q => \skid_buffer_reg[46]\(4), Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4) => \cnt_read_reg[4]_rep_n_0\, A(3) => \cnt_read_reg[3]_rep_n_0\, A(2) => \cnt_read_reg[2]_rep_n_0\, A(1) => \cnt_read_reg[1]_rep_n_0\, A(0) => \cnt_read_reg[0]_rep_n_0\, CE => r_push_r, CLK => aclk, D => \in\(5), Q => \skid_buffer_reg[46]\(5), Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(6), Q => \skid_buffer_reg[46]\(6), Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(7), Q => \skid_buffer_reg[46]\(7), Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(8), Q => \skid_buffer_reg[46]\(8), Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ ); \memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => cnt_read(4 downto 0), CE => r_push_r, CLK => aclk, D => \in\(9), Q => \skid_buffer_reg[46]\(9), Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ ); \state[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"BFEEAAAAAAAAAAAA" ) port map ( I0 => \cnt_read_reg[0]_rep__3_0\, I1 => \cnt_read_reg[2]_rep__0_n_0\, I2 => \cnt_read_reg[0]_rep__1_n_0\, I3 => \cnt_read_reg[1]_rep__0_n_0\, I4 => \cnt_read_reg[3]_rep__0_n_0\, I5 => \cnt_read_reg[4]_rep__0_n_0\, O => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is port ( \axlen_cnt_reg[7]\ : out STD_LOGIC; \axlen_cnt_reg[7]_0\ : out STD_LOGIC; \axlen_cnt_reg[7]_1\ : out STD_LOGIC; \next\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); D : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axburst_eq0_reg : out STD_LOGIC; incr_next_pending : out STD_LOGIC; sel_first_i : out STD_LOGIC; s_axburst_eq1_reg : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); sel_first_reg : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); b_push : out STD_LOGIC; m_axi_awvalid : out STD_LOGIC; s_axburst_eq1_reg_0 : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; \cnt_read_reg[0]_rep__0\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC; si_rs_awvalid : in STD_LOGIC; \axlen_cnt_reg[7]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axlen_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); wrap_next_pending : in STD_LOGIC; next_pending_r_reg : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; sel_first : in STD_LOGIC; areset_d1 : in STD_LOGIC; sel_first_0 : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[5]\ : in STD_LOGIC; aclk : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm is signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^axlen_cnt_reg[7]\ : STD_LOGIC; signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC; signal \^b_push\ : STD_LOGIC; signal \^incr_next_pending\ : STD_LOGIC; signal \^next\ : STD_LOGIC; signal \^sel_first_i\ : STD_LOGIC; signal \state[0]_i_1_n_0\ : STD_LOGIC; signal \state[0]_i_2_n_0\ : STD_LOGIC; signal \state[1]_i_1__0_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \axlen_cnt[3]_i_1__0\ : label is "soft_lutpair109"; attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair110"; attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair110"; attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair109"; attribute KEEP : string; attribute KEEP of \state_reg[0]\ : label is "yes"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]"; attribute IS_FANOUT_CONSTRAINED : integer; attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1; attribute KEEP of \state_reg[0]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]"; attribute KEEP of \state_reg[1]\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]"; attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1; attribute KEEP of \state_reg[1]_rep\ : label is "yes"; attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair108"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_4\ : label is "soft_lutpair111"; attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_6\ : label is "soft_lutpair111"; begin E(0) <= \^e\(0); Q(1 downto 0) <= \^q\(1 downto 0); \axlen_cnt_reg[7]\ <= \^axlen_cnt_reg[7]\; \axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\; b_push <= \^b_push\; incr_next_pending <= \^incr_next_pending\; \next\ <= \^next\; sel_first_i <= \^sel_first_i\; \axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAACAAAAAAA0AA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \m_payload_i_reg[46]\(2), I2 => \^axlen_cnt_reg[7]_0\, I3 => si_rs_awvalid, I4 => \^axlen_cnt_reg[7]\, I5 => \m_payload_i_reg[5]\, O => \axaddr_offset_r_reg[2]\(0) ); \axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0400FFFF04000400" ) port map ( I0 => \^q\(1), I1 => si_rs_awvalid, I2 => \^q\(0), I3 => \m_payload_i_reg[46]\(1), I4 => \axlen_cnt_reg[0]_0\(0), I5 => \axlen_cnt_reg[7]_2\, O => \axlen_cnt_reg[0]\(0) ); \axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FF04" ) port map ( I0 => \^q\(0), I1 => si_rs_awvalid, I2 => \^q\(1), I3 => \^next\, O => \axaddr_wrap_reg[11]\(0) ); \axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF04" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]\, I3 => \^next\, I4 => \axlen_cnt_reg[7]_2\, O => \axlen_cnt_reg[7]_1\ ); m_axi_awvalid_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => \^axlen_cnt_reg[7]\, O => m_axi_awvalid ); \m_payload_i[31]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^b_push\, I1 => si_rs_awvalid, O => \m_payload_i_reg[0]\(0) ); \memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"88008888A800A8A8" ) port map ( I0 => \^axlen_cnt_reg[7]_0\, I1 => \^axlen_cnt_reg[7]\, I2 => m_axi_awready, I3 => \cnt_read_reg[0]_rep__0\, I4 => \cnt_read_reg[1]_rep__0\, I5 => s_axburst_eq1_reg_0, O => \^b_push\ ); next_pending_r_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFF404" ) port map ( I0 => \^e\(0), I1 => next_pending_r_reg, I2 => \^next\, I3 => \axlen_cnt_reg[7]_2\, I4 => \m_payload_i_reg[47]\, O => \^incr_next_pending\ ); next_pending_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"F3F3FFFF51000000" ) port map ( I0 => s_axburst_eq1_reg_0, I1 => \cnt_read_reg[1]_rep__0\, I2 => \cnt_read_reg[0]_rep__0\, I3 => m_axi_awready, I4 => \^axlen_cnt_reg[7]_0\, I5 => \^axlen_cnt_reg[7]\, O => \^next\ ); s_axburst_eq0_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"BA8A" ) port map ( I0 => \^incr_next_pending\, I1 => \^sel_first_i\, I2 => \m_payload_i_reg[46]\(0), I3 => wrap_next_pending, O => s_axburst_eq0_reg ); s_axburst_eq1_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FE02" ) port map ( I0 => \^incr_next_pending\, I1 => \m_payload_i_reg[46]\(0), I2 => \^sel_first_i\, I3 => wrap_next_pending, O => s_axburst_eq1_reg ); sel_first_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF44444F44" ) port map ( I0 => \^next\, I1 => sel_first, I2 => \^q\(1), I3 => si_rs_awvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg ); \sel_first_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF44444F44" ) port map ( I0 => \^next\, I1 => sel_first_0, I2 => \^q\(1), I3 => si_rs_awvalid, I4 => \^q\(0), I5 => areset_d1, O => sel_first_reg_0 ); \sel_first_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF04FFFFFF04FF04" ) port map ( I0 => \^axlen_cnt_reg[7]\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]_0\, I3 => areset_d1, I4 => \^next\, I5 => sel_first_reg_1, O => \^sel_first_i\ ); \state[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BBBA" ) port map ( I0 => \state[0]_i_2_n_0\, I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), O => \state[0]_i_1_n_0\ ); \state[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00F000F055750000" ) port map ( I0 => m_axi_awready, I1 => s_axburst_eq1_reg_0, I2 => \cnt_read_reg[1]_rep__0\, I3 => \cnt_read_reg[0]_rep__0\, I4 => \^axlen_cnt_reg[7]_0\, I5 => \^axlen_cnt_reg[7]\, O => \state[0]_i_2_n_0\ ); \state[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0C0CAE0000000000" ) port map ( I0 => s_axburst_eq1_reg_0, I1 => \cnt_read_reg[1]_rep__0\, I2 => \cnt_read_reg[0]_rep__0\, I3 => m_axi_awready, I4 => \^axlen_cnt_reg[7]\, I5 => \^axlen_cnt_reg[7]_0\, O => \state[1]_i_1__0_n_0\ ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[0]_i_1_n_0\, Q => \^q\(0), R => areset_d1 ); \state_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[0]_i_1_n_0\, Q => \^axlen_cnt_reg[7]_0\, R => areset_d1 ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[1]_i_1__0_n_0\, Q => \^q\(1), R => areset_d1 ); \state_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \state[1]_i_1__0_n_0\, Q => \^axlen_cnt_reg[7]\, R => areset_d1 ); \wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \^axlen_cnt_reg[7]\, I1 => si_rs_awvalid, I2 => \^axlen_cnt_reg[7]_0\, O => \^e\(0) ); \wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8A5575AA8A5545" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => D(0) ); \wrap_cnt_r[3]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(1), I1 => \^axlen_cnt_reg[7]_0\, I2 => si_rs_awvalid, I3 => \^axlen_cnt_reg[7]\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\(0), I1 => \^axlen_cnt_reg[7]_0\, I2 => si_rs_awvalid, I3 => \^axlen_cnt_reg[7]\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AA8AAA8AAA8AAABA" ) port map ( I0 => \wrap_second_len_r_reg[0]_0\(0), I1 => \^q\(0), I2 => si_rs_awvalid, I3 => \^q\(1), I4 => \axaddr_offset_r_reg[3]\, I5 => axaddr_offset(0), O => \wrap_second_len_r_reg[0]\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is port ( wrap_next_pending : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_awvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \next\ : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 10 downto 0 ); sel_first_reg_3 : in STD_LOGIC; \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd is signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 ); signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC; signal \axlen_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \next_pending_r_i_2__1_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \^sel_first_reg_0\ : STD_LOGIC; signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 1 to 1 ); signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^wrap_next_pending\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); begin sel_first_reg_0 <= \^sel_first_reg_0\; wrap_next_pending <= \^wrap_next_pending\; \wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0); \axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => \axaddr_offset_r_reg[3]_0\(0), R => '0' ); \axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => \axaddr_offset_r_reg[3]_0\(1), R => '0' ); \axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => \axaddr_offset_r_reg[3]_0\(2), R => '0' ); \axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => \axaddr_offset_r_reg[3]_0\(3), R => '0' ); \axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(0), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(0), I3 => \next\, I4 => \m_payload_i_reg[47]\(0), O => \axaddr_wrap[0]_i_1_n_0\ ); \axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(10), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(10), I3 => \next\, I4 => \m_payload_i_reg[47]\(10), O => \axaddr_wrap[10]_i_1_n_0\ ); \axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(11), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(11), I3 => \next\, I4 => \m_payload_i_reg[47]\(11), O => \axaddr_wrap[11]_i_1_n_0\ ); \axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"41" ) port map ( I0 => \axaddr_wrap[11]_i_4_n_0\, I1 => wrap_cnt_r(3), I2 => \axlen_cnt_reg_n_0_[3]\, O => \axaddr_wrap[11]_i_2_n_0\ ); \axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"6FF6FFFFFFFF6FF6" ) port map ( I0 => wrap_cnt_r(0), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => wrap_cnt_r(1), I4 => \axlen_cnt_reg_n_0_[2]\, I5 => wrap_cnt_r(2), O => \axaddr_wrap[11]_i_4_n_0\ ); \axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(1), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(1), I3 => \next\, I4 => \m_payload_i_reg[47]\(1), O => \axaddr_wrap[1]_i_1_n_0\ ); \axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(2), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(2), I3 => \next\, I4 => \m_payload_i_reg[47]\(2), O => \axaddr_wrap[2]_i_1_n_0\ ); \axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(3), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(3), I3 => \next\, I4 => \m_payload_i_reg[47]\(3), O => \axaddr_wrap[3]_i_1_n_0\ ); \axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => axaddr_wrap(3), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_3_n_0\ ); \axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => axaddr_wrap(2), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_4_n_0\ ); \axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => axaddr_wrap(1), I1 => \m_payload_i_reg[47]\(13), I2 => \m_payload_i_reg[47]\(12), O => \axaddr_wrap[3]_i_5_n_0\ ); \axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => axaddr_wrap(0), I1 => \m_payload_i_reg[47]\(12), I2 => \m_payload_i_reg[47]\(13), O => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(4), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(4), I3 => \next\, I4 => \m_payload_i_reg[47]\(4), O => \axaddr_wrap[4]_i_1_n_0\ ); \axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(5), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(5), I3 => \next\, I4 => \m_payload_i_reg[47]\(5), O => \axaddr_wrap[5]_i_1_n_0\ ); \axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(6), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(6), I3 => \next\, I4 => \m_payload_i_reg[47]\(6), O => \axaddr_wrap[6]_i_1_n_0\ ); \axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(7), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(7), I3 => \next\, I4 => \m_payload_i_reg[47]\(7), O => \axaddr_wrap[7]_i_1_n_0\ ); \axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(8), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(8), I3 => \next\, I4 => \m_payload_i_reg[47]\(8), O => \axaddr_wrap[8]_i_1_n_0\ ); \axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => wrap_boundary_axaddr_r(9), I1 => \axaddr_wrap[11]_i_2_n_0\, I2 => axaddr_wrap0(9), I3 => \next\, I4 => \m_payload_i_reg[47]\(9), O => \axaddr_wrap[9]_i_1_n_0\ ); \axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[0]_i_1_n_0\, Q => axaddr_wrap(0), R => '0' ); \axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[10]_i_1_n_0\, Q => axaddr_wrap(10), R => '0' ); \axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[11]_i_1_n_0\, Q => axaddr_wrap(11), R => '0' ); \axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[7]_i_2_n_0\, CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3), CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\, CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\, CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_wrap0(11 downto 8), S(3 downto 0) => axaddr_wrap(11 downto 8) ); \axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[1]_i_1_n_0\, Q => axaddr_wrap(1), R => '0' ); \axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[2]_i_1_n_0\, Q => axaddr_wrap(2), R => '0' ); \axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[3]_i_1_n_0\, Q => axaddr_wrap(3), R => '0' ); \axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\, CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\, CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\, CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => axaddr_wrap(3 downto 0), O(3 downto 0) => axaddr_wrap0(3 downto 0), S(3) => \axaddr_wrap[3]_i_3_n_0\, S(2) => \axaddr_wrap[3]_i_4_n_0\, S(1) => \axaddr_wrap[3]_i_5_n_0\, S(0) => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[4]_i_1_n_0\, Q => axaddr_wrap(4), R => '0' ); \axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[5]_i_1_n_0\, Q => axaddr_wrap(5), R => '0' ); \axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[6]_i_1_n_0\, Q => axaddr_wrap(6), R => '0' ); \axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[7]_i_1_n_0\, Q => axaddr_wrap(7), R => '0' ); \axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[3]_i_2_n_0\, CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\, CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\, CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\, CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_wrap0(7 downto 4), S(3 downto 0) => axaddr_wrap(7 downto 4) ); \axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[8]_i_1_n_0\, Q => axaddr_wrap(8), R => '0' ); \axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axaddr_wrap[9]_i_1_n_0\, Q => axaddr_wrap(9), R => '0' ); \axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"A3A3A3A3A3A3A3A0" ) port map ( I0 => \m_payload_i_reg[47]\(15), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => E(0), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \axlen_cnt[0]_i_1_n_0\ ); \axlen_cnt[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAC3AAC3AAC3AAC0" ) port map ( I0 => \m_payload_i_reg[47]\(16), I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => E(0), I4 => \axlen_cnt_reg_n_0_[3]\, I5 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[1]_i_1_n_0\ ); \axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA9A80000A9A8" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => E(0), I5 => \m_payload_i_reg[47]\(17), O => \axlen_cnt[2]_i_1__0_n_0\ ); \axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAACCCCCCC0" ) port map ( I0 => \m_payload_i_reg[47]\(18), I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[0]\, I5 => E(0), O => \axlen_cnt[3]_i_1_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[0]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[1]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[2]_i_1__0_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \state_reg[0]\(0), D => \axlen_cnt[3]_i_1_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(0), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(0), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(0), O => m_axi_awaddr(0) ); \m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(10), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(10), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(9), O => m_axi_awaddr(10) ); \m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(11), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(11), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(10), O => m_axi_awaddr(11) ); \m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(1), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(1), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(1), O => m_axi_awaddr(1) ); \m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(2), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(2), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(2), O => m_axi_awaddr(2) ); \m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(3), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(3), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(3), O => m_axi_awaddr(3) ); \m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(4), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(4), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(4), O => m_axi_awaddr(4) ); \m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \m_payload_i_reg[47]\(5), I1 => \^sel_first_reg_0\, I2 => axaddr_wrap(5), I3 => \m_payload_i_reg[47]\(14), I4 => sel_first_reg_3, O => m_axi_awaddr(5) ); \m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(6), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(6), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(5), O => m_axi_awaddr(6) ); \m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(7), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(7), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(6), O => m_axi_awaddr(7) ); \m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(8), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(8), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(7), O => m_axi_awaddr(8) ); \m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => axaddr_wrap(9), I2 => \m_payload_i_reg[47]\(14), I3 => \m_payload_i_reg[47]\(9), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(8), O => m_axi_awaddr(9) ); \next_pending_r_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FEAAFEAE" ) port map ( I0 => \m_payload_i_reg[47]_0\, I1 => next_pending_r_reg_n_0, I2 => \next\, I3 => \next_pending_r_i_2__1_n_0\, I4 => E(0), O => \^wrap_next_pending\ ); \next_pending_r_i_2__1\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBFBFBFBFBFB00" ) port map ( I0 => \state_reg[1]\(0), I1 => si_rs_awvalid, I2 => \state_reg[1]\(1), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \next_pending_r_i_2__1_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \^wrap_next_pending\, Q => next_pending_r_reg_n_0, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_1, Q => \^sel_first_reg_0\, R => '0' ); \wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(0), Q => wrap_boundary_axaddr_r(0), R => '0' ); \wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(10), Q => wrap_boundary_axaddr_r(10), R => '0' ); \wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(11), Q => wrap_boundary_axaddr_r(11), R => '0' ); \wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(1), Q => wrap_boundary_axaddr_r(1), R => '0' ); \wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(2), Q => wrap_boundary_axaddr_r(2), R => '0' ); \wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(3), Q => wrap_boundary_axaddr_r(3), R => '0' ); \wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(4), Q => wrap_boundary_axaddr_r(4), R => '0' ); \wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(5), Q => wrap_boundary_axaddr_r(5), R => '0' ); \wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(6), Q => wrap_boundary_axaddr_r(6), R => '0' ); \wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(7), Q => wrap_boundary_axaddr_r(7), R => '0' ); \wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(8), Q => wrap_boundary_axaddr_r(8), R => '0' ); \wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[47]\(9), Q => wrap_boundary_axaddr_r(9), R => '0' ); \wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"3D310E02" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(0), I1 => E(0), I2 => \axaddr_offset_r_reg[3]_2\, I3 => D(1), I4 => \^wrap_second_len_r_reg[3]_0\(1), O => wrap_cnt(1) ); \wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"000CAAA8000C0000" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(1), I1 => \axaddr_offset_r_reg[3]_1\, I2 => D(1), I3 => D(0), I4 => E(0), I5 => \^wrap_second_len_r_reg[3]_0\(0), O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(0), Q => wrap_cnt_r(0), R => '0' ); \wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cnt(1), Q => wrap_cnt_r(1), R => '0' ); \wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(1), Q => wrap_cnt_r(2), R => '0' ); \wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(2), Q => wrap_cnt_r(3), R => '0' ); \wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(0), Q => \^wrap_second_len_r_reg[3]_0\(0), R => '0' ); \wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(1), Q => \^wrap_second_len_r_reg[3]_0\(1), R => '0' ); \wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(2), Q => \^wrap_second_len_r_reg[3]_0\(2), R => '0' ); \wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(3), Q => \^wrap_second_len_r_reg[3]_0\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is port ( sel_first_reg_0 : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axburst_eq0_reg : out STD_LOGIC; s_axburst_eq1_reg : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 18 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_arvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); sel_first_i : in STD_LOGIC; incr_next_pending : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; \axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); sel_first_reg_3 : in STD_LOGIC; sel_first_reg_4 : in STD_LOGIC; sel_first_reg_5 : in STD_LOGIC; sel_first_reg_6 : in STD_LOGIC; \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_17_b2s_wrap_cmd"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 is signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC; signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC; signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC; signal \axlen_cnt[0]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC; signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC; signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC; signal \next_pending_r_i_2__2_n_0\ : STD_LOGIC; signal next_pending_r_reg_n_0 : STD_LOGIC; signal \^sel_first_reg_0\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC; signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC; signal wrap_next_pending : STD_LOGIC; signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair16"; begin sel_first_reg_0 <= \^sel_first_reg_0\; \wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0); \axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => \axaddr_offset_r_reg[3]_0\(0), R => '0' ); \axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => \axaddr_offset_r_reg[3]_0\(1), R => '0' ); \axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => \axaddr_offset_r_reg[3]_0\(2), R => '0' ); \axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => \axaddr_offset_r_reg[3]_0\(3), R => '0' ); \axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(0), O => \axaddr_wrap[0]_i_1__0_n_0\ ); \axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(10), O => \axaddr_wrap[10]_i_1__0_n_0\ ); \axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(11), O => \axaddr_wrap[11]_i_1__0_n_0\ ); \axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"41" ) port map ( I0 => \axaddr_wrap[11]_i_4__0_n_0\, I1 => \wrap_cnt_r_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[3]\, O => \axaddr_wrap[11]_i_2__0_n_0\ ); \axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"6FF6FFFFFFFF6FF6" ) port map ( I0 => \wrap_cnt_r_reg_n_0_[0]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \wrap_cnt_r_reg_n_0_[2]\, I4 => \axlen_cnt_reg_n_0_[1]\, I5 => \wrap_cnt_r_reg_n_0_[1]\, O => \axaddr_wrap[11]_i_4__0_n_0\ ); \axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(1), O => \axaddr_wrap[1]_i_1__0_n_0\ ); \axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(2), O => \axaddr_wrap[2]_i_1__0_n_0\ ); \axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(3), O => \axaddr_wrap[3]_i_1__0_n_0\ ); \axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[3]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_3_n_0\ ); \axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[2]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_4_n_0\ ); \axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \axaddr_wrap_reg_n_0_[1]\, I1 => Q(13), I2 => Q(12), O => \axaddr_wrap[3]_i_5_n_0\ ); \axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"A9" ) port map ( I0 => \axaddr_wrap_reg_n_0_[0]\, I1 => Q(12), I2 => Q(13), O => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(4), O => \axaddr_wrap[4]_i_1__0_n_0\ ); \axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(5), O => \axaddr_wrap[5]_i_1__0_n_0\ ); \axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\, I3 => \state_reg[1]_rep\, I4 => Q(6), O => \axaddr_wrap[6]_i_1__0_n_0\ ); \axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\, I3 => \state_reg[1]_rep\, I4 => Q(7), O => \axaddr_wrap[7]_i_1__0_n_0\ ); \axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\, I3 => \state_reg[1]_rep\, I4 => Q(8), O => \axaddr_wrap[8]_i_1__0_n_0\ ); \axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\, I1 => \axaddr_wrap[11]_i_2__0_n_0\, I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\, I3 => \state_reg[1]_rep\, I4 => Q(9), O => \axaddr_wrap[9]_i_1__0_n_0\ ); \axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[0]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[0]\, R => '0' ); \axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[10]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[10]\, R => '0' ); \axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[11]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[11]\, R => '0' ); \axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[7]_i_2__0_n_0\, CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\, CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\, CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\, O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\, O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\, O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\, S(3) => \axaddr_wrap_reg_n_0_[11]\, S(2) => \axaddr_wrap_reg_n_0_[10]\, S(1) => \axaddr_wrap_reg_n_0_[9]\, S(0) => \axaddr_wrap_reg_n_0_[8]\ ); \axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[1]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[1]\, R => '0' ); \axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[2]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[2]\, R => '0' ); \axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[3]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[3]\, R => '0' ); \axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\, CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\, CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\, CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\, CYINIT => '0', DI(3) => \axaddr_wrap_reg_n_0_[3]\, DI(2) => \axaddr_wrap_reg_n_0_[2]\, DI(1) => \axaddr_wrap_reg_n_0_[1]\, DI(0) => \axaddr_wrap_reg_n_0_[0]\, O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\, O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\, O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\, O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\, S(3) => \axaddr_wrap[3]_i_3_n_0\, S(2) => \axaddr_wrap[3]_i_4_n_0\, S(1) => \axaddr_wrap[3]_i_5_n_0\, S(0) => \axaddr_wrap[3]_i_6_n_0\ ); \axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[4]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[4]\, R => '0' ); \axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[5]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[5]\, R => '0' ); \axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[6]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[6]\, R => '0' ); \axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[7]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[7]\, R => '0' ); \axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_wrap_reg[3]_i_2__0_n_0\, CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\, CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\, CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\, CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\, O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\, O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\, O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\, S(3) => \axaddr_wrap_reg_n_0_[7]\, S(2) => \axaddr_wrap_reg_n_0_[6]\, S(1) => \axaddr_wrap_reg_n_0_[5]\, S(0) => \axaddr_wrap_reg_n_0_[4]\ ); \axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[8]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[8]\, R => '0' ); \axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axaddr_wrap[9]_i_1__0_n_0\, Q => \axaddr_wrap_reg_n_0_[9]\, R => '0' ); \axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"A3A3A3A3A3A3A3A0" ) port map ( I0 => Q(15), I1 => \axlen_cnt_reg_n_0_[0]\, I2 => E(0), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \axlen_cnt[0]_i_1__1_n_0\ ); \axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"AAC3AAC3AAC3AAC0" ) port map ( I0 => Q(16), I1 => \axlen_cnt_reg_n_0_[1]\, I2 => \axlen_cnt_reg_n_0_[0]\, I3 => E(0), I4 => \axlen_cnt_reg_n_0_[3]\, I5 => \axlen_cnt_reg_n_0_[2]\, O => \axlen_cnt[1]_i_1__2_n_0\ ); \axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA9A80000A9A8" ) port map ( I0 => \axlen_cnt_reg_n_0_[2]\, I1 => \axlen_cnt_reg_n_0_[0]\, I2 => \axlen_cnt_reg_n_0_[1]\, I3 => \axlen_cnt_reg_n_0_[3]\, I4 => E(0), I5 => Q(17), O => \axlen_cnt[2]_i_1__2_n_0\ ); \axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAACCCCCCC0" ) port map ( I0 => Q(18), I1 => \axlen_cnt_reg_n_0_[3]\, I2 => \axlen_cnt_reg_n_0_[2]\, I3 => \axlen_cnt_reg_n_0_[1]\, I4 => \axlen_cnt_reg_n_0_[0]\, I5 => E(0), O => \axlen_cnt[3]_i_1__1_n_0\ ); \axlen_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[0]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[0]\, R => '0' ); \axlen_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[1]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[1]\, R => '0' ); \axlen_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[2]_i_1__2_n_0\, Q => \axlen_cnt_reg_n_0_[2]\, R => '0' ); \axlen_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg(0), D => \axlen_cnt[3]_i_1__1_n_0\, Q => \axlen_cnt_reg_n_0_[3]\, R => '0' ); \m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[0]\, I2 => Q(14), I3 => Q(0), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(0), O => m_axi_araddr(0) ); \m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[10]\, I2 => Q(14), I3 => Q(10), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(6), O => m_axi_araddr(10) ); \m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[11]\, I2 => Q(14), I3 => Q(11), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(7), O => m_axi_araddr(11) ); \m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(1), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[1]\, I3 => Q(14), I4 => sel_first_reg_6, O => m_axi_araddr(1) ); \m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(2), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[2]\, I3 => Q(14), I4 => sel_first_reg_5, O => m_axi_araddr(2) ); \m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(3), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[3]\, I3 => Q(14), I4 => sel_first_reg_4, O => m_axi_araddr(3) ); \m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[4]\, I2 => Q(14), I3 => Q(4), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(1), O => m_axi_araddr(4) ); \m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8FFB800" ) port map ( I0 => Q(5), I1 => \^sel_first_reg_0\, I2 => \axaddr_wrap_reg_n_0_[5]\, I3 => Q(14), I4 => sel_first_reg_3, O => m_axi_araddr(5) ); \m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[6]\, I2 => Q(14), I3 => Q(6), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(2), O => m_axi_araddr(6) ); \m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[7]\, I2 => Q(14), I3 => Q(7), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(3), O => m_axi_araddr(7) ); \m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[8]\, I2 => Q(14), I3 => Q(8), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(4), O => m_axi_araddr(8) ); \m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"EF40EF4FEF40E040" ) port map ( I0 => \^sel_first_reg_0\, I1 => \axaddr_wrap_reg_n_0_[9]\, I2 => Q(14), I3 => Q(9), I4 => sel_first_reg_2, I5 => \axaddr_incr_reg[11]\(5), O => m_axi_araddr(9) ); \next_pending_r_i_1__1\: unisim.vcomponents.LUT5 generic map( INIT => X"FEAAFEAE" ) port map ( I0 => \m_payload_i_reg[47]\, I1 => next_pending_r_reg_n_0, I2 => \state_reg[1]_rep\, I3 => \next_pending_r_i_2__2_n_0\, I4 => E(0), O => wrap_next_pending ); \next_pending_r_i_2__2\: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBFBFBFBFBFB00" ) port map ( I0 => \state_reg[1]\(0), I1 => si_rs_arvalid, I2 => \state_reg[1]\(1), I3 => \axlen_cnt_reg_n_0_[3]\, I4 => \axlen_cnt_reg_n_0_[2]\, I5 => \axlen_cnt_reg_n_0_[1]\, O => \next_pending_r_i_2__2_n_0\ ); next_pending_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_next_pending, Q => next_pending_r_reg_n_0, R => '0' ); \s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => wrap_next_pending, I1 => Q(14), I2 => sel_first_i, I3 => incr_next_pending, O => s_axburst_eq0_reg ); \s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"ABA8" ) port map ( I0 => wrap_next_pending, I1 => Q(14), I2 => sel_first_i, I3 => incr_next_pending, O => s_axburst_eq1_reg ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_reg_1, Q => \^sel_first_reg_0\, R => '0' ); \wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(0), Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\, R => '0' ); \wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(10), Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\, R => '0' ); \wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(11), Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\, R => '0' ); \wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(1), Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\, R => '0' ); \wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(2), Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\, R => '0' ); \wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(3), Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\, R => '0' ); \wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(4), Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\, R => '0' ); \wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(5), Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\, R => '0' ); \wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => \m_payload_i_reg[6]\(6), Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\, R => '0' ); \wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(7), Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\, R => '0' ); \wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(8), Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\, R => '0' ); \wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => Q(9), Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\, R => '0' ); \wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"3D310E02" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(0), I1 => E(0), I2 => \axaddr_offset_r_reg[3]_2\, I3 => D(1), I4 => \^wrap_second_len_r_reg[3]_0\(1), O => \wrap_cnt_r[1]_i_1__0_n_0\ ); \wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"000CAAA8000C0000" ) port map ( I0 => \^wrap_second_len_r_reg[3]_0\(1), I1 => \axaddr_offset_r_reg[3]_1\, I2 => D(1), I3 => D(0), I4 => E(0), I5 => \^wrap_second_len_r_reg[3]_0\(0), O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(0), Q => \wrap_cnt_r_reg_n_0_[0]\, R => '0' ); \wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_cnt_r[1]_i_1__0_n_0\, Q => \wrap_cnt_r_reg_n_0_[1]\, R => '0' ); \wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(1), Q => \wrap_cnt_r_reg_n_0_[2]\, R => '0' ); \wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_2\(2), Q => \wrap_cnt_r_reg_n_0_[3]\, R => '0' ); \wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(0), Q => \^wrap_second_len_r_reg[3]_0\(0), R => '0' ); \wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(1), Q => \^wrap_second_len_r_reg[3]_0\(1), R => '0' ); \wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(2), Q => \^wrap_second_len_r_reg[3]_0\(2), R => '0' ); \wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \wrap_second_len_r_reg[3]_1\(3), Q => \^wrap_second_len_r_reg[3]_0\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice is port ( s_axi_arready : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC; m_valid_i_reg_0 : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); O : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; \axaddr_offset_r_reg[0]\ : out STD_LOGIC; axaddr_offset_0 : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \aresetn_d_reg[0]\ : in STD_LOGIC; s_ready_i0 : in STD_LOGIC; aclk : in STD_LOGIC; m_valid_i0 : in STD_LOGIC; \aresetn_d_reg[0]_0\ : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice; architecture STRUCTURE of design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice is signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 ); signal \axaddr_incr[3]_i_4__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_5__0_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_6__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2__0_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2__0_n_3\ : STD_LOGIC; signal \^axaddr_offset_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC; signal \axaddr_offset_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC; signal \^axlen_cnt_reg[3]\ : STD_LOGIC; signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC; signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[52]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal \^s_axi_arready\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \wrap_cnt_r[3]_i_5__0_n_0\ : STD_LOGIC; signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_3__0_n_0\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \m_payload_i[52]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair21"; begin Q(54 downto 0) <= \^q\(54 downto 0); axaddr_offset_0(1 downto 0) <= \^axaddr_offset_0\(1 downto 0); \axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\; \axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\; \axaddr_offset_r_reg[3]\ <= \^axaddr_offset_r_reg[3]\; \axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; s_axi_arready <= \^s_axi_arready\; \wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\; \wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0); \aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => aclk, CE => '1', D => \aresetn_d_reg[0]_0\, Q => \^m_valid_i_reg_0\, R => '0' ); \axaddr_incr[3]_i_4__0\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => \^q\(2), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_4__0_n_0\ ); \axaddr_incr[3]_i_5__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(1), I1 => \^q\(36), O => \axaddr_incr[3]_i_5__0_n_0\ ); \axaddr_incr[3]_i_6__0\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_6__0_n_0\ ); \axaddr_incr_reg[11]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_2__0_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_3__0_n_1\, CO(1) => \axaddr_incr_reg[11]_i_3__0_n_2\, CO(0) => \axaddr_incr_reg[11]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => O(3 downto 0), S(3 downto 0) => \^q\(11 downto 8) ); \axaddr_incr_reg[3]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_2__0_n_0\, CO(2) => \axaddr_incr_reg[3]_i_2__0_n_1\, CO(1) => \axaddr_incr_reg[3]_i_2__0_n_2\, CO(0) => \axaddr_incr_reg[3]_i_2__0_n_3\, CYINIT => '0', DI(3) => \^q\(3), DI(2) => \axaddr_incr[3]_i_4__0_n_0\, DI(1) => \axaddr_incr[3]_i_5__0_n_0\, DI(0) => \axaddr_incr[3]_i_6__0_n_0\, O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0) ); \axaddr_incr_reg[7]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_2__0_n_0\, CO(3) => \axaddr_incr_reg[7]_i_2__0_n_0\, CO(2) => \axaddr_incr_reg[7]_i_2__0_n_1\, CO(1) => \axaddr_incr_reg[7]_i_2__0_n_2\, CO(0) => \axaddr_incr_reg[7]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), S(3 downto 0) => \^q\(7 downto 4) ); \axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[0]_i_2__0_n_0\, I1 => \^q\(39), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(0), O => \^axaddr_offset_r_reg[0]\ ); \axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(3), I1 => \^q\(2), I2 => \^q\(36), I3 => \^q\(1), I4 => \^q\(35), I5 => \^q\(0), O => \axaddr_offset_r[0]_i_2__0_n_0\ ); \axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[1]_i_2__0_n_0\, I1 => \^q\(40), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(1), O => \^axaddr_offset_0\(0) ); \axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(4), I1 => \^q\(3), I2 => \^q\(36), I3 => \^q\(2), I4 => \^q\(35), I5 => \^q\(1), O => \axaddr_offset_r[1]_i_2__0_n_0\ ); \axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(5), I1 => \^q\(4), I2 => \^q\(36), I3 => \^q\(3), I4 => \^q\(35), I5 => \^q\(2), O => \^axaddr_offset_r_reg[2]\ ); \axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[3]_i_2__0_n_0\, I1 => \^q\(42), I2 => \state_reg[1]\(1), I3 => \^axaddr_offset_r_reg[3]\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]_0\(2), O => \^axaddr_offset_0\(1) ); \axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(6), I1 => \^q\(5), I2 => \^q\(36), I3 => \^q\(4), I4 => \^q\(35), I5 => \^q\(3), O => \axaddr_offset_r[3]_i_2__0_n_0\ ); \axlen_cnt[3]_i_3__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0020" ) port map ( I0 => \^q\(42), I1 => \state_reg[1]\(0), I2 => \^axaddr_offset_r_reg[3]\, I3 => \state_reg[1]\(1), O => \^axlen_cnt_reg[3]\ ); \m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__0_n_0\ ); \m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(10), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__0_n_0\ ); \m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(11), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__0_n_0\ ); \m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(12), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__0_n_0\ ); \m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(13), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_1__1_n_0\ ); \m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(14), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[14]\, O => \m_payload_i[14]_i_1__0_n_0\ ); \m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(15), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[15]\, O => \m_payload_i[15]_i_1__0_n_0\ ); \m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(16), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[16]\, O => \m_payload_i[16]_i_1__0_n_0\ ); \m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(17), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[17]\, O => \m_payload_i[17]_i_1__0_n_0\ ); \m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(18), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[18]\, O => \m_payload_i[18]_i_1__0_n_0\ ); \m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(19), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[19]\, O => \m_payload_i[19]_i_1__0_n_0\ ); \m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__0_n_0\ ); \m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(20), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[20]\, O => \m_payload_i[20]_i_1__0_n_0\ ); \m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(21), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[21]\, O => \m_payload_i[21]_i_1__0_n_0\ ); \m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(22), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[22]\, O => \m_payload_i[22]_i_1__0_n_0\ ); \m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(23), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[23]\, O => \m_payload_i[23]_i_1__0_n_0\ ); \m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(24), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[24]\, O => \m_payload_i[24]_i_1__0_n_0\ ); \m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(25), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[25]\, O => \m_payload_i[25]_i_1__0_n_0\ ); \m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(26), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[26]\, O => \m_payload_i[26]_i_1__0_n_0\ ); \m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(27), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[27]\, O => \m_payload_i[27]_i_1__0_n_0\ ); \m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(28), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[28]\, O => \m_payload_i[28]_i_1__0_n_0\ ); \m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(29), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[29]\, O => \m_payload_i[29]_i_1__0_n_0\ ); \m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__0_n_0\ ); \m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(30), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[30]\, O => \m_payload_i[30]_i_1__0_n_0\ ); \m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(31), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[31]\, O => \m_payload_i[31]_i_2__0_n_0\ ); \m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[32]\, O => \m_payload_i[32]_i_1__0_n_0\ ); \m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[33]\, O => \m_payload_i[33]_i_1__0_n_0\ ); \m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arprot(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[34]\, O => \m_payload_i[34]_i_1__0_n_0\ ); \m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arsize(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[35]\, O => \m_payload_i[35]_i_1__0_n_0\ ); \m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arsize(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[36]\, O => \m_payload_i[36]_i_1__0_n_0\ ); \m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arburst(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[38]\, O => \m_payload_i[38]_i_1__0_n_0\ ); \m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arburst(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[39]\, O => \m_payload_i[39]_i_1__0_n_0\ ); \m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__0_n_0\ ); \m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[44]\, O => \m_payload_i[44]_i_1__0_n_0\ ); \m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[45]\, O => \m_payload_i[45]_i_1__0_n_0\ ); \m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[46]\, O => \m_payload_i[46]_i_1__1_n_0\ ); \m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arlen(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[47]\, O => \m_payload_i[47]_i_1__0_n_0\ ); \m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(4), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__0_n_0\ ); \m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(0), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[50]\, O => \m_payload_i[50]_i_1__0_n_0\ ); \m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(1), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[51]\, O => \m_payload_i[51]_i_1__0_n_0\ ); \m_payload_i[52]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(2), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[52]\, O => \m_payload_i[52]_i_1__0_n_0\ ); \m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(3), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[53]\, O => \m_payload_i[53]_i_1__0_n_0\ ); \m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(4), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[54]\, O => \m_payload_i[54]_i_1__0_n_0\ ); \m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(5), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[55]\, O => \m_payload_i[55]_i_1__0_n_0\ ); \m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(6), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[56]\, O => \m_payload_i[56]_i_1__0_n_0\ ); \m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(7), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[57]\, O => \m_payload_i[57]_i_1__0_n_0\ ); \m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(8), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[58]\, O => \m_payload_i[58]_i_1__0_n_0\ ); \m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(9), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[59]\, O => \m_payload_i[59]_i_1__0_n_0\ ); \m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(5), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__0_n_0\ ); \m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(10), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[60]\, O => \m_payload_i[60]_i_1__0_n_0\ ); \m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_arid(11), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[61]\, O => \m_payload_i[61]_i_1__0_n_0\ ); \m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(6), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__0_n_0\ ); \m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(7), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__0_n_0\ ); \m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(8), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__0_n_0\ ); \m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_araddr(9), I1 => \^s_axi_arready\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__0_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[0]_i_1__0_n_0\, Q => \^q\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[10]_i_1__0_n_0\, Q => \^q\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[11]_i_1__0_n_0\, Q => \^q\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[12]_i_1__0_n_0\, Q => \^q\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[13]_i_1__1_n_0\, Q => \^q\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[14]_i_1__0_n_0\, Q => \^q\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[15]_i_1__0_n_0\, Q => \^q\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[16]_i_1__0_n_0\, Q => \^q\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[17]_i_1__0_n_0\, Q => \^q\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[18]_i_1__0_n_0\, Q => \^q\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[19]_i_1__0_n_0\, Q => \^q\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[1]_i_1__0_n_0\, Q => \^q\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[20]_i_1__0_n_0\, Q => \^q\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[21]_i_1__0_n_0\, Q => \^q\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[22]_i_1__0_n_0\, Q => \^q\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[23]_i_1__0_n_0\, Q => \^q\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[24]_i_1__0_n_0\, Q => \^q\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[25]_i_1__0_n_0\, Q => \^q\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[26]_i_1__0_n_0\, Q => \^q\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[27]_i_1__0_n_0\, Q => \^q\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[28]_i_1__0_n_0\, Q => \^q\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[29]_i_1__0_n_0\, Q => \^q\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[2]_i_1__0_n_0\, Q => \^q\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[30]_i_1__0_n_0\, Q => \^q\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[31]_i_2__0_n_0\, Q => \^q\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[32]_i_1__0_n_0\, Q => \^q\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[33]_i_1__0_n_0\, Q => \^q\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[34]_i_1__0_n_0\, Q => \^q\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[35]_i_1__0_n_0\, Q => \^q\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[36]_i_1__0_n_0\, Q => \^q\(36), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[38]_i_1__0_n_0\, Q => \^q\(37), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[39]_i_1__0_n_0\, Q => \^q\(38), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[3]_i_1__0_n_0\, Q => \^q\(3), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[44]_i_1__0_n_0\, Q => \^q\(39), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[45]_i_1__0_n_0\, Q => \^q\(40), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[46]_i_1__1_n_0\, Q => \^q\(41), R => '0' ); \m_payload_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[47]_i_1__0_n_0\, Q => \^q\(42), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[4]_i_1__0_n_0\, Q => \^q\(4), R => '0' ); \m_payload_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[50]_i_1__0_n_0\, Q => \^q\(43), R => '0' ); \m_payload_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[51]_i_1__0_n_0\, Q => \^q\(44), R => '0' ); \m_payload_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[52]_i_1__0_n_0\, Q => \^q\(45), R => '0' ); \m_payload_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[53]_i_1__0_n_0\, Q => \^q\(46), R => '0' ); \m_payload_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[54]_i_1__0_n_0\, Q => \^q\(47), R => '0' ); \m_payload_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[55]_i_1__0_n_0\, Q => \^q\(48), R => '0' ); \m_payload_i_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[56]_i_1__0_n_0\, Q => \^q\(49), R => '0' ); \m_payload_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[57]_i_1__0_n_0\, Q => \^q\(50), R => '0' ); \m_payload_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[58]_i_1__0_n_0\, Q => \^q\(51), R => '0' ); \m_payload_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[59]_i_1__0_n_0\, Q => \^q\(52), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[5]_i_1__0_n_0\, Q => \^q\(5), R => '0' ); \m_payload_i_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[60]_i_1__0_n_0\, Q => \^q\(53), R => '0' ); \m_payload_i_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[61]_i_1__0_n_0\, Q => \^q\(54), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[6]_i_1__0_n_0\, Q => \^q\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[7]_i_1__0_n_0\, Q => \^q\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[8]_i_1__0_n_0\, Q => \^q\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => m_valid_i_reg_1(0), D => \m_payload_i[9]_i_1__0_n_0\, Q => \^q\(9), R => '0' ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^axaddr_offset_r_reg[3]\, R => \^m_valid_i_reg_0\ ); next_pending_r_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => \state_reg[1]_rep\, I1 => \^q\(42), I2 => \^q\(40), I3 => \^q\(39), I4 => \^q\(41), O => next_pending_r_reg ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^s_axi_arready\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arprot(2), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arsize(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arsize(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arburst(0), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arburst(1), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(0), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(1), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(2), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arlen(3), Q => \skid_buffer_reg_n_0_[47]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(0), Q => \skid_buffer_reg_n_0_[50]\, R => '0' ); \skid_buffer_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(1), Q => \skid_buffer_reg_n_0_[51]\, R => '0' ); \skid_buffer_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(2), Q => \skid_buffer_reg_n_0_[52]\, R => '0' ); \skid_buffer_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(3), Q => \skid_buffer_reg_n_0_[53]\, R => '0' ); \skid_buffer_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(4), Q => \skid_buffer_reg_n_0_[54]\, R => '0' ); \skid_buffer_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(5), Q => \skid_buffer_reg_n_0_[55]\, R => '0' ); \skid_buffer_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(6), Q => \skid_buffer_reg_n_0_[56]\, R => '0' ); \skid_buffer_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(7), Q => \skid_buffer_reg_n_0_[57]\, R => '0' ); \skid_buffer_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(8), Q => \skid_buffer_reg_n_0_[58]\, R => '0' ); \skid_buffer_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(9), Q => \skid_buffer_reg_n_0_[59]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(10), Q => \skid_buffer_reg_n_0_[60]\, R => '0' ); \skid_buffer_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_arid(11), Q => \skid_buffer_reg_n_0_[61]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_arready\, D => s_axi_araddr(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); \wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(39), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(0) ); \wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"8A888AAA" ) port map ( I0 => \^q\(1), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(40), O => \wrap_boundary_axaddr_r_reg[6]\(1) ); \wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0F553300000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(36), I5 => \^q\(2), O => \wrap_boundary_axaddr_r_reg[6]\(2) ); \wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"020202A2A2A202A2" ) port map ( I0 => \^q\(3), I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\, I2 => \^q\(36), I3 => \^q\(40), I4 => \^q\(35), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(3) ); \wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(41), I1 => \^q\(35), I2 => \^q\(42), O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ ); \wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"503F5F3F00000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(36), I3 => \^q\(35), I4 => \^q\(42), I5 => \^q\(4), O => \wrap_boundary_axaddr_r_reg[6]\(4) ); \wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"2A222AAA" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(41), I3 => \^q\(35), I4 => \^q\(42), O => \wrap_boundary_axaddr_r_reg[6]\(5) ); \wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"2AAA" ) port map ( I0 => \^q\(6), I1 => \^q\(42), I2 => \^q\(35), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(6) ); \wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA6AA56AAAAAAAA" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(1), I1 => \wrap_second_len_r_reg[3]_0\(0), I2 => \state_reg[1]_rep\, I3 => \^wrap_cnt_r_reg[2]\, I4 => \^axaddr_offset_r_reg[0]\, I5 => \^wrap_second_len_r_reg[3]\(0), O => \wrap_cnt_r_reg[3]\(0) ); \wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(2), I1 => \wrap_second_len_r_reg[1]\, I2 => \^wrap_second_len_r_reg[3]\(1), O => \wrap_cnt_r_reg[3]\(1) ); \wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFEAEAFFEA" ) port map ( I0 => \axaddr_offset_r_reg[3]_1\, I1 => \^axlen_cnt_reg[3]\, I2 => \axaddr_offset_r[3]_i_2__0_n_0\, I3 => \^axaddr_offset_r_reg[2]\, I4 => \wrap_cnt_r[3]_i_5__0_n_0\, I5 => \axaddr_offset_r_reg[2]_1\, O => \wrap_cnt_r_reg[3]_0\ ); \wrap_cnt_r[3]_i_5__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \^q\(41), I1 => \state_reg[0]_rep\, I2 => \^axaddr_offset_r_reg[3]\, I3 => \state_reg[1]_rep_0\, O => \wrap_cnt_r[3]_i_5__0_n_0\ ); \wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0001000000010001" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset_0\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2__0_n_0\, I4 => \state_reg[1]_rep\, I5 => \axaddr_offset_r_reg[3]_0\(2), O => \^wrap_cnt_r_reg[2]\ ); \wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"F00EFFFFF00E0000" ) port map ( I0 => \^axaddr_offset_0\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_r_reg[0]\, I3 => \^axaddr_offset_0\(0), I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(1), O => \^wrap_second_len_r_reg[3]\(0) ); \wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"CCC2FFFFCCC20000" ) port map ( I0 => \^axaddr_offset_0\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_0\(0), I3 => \^axaddr_offset_r_reg[0]\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(2), O => \^wrap_second_len_r_reg[3]\(1) ); \wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FE00FFFFFE00FE00" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset_0\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2__0_n_0\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(3), O => \^wrap_second_len_r_reg[3]\(2) ); \wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"A8A8A8080808A808" ) port map ( I0 => \^axlen_cnt_reg[3]\, I1 => \wrap_second_len_r[3]_i_3__0_n_0\, I2 => \^q\(36), I3 => \^q\(5), I4 => \^q\(35), I5 => \^q\(6), O => \wrap_second_len_r[3]_i_2__0_n_0\ ); \wrap_second_len_r[3]_i_3__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(4), I1 => \^q\(35), I2 => \^q\(3), O => \wrap_second_len_r[3]_i_3__0_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 is port ( s_axi_awready : out STD_LOGIC; s_ready_i_reg_0 : out STD_LOGIC; m_valid_i_reg_0 : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; \axaddr_offset_r_reg[0]\ : out STD_LOGIC; axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \aresetn_d_reg[1]_inv\ : out STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[1]_inv_0\ : in STD_LOGIC; aresetn : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); S : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; b_push : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0; architecture STRUCTURE of design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 is signal \^q\ : STD_LOGIC_VECTOR ( 54 downto 0 ); signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC; signal \axaddr_incr[3]_i_4_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_5_n_0\ : STD_LOGIC; signal \axaddr_incr[3]_i_6_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[11]_i_3_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[3]_i_2_n_3\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_0\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_1\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_2\ : STD_LOGIC; signal \axaddr_incr_reg[7]_i_2_n_3\ : STD_LOGIC; signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC; signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC; signal \axaddr_offset_r[3]_i_2_n_0\ : STD_LOGIC; signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC; signal \^axlen_cnt_reg[3]\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal \^m_valid_i_reg_0\ : STD_LOGIC; signal \^s_axi_awready\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^s_ready_i_reg_0\ : STD_LOGIC; signal skid_buffer : STD_LOGIC_VECTOR ( 61 downto 0 ); signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[52]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC; signal \wrap_cnt_r[3]_i_5_n_0\ : STD_LOGIC; signal \^wrap_cnt_r_reg[2]\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC; signal \wrap_second_len_r[3]_i_3_n_0\ : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \m_payload_i[52]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair49"; begin Q(54 downto 0) <= \^q\(54 downto 0); axaddr_offset(1 downto 0) <= \^axaddr_offset\(1 downto 0); \axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\; \axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\; \axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\; m_valid_i_reg_0 <= \^m_valid_i_reg_0\; s_axi_awready <= \^s_axi_awready\; s_ready_i_reg_0 <= \^s_ready_i_reg_0\; \wrap_cnt_r_reg[2]\ <= \^wrap_cnt_r_reg[2]\; \wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0); \aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \aresetn_d_reg_n_0_[0]\, I1 => aresetn, O => \aresetn_d_reg[1]_inv\ ); \aresetn_d_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => aresetn, Q => \aresetn_d_reg_n_0_[0]\, R => '0' ); \axaddr_incr[3]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => \^q\(2), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_4_n_0\ ); \axaddr_incr[3]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^q\(1), I1 => \^q\(36), O => \axaddr_incr[3]_i_5_n_0\ ); \axaddr_incr[3]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(36), O => \axaddr_incr[3]_i_6_n_0\ ); \axaddr_incr_reg[11]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[7]_i_2_n_0\, CO(3) => \NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED\(3), CO(2) => \axaddr_incr_reg[11]_i_3_n_1\, CO(1) => \axaddr_incr_reg[11]_i_3_n_2\, CO(0) => \axaddr_incr_reg[11]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_incr(11 downto 8), S(3 downto 0) => \^q\(11 downto 8) ); \axaddr_incr_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \axaddr_incr_reg[3]_i_2_n_0\, CO(2) => \axaddr_incr_reg[3]_i_2_n_1\, CO(1) => \axaddr_incr_reg[3]_i_2_n_2\, CO(0) => \axaddr_incr_reg[3]_i_2_n_3\, CYINIT => '0', DI(3) => \^q\(3), DI(2) => \axaddr_incr[3]_i_4_n_0\, DI(1) => \axaddr_incr[3]_i_5_n_0\, DI(0) => \axaddr_incr[3]_i_6_n_0\, O(3 downto 0) => axaddr_incr(3 downto 0), S(3 downto 0) => S(3 downto 0) ); \axaddr_incr_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \axaddr_incr_reg[3]_i_2_n_0\, CO(3) => \axaddr_incr_reg[7]_i_2_n_0\, CO(2) => \axaddr_incr_reg[7]_i_2_n_1\, CO(1) => \axaddr_incr_reg[7]_i_2_n_2\, CO(0) => \axaddr_incr_reg[7]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 0) => axaddr_incr(7 downto 4), S(3 downto 0) => \^q\(7 downto 4) ); \axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[0]_i_2_n_0\, I1 => \^q\(39), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(0), O => \^axaddr_offset_r_reg[0]\ ); \axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(3), I1 => \^q\(2), I2 => \^q\(36), I3 => \^q\(1), I4 => \^q\(35), I5 => \^q\(0), O => \axaddr_offset_r[0]_i_2_n_0\ ); \axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[1]_i_2_n_0\, I1 => \^q\(40), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(1), O => \^axaddr_offset\(0) ); \axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(4), I1 => \^q\(3), I2 => \^q\(36), I3 => \^q\(2), I4 => \^q\(35), I5 => \^q\(1), O => \axaddr_offset_r[1]_i_2_n_0\ ); \axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(5), I1 => \^q\(4), I2 => \^q\(36), I3 => \^q\(3), I4 => \^q\(35), I5 => \^q\(2), O => \^axaddr_offset_r_reg[2]\ ); \axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF8FF00000800" ) port map ( I0 => \axaddr_offset_r[3]_i_2_n_0\, I1 => \^q\(42), I2 => \state_reg[1]\(1), I3 => \^m_valid_i_reg_0\, I4 => \state_reg[1]\(0), I5 => \axaddr_offset_r_reg[3]\(2), O => \^axaddr_offset\(1) ); \axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \^q\(6), I1 => \^q\(5), I2 => \^q\(36), I3 => \^q\(4), I4 => \^q\(35), I5 => \^q\(3), O => \axaddr_offset_r[3]_i_2_n_0\ ); \axlen_cnt[3]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0020" ) port map ( I0 => \^q\(42), I1 => \state_reg[1]\(0), I2 => \^m_valid_i_reg_0\, I3 => \state_reg[1]\(1), O => \^axlen_cnt_reg[3]\ ); \m_payload_i[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[0]\, O => skid_buffer(0) ); \m_payload_i[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(10), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[10]\, O => skid_buffer(10) ); \m_payload_i[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(11), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[11]\, O => skid_buffer(11) ); \m_payload_i[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(12), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[12]\, O => skid_buffer(12) ); \m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(13), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[13]\, O => skid_buffer(13) ); \m_payload_i[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(14), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[14]\, O => skid_buffer(14) ); \m_payload_i[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(15), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[15]\, O => skid_buffer(15) ); \m_payload_i[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(16), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[16]\, O => skid_buffer(16) ); \m_payload_i[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(17), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[17]\, O => skid_buffer(17) ); \m_payload_i[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(18), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[18]\, O => skid_buffer(18) ); \m_payload_i[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(19), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[19]\, O => skid_buffer(19) ); \m_payload_i[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[1]\, O => skid_buffer(1) ); \m_payload_i[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(20), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[20]\, O => skid_buffer(20) ); \m_payload_i[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(21), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[21]\, O => skid_buffer(21) ); \m_payload_i[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(22), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[22]\, O => skid_buffer(22) ); \m_payload_i[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(23), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[23]\, O => skid_buffer(23) ); \m_payload_i[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(24), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[24]\, O => skid_buffer(24) ); \m_payload_i[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(25), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[25]\, O => skid_buffer(25) ); \m_payload_i[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(26), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[26]\, O => skid_buffer(26) ); \m_payload_i[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(27), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[27]\, O => skid_buffer(27) ); \m_payload_i[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(28), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[28]\, O => skid_buffer(28) ); \m_payload_i[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(29), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[29]\, O => skid_buffer(29) ); \m_payload_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[2]\, O => skid_buffer(2) ); \m_payload_i[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(30), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[30]\, O => skid_buffer(30) ); \m_payload_i[31]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(31), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[31]\, O => skid_buffer(31) ); \m_payload_i[32]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[32]\, O => skid_buffer(32) ); \m_payload_i[33]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[33]\, O => skid_buffer(33) ); \m_payload_i[34]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awprot(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[34]\, O => skid_buffer(34) ); \m_payload_i[35]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awsize(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[35]\, O => skid_buffer(35) ); \m_payload_i[36]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awsize(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[36]\, O => skid_buffer(36) ); \m_payload_i[38]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awburst(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[38]\, O => skid_buffer(38) ); \m_payload_i[39]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awburst(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[39]\, O => skid_buffer(39) ); \m_payload_i[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[3]\, O => skid_buffer(3) ); \m_payload_i[44]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[44]\, O => skid_buffer(44) ); \m_payload_i[45]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[45]\, O => skid_buffer(45) ); \m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[46]\, O => skid_buffer(46) ); \m_payload_i[47]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awlen(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[47]\, O => skid_buffer(47) ); \m_payload_i[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(4), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[4]\, O => skid_buffer(4) ); \m_payload_i[50]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(0), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[50]\, O => skid_buffer(50) ); \m_payload_i[51]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(1), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[51]\, O => skid_buffer(51) ); \m_payload_i[52]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(2), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[52]\, O => skid_buffer(52) ); \m_payload_i[53]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(3), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[53]\, O => skid_buffer(53) ); \m_payload_i[54]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(4), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[54]\, O => skid_buffer(54) ); \m_payload_i[55]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(5), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[55]\, O => skid_buffer(55) ); \m_payload_i[56]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(6), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[56]\, O => skid_buffer(56) ); \m_payload_i[57]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(7), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[57]\, O => skid_buffer(57) ); \m_payload_i[58]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(8), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[58]\, O => skid_buffer(58) ); \m_payload_i[59]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(9), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[59]\, O => skid_buffer(59) ); \m_payload_i[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(5), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[5]\, O => skid_buffer(5) ); \m_payload_i[60]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(10), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[60]\, O => skid_buffer(60) ); \m_payload_i[61]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awid(11), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[61]\, O => skid_buffer(61) ); \m_payload_i[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(6), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[6]\, O => skid_buffer(6) ); \m_payload_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(7), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[7]\, O => skid_buffer(7) ); \m_payload_i[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(8), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[8]\, O => skid_buffer(8) ); \m_payload_i[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axi_awaddr(9), I1 => \^s_axi_awready\, I2 => \skid_buffer_reg_n_0_[9]\, O => skid_buffer(9) ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(0), Q => \^q\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(10), Q => \^q\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(11), Q => \^q\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(12), Q => \^q\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(13), Q => \^q\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(14), Q => \^q\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(15), Q => \^q\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(16), Q => \^q\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(17), Q => \^q\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(18), Q => \^q\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(19), Q => \^q\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(1), Q => \^q\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(20), Q => \^q\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(21), Q => \^q\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(22), Q => \^q\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(23), Q => \^q\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(24), Q => \^q\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(25), Q => \^q\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(26), Q => \^q\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(27), Q => \^q\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(28), Q => \^q\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(29), Q => \^q\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(2), Q => \^q\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(30), Q => \^q\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(31), Q => \^q\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(32), Q => \^q\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(33), Q => \^q\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(34), Q => \^q\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(35), Q => \^q\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(36), Q => \^q\(36), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(38), Q => \^q\(37), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(39), Q => \^q\(38), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(3), Q => \^q\(3), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(44), Q => \^q\(39), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(45), Q => \^q\(40), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(46), Q => \^q\(41), R => '0' ); \m_payload_i_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(47), Q => \^q\(42), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(4), Q => \^q\(4), R => '0' ); \m_payload_i_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(50), Q => \^q\(43), R => '0' ); \m_payload_i_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(51), Q => \^q\(44), R => '0' ); \m_payload_i_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(52), Q => \^q\(45), R => '0' ); \m_payload_i_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(53), Q => \^q\(46), R => '0' ); \m_payload_i_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(54), Q => \^q\(47), R => '0' ); \m_payload_i_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(55), Q => \^q\(48), R => '0' ); \m_payload_i_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(56), Q => \^q\(49), R => '0' ); \m_payload_i_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(57), Q => \^q\(50), R => '0' ); \m_payload_i_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(58), Q => \^q\(51), R => '0' ); \m_payload_i_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(59), Q => \^q\(52), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(5), Q => \^q\(5), R => '0' ); \m_payload_i_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(60), Q => \^q\(53), R => '0' ); \m_payload_i_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(61), Q => \^q\(54), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(6), Q => \^q\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(7), Q => \^q\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(8), Q => \^q\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => E(0), D => skid_buffer(9), Q => \^q\(9), R => '0' ); m_valid_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => b_push, I1 => \^m_valid_i_reg_0\, I2 => s_axi_awvalid, I3 => \^s_axi_awready\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^m_valid_i_reg_0\, R => \aresetn_d_reg[1]_inv_0\ ); next_pending_r_i_4: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => \state_reg[1]_rep\, I1 => \^q\(42), I2 => \^q\(40), I3 => \^q\(39), I4 => \^q\(41), O => next_pending_r_reg ); \s_ready_i_i_1__1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \aresetn_d_reg_n_0_[0]\, O => \^s_ready_i_reg_0\ ); s_ready_i_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => s_axi_awvalid, I1 => \^s_axi_awready\, I2 => b_push, I3 => \^m_valid_i_reg_0\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^s_axi_awready\, R => \^s_ready_i_reg_0\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(0), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(1), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awprot(2), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awsize(0), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awsize(1), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awburst(0), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awburst(1), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(0), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(1), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(2), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[47]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awlen(3), Q => \skid_buffer_reg_n_0_[47]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[50]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(0), Q => \skid_buffer_reg_n_0_[50]\, R => '0' ); \skid_buffer_reg[51]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(1), Q => \skid_buffer_reg_n_0_[51]\, R => '0' ); \skid_buffer_reg[52]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(2), Q => \skid_buffer_reg_n_0_[52]\, R => '0' ); \skid_buffer_reg[53]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(3), Q => \skid_buffer_reg_n_0_[53]\, R => '0' ); \skid_buffer_reg[54]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(4), Q => \skid_buffer_reg_n_0_[54]\, R => '0' ); \skid_buffer_reg[55]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(5), Q => \skid_buffer_reg_n_0_[55]\, R => '0' ); \skid_buffer_reg[56]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(6), Q => \skid_buffer_reg_n_0_[56]\, R => '0' ); \skid_buffer_reg[57]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(7), Q => \skid_buffer_reg_n_0_[57]\, R => '0' ); \skid_buffer_reg[58]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(8), Q => \skid_buffer_reg_n_0_[58]\, R => '0' ); \skid_buffer_reg[59]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(9), Q => \skid_buffer_reg_n_0_[59]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[60]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(10), Q => \skid_buffer_reg_n_0_[60]\, R => '0' ); \skid_buffer_reg[61]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awid(11), Q => \skid_buffer_reg_n_0_[61]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^s_axi_awready\, D => s_axi_awaddr(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); \wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"AA8A" ) port map ( I0 => \^q\(0), I1 => \^q\(35), I2 => \^q\(39), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(0) ); \wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"8A888AAA" ) port map ( I0 => \^q\(1), I1 => \^q\(36), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(40), O => \wrap_boundary_axaddr_r_reg[6]\(1) ); \wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0F553300000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(39), I3 => \^q\(35), I4 => \^q\(36), I5 => \^q\(2), O => \wrap_boundary_axaddr_r_reg[6]\(2) ); \wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"020202A2A2A202A2" ) port map ( I0 => \^q\(3), I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\, I2 => \^q\(36), I3 => \^q\(40), I4 => \^q\(35), I5 => \^q\(39), O => \wrap_boundary_axaddr_r_reg[6]\(3) ); \wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(41), I1 => \^q\(35), I2 => \^q\(42), O => \wrap_boundary_axaddr_r[3]_i_2_n_0\ ); \wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"503F5F3F00000000" ) port map ( I0 => \^q\(40), I1 => \^q\(41), I2 => \^q\(36), I3 => \^q\(35), I4 => \^q\(42), I5 => \^q\(4), O => \wrap_boundary_axaddr_r_reg[6]\(4) ); \wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"2A222AAA" ) port map ( I0 => \^q\(5), I1 => \^q\(36), I2 => \^q\(41), I3 => \^q\(35), I4 => \^q\(42), O => \wrap_boundary_axaddr_r_reg[6]\(5) ); \wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2AAA" ) port map ( I0 => \^q\(6), I1 => \^q\(42), I2 => \^q\(35), I3 => \^q\(36), O => \wrap_boundary_axaddr_r_reg[6]\(6) ); \wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAA6AA56AAAAAAAA" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(1), I1 => \wrap_second_len_r_reg[3]_0\(0), I2 => \state_reg[1]_rep\, I3 => \^wrap_cnt_r_reg[2]\, I4 => \^axaddr_offset_r_reg[0]\, I5 => \^wrap_second_len_r_reg[3]\(0), O => D(0) ); \wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^wrap_second_len_r_reg[3]\(2), I1 => \wrap_second_len_r_reg[1]\, I2 => \^wrap_second_len_r_reg[3]\(1), O => D(1) ); \wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFEAEAFFEA" ) port map ( I0 => \axaddr_offset_r_reg[3]_0\, I1 => \^axlen_cnt_reg[3]\, I2 => \axaddr_offset_r[3]_i_2_n_0\, I3 => \^axaddr_offset_r_reg[2]\, I4 => \wrap_cnt_r[3]_i_5_n_0\, I5 => \axaddr_offset_r_reg[2]_1\, O => \wrap_cnt_r_reg[3]\ ); \wrap_cnt_r[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \^q\(41), I1 => \state_reg[0]_rep\, I2 => \^m_valid_i_reg_0\, I3 => \state_reg[1]_rep_0\, O => \wrap_cnt_r[3]_i_5_n_0\ ); \wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0001000000010001" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2_n_0\, I4 => \state_reg[1]_rep\, I5 => \axaddr_offset_r_reg[3]\(2), O => \^wrap_cnt_r_reg[2]\ ); \wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F00EFFFFF00E0000" ) port map ( I0 => \^axaddr_offset\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset_r_reg[0]\, I3 => \^axaddr_offset\(0), I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(1), O => \^wrap_second_len_r_reg[3]\(0) ); \wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"CCC2FFFFCCC20000" ) port map ( I0 => \^axaddr_offset\(1), I1 => \axaddr_offset_r_reg[2]_0\(0), I2 => \^axaddr_offset\(0), I3 => \^axaddr_offset_r_reg[0]\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(2), O => \^wrap_second_len_r_reg[3]\(1) ); \wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FE00FFFFFE00FE00" ) port map ( I0 => \^axaddr_offset_r_reg[0]\, I1 => \^axaddr_offset\(0), I2 => \axaddr_offset_r_reg[2]_0\(0), I3 => \wrap_second_len_r[3]_i_2_n_0\, I4 => \state_reg[1]_rep\, I5 => \wrap_second_len_r_reg[3]_0\(3), O => \^wrap_second_len_r_reg[3]\(2) ); \wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"A8A8A8080808A808" ) port map ( I0 => \^axlen_cnt_reg[3]\, I1 => \wrap_second_len_r[3]_i_3_n_0\, I2 => \^q\(36), I3 => \^q\(5), I4 => \^q\(35), I5 => \^q\(6), O => \wrap_second_len_r[3]_i_2_n_0\ ); \wrap_second_len_r[3]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \^q\(4), I1 => \^q\(35), I2 => \^q\(3), O => \wrap_second_len_r[3]_i_3_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is port ( s_axi_bvalid : out STD_LOGIC; \skid_buffer_reg[0]_0\ : out STD_LOGIC; \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \aresetn_d_reg[1]_inv\ : in STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; si_rs_bvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\; architecture STRUCTURE of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ is signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC; signal m_valid_i0 : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^s_axi_bvalid\ : STD_LOGIC; signal s_ready_i0 : STD_LOGIC; signal \^skid_buffer_reg[0]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair79"; begin s_axi_bvalid <= \^s_axi_bvalid\; \skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\; \m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \s_bresp_acc_reg[1]\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__1_n_0\ ); \m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__1_n_0\ ); \m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__1_n_0\ ); \m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__1_n_0\ ); \m_payload_i[13]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, O => p_1_in ); \m_payload_i[13]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_2_n_0\ ); \m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \s_bresp_acc_reg[1]\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__1_n_0\ ); \m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__1_n_0\ ); \m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__1_n_0\ ); \m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__1_n_0\ ); \m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__1_n_0\ ); \m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__1_n_0\ ); \m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__1_n_0\ ); \m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__1_n_0\ ); \m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \out\(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__1_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[0]_i_1__1_n_0\, Q => \s_axi_bid[11]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[10]_i_1__1_n_0\, Q => \s_axi_bid[11]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[11]_i_1__1_n_0\, Q => \s_axi_bid[11]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[12]_i_1__1_n_0\, Q => \s_axi_bid[11]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[13]_i_2_n_0\, Q => \s_axi_bid[11]\(13), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[1]_i_1__1_n_0\, Q => \s_axi_bid[11]\(1), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[2]_i_1__1_n_0\, Q => \s_axi_bid[11]\(2), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[3]_i_1__1_n_0\, Q => \s_axi_bid[11]\(3), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[4]_i_1__1_n_0\, Q => \s_axi_bid[11]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[5]_i_1__1_n_0\, Q => \s_axi_bid[11]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[6]_i_1__1_n_0\, Q => \s_axi_bid[11]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[7]_i_1__1_n_0\, Q => \s_axi_bid[11]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[8]_i_1__1_n_0\, Q => \s_axi_bid[11]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[9]_i_1__1_n_0\, Q => \s_axi_bid[11]\(9), R => '0' ); \m_valid_i_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, I2 => si_rs_bvalid, I3 => \^skid_buffer_reg[0]_0\, O => m_valid_i0 ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => m_valid_i0, Q => \^s_axi_bvalid\, R => \aresetn_d_reg[1]_inv\ ); s_ready_i_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F4FF" ) port map ( I0 => si_rs_bvalid, I1 => \^skid_buffer_reg[0]_0\, I2 => s_axi_bready, I3 => \^s_axi_bvalid\, O => s_ready_i0 ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => s_ready_i0, Q => \^skid_buffer_reg[0]_0\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \s_bresp_acc_reg[1]\(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(8), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(9), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(10), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(11), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \s_bresp_acc_reg[1]\(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(0), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(1), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(2), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(3), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(4), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(5), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(6), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \out\(7), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is port ( s_axi_rvalid : out STD_LOGIC; \skid_buffer_reg[0]_0\ : out STD_LOGIC; \cnt_read_reg[2]_rep__0\ : out STD_LOGIC; \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); \aresetn_d_reg[1]_inv\ : in STD_LOGIC; aclk : in STD_LOGIC; \aresetn_d_reg[0]\ : in STD_LOGIC; \cnt_read_reg[4]_rep__0\ : in STD_LOGIC; s_axi_rready : in STD_LOGIC; r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 ); \cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_17_axic_register_slice"; end \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\; architecture STRUCTURE of \design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ is signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC; signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC; signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC; signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC; signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC; signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^s_axi_rvalid\ : STD_LOGIC; signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC; signal \^skid_buffer_reg[0]_0\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC; signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cnt_read[4]_i_4\ : label is "soft_lutpair84"; attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair102"; attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair101"; attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair95"; attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair107"; attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair106"; attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair105"; attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair104"; attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair103"; attribute SOFT_HLUTNM of \s_ready_i_i_1__2\ : label is "soft_lutpair84"; begin s_axi_rvalid <= \^s_axi_rvalid\; \skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\; \cnt_read[4]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^skid_buffer_reg[0]_0\, I1 => \cnt_read_reg[4]_rep__0\, O => \cnt_read_reg[2]_rep__0\ ); \m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[0]\, O => \m_payload_i[0]_i_1__2_n_0\ ); \m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[10]\, O => \m_payload_i[10]_i_1__2_n_0\ ); \m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[11]\, O => \m_payload_i[11]_i_1__2_n_0\ ); \m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(12), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[12]\, O => \m_payload_i[12]_i_1__2_n_0\ ); \m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(13), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[13]\, O => \m_payload_i[13]_i_1__2_n_0\ ); \m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(14), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[14]\, O => \m_payload_i[14]_i_1__1_n_0\ ); \m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(15), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[15]\, O => \m_payload_i[15]_i_1__1_n_0\ ); \m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(16), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[16]\, O => \m_payload_i[16]_i_1__1_n_0\ ); \m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(17), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[17]\, O => \m_payload_i[17]_i_1__1_n_0\ ); \m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(18), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[18]\, O => \m_payload_i[18]_i_1__1_n_0\ ); \m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(19), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[19]\, O => \m_payload_i[19]_i_1__1_n_0\ ); \m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[1]\, O => \m_payload_i[1]_i_1__2_n_0\ ); \m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(20), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[20]\, O => \m_payload_i[20]_i_1__1_n_0\ ); \m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(21), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[21]\, O => \m_payload_i[21]_i_1__1_n_0\ ); \m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(22), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[22]\, O => \m_payload_i[22]_i_1__1_n_0\ ); \m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(23), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[23]\, O => \m_payload_i[23]_i_1__1_n_0\ ); \m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(24), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[24]\, O => \m_payload_i[24]_i_1__1_n_0\ ); \m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(25), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[25]\, O => \m_payload_i[25]_i_1__1_n_0\ ); \m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(26), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[26]\, O => \m_payload_i[26]_i_1__1_n_0\ ); \m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(27), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[27]\, O => \m_payload_i[27]_i_1__1_n_0\ ); \m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(28), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[28]\, O => \m_payload_i[28]_i_1__1_n_0\ ); \m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(29), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[29]\, O => \m_payload_i[29]_i_1__1_n_0\ ); \m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[2]\, O => \m_payload_i[2]_i_1__2_n_0\ ); \m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(30), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[30]\, O => \m_payload_i[30]_i_1__1_n_0\ ); \m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(31), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[31]\, O => \m_payload_i[31]_i_1__1_n_0\ ); \m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(32), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[32]\, O => \m_payload_i[32]_i_1__1_n_0\ ); \m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(33), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[33]\, O => \m_payload_i[33]_i_1__1_n_0\ ); \m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(0), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[34]\, O => \m_payload_i[34]_i_1__1_n_0\ ); \m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(1), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[35]\, O => \m_payload_i[35]_i_1__1_n_0\ ); \m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(2), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[36]\, O => \m_payload_i[36]_i_1__1_n_0\ ); \m_payload_i[37]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[37]\, O => \m_payload_i[37]_i_1_n_0\ ); \m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[38]\, O => \m_payload_i[38]_i_1__1_n_0\ ); \m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[39]\, O => \m_payload_i[39]_i_1__1_n_0\ ); \m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(3), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[3]\, O => \m_payload_i[3]_i_1__2_n_0\ ); \m_payload_i[40]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[40]\, O => \m_payload_i[40]_i_1_n_0\ ); \m_payload_i[41]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[41]\, O => \m_payload_i[41]_i_1_n_0\ ); \m_payload_i[42]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[42]\, O => \m_payload_i[42]_i_1_n_0\ ); \m_payload_i[43]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[43]\, O => \m_payload_i[43]_i_1_n_0\ ); \m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(10), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[44]\, O => \m_payload_i[44]_i_1__1_n_0\ ); \m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(11), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[45]\, O => \m_payload_i[45]_i_1__1_n_0\ ); \m_payload_i[46]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, O => p_1_in ); \m_payload_i[46]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => r_push_r_reg(12), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[46]\, O => \m_payload_i[46]_i_2_n_0\ ); \m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(4), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[4]\, O => \m_payload_i[4]_i_1__2_n_0\ ); \m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(5), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[5]\, O => \m_payload_i[5]_i_1__2_n_0\ ); \m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(6), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[6]\, O => \m_payload_i[6]_i_1__2_n_0\ ); \m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(7), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[7]\, O => \m_payload_i[7]_i_1__2_n_0\ ); \m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(8), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[8]\, O => \m_payload_i[8]_i_1__2_n_0\ ); \m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \cnt_read_reg[4]\(9), I1 => \^skid_buffer_reg[0]_0\, I2 => \skid_buffer_reg_n_0_[9]\, O => \m_payload_i[9]_i_1__2_n_0\ ); \m_payload_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[0]_i_1__2_n_0\, Q => \s_axi_rid[11]\(0), R => '0' ); \m_payload_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[10]_i_1__2_n_0\, Q => \s_axi_rid[11]\(10), R => '0' ); \m_payload_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[11]_i_1__2_n_0\, Q => \s_axi_rid[11]\(11), R => '0' ); \m_payload_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[12]_i_1__2_n_0\, Q => \s_axi_rid[11]\(12), R => '0' ); \m_payload_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[13]_i_1__2_n_0\, Q => \s_axi_rid[11]\(13), R => '0' ); \m_payload_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[14]_i_1__1_n_0\, Q => \s_axi_rid[11]\(14), R => '0' ); \m_payload_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[15]_i_1__1_n_0\, Q => \s_axi_rid[11]\(15), R => '0' ); \m_payload_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[16]_i_1__1_n_0\, Q => \s_axi_rid[11]\(16), R => '0' ); \m_payload_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[17]_i_1__1_n_0\, Q => \s_axi_rid[11]\(17), R => '0' ); \m_payload_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[18]_i_1__1_n_0\, Q => \s_axi_rid[11]\(18), R => '0' ); \m_payload_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[19]_i_1__1_n_0\, Q => \s_axi_rid[11]\(19), R => '0' ); \m_payload_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[1]_i_1__2_n_0\, Q => \s_axi_rid[11]\(1), R => '0' ); \m_payload_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[20]_i_1__1_n_0\, Q => \s_axi_rid[11]\(20), R => '0' ); \m_payload_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[21]_i_1__1_n_0\, Q => \s_axi_rid[11]\(21), R => '0' ); \m_payload_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[22]_i_1__1_n_0\, Q => \s_axi_rid[11]\(22), R => '0' ); \m_payload_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[23]_i_1__1_n_0\, Q => \s_axi_rid[11]\(23), R => '0' ); \m_payload_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[24]_i_1__1_n_0\, Q => \s_axi_rid[11]\(24), R => '0' ); \m_payload_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[25]_i_1__1_n_0\, Q => \s_axi_rid[11]\(25), R => '0' ); \m_payload_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[26]_i_1__1_n_0\, Q => \s_axi_rid[11]\(26), R => '0' ); \m_payload_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[27]_i_1__1_n_0\, Q => \s_axi_rid[11]\(27), R => '0' ); \m_payload_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[28]_i_1__1_n_0\, Q => \s_axi_rid[11]\(28), R => '0' ); \m_payload_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[29]_i_1__1_n_0\, Q => \s_axi_rid[11]\(29), R => '0' ); \m_payload_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[2]_i_1__2_n_0\, Q => \s_axi_rid[11]\(2), R => '0' ); \m_payload_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[30]_i_1__1_n_0\, Q => \s_axi_rid[11]\(30), R => '0' ); \m_payload_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[31]_i_1__1_n_0\, Q => \s_axi_rid[11]\(31), R => '0' ); \m_payload_i_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[32]_i_1__1_n_0\, Q => \s_axi_rid[11]\(32), R => '0' ); \m_payload_i_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[33]_i_1__1_n_0\, Q => \s_axi_rid[11]\(33), R => '0' ); \m_payload_i_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[34]_i_1__1_n_0\, Q => \s_axi_rid[11]\(34), R => '0' ); \m_payload_i_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[35]_i_1__1_n_0\, Q => \s_axi_rid[11]\(35), R => '0' ); \m_payload_i_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[36]_i_1__1_n_0\, Q => \s_axi_rid[11]\(36), R => '0' ); \m_payload_i_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[37]_i_1_n_0\, Q => \s_axi_rid[11]\(37), R => '0' ); \m_payload_i_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[38]_i_1__1_n_0\, Q => \s_axi_rid[11]\(38), R => '0' ); \m_payload_i_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[39]_i_1__1_n_0\, Q => \s_axi_rid[11]\(39), R => '0' ); \m_payload_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[3]_i_1__2_n_0\, Q => \s_axi_rid[11]\(3), R => '0' ); \m_payload_i_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[40]_i_1_n_0\, Q => \s_axi_rid[11]\(40), R => '0' ); \m_payload_i_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[41]_i_1_n_0\, Q => \s_axi_rid[11]\(41), R => '0' ); \m_payload_i_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[42]_i_1_n_0\, Q => \s_axi_rid[11]\(42), R => '0' ); \m_payload_i_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[43]_i_1_n_0\, Q => \s_axi_rid[11]\(43), R => '0' ); \m_payload_i_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[44]_i_1__1_n_0\, Q => \s_axi_rid[11]\(44), R => '0' ); \m_payload_i_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[45]_i_1__1_n_0\, Q => \s_axi_rid[11]\(45), R => '0' ); \m_payload_i_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[46]_i_2_n_0\, Q => \s_axi_rid[11]\(46), R => '0' ); \m_payload_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[4]_i_1__2_n_0\, Q => \s_axi_rid[11]\(4), R => '0' ); \m_payload_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[5]_i_1__2_n_0\, Q => \s_axi_rid[11]\(5), R => '0' ); \m_payload_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[6]_i_1__2_n_0\, Q => \s_axi_rid[11]\(6), R => '0' ); \m_payload_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[7]_i_1__2_n_0\, Q => \s_axi_rid[11]\(7), R => '0' ); \m_payload_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[8]_i_1__2_n_0\, Q => \s_axi_rid[11]\(8), R => '0' ); \m_payload_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => p_1_in, D => \m_payload_i[9]_i_1__2_n_0\, Q => \s_axi_rid[11]\(9), R => '0' ); \m_valid_i_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"4FFF" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, I2 => \cnt_read_reg[4]_rep__0\, I3 => \^skid_buffer_reg[0]_0\, O => \m_valid_i_i_1__2_n_0\ ); m_valid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \m_valid_i_i_1__2_n_0\, Q => \^s_axi_rvalid\, R => \aresetn_d_reg[1]_inv\ ); \s_ready_i_i_1__2\: unisim.vcomponents.LUT4 generic map( INIT => X"F8FF" ) port map ( I0 => \cnt_read_reg[4]_rep__0\, I1 => \^skid_buffer_reg[0]_0\, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, O => \s_ready_i_i_1__2_n_0\ ); s_ready_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => \s_ready_i_i_1__2_n_0\, Q => \^skid_buffer_reg[0]_0\, R => \aresetn_d_reg[0]\ ); \skid_buffer_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(0), Q => \skid_buffer_reg_n_0_[0]\, R => '0' ); \skid_buffer_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(10), Q => \skid_buffer_reg_n_0_[10]\, R => '0' ); \skid_buffer_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(11), Q => \skid_buffer_reg_n_0_[11]\, R => '0' ); \skid_buffer_reg[12]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(12), Q => \skid_buffer_reg_n_0_[12]\, R => '0' ); \skid_buffer_reg[13]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(13), Q => \skid_buffer_reg_n_0_[13]\, R => '0' ); \skid_buffer_reg[14]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(14), Q => \skid_buffer_reg_n_0_[14]\, R => '0' ); \skid_buffer_reg[15]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(15), Q => \skid_buffer_reg_n_0_[15]\, R => '0' ); \skid_buffer_reg[16]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(16), Q => \skid_buffer_reg_n_0_[16]\, R => '0' ); \skid_buffer_reg[17]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(17), Q => \skid_buffer_reg_n_0_[17]\, R => '0' ); \skid_buffer_reg[18]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(18), Q => \skid_buffer_reg_n_0_[18]\, R => '0' ); \skid_buffer_reg[19]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(19), Q => \skid_buffer_reg_n_0_[19]\, R => '0' ); \skid_buffer_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(1), Q => \skid_buffer_reg_n_0_[1]\, R => '0' ); \skid_buffer_reg[20]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(20), Q => \skid_buffer_reg_n_0_[20]\, R => '0' ); \skid_buffer_reg[21]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(21), Q => \skid_buffer_reg_n_0_[21]\, R => '0' ); \skid_buffer_reg[22]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(22), Q => \skid_buffer_reg_n_0_[22]\, R => '0' ); \skid_buffer_reg[23]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(23), Q => \skid_buffer_reg_n_0_[23]\, R => '0' ); \skid_buffer_reg[24]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(24), Q => \skid_buffer_reg_n_0_[24]\, R => '0' ); \skid_buffer_reg[25]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(25), Q => \skid_buffer_reg_n_0_[25]\, R => '0' ); \skid_buffer_reg[26]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(26), Q => \skid_buffer_reg_n_0_[26]\, R => '0' ); \skid_buffer_reg[27]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(27), Q => \skid_buffer_reg_n_0_[27]\, R => '0' ); \skid_buffer_reg[28]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(28), Q => \skid_buffer_reg_n_0_[28]\, R => '0' ); \skid_buffer_reg[29]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(29), Q => \skid_buffer_reg_n_0_[29]\, R => '0' ); \skid_buffer_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(2), Q => \skid_buffer_reg_n_0_[2]\, R => '0' ); \skid_buffer_reg[30]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(30), Q => \skid_buffer_reg_n_0_[30]\, R => '0' ); \skid_buffer_reg[31]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(31), Q => \skid_buffer_reg_n_0_[31]\, R => '0' ); \skid_buffer_reg[32]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(32), Q => \skid_buffer_reg_n_0_[32]\, R => '0' ); \skid_buffer_reg[33]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(33), Q => \skid_buffer_reg_n_0_[33]\, R => '0' ); \skid_buffer_reg[34]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(0), Q => \skid_buffer_reg_n_0_[34]\, R => '0' ); \skid_buffer_reg[35]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(1), Q => \skid_buffer_reg_n_0_[35]\, R => '0' ); \skid_buffer_reg[36]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(2), Q => \skid_buffer_reg_n_0_[36]\, R => '0' ); \skid_buffer_reg[37]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(3), Q => \skid_buffer_reg_n_0_[37]\, R => '0' ); \skid_buffer_reg[38]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(4), Q => \skid_buffer_reg_n_0_[38]\, R => '0' ); \skid_buffer_reg[39]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(5), Q => \skid_buffer_reg_n_0_[39]\, R => '0' ); \skid_buffer_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(3), Q => \skid_buffer_reg_n_0_[3]\, R => '0' ); \skid_buffer_reg[40]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(6), Q => \skid_buffer_reg_n_0_[40]\, R => '0' ); \skid_buffer_reg[41]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(7), Q => \skid_buffer_reg_n_0_[41]\, R => '0' ); \skid_buffer_reg[42]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(8), Q => \skid_buffer_reg_n_0_[42]\, R => '0' ); \skid_buffer_reg[43]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(9), Q => \skid_buffer_reg_n_0_[43]\, R => '0' ); \skid_buffer_reg[44]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(10), Q => \skid_buffer_reg_n_0_[44]\, R => '0' ); \skid_buffer_reg[45]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(11), Q => \skid_buffer_reg_n_0_[45]\, R => '0' ); \skid_buffer_reg[46]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => r_push_r_reg(12), Q => \skid_buffer_reg_n_0_[46]\, R => '0' ); \skid_buffer_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(4), Q => \skid_buffer_reg_n_0_[4]\, R => '0' ); \skid_buffer_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(5), Q => \skid_buffer_reg_n_0_[5]\, R => '0' ); \skid_buffer_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(6), Q => \skid_buffer_reg_n_0_[6]\, R => '0' ); \skid_buffer_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(7), Q => \skid_buffer_reg_n_0_[7]\, R => '0' ); \skid_buffer_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(8), Q => \skid_buffer_reg_n_0_[8]\, R => '0' ); \skid_buffer_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => \^skid_buffer_reg[0]_0\, D => \cnt_read_reg[4]\(9), Q => \skid_buffer_reg_n_0_[9]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel is port ( si_rs_bvalid : out STD_LOGIC; \cnt_read_reg[0]_rep__0\ : out STD_LOGIC; \cnt_read_reg[1]_rep__0\ : out STD_LOGIC; m_axi_bready : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); \skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); areset_d1 : in STD_LOGIC; aclk : in STD_LOGIC; b_push : in STD_LOGIC; si_rs_bready : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 15 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel is signal bid_fifo_0_n_3 : STD_LOGIC; signal bid_fifo_0_n_5 : STD_LOGIC; signal \bresp_cnt[7]_i_6_n_0\ : STD_LOGIC; signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal bresp_push : STD_LOGIC; signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 ); signal mhandshake : STD_LOGIC; signal mhandshake_r : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 ); signal s_bresp_acc0 : STD_LOGIC; signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC; signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC; signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC; signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC; signal shandshake : STD_LOGIC; signal shandshake_r : STD_LOGIC; signal \^si_rs_bvalid\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair125"; attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair123"; attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair124"; attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair124"; begin si_rs_bvalid <= \^si_rs_bvalid\; bid_fifo_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo port map ( D(0) => bid_fifo_0_n_3, Q(1 downto 0) => cnt_read(1 downto 0), SR(0) => s_bresp_acc0, aclk => aclk, areset_d1 => areset_d1, b_push => b_push, \bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0), bresp_push => bresp_push, bvalid_i_reg => bid_fifo_0_n_5, bvalid_i_reg_0 => \^si_rs_bvalid\, \cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\, \cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0\, \in\(15 downto 0) => \in\(15 downto 0), mhandshake_r => mhandshake_r, \out\(11 downto 0) => \out\(11 downto 0), shandshake_r => shandshake_r, si_rs_bready => si_rs_bready ); \bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \bresp_cnt_reg__0\(0), O => p_0_in(0) ); \bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bresp_cnt_reg__0\(1), I1 => \bresp_cnt_reg__0\(0), O => p_0_in(1) ); \bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \bresp_cnt_reg__0\(2), I1 => \bresp_cnt_reg__0\(0), I2 => \bresp_cnt_reg__0\(1), O => p_0_in(2) ); \bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \bresp_cnt_reg__0\(3), I1 => \bresp_cnt_reg__0\(1), I2 => \bresp_cnt_reg__0\(0), I3 => \bresp_cnt_reg__0\(2), O => p_0_in(3) ); \bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \bresp_cnt_reg__0\(4), I1 => \bresp_cnt_reg__0\(2), I2 => \bresp_cnt_reg__0\(0), I3 => \bresp_cnt_reg__0\(1), I4 => \bresp_cnt_reg__0\(3), O => p_0_in(4) ); \bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => \bresp_cnt_reg__0\(5), I1 => \bresp_cnt_reg__0\(3), I2 => \bresp_cnt_reg__0\(1), I3 => \bresp_cnt_reg__0\(0), I4 => \bresp_cnt_reg__0\(2), I5 => \bresp_cnt_reg__0\(4), O => p_0_in(5) ); \bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \bresp_cnt_reg__0\(6), I1 => \bresp_cnt[7]_i_6_n_0\, O => p_0_in(6) ); \bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \bresp_cnt_reg__0\(7), I1 => \bresp_cnt[7]_i_6_n_0\, I2 => \bresp_cnt_reg__0\(6), O => p_0_in(7) ); \bresp_cnt[7]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \bresp_cnt_reg__0\(5), I1 => \bresp_cnt_reg__0\(3), I2 => \bresp_cnt_reg__0\(1), I3 => \bresp_cnt_reg__0\(0), I4 => \bresp_cnt_reg__0\(2), I5 => \bresp_cnt_reg__0\(4), O => \bresp_cnt[7]_i_6_n_0\ ); \bresp_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(0), Q => \bresp_cnt_reg__0\(0), R => s_bresp_acc0 ); \bresp_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(1), Q => \bresp_cnt_reg__0\(1), R => s_bresp_acc0 ); \bresp_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(2), Q => \bresp_cnt_reg__0\(2), R => s_bresp_acc0 ); \bresp_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(3), Q => \bresp_cnt_reg__0\(3), R => s_bresp_acc0 ); \bresp_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(4), Q => \bresp_cnt_reg__0\(4), R => s_bresp_acc0 ); \bresp_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(5), Q => \bresp_cnt_reg__0\(5), R => s_bresp_acc0 ); \bresp_cnt_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(6), Q => \bresp_cnt_reg__0\(6), R => s_bresp_acc0 ); \bresp_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => mhandshake_r, D => p_0_in(7), Q => \bresp_cnt_reg__0\(7), R => s_bresp_acc0 ); bresp_fifo_0: entity work.\design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0\ port map ( D(0) => bid_fifo_0_n_3, Q(1 downto 0) => cnt_read(1 downto 0), aclk => aclk, areset_d1 => areset_d1, \in\(1) => \s_bresp_acc_reg_n_0_[1]\, \in\(0) => \s_bresp_acc_reg_n_0_[0]\, m_axi_bready => m_axi_bready, m_axi_bvalid => m_axi_bvalid, mhandshake => mhandshake, mhandshake_r => mhandshake_r, sel => bresp_push, shandshake_r => shandshake_r, \skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0) ); bvalid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => bid_fifo_0_n_5, Q => \^si_rs_bvalid\, R => '0' ); mhandshake_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => mhandshake, Q => mhandshake_r, R => areset_d1 ); \s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000EACEAAAA" ) port map ( I0 => \s_bresp_acc_reg_n_0_[0]\, I1 => m_axi_bresp(0), I2 => m_axi_bresp(1), I3 => \s_bresp_acc_reg_n_0_[1]\, I4 => mhandshake, I5 => s_bresp_acc0, O => \s_bresp_acc[0]_i_1_n_0\ ); \s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"00EC" ) port map ( I0 => m_axi_bresp(1), I1 => \s_bresp_acc_reg_n_0_[1]\, I2 => mhandshake, I3 => s_bresp_acc0, O => \s_bresp_acc[1]_i_1_n_0\ ); \s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \s_bresp_acc[0]_i_1_n_0\, Q => \s_bresp_acc_reg_n_0_[0]\, R => '0' ); \s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \s_bresp_acc[1]_i_1_n_0\, Q => \s_bresp_acc_reg_n_0_[1]\, R => '0' ); shandshake_r_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^si_rs_bvalid\, I1 => si_rs_bready, O => shandshake ); shandshake_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => shandshake, Q => shandshake_r, R => areset_d1 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator is port ( next_pending_r_reg : out STD_LOGIC; wrap_next_pending : out STD_LOGIC; sel_first_reg_0 : out STD_LOGIC; sel_first_0 : out STD_LOGIC; sel_first : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 0 to 0 ); \axlen_cnt_reg[2]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); incr_next_pending : in STD_LOGIC; aclk : in STD_LOGIC; sel_first_i : in STD_LOGIC; \m_payload_i_reg[39]\ : in STD_LOGIC; \m_payload_i_reg[39]_0\ : in STD_LOGIC; sel_first_reg_1 : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 19 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_awvalid : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \m_payload_i_reg[47]_1\ : in STD_LOGIC; \next\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[0]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator is signal incr_cmd_0_n_10 : STD_LOGIC; signal incr_cmd_0_n_11 : STD_LOGIC; signal incr_cmd_0_n_12 : STD_LOGIC; signal incr_cmd_0_n_13 : STD_LOGIC; signal incr_cmd_0_n_14 : STD_LOGIC; signal incr_cmd_0_n_15 : STD_LOGIC; signal incr_cmd_0_n_16 : STD_LOGIC; signal incr_cmd_0_n_4 : STD_LOGIC; signal incr_cmd_0_n_5 : STD_LOGIC; signal incr_cmd_0_n_6 : STD_LOGIC; signal incr_cmd_0_n_7 : STD_LOGIC; signal incr_cmd_0_n_8 : STD_LOGIC; signal incr_cmd_0_n_9 : STD_LOGIC; signal s_axburst_eq0 : STD_LOGIC; signal s_axburst_eq1 : STD_LOGIC; begin incr_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd port map ( E(0) => E(0), Q(0) => Q(0), S(3 downto 0) => S(3 downto 0), aclk => aclk, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_incr_reg[0]_0\ => sel_first_0, \axaddr_incr_reg[11]_0\(10) => incr_cmd_0_n_4, \axaddr_incr_reg[11]_0\(9) => incr_cmd_0_n_5, \axaddr_incr_reg[11]_0\(8) => incr_cmd_0_n_6, \axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_7, \axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_8, \axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_9, \axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_10, \axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_11, \axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_12, \axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_13, \axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_14, \axlen_cnt_reg[2]_0\ => \axlen_cnt_reg[2]\, incr_next_pending => incr_next_pending, \m_axi_awaddr[11]\ => incr_cmd_0_n_15, \m_axi_awaddr[5]\ => incr_cmd_0_n_16, \m_payload_i_reg[46]\(9 downto 8) => \m_payload_i_reg[47]\(18 downto 17), \m_payload_i_reg[46]\(7 downto 5) => \m_payload_i_reg[47]\(14 downto 12), \m_payload_i_reg[46]\(4) => \m_payload_i_reg[47]\(5), \m_payload_i_reg[46]\(3 downto 0) => \m_payload_i_reg[47]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \next\ => \next\, next_pending_r_reg_0 => next_pending_r_reg, sel_first_reg_0 => sel_first_reg_1, \state_reg[0]\(0) => \state_reg[0]\(0), \state_reg[0]_rep\ => \state_reg[0]_rep\, \state_reg[1]\(0) => \state_reg[1]_0\(0) ); \memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axburst_eq1, I1 => \m_payload_i_reg[47]\(15), I2 => s_axburst_eq0, O => \state_reg[1]_rep\ ); s_axburst_eq0_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]\, Q => s_axburst_eq0, R => '0' ); s_axburst_eq1_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \m_payload_i_reg[39]_0\, Q => s_axburst_eq1, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_i, Q => sel_first_reg_0, R => '0' ); wrap_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd port map ( D(3 downto 0) => D(3 downto 0), E(0) => E(0), aclk => aclk, \axaddr_incr_reg[11]\(10) => incr_cmd_0_n_4, \axaddr_incr_reg[11]\(9) => incr_cmd_0_n_5, \axaddr_incr_reg[11]\(8) => incr_cmd_0_n_6, \axaddr_incr_reg[11]\(7) => incr_cmd_0_n_7, \axaddr_incr_reg[11]\(6) => incr_cmd_0_n_8, \axaddr_incr_reg[11]\(5) => incr_cmd_0_n_9, \axaddr_incr_reg[11]\(4) => incr_cmd_0_n_10, \axaddr_incr_reg[11]\(3) => incr_cmd_0_n_11, \axaddr_incr_reg[11]\(2) => incr_cmd_0_n_12, \axaddr_incr_reg[11]\(1) => incr_cmd_0_n_13, \axaddr_incr_reg[11]\(0) => incr_cmd_0_n_14, \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), \m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[47]\(19 downto 15), \m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[47]\(13 downto 0), \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_1\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \next\ => \next\, sel_first_reg_0 => sel_first, sel_first_reg_1 => sel_first_reg_2, sel_first_reg_2 => incr_cmd_0_n_15, sel_first_reg_3 => incr_cmd_0_n_16, si_rs_awvalid => si_rs_awvalid, \state_reg[0]\(0) => \state_reg[0]\(0), \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0), \wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is port ( sel_first_reg_0 : out STD_LOGIC; sel_first : out STD_LOGIC; sel_first_reg_1 : out STD_LOGIC; \axlen_cnt_reg[0]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); r_rlast : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; sel_first_i : in STD_LOGIC; sel_first_reg_2 : in STD_LOGIC; sel_first_reg_3 : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 19 downto 0 ); \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); si_rs_arvalid : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; \state_reg[1]_rep\ : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[0]_rep_0\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \state_reg[1]_0\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ); sel_first_reg_4 : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arready : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_17_b2s_cmd_translator"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 is signal incr_cmd_0_n_10 : STD_LOGIC; signal incr_cmd_0_n_11 : STD_LOGIC; signal incr_cmd_0_n_12 : STD_LOGIC; signal incr_cmd_0_n_13 : STD_LOGIC; signal incr_cmd_0_n_14 : STD_LOGIC; signal incr_cmd_0_n_15 : STD_LOGIC; signal incr_cmd_0_n_3 : STD_LOGIC; signal incr_cmd_0_n_4 : STD_LOGIC; signal incr_cmd_0_n_5 : STD_LOGIC; signal incr_cmd_0_n_6 : STD_LOGIC; signal incr_cmd_0_n_7 : STD_LOGIC; signal incr_cmd_0_n_8 : STD_LOGIC; signal incr_cmd_0_n_9 : STD_LOGIC; signal incr_next_pending : STD_LOGIC; signal s_axburst_eq0 : STD_LOGIC; signal s_axburst_eq1 : STD_LOGIC; signal wrap_cmd_0_n_6 : STD_LOGIC; signal wrap_cmd_0_n_7 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair17"; begin incr_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 port map ( E(0) => E(0), O(3 downto 0) => O(3 downto 0), Q(10 downto 8) => Q(18 downto 16), Q(7 downto 5) => Q(14 downto 12), Q(4) => Q(5), Q(3 downto 0) => Q(3 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, \axaddr_incr_reg[0]_0\ => sel_first, \axaddr_incr_reg[11]_0\(7) => incr_cmd_0_n_3, \axaddr_incr_reg[11]_0\(6) => incr_cmd_0_n_4, \axaddr_incr_reg[11]_0\(5) => incr_cmd_0_n_5, \axaddr_incr_reg[11]_0\(4) => incr_cmd_0_n_6, \axaddr_incr_reg[11]_0\(3) => incr_cmd_0_n_7, \axaddr_incr_reg[11]_0\(2) => incr_cmd_0_n_8, \axaddr_incr_reg[11]_0\(1) => incr_cmd_0_n_9, \axaddr_incr_reg[11]_0\(0) => incr_cmd_0_n_10, \axlen_cnt_reg[0]_0\ => \axlen_cnt_reg[0]\, incr_next_pending => incr_next_pending, \m_axi_araddr[11]\ => incr_cmd_0_n_11, \m_axi_araddr[1]\ => incr_cmd_0_n_15, \m_axi_araddr[2]\ => incr_cmd_0_n_14, \m_axi_araddr[3]\ => incr_cmd_0_n_13, \m_axi_araddr[5]\ => incr_cmd_0_n_12, m_axi_arready => m_axi_arready, \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0), m_valid_i_reg(0) => m_valid_i_reg(0), sel_first_reg_0 => sel_first_reg_2, sel_first_reg_1(0) => sel_first_reg_4(0), si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\ => \state_reg[0]_rep_0\, \state_reg[1]\ => \state_reg[1]_0\, \state_reg[1]_0\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\ ); r_rlast_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"1D" ) port map ( I0 => s_axburst_eq0, I1 => Q(15), I2 => s_axburst_eq1, O => r_rlast ); s_axburst_eq0_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cmd_0_n_6, Q => s_axburst_eq0, R => '0' ); s_axburst_eq1_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => wrap_cmd_0_n_7, Q => s_axburst_eq1, R => '0' ); sel_first_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => sel_first_i, Q => sel_first_reg_0, R => '0' ); \state[1]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => s_axburst_eq1, I1 => Q(15), I2 => s_axburst_eq0, O => \state_reg[0]_rep\ ); wrap_cmd_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 port map ( D(3 downto 0) => D(3 downto 0), E(0) => E(0), Q(18 downto 14) => Q(19 downto 15), Q(13 downto 0) => Q(13 downto 0), aclk => aclk, \axaddr_incr_reg[11]\(7) => incr_cmd_0_n_3, \axaddr_incr_reg[11]\(6) => incr_cmd_0_n_4, \axaddr_incr_reg[11]\(5) => incr_cmd_0_n_5, \axaddr_incr_reg[11]\(4) => incr_cmd_0_n_6, \axaddr_incr_reg[11]\(3) => incr_cmd_0_n_7, \axaddr_incr_reg[11]\(2) => incr_cmd_0_n_8, \axaddr_incr_reg[11]\(1) => incr_cmd_0_n_9, \axaddr_incr_reg[11]\(0) => incr_cmd_0_n_10, \axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_2\ => \axaddr_offset_r_reg[3]_1\, incr_next_pending => incr_next_pending, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), m_valid_i_reg(0) => m_valid_i_reg(0), s_axburst_eq0_reg => wrap_cmd_0_n_6, s_axburst_eq1_reg => wrap_cmd_0_n_7, sel_first_i => sel_first_i, sel_first_reg_0 => sel_first_reg_1, sel_first_reg_1 => sel_first_reg_3, sel_first_reg_2 => incr_cmd_0_n_11, sel_first_reg_3 => incr_cmd_0_n_12, sel_first_reg_4 => incr_cmd_0_n_13, sel_first_reg_5 => incr_cmd_0_n_14, sel_first_reg_6 => incr_cmd_0_n_15, si_rs_arvalid => si_rs_arvalid, \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0), \wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel is port ( m_valid_i_reg : out STD_LOGIC; \state_reg[1]_rep\ : out STD_LOGIC; m_axi_rready : out STD_LOGIC; \out\ : out STD_LOGIC_VECTOR ( 33 downto 0 ); \skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 ); \state_reg[1]_rep_0\ : in STD_LOGIC; aclk : in STD_LOGIC; r_rlast : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; si_rs_rready : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); areset_d1 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 11 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel is signal \^m_valid_i_reg\ : STD_LOGIC; signal r_push_r : STD_LOGIC; signal rd_data_fifo_0_n_0 : STD_LOGIC; signal rd_data_fifo_0_n_1 : STD_LOGIC; signal rd_data_fifo_0_n_2 : STD_LOGIC; signal rd_data_fifo_0_n_4 : STD_LOGIC; signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 ); begin m_valid_i_reg <= \^m_valid_i_reg\; \r_arid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(0), Q => trans_in(1), R => '0' ); \r_arid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(10), Q => trans_in(11), R => '0' ); \r_arid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(11), Q => trans_in(12), R => '0' ); \r_arid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(1), Q => trans_in(2), R => '0' ); \r_arid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(2), Q => trans_in(3), R => '0' ); \r_arid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(3), Q => trans_in(4), R => '0' ); \r_arid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(4), Q => trans_in(5), R => '0' ); \r_arid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(5), Q => trans_in(6), R => '0' ); \r_arid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(6), Q => trans_in(7), R => '0' ); \r_arid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(7), Q => trans_in(8), R => '0' ); \r_arid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(8), Q => trans_in(9), R => '0' ); \r_arid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => D(9), Q => trans_in(10), R => '0' ); r_push_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => \state_reg[1]_rep_0\, Q => r_push_r, R => '0' ); r_rlast_r_reg: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => r_rlast, Q => trans_in(0), R => '0' ); rd_data_fifo_0: entity work.\design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1\ port map ( aclk => aclk, areset_d1 => areset_d1, \cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\, \cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_0, \cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_1, \cnt_read_reg[4]_rep__2_2\ => rd_data_fifo_0_n_2, \in\(33 downto 0) => \in\(33 downto 0), m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, \out\(33 downto 0) => \out\(33 downto 0), s_ready_i_reg => s_ready_i_reg, si_rs_rready => si_rs_rready, \state_reg[1]_rep\ => rd_data_fifo_0_n_4 ); transaction_fifo_0: entity work.\design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2\ port map ( aclk => aclk, areset_d1 => areset_d1, \cnt_read_reg[0]_rep__3\ => rd_data_fifo_0_n_2, \cnt_read_reg[0]_rep__3_0\ => rd_data_fifo_0_n_4, \cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0, \cnt_read_reg[4]_rep__2\ => rd_data_fifo_0_n_1, \in\(12 downto 0) => trans_in(12 downto 0), m_valid_i_reg => \^m_valid_i_reg\, r_push_r => r_push_r, s_ready_i_reg => s_ready_i_reg, si_rs_rready => si_rs_rready, \skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice is port ( s_axi_awready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; si_rs_awvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; si_rs_bready : out STD_LOGIC; si_rs_arvalid : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; si_rs_rready : out STD_LOGIC; \axlen_cnt_reg[3]\ : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 54 downto 0 ); \axlen_cnt_reg[3]_0\ : out STD_LOGIC; \s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 54 downto 0 ); axaddr_incr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); O : out STD_LOGIC_VECTOR ( 3 downto 0 ); D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]\ : out STD_LOGIC; axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \axaddr_offset_r_reg[2]\ : out STD_LOGIC; next_pending_r_reg : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[2]_0\ : out STD_LOGIC; axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; \axaddr_offset_r_reg[2]_0\ : out STD_LOGIC; next_pending_r_reg_0 : out STD_LOGIC; \cnt_read_reg[2]_rep__0\ : out STD_LOGIC; \wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); aclk : in STD_LOGIC; s_ready_i0 : in STD_LOGIC; m_valid_i0 : in STD_LOGIC; aresetn : in STD_LOGIC; \state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \cnt_read_reg[4]_rep__0\ : in STD_LOGIC; s_axi_rready : in STD_LOGIC; S : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep\ : in STD_LOGIC; \wrap_second_len_r_reg[1]\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_2\ : in STD_LOGIC; \state_reg[0]_rep\ : in STD_LOGIC; \state_reg[1]_rep_0\ : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; b_push : in STD_LOGIC; \wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \state_reg[1]_rep_1\ : in STD_LOGIC; \wrap_second_len_r_reg[1]_0\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_2\ : in STD_LOGIC; \axaddr_offset_r_reg[2]_4\ : in STD_LOGIC; \state_reg[0]_rep_0\ : in STD_LOGIC; \state_reg[1]_rep_2\ : in STD_LOGIC; si_rs_bvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); \out\ : in STD_LOGIC_VECTOR ( 11 downto 0 ); \s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 ); \cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice; architecture STRUCTURE of design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice is signal \ar.ar_pipe_n_2\ : STD_LOGIC; signal \aw.aw_pipe_n_1\ : STD_LOGIC; signal \aw.aw_pipe_n_90\ : STD_LOGIC; begin \ar.ar_pipe\: entity work.design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice port map ( O(3 downto 0) => O(3 downto 0), Q(54 downto 0) => \s_arid_r_reg[11]\(54 downto 0), aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[0]_0\ => \aw.aw_pipe_n_90\, \axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0), \axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0), axaddr_offset_0(1 downto 0) => axaddr_offset_0(2 downto 1), \axaddr_offset_r_reg[0]\ => axaddr_offset_0(0), \axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]_0\, \axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_3\(0), \axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_4\, \axaddr_offset_r_reg[3]\ => si_rs_arvalid, \axaddr_offset_r_reg[3]_0\(2 downto 0) => \axaddr_offset_r_reg[3]_1\(2 downto 0), \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_2\, \axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\, \m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), m_valid_i0 => m_valid_i0, m_valid_i_reg_0 => \ar.ar_pipe_n_2\, m_valid_i_reg_1(0) => m_valid_i_reg(0), next_pending_r_reg => next_pending_r_reg_0, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_ready_i0 => s_ready_i0, \state_reg[0]_rep\ => \state_reg[0]_rep_0\, \state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep_1\, \state_reg[1]_rep_0\ => \state_reg[1]_rep_2\, \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0), \wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]_0\, \wrap_cnt_r_reg[3]\(1 downto 0) => \wrap_cnt_r_reg[3]_0\(1 downto 0), \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, \wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]_0\, \wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_2\(3 downto 0) ); \aw.aw_pipe\: entity work.design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice_0 port map ( D(1 downto 0) => D(1 downto 0), E(0) => E(0), Q(54 downto 0) => Q(54 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, aresetn => aresetn, \aresetn_d_reg[1]_inv\ => \aw.aw_pipe_n_90\, \aresetn_d_reg[1]_inv_0\ => \ar.ar_pipe_n_2\, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), axaddr_offset(1 downto 0) => axaddr_offset(2 downto 1), \axaddr_offset_r_reg[0]\ => axaddr_offset(0), \axaddr_offset_r_reg[2]\ => \axaddr_offset_r_reg[2]\, \axaddr_offset_r_reg[2]_0\(0) => \axaddr_offset_r_reg[2]_1\(0), \axaddr_offset_r_reg[2]_1\ => \axaddr_offset_r_reg[2]_2\, \axaddr_offset_r_reg[3]\(2 downto 0) => \axaddr_offset_r_reg[3]\(2 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\, b_push => b_push, m_valid_i_reg_0 => si_rs_awvalid, next_pending_r_reg => next_pending_r_reg, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, s_ready_i_reg_0 => \aw.aw_pipe_n_1\, \state_reg[0]_rep\ => \state_reg[0]_rep\, \state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0), \state_reg[1]_rep\ => \state_reg[1]_rep\, \state_reg[1]_rep_0\ => \state_reg[1]_rep_0\, \wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0), \wrap_cnt_r_reg[2]\ => \wrap_cnt_r_reg[2]\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[1]\ => \wrap_second_len_r_reg[1]\, \wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0) ); \b.b_pipe\: entity work.\design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized1\ port map ( aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\, \out\(11 downto 0) => \out\(11 downto 0), \s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0), si_rs_bvalid => si_rs_bvalid, \skid_buffer_reg[0]_0\ => si_rs_bready ); \r.r_pipe\: entity work.\design_1_auto_pc_0_axi_register_slice_v2_1_17_axic_register_slice__parameterized2\ port map ( aclk => aclk, \aresetn_d_reg[0]\ => \aw.aw_pipe_n_1\, \aresetn_d_reg[1]_inv\ => \ar.ar_pipe_n_2\, \cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\, \cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0), \cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\, r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0), \s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, \skid_buffer_reg[0]_0\ => si_rs_rready ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel is port ( \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); r_push_r_reg : out STD_LOGIC; \m_payload_i_reg[0]\ : out STD_LOGIC; \m_payload_i_reg[0]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; m_valid_i0 : out STD_LOGIC; s_ready_i0 : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); r_rlast : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arready : in STD_LOGIC; si_rs_arvalid : in STD_LOGIC; \cnt_read_reg[2]_rep__0\ : in STD_LOGIC; \m_payload_i_reg[47]\ : in STD_LOGIC; \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[47]_0\ : in STD_LOGIC; areset_d1 : in STD_LOGIC; \m_payload_i_reg[5]\ : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_ready_i_reg : in STD_LOGIC; O : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel is signal ar_cmd_fsm_0_n_0 : STD_LOGIC; signal ar_cmd_fsm_0_n_10 : STD_LOGIC; signal ar_cmd_fsm_0_n_16 : STD_LOGIC; signal ar_cmd_fsm_0_n_6 : STD_LOGIC; signal ar_cmd_fsm_0_n_8 : STD_LOGIC; signal ar_cmd_fsm_0_n_9 : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal cmd_translator_0_n_0 : STD_LOGIC; signal cmd_translator_0_n_10 : STD_LOGIC; signal cmd_translator_0_n_2 : STD_LOGIC; signal cmd_translator_0_n_3 : STD_LOGIC; signal \incr_cmd_0/sel_first\ : STD_LOGIC; signal \^m_payload_i_reg[0]_0\ : STD_LOGIC; signal \^r_push_r_reg\ : STD_LOGIC; signal sel_first_i : STD_LOGIC; signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC; signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 ); begin \axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0); \axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0); \m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\; r_push_r_reg <= \^r_push_r_reg\; \state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0); \wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\; \wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0); ar_cmd_fsm_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm port map ( D(0) => ar_cmd_fsm_0_n_6, E(0) => ar_cmd_fsm_0_n_8, Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), aclk => aclk, areset_d1 => areset_d1, \axaddr_incr_reg[0]\(0) => ar_cmd_fsm_0_n_16, axaddr_offset(0) => axaddr_offset(0), \axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0), \axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2), \axlen_cnt_reg[7]\ => ar_cmd_fsm_0_n_0, \axlen_cnt_reg[7]_0\ => cmd_translator_0_n_3, \cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\, m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, \m_payload_i_reg[0]\ => \m_payload_i_reg[0]\, \m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]_0\, \m_payload_i_reg[0]_1\(0) => E(0), \m_payload_i_reg[46]\(0) => Q(18), \m_payload_i_reg[5]\ => \m_payload_i_reg[5]\, m_valid_i0 => m_valid_i0, r_push_r_reg => \^r_push_r_reg\, s_axburst_eq1_reg => cmd_translator_0_n_10, s_axi_arvalid => s_axi_arvalid, s_ready_i0 => s_ready_i0, s_ready_i_reg => s_ready_i_reg, sel_first => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg => ar_cmd_fsm_0_n_9, sel_first_reg_0 => ar_cmd_fsm_0_n_10, sel_first_reg_1 => cmd_translator_0_n_2, sel_first_reg_2 => cmd_translator_0_n_0, si_rs_arvalid => si_rs_arvalid, \wrap_boundary_axaddr_r_reg[11]\(0) => \^wrap_boundary_axaddr_r_reg[11]\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, \wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0) ); cmd_translator_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 port map ( D(3) => axaddr_offset(2), D(2) => \^axaddr_offset_r_reg[2]\(0), D(1 downto 0) => axaddr_offset(1 downto 0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, O(3 downto 0) => O(3 downto 0), Q(19 downto 0) => Q(19 downto 0), S(3 downto 0) => S(3 downto 0), aclk => aclk, \axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\, \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[0]\ => cmd_translator_0_n_3, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), m_axi_arready => m_axi_arready, \m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \m_payload_i_reg[7]\(3 downto 0) => \m_payload_i_reg[7]\(3 downto 0), m_valid_i_reg(0) => ar_cmd_fsm_0_n_8, r_rlast => r_rlast, sel_first => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg_0 => cmd_translator_0_n_0, sel_first_reg_1 => cmd_translator_0_n_2, sel_first_reg_2 => ar_cmd_fsm_0_n_10, sel_first_reg_3 => ar_cmd_fsm_0_n_9, sel_first_reg_4(0) => ar_cmd_fsm_0_n_16, si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\ => cmd_translator_0_n_10, \state_reg[0]_rep_0\ => \^m_payload_i_reg[0]_0\, \state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), \state_reg[1]_0\ => ar_cmd_fsm_0_n_0, \state_reg[1]_rep\ => \^r_push_r_reg\, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, \wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_0\(3 downto 1) => D(2 downto 0), \wrap_second_len_r_reg[3]_0\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[3]_1\(2 downto 1) => \wrap_second_len_r_reg[3]_0\(1 downto 0), \wrap_second_len_r_reg[3]_1\(0) => ar_cmd_fsm_0_n_6 ); \s_arid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(20), Q => \r_arid_r_reg[11]\(0), R => '0' ); \s_arid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(30), Q => \r_arid_r_reg[11]\(10), R => '0' ); \s_arid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(31), Q => \r_arid_r_reg[11]\(11), R => '0' ); \s_arid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(21), Q => \r_arid_r_reg[11]\(1), R => '0' ); \s_arid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(22), Q => \r_arid_r_reg[11]\(2), R => '0' ); \s_arid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(23), Q => \r_arid_r_reg[11]\(3), R => '0' ); \s_arid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(24), Q => \r_arid_r_reg[11]\(4), R => '0' ); \s_arid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(25), Q => \r_arid_r_reg[11]\(5), R => '0' ); \s_arid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(26), Q => \r_arid_r_reg[11]\(6), R => '0' ); \s_arid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(27), Q => \r_arid_r_reg[11]\(7), R => '0' ); \s_arid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(28), Q => \r_arid_r_reg[11]\(8), R => '0' ); \s_arid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(29), Q => \r_arid_r_reg[11]\(9), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel is port ( \wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC; \state_reg[0]_rep\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); \axlen_cnt_reg[7]\ : out STD_LOGIC; \axlen_cnt_reg[7]_0\ : out STD_LOGIC; \wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 ); \wrap_cnt_r_reg[3]\ : out STD_LOGIC; \wrap_cnt_r_reg[3]_0\ : out STD_LOGIC; \axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_cnt_r_reg[3]_1\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); b_push : out STD_LOGIC; m_axi_awvalid : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); \in\ : out STD_LOGIC_VECTOR ( 15 downto 0 ); S : out STD_LOGIC_VECTOR ( 3 downto 0 ); aclk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 31 downto 0 ); si_rs_awvalid : in STD_LOGIC; \cnt_read_reg[1]_rep__0\ : in STD_LOGIC; \cnt_read_reg[0]_rep__0\ : in STD_LOGIC; m_axi_awready : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 1 downto 0 ); \axaddr_offset_r_reg[3]_0\ : in STD_LOGIC; axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 ); \axaddr_offset_r_reg[3]_1\ : in STD_LOGIC; \wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \m_payload_i_reg[47]\ : in STD_LOGIC; \m_payload_i_reg[47]_0\ : in STD_LOGIC; areset_d1 : in STD_LOGIC; \m_payload_i_reg[5]\ : in STD_LOGIC; axaddr_incr : in STD_LOGIC_VECTOR ( 11 downto 0 ); \m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 ) ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel is signal aw_cmd_fsm_0_n_12 : STD_LOGIC; signal aw_cmd_fsm_0_n_14 : STD_LOGIC; signal aw_cmd_fsm_0_n_15 : STD_LOGIC; signal aw_cmd_fsm_0_n_16 : STD_LOGIC; signal aw_cmd_fsm_0_n_2 : STD_LOGIC; signal aw_cmd_fsm_0_n_8 : STD_LOGIC; signal aw_cmd_fsm_0_n_9 : STD_LOGIC; signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal cmd_translator_0_n_0 : STD_LOGIC; signal cmd_translator_0_n_12 : STD_LOGIC; signal cmd_translator_0_n_2 : STD_LOGIC; signal cmd_translator_0_n_5 : STD_LOGIC; signal cmd_translator_0_n_6 : STD_LOGIC; signal \incr_cmd_0/sel_first\ : STD_LOGIC; signal incr_next_pending : STD_LOGIC; signal \next\ : STD_LOGIC; signal sel_first : STD_LOGIC; signal sel_first_i : STD_LOGIC; signal \^state_reg[0]_rep\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC; signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 to 2 ); signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 0 to 0 ); signal wrap_next_pending : STD_LOGIC; signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 ); begin \axaddr_offset_r_reg[2]\(0) <= \^axaddr_offset_r_reg[2]\(0); \axaddr_offset_r_reg[3]\(2 downto 0) <= \^axaddr_offset_r_reg[3]\(2 downto 0); \state_reg[0]_rep\(1 downto 0) <= \^state_reg[0]_rep\(1 downto 0); \wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\; \wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0); aw_cmd_fsm_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm port map ( D(0) => wrap_cnt(0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, Q(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), aclk => aclk, areset_d1 => areset_d1, axaddr_offset(0) => axaddr_offset(0), \axaddr_offset_r_reg[2]\(0) => \^axaddr_offset_r_reg[2]\(0), \axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\, \axaddr_offset_r_reg[3]_0\(1) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]_0\(0) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_wrap_reg[11]\(0) => aw_cmd_fsm_0_n_14, \axlen_cnt_reg[0]\(0) => aw_cmd_fsm_0_n_8, \axlen_cnt_reg[0]_0\(0) => cmd_translator_0_n_5, \axlen_cnt_reg[7]\ => \axlen_cnt_reg[7]\, \axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]_0\, \axlen_cnt_reg[7]_1\ => aw_cmd_fsm_0_n_2, \axlen_cnt_reg[7]_2\ => cmd_translator_0_n_6, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\, \cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\, incr_next_pending => incr_next_pending, m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, \m_payload_i_reg[0]\(0) => E(0), \m_payload_i_reg[46]\(2) => Q(18), \m_payload_i_reg[46]\(1 downto 0) => Q(16 downto 15), \m_payload_i_reg[47]\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[5]\ => \m_payload_i_reg[5]\, \next\ => \next\, next_pending_r_reg => cmd_translator_0_n_0, s_axburst_eq0_reg => aw_cmd_fsm_0_n_9, s_axburst_eq1_reg => aw_cmd_fsm_0_n_12, s_axburst_eq1_reg_0 => cmd_translator_0_n_12, sel_first => sel_first, sel_first_0 => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg => aw_cmd_fsm_0_n_15, sel_first_reg_0 => aw_cmd_fsm_0_n_16, sel_first_reg_1 => cmd_translator_0_n_2, si_rs_awvalid => si_rs_awvalid, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]_0\, \wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[0]\(0) => \wrap_cmd_0/wrap_second_len\(0), \wrap_second_len_r_reg[0]_0\(0) => \^wrap_second_len_r_reg[3]\(0) ); cmd_translator_0: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_cmd_translator port map ( D(3) => axaddr_offset(2), D(2) => \^axaddr_offset_r_reg[2]\(0), D(1 downto 0) => axaddr_offset(1 downto 0), E(0) => \^wrap_boundary_axaddr_r_reg[11]\, Q(0) => cmd_translator_0_n_5, S(3 downto 0) => S(3 downto 0), aclk => aclk, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_offset_r_reg[3]\(3) => \^axaddr_offset_r_reg[3]\(2), \axaddr_offset_r_reg[3]\(2) => \wrap_cmd_0/axaddr_offset_r\(2), \axaddr_offset_r_reg[3]\(1 downto 0) => \^axaddr_offset_r_reg[3]\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \axaddr_offset_r_reg[3]_1\, \axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\, \axlen_cnt_reg[2]\ => cmd_translator_0_n_6, incr_next_pending => incr_next_pending, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), \m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_9, \m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_12, \m_payload_i_reg[47]\(19 downto 0) => Q(19 downto 0), \m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]\, \m_payload_i_reg[47]_1\ => \m_payload_i_reg[47]_0\, \m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0), \next\ => \next\, next_pending_r_reg => cmd_translator_0_n_0, sel_first => sel_first, sel_first_0 => \incr_cmd_0/sel_first\, sel_first_i => sel_first_i, sel_first_reg_0 => cmd_translator_0_n_2, sel_first_reg_1 => aw_cmd_fsm_0_n_16, sel_first_reg_2 => aw_cmd_fsm_0_n_15, si_rs_awvalid => si_rs_awvalid, \state_reg[0]\(0) => aw_cmd_fsm_0_n_14, \state_reg[0]_rep\ => aw_cmd_fsm_0_n_2, \state_reg[1]\(1 downto 0) => \^state_reg[0]_rep\(1 downto 0), \state_reg[1]_0\(0) => aw_cmd_fsm_0_n_8, \state_reg[1]_rep\ => cmd_translator_0_n_12, \wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\, wrap_next_pending => wrap_next_pending, \wrap_second_len_r_reg[3]\(3 downto 0) => \^wrap_second_len_r_reg[3]\(3 downto 0), \wrap_second_len_r_reg[3]_0\(2 downto 1) => D(1 downto 0), \wrap_second_len_r_reg[3]_0\(0) => wrap_cnt(0), \wrap_second_len_r_reg[3]_1\(3 downto 1) => \wrap_second_len_r_reg[3]_0\(2 downto 0), \wrap_second_len_r_reg[3]_1\(0) => \wrap_cmd_0/wrap_second_len\(0) ); \s_awid_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(20), Q => \in\(4), R => '0' ); \s_awid_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(30), Q => \in\(14), R => '0' ); \s_awid_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(31), Q => \in\(15), R => '0' ); \s_awid_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(21), Q => \in\(5), R => '0' ); \s_awid_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(22), Q => \in\(6), R => '0' ); \s_awid_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(23), Q => \in\(7), R => '0' ); \s_awid_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(24), Q => \in\(8), R => '0' ); \s_awid_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(25), Q => \in\(9), R => '0' ); \s_awid_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(26), Q => \in\(10), R => '0' ); \s_awid_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(27), Q => \in\(11), R => '0' ); \s_awid_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(28), Q => \in\(12), R => '0' ); \s_awid_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(29), Q => \in\(13), R => '0' ); \s_awlen_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(16), Q => \in\(0), R => '0' ); \s_awlen_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(17), Q => \in\(1), R => '0' ); \s_awlen_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(18), Q => \in\(2), R => '0' ); \s_awlen_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => aclk, CE => '1', D => Q(19), Q => \in\(3), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s is port ( s_axi_rvalid : out STD_LOGIC; s_axi_awready : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 22 downto 0 ); s_axi_arready : out STD_LOGIC; \m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 ); s_axi_bvalid : out STD_LOGIC; \s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 ); \s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arvalid : out STD_LOGIC; m_axi_rready : out STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awready : in STD_LOGIC; m_axi_arready : in STD_LOGIC; s_axi_rready : in STD_LOGIC; aclk : in STD_LOGIC; \in\ : in STD_LOGIC_VECTOR ( 33 downto 0 ); s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awvalid : in STD_LOGIC; m_axi_bvalid : in STD_LOGIC; m_axi_rvalid : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; aresetn : in STD_LOGIC ); end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s is signal \RD.ar_channel_0_n_0\ : STD_LOGIC; signal \RD.ar_channel_0_n_10\ : STD_LOGIC; signal \RD.ar_channel_0_n_11\ : STD_LOGIC; signal \RD.ar_channel_0_n_16\ : STD_LOGIC; signal \RD.ar_channel_0_n_3\ : STD_LOGIC; signal \RD.ar_channel_0_n_4\ : STD_LOGIC; signal \RD.ar_channel_0_n_46\ : STD_LOGIC; signal \RD.ar_channel_0_n_47\ : STD_LOGIC; signal \RD.ar_channel_0_n_48\ : STD_LOGIC; signal \RD.ar_channel_0_n_49\ : STD_LOGIC; signal \RD.ar_channel_0_n_5\ : STD_LOGIC; signal \RD.r_channel_0_n_0\ : STD_LOGIC; signal \RD.r_channel_0_n_1\ : STD_LOGIC; signal SI_REG_n_132 : STD_LOGIC; signal SI_REG_n_133 : STD_LOGIC; signal SI_REG_n_134 : STD_LOGIC; signal SI_REG_n_135 : STD_LOGIC; signal SI_REG_n_136 : STD_LOGIC; signal SI_REG_n_137 : STD_LOGIC; signal SI_REG_n_138 : STD_LOGIC; signal SI_REG_n_139 : STD_LOGIC; signal SI_REG_n_140 : STD_LOGIC; signal SI_REG_n_141 : STD_LOGIC; signal SI_REG_n_142 : STD_LOGIC; signal SI_REG_n_143 : STD_LOGIC; signal SI_REG_n_149 : STD_LOGIC; signal SI_REG_n_153 : STD_LOGIC; signal SI_REG_n_154 : STD_LOGIC; signal SI_REG_n_155 : STD_LOGIC; signal SI_REG_n_156 : STD_LOGIC; signal SI_REG_n_157 : STD_LOGIC; signal SI_REG_n_161 : STD_LOGIC; signal SI_REG_n_165 : STD_LOGIC; signal SI_REG_n_166 : STD_LOGIC; signal SI_REG_n_167 : STD_LOGIC; signal SI_REG_n_168 : STD_LOGIC; signal SI_REG_n_169 : STD_LOGIC; signal SI_REG_n_170 : STD_LOGIC; signal SI_REG_n_171 : STD_LOGIC; signal SI_REG_n_172 : STD_LOGIC; signal SI_REG_n_173 : STD_LOGIC; signal SI_REG_n_174 : STD_LOGIC; signal SI_REG_n_175 : STD_LOGIC; signal SI_REG_n_176 : STD_LOGIC; signal SI_REG_n_177 : STD_LOGIC; signal SI_REG_n_178 : STD_LOGIC; signal SI_REG_n_179 : STD_LOGIC; signal SI_REG_n_180 : STD_LOGIC; signal SI_REG_n_181 : STD_LOGIC; signal SI_REG_n_182 : STD_LOGIC; signal SI_REG_n_26 : STD_LOGIC; signal SI_REG_n_64 : STD_LOGIC; signal SI_REG_n_8 : STD_LOGIC; signal SI_REG_n_82 : STD_LOGIC; signal \WR.aw_channel_0_n_0\ : STD_LOGIC; signal \WR.aw_channel_0_n_10\ : STD_LOGIC; signal \WR.aw_channel_0_n_15\ : STD_LOGIC; signal \WR.aw_channel_0_n_3\ : STD_LOGIC; signal \WR.aw_channel_0_n_4\ : STD_LOGIC; signal \WR.aw_channel_0_n_47\ : STD_LOGIC; signal \WR.aw_channel_0_n_48\ : STD_LOGIC; signal \WR.aw_channel_0_n_49\ : STD_LOGIC; signal \WR.aw_channel_0_n_50\ : STD_LOGIC; signal \WR.aw_channel_0_n_9\ : STD_LOGIC; signal \WR.b_channel_0_n_1\ : STD_LOGIC; signal \WR.b_channel_0_n_2\ : STD_LOGIC; signal \ar.ar_pipe/m_valid_i0\ : STD_LOGIC; signal \ar.ar_pipe/p_1_in\ : STD_LOGIC; signal \ar.ar_pipe/s_ready_i0\ : STD_LOGIC; signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal areset_d1 : STD_LOGIC; signal areset_d1_i_1_n_0 : STD_LOGIC; signal \aw.aw_pipe/p_1_in\ : STD_LOGIC; signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axaddr_incr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal b_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal b_push : STD_LOGIC; signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal r_rlast : STD_LOGIC; signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 ); signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \^s_axi_arready\ : STD_LOGIC; signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 ); signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_arvalid : STD_LOGIC; signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 ); signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 ); signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_awvalid : STD_LOGIC; signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_bready : STD_LOGIC; signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal si_rs_bvalid : STD_LOGIC; signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 ); signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 ); signal si_rs_rlast : STD_LOGIC; signal si_rs_rready : STD_LOGIC; signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 ); signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 2 ); begin s_axi_arready <= \^s_axi_arready\; \RD.ar_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_ar_channel port map ( D(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1), E(0) => \ar.ar_pipe/p_1_in\, O(3) => SI_REG_n_140, O(2) => SI_REG_n_141, O(1) => SI_REG_n_142, O(0) => SI_REG_n_143, Q(31 downto 20) => s_arid(11 downto 0), Q(19 downto 16) => si_rs_arlen(3 downto 0), Q(15) => si_rs_arburst(1), Q(14) => SI_REG_n_82, Q(13 downto 12) => si_rs_arsize(1 downto 0), Q(11 downto 0) => si_rs_araddr(11 downto 0), S(3) => \RD.ar_channel_0_n_46\, S(2) => \RD.ar_channel_0_n_47\, S(1) => \RD.ar_channel_0_n_48\, S(0) => \RD.ar_channel_0_n_49\, aclk => aclk, areset_d1 => areset_d1, axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0), \axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2), \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => SI_REG_n_161, \axaddr_offset_r_reg[3]_1\ => SI_REG_n_165, \cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_1\, m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, \m_payload_i_reg[0]\ => \RD.ar_channel_0_n_4\, \m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_5\, \m_payload_i_reg[3]\(3) => SI_REG_n_132, \m_payload_i_reg[3]\(2) => SI_REG_n_133, \m_payload_i_reg[3]\(1) => SI_REG_n_134, \m_payload_i_reg[3]\(0) => SI_REG_n_135, \m_payload_i_reg[47]\ => SI_REG_n_64, \m_payload_i_reg[47]_0\ => SI_REG_n_167, \m_payload_i_reg[5]\ => SI_REG_n_166, \m_payload_i_reg[6]\(6) => SI_REG_n_176, \m_payload_i_reg[6]\(5) => SI_REG_n_177, \m_payload_i_reg[6]\(4) => SI_REG_n_178, \m_payload_i_reg[6]\(3) => SI_REG_n_179, \m_payload_i_reg[6]\(2) => SI_REG_n_180, \m_payload_i_reg[6]\(1) => SI_REG_n_181, \m_payload_i_reg[6]\(0) => SI_REG_n_182, \m_payload_i_reg[7]\(3) => SI_REG_n_136, \m_payload_i_reg[7]\(2) => SI_REG_n_137, \m_payload_i_reg[7]\(1) => SI_REG_n_138, \m_payload_i_reg[7]\(0) => SI_REG_n_139, m_valid_i0 => \ar.ar_pipe/m_valid_i0\, \r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0), r_push_r_reg => \RD.ar_channel_0_n_3\, r_rlast => r_rlast, s_axi_arvalid => s_axi_arvalid, s_ready_i0 => \ar.ar_pipe/s_ready_i0\, s_ready_i_reg => \^s_axi_arready\, si_rs_arvalid => si_rs_arvalid, \state_reg[0]_rep\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0), \wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_0\, \wrap_cnt_r_reg[3]\ => \RD.ar_channel_0_n_10\, \wrap_cnt_r_reg[3]_0\ => \RD.ar_channel_0_n_11\, \wrap_cnt_r_reg[3]_1\ => \RD.ar_channel_0_n_16\, \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0), \wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_156, \wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_157 ); \RD.r_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_r_channel port map ( D(11 downto 0) => s_arid_r(11 downto 0), aclk => aclk, areset_d1 => areset_d1, \in\(33 downto 0) => \in\(33 downto 0), m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, m_valid_i_reg => \RD.r_channel_0_n_0\, \out\(33 downto 32) => si_rs_rresp(1 downto 0), \out\(31 downto 0) => si_rs_rdata(31 downto 0), r_rlast => r_rlast, s_ready_i_reg => SI_REG_n_168, si_rs_rready => si_rs_rready, \skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0), \skid_buffer_reg[46]\(0) => si_rs_rlast, \state_reg[1]_rep\ => \RD.r_channel_0_n_1\, \state_reg[1]_rep_0\ => \RD.ar_channel_0_n_3\ ); SI_REG: entity work.design_1_auto_pc_0_axi_register_slice_v2_1_17_axi_register_slice port map ( D(1 downto 0) => wrap_cnt(3 downto 2), E(0) => \aw.aw_pipe/p_1_in\, O(3) => SI_REG_n_140, O(2) => SI_REG_n_141, O(1) => SI_REG_n_142, O(0) => SI_REG_n_143, Q(54 downto 43) => s_awid(11 downto 0), Q(42 downto 39) => si_rs_awlen(3 downto 0), Q(38) => si_rs_awburst(1), Q(37) => SI_REG_n_26, Q(36 downto 35) => si_rs_awsize(1 downto 0), Q(34 downto 12) => Q(22 downto 0), Q(11 downto 0) => si_rs_awaddr(11 downto 0), S(3) => \WR.aw_channel_0_n_47\, S(2) => \WR.aw_channel_0_n_48\, S(1) => \WR.aw_channel_0_n_49\, S(0) => \WR.aw_channel_0_n_50\, aclk => aclk, aresetn => aresetn, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), \axaddr_incr_reg[3]\(3) => SI_REG_n_132, \axaddr_incr_reg[3]\(2) => SI_REG_n_133, \axaddr_incr_reg[3]\(1) => SI_REG_n_134, \axaddr_incr_reg[3]\(0) => SI_REG_n_135, \axaddr_incr_reg[7]\(3) => SI_REG_n_136, \axaddr_incr_reg[7]\(2) => SI_REG_n_137, \axaddr_incr_reg[7]\(1) => SI_REG_n_138, \axaddr_incr_reg[7]\(0) => SI_REG_n_139, axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0), axaddr_offset_0(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3), axaddr_offset_0(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(1 downto 0), \axaddr_offset_r_reg[2]\ => SI_REG_n_154, \axaddr_offset_r_reg[2]_0\ => SI_REG_n_166, \axaddr_offset_r_reg[2]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2), \axaddr_offset_r_reg[2]_2\ => \WR.aw_channel_0_n_15\, \axaddr_offset_r_reg[2]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2), \axaddr_offset_r_reg[2]_4\ => \RD.ar_channel_0_n_16\, \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => \WR.aw_channel_0_n_10\, \axaddr_offset_r_reg[3]_1\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3), \axaddr_offset_r_reg[3]_1\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(1 downto 0), \axaddr_offset_r_reg[3]_2\ => \RD.ar_channel_0_n_11\, \axlen_cnt_reg[3]\ => SI_REG_n_8, \axlen_cnt_reg[3]_0\ => SI_REG_n_64, b_push => b_push, \cnt_read_reg[2]_rep__0\ => SI_REG_n_168, \cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0), \cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0), \cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_0\, \m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_46\, \m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_47\, \m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_48\, \m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_49\, m_valid_i0 => \ar.ar_pipe/m_valid_i0\, m_valid_i_reg(0) => \ar.ar_pipe/p_1_in\, next_pending_r_reg => SI_REG_n_155, next_pending_r_reg_0 => SI_REG_n_167, \out\(11 downto 0) => si_rs_bid(11 downto 0), r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0), r_push_r_reg(0) => si_rs_rlast, \s_arid_r_reg[11]\(54 downto 43) => s_arid(11 downto 0), \s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0), \s_arid_r_reg[11]\(38) => si_rs_arburst(1), \s_arid_r_reg[11]\(37) => SI_REG_n_82, \s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0), \s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0), \s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0), s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => \^s_axi_arready\, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, \s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, \s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0), s_ready_i0 => \ar.ar_pipe/s_ready_i0\, si_rs_arvalid => si_rs_arvalid, si_rs_awvalid => si_rs_awvalid, si_rs_bready => si_rs_bready, si_rs_bvalid => si_rs_bvalid, si_rs_rready => si_rs_rready, \state_reg[0]_rep\ => \WR.aw_channel_0_n_4\, \state_reg[0]_rep_0\ => \RD.ar_channel_0_n_5\, \state_reg[1]\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0), \state_reg[1]_0\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0), \state_reg[1]_rep\ => \WR.aw_channel_0_n_0\, \state_reg[1]_rep_0\ => \WR.aw_channel_0_n_3\, \state_reg[1]_rep_1\ => \RD.ar_channel_0_n_0\, \state_reg[1]_rep_2\ => \RD.ar_channel_0_n_4\, \wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_169, \wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_170, \wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_171, \wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_172, \wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_173, \wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_174, \wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_175, \wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_176, \wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_177, \wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_178, \wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_179, \wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_180, \wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_181, \wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_182, \wrap_cnt_r_reg[2]\ => SI_REG_n_149, \wrap_cnt_r_reg[2]_0\ => SI_REG_n_161, \wrap_cnt_r_reg[3]\ => SI_REG_n_153, \wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_156, \wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_157, \wrap_cnt_r_reg[3]_1\ => SI_REG_n_165, \wrap_second_len_r_reg[1]\ => \WR.aw_channel_0_n_9\, \wrap_second_len_r_reg[1]_0\ => \RD.ar_channel_0_n_10\, \wrap_second_len_r_reg[3]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1), \wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 1), \wrap_second_len_r_reg[3]_1\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0), \wrap_second_len_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 0) ); \WR.aw_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_aw_channel port map ( D(1 downto 0) => wrap_cnt(3 downto 2), E(0) => \aw.aw_pipe/p_1_in\, Q(31 downto 20) => s_awid(11 downto 0), Q(19 downto 16) => si_rs_awlen(3 downto 0), Q(15) => si_rs_awburst(1), Q(14) => SI_REG_n_26, Q(13 downto 12) => si_rs_awsize(1 downto 0), Q(11 downto 0) => si_rs_awaddr(11 downto 0), S(3) => \WR.aw_channel_0_n_47\, S(2) => \WR.aw_channel_0_n_48\, S(1) => \WR.aw_channel_0_n_49\, S(0) => \WR.aw_channel_0_n_50\, aclk => aclk, areset_d1 => areset_d1, axaddr_incr(11 downto 0) => axaddr_incr(11 downto 0), axaddr_offset(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3), axaddr_offset(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(1 downto 0), \axaddr_offset_r_reg[2]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2), \axaddr_offset_r_reg[3]\(2) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3), \axaddr_offset_r_reg[3]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(1 downto 0), \axaddr_offset_r_reg[3]_0\ => SI_REG_n_149, \axaddr_offset_r_reg[3]_1\ => SI_REG_n_153, \axlen_cnt_reg[7]\ => \WR.aw_channel_0_n_3\, \axlen_cnt_reg[7]_0\ => \WR.aw_channel_0_n_4\, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\, \cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\, \in\(15 downto 4) => b_awid(11 downto 0), \in\(3 downto 0) => b_awlen(3 downto 0), m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, \m_payload_i_reg[47]\ => SI_REG_n_8, \m_payload_i_reg[47]_0\ => SI_REG_n_155, \m_payload_i_reg[5]\ => SI_REG_n_154, \m_payload_i_reg[6]\(6) => SI_REG_n_169, \m_payload_i_reg[6]\(5) => SI_REG_n_170, \m_payload_i_reg[6]\(4) => SI_REG_n_171, \m_payload_i_reg[6]\(3) => SI_REG_n_172, \m_payload_i_reg[6]\(2) => SI_REG_n_173, \m_payload_i_reg[6]\(1) => SI_REG_n_174, \m_payload_i_reg[6]\(0) => SI_REG_n_175, si_rs_awvalid => si_rs_awvalid, \state_reg[0]_rep\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0), \wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_0\, \wrap_cnt_r_reg[3]\ => \WR.aw_channel_0_n_9\, \wrap_cnt_r_reg[3]_0\ => \WR.aw_channel_0_n_10\, \wrap_cnt_r_reg[3]_1\ => \WR.aw_channel_0_n_15\, \wrap_second_len_r_reg[3]\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 0), \wrap_second_len_r_reg[3]_0\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 1) ); \WR.b_channel_0\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s_b_channel port map ( aclk => aclk, areset_d1 => areset_d1, b_push => b_push, \cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\, \cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\, \in\(15 downto 4) => b_awid(11 downto 0), \in\(3 downto 0) => b_awlen(3 downto 0), m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_bvalid => m_axi_bvalid, \out\(11 downto 0) => si_rs_bid(11 downto 0), si_rs_bready => si_rs_bready, si_rs_bvalid => si_rs_bvalid, \skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0) ); areset_d1_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aresetn, O => areset_d1_i_1_n_0 ); areset_d1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => aclk, CE => '1', D => areset_d1_i_1_n_0, Q => areset_d1, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wlast : out STD_LOGIC; m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 ); m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rlast : in STD_LOGIC; m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_FAMILY : string; attribute C_FAMILY of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute P_AXI4 : integer; attribute P_AXI4 of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 0; attribute P_AXILITE : integer; attribute P_AXILITE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 2; attribute P_DECERR : string; attribute P_DECERR of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b11"; attribute P_INCR : string; attribute P_INCR of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is 1; attribute P_SLVERR : string; attribute P_SLVERR of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter : entity is "2'b10"; end design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter; architecture STRUCTURE of design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal \^m_axi_wready\ : STD_LOGIC; signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_wvalid\ : STD_LOGIC; begin \^m_axi_wready\ <= m_axi_wready; \^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0); \^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0); \^s_axi_wvalid\ <= s_axi_wvalid; m_axi_arburst(1) <= \<const0>\; m_axi_arburst(0) <= \<const1>\; m_axi_arcache(3) <= \<const0>\; m_axi_arcache(2) <= \<const0>\; m_axi_arcache(1) <= \<const0>\; m_axi_arcache(0) <= \<const0>\; m_axi_arid(11) <= \<const0>\; m_axi_arid(10) <= \<const0>\; m_axi_arid(9) <= \<const0>\; m_axi_arid(8) <= \<const0>\; m_axi_arid(7) <= \<const0>\; m_axi_arid(6) <= \<const0>\; m_axi_arid(5) <= \<const0>\; m_axi_arid(4) <= \<const0>\; m_axi_arid(3) <= \<const0>\; m_axi_arid(2) <= \<const0>\; m_axi_arid(1) <= \<const0>\; m_axi_arid(0) <= \<const0>\; m_axi_arlen(7) <= \<const0>\; m_axi_arlen(6) <= \<const0>\; m_axi_arlen(5) <= \<const0>\; m_axi_arlen(4) <= \<const0>\; m_axi_arlen(3) <= \<const0>\; m_axi_arlen(2) <= \<const0>\; m_axi_arlen(1) <= \<const0>\; m_axi_arlen(0) <= \<const0>\; m_axi_arlock(0) <= \<const0>\; m_axi_arqos(3) <= \<const0>\; m_axi_arqos(2) <= \<const0>\; m_axi_arqos(1) <= \<const0>\; m_axi_arqos(0) <= \<const0>\; m_axi_arregion(3) <= \<const0>\; m_axi_arregion(2) <= \<const0>\; m_axi_arregion(1) <= \<const0>\; m_axi_arregion(0) <= \<const0>\; m_axi_arsize(2) <= \<const0>\; m_axi_arsize(1) <= \<const1>\; m_axi_arsize(0) <= \<const0>\; m_axi_aruser(0) <= \<const0>\; m_axi_awburst(1) <= \<const0>\; m_axi_awburst(0) <= \<const1>\; m_axi_awcache(3) <= \<const0>\; m_axi_awcache(2) <= \<const0>\; m_axi_awcache(1) <= \<const0>\; m_axi_awcache(0) <= \<const0>\; m_axi_awid(11) <= \<const0>\; m_axi_awid(10) <= \<const0>\; m_axi_awid(9) <= \<const0>\; m_axi_awid(8) <= \<const0>\; m_axi_awid(7) <= \<const0>\; m_axi_awid(6) <= \<const0>\; m_axi_awid(5) <= \<const0>\; m_axi_awid(4) <= \<const0>\; m_axi_awid(3) <= \<const0>\; m_axi_awid(2) <= \<const0>\; m_axi_awid(1) <= \<const0>\; m_axi_awid(0) <= \<const0>\; m_axi_awlen(7) <= \<const0>\; m_axi_awlen(6) <= \<const0>\; m_axi_awlen(5) <= \<const0>\; m_axi_awlen(4) <= \<const0>\; m_axi_awlen(3) <= \<const0>\; m_axi_awlen(2) <= \<const0>\; m_axi_awlen(1) <= \<const0>\; m_axi_awlen(0) <= \<const0>\; m_axi_awlock(0) <= \<const0>\; m_axi_awqos(3) <= \<const0>\; m_axi_awqos(2) <= \<const0>\; m_axi_awqos(1) <= \<const0>\; m_axi_awqos(0) <= \<const0>\; m_axi_awregion(3) <= \<const0>\; m_axi_awregion(2) <= \<const0>\; m_axi_awregion(1) <= \<const0>\; m_axi_awregion(0) <= \<const0>\; m_axi_awsize(2) <= \<const0>\; m_axi_awsize(1) <= \<const1>\; m_axi_awsize(0) <= \<const0>\; m_axi_awuser(0) <= \<const0>\; m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0); m_axi_wid(11) <= \<const0>\; m_axi_wid(10) <= \<const0>\; m_axi_wid(9) <= \<const0>\; m_axi_wid(8) <= \<const0>\; m_axi_wid(7) <= \<const0>\; m_axi_wid(6) <= \<const0>\; m_axi_wid(5) <= \<const0>\; m_axi_wid(4) <= \<const0>\; m_axi_wid(3) <= \<const0>\; m_axi_wid(2) <= \<const0>\; m_axi_wid(1) <= \<const0>\; m_axi_wid(0) <= \<const0>\; m_axi_wlast <= \<const1>\; m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0); m_axi_wuser(0) <= \<const0>\; m_axi_wvalid <= \^s_axi_wvalid\; s_axi_buser(0) <= \<const0>\; s_axi_ruser(0) <= \<const0>\; s_axi_wready <= \^m_axi_wready\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_b2s port map ( Q(22 downto 20) => m_axi_awprot(2 downto 0), Q(19 downto 0) => m_axi_awaddr(31 downto 12), aclk => aclk, aresetn => aresetn, \in\(33 downto 32) => m_axi_rresp(1 downto 0), \in\(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0), \m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0), \m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12), m_axi_arready => m_axi_arready, m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0), m_axi_awready => m_axi_awready, m_axi_awvalid => m_axi_awvalid, m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_bvalid => m_axi_bvalid, m_axi_rready => m_axi_rready, m_axi_rvalid => m_axi_rvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0), s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0), s_axi_awvalid => s_axi_awvalid, \s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0), \s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, \s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0), \s_axi_rid[11]\(34) => s_axi_rlast, \s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0), \s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity design_1_auto_pc_0 is port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_awvalid : out STD_LOGIC; m_axi_awready : in STD_LOGIC; m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 ); m_axi_wvalid : out STD_LOGIC; m_axi_wready : in STD_LOGIC; m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_bvalid : in STD_LOGIC; m_axi_bready : out STD_LOGIC; m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 ); m_axi_arvalid : out STD_LOGIC; m_axi_arready : in STD_LOGIC; m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 ); m_axi_rvalid : in STD_LOGIC; m_axi_rready : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of design_1_auto_pc_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of design_1_auto_pc_0 : entity is "design_1_auto_pc_0,axi_protocol_converter_v2_1_17_axi_protocol_converter,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of design_1_auto_pc_0 : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of design_1_auto_pc_0 : entity is "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2"; end design_1_auto_pc_0; architecture STRUCTURE of design_1_auto_pc_0 is signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC; signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_AXI_ADDR_WIDTH : integer; attribute C_AXI_ADDR_WIDTH of inst : label is 32; attribute C_AXI_ARUSER_WIDTH : integer; attribute C_AXI_ARUSER_WIDTH of inst : label is 1; attribute C_AXI_AWUSER_WIDTH : integer; attribute C_AXI_AWUSER_WIDTH of inst : label is 1; attribute C_AXI_BUSER_WIDTH : integer; attribute C_AXI_BUSER_WIDTH of inst : label is 1; attribute C_AXI_DATA_WIDTH : integer; attribute C_AXI_DATA_WIDTH of inst : label is 32; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of inst : label is 12; attribute C_AXI_RUSER_WIDTH : integer; attribute C_AXI_RUSER_WIDTH of inst : label is 1; attribute C_AXI_SUPPORTS_READ : integer; attribute C_AXI_SUPPORTS_READ of inst : label is 1; attribute C_AXI_SUPPORTS_USER_SIGNALS : integer; attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0; attribute C_AXI_SUPPORTS_WRITE : integer; attribute C_AXI_SUPPORTS_WRITE of inst : label is 1; attribute C_AXI_WUSER_WIDTH : integer; attribute C_AXI_WUSER_WIDTH of inst : label is 1; attribute C_FAMILY : string; attribute C_FAMILY of inst : label is "zynq"; attribute C_IGNORE_ID : integer; attribute C_IGNORE_ID of inst : label is 0; attribute C_M_AXI_PROTOCOL : integer; attribute C_M_AXI_PROTOCOL of inst : label is 2; attribute C_S_AXI_PROTOCOL : integer; attribute C_S_AXI_PROTOCOL of inst : label is 1; attribute C_TRANSLATION_MODE : integer; attribute C_TRANSLATION_MODE of inst : label is 2; attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; attribute P_AXI3 : integer; attribute P_AXI3 of inst : label is 1; attribute P_AXI4 : integer; attribute P_AXI4 of inst : label is 0; attribute P_AXILITE : integer; attribute P_AXILITE of inst : label is 2; attribute P_AXILITE_SIZE : string; attribute P_AXILITE_SIZE of inst : label is "3'b010"; attribute P_CONVERSION : integer; attribute P_CONVERSION of inst : label is 2; attribute P_DECERR : string; attribute P_DECERR of inst : label is "2'b11"; attribute P_INCR : string; attribute P_INCR of inst : label is "2'b01"; attribute P_PROTECTION : integer; attribute P_PROTECTION of inst : label is 1; attribute P_SLVERR : string; attribute P_SLVERR of inst : label is "2'b10"; attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of aclk : signal is "xilinx.com:signal:clock:1.0 CLK CLK"; attribute X_INTERFACE_PARAMETER : string; attribute X_INTERFACE_PARAMETER of aclk : signal is "XIL_INTERFACENAME CLK, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN"; attribute X_INTERFACE_INFO of aresetn : signal is "xilinx.com:signal:reset:1.0 RST RST"; attribute X_INTERFACE_PARAMETER of aresetn : signal is "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; attribute X_INTERFACE_INFO of m_axi_arready : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARREADY"; attribute X_INTERFACE_INFO of m_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARVALID"; attribute X_INTERFACE_INFO of m_axi_awready : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWREADY"; attribute X_INTERFACE_INFO of m_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWVALID"; attribute X_INTERFACE_INFO of m_axi_bready : signal is "xilinx.com:interface:aximm:1.0 M_AXI BREADY"; attribute X_INTERFACE_INFO of m_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI BVALID"; attribute X_INTERFACE_INFO of m_axi_rready : signal is "xilinx.com:interface:aximm:1.0 M_AXI RREADY"; attribute X_INTERFACE_PARAMETER of m_axi_rready : signal is "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of m_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI RVALID"; attribute X_INTERFACE_INFO of m_axi_wready : signal is "xilinx.com:interface:aximm:1.0 M_AXI WREADY"; attribute X_INTERFACE_INFO of m_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 M_AXI WVALID"; attribute X_INTERFACE_INFO of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; attribute X_INTERFACE_INFO of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; attribute X_INTERFACE_INFO of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; attribute X_INTERFACE_INFO of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; attribute X_INTERFACE_INFO of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; attribute X_INTERFACE_INFO of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; attribute X_INTERFACE_INFO of s_axi_rlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI RLAST"; attribute X_INTERFACE_INFO of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; attribute X_INTERFACE_PARAMETER of s_axi_rready : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; attribute X_INTERFACE_INFO of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; attribute X_INTERFACE_INFO of s_axi_wlast : signal is "xilinx.com:interface:aximm:1.0 S_AXI WLAST"; attribute X_INTERFACE_INFO of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; attribute X_INTERFACE_INFO of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; attribute X_INTERFACE_INFO of m_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARADDR"; attribute X_INTERFACE_INFO of m_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI ARPROT"; attribute X_INTERFACE_INFO of m_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWADDR"; attribute X_INTERFACE_INFO of m_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 M_AXI AWPROT"; attribute X_INTERFACE_INFO of m_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI BRESP"; attribute X_INTERFACE_INFO of m_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI RDATA"; attribute X_INTERFACE_INFO of m_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 M_AXI RRESP"; attribute X_INTERFACE_INFO of m_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 M_AXI WDATA"; attribute X_INTERFACE_INFO of m_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 M_AXI WSTRB"; attribute X_INTERFACE_INFO of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; attribute X_INTERFACE_INFO of s_axi_arburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARBURST"; attribute X_INTERFACE_INFO of s_axi_arcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"; attribute X_INTERFACE_INFO of s_axi_arid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARID"; attribute X_INTERFACE_INFO of s_axi_arlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLEN"; attribute X_INTERFACE_INFO of s_axi_arlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"; attribute X_INTERFACE_INFO of s_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARPROT"; attribute X_INTERFACE_INFO of s_axi_arqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARQOS"; attribute X_INTERFACE_INFO of s_axi_arsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"; attribute X_INTERFACE_INFO of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; attribute X_INTERFACE_INFO of s_axi_awburst : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWBURST"; attribute X_INTERFACE_INFO of s_axi_awcache : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"; attribute X_INTERFACE_INFO of s_axi_awid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWID"; attribute X_INTERFACE_INFO of s_axi_awlen : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLEN"; attribute X_INTERFACE_INFO of s_axi_awlock : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"; attribute X_INTERFACE_INFO of s_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWPROT"; attribute X_INTERFACE_INFO of s_axi_awqos : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWQOS"; attribute X_INTERFACE_INFO of s_axi_awsize : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"; attribute X_INTERFACE_INFO of s_axi_bid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BID"; attribute X_INTERFACE_INFO of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; attribute X_INTERFACE_INFO of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; attribute X_INTERFACE_INFO of s_axi_rid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RID"; attribute X_INTERFACE_INFO of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; attribute X_INTERFACE_INFO of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; attribute X_INTERFACE_INFO of s_axi_wid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WID"; attribute X_INTERFACE_INFO of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; begin inst: entity work.design_1_auto_pc_0_axi_protocol_converter_v2_1_17_axi_protocol_converter port map ( aclk => aclk, aresetn => aresetn, m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0), m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0), m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0), m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0), m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0), m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0), m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0), m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0), m_axi_arready => m_axi_arready, m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0), m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0), m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0), m_axi_arvalid => m_axi_arvalid, m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0), m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0), m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0), m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0), m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0), m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0), m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0), m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0), m_axi_awready => m_axi_awready, m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0), m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0), m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0), m_axi_awvalid => m_axi_awvalid, m_axi_bid(11 downto 0) => B"000000000000", m_axi_bready => m_axi_bready, m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0), m_axi_buser(0) => '0', m_axi_bvalid => m_axi_bvalid, m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0), m_axi_rid(11 downto 0) => B"000000000000", m_axi_rlast => '1', m_axi_rready => m_axi_rready, m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0), m_axi_ruser(0) => '0', m_axi_rvalid => m_axi_rvalid, m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0), m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0), m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED, m_axi_wready => m_axi_wready, m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0), m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0), m_axi_wvalid => m_axi_wvalid, s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0), s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0), s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0), s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0), s_axi_arready => s_axi_arready, s_axi_arregion(3 downto 0) => B"0000", s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0), s_axi_aruser(0) => '0', s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0), s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0), s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0), s_axi_awready => s_axi_awready, s_axi_awregion(3 downto 0) => B"0000", s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0), s_axi_awuser(0) => '0', s_axi_awvalid => s_axi_awvalid, s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0), s_axi_bready => s_axi_bready, s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0), s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0), s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wuser(0) => '0', s_axi_wvalid => s_axi_wvalid ); end STRUCTURE;
-- -- This file is part of top_mandelbrot_1b -- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr ) -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/> -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity top_mandel is Port ( clk : in STD_LOGIC; w1a : inout STD_LOGIC_VECTOR (15 downto 0); w1b : inout STD_LOGIC_VECTOR (15 downto 0); w2c : inout STD_LOGIC_VECTOR (15 downto 0); rx : in STD_LOGIC; tx : inout STD_LOGIC ); end top_mandel; architecture Behavioral of top_mandel is COMPONENT clock_25mhz PORT( CLKIN_IN : IN std_logic; CLKFX_OUT : OUT std_logic; CLKIN_IBUFG_OUT : OUT std_logic; CLK0_OUT : OUT std_logic ); END COMPONENT; signal clk_25mhz : std_logic; signal reset : std_logic; signal vsync : std_logic; signal hsync : std_logic; signal enable : std_logic; signal screen_right_left : std_logic; signal screen_up_down : std_logic; signal r : std_logic_vector ( 5 downto 0); signal g : std_logic_vector ( 5 downto 0); signal b : std_logic_vector ( 5 downto 0); signal audio_right : std_logic; signal audio_left : std_logic; signal x_out : std_logic_vector( 9 downto 0); signal y_out : std_logic_vector( 8 downto 0); signal vsync_ok : std_logic; signal hsync_ok : std_logic; signal enable_ok : std_logic; -- Signals to write in screen memory signal addr : std_logic_vector(18 downto 0) := (others => '0'); signal data_in : std_logic; signal write_enable : std_logic; signal edge : std_logic; signal next_step : std_logic; begin Inst_clock_25mhz: clock_25mhz PORT MAP( CLKIN_IN => clk, CLKFX_OUT => clk_25mhz, CLKIN_IBUFG_OUT => open, CLK0_OUT => open ); Inst_giovanni_card : entity work.giovanni_card PORT MAP( w1a => w1a, w1b => w1b, scr_red => r, scr_green => g, scr_blue => b, scr_clk => clk_25mhz, scr_hsync => hsync_ok, scr_vsync => vsync_ok, scr_enable => enable_ok, scr_right_left => screen_right_left, scr_up_down => screen_up_down, audio_right => audio_right, audio_left => audio_left, audio_stereo_ok => open, audio_plugged => open, io => open ); Inst_driver_sharp : entity work.driver_sharp(behavorial) PORT MAP( clk => clk_25mhz, rst => reset, vsync => vsync, hsync => hsync, enable => enable, x_out => x_out, y_out => y_out ); inst_image_controler : entity work.image_controler PORT MAP( clk => clk_25mhz, rst => reset, r => r, g => g, b => b, x => x_out, y => y_out, hsync_in => hsync, vsync_in => vsync, enable_in => enable, write_enable => write_enable, write_addr => addr, data_in => data_in, hsync_out => hsync_ok, vsync_out => vsync_ok, enable_out => enable_ok ); inst_image_generator : entity work.image_generator port map ( clk => clk_25mhz, rst => reset, write_enable => write_enable, data => data_in, addr => addr, next_step => next_step); inst_falling_edge_detector : entity work.falling_edge_detector port map ( clk => clk_25mhz, rst => reset, input => vsync_ok, edge => edge); inst_clk_divider : entity work.clk_divider port map ( clk => clk_25mhz, rst => reset, input => edge, output => next_step); reset <= '0'; screen_right_left <= '1'; screen_up_down <= '1'; audio_right <= '0'; audio_left <= '0'; end Behavioral;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.ComFlow_pkg.all; -- Top level du driver USB -- 4 output flows max -- 2 input flow max -- TODO -- PASSER LES Identifiants de FLOW en générique du driver: -- ca permettrait de specifier les valeurs des identifiants des trames par GPStudio -- Header trame USB -- TRAME USB 16 bits : permier mot header: FLOW ID/FLAG (8b/8b) -- : second mot header : Packet number (16b) entity gp_com is generic ( IN0_SIZE : INTEGER := 8; IN1_SIZE : INTEGER := 8; IN2_SIZE : INTEGER := 8; IN3_SIZE : INTEGER := 8; OUT0_SIZE : INTEGER := 8; OUT1_SIZE : INTEGER := 8; IN0_NBWORDS : INTEGER := 1280; IN1_NBWORDS : INTEGER := 1280; IN2_NBWORDS : INTEGER := 1280; IN3_NBWORDS : INTEGER := 1280; OUT0_NBWORDS : INTEGER := 2000; OUT1_NBWORDS : INTEGER := 2000; CLK_PROC_FREQ : INTEGER; CLK_HAL_FREQ : INTEGER; DATA_HAL_SIZE : INTEGER; PACKET_HAL_SIZE : INTEGER; MASTER_ADDR_WIDTH : INTEGER ); port ( clk_proc : in std_logic; reset_n : in std_logic; ------ hal connections ------ clk_hal : in std_logic; from_hal_data : in std_logic_vector(DATA_HAL_SIZE-1 downto 0); from_hal_wr : in std_logic; from_hal_full : out std_logic; from_hal_pktend : in std_logic; to_hal_data : out std_logic_vector(DATA_HAL_SIZE-1 downto 0); to_hal_rd : in std_logic; to_hal_empty : out std_logic; to_hal_rdy : out std_logic; to_hal_size_packet : out std_logic_vector(15 downto 0); -------- slave ------- status_enable : in std_logic; flow_in0_enable : in std_logic; flow_in1_enable : in std_logic; flow_in2_enable : in std_logic; flow_in3_enable : in std_logic; ------ in0 flow ------ in0_data : in std_logic_vector(IN0_SIZE-1 downto 0); in0_fv : in std_logic; in0_dv : in std_logic; ------ in1 flow ------ in1_data : in std_logic_vector(IN1_SIZE-1 downto 0); in1_fv : in std_logic; in1_dv : in std_logic; ------ in2 flow ------ in2_data : in std_logic_vector(IN2_SIZE-1 downto 0); in2_fv : in std_logic; in2_dv : in std_logic; ------ in3 flow ------ in3_data : in std_logic_vector(IN3_SIZE-1 downto 0); in3_fv : in std_logic; in3_dv : in std_logic; ------ out0 flow ------ out0_data : out std_logic_vector(OUT0_SIZE-1 downto 0); out0_fv : out std_logic; out0_dv : out std_logic; ------ out1 flow ------ out1_data : out std_logic_vector(OUT1_SIZE-1 downto 0); out1_fv : out std_logic; out1_dv : out std_logic; ---- ===== Masters ===== ------ bus_master ------ master_addr_o : out std_logic_vector(MASTER_ADDR_WIDTH-1 downto 0); master_wr_o : out std_logic; master_rd_o : out std_logic; master_datawr_o : out std_logic_vector(31 downto 0); master_datard_i : in std_logic_vector(31 downto 0) ); end entity; architecture rtl of gp_com is -- flow signals signal flow_out_data_0_s : std_logic_vector(DATA_HAL_SIZE-1 downto 0) := (others => '0'); signal flow_out_empty_0_s : std_logic := '0'; signal flow_out_rd_0_s : std_logic := '0'; signal flow_out_rdy_0_s : std_logic := '0'; signal flow_out_size_0_packet_s : std_logic_vector(15 downto 0) := (others => '0'); signal flow_out_data_1_s : std_logic_vector(DATA_HAL_SIZE-1 downto 0) := (others => '0'); signal flow_out_empty_1_s : std_logic := '0'; signal flow_out_rd_1_s : std_logic := '0'; signal flow_out_rdy_1_s : std_logic := '0'; signal flow_out_size_1_packet_s : std_logic_vector(15 downto 0) := (others => '0'); signal flow_out_data_2_s : std_logic_vector(DATA_HAL_SIZE-1 downto 0) := (others => '0'); signal flow_out_empty_2_s : std_logic := '0'; signal flow_out_rd_2_s : std_logic := '0'; signal flow_out_rdy_2_s : std_logic := '0'; signal flow_out_size_2_packet_s : std_logic_vector(15 downto 0) := (others => '0'); signal flow_out_data_3_s : std_logic_vector(DATA_HAL_SIZE-1 downto 0) := (others => '0'); signal flow_out_empty_3_s : std_logic := '0'; signal flow_out_rd_3_s : std_logic := '0'; signal flow_out_rdy_3_s : std_logic := '0'; signal flow_out_size_3_packet_s : std_logic_vector(15 downto 0) := (others => '0'); -- FLOW_PARAMS signal update_port_s : std_logic := '0'; begin --FLOW_OUT out0 FO0_disabled : if OUT0_NBWORDS = 0 generate out0_data <= (others => '0'); out0_fv <= '0'; out0_dv <= '0'; end generate FO0_disabled; FO0_enabled : if OUT0_NBWORDS > 0 generate FLOW_OUT0: component com_to_flow generic map ( FIFO_DEPTH => OUT0_NBWORDS, FLOW_ID => 1, FLAGS_CODES => InitFlagCodes, FLOW_SIZE => OUT0_SIZE, DATA_HAL_SIZE => DATA_HAL_SIZE ) port map ( clk_hal => clk_hal, clk_proc => clk_proc, rst_n => reset_n, data_wr_i => from_hal_wr, data_i => from_hal_data, pktend_i => from_hal_pktend, enable_i => status_enable, data_o => out0_data, fv_o => out0_fv, dv_o => out0_dv, flow_full_o => open ); end generate FO0_enabled; --FLOW_OUT out1 FO1_disabled : if OUT1_NBWORDS = 0 generate out1_data <= (others => '0'); out1_fv <= '0'; out1_dv <= '0'; end generate FO1_disabled; FO1_enabled : if OUT1_NBWORDS > 0 generate FLOW_OUT1: component com_to_flow generic map ( FIFO_DEPTH => OUT1_NBWORDS, FLOW_ID => 2, FLAGS_CODES => InitFlagCodes, FLOW_SIZE => OUT1_SIZE, DATA_HAL_SIZE => DATA_HAL_SIZE ) port map ( clk_hal => clk_hal, clk_proc => clk_proc, rst_n => reset_n, data_wr_i => from_hal_wr, data_i => from_hal_data, pktend_i => from_hal_pktend, enable_i => status_enable, data_o => out1_data, fv_o => out1_fv, dv_o => out1_dv, flow_full_o => open ); end generate FO1_enabled; ------------------------------------------------------------ --FLOW IN in0 --Disable flow if not used FI0_disabled : if IN0_NBWORDS = 0 generate flow_out_rdy_0_s <= '0'; flow_out_empty_0_s <= '0'; flow_out_data_0_s <= (others => '0'); end generate FI0_disabled; FI0_enabled : if IN0_NBWORDS > 0 generate FLOW_IN0: component flow_to_com generic map ( FLOW_SIZE => IN0_SIZE, FIFO_DEPTH => IN0_NBWORDS, FLOW_ID => 128, PACKET_SIZE => PACKET_HAL_SIZE, -- header inclus FLAGS_CODES => InitFlagCodes, DATA_HAL_SIZE => DATA_HAL_SIZE ) port map ( clk_proc => clk_proc, clk_hal => clk_hal, rst_n => reset_n, in_data => in0_data, in_fv => in0_fv, in_dv => in0_dv, enable_flow_i => flow_in0_enable, enable_global_i => status_enable, -- to arbitrer rdreq_i => flow_out_rd_0_s, data_o => flow_out_data_0_s, flow_rdy_o => flow_out_rdy_0_s, f_empty_o => flow_out_empty_0_s, size_packet_o => flow_out_size_0_packet_s ); end generate FI0_enabled; ------------------------------------------------------------ ------------------------------------------------------------ --FLOW IN in1 FI1_disabled : if IN1_NBWORDS = 0 generate flow_out_rdy_1_s <= '0'; flow_out_empty_1_s <= '0'; flow_out_data_1_s <= (others => '0'); end generate FI1_disabled; FI1_enabled : if IN1_NBWORDS > 0 generate FLOW_IN1: component flow_to_com generic map ( FLOW_SIZE => IN1_SIZE, FIFO_DEPTH => IN1_NBWORDS, FLOW_ID => 129, PACKET_SIZE => PACKET_HAL_SIZE, -- header inclus FLAGS_CODES => InitFlagCodes, DATA_HAL_SIZE => DATA_HAL_SIZE ) port map ( clk_proc => clk_proc, clk_hal => clk_hal, rst_n => reset_n, in_data => in1_data, in_fv => in1_fv, in_dv => in1_dv, enable_flow_i => flow_in1_enable, enable_global_i => status_enable, -- to arbitrer rdreq_i => flow_out_rd_1_s, data_o => flow_out_data_1_s, flow_rdy_o => flow_out_rdy_1_s, f_empty_o => flow_out_empty_1_s, size_packet_o => flow_out_size_1_packet_s ); end generate FI1_enabled; ------------------------------------------------------------ ------------------------------------------------------------ --FLOW IN in2 FI2_disabled : if IN2_NBWORDS = 0 generate flow_out_rdy_2_s <= '0'; flow_out_empty_2_s <= '0'; flow_out_data_2_s <= (others => '0'); end generate FI2_disabled; FI2_enabled : if IN2_NBWORDS > 0 generate FLOW_IN2: component flow_to_com generic map ( FLOW_SIZE => IN2_SIZE, FIFO_DEPTH => IN2_NBWORDS, FLOW_ID => 130, PACKET_SIZE => PACKET_HAL_SIZE, -- header inclus FLAGS_CODES => InitFlagCodes, DATA_HAL_SIZE => DATA_HAL_SIZE ) port map ( clk_proc => clk_proc, clk_hal => clk_hal, rst_n => reset_n, in_data => in2_data, in_fv => in2_fv, in_dv => in2_dv, enable_flow_i => flow_in2_enable, enable_global_i => status_enable, -- to arbitrer rdreq_i => flow_out_rd_2_s, data_o => flow_out_data_2_s, flow_rdy_o => flow_out_rdy_2_s, f_empty_o => flow_out_empty_2_s, size_packet_o => flow_out_size_2_packet_s ); end generate FI2_enabled; ------------------------------------------------------------ ------------------------------------------------------------ --FLOW IN in3 FI3_disabled : if IN3_NBWORDS = 0 generate flow_out_rdy_3_s <= '0'; flow_out_empty_3_s <= '0'; flow_out_data_3_s <= (others => '0'); end generate FI3_disabled; FI3_enabled : if IN3_NBWORDS > 0 generate FLOW_IN3: component flow_to_com generic map ( FLOW_SIZE => IN3_SIZE, FIFO_DEPTH => IN3_NBWORDS, FLOW_ID => 131, PACKET_SIZE => PACKET_HAL_SIZE, -- header inclus FLAGS_CODES => InitFlagCodes, DATA_HAL_SIZE => DATA_HAL_SIZE ) port map ( clk_proc => clk_proc, clk_hal => clk_hal, rst_n => reset_n, in_data => in3_data, in_fv => in3_fv, in_dv => in3_dv, enable_flow_i => flow_in3_enable, enable_global_i => status_enable, -- to arbitrer rdreq_i => flow_out_rd_3_s, data_o => flow_out_data_3_s, flow_rdy_o => flow_out_rdy_3_s, f_empty_o => flow_out_empty_3_s, size_packet_o => flow_out_size_3_packet_s ); end generate FI3_enabled; ------------------------------------------------------------ -- component flow_to_com_arb4 FLOW_ARB : component flow_to_com_arb4 generic map ( DATA_HAL_SIZE => DATA_HAL_SIZE ) port map ( clk => clk_hal, rst_n => reset_n, -- fv 0 signals rdreq_0_o => flow_out_rd_0_s, data_0_i => flow_out_data_0_s, flow_rdy_0_i => flow_out_rdy_0_s, f_empty_0_i => flow_out_empty_0_s, size_packet_0_i => flow_out_size_0_packet_s, -- fv 1 signals rdreq_1_o => flow_out_rd_1_s, data_1_i => flow_out_data_1_s, flow_rdy_1_i => flow_out_rdy_1_s, f_empty_1_i => flow_out_empty_1_s, size_packet_1_i => flow_out_size_1_packet_s, -- fv 2 signals rdreq_2_o => flow_out_rd_2_s, data_2_i => flow_out_data_2_s, flow_rdy_2_i => flow_out_rdy_2_s, f_empty_2_i => flow_out_empty_2_s, size_packet_2_i => flow_out_size_2_packet_s, -- fv 3 signals rdreq_3_o => flow_out_rd_3_s, data_3_i => flow_out_data_3_s, flow_rdy_3_i => flow_out_rdy_3_s, f_empty_3_i => flow_out_empty_3_s, size_packet_3_i => flow_out_size_3_packet_s, -- fv usb signals rdreq_usb_i => to_hal_rd, data_usb_o => to_hal_data, flow_rdy_usb_o => to_hal_rdy, f_empty_usb_o => to_hal_empty, size_packet_o => to_hal_size_packet ); -- FLOW_PARAMS module --> Parameter Interconnect Master FLOW_PARAMS : component com_to_master_pi generic map ( FIFO_DEPTH => 64, FLOW_ID_SET => 15, MASTER_ADDR_WIDTH => MASTER_ADDR_WIDTH, DATA_HAL_SIZE => DATA_HAL_SIZE ) port map ( clk_hal => clk_hal, clk_proc => clk_proc, rst_n => reset_n, data_wr_i => from_hal_wr, data_i => from_hal_data, pktend_i => from_hal_pktend, fifo_full_o => from_hal_full, param_addr_o => master_addr_o, param_data_o => master_datawr_o, param_wr_o => master_wr_o -- rajouter fin d'ecriture dans la memoire... --~ tmp_update_port_o => update_port_s ); end rtl;
-- ////////////////////////////////////////////////////////////////////////////// -- /// Copyright (c) 2013, Jahanzeb Ahmad -- /// All rights reserved. -- /// -- // Redistribution and use in source and binary forms, with or without modification, -- /// are permitted provided that the following conditions are met: -- /// -- /// * Redistributions of source code must retain the above copyright notice, -- /// this list of conditions and the following disclaimer. -- /// * Redistributions in binary form must reproduce the above copyright notice, -- /// this list of conditions and the following disclaimer in the documentation and/or -- /// other materials provided with the distribution. -- /// -- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY -- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT -- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- /// POSSIBILITY OF SUCH DAMAGE. -- /// -- /// -- /// * http://opensource.org/licenses/MIT -- /// * http://copyfree.org/licenses/mit/license.txt -- /// -- ////////////////////////////////////////////////////////////////////////////// LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity usb_top is port ( -- EDID structure edid0_byte : in std_logic_vector(7 downto 0); edid0_byte_en : in std_logic; edid1_byte : in std_logic_vector(7 downto 0); edid1_byte_en : in std_logic; -- jpeg encoder jpeg_byte : in std_logic_vector(7 downto 0); jpeg_clk : in std_logic; jpeg_en : in std_logic; jpeg_fifo_full : out std_logic; -- raw input raw_en : in std_logic; raw_bytes : in std_logic_vector(23 downto 0); raw_fifo_full : out std_logic; raw_clk : in std_logic; -- cypress chip signals fdata : inout std_logic_vector(7 downto 0); flag_full : in std_logic; flag_empty : in std_logic; faddr : out std_logic_vector(1 downto 0); slwr : out std_logic; slrd : out std_logic; sloe : out std_logic; pktend : out std_logic; ifclk : in std_logic; -- status inputs resX_H0 : in std_logic_vector(15 downto 0); resY_H0 : in std_logic_vector(15 downto 0); resX_H1 : in std_logic_vector(15 downto 0); resY_H1 : in std_logic_vector(15 downto 0); de_H0 : in std_logic; -- to check activity on hdmi de_H1 : in std_logic; -- to check activity on hdmi status : in std_logic_vector(4 downto 0); usb_cmd : in std_logic_vector(2 downto 0); -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2) jpeg_encoder_cmd : in std_logic_vector(1 downto 0); -- encodingQuality(1 downto 0) selector_cmd : in std_logic_vector(12 downto 0); -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off) hdmi_cmd : in std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi uvc_rst : in std_logic; to_send : in std_logic_vector(23 downto 0); cmd_en : out std_logic; cmd : out std_logic_vector(7 downto 0); --debug debug_byte : in std_logic_vector(7 downto 0); debug_index : out integer range 0 to 15; eof_jpg : out std_logic; -- clk,rst rst : in std_logic; clk : in std_logic ); end entity usb_top; architecture rtl of usb_top is ----------- signals constant cdcout : std_logic_vector(1 downto 0):= "00"; --ep 2 constant cdcin : std_logic_vector(1 downto 0):= "01"; --ep 4 constant uvcin : std_logic_vector(1 downto 0):= "10"; --ep 6 type states is (s_reset,s_cdc_in,s_cdc_out,s_uvc_in,s_cdc_in_w,s_cdc_out_w,s_uvc_in_w); signal ps : states; signal sloe_i : std_logic; signal slrd_cdc : std_logic; signal slwr_cdc : std_logic; signal pktend_cdc : std_logic; signal slwr_jpg_uvc : std_logic; signal slwr_raw_uvc : std_logic; signal pktend_jpg_uvc : std_logic; signal pktend_raw_uvc : std_logic; signal cdc_out_free : std_logic; signal cdc_in_free : std_logic; signal uvc_in_jpg_free : std_logic; signal uvc_in_raw_free : std_logic; signal fdatain : std_logic_vector(7 downto 0); signal fdataout : std_logic_vector(7 downto 0); signal fdataout_cdc : std_logic_vector(7 downto 0); signal fdataout_jpg_uvc : std_logic_vector(7 downto 0); signal fdataout_raw_uvc : std_logic_vector(7 downto 0); signal faddr_i : std_logic_vector(1 downto 0); signal jpg_uvc_error : std_logic; signal raw_uvc_error : std_logic; signal jpg_uvc_enable,raw_uvc_enable,uvc_enable,header : std_logic; -- components signals begin -- architecture -- usb_cmd -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2) sloe <= sloe_i; faddr <= faddr_i; jpg_uvc_enable <= usb_cmd(1) and usb_cmd(2); raw_uvc_enable <= (not usb_cmd(1)) and usb_cmd(2); uvc_enable <= usb_cmd(2); header <= usb_cmd(0); fdatain <= fdata; fdata <= fdataout when sloe_i = '1' else "ZZZZZZZZ"; sloe_i <= '0' when (faddr_i = cdcout) else '1'; syncProc: process(rst,ifclk) -- usb process begin -- process if rst = '1' then faddr_i <= cdcout; slwr <= '1'; slrd <= '1'; pktend <= '1'; ps <= s_reset; fdataout <= (others => '0'); elsif falling_edge(ifclk) then slwr <= '1'; slrd <= '1'; pktend <= '1'; case ps is when s_reset => faddr_i <= cdcout; slwr <= '1'; slrd <= '1'; pktend <= '1'; ps <= s_cdc_out_w; fdataout <= (others => '0'); when s_cdc_out_w => ps <= s_cdc_out; when s_cdc_out => slrd <= slrd_cdc; if cdc_out_free = '1' then faddr_i <= cdcin; ps <= s_cdc_in_w; end if; when s_cdc_in_w => ps <= s_cdc_in; when s_cdc_in => slwr <= slwr_cdc; pktend <= pktend_cdc; fdataout <= fdataout_cdc; if cdc_in_free = '1' then if uvc_enable = '1' then faddr_i <= uvcin; ps <= s_uvc_in_w; else faddr_i <= cdcout; ps <= s_cdc_out_w; end if; end if; when s_uvc_in_w => ps <= s_uvc_in; when s_uvc_in => if usb_cmd(1) = '1' then -- jpeg encoder slwr <= slwr_jpg_uvc; pktend <= pktend_jpg_uvc; fdataout <= fdataout_jpg_uvc; if uvc_in_jpg_free = '1' then faddr_i <= cdcout; ps <= s_cdc_out_w; end if; else -- raw output slwr <= slwr_raw_uvc; pktend <= pktend_raw_uvc; fdataout <= fdataout_raw_uvc; if uvc_in_raw_free = '1' then faddr_i <= cdcout; ps <= s_cdc_out_w; end if; end if; when others => ps <= s_reset; end case; end if; end process; ---------------------- components cdc_out_comp: entity work.cdc_out port map(fdata => fdatain, flag_empty => flag_empty, faddr => faddr_i, cdcout => cdcout, slrd => slrd_cdc, cmd => cmd, cmd_en => cmd_en, cdc_out_free => cdc_out_free, rst => rst, ifclk => ifclk); jpg_uvc_comp: entity work.jpg_uvc port map(jpeg_en => jpeg_en, jpeg_byte => jpeg_byte, jpeg_fifo_full => jpeg_fifo_full, error => jpg_uvc_error, jpeg_clk => jpeg_clk, jpeg_enable => jpg_uvc_enable, slwr => slwr_jpg_uvc, pktend => pktend_jpg_uvc, fdata => fdataout_jpg_uvc, flag_full => flag_full, ifclk => ifclk, faddr => faddr_i, uvcin => uvcin, header => header, eof_jpg => eof_jpg, uvc_in_free => uvc_in_jpg_free, uvc_rst => uvc_rst); raw_uvc_comp: entity work.raw_uvc port map(raw_en => raw_en, raw_bytes => raw_bytes, raw_fifo_full => raw_fifo_full, error => raw_uvc_error, raw_clk => raw_clk, raw_enable => raw_uvc_enable, slwr => slwr_raw_uvc, pktend => pktend_raw_uvc, fdata => fdataout_raw_uvc, flag_full => flag_full, ifclk => ifclk, faddr => faddr_i, uvcin => uvcin, header => header, to_send => to_send, uvc_in_free => uvc_in_raw_free, uvc_rst => uvc_rst); cdc_in_comp: entity work.cdc_in port map(ifclk => ifclk, faddr => faddr_i, cdcin => cdcin, slwr => slwr_cdc, pktend => pktend_cdc, fdata => fdataout_cdc, cdc_in_free => cdc_in_free, edid0_byte => edid0_byte, edid0_byte_en => edid0_byte_en, edid1_byte => edid1_byte, edid1_byte_en => edid1_byte_en, resX0 => resX_H0, resY0 => resY_H0, resX1 => resX_H1, resY1 => resY_H1, jpeg_error => jpg_uvc_error, rgb_de0 => de_H0, rgb_de1 => de_H1, status => status, usb_cmd => usb_cmd, jpeg_encoder_cmd => jpeg_encoder_cmd, selector_cmd => selector_cmd, hdmi_cmd => hdmi_cmd, debug_byte => debug_byte, debug_index => debug_index, rst => rst, clk => clk ); end architecture;
-- ////////////////////////////////////////////////////////////////////////////// -- /// Copyright (c) 2013, Jahanzeb Ahmad -- /// All rights reserved. -- /// -- // Redistribution and use in source and binary forms, with or without modification, -- /// are permitted provided that the following conditions are met: -- /// -- /// * Redistributions of source code must retain the above copyright notice, -- /// this list of conditions and the following disclaimer. -- /// * Redistributions in binary form must reproduce the above copyright notice, -- /// this list of conditions and the following disclaimer in the documentation and/or -- /// other materials provided with the distribution. -- /// -- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY -- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT -- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- /// POSSIBILITY OF SUCH DAMAGE. -- /// -- /// -- /// * http://opensource.org/licenses/MIT -- /// * http://copyfree.org/licenses/mit/license.txt -- /// -- ////////////////////////////////////////////////////////////////////////////// LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity usb_top is port ( -- EDID structure edid0_byte : in std_logic_vector(7 downto 0); edid0_byte_en : in std_logic; edid1_byte : in std_logic_vector(7 downto 0); edid1_byte_en : in std_logic; -- jpeg encoder jpeg_byte : in std_logic_vector(7 downto 0); jpeg_clk : in std_logic; jpeg_en : in std_logic; jpeg_fifo_full : out std_logic; -- raw input raw_en : in std_logic; raw_bytes : in std_logic_vector(23 downto 0); raw_fifo_full : out std_logic; raw_clk : in std_logic; -- cypress chip signals fdata : inout std_logic_vector(7 downto 0); flag_full : in std_logic; flag_empty : in std_logic; faddr : out std_logic_vector(1 downto 0); slwr : out std_logic; slrd : out std_logic; sloe : out std_logic; pktend : out std_logic; ifclk : in std_logic; -- status inputs resX_H0 : in std_logic_vector(15 downto 0); resY_H0 : in std_logic_vector(15 downto 0); resX_H1 : in std_logic_vector(15 downto 0); resY_H1 : in std_logic_vector(15 downto 0); de_H0 : in std_logic; -- to check activity on hdmi de_H1 : in std_logic; -- to check activity on hdmi status : in std_logic_vector(4 downto 0); usb_cmd : in std_logic_vector(2 downto 0); -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2) jpeg_encoder_cmd : in std_logic_vector(1 downto 0); -- encodingQuality(1 downto 0) selector_cmd : in std_logic_vector(12 downto 0); -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off) hdmi_cmd : in std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi uvc_rst : in std_logic; to_send : in std_logic_vector(23 downto 0); cmd_en : out std_logic; cmd : out std_logic_vector(7 downto 0); --debug debug_byte : in std_logic_vector(7 downto 0); debug_index : out integer range 0 to 15; eof_jpg : out std_logic; -- clk,rst rst : in std_logic; clk : in std_logic ); end entity usb_top; architecture rtl of usb_top is ----------- signals constant cdcout : std_logic_vector(1 downto 0):= "00"; --ep 2 constant cdcin : std_logic_vector(1 downto 0):= "01"; --ep 4 constant uvcin : std_logic_vector(1 downto 0):= "10"; --ep 6 type states is (s_reset,s_cdc_in,s_cdc_out,s_uvc_in,s_cdc_in_w,s_cdc_out_w,s_uvc_in_w); signal ps : states; signal sloe_i : std_logic; signal slrd_cdc : std_logic; signal slwr_cdc : std_logic; signal pktend_cdc : std_logic; signal slwr_jpg_uvc : std_logic; signal slwr_raw_uvc : std_logic; signal pktend_jpg_uvc : std_logic; signal pktend_raw_uvc : std_logic; signal cdc_out_free : std_logic; signal cdc_in_free : std_logic; signal uvc_in_jpg_free : std_logic; signal uvc_in_raw_free : std_logic; signal fdatain : std_logic_vector(7 downto 0); signal fdataout : std_logic_vector(7 downto 0); signal fdataout_cdc : std_logic_vector(7 downto 0); signal fdataout_jpg_uvc : std_logic_vector(7 downto 0); signal fdataout_raw_uvc : std_logic_vector(7 downto 0); signal faddr_i : std_logic_vector(1 downto 0); signal jpg_uvc_error : std_logic; signal raw_uvc_error : std_logic; signal jpg_uvc_enable,raw_uvc_enable,uvc_enable,header : std_logic; -- components signals begin -- architecture -- usb_cmd -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2) sloe <= sloe_i; faddr <= faddr_i; jpg_uvc_enable <= usb_cmd(1) and usb_cmd(2); raw_uvc_enable <= (not usb_cmd(1)) and usb_cmd(2); uvc_enable <= usb_cmd(2); header <= usb_cmd(0); fdatain <= fdata; fdata <= fdataout when sloe_i = '1' else "ZZZZZZZZ"; sloe_i <= '0' when (faddr_i = cdcout) else '1'; syncProc: process(rst,ifclk) -- usb process begin -- process if rst = '1' then faddr_i <= cdcout; slwr <= '1'; slrd <= '1'; pktend <= '1'; ps <= s_reset; fdataout <= (others => '0'); elsif falling_edge(ifclk) then slwr <= '1'; slrd <= '1'; pktend <= '1'; case ps is when s_reset => faddr_i <= cdcout; slwr <= '1'; slrd <= '1'; pktend <= '1'; ps <= s_cdc_out_w; fdataout <= (others => '0'); when s_cdc_out_w => ps <= s_cdc_out; when s_cdc_out => slrd <= slrd_cdc; if cdc_out_free = '1' then faddr_i <= cdcin; ps <= s_cdc_in_w; end if; when s_cdc_in_w => ps <= s_cdc_in; when s_cdc_in => slwr <= slwr_cdc; pktend <= pktend_cdc; fdataout <= fdataout_cdc; if cdc_in_free = '1' then if uvc_enable = '1' then faddr_i <= uvcin; ps <= s_uvc_in_w; else faddr_i <= cdcout; ps <= s_cdc_out_w; end if; end if; when s_uvc_in_w => ps <= s_uvc_in; when s_uvc_in => if usb_cmd(1) = '1' then -- jpeg encoder slwr <= slwr_jpg_uvc; pktend <= pktend_jpg_uvc; fdataout <= fdataout_jpg_uvc; if uvc_in_jpg_free = '1' then faddr_i <= cdcout; ps <= s_cdc_out_w; end if; else -- raw output slwr <= slwr_raw_uvc; pktend <= pktend_raw_uvc; fdataout <= fdataout_raw_uvc; if uvc_in_raw_free = '1' then faddr_i <= cdcout; ps <= s_cdc_out_w; end if; end if; when others => ps <= s_reset; end case; end if; end process; ---------------------- components cdc_out_comp: entity work.cdc_out port map(fdata => fdatain, flag_empty => flag_empty, faddr => faddr_i, cdcout => cdcout, slrd => slrd_cdc, cmd => cmd, cmd_en => cmd_en, cdc_out_free => cdc_out_free, rst => rst, ifclk => ifclk); jpg_uvc_comp: entity work.jpg_uvc port map(jpeg_en => jpeg_en, jpeg_byte => jpeg_byte, jpeg_fifo_full => jpeg_fifo_full, error => jpg_uvc_error, jpeg_clk => jpeg_clk, jpeg_enable => jpg_uvc_enable, slwr => slwr_jpg_uvc, pktend => pktend_jpg_uvc, fdata => fdataout_jpg_uvc, flag_full => flag_full, ifclk => ifclk, faddr => faddr_i, uvcin => uvcin, header => header, eof_jpg => eof_jpg, uvc_in_free => uvc_in_jpg_free, uvc_rst => uvc_rst); raw_uvc_comp: entity work.raw_uvc port map(raw_en => raw_en, raw_bytes => raw_bytes, raw_fifo_full => raw_fifo_full, error => raw_uvc_error, raw_clk => raw_clk, raw_enable => raw_uvc_enable, slwr => slwr_raw_uvc, pktend => pktend_raw_uvc, fdata => fdataout_raw_uvc, flag_full => flag_full, ifclk => ifclk, faddr => faddr_i, uvcin => uvcin, header => header, to_send => to_send, uvc_in_free => uvc_in_raw_free, uvc_rst => uvc_rst); cdc_in_comp: entity work.cdc_in port map(ifclk => ifclk, faddr => faddr_i, cdcin => cdcin, slwr => slwr_cdc, pktend => pktend_cdc, fdata => fdataout_cdc, cdc_in_free => cdc_in_free, edid0_byte => edid0_byte, edid0_byte_en => edid0_byte_en, edid1_byte => edid1_byte, edid1_byte_en => edid1_byte_en, resX0 => resX_H0, resY0 => resY_H0, resX1 => resX_H1, resY1 => resY_H1, jpeg_error => jpg_uvc_error, rgb_de0 => de_H0, rgb_de1 => de_H1, status => status, usb_cmd => usb_cmd, jpeg_encoder_cmd => jpeg_encoder_cmd, selector_cmd => selector_cmd, hdmi_cmd => hdmi_cmd, debug_byte => debug_byte, debug_index => debug_index, rst => rst, clk => clk ); end architecture;
-- ////////////////////////////////////////////////////////////////////////////// -- /// Copyright (c) 2013, Jahanzeb Ahmad -- /// All rights reserved. -- /// -- // Redistribution and use in source and binary forms, with or without modification, -- /// are permitted provided that the following conditions are met: -- /// -- /// * Redistributions of source code must retain the above copyright notice, -- /// this list of conditions and the following disclaimer. -- /// * Redistributions in binary form must reproduce the above copyright notice, -- /// this list of conditions and the following disclaimer in the documentation and/or -- /// other materials provided with the distribution. -- /// -- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY -- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT -- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- /// POSSIBILITY OF SUCH DAMAGE. -- /// -- /// -- /// * http://opensource.org/licenses/MIT -- /// * http://copyfree.org/licenses/mit/license.txt -- /// -- ////////////////////////////////////////////////////////////////////////////// LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity usb_top is port ( -- EDID structure edid0_byte : in std_logic_vector(7 downto 0); edid0_byte_en : in std_logic; edid1_byte : in std_logic_vector(7 downto 0); edid1_byte_en : in std_logic; -- jpeg encoder jpeg_byte : in std_logic_vector(7 downto 0); jpeg_clk : in std_logic; jpeg_en : in std_logic; jpeg_fifo_full : out std_logic; -- raw input raw_en : in std_logic; raw_bytes : in std_logic_vector(23 downto 0); raw_fifo_full : out std_logic; raw_clk : in std_logic; -- cypress chip signals fdata : inout std_logic_vector(7 downto 0); flag_full : in std_logic; flag_empty : in std_logic; faddr : out std_logic_vector(1 downto 0); slwr : out std_logic; slrd : out std_logic; sloe : out std_logic; pktend : out std_logic; ifclk : in std_logic; -- status inputs resX_H0 : in std_logic_vector(15 downto 0); resY_H0 : in std_logic_vector(15 downto 0); resX_H1 : in std_logic_vector(15 downto 0); resY_H1 : in std_logic_vector(15 downto 0); de_H0 : in std_logic; -- to check activity on hdmi de_H1 : in std_logic; -- to check activity on hdmi status : in std_logic_vector(4 downto 0); usb_cmd : in std_logic_vector(2 downto 0); -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2) jpeg_encoder_cmd : in std_logic_vector(1 downto 0); -- encodingQuality(1 downto 0) selector_cmd : in std_logic_vector(12 downto 0); -- (1:0 source ) (2 gray/color) (3 inverted/not-inverted) (4:5 blue depth) (6:7 green depth) (8:9 red depth) (10 blue on/off) (11 green on/off) (12 red on/off) hdmi_cmd : in std_logic_vector(1 downto 0); -- if 1 then dvi else hdmi uvc_rst : in std_logic; to_send : in std_logic_vector(23 downto 0); cmd_en : out std_logic; cmd : out std_logic_vector(7 downto 0); --debug debug_byte : in std_logic_vector(7 downto 0); debug_index : out integer range 0 to 15; eof_jpg : out std_logic; -- clk,rst rst : in std_logic; clk : in std_logic ); end entity usb_top; architecture rtl of usb_top is ----------- signals constant cdcout : std_logic_vector(1 downto 0):= "00"; --ep 2 constant cdcin : std_logic_vector(1 downto 0):= "01"; --ep 4 constant uvcin : std_logic_vector(1 downto 0):= "10"; --ep 6 type states is (s_reset,s_cdc_in,s_cdc_out,s_uvc_in,s_cdc_in_w,s_cdc_out_w,s_uvc_in_w); signal ps : states; signal sloe_i : std_logic; signal slrd_cdc : std_logic; signal slwr_cdc : std_logic; signal pktend_cdc : std_logic; signal slwr_jpg_uvc : std_logic; signal slwr_raw_uvc : std_logic; signal pktend_jpg_uvc : std_logic; signal pktend_raw_uvc : std_logic; signal cdc_out_free : std_logic; signal cdc_in_free : std_logic; signal uvc_in_jpg_free : std_logic; signal uvc_in_raw_free : std_logic; signal fdatain : std_logic_vector(7 downto 0); signal fdataout : std_logic_vector(7 downto 0); signal fdataout_cdc : std_logic_vector(7 downto 0); signal fdataout_jpg_uvc : std_logic_vector(7 downto 0); signal fdataout_raw_uvc : std_logic_vector(7 downto 0); signal faddr_i : std_logic_vector(1 downto 0); signal jpg_uvc_error : std_logic; signal raw_uvc_error : std_logic; signal jpg_uvc_enable,raw_uvc_enable,uvc_enable,header : std_logic; -- components signals begin -- architecture -- usb_cmd -- UVCpayloadheader(0), raw/jpeg(1), uvc on/off(2) sloe <= sloe_i; faddr <= faddr_i; jpg_uvc_enable <= usb_cmd(1) and usb_cmd(2); raw_uvc_enable <= (not usb_cmd(1)) and usb_cmd(2); uvc_enable <= usb_cmd(2); header <= usb_cmd(0); fdatain <= fdata; fdata <= fdataout when sloe_i = '1' else "ZZZZZZZZ"; sloe_i <= '0' when (faddr_i = cdcout) else '1'; syncProc: process(rst,ifclk) -- usb process begin -- process if rst = '1' then faddr_i <= cdcout; slwr <= '1'; slrd <= '1'; pktend <= '1'; ps <= s_reset; fdataout <= (others => '0'); elsif falling_edge(ifclk) then slwr <= '1'; slrd <= '1'; pktend <= '1'; case ps is when s_reset => faddr_i <= cdcout; slwr <= '1'; slrd <= '1'; pktend <= '1'; ps <= s_cdc_out_w; fdataout <= (others => '0'); when s_cdc_out_w => ps <= s_cdc_out; when s_cdc_out => slrd <= slrd_cdc; if cdc_out_free = '1' then faddr_i <= cdcin; ps <= s_cdc_in_w; end if; when s_cdc_in_w => ps <= s_cdc_in; when s_cdc_in => slwr <= slwr_cdc; pktend <= pktend_cdc; fdataout <= fdataout_cdc; if cdc_in_free = '1' then if uvc_enable = '1' then faddr_i <= uvcin; ps <= s_uvc_in_w; else faddr_i <= cdcout; ps <= s_cdc_out_w; end if; end if; when s_uvc_in_w => ps <= s_uvc_in; when s_uvc_in => if usb_cmd(1) = '1' then -- jpeg encoder slwr <= slwr_jpg_uvc; pktend <= pktend_jpg_uvc; fdataout <= fdataout_jpg_uvc; if uvc_in_jpg_free = '1' then faddr_i <= cdcout; ps <= s_cdc_out_w; end if; else -- raw output slwr <= slwr_raw_uvc; pktend <= pktend_raw_uvc; fdataout <= fdataout_raw_uvc; if uvc_in_raw_free = '1' then faddr_i <= cdcout; ps <= s_cdc_out_w; end if; end if; when others => ps <= s_reset; end case; end if; end process; ---------------------- components cdc_out_comp: entity work.cdc_out port map(fdata => fdatain, flag_empty => flag_empty, faddr => faddr_i, cdcout => cdcout, slrd => slrd_cdc, cmd => cmd, cmd_en => cmd_en, cdc_out_free => cdc_out_free, rst => rst, ifclk => ifclk); jpg_uvc_comp: entity work.jpg_uvc port map(jpeg_en => jpeg_en, jpeg_byte => jpeg_byte, jpeg_fifo_full => jpeg_fifo_full, error => jpg_uvc_error, jpeg_clk => jpeg_clk, jpeg_enable => jpg_uvc_enable, slwr => slwr_jpg_uvc, pktend => pktend_jpg_uvc, fdata => fdataout_jpg_uvc, flag_full => flag_full, ifclk => ifclk, faddr => faddr_i, uvcin => uvcin, header => header, eof_jpg => eof_jpg, uvc_in_free => uvc_in_jpg_free, uvc_rst => uvc_rst); raw_uvc_comp: entity work.raw_uvc port map(raw_en => raw_en, raw_bytes => raw_bytes, raw_fifo_full => raw_fifo_full, error => raw_uvc_error, raw_clk => raw_clk, raw_enable => raw_uvc_enable, slwr => slwr_raw_uvc, pktend => pktend_raw_uvc, fdata => fdataout_raw_uvc, flag_full => flag_full, ifclk => ifclk, faddr => faddr_i, uvcin => uvcin, header => header, to_send => to_send, uvc_in_free => uvc_in_raw_free, uvc_rst => uvc_rst); cdc_in_comp: entity work.cdc_in port map(ifclk => ifclk, faddr => faddr_i, cdcin => cdcin, slwr => slwr_cdc, pktend => pktend_cdc, fdata => fdataout_cdc, cdc_in_free => cdc_in_free, edid0_byte => edid0_byte, edid0_byte_en => edid0_byte_en, edid1_byte => edid1_byte, edid1_byte_en => edid1_byte_en, resX0 => resX_H0, resY0 => resY_H0, resX1 => resX_H1, resY1 => resY_H1, jpeg_error => jpg_uvc_error, rgb_de0 => de_H0, rgb_de1 => de_H1, status => status, usb_cmd => usb_cmd, jpeg_encoder_cmd => jpeg_encoder_cmd, selector_cmd => selector_cmd, hdmi_cmd => hdmi_cmd, debug_byte => debug_byte, debug_index => debug_index, rst => rst, clk => clk ); end architecture;
-------------------------------------------------------------------------------- -- Author: Ahmad Anvari -------------------------------------------------------------------------------- -- Create Date: 07-04-2017 -- Package Name: alu/components -- Module Name: FULL_ADDER -------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; entity FULL_ADDER is port( CIN : in std_logic; A : in std_logic; B : in std_logic; SUM : out std_logic; CARRY : out std_logic ); end entity; architecture FULL_ADDER_ARCH of FULL_ADDER is begin SUM <= CIN xor A xor B; CARRY <= (A and B) or (A and CIN) or (B and CIN); end architecture;
entity step1_read_print is end entity step1_read_print; library STD; use STD.textio.all; library WORK; use WORK.pkg_readline.all; use WORK.types.all; use WORK.printer.all; use WORK.reader.all; architecture test of step1_read_print is procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is begin read_str(str, ast, err); end procedure mal_READ; procedure EVAL(ast: inout mal_val_ptr; env: in string; result: out mal_val_ptr) is begin result := ast; end procedure EVAL; procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is begin pr_str(exp, true, result); end procedure mal_PRINT; procedure REP(str: in string; result: out line; err: out mal_val_ptr) is variable ast, eval_res, read_err: mal_val_ptr; begin mal_READ(str, ast, read_err); if read_err /= null then err := read_err; result := null; return; end if; if ast = null then result := null; return; end if; EVAL(ast, "", eval_res); mal_PRINT(eval_res, result); end procedure REP; procedure repl is variable is_eof: boolean; variable input_line, result: line; variable err: mal_val_ptr; begin loop mal_readline("user> ", is_eof, input_line); exit when is_eof; next when input_line'length = 0; REP(input_line.all, result, err); if err /= null then pr_str(err, false, result); result := new string'("Error: " & result.all); end if; if result /= null then mal_printline(result.all); end if; deallocate(result); deallocate(err); end loop; mal_printline(""); end procedure repl; begin repl; end architecture test;
entity step1_read_print is end entity step1_read_print; library STD; use STD.textio.all; library WORK; use WORK.pkg_readline.all; use WORK.types.all; use WORK.printer.all; use WORK.reader.all; architecture test of step1_read_print is procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is begin read_str(str, ast, err); end procedure mal_READ; procedure EVAL(ast: inout mal_val_ptr; env: in string; result: out mal_val_ptr) is begin result := ast; end procedure EVAL; procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is begin pr_str(exp, true, result); end procedure mal_PRINT; procedure REP(str: in string; result: out line; err: out mal_val_ptr) is variable ast, eval_res, read_err: mal_val_ptr; begin mal_READ(str, ast, read_err); if read_err /= null then err := read_err; result := null; return; end if; if ast = null then result := null; return; end if; EVAL(ast, "", eval_res); mal_PRINT(eval_res, result); end procedure REP; procedure repl is variable is_eof: boolean; variable input_line, result: line; variable err: mal_val_ptr; begin loop mal_readline("user> ", is_eof, input_line); exit when is_eof; next when input_line'length = 0; REP(input_line.all, result, err); if err /= null then pr_str(err, false, result); result := new string'("Error: " & result.all); end if; if result /= null then mal_printline(result.all); end if; deallocate(result); deallocate(err); end loop; mal_printline(""); end procedure repl; begin repl; end architecture test;
entity step1_read_print is end entity step1_read_print; library STD; use STD.textio.all; library WORK; use WORK.pkg_readline.all; use WORK.types.all; use WORK.printer.all; use WORK.reader.all; architecture test of step1_read_print is procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is begin read_str(str, ast, err); end procedure mal_READ; procedure EVAL(ast: inout mal_val_ptr; env: in string; result: out mal_val_ptr) is begin result := ast; end procedure EVAL; procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is begin pr_str(exp, true, result); end procedure mal_PRINT; procedure REP(str: in string; result: out line; err: out mal_val_ptr) is variable ast, eval_res, read_err: mal_val_ptr; begin mal_READ(str, ast, read_err); if read_err /= null then err := read_err; result := null; return; end if; if ast = null then result := null; return; end if; EVAL(ast, "", eval_res); mal_PRINT(eval_res, result); end procedure REP; procedure repl is variable is_eof: boolean; variable input_line, result: line; variable err: mal_val_ptr; begin loop mal_readline("user> ", is_eof, input_line); exit when is_eof; next when input_line'length = 0; REP(input_line.all, result, err); if err /= null then pr_str(err, false, result); result := new string'("Error: " & result.all); end if; if result /= null then mal_printline(result.all); end if; deallocate(result); deallocate(err); end loop; mal_printline(""); end procedure repl; begin repl; end architecture test;
entity step1_read_print is end entity step1_read_print; library STD; use STD.textio.all; library WORK; use WORK.pkg_readline.all; use WORK.types.all; use WORK.printer.all; use WORK.reader.all; architecture test of step1_read_print is procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is begin read_str(str, ast, err); end procedure mal_READ; procedure EVAL(ast: inout mal_val_ptr; env: in string; result: out mal_val_ptr) is begin result := ast; end procedure EVAL; procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is begin pr_str(exp, true, result); end procedure mal_PRINT; procedure REP(str: in string; result: out line; err: out mal_val_ptr) is variable ast, eval_res, read_err: mal_val_ptr; begin mal_READ(str, ast, read_err); if read_err /= null then err := read_err; result := null; return; end if; if ast = null then result := null; return; end if; EVAL(ast, "", eval_res); mal_PRINT(eval_res, result); end procedure REP; procedure repl is variable is_eof: boolean; variable input_line, result: line; variable err: mal_val_ptr; begin loop mal_readline("user> ", is_eof, input_line); exit when is_eof; next when input_line'length = 0; REP(input_line.all, result, err); if err /= null then pr_str(err, false, result); result := new string'("Error: " & result.all); end if; if result /= null then mal_printline(result.all); end if; deallocate(result); deallocate(err); end loop; mal_printline(""); end procedure repl; begin repl; end architecture test;
entity step1_read_print is end entity step1_read_print; library STD; use STD.textio.all; library WORK; use WORK.pkg_readline.all; use WORK.types.all; use WORK.printer.all; use WORK.reader.all; architecture test of step1_read_print is procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is begin read_str(str, ast, err); end procedure mal_READ; procedure EVAL(ast: inout mal_val_ptr; env: in string; result: out mal_val_ptr) is begin result := ast; end procedure EVAL; procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is begin pr_str(exp, true, result); end procedure mal_PRINT; procedure REP(str: in string; result: out line; err: out mal_val_ptr) is variable ast, eval_res, read_err: mal_val_ptr; begin mal_READ(str, ast, read_err); if read_err /= null then err := read_err; result := null; return; end if; if ast = null then result := null; return; end if; EVAL(ast, "", eval_res); mal_PRINT(eval_res, result); end procedure REP; procedure repl is variable is_eof: boolean; variable input_line, result: line; variable err: mal_val_ptr; begin loop mal_readline("user> ", is_eof, input_line); exit when is_eof; next when input_line'length = 0; REP(input_line.all, result, err); if err /= null then pr_str(err, false, result); result := new string'("Error: " & result.all); end if; if result /= null then mal_printline(result.all); end if; deallocate(result); deallocate(err); end loop; mal_printline(""); end procedure repl; begin repl; end architecture test;
entity step1_read_print is end entity step1_read_print; library STD; use STD.textio.all; library WORK; use WORK.pkg_readline.all; use WORK.types.all; use WORK.printer.all; use WORK.reader.all; architecture test of step1_read_print is procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is begin read_str(str, ast, err); end procedure mal_READ; procedure EVAL(ast: inout mal_val_ptr; env: in string; result: out mal_val_ptr) is begin result := ast; end procedure EVAL; procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is begin pr_str(exp, true, result); end procedure mal_PRINT; procedure REP(str: in string; result: out line; err: out mal_val_ptr) is variable ast, eval_res, read_err: mal_val_ptr; begin mal_READ(str, ast, read_err); if read_err /= null then err := read_err; result := null; return; end if; if ast = null then result := null; return; end if; EVAL(ast, "", eval_res); mal_PRINT(eval_res, result); end procedure REP; procedure repl is variable is_eof: boolean; variable input_line, result: line; variable err: mal_val_ptr; begin loop mal_readline("user> ", is_eof, input_line); exit when is_eof; next when input_line'length = 0; REP(input_line.all, result, err); if err /= null then pr_str(err, false, result); result := new string'("Error: " & result.all); end if; if result /= null then mal_printline(result.all); end if; deallocate(result); deallocate(err); end loop; mal_printline(""); end procedure repl; begin repl; end architecture test;
entity step1_read_print is end entity step1_read_print; library STD; use STD.textio.all; library WORK; use WORK.pkg_readline.all; use WORK.types.all; use WORK.printer.all; use WORK.reader.all; architecture test of step1_read_print is procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is begin read_str(str, ast, err); end procedure mal_READ; procedure EVAL(ast: inout mal_val_ptr; env: in string; result: out mal_val_ptr) is begin result := ast; end procedure EVAL; procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is begin pr_str(exp, true, result); end procedure mal_PRINT; procedure REP(str: in string; result: out line; err: out mal_val_ptr) is variable ast, eval_res, read_err: mal_val_ptr; begin mal_READ(str, ast, read_err); if read_err /= null then err := read_err; result := null; return; end if; if ast = null then result := null; return; end if; EVAL(ast, "", eval_res); mal_PRINT(eval_res, result); end procedure REP; procedure repl is variable is_eof: boolean; variable input_line, result: line; variable err: mal_val_ptr; begin loop mal_readline("user> ", is_eof, input_line); exit when is_eof; next when input_line'length = 0; REP(input_line.all, result, err); if err /= null then pr_str(err, false, result); result := new string'("Error: " & result.all); end if; if result /= null then mal_printline(result.all); end if; deallocate(result); deallocate(err); end loop; mal_printline(""); end procedure repl; begin repl; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_03_tb_03_02.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $ -- $Revision: 1.1.1.1 $ -- -- --------------------------------------------------------------------- package test_bench_03_02 is -- following type used in Figure 3-02 -- code from book: type sel_range is range 0 to 3; -- end of code from book end package test_bench_03_02;