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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_02.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package test_bench_03_02 is
-- following type used in Figure 3-02
-- code from book:
type sel_range is range 0 to 3;
-- end of code from book
end package test_bench_03_02;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_02.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package test_bench_03_02 is
-- following type used in Figure 3-02
-- code from book:
type sel_range is range 0 to 3;
-- end of code from book
end package test_bench_03_02;
|
--!
--! @file: exercise8_3.vhd
--! @brief: circuilar shift with compenet #1 constant stages
--! @author: Antonio Gutierrez
--! @date: 2013-11-26
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
library work;
use work.my_components.all;
-- Main code
--------------------------------------
entity exercise8_3 is
generic (N: integer := 5); -- num of stages
port (
clk, load: in std_logic;
d: in twoD(0 to M-1, N-1 downto 0);
q: buffer twoD(0 to M-1, N-1 downto 0));
constant M: integer := 8; -- bits per stage
end entity exercise8_3;
--------------------------------------
architecture circuit of exercise8_3 is
signal u: twoD(0 to M-1, N-1 downto 0); -- output of muxes
signal v: twoD(0 to M-1, N-1 downto 0); -- output of ffs
begin
gen1: for i in N-1 downto 0 generate -- width
gen2: for j in 0 to M-1 generate -- length
mux1: mux port map (
a => d(i, j),
b => v(i, M-1( - j)),
sel => load,
q => u(i, j)
);
dff1: flipflop port map (
d => u(i, j),
clk => clk,
q => v(i, j)
);
end generate gen2;
end generate gen1;
end architecture circuit;
--------------------------------------
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
USE ieee.numeric_std.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module clips video streams on the DE boards. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Video_Clipper IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
DW :INTEGER := 15; -- Frame's data width
EW :INTEGER := 0; -- Frame's empty width
WIDTH_IN :INTEGER := 720; -- Incoming frame's width in pixels
HEIGHT_IN :INTEGER := 244; -- Incoming frame's height in lines
WW_IN :INTEGER := 9; -- Incoming frame's width's address width
HW_IN :INTEGER := 7; -- Incoming frame's height's address width
DROP_PIXELS_AT_START :INTEGER := 40;
DROP_PIXELS_AT_END :INTEGER := 40;
DROP_LINES_AT_START :INTEGER := 2;
DROP_LINES_AT_END :INTEGER := 2;
WIDTH_OUT :INTEGER := 640; -- Final frame's width in pixels
HEIGHT_OUT :INTEGER := 240; -- Final frame's height in lines
WW_OUT :INTEGER := 9; -- Final frame's width's address width
HW_OUT :INTEGER := 7; -- Final frame's height's address width
ADD_PIXELS_AT_START :INTEGER := 0;
ADD_PIXELS_AT_END :INTEGER := 0;
ADD_LINES_AT_START :INTEGER := 0;
ADD_LINES_AT_END :INTEGER := 0;
ADD_DATA :STD_LOGIC_VECTOR(15 DOWNTO 0) := B"0000000000000000" -- Data value for added pixels
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END Video_System_Video_Clipper;
ARCHITECTURE Behaviour OF Video_System_Video_Clipper IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL internal_data :STD_LOGIC_VECTOR(DW DOWNTO 0);
SIGNAL internal_startofpacket :STD_LOGIC;
SIGNAL internal_endofpacket :STD_LOGIC;
SIGNAL internal_empty :STD_LOGIC_VECTOR(EW DOWNTO 0);
SIGNAL internal_valid :STD_LOGIC;
SIGNAL internal_ready :STD_LOGIC;
-- Internal Registers
-- State Machine Registers
-- Integers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
COMPONENT altera_up_video_clipper_drop
GENERIC (
DW :INTEGER;
EW :INTEGER;
IMAGE_WIDTH :INTEGER;
IMAGE_HEIGHT :INTEGER;
WW :INTEGER;
HW :INTEGER;
DROP_PIXELS_AT_START :INTEGER;
DROP_PIXELS_AT_END :INTEGER;
DROP_LINES_AT_START :INTEGER;
DROP_LINES_AT_END :INTEGER;
ADD_DATA :STD_LOGIC_VECTOR(15 DOWNTO 0)
);
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END COMPONENT;
COMPONENT altera_up_video_clipper_add
GENERIC (
DW :INTEGER;
EW :INTEGER;
IMAGE_WIDTH :INTEGER;
IMAGE_HEIGHT :INTEGER;
WW :INTEGER;
HW :INTEGER;
ADD_PIXELS_AT_START :INTEGER;
ADD_PIXELS_AT_END :INTEGER;
ADD_LINES_AT_START :INTEGER;
ADD_LINES_AT_END :INTEGER;
ADD_DATA :STD_LOGIC_VECTOR(15 DOWNTO 0)
);
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(DW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(EW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END COMPONENT;
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
-- Internal Registers
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
-- Internal Assignments
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
Clipper_Drop : altera_up_video_clipper_drop
GENERIC MAP (
DW => DW,
EW => EW,
IMAGE_WIDTH => WIDTH_IN,
IMAGE_HEIGHT => HEIGHT_IN,
WW => WW_IN,
HW => HW_IN,
DROP_PIXELS_AT_START => DROP_PIXELS_AT_START,
DROP_PIXELS_AT_END => DROP_PIXELS_AT_END,
DROP_LINES_AT_START => DROP_LINES_AT_START,
DROP_LINES_AT_END => DROP_LINES_AT_END,
ADD_DATA => ADD_DATA
)
PORT MAP (
-- Inputs
clk => clk,
reset => reset,
stream_in_data => stream_in_data,
stream_in_startofpacket => stream_in_startofpacket,
stream_in_endofpacket => stream_in_endofpacket,
stream_in_empty => stream_in_empty,
stream_in_valid => stream_in_valid,
stream_out_ready => internal_ready,
-- Bidirectional
-- Outputs
stream_in_ready => stream_in_ready,
stream_out_data => internal_data,
stream_out_startofpacket => internal_startofpacket,
stream_out_endofpacket => internal_endofpacket,
stream_out_empty => internal_empty,
stream_out_valid => internal_valid
);
Clipper_Add : altera_up_video_clipper_add
GENERIC MAP (
DW => DW,
EW => EW,
IMAGE_WIDTH => WIDTH_OUT,
IMAGE_HEIGHT => HEIGHT_OUT,
WW => WW_OUT,
HW => HW_OUT,
ADD_PIXELS_AT_START => ADD_PIXELS_AT_START,
ADD_PIXELS_AT_END => ADD_PIXELS_AT_END,
ADD_LINES_AT_START => ADD_LINES_AT_START,
ADD_LINES_AT_END => ADD_LINES_AT_END,
ADD_DATA => ADD_DATA
)
PORT MAP (
-- Inputs
clk => clk,
reset => reset,
stream_in_data => internal_data,
stream_in_startofpacket => internal_startofpacket,
stream_in_endofpacket => internal_endofpacket,
stream_in_empty => internal_empty,
stream_in_valid => internal_valid,
stream_out_ready => stream_out_ready,
-- Bidirectional
-- Outputs
stream_in_ready => internal_ready,
stream_out_data => stream_out_data,
stream_out_startofpacket => stream_out_startofpacket,
stream_out_endofpacket => stream_out_endofpacket,
stream_out_empty => stream_out_empty,
stream_out_valid => stream_out_valid
);
END Behaviour;
|
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use IEEE.std_logic_unsigned.all;
use work.PhoenixPackage.all;
entity outputModule is
generic(
address: regflit
);
port(
clock: in std_logic;
tx: in std_logic;
data: in regflit;
currentTime: std_logic_vector(4*TAM_FLIT-1 downto 0)
);
end;
architecture outputModule of outputModule is
begin
process(clock, tx, data, currentTime)
variable cont : integer := 0;
variable remaining_flits : std_logic_vector(TAM_FLIT-1 downto 0) := (others=>'0');
file my_output : TEXT open WRITE_MODE is "Out/out"&to_hstring(address)&".txt";
variable my_output_line : LINE;
variable timeSourceCore: std_logic_vector ((TAM_FLIT*4)-1 downto 0) := (others=>'0');
variable timeSourceNet: std_logic_vector ((TAM_FLIT*4)-1 downto 0) := (others=>'0');
variable timeTarget: std_logic_vector ((TAM_FLIT*4)-1 downto 0) := (others=>'0');
variable aux_latency: std_logic_vector ((TAM_FLIT*4)-1 downto 0) := (others=>'0'); --latência desde o tempo de criação do pacote (em decimal)
variable control_pkt: std_logic;
begin
if(clock'event and clock='0' and tx='1')then
-- DADOS DE CONTROLE:
if (cont = 0) then -- destino
write(my_output_line, string'(to_hstring(data)));
write(my_output_line, string'(" "));
cont := 1;
control_pkt := data((TAM_FLIT-1));
elsif (cont = 1) then -- tamanho
write(my_output_line, string'(to_hstring(data)));
write(my_output_line, string'(" "));
remaining_flits := data;
cont := 2;
-- DADOS DO PAYLOAD:
elsif (remaining_flits > 1) then
remaining_flits := remaining_flits - 1; -- vai sair quando remaining_flits for 0
if (cont >= 3 and cont <= 6 and control_pkt='0') then -- captura timestamp
timeSourceCore((TAM_FLIT*(7-cont)-1) downto (TAM_FLIT*(6-cont))) := data;
end if;
if (cont >= 9 and cont <= 12 and control_pkt='0') then -- captura timestamp
timeSourceNet((TAM_FLIT*(13-cont)-1) downto (TAM_FLIT*(12-cont))) := data;
end if;
write(my_output_line, string'(to_hstring(data)));
write(my_output_line, string'(" "));
cont := cont + 1;
-- ultimo flit do pacote
else
write(my_output_line, string'(to_hstring(data)));
--writeline(my_output, my_output_line);
cont := 0;
if (control_pkt='0') then
timeTarget := currentTime;
for j in (TAM_FLIT/4) downto 1 loop
write(my_output_line, string'(" "));
write(my_output_line, string'(to_hstring(timeTarget( TAM_FLIT*j-1 downto TAM_FLIT*(j-1) ))));
end loop;
write(my_output_line, string'(" "));
write(my_output_line, string'(integer'image(CONV_INTEGER(timeSourceCore((TAM_FLIT*2)-1 downto 0)))));
write(my_output_line, string'(" "));
write(my_output_line, string'(integer'image(CONV_INTEGER(timeSourceNet((TAM_FLIT*2)-1 downto 0)))));
write(my_output_line, string'(" "));
write(my_output_line, string'(integer'image(CONV_INTEGER(timeTarget((TAM_FLIT*2)-1 downto 0)))));
write(my_output_line, string'(" "));
aux_latency := (timeTarget-timeSourceCore);
write(my_output_line, string'(integer'image(CONV_INTEGER(aux_latency((TAM_FLIT*2)-1 downto 0)))));
write(my_output_line, string'(" "));
write(my_output_line, string'("0"));
writeline(my_output, my_output_line);
end if;
end if;
end if; --end if clock'event...
end process;
end outputModule;
|
----------------------------------------------------------------------------------
-- Module Name: link_signal_mgmt - Behavioral
--
-- Description: Controls the settings and state of the GTX transceivers based on
-- The registers that are read from the host.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity link_signal_mgmt is
Port ( mgmt_clk : in STD_LOGIC;
tx_powerup : in STD_LOGIC; -- Falling edge is used used as a reset too!
status_de : in std_logic;
adjust_de : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : in std_logic_vector(7 downto 0);
-------------------------------------------
sink_channel_count : in std_logic_vector(2 downto 0);
source_channel_count : in std_logic_vector(2 downto 0);
stream_channel_count : in std_logic_vector(2 downto 0);
active_channel_count : out std_logic_vector(2 downto 0);
---------------------------------------------------------
powerup_channel : out std_logic_vector(3 downto 0) := (others => '0');
-----------------------------------------
clock_locked : out STD_LOGIC;
equ_locked : out STD_LOGIC;
symbol_locked : out STD_LOGIC;
align_locked : out STD_LOGIC;
preemp_0p0 : out STD_LOGIC := '0';
preemp_3p5 : out STD_LOGIC := '0';
preemp_6p0 : out STD_LOGIC := '0';
swing_0p4 : out STD_LOGIC := '0';
swing_0p6 : out STD_LOGIC := '0';
swing_0p8 : out STD_LOGIC := '0');
end link_signal_mgmt;
architecture arch of link_signal_mgmt is
signal power_mask : std_logic_vector(3 downto 0) := "0000";
signal preemp_level : std_logic_vector(1 downto 0) := "00";
signal voltage_level : std_logic_vector(1 downto 0) := "00";
signal channel_state : std_logic_vector(23 downto 0):= (others => '0');
signal channel_adjust : std_logic_vector(15 downto 0):= (others => '0');
signal active_channel_count_i : std_logic_vector(2 downto 0);
signal pipe_channel_count : std_logic_vector(2 downto 0);
begin
active_channel_count <= active_channel_count_i;
process(mgmt_clk)
begin
if rising_edge(mgmt_clk) then
----------------------------------------------------------
-- Work out how many channels will be active
-- (the min of source_channel_count and sink_channel_count
--
-- Also work out the power-up mask for the transceivers
-----------------------------------------------------------
case source_channel_count is
when "100" =>
case sink_channel_count is
when "100" => pipe_channel_count <= "100";
when "010" => pipe_channel_count <= "010";
when others => pipe_channel_count <= "001";
end case;
when "010" =>
case sink_channel_count is
when "100" => pipe_channel_count <= "010";
when "010" => pipe_channel_count <= "010";
when others => pipe_channel_count <= "001";
end case;
when others =>
pipe_channel_count <= "001";
end case;
case stream_channel_count is
when "100" =>
case pipe_channel_count is
when "100" => active_channel_count_i <= "100"; power_mask <= "1111";
when "010" => active_channel_count_i <= "010"; power_mask <= "0000";
when others => active_channel_count_i <= "000"; power_mask <= "0000";
end case;
when "010" =>
case pipe_channel_count is
when "100" => active_channel_count_i <= "010"; power_mask <= "0011";
when "010" => active_channel_count_i <= "010"; power_mask <= "0011";
when others => active_channel_count_i <= "000"; power_mask <= "0000";
end case;
when others =>
active_channel_count_i <= "001"; power_mask <= "0001";
end case;
---------------------------------------------
-- If the powerup is not asserted, then reset
-- everything.
---------------------------------------------
if tx_powerup = '1' then
powerup_channel <= power_mask;
else
powerup_channel <= (others => '0');
preemp_level <= "00";
voltage_level <= "00";
channel_state <= (others => '0');
channel_adjust <= (others => '0');
end if;
---------------------------------------------
-- Decode the power and pre-emphasis levels
---------------------------------------------
case preemp_level is
when "00" => preemp_0p0 <= '1'; preemp_3p5 <= '0'; preemp_6p0 <= '0';
when "01" => preemp_0p0 <= '0'; preemp_3p5 <= '1'; preemp_6p0 <= '0';
when others => preemp_0p0 <= '0'; preemp_3p5 <= '0'; preemp_6p0 <= '1';
end case;
case voltage_level is
when "00" => swing_0p4 <= '1'; swing_0p6 <= '0'; swing_0p8 <= '0';
when "01" => swing_0p4 <= '0'; swing_0p6 <= '1'; swing_0p8 <= '0';
when others => swing_0p4 <= '0'; swing_0p6 <= '0'; swing_0p8 <= '1';
end case;
-----------------------------------------------
-- Receive the status data from the AUX channel
-----------------------------------------------
if status_de = '1' then
case addr is
when x"02" => channel_state( 7 downto 0) <= data;
when x"03" => channel_state(15 downto 8) <= data;
when x"04" => channel_state(23 downto 16) <= data;
when others => NULL;
end case;
end if;
-----------------------------------------------
-- Receive the channel adjustment request
-----------------------------------------------
if adjust_de = '1' then
case addr is
when x"00" => channel_adjust( 7 downto 0) <= data;
when x"01" => channel_adjust(15 downto 8) <= data;
when others => NULL;
end case;
end if;
-----------------------------------------------
-- Update the status signals based on the
-- register data recieved over from the AUX
-- channel.
-----------------------------------------------
clock_locked <= '0';
equ_locked <= '0';
symbol_locked <= '0';
case active_channel_count_i is
when "001" => if (channel_state(3 downto 0) AND x"1") = x"1" then
clock_locked <= '1';
end if;
if (channel_state(3 downto 0) AND x"3") = x"3" then
equ_locked <= '1';
end if;
if (channel_state(3 downto 0) AND x"7") = x"7" then
symbol_locked <= '1';
end if;
when "010" => if (channel_state(7 downto 0) AND x"11") = x"11" then
clock_locked <= '1';
end if;
if (channel_state(7 downto 0) AND x"33") = x"33" then
equ_locked <= '1';
end if;
if (channel_state(7 downto 0) AND x"77") = x"77" then
symbol_locked <= '1';
end if;
when "100" => if (channel_state(15 downto 0) AND x"1111") = x"1111" then
clock_locked <= '1';
end if;
if (channel_state(15 downto 0) AND x"3333") = x"3333" then
equ_locked <= '1';
end if;
if (channel_state(15 downto 0) AND x"7777") = x"7777" then
symbol_locked <= '1';
end if;
when others => NULL;
end case;
align_locked <= channel_state(16);
end if;
end process;
end architecture; |
---------------------------------------------------------------------
-- TITLE: Multiplication and Division Unit
-- AUTHORS: Steve Rhoads ([email protected])
-- DATE CREATED: 1/31/01
-- FILENAME: mult.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the multiplication and division unit in 32 clocks.
--
-- To reduce space, compile your code using the flag "-mno-mul" which
-- will use software base routines in math.c if USE_SW_MULT is defined.
-- Then remove references to the entity mult in mlite_cpu.vhd.
--
-- MULTIPLICATION
-- long64 answer = 0;
-- for(i = 0; i < 32; ++i)
-- {
-- answer = (answer >> 1) + (((b&1)?a:0) << 31);
-- b = b >> 1;
-- }
--
-- DIVISION
-- long upper=a, lower=0;
-- a = b << 31;
-- for(i = 0; i < 32; ++i)
-- {
-- lower = lower << 1;
-- if(upper >= a && a && b < 2)
-- {
-- upper = upper - a;
-- lower |= 1;
-- }
-- a = ((b&2) << 30) | (a >> 1);
-- b = b >> 1;
-- }
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
library work;
use work.mips_constants.all;
entity mult is
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end; --entity mult
architecture logic of mult is
constant MODE_MULT : std_logic := '1';
constant MODE_DIV : std_logic := '0';
signal mode_reg : std_logic;
signal negate_reg : std_logic;
signal sign_reg : std_logic;
signal sign2_reg : std_logic;
signal count_reg : std_logic_vector(5 downto 0) := (others => '0');
signal aa_reg : std_logic_vector(31 downto 0);
signal bb_reg : std_logic_vector(31 downto 0);
signal upper_reg : std_logic_vector(31 downto 0);
signal lower_reg : std_logic_vector(31 downto 0);
signal a_neg : std_logic_vector(31 downto 0);
signal b_neg : std_logic_vector(31 downto 0);
signal sum : std_logic_vector(32 downto 0);
begin
-- Result
c_mult <= lower_reg when mult_func = MULT_READ_LO and negate_reg = '0' else
bv_negate(lower_reg) when mult_func = MULT_READ_LO
and negate_reg = '1' else
upper_reg when mult_func = MULT_READ_HI else
ZERO;
pause_out <= '1' when (count_reg /= "000000") else '0';
-- and
-- (mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) else '0';
-- ABS and remainder signals
a_neg <= bv_negate(a);
b_neg <= bv_negate(b);
sum <= bv_adder(upper_reg, aa_reg, mode_reg);
--multiplication/division unit
mult_proc: process(clk, reset_in, a, b, mult_func,
a_neg, b_neg, sum, sign_reg, mode_reg, negate_reg,
count_reg, aa_reg, bb_reg, upper_reg, lower_reg)
variable count : std_logic_vector(2 downto 0);
begin
count := "001";
if reset_in = '1' then
mode_reg <= '0';
negate_reg <= '0';
sign_reg <= '0';
sign2_reg <= '0';
count_reg <= "000000";
aa_reg <= ZERO;
bb_reg <= ZERO;
upper_reg <= ZERO;
lower_reg <= ZERO;
elsif rising_edge(clk) then
case mult_func is
when MULT_WRITE_LO =>
lower_reg <= a;
negate_reg <= '0';
when MULT_WRITE_HI =>
upper_reg <= a;
negate_reg <= '0';
when MULT_MULT =>
mode_reg <= MODE_MULT;
aa_reg <= a;
bb_reg <= b;
upper_reg <= ZERO;
count_reg <= "100000";
negate_reg <= '0';
sign_reg <= '0';
sign2_reg <= '0';
when MULT_SIGNED_MULT =>
mode_reg <= MODE_MULT;
if b(31) = '0' then
aa_reg <= a;
bb_reg <= b;
else
aa_reg <= a_neg;
bb_reg <= b_neg;
end if;
sign_reg <= a(31) xor b(31);
sign2_reg <= '0';
upper_reg <= ZERO;
count_reg <= "100000";
negate_reg <= '0';
when MULT_DIVIDE =>
mode_reg <= MODE_DIV;
aa_reg <= b(0) & ZERO(30 downto 0);
bb_reg <= b;
upper_reg <= a;
count_reg <= "100000";
negate_reg <= '0';
when MULT_SIGNED_DIVIDE =>
mode_reg <= MODE_DIV;
if b(31) = '0' then
aa_reg(31) <= b(0);
bb_reg <= b;
else
aa_reg(31) <= b_neg(0);
bb_reg <= b_neg;
end if;
if a(31) = '0' then
upper_reg <= a;
else
upper_reg <= a_neg;
end if;
aa_reg(30 downto 0) <= ZERO(30 downto 0);
count_reg <= "100000";
negate_reg <= a(31) xor b(31);
when others =>
if count_reg /= "000000" then
if mode_reg = MODE_MULT then
-- Multiplication
if bb_reg(0) = '1' then
upper_reg <= (sign_reg xor sum(32)) & sum(31 downto 1);
lower_reg <= sum(0) & lower_reg(31 downto 1);
sign2_reg <= sign2_reg or sign_reg;
sign_reg <= '0';
bb_reg <= '0' & bb_reg(31 downto 1);
-- The following six lines are optional for speedup
--elsif bb_reg(3 downto 0) = "0000" and sign2_reg = '0' and
-- count_reg(5 downto 2) /= "0000" then
-- upper_reg <= "0000" & upper_reg(31 downto 4);
-- lower_reg <= upper_reg(3 downto 0) & lower_reg(31 downto 4);
-- count := "100";
-- bb_reg <= "0000" & bb_reg(31 downto 4);
else
upper_reg <= sign2_reg & upper_reg(31 downto 1);
lower_reg <= upper_reg(0) & lower_reg(31 downto 1);
bb_reg <= '0' & bb_reg(31 downto 1);
end if;
else
-- Division
if sum(32) = '0' and aa_reg /= ZERO and
bb_reg(31 downto 1) = ZERO(31 downto 1) then
upper_reg <= sum(31 downto 0);
lower_reg(0) <= '1';
else
lower_reg(0) <= '0';
end if;
aa_reg <= bb_reg(1) & aa_reg(31 downto 1);
lower_reg(31 downto 1) <= lower_reg(30 downto 0);
bb_reg <= '0' & bb_reg(31 downto 1);
end if;
count_reg <= count_reg - count;
end if; --count
end case;
end if;
end process;
end; --architecture logic
|
-------------------------------------------------------------------------------
-- Title : Bus Module for ADC AD7266
-- Project : Loa
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
-- TODO mask does not work here
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.utils_pkg.all;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.adc_ad7266_pkg.all;
-------------------------------------------------------------------------------
entity adc_ad7266_single_ended_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
CHANNELS : positive := 12); -- AD7266 has 12 single ended channels
port (
adc_out_p : out adc_ad7266_spi_out_type;
adc_in_p : in adc_ad7266_spi_in_type;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
-- direct access to the read adc samples
adc_values_o : out adc_ad7266_values_type(CHANNELS - 1 downto 0);
clk : in std_logic
);
end adc_ad7266_single_ended_module;
-------------------------------------------------------------------------------
architecture behavioral of adc_ad7266_single_ended_module is
constant REG_ADDR_BIT : positive := required_bits(CHANNELS);
type adc_ad7266_module_state_type is (IDLE, WAIT_FOR_ADC);
type adc_ad7266_module_type is record
state : adc_ad7266_module_state_type;
start : std_logic;
current_ch : integer range 0 to (CHANNELS / 2) - 1;
reg : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : adc_ad7266_module_type := (state => IDLE,
current_ch => (CHANNELS / 2) - 1,
start => '0',
reg => (others => (others => '0')));
signal adc_mode_s : std_logic;
signal channel_s : std_logic_vector(2 downto 0);
signal value_a_s : std_logic_vector(11 downto 0); --AD7266 converts two
--channels a,b at one
--address (12 channels
--vs 6 addresses)
signal value_b_s : std_logic_vector(11 downto 0);
signal done_s : std_logic;
signal reg_o : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
signal reg_i : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
signal mask_s : std_logic_vector(((CHANNELS / 2) - 1) downto 0);
begin
-- mapping signals to adc i/f
adc_mode_s <= '1'; -- we don't use differential mode
channel_s <= std_logic_vector(to_unsigned(r.current_ch, 3));
reg_i <= r.reg;
-- present last value of each channel on this modules ports
copy_loop : for ii in 0 to 11 generate -- (2**REG_ADDR_BIT-1)
adc_values_o(ii) <= r.reg(ii)(11 downto 0); --12bit ADC (AD7266)
end generate copy_loop;
-- register for channel mask
-- you will always mask out two channels at once
mask_s <= reg_o(0)((CHANNELS / 2) - 1 downto 0);
-------------------------------------------------------------------------------
---- seq part of FSM
-------------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
-----------------------------------------------------------------------------
-- transitions and actions of FSM
-----------------------------------------------------------------------------
comb_proc : process(done_s, mask_s, r, value_a_s, value_b_s)
variable v : adc_ad7266_module_type;
begin
v := r;
case v.state is
when IDLE =>
-- in this state we iterate over the channels
if v.current_ch = ((CHANNELS / 2)-1) then
-- we wrap around (to 0)
v.current_ch := 0;
else
-- or increment the currently selected channel
v.current_ch := v.current_ch + 1;
end if;
-- if the channel isn't masked out, we take a sample
-- if mask_s(v.current_ch) = '0' then
v.start := '1';
v.state := WAIT_FOR_ADC;
-- end if;
when WAIT_FOR_ADC =>
-- adc i/f has already started conversion, we stay in this state until
-- the conversion is over.
v.start := '0';
if done_s = '1' then
-- if the conversion is done we put its result in the right register,
-- for each value a,b
-- and return to the "idle" state.
v.reg(v.current_ch) := ("0000") & value_a_s;
v.reg(v.current_ch + (CHANNELS / 2)) := ("0000") & value_b_s;
v.state := IDLE;
end if;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- Register file to present ADC values to bus
-- and configuration
reg_file_1 : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => REG_ADDR_BIT)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
clk => clk);
-- ADC interface module
adc_ad7266_1 : adc_ad7266_single_ended
generic map (
DELAY => 1)
port map (
adc_out => adc_out_p,
adc_in => adc_in_p,
start_p => r.start,
adc_mode_p => adc_mode_s,
channel_p => channel_s,
value_a_p => value_a_s,
value_b_p => value_b_s,
done_p => done_s,
clk => clk);
end behavioral;
|
-------------------------------------------------------------------------------
-- Title : Bus Module for ADC AD7266
-- Project : Loa
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
-- TODO mask does not work here
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.utils_pkg.all;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.adc_ad7266_pkg.all;
-------------------------------------------------------------------------------
entity adc_ad7266_single_ended_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
CHANNELS : positive := 12); -- AD7266 has 12 single ended channels
port (
adc_out_p : out adc_ad7266_spi_out_type;
adc_in_p : in adc_ad7266_spi_in_type;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
-- direct access to the read adc samples
adc_values_o : out adc_ad7266_values_type(CHANNELS - 1 downto 0);
clk : in std_logic
);
end adc_ad7266_single_ended_module;
-------------------------------------------------------------------------------
architecture behavioral of adc_ad7266_single_ended_module is
constant REG_ADDR_BIT : positive := required_bits(CHANNELS);
type adc_ad7266_module_state_type is (IDLE, WAIT_FOR_ADC);
type adc_ad7266_module_type is record
state : adc_ad7266_module_state_type;
start : std_logic;
current_ch : integer range 0 to (CHANNELS / 2) - 1;
reg : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : adc_ad7266_module_type := (state => IDLE,
current_ch => (CHANNELS / 2) - 1,
start => '0',
reg => (others => (others => '0')));
signal adc_mode_s : std_logic;
signal channel_s : std_logic_vector(2 downto 0);
signal value_a_s : std_logic_vector(11 downto 0); --AD7266 converts two
--channels a,b at one
--address (12 channels
--vs 6 addresses)
signal value_b_s : std_logic_vector(11 downto 0);
signal done_s : std_logic;
signal reg_o : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
signal reg_i : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
signal mask_s : std_logic_vector(((CHANNELS / 2) - 1) downto 0);
begin
-- mapping signals to adc i/f
adc_mode_s <= '1'; -- we don't use differential mode
channel_s <= std_logic_vector(to_unsigned(r.current_ch, 3));
reg_i <= r.reg;
-- present last value of each channel on this modules ports
copy_loop : for ii in 0 to 11 generate -- (2**REG_ADDR_BIT-1)
adc_values_o(ii) <= r.reg(ii)(11 downto 0); --12bit ADC (AD7266)
end generate copy_loop;
-- register for channel mask
-- you will always mask out two channels at once
mask_s <= reg_o(0)((CHANNELS / 2) - 1 downto 0);
-------------------------------------------------------------------------------
---- seq part of FSM
-------------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
-----------------------------------------------------------------------------
-- transitions and actions of FSM
-----------------------------------------------------------------------------
comb_proc : process(done_s, mask_s, r, value_a_s, value_b_s)
variable v : adc_ad7266_module_type;
begin
v := r;
case v.state is
when IDLE =>
-- in this state we iterate over the channels
if v.current_ch = ((CHANNELS / 2)-1) then
-- we wrap around (to 0)
v.current_ch := 0;
else
-- or increment the currently selected channel
v.current_ch := v.current_ch + 1;
end if;
-- if the channel isn't masked out, we take a sample
-- if mask_s(v.current_ch) = '0' then
v.start := '1';
v.state := WAIT_FOR_ADC;
-- end if;
when WAIT_FOR_ADC =>
-- adc i/f has already started conversion, we stay in this state until
-- the conversion is over.
v.start := '0';
if done_s = '1' then
-- if the conversion is done we put its result in the right register,
-- for each value a,b
-- and return to the "idle" state.
v.reg(v.current_ch) := ("0000") & value_a_s;
v.reg(v.current_ch + (CHANNELS / 2)) := ("0000") & value_b_s;
v.state := IDLE;
end if;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- Register file to present ADC values to bus
-- and configuration
reg_file_1 : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => REG_ADDR_BIT)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
clk => clk);
-- ADC interface module
adc_ad7266_1 : adc_ad7266_single_ended
generic map (
DELAY => 1)
port map (
adc_out => adc_out_p,
adc_in => adc_in_p,
start_p => r.start,
adc_mode_p => adc_mode_s,
channel_p => channel_s,
value_a_p => value_a_s,
value_b_p => value_b_s,
done_p => done_s,
clk => clk);
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
package xtccomppkg is
component generic_dp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(data_bits-1 downto 0);
dob: out std_logic_vector(data_bits-1 downto 0)
);
end component;
component generic_dp_ram_r is
generic (
address_bits: integer := 8;
srval_1: std_logic_vector(31 downto 0);
srval_2: std_logic_vector(31 downto 0)
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
ssra: in std_logic;
dia: in std_logic_vector(31 downto 0);
doa: out std_logic_vector(31 downto 0);
clkb: in std_logic;
enb: in std_logic;
ssrb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(31 downto 0);
dob: out std_logic_vector(31 downto 0);
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0);
dbg_do: out std_logic_vector(32-1 downto 0)
);
end component;
component xtc is
port (
wb_syscon: in wb_syscon_type;
-- Master wishbone interface
wbo: out wb_mosi_type;
wbi: in wb_miso_type;
-- ROM wb interface
romwbo: out wb_mosi_type;
romwbi: in wb_miso_type;
nmi: in std_logic;
nmiack: out std_logic;
rstreq: out std_logic;
break: out std_logic;
intack: out std_logic;
edbg: in memory_debug_type
);
end component;
component icache is
generic (
ADDRESS_HIGH: integer := 26
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
valid: out std_logic;
data: out std_logic_vector(31 downto 0);
address: in std_logic_vector(31 downto 0);
strobe: in std_logic;
enable: in std_logic;
stall: out std_logic;
flush: in std_logic;
abort: in std_logic;
tag: in std_logic_vector(31 downto 0);
tagen: in std_logic;
-- Master wishbone interface
m_wb_ack_i: in std_logic;
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_adr_o: out std_logic_vector(31 downto 0);
m_wb_cyc_o: out std_logic;
m_wb_stb_o: out std_logic;
m_wb_stall_i: in std_logic;
m_wb_we_o: out std_logic
);
end component;
component mux32_4 is
port (
i0: in std_logic_vector(31 downto 0);
i1: in std_logic_vector(31 downto 0);
i2: in std_logic_vector(31 downto 0);
i3: in std_logic_vector(31 downto 0);
sel: in std_logic_vector(1 downto 0);
o: out std_logic_vector(31 downto 0)
);
end component;
component mux32_2 is
port (
i0: in std_logic_vector(31 downto 0);
i1: in std_logic_vector(31 downto 0);
sel: in std_logic;
o: out std_logic_vector(31 downto 0)
);
end component mux32_2;
component alu is
port (
clk: in std_logic;
rst: in std_logic;
a: in unsigned(31 downto 0);
b: in unsigned(31 downto 0);
o: out unsigned(31 downto 0);
y: out unsigned(31 downto 0);
op: in alu_op_type;
en: in std_logic;
ci: in std_logic;
cen:in std_logic;
busy: out std_logic;
valid: out std_logic;
co: out std_logic;
zero: out std_logic;
ovf: out std_logic;
sign: out std_logic
);
end component;
component fetch is port (
clk: in std_logic;
rst: in std_logic;
-- Connection to ROM
stall: in std_logic;
valid: in std_logic;
address: out std_logic_vector(31 downto 0);
read: in std_logic_vector(31 downto 0);
enable: out std_logic;
strobe: out std_logic;
abort: out std_logic;
nseq: out std_logic;
-- Control
freeze: in std_logic;
jump: in std_logic;
jumpaddr: in word_type;
dual: in std_logic;
-- Outputs for next stages
fuo: out fetch_output_type
);
end component;
component decode is
port (
clk: in std_logic;
rst: in std_logic;
-- Input for previous stages
fui: in fetch_output_type;
-- Output for next stages
duo: out decode_output_type;
busy: out std_logic;
freeze: in std_logic;
flush: in std_logic;
jump: in std_logic;
jumpmsb: in std_logic;
dual: out std_logic
);
end component;
component fetchdata is
port (
clk: in std_logic;
rst: in std_logic;
-- Register access
r1_en: out std_logic;
r1_addr: out regaddress_type;
r1_read: in word_type_std;
r2_en: out std_logic;
r2_addr: out regaddress_type;
r2_read: in word_type_std;
w_addr: out regaddress_type;
w_en: out std_logic;
-- Input for previous stages
dui: in decode_output_type;
freeze: in std_logic;
flush: in std_logic;
refetch: in std_logic;
executed: in boolean;
clrhold: in std_logic;
-- Output for next stages
fduo: out fetchdata_output_type
);
end component;
component execute is
port (
clk: in std_logic;
rst: in std_logic;
mem_busy: in std_logic;
busy: out std_logic;
refetch: in std_logic;
wb_busy: in std_logic;
int: in std_logic;
intline: in std_logic_vector(7 downto 0);
nmi: in std_logic;
nmiack: out std_logic;
-- Input for previous stages
fdui: in fetchdata_output_type;
-- Output for next stages
euo: out execute_output_type;
-- Input from memory unit, for SPR update
mui: in memory_output_type;
-- Coprocessor interface
co: out copifo;
ci: in copifi;
dbgo: out execute_debug_type
);
end component execute;
component memory is
port (
clk: in std_logic;
rst: in std_logic;
-- Memory interface
wb_ack_i: in std_logic;
wb_err_i: in std_logic;
wb_dat_i: in std_logic_vector(31 downto 0);
wb_dat_o: out std_logic_vector(31 downto 0);
wb_adr_o: out std_logic_vector(31 downto 0);
wb_tag_o: out std_logic_vector(31 downto 0);
wb_tag_i: in std_logic_vector(31 downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_stall_i: in std_logic;
protw: in std_logic_vector(31 downto 0);
proten: in std_logic;
busy: out std_logic;
refetch: out std_logic;
dbgo: out memory_debug_type;
-- Input for previous stages
eui: in execute_output_type;
-- Output for next stages
muo: out memory_output_type
);
end component memory;
component writeback is
port (
clk: in std_logic;
rst: in std_logic;
busy: out std_logic;
-- Register 0 access writeback
r0_en: out std_logic;
r0_we: out std_logic;
r0_addr: out regaddress_type;
r0_write: out word_type_std;
-- Register 1 access writeback
r1_en: out std_logic;
r1_we: out std_logic;
r1_addr: out regaddress_type;
r1_write: out word_type_std;
-- Input for previous stages
mui: in memory_output_type;
eui: in execute_output_type
);
end component;
component regbank_2p is
generic (
ADDRESS_BITS: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_wr: in std_logic_vector(31 downto 0);
rb2_we: in std_logic;
rb2_en: in std_logic;
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
dbg_do: out std_logic_vector(32-1 downto 0)
);
end component;
component regbank_3p is
generic (
ADDRESS_BITS: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_en: in std_logic;
rb2_rd: out std_logic_vector(31 downto 0);
rb3_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb3_wr: in std_logic_vector(31 downto 0);
rb3_we: in std_logic;
rb3_en: in std_logic
-- RTL Debug access
--dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
--dbg_do: out std_logic_vector(32-1 downto 0)
);
end component;
component opdec is
port (
opcode_low: in std_logic_vector(15 downto 0);
opcode_high: in std_logic_vector(15 downto 0);
dec: out opdec_type
);
end component;
component taint is
generic (
COUNT: integer := 16
);
port (
clk: in std_logic;
rst: in std_logic;
req1_en: in std_logic;
req1_r: in regaddress_type;
req2_en: in std_logic;
req2_r: in regaddress_type;
ready: out std_logic;
set_en: in std_logic;
set_r: in regaddress_type;
clr_en: in std_logic;
clr_r: in regaddress_type;
taint: out std_logic_vector(COUNT-1 downto 0)
);
end component;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_syscon: in wb_syscon_type;
-- Master
m_wbi: in wb_mosi_type;
m_wbo: out wb_miso_type;
-- Slave signals
s0_wbo: out wb_mosi_type;
s0_wbi: in wb_miso_type;
s1_wbo: out wb_mosi_type;
s1_wbi: in wb_miso_type
);
end component;
component xtc_wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_syscon: in wb_syscon_type;
-- Master
m_wbi: in wb_mosi_type;
m_wbo: out wb_miso_type;
-- Slave signals
s0_wbo: out wb_mosi_type;
s0_wbi: in wb_miso_type;
s1_wbo: out wb_mosi_type;
s1_wbi: in wb_miso_type
);
end component;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := 31;
ADDRESS_LOW: integer := 0
);
port (
wb_syscon: in wb_syscon_type;
-- Master 0 signals
m0_wbi: in wb_mosi_type;
m0_wbo: out wb_miso_type;
-- Master 1 signals
m1_wbi: in wb_mosi_type;
m1_wbo: out wb_miso_type;
-- Slave signals
s0_wbi: in wb_miso_type;
s0_wbo: out wb_mosi_type
);
end component;
component wb_master_p_to_slave_np is
port (
syscon: in wb_syscon_type;
-- Master signals
mwbi: in wb_mosi_type;
mwbo: out wb_miso_type;
-- Slave signals
swbi: in wb_miso_type;
swbo: out wb_mosi_type
);
end component;
component xtc_top_bram is
port (
wb_syscon: in wb_syscon_type;
-- IO wishbone interface
iowbo: out wb_mosi_type;
iowbi: in wb_miso_type
);
end component;
component xtc_top_sdram is
port (
wb_syscon: in wb_syscon_type;
-- IO wishbone interface
iowbo: out wb_mosi_type;
iowbi: in wb_miso_type;
-- DMA
dmawbi: in wb_mosi_type;
dmawbo: out wb_miso_type;
nmi: in std_logic;
nmiack: out std_logic;
rstreq: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end component;
component regbank_5p is
generic (
ADDRESS_BITS: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_en: in std_logic;
rb2_rd: out std_logic_vector(31 downto 0);
rb3_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb3_en: in std_logic;
rb3_rd: out std_logic_vector(31 downto 0);
rb4_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb4_en: in std_logic;
rb4_rd: out std_logic_vector(31 downto 0);
rbw_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rbw_wr: in std_logic_vector(31 downto 0);
rbw_we: in std_logic;
rbw_en: in std_logic;
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
dbg_do: out std_logic_vector(32-1 downto 0)
);
end component regbank_5p;
component regbank_4r_2w is
generic (
ADDRESS_BITS: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_en: in std_logic;
rb2_rd: out std_logic_vector(31 downto 0);
rb3_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb3_en: in std_logic;
rb3_rd: out std_logic_vector(31 downto 0);
rb4_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb4_en: in std_logic;
rb4_rd: out std_logic_vector(31 downto 0);
rbw1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rbw1_wr: in std_logic_vector(31 downto 0);
rbw1_we: in std_logic;
rbw1_en: in std_logic;
rbw2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rbw2_wr: in std_logic_vector(31 downto 0);
rbw2_we: in std_logic;
rbw2_en: in std_logic;
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
dbg_do: out std_logic_vector(32-1 downto 0)
);
end component;
component insnqueue is
port (
rst: in std_logic;
clkw: in std_logic;
din: in std_logic_vector(15 downto 0);
en: in std_logic;
clr: in std_logic;
full: out std_logic;
clkr: in std_logic;
pop: in std_logic;
dualpop: in std_logic;
dout0: out std_logic_vector(15 downto 0);
dout1: out std_logic_vector(15 downto 0);
empty: out std_logic;
dvalid: out std_logic
);
end component;
component xtc_ioctrl is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type;
-- Slaves
swbi: in slot_wbi;
swbo: out slot_wbo;
sids: in slot_ids
);
end component xtc_ioctrl;
component mmu is
generic (
TLB_ENTRY_BITS: natural := 3;
CONTEXT_SIZE_BITS: natural := 6;
SIMPLIFIED: boolean := true
);
port (
clk: in std_logic;
rst: in std_logic;
addr: in std_logic_vector(31 downto 0);
ctx: in std_logic_vector(CONTEXT_SIZE_BITS-1 downto 0);
en: in std_logic;
tlbw: in std_logic;
tlba: in std_logic_vector(TLB_ENTRY_BITS-1 downto 0);
tlbv: in tlb_entry_type;
paddr: out std_logic_vector(31 downto 0);
valid: out std_logic;
pw: out std_logic; -- Write permission
pr: out std_logic; -- Read permission
px: out std_logic; -- eXecute permission
ps: out std_logic -- Supervisor/User
);
end component;
component dcache is
generic (
ADDRESS_HIGH: integer := 31;
CACHE_MAX_BITS: integer := 13; -- 8 Kb
CACHE_LINE_SIZE_BITS: integer := 6 -- 64 bytes
);
port (
syscon: in wb_syscon_type;
ci: in dcache_in_type;
co: out dcache_out_type;
mwbi: in wb_miso_type;
mwbo: out wb_mosi_type
);
end component;
component generic_dp_ram_rf is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(data_bits-1 downto 0);
dob: out std_logic_vector(data_bits-1 downto 0)
);
end component;
component nodev is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type
);
end component;
component sinkdev is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type
);
end component;
end package;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3044.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b02x00p02n03i03044ent IS
END c12s02b02x00p02n03i03044ent;
ARCHITECTURE c12s02b02x00p02n03i03044arch OF c12s02b02x00p02n03i03044ent IS
BEGIN
bl1: block
generic (i1:integer; i2:integer; i3:integer; i4:integer);
generic map(3, -5, 6, -4);
begin
assert (i1=3)
report "Generic association for first element I1 incorrect"
severity failure;
assert (i2=-5)
report "Generic association for second element I2 incorrect"
severity failure;
assert (i3=6)
report "Generic association for third element I3 incorrect"
severity failure;
assert (i4=-4)
report "Generic association for fourth element I4 incorrect"
severity failure;
assert NOT( i1=3 and i2=-5 and i3=6 and i4=-4 )
report "***PASSED TEST: c12s02b02x00p02n03i03044"
severity NOTE;
assert ( i1=3 and i2=-5 and i3=6 and i4=-4 )
report "***FAILED TEST: c12s02b02x00p02n03i03044 - Positional association of generics creates constants without the correct values."
severity ERROR;
end block;
END c12s02b02x00p02n03i03044arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3044.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b02x00p02n03i03044ent IS
END c12s02b02x00p02n03i03044ent;
ARCHITECTURE c12s02b02x00p02n03i03044arch OF c12s02b02x00p02n03i03044ent IS
BEGIN
bl1: block
generic (i1:integer; i2:integer; i3:integer; i4:integer);
generic map(3, -5, 6, -4);
begin
assert (i1=3)
report "Generic association for first element I1 incorrect"
severity failure;
assert (i2=-5)
report "Generic association for second element I2 incorrect"
severity failure;
assert (i3=6)
report "Generic association for third element I3 incorrect"
severity failure;
assert (i4=-4)
report "Generic association for fourth element I4 incorrect"
severity failure;
assert NOT( i1=3 and i2=-5 and i3=6 and i4=-4 )
report "***PASSED TEST: c12s02b02x00p02n03i03044"
severity NOTE;
assert ( i1=3 and i2=-5 and i3=6 and i4=-4 )
report "***FAILED TEST: c12s02b02x00p02n03i03044 - Positional association of generics creates constants without the correct values."
severity ERROR;
end block;
END c12s02b02x00p02n03i03044arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3044.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b02x00p02n03i03044ent IS
END c12s02b02x00p02n03i03044ent;
ARCHITECTURE c12s02b02x00p02n03i03044arch OF c12s02b02x00p02n03i03044ent IS
BEGIN
bl1: block
generic (i1:integer; i2:integer; i3:integer; i4:integer);
generic map(3, -5, 6, -4);
begin
assert (i1=3)
report "Generic association for first element I1 incorrect"
severity failure;
assert (i2=-5)
report "Generic association for second element I2 incorrect"
severity failure;
assert (i3=6)
report "Generic association for third element I3 incorrect"
severity failure;
assert (i4=-4)
report "Generic association for fourth element I4 incorrect"
severity failure;
assert NOT( i1=3 and i2=-5 and i3=6 and i4=-4 )
report "***PASSED TEST: c12s02b02x00p02n03i03044"
severity NOTE;
assert ( i1=3 and i2=-5 and i3=6 and i4=-4 )
report "***FAILED TEST: c12s02b02x00p02n03i03044 - Positional association of generics creates constants without the correct values."
severity ERROR;
end block;
END c12s02b02x00p02n03i03044arch;
|
-- $RCSfile: mult_gen_v11_2_xst_comp.vhd,v $ $Revision: 1.4 $ $Date: 2010/03/19 10:56:59 $
--------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mult_gen_v11_2_xst_comp is
component mult_gen_v11_2_xst is
generic (
C_VERBOSITY : integer := 0;
C_MODEL_TYPE : integer := 0;
C_XDEVICEFAMILY : string := "virtex4";
C_A_WIDTH : integer := 18;
C_A_TYPE : integer := 0;
C_B_WIDTH : integer := 18;
C_B_TYPE : integer := 0;
C_OUT_HIGH : integer := 35;
C_OUT_LOW : integer := 0;
C_MULT_TYPE : integer := 1;
C_OPTIMIZE_GOAL : integer := 1;
C_HAS_CE : integer := 0;
C_HAS_SCLR : integer := 0;
C_CE_OVERRIDES_SCLR : integer := 1;
C_LATENCY : integer := -1;
C_CCM_IMP : integer := 0;
C_B_VALUE : string := "111111111111111111";
C_HAS_ZERO_DETECT : integer := 0;
C_ROUND_OUTPUT : integer := 0;
C_ROUND_PT : integer := 0);
port (
CLK : in std_logic := '1';
A : in std_logic_vector(C_A_WIDTH-1 downto 0) := (others => '0');
B : in std_logic_vector(C_B_WIDTH-1 downto 0) := (others => '0');
CE : in std_logic := '1';
SCLR : in std_logic := '0';
ZERO_DETECT : out std_logic_vector(1 downto 0) := (others => '0');
P : out std_logic_vector(C_OUT_HIGH-C_OUT_LOW downto 0) := (others => '0');
PCASC : out std_logic_vector(47 downto 0) := (others => '0'));
end component;
end mult_gen_v11_2_xst_comp;
|
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rpm_counter_tb is
generic
(
BITS_N : natural := 20;
MIN_RPM_LIM : natural := 2**18;
TEST_RPM : natural := 2**16
);
end entity;
architecture rtl of rpm_counter_tb is
-- Main clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
signal clk : std_logic := '0';
signal reset : std_logic;
signal rpm : std_logic;
signal fault : std_logic;
begin
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
DUT_inst: entity work.rpm_counter(rtl)
generic map
(
BITS_N => BITS_N,
MIN_RPM_LIM => 2**18,
DEBOUNCE_D => 10000
)
port map
(
clk => clk,
reset => reset,
rpm_in => rpm,
fault_out => fault
);
rpm_gen: process(clk, reset)
variable counter : unsigned(BITS_N - 1 downto 0);
variable start_done : boolean;
begin
if reset = '1' then
counter := (others => '0');
rpm <= '1';
start_done := false;
elsif rising_edge(clk) then
if start_done then
counter := counter + 1;
-- Wait until we get fault indication for no RPM
elsif fault = '1' then
start_done := true;
end if;
if counter > TEST_RPM then
rpm <= not rpm;
counter := (others => '0');
end if;
end if;
end process;
end;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_b_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_b_e-c.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_shadow_b_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_shadow_b_rtl_conf / inst_shadow_b_e
--
configuration inst_shadow_b_rtl_conf of inst_shadow_b_e is
for rtl
-- Generated Configuration
end for;
end inst_shadow_b_rtl_conf;
--
-- End of Generated Configuration inst_shadow_b_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sadd23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sadd23;
architecture rtl of sadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sadd23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sadd23;
architecture rtl of sadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sadd23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sadd23;
architecture rtl of sadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sadd23 is
port (
a_i : in signed (22 downto 0);
b_i : in signed (22 downto 0);
c_o : out signed (22 downto 0)
);
end entity sadd23;
architecture rtl of sadd23 is
begin
c_o <= a_i + b_i;
end architecture rtl;
|
library verilog;
use verilog.vl_types.all;
entity flag is
port(
busOut : in vl_logic_vector(31 downto 0);
busA : in vl_logic_vector(31 downto 0);
busB : in vl_logic_vector(31 downto 0);
carryOut : in vl_logic;
z : out vl_logic;
o : out vl_logic;
c : out vl_logic;
n : out vl_logic
);
end flag;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
--signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
--signal reg5, reg5_next : std_logic_vector(0 to 31);
--signal reg6, reg6_next : std_logic_vector(0 to 31);
--signal reg7, reg7_next : std_logic_vector(0 to 31);
--signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
--retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
--reg5 <= reg5_next;
--reg6 <= reg6_next;
--reg7 <= reg7_next;
--reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
--retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
--reg5_next <= reg5;
--reg6_next <= reg6;
--reg7_next <= reg7;
--reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: cond_init_stress_1
-- reg1 = numberOfTestsToComplete
-- reg2 = * numberOfTestsCompleted
-- reg3 = * completedMutex
-- reg4 = * condvar
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Read the value of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg1_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of completedMutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg3_next <= intrfc2thrd_value;
next_state <= STATE_6;
-- while( *(data->numberOfTestsCompleted) < *(data->numberOfTestsToComplete) )
when STATE_6 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- Do the comparision between completed and toBeCompleted
if ( intrfc2thrd_value < reg1 ) then
next_state <= STATE_8;
else
next_state <= FUNCTION_EXIT;
end if;
-- condvar = (hthread_cond_t *) malloc( sizeof( hthread_cond_t ) );
when STATE_8 =>
-- push 4B, the size of a hthread_cond_t
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- call malloc
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_MALLOC;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_10;
next_state <= WAIT_STATE;
-- if ( condvar == NULL ) thread_exit_WITHERROR( NULL );
when STATE_10 =>
reg4_next <= intrfc2thrd_value;
case intrfc2thrd_value is
when x"00000000" =>
-- push null and call exit
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when others =>
next_state <= STATE_12;
end case;
when STATE_11 =>
-- Call exit with error
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT_ERROR;
thrd2intrfc_value <= Z32;
-- hthread_cond_init( condvar, NULL );
when STATE_12 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_14;
when STATE_14 =>
-- call COND_INIT
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_15;
next_state <= WAIT_STATE;
-- hthread_cond_signal( condvar );
when STATE_15 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
when STATE_16 =>
-- call COND_SIGNAL
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_17;
next_state <= WAIT_STATE;
-- hthread_cond_destroy( condvar );
when STATE_17 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
-- call hthread_cond_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_19;
next_state <= WAIT_STATE;
-- free( condvar );
when STATE_19 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_20;
when STATE_20 =>
-- call free
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_FREE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_21;
next_state <= WAIT_STATE;
-- hthread_mutex_lock( data->completedMutex );
when STATE_21 =>
-- push data->completedMutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_22;
when STATE_22 =>
-- call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_23;
next_state <= WAIT_STATE;
-- *( data->numberOfTestsCompleted) += 1;
when STATE_23 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_24;
when STATE_24 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= reg2;
thrd2intrfc_value <= intrfc2thrd_value + x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_25;
-- hthread_mutex_unlock( data->completedMutex );
when STATE_25 =>
-- push data->completedMutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_26;
when STATE_26 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
use work.vvc_cmd_pkg.all;
use work.vvc_methods_pkg.all;
use work.td_vvc_framework_common_methods_pkg.all;
use work.td_target_support_pkg.all;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package td_vvc_entity_support_pkg is
type t_vvc_labels is record
scope : string(1 to C_LOG_SCOPE_WIDTH);
vvc_name : string(1 to C_LOG_SCOPE_WIDTH-2);
instance_idx : natural;
channel : t_channel;
end record;
-------------------------------------------
-- assign_vvc_labels
-------------------------------------------
-- This function puts common VVC labels into a record - to reduce the number of procedure parameters
function assign_vvc_labels(
scope : string;
vvc_name : string;
instance_idx : integer;
channel : t_channel
) return t_vvc_labels;
-------------------------------------------
-- format_msg
-------------------------------------------
-- Generates a sting containing the command message and index
-- - Format: Message [index]
impure function format_msg(
command : t_vvc_cmd_record
) return string;
-------------------------------------------
-- vvc_constructor
-------------------------------------------
-- Procedure used as concurrent process in the VVCs
-- - Sets up the vvc_config, command queue and result_queue
-- - Verifies that UVVM has been initialized
procedure vvc_constructor(
constant scope : in string;
constant instance_idx : in natural;
variable vvc_config : inout t_vvc_config;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
variable result_queue : inout work.td_result_queue_pkg.t_generic_queue;
constant bfm_config : in t_bfm_config;
constant cmd_queue_count_max : in natural;
constant cmd_queue_count_threshold : in natural;
constant cmd_queue_count_threshold_severity : in t_alert_level;
constant result_queue_count_max : in natural;
constant result_queue_count_threshold : in natural;
constant result_queue_count_threshold_severity : in t_alert_level
);
-------------------------------------------
-- initialize_interpreter
-------------------------------------------
-- Initialises the VVC interpreter
-- - Clears terminate_current_cmd.set to '0'
procedure initialize_interpreter (
signal terminate_current_cmd : out t_flag_record;
signal global_awaiting_completion : out std_logic_vector(C_MAX_NUM_SEQUENCERS-1 downto 0)
);
-------------------------------------------
-- await_cmd_from_sequencer
-------------------------------------------
-- Waits for a command from the central sequencer. Continues on matching VVC, Instance, Name and Channel (unless channel = NA)
-- - Log at start using ID_CMD_INTERPRETER_WAIT and at the end using ID_CMD_INTERPRETER
procedure await_cmd_from_sequencer(
constant vvc_labels : in t_vvc_labels;
constant vvc_config : in t_vvc_config;
signal VVCT : in t_vvc_target_record;
signal VVC_BROADCAST : inout std_logic;
signal global_vvc_busy : inout std_logic;
signal vvc_ack : out std_logic;
constant shared_vvc_cmd : in t_vvc_cmd_record;
variable output_vvc_cmd : out t_vvc_cmd_record
);
-------------------------------------------
-- put_command_on_queue
-------------------------------------------
-- Puts the received command (by Interpreter) on the VVC queue (for later retrieval by Executor)
procedure put_command_on_queue(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
variable vvc_status : inout t_vvc_status;
signal queue_is_increasing : out boolean
);
-------------------------------------------
-- interpreter_await_completion
-------------------------------------------
-- Immediate command: await_completion (in interpreter)
-- - Command description in Quick reference for UVVM common methods
-- - Will wait until given command(s) is completed by the excutor (if not already completed)
-- - Log using ID_IMMEDIATE_CMD when await completed
-- - Log using ID_IMMEDIATE_CMD_WAIT if waiting is actually needed
procedure interpreter_await_completion(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
signal executor_is_busy : in boolean;
constant vvc_labels : in t_vvc_labels;
signal last_cmd_idx_executed : in natural;
constant await_completion_pending_msg_id : in t_msg_id := ID_IMMEDIATE_CMD_WAIT;
constant await_completion_finished_msg_id : in t_msg_id := ID_IMMEDIATE_CMD
);
-------------------------------------------
-- interpreter_await_any_completion
-------------------------------------------
-- Immediate command: await_any_completion() (in interpreter)
-- - This procedure is called by the interpreter if sequencer calls await_any_completion()
-- - It waits for the first of the following :
-- 'await_completion' of this VVC, or
-- until global_awaiting_completion(idx) /= '1' (any of the other involved VVCs completed).
-- - Refer to description in Quick reference for UVVM common methods
-- - Log using ID_IMMEDIATE_CMD when the wait completed
-- - Log using ID_IMMEDIATE_CMD_WAIT if waiting is actually needed
procedure interpreter_await_any_completion(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
signal executor_is_busy : in boolean;
constant vvc_labels : in t_vvc_labels;
signal last_cmd_idx_executed : in natural;
signal global_awaiting_completion : inout std_logic_vector; -- Handshake with other VVCs performing await_any_completion
constant await_completion_pending_msg_id : in t_msg_id := ID_IMMEDIATE_CMD_WAIT;
constant await_completion_finished_msg_id : in t_msg_id := ID_IMMEDIATE_CMD
);
-------------------------------------------
-- interpreter_flush_command_queue
-------------------------------------------
-- Immediate command: flush_command_queue (in interpreter)
-- - Command description in Quick reference for UVVM common methods
-- - Log using ID_IMMEDIATE_CMD
procedure interpreter_flush_command_queue(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
variable vvc_status : inout t_vvc_status;
constant vvc_labels : in t_vvc_labels
);
-------------------------------------------
-- interpreter_terminate_current_command
-------------------------------------------
-- Immediate command: terminate_current_command (in interpreter)
-- - Command description in Quick reference for UVVM common methods
-- - Log using ID_IMMEDIATE_CMD
procedure interpreter_terminate_current_command(
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant vvc_labels : in t_vvc_labels;
signal terminate_current_cmd : inout t_flag_record
);
-------------------------------------------
-- interpreter_fetch_result
-------------------------------------------
-- Immediate command: interpreter_fetch_result (in interpreter)
-- - Command description in Quick reference for UVVM common methods
-- - Log using ID_IMMEDIATE_CMD
-- t_vvc_response is specific to each VVC,
-- so the BFM can return any type which is then transported from the VVC to the sequencer via a fetch_result() call
procedure interpreter_fetch_result(
variable result_queue : inout work.td_result_queue_pkg.t_generic_queue;
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant vvc_labels : in t_vvc_labels;
constant last_cmd_idx_executed : in natural;
variable shared_vvc_response : inout work.vvc_cmd_pkg.t_vvc_response
);
-------------------------------------------
-- initialize_executor
-------------------------------------------
-- Initialises the VVC executor
-- - Resets terminate_current_cmd.reset flag
procedure initialize_executor (
signal terminate_current_cmd : inout t_flag_record
);
-------------------------------------------
-- fetch_command_and_prepare_executor
-------------------------------------------
-- Fetches a command from the queue (waits until available if needed)
-- - Log command using ID_CMD_EXECUTOR
-- - Log using ID_CMD_EXECUTOR_WAIT if queue is empty
-- - Sets relevant flags
procedure fetch_command_and_prepare_executor(
variable command : inout t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
variable vvc_status : inout t_vvc_status;
signal queue_is_increasing : in boolean;
signal executor_is_busy : inout boolean;
constant vvc_labels : in t_vvc_labels
);
-------------------------------------------
-- store_result
-------------------------------------------
-- Store result from BFM in the VVC's result_queue
-- The result_queue is used to store a generic type that is returned from
-- a read/expect BFM procedure.
-- It can be fetched later using fetch_result() to return it from the VVC to sequencer
procedure store_result(
variable result_queue : inout work.td_result_queue_pkg.t_generic_queue;
constant cmd_idx : in natural;
constant result : in t_vvc_result
);
-------------------------------------------
-- insert_inter_bfm_delay_if_requested
-------------------------------------------
-- Inserts delay of either START2START or FINISH2START in time, given that
-- - vvc_config inter-bfm delay type is not set to NO_DELAY
-- - command_is_bfm_access is set to true
-- - Both timestamps are not set to 0 ns.
-- A log message with ID ID_CMD_EXECUTOR is issued when the delay begins and
-- when it has finished delaying.
procedure insert_inter_bfm_delay_if_requested(
constant vvc_config : in t_vvc_config;
constant command_is_bfm_access : in boolean;
constant timestamp_start_of_last_bfm_access : in time;
constant timestamp_end_of_last_bfm_access : in time;
constant scope : in string := C_SCOPE
);
function broadcast_cmd_to_shared_cmd (
constant broadcast_cmd : t_broadcastable_cmd
) return t_operation;
function get_command_type_from_operation (
constant broadcast_cmd : t_broadcastable_cmd
) return t_immediate_or_queued;
procedure populate_shared_vvc_cmd_with_broadcast (
variable output_vvc_cmd : out t_vvc_cmd_record
);
end package td_vvc_entity_support_pkg;
package body td_vvc_entity_support_pkg is
function assign_vvc_labels(
scope : string;
vvc_name : string;
instance_idx : integer;
channel : t_channel
) return t_vvc_labels is
variable vvc_labels : t_vvc_labels;
begin
vvc_labels.scope := pad_string(scope, NUL, vvc_labels.scope'length);
vvc_labels.vvc_name := pad_string(vvc_name, NUL, vvc_labels.vvc_name'length);
vvc_labels.instance_idx := instance_idx;
vvc_labels.channel := channel;
return vvc_labels;
end;
impure function format_msg(
command : t_vvc_cmd_record
) return string is
begin
return add_msg_delimiter(to_string(command.msg)) & " " & format_command_idx(command);
end;
procedure vvc_constructor(
constant scope : in string;
constant instance_idx : in natural;
variable vvc_config : inout t_vvc_config;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
variable result_queue : inout work.td_result_queue_pkg.t_generic_queue;
constant bfm_config : in t_bfm_config;
constant cmd_queue_count_max : in natural;
constant cmd_queue_count_threshold : in natural;
constant cmd_queue_count_threshold_severity : in t_alert_level;
constant result_queue_count_max : in natural;
constant result_queue_count_threshold : in natural;
constant result_queue_count_threshold_severity : in t_alert_level
) is
variable v_delta_cycle_counter : natural := 0;
begin
check_value(instance_idx <= C_MAX_VVC_INSTANCE_NUM, TB_FAILURE, "Generic VVC Instance index =" & to_string(instance_idx) &
" cannot exceed C_MAX_VVC_INSTANCE_NUM in UVVM adaptations = " & to_string(C_MAX_VVC_INSTANCE_NUM), C_SCOPE, ID_NEVER);
vvc_config.bfm_config := bfm_config;
vvc_config.cmd_queue_count_max := cmd_queue_count_max;
vvc_config.cmd_queue_count_threshold := cmd_queue_count_threshold;
vvc_config.cmd_queue_count_threshold_severity := cmd_queue_count_threshold_severity;
vvc_config.result_queue_count_max := result_queue_count_max;
vvc_config.result_queue_count_threshold := result_queue_count_threshold;
vvc_config.result_queue_count_threshold_severity := result_queue_count_threshold_severity;
log(ID_CONSTRUCTOR, "VVC instantiated.", scope, vvc_config.msg_id_panel);
command_queue.set_scope(scope & ":cmd_queue");
command_queue.set_queue_count_max(cmd_queue_count_max);
command_queue.set_queue_count_threshold(cmd_queue_count_threshold);
command_queue.set_queue_count_threshold_severity(cmd_queue_count_threshold_severity);
log(ID_CONSTRUCTOR_SUB, "Command queue instantiated with size " & to_string(command_queue.get_queue_count_max(VOID)), command_queue.get_scope(VOID), vvc_config.msg_id_panel);
result_queue.set_scope(scope & ":result_queue");
result_queue.set_queue_count_max(result_queue_count_max);
result_queue.set_queue_count_threshold(result_queue_count_threshold);
result_queue.set_queue_count_threshold_severity(result_queue_count_threshold_severity);
log(ID_CONSTRUCTOR_SUB, "Result queue instantiated with size " & to_string(result_queue.get_queue_count_max(VOID)), result_queue.get_scope(VOID), vvc_config.msg_id_panel);
if shared_uvvm_state /= PHASE_A then
loop
wait for 0 ns;
v_delta_cycle_counter := v_delta_cycle_counter + 1;
exit when shared_uvvm_state = PHASE_A;
check_value((shared_uvvm_state /= IDLE), TB_FAILURE, "UVVM will not work without intitalize_uvvm instantiated as a concurrent procedure in the test harness", scope);
end loop;
end if;
wait; -- show message only once per VVC instance
end procedure;
procedure initialize_interpreter (
signal terminate_current_cmd : out t_flag_record;
signal global_awaiting_completion : out std_logic_vector(C_MAX_NUM_SEQUENCERS-1 downto 0)
) is
begin
terminate_current_cmd <= (set => '0', reset => 'Z', is_active => 'Z'); -- Initialise to avoid undefineds. This process is driving param 1 only.
wait for 0 ns; -- delay by 1 delta cycle to allow constructor to finish first
global_awaiting_completion <= (others => 'Z'); -- Avoid driving until the VVC is involved in await_any_completion()
end procedure;
function broadcast_cmd_to_shared_cmd (
constant broadcast_cmd : t_broadcastable_cmd
) return t_operation is
begin
case broadcast_cmd is
when AWAIT_COMPLETION => return AWAIT_COMPLETION;
when ENABLE_LOG_MSG => return ENABLE_LOG_MSG;
when DISABLE_LOG_MSG => return DISABLE_LOG_MSG;
when FLUSH_COMMAND_QUEUE => return FLUSH_COMMAND_QUEUE;
when INSERT_DELAY => return INSERT_DELAY;
when TERMINATE_CURRENT_COMMAND => return TERMINATE_CURRENT_COMMAND;
when others => return NO_OPERATION;
end case;
end function;
function get_command_type_from_operation (
constant broadcast_cmd : t_broadcastable_cmd
) return t_immediate_or_queued is
begin
case broadcast_cmd is
when AWAIT_COMPLETION => return IMMEDIATE;
when ENABLE_LOG_MSG => return IMMEDIATE;
when DISABLE_LOG_MSG => return IMMEDIATE;
when FLUSH_COMMAND_QUEUE => return IMMEDIATE;
when TERMINATE_CURRENT_COMMAND => return IMMEDIATE;
when INSERT_DELAY => return QUEUED;
when others => return NO_command_type;
end case;
end function;
procedure populate_shared_vvc_cmd_with_broadcast (
variable output_vvc_cmd : out t_vvc_cmd_record
) is
begin
-- Increment the shared command index. This is normally done in the CDM, but for broadcast commands it is done by the VVC itself.
check_value((shared_uvvm_state /= IDLE), TB_FAILURE, "UVVM will not work without uvvm_vvc_framework.ti_uvvm_engine instantiated in the test harness", C_SCOPE, ID_NEVER);
await_semaphore_in_delta_cycles(protected_broadcast_semaphore);
shared_cmd_idx := shared_cmd_idx + 1;
-- Populate the shared VVC command record
output_vvc_cmd.operation := broadcast_cmd_to_shared_cmd(shared_vvc_broadcast_cmd.operation);
output_vvc_cmd.msg_id := shared_vvc_broadcast_cmd.msg_id;
output_vvc_cmd.msg := shared_vvc_broadcast_cmd.msg;
output_vvc_cmd.quietness := shared_vvc_broadcast_cmd.quietness;
output_vvc_cmd.delay := shared_vvc_broadcast_cmd.delay;
output_vvc_cmd.timeout := shared_vvc_broadcast_cmd.timeout;
output_vvc_cmd.gen_integer_array(0) := shared_vvc_broadcast_cmd.gen_integer;
output_vvc_cmd.proc_call := shared_vvc_broadcast_cmd.proc_call;
output_vvc_cmd.cmd_idx := shared_cmd_idx;
output_vvc_cmd.command_type := get_command_type_from_operation(shared_vvc_broadcast_cmd.operation);
if global_show_msg_for_uvvm_cmd then
log(ID_UVVM_SEND_CMD, to_string(shared_vvc_cmd.proc_call) & ": " & add_msg_delimiter(to_string(shared_vvc_cmd.msg)) & "."
& format_command_idx(shared_cmd_idx), C_SCOPE);
else
log(ID_UVVM_SEND_CMD, to_string(shared_vvc_cmd.proc_call)
& format_command_idx(shared_cmd_idx), C_SCOPE);
end if;
release_semaphore(protected_broadcast_semaphore);
end procedure;
procedure await_cmd_from_sequencer(
constant vvc_labels : in t_vvc_labels;
constant vvc_config : in t_vvc_config;
signal VVCT : in t_vvc_target_record;
signal VVC_BROADCAST : inout std_logic;
signal global_vvc_busy : inout std_logic;
signal vvc_ack : out std_logic;
constant shared_vvc_cmd : in t_vvc_cmd_record;
variable output_vvc_cmd : out t_vvc_cmd_record
) is
variable v_was_broadcast : boolean := false;
begin
vvc_ack <= 'Z'; -- Do not contribute to the acknowledge unless selected
-- Wait for a new command
log(ID_CMD_INTERPRETER_WAIT, "Interpreter: Waiting for command", to_string(vvc_labels.scope) , vvc_config.msg_id_panel);
loop
VVC_BROADCAST <= 'Z';
global_vvc_busy <= 'L';
wait until (VVCT.trigger = '1' or VVC_BROADCAST = '1');
if VVC_BROADCAST'event and VVC_BROADCAST = '1' then
v_was_broadcast := true;
VVC_BROADCAST <= '1';
populate_shared_vvc_cmd_with_broadcast(output_vvc_cmd);
else
-- set VVC_BROADCAST to 0 to force a broadcast to wait for that VVC
VVC_BROADCAST <= '0';
global_vvc_busy <= '1';
-- copy shared_vvc_cmd to release the semaphore
output_vvc_cmd := shared_vvc_cmd;
end if;
-- Check that the channel is valid
if (not v_was_broadcast) then
if (VVCT.vvc_instance_idx = vvc_labels.instance_idx and
VVCT.vvc_name(1 to valid_length(vvc_labels.vvc_name)) = vvc_labels.vvc_name(1 to valid_length(vvc_labels.vvc_name))) then
if ((VVCT.vvc_channel = NA and vvc_labels.channel /= NA) or
(vvc_labels.channel = NA and (VVCT.vvc_channel /= NA and VVCT.vvc_channel /= ALL_CHANNELS))) then
tb_warning(to_string(output_vvc_cmd.proc_call) & " Channel "& to_string(VVCT.vvc_channel) & " not supported on this VVC " & format_command_idx(output_vvc_cmd), to_string(vvc_labels.scope));
-- only release semaphore and stay in loop forcing a timeout too
release_semaphore(protected_semaphore);
end if;
end if;
end if;
exit when (v_was_broadcast or -- Broadcast, or
(((VVCT.vvc_instance_idx = vvc_labels.instance_idx) or (VVCT.vvc_instance_idx = C_VVCT_ALL_INSTANCES)) and -- Index is correct or broadcast index
((VVCT.vvc_channel = ALL_CHANNELS) or (VVCT.vvc_channel = vvc_labels.channel)) and -- Channel is correct or broadcast channel
VVCT.vvc_name(1 to valid_length(vvc_labels.vvc_name)) = vvc_labels.vvc_name(1 to valid_length(vvc_labels.vvc_name)))); -- Name is correct
end loop;
if ((VVCT.vvc_instance_idx = C_VVCT_ALL_INSTANCES) or (VVCT.vvc_channel = ALL_CHANNELS) ) then
-- in case of a multicast block the global acknowledge until all vvc receiving the message processed it
vvc_ack <= '0';
end if;
wait for 0 ns;
if not v_was_broadcast then
-- release the semaphore if it was not a broadcast
release_semaphore(protected_semaphore);
end if;
log(ID_CMD_INTERPRETER, to_string(output_vvc_cmd.proc_call) & ". Command received " & format_command_idx(output_vvc_cmd), vvc_labels.scope, vvc_config.msg_id_panel); -- Get and ack the new command
end procedure;
procedure put_command_on_queue(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
variable vvc_status : inout t_vvc_status;
signal queue_is_increasing : out boolean
) is
begin
command_queue.put(command);
vvc_status.pending_cmd_cnt := command_queue.get_count(VOID);
queue_is_increasing <= true;
wait for 0 ns;
queue_is_increasing <= false;
end procedure;
procedure interpreter_await_completion(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
signal executor_is_busy : in boolean;
constant vvc_labels : in t_vvc_labels;
signal last_cmd_idx_executed : in natural;
constant await_completion_pending_msg_id : in t_msg_id := ID_IMMEDIATE_CMD_WAIT;
constant await_completion_finished_msg_id : in t_msg_id := ID_IMMEDIATE_CMD
) is
alias wanted_idx : integer is command.gen_integer_array(0); -- generic integer used as wanted command idx to wait for
begin
if wanted_idx = -1 then
-- await completion of all commands
if command_queue.is_not_empty(VOID) or executor_is_busy then
log(await_completion_pending_msg_id, "await_completion() - Pending completion " & to_string(command.msg) & " " & format_command_idx(command), to_string(vvc_labels.scope), vvc_config.msg_id_panel); -- Get and ack the new command
loop
if command.timeout = 0 ns then
wait until executor_is_busy = false;
else
wait until (executor_is_busy = false) for command.timeout;
end if;
if command_queue.is_empty(VOID) or not executor_is_busy'event then
exit;
end if;
end loop;
end if;
log(await_completion_finished_msg_id, "await_completion() => Finished. " & to_string(command.msg) & " " & format_command_idx(command), to_string(vvc_labels.scope), vvc_config.msg_id_panel); -- Get and ack the new command
else -- await specific instruction
if last_cmd_idx_executed < wanted_idx then
log(await_completion_pending_msg_id, "await_completion(" & to_string(wanted_idx) & ") - Pending selected " & to_string(command.msg) & " " & format_command_idx(command), to_string(vvc_labels.scope), vvc_config.msg_id_panel); -- Get and ack the new command
loop
if command.timeout = 0 ns then
wait until executor_is_busy = false;
else
wait until executor_is_busy = false for command.timeout;
end if;
if last_cmd_idx_executed >= wanted_idx or not executor_is_busy'event then
exit;
end if;
end loop;
end if;
log(await_completion_finished_msg_id, "await_completion(" & to_string(wanted_idx) & ") => Finished. " & to_string(command.msg) & " " & format_command_idx(command), to_string(vvc_labels.scope), vvc_config.msg_id_panel); -- Get & ack the new command
end if;
end procedure;
------------------------------------------------------------------------------------------
-- Wait for any of the following :
-- await_completion of this VVC, or
-- until global_awaiting_completion /= '1' (any of the other involved VVCs completed).
------------------------------------------------------------------------------------------
procedure interpreter_await_any_completion(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
signal executor_is_busy : in boolean;
constant vvc_labels : in t_vvc_labels;
signal last_cmd_idx_executed : in natural;
signal global_awaiting_completion : inout std_logic_vector; -- Handshake from other VVCs performing await_any_completion
constant await_completion_pending_msg_id : in t_msg_id := ID_IMMEDIATE_CMD_WAIT;
constant await_completion_finished_msg_id : in t_msg_id := ID_IMMEDIATE_CMD
) is
alias wanted_idx : integer is command.gen_integer_array(0); -- generic integer used as wanted command idx to wait for
alias awaiting_completion_idx : integer is command.gen_integer_array(1); -- generic integer used as awaiting_completion_idx
variable v_done : boolean := false; -- Whether we're done waiting
-----------------------------------------------
-- Local function
-- Return whether if this VVC has completed
-----------------------------------------------
impure function this_vvc_completed (
dummy : t_void
) return boolean is
begin
if wanted_idx = -1 then
-- All commands must be completed (i.e. not just a selected command index)
return (executor_is_busy = false and command_queue.is_empty(VOID));
else
-- await a SPECIFIC command in this VVC
return (last_cmd_idx_executed >= wanted_idx);
end if;
end;
begin
--
-- Signal that this VVC is participating in the await_any_completion group by driving global_awaiting_completion
--
if not command.gen_boolean then -- NOT_LAST
-- If this is a NOT_LAST call: Wait for delta cycles until the LAST call sets it to '1',
-- then set it to '1' here.
-- Purpose of waiting : synchronize the LAST VVC with all the NOT_LAST VVCs, so that it doesn't have to wait a magic number of delta cycles
while global_awaiting_completion(awaiting_completion_idx) = 'Z' loop
wait for 0 ns;
end loop;
global_awaiting_completion(awaiting_completion_idx) <= '1';
else
-- If this is a LAST call: Set to '1' for at least one delta cycle, so that all NOT_LAST calls detects it.
global_awaiting_completion(awaiting_completion_idx) <= '1';
wait for 0 ns;
end if;
-- This VVC already completed?
if this_vvc_completed(VOID) then
v_done := true;
end if;
-- Any of the other involved VVCs already completed?
if (global_awaiting_completion(awaiting_completion_idx) = 'X' or global_awaiting_completion(awaiting_completion_idx) = '0') then
v_done := true;
end if;
if not v_done then
-- Start waiting for the first of this VVC or other VVC
log(await_completion_pending_msg_id, to_string(command.proc_call) & " - Pending completion " & to_string(command.msg) & " " & format_command_idx(command), to_string(vvc_labels.scope), vvc_config.msg_id_panel);
loop
wait until ((executor_is_busy = false) or (global_awaiting_completion(awaiting_completion_idx) /= '1')) for command.timeout;
if this_vvc_completed(VOID) or -- This VVC is done
global_awaiting_completion(awaiting_completion_idx) = '0' or -- All other involved VVCs are done
global_awaiting_completion(awaiting_completion_idx) = 'X' then -- Some other involved VVCs are done
exit;
end if;
if not ((executor_is_busy'event) or (global_awaiting_completion(awaiting_completion_idx) /= '1')) then -- Indicates timeout
-- When NOT_LAST (command.gen_boolean = false): Timeout must be reported here instead of in send_command_to_vvc()
-- becuase the command is always acknowledged immediately by the VVC to allow the sequencer to continue
if not command.gen_boolean then
tb_error("Timeout during " & to_string(command.proc_call) & "=> " & format_msg(command), to_string(vvc_labels.scope));
end if;
exit;
end if;
end loop;
end if;
global_awaiting_completion(awaiting_completion_idx) <= '0'; -- Signal that we're done waiting
-- Handshake : Wait until every involved VVC notice the value is 'X' or '0', and all agree to being done ('0')
if global_awaiting_completion(awaiting_completion_idx) /= '0' then
wait until (global_awaiting_completion(awaiting_completion_idx) = '0');
end if;
global_awaiting_completion(awaiting_completion_idx) <= 'Z'; -- Idle
log(await_completion_finished_msg_id, to_string(command.proc_call) & "=> Finished. " & format_msg(command), to_string(vvc_labels.scope), vvc_config.msg_id_panel); -- Get & ack the new command
end procedure;
procedure interpreter_flush_command_queue(
constant command : in t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
variable vvc_status : inout t_vvc_status;
constant vvc_labels : in t_vvc_labels
) is
begin
log(ID_IMMEDIATE_CMD, "Flushing command queue (" & to_string(shared_vvc_cmd.gen_integer_array(0)) & ") " & format_command_idx(shared_vvc_cmd), to_string(vvc_labels.scope), vvc_config.msg_id_panel);
command_queue.flush(VOID);
vvc_status.pending_cmd_cnt := command_queue.get_count(VOID);
end;
procedure interpreter_terminate_current_command(
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant vvc_labels : in t_vvc_labels;
signal terminate_current_cmd : inout t_flag_record
) is
begin
log(ID_IMMEDIATE_CMD, "Terminating command in executor", to_string(vvc_labels.scope), vvc_config.msg_id_panel);
set_flag(terminate_current_cmd);
end procedure;
procedure interpreter_fetch_result(
variable result_queue : inout work.td_result_queue_pkg.t_generic_queue;
constant command : in t_vvc_cmd_record;
constant vvc_config : in t_vvc_config;
constant vvc_labels : in t_vvc_labels;
constant last_cmd_idx_executed : in natural;
variable shared_vvc_response : inout work.vvc_cmd_pkg.t_vvc_response
) is
variable v_current_element : work.vvc_cmd_pkg.t_vvc_result_queue_element;
variable v_local_result_queue : work.td_result_queue_pkg.t_generic_queue;
begin
v_local_result_queue.set_scope(to_string(vvc_labels.scope));
shared_vvc_response.fetch_is_accepted := false; -- default
if last_cmd_idx_executed < command.gen_integer_array(0) then
tb_warning(to_string(command.proc_call) & ". Requested result is not yet available. " & format_command_idx(command), to_string(vvc_labels.scope));
else
-- Search for the command idx among the elements of the queue.
-- Easiest method of doing this is to pop elements, and pushing them again
-- if the cmd idx does not match. Not very efficient, but an OK initial implementation.
-- Pop the element. Compare cmd idx. If it does not match, push to local result queue.
-- If an index matches, set shared_vvc_response.result. (Don't push element back to result queue)
while result_queue.get_count(VOID) > 0 loop
v_current_element := result_queue.get(VOID);
if v_current_element.cmd_idx = command.gen_integer_array(0) then
shared_vvc_response.fetch_is_accepted := true;
shared_vvc_response.result := v_current_element.result;
log(ID_IMMEDIATE_CMD, to_string(command.proc_call) & " Requested result is found" & ". " & to_string(command.msg) & " " & format_command_idx(command), to_string(vvc_labels.scope), vvc_config.msg_id_panel); -- Get and ack the new command
exit;
else
-- No match for element: put in local result queue
v_local_result_queue.put(v_current_element);
end if;
end loop;
-- Pop each element of local result queue and push to result queue.
-- This is to clear the local result queue and restore the result
-- queue to its original state (except that the matched element is not put back).
while v_local_result_queue.get_count(VOID) > 0 loop
result_queue.put(v_local_result_queue.get(VOID));
end loop;
if not shared_vvc_response.fetch_is_accepted then
tb_warning(to_string(command.proc_call) & ". Requested result was not found. Given command index is not available in this VVC. " & format_command_idx(command), to_string(vvc_labels.scope));
end if;
end if;
end procedure;
procedure initialize_executor (
signal terminate_current_cmd : inout t_flag_record
) is
begin
reset_flag(terminate_current_cmd);
wait for 0 ns; -- delay by 1 delta cycle to allow constructor to finish first
end procedure;
procedure fetch_command_and_prepare_executor(
variable command : inout t_vvc_cmd_record;
variable command_queue : inout work.td_cmd_queue_pkg.t_generic_queue;
constant vvc_config : in t_vvc_config;
variable vvc_status : inout t_vvc_status;
signal queue_is_increasing : in boolean;
signal executor_is_busy : inout boolean;
constant vvc_labels : in t_vvc_labels
) is
begin
executor_is_busy <= false;
wait for 0 ns; -- to allow delta updates in other processes.
if command_queue.is_empty(VOID) then
log(ID_CMD_EXECUTOR_WAIT, "Executor: Waiting for command", to_string(vvc_labels.scope), vvc_config.msg_id_panel);
wait until queue_is_increasing;
end if;
-- Queue is now not empty
executor_is_busy <= true;
wait until executor_is_busy;
vvc_status.previous_cmd_idx := command.cmd_idx;
command := command_queue.get(VOID);
log(ID_CMD_EXECUTOR, to_string(command.proc_call) & " - Will be executed " & format_command_idx(command), to_string(vvc_labels.scope), vvc_config.msg_id_panel); -- Get and ack the new command
vvc_status.pending_cmd_cnt := command_queue.get_count(VOID);
vvc_status.current_cmd_idx := command.cmd_idx;
end procedure;
-- The result_queue is used so that whatever type defined in the VVC can be stored,
-- and later fetched with fetch_result()
procedure store_result(
variable result_queue : inout work.td_result_queue_pkg.t_generic_queue;
constant cmd_idx : in natural;
constant result : in t_vvc_result
) is
variable v_result_queue_element : t_vvc_result_queue_element;
begin
v_result_queue_element.cmd_idx := cmd_idx;
v_result_queue_element.result := result;
result_queue.put(v_result_queue_element);
end procedure;
procedure insert_inter_bfm_delay_if_requested(
constant vvc_config : in t_vvc_config;
constant command_is_bfm_access : in boolean;
constant timestamp_start_of_last_bfm_access : in time;
constant timestamp_end_of_last_bfm_access : in time;
constant scope : in string := C_SCOPE
) is
begin
-- If both timestamps are at 0 ns we interpret this as the first BFM access, hence no delay shall be applied.
if ((vvc_config.inter_bfm_delay.delay_type /= NO_DELAY) and
command_is_bfm_access and
not ((timestamp_start_of_last_bfm_access = 0 ns) and (timestamp_end_of_last_bfm_access = 0 ns))) then
case vvc_config.inter_bfm_delay.delay_type is
when TIME_FINISH2START =>
if now < (timestamp_end_of_last_bfm_access + vvc_config.inter_bfm_delay.delay_in_time) then
log(ID_INSERTED_DELAY, "Delaying BFM access until time " & to_string(timestamp_end_of_last_bfm_access + vvc_config.inter_bfm_delay.delay_in_time)
& ".", scope, vvc_config.msg_id_panel);
wait for (timestamp_end_of_last_bfm_access + vvc_config.inter_bfm_delay.delay_in_time - now);
end if;
when TIME_START2START =>
if now < (timestamp_start_of_last_bfm_access + vvc_config.inter_bfm_delay.delay_in_time) then
log(ID_INSERTED_DELAY, "Delaying BFM access until time " & to_string(timestamp_start_of_last_bfm_access + vvc_config.inter_bfm_delay.delay_in_time)
& ".", scope, vvc_config.msg_id_panel);
wait for (timestamp_start_of_last_bfm_access + vvc_config.inter_bfm_delay.delay_in_time - now);
end if;
when others =>
tb_error("Delay type " & to_upper(to_string(vvc_config.inter_bfm_delay.delay_type)) & " not supported for this VVC.", C_SCOPE);
end case;
log(ID_INSERTED_DELAY, "Finished delaying BFM access", scope, vvc_config.msg_id_panel);
end if;
end procedure;
end package body td_vvc_entity_support_pkg;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.flat_memory_model.all;
entity tb_proc_core is
generic (
test_file : string := "testcode";
test_base : integer := 16#FF00# );
end tb_proc_core;
architecture tb of tb_proc_core is
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal addr_out : std_logic_vector(16 downto 0);
signal data_in : std_logic_vector(7 downto 0) := X"AA";
signal data_out : std_logic_vector(7 downto 0);
signal read_write_n : std_logic;
signal nmi_n : std_logic := '1';
signal irq_n : std_logic := '1';
signal stop_clock : boolean := false;
shared variable ram : h_mem_object;
begin
clock <= not clock after 50 ns when not stop_clock;
clock_en <= '1';
reset <= '1', '0' after 300 ns;
core: entity work.proc_core
generic map (
support_bcd => true )
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
irq_n => irq_n,
nmi_n => nmi_n,
addr_out => addr_out,
data_in => data_in,
data_out => data_out,
read_write_n => read_write_n );
process(clock)
variable addr : std_logic_vector(31 downto 0) := (others => '0');
begin
if falling_edge(clock) then
addr(15 downto 0) := addr_out(15 downto 0);
data_in <= read_memory_8(ram, addr);
if read_write_n = '0' then
write_memory_8(ram, addr, data_out);
if addr_out(15 downto 0) = X"FFF8" then
stop_clock <= true;
if data_out = X"55" then
report "Test program completed successfully." severity note;
else
report "Test program failed." severity error;
end if;
elsif addr_out(15 downto 0) = X"FFF9" then
case data_out is
when X"01" => report "Break IRQ service routine." severity note;
when X"02" => report "External IRQ service routine." severity note;
when X"03" => report "NMI service routine." severity note;
when others => report "Unknown event message." severity warning;
end case;
end if;
end if;
end if;
end process;
test: process
begin
register_mem_model("6502 ram", ram);
load_memory(test_file, ram, conv_std_logic_vector(test_base, 32));
wait for 30 us;
irq_n <= '0';
wait for 10 us;
irq_n <= '1';
wait for 10 us;
nmi_n <= '0';
wait for 10 us;
nmi_n <= '1';
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.flat_memory_model.all;
entity tb_proc_core is
generic (
test_file : string := "testcode";
test_base : integer := 16#FF00# );
end tb_proc_core;
architecture tb of tb_proc_core is
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal addr_out : std_logic_vector(16 downto 0);
signal data_in : std_logic_vector(7 downto 0) := X"AA";
signal data_out : std_logic_vector(7 downto 0);
signal read_write_n : std_logic;
signal nmi_n : std_logic := '1';
signal irq_n : std_logic := '1';
signal stop_clock : boolean := false;
shared variable ram : h_mem_object;
begin
clock <= not clock after 50 ns when not stop_clock;
clock_en <= '1';
reset <= '1', '0' after 300 ns;
core: entity work.proc_core
generic map (
support_bcd => true )
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
irq_n => irq_n,
nmi_n => nmi_n,
addr_out => addr_out,
data_in => data_in,
data_out => data_out,
read_write_n => read_write_n );
process(clock)
variable addr : std_logic_vector(31 downto 0) := (others => '0');
begin
if falling_edge(clock) then
addr(15 downto 0) := addr_out(15 downto 0);
data_in <= read_memory_8(ram, addr);
if read_write_n = '0' then
write_memory_8(ram, addr, data_out);
if addr_out(15 downto 0) = X"FFF8" then
stop_clock <= true;
if data_out = X"55" then
report "Test program completed successfully." severity note;
else
report "Test program failed." severity error;
end if;
elsif addr_out(15 downto 0) = X"FFF9" then
case data_out is
when X"01" => report "Break IRQ service routine." severity note;
when X"02" => report "External IRQ service routine." severity note;
when X"03" => report "NMI service routine." severity note;
when others => report "Unknown event message." severity warning;
end case;
end if;
end if;
end if;
end process;
test: process
begin
register_mem_model("6502 ram", ram);
load_memory(test_file, ram, conv_std_logic_vector(test_base, 32));
wait for 30 us;
irq_n <= '0';
wait for 10 us;
irq_n <= '1';
wait for 10 us;
nmi_n <= '0';
wait for 10 us;
nmi_n <= '1';
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.flat_memory_model.all;
entity tb_proc_core is
generic (
test_file : string := "testcode";
test_base : integer := 16#FF00# );
end tb_proc_core;
architecture tb of tb_proc_core is
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal addr_out : std_logic_vector(16 downto 0);
signal data_in : std_logic_vector(7 downto 0) := X"AA";
signal data_out : std_logic_vector(7 downto 0);
signal read_write_n : std_logic;
signal nmi_n : std_logic := '1';
signal irq_n : std_logic := '1';
signal stop_clock : boolean := false;
shared variable ram : h_mem_object;
begin
clock <= not clock after 50 ns when not stop_clock;
clock_en <= '1';
reset <= '1', '0' after 300 ns;
core: entity work.proc_core
generic map (
support_bcd => true )
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
irq_n => irq_n,
nmi_n => nmi_n,
addr_out => addr_out,
data_in => data_in,
data_out => data_out,
read_write_n => read_write_n );
process(clock)
variable addr : std_logic_vector(31 downto 0) := (others => '0');
begin
if falling_edge(clock) then
addr(15 downto 0) := addr_out(15 downto 0);
data_in <= read_memory_8(ram, addr);
if read_write_n = '0' then
write_memory_8(ram, addr, data_out);
if addr_out(15 downto 0) = X"FFF8" then
stop_clock <= true;
if data_out = X"55" then
report "Test program completed successfully." severity note;
else
report "Test program failed." severity error;
end if;
elsif addr_out(15 downto 0) = X"FFF9" then
case data_out is
when X"01" => report "Break IRQ service routine." severity note;
when X"02" => report "External IRQ service routine." severity note;
when X"03" => report "NMI service routine." severity note;
when others => report "Unknown event message." severity warning;
end case;
end if;
end if;
end if;
end process;
test: process
begin
register_mem_model("6502 ram", ram);
load_memory(test_file, ram, conv_std_logic_vector(test_base, 32));
wait for 30 us;
irq_n <= '0';
wait for 10 us;
irq_n <= '1';
wait for 10 us;
nmi_n <= '0';
wait for 10 us;
nmi_n <= '1';
wait;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.flat_memory_model.all;
entity tb_proc_core is
generic (
test_file : string := "testcode";
test_base : integer := 16#FF00# );
end tb_proc_core;
architecture tb of tb_proc_core is
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal addr_out : std_logic_vector(16 downto 0);
signal data_in : std_logic_vector(7 downto 0) := X"AA";
signal data_out : std_logic_vector(7 downto 0);
signal read_write_n : std_logic;
signal nmi_n : std_logic := '1';
signal irq_n : std_logic := '1';
signal stop_clock : boolean := false;
shared variable ram : h_mem_object;
begin
clock <= not clock after 50 ns when not stop_clock;
clock_en <= '1';
reset <= '1', '0' after 300 ns;
core: entity work.proc_core
generic map (
support_bcd => true )
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
irq_n => irq_n,
nmi_n => nmi_n,
addr_out => addr_out,
data_in => data_in,
data_out => data_out,
read_write_n => read_write_n );
process(clock)
variable addr : std_logic_vector(31 downto 0) := (others => '0');
begin
if falling_edge(clock) then
addr(15 downto 0) := addr_out(15 downto 0);
data_in <= read_memory_8(ram, addr);
if read_write_n = '0' then
write_memory_8(ram, addr, data_out);
if addr_out(15 downto 0) = X"FFF8" then
stop_clock <= true;
if data_out = X"55" then
report "Test program completed successfully." severity note;
else
report "Test program failed." severity error;
end if;
elsif addr_out(15 downto 0) = X"FFF9" then
case data_out is
when X"01" => report "Break IRQ service routine." severity note;
when X"02" => report "External IRQ service routine." severity note;
when X"03" => report "NMI service routine." severity note;
when others => report "Unknown event message." severity warning;
end case;
end if;
end if;
end if;
end process;
test: process
begin
register_mem_model("6502 ram", ram);
load_memory(test_file, ram, conv_std_logic_vector(test_base, 32));
wait for 30 us;
irq_n <= '0';
wait for 10 us;
irq_n <= '1';
wait for 10 us;
nmi_n <= '0';
wait for 10 us;
nmi_n <= '1';
wait;
end process;
end tb;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3200;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3200.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 13;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_MEM_BURST_LEN : integer := 4;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_SIMULATION : string := "TRUE";
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p2_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000");
constant C3_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p3_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000006ff", x"06ffffff");
constant C3_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"f8000000");
constant C3_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000");
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component ddr2ram is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic; c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_wr_clk : in std_logic;
c3_p3_wr_en : in std_logic;
c3_p3_wr_mask : in std_logic_vector(3 downto 0);
c3_p3_wr_data : in std_logic_vector(31 downto 0);
c3_p3_wr_full : out std_logic;
c3_p3_wr_empty : out std_logic;
c3_p3_wr_count : out std_logic_vector(6 downto 0);
c3_p3_wr_underrun : out std_logic;
c3_p3_wr_error : out std_logic
);
end component;
component ddr2_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_rdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
rdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic
);
end component;
component memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p3_mcb_cmd_en_o : out std_logic;
p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p3_mcb_cmd_full_i : in std_logic;
p3_mcb_wr_en_o : out std_logic;
p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
p3_mcb_wr_data_o : out std_logic_vector(31 downto 0);
p3_mcb_wr_full_i : in std_logic;
p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_cmp_error : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal c3_p2_cmd_en : std_logic;
signal c3_p2_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p2_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p2_cmd_empty : std_logic;
signal c3_p2_cmd_full : std_logic;
signal c3_p2_rd_en : std_logic;
signal c3_p2_rd_data : std_logic_vector(31 downto 0);
signal c3_p2_rd_full : std_logic;
signal c3_p2_rd_empty : std_logic;
signal c3_p2_rd_count : std_logic_vector(6 downto 0);
signal c3_p2_rd_overflow : std_logic;
signal c3_p2_rd_error : std_logic;
signal c3_p3_cmd_en : std_logic;
signal c3_p3_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p3_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p3_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p3_cmd_empty : std_logic;
signal c3_p3_cmd_full : std_logic;
signal c3_p3_wr_en : std_logic;
signal c3_p3_wr_mask : std_logic_vector(3 downto 0);
signal c3_p3_wr_data : std_logic_vector(31 downto 0);
signal c3_p3_wr_full : std_logic;
signal c3_p3_wr_empty : std_logic;
signal c3_p3_wr_count : std_logic_vector(6 downto 0);
signal c3_p3_wr_underrun : std_logic;
signal c3_p3_wr_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
signal rzq3 : std_logic;
signal zio3 : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
error <= c3_error;
calib_done <= c3_calib_done;
-- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
zio_pulldown3 : PULLDOWN port map(O => zio3);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : ddr2ram generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => rzq3,
mcb3_zio => zio3,
c3_p2_cmd_clk => (c3_clk0),
c3_p2_cmd_en => c3_p2_cmd_en,
c3_p2_cmd_instr => c3_p2_cmd_instr,
c3_p2_cmd_bl => c3_p2_cmd_bl,
c3_p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
c3_p2_cmd_empty => c3_p2_cmd_empty,
c3_p2_cmd_full => c3_p2_cmd_full,
c3_p2_rd_clk => (c3_clk0),
c3_p2_rd_en => c3_p2_rd_en,
c3_p2_rd_data => c3_p2_rd_data,
c3_p2_rd_full => c3_p2_rd_full,
c3_p2_rd_empty => c3_p2_rd_empty,
c3_p2_rd_count => c3_p2_rd_count,
c3_p2_rd_overflow => c3_p2_rd_overflow,
c3_p2_rd_error => c3_p2_rd_error,
c3_p3_cmd_clk => (c3_clk0),
c3_p3_cmd_en => c3_p3_cmd_en,
c3_p3_cmd_instr => c3_p3_cmd_instr,
c3_p3_cmd_bl => c3_p3_cmd_bl,
c3_p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
c3_p3_cmd_empty => c3_p3_cmd_empty,
c3_p3_cmd_full => c3_p3_cmd_full,
c3_p3_wr_clk => (c3_clk0),
c3_p3_wr_en => c3_p3_wr_en,
c3_p3_wr_mask => c3_p3_wr_mask,
c3_p3_wr_data => c3_p3_wr_data,
c3_p3_wr_full => c3_p3_wr_full,
c3_p3_wr_empty => c3_p3_wr_empty,
c3_p3_wr_count => c3_p3_wr_count,
c3_p3_wr_underrun => c3_p3_wr_underrun,
c3_p3_wr_error => c3_p3_wr_error
);
-- user interface
memc3_tb_top_inst : memc3_tb_top generic map
(
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_p2_BEGIN_ADDRESS => C3_p2_BEGIN_ADDRESS,
C_p2_DATA_MODE => C3_p2_DATA_MODE,
C_p2_END_ADDRESS => C3_p2_END_ADDRESS,
C_p2_PRBS_EADDR_MASK_POS => C3_p2_PRBS_EADDR_MASK_POS,
C_p2_PRBS_SADDR_MASK_POS => C3_p2_PRBS_SADDR_MASK_POS,
C_p3_BEGIN_ADDRESS => C3_p3_BEGIN_ADDRESS,
C_p3_DATA_MODE => C3_p3_DATA_MODE,
C_p3_END_ADDRESS => C3_p3_END_ADDRESS,
C_p3_PRBS_EADDR_MASK_POS => C3_p3_PRBS_EADDR_MASK_POS,
C_p3_PRBS_SADDR_MASK_POS => C3_p3_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c3_clk0,
rst0 => c3_rst0,
calib_done => c3_calib_done,
cmp_error => c3_cmp_error,
error => c3_error,
error_status => c3_error_status,
vio_modify_enable => c3_vio_modify_enable,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
p2_mcb_cmd_en_o => c3_p2_cmd_en,
p2_mcb_cmd_instr_o => c3_p2_cmd_instr,
p2_mcb_cmd_bl_o => c3_p2_cmd_bl,
p2_mcb_cmd_addr_o => c3_p2_cmd_byte_addr,
p2_mcb_cmd_full_i => c3_p2_cmd_full,
p2_mcb_rd_en_o => c3_p2_rd_en,
p2_mcb_rd_data_i => c3_p2_rd_data,
p2_mcb_rd_empty_i => c3_p2_rd_empty,
p2_mcb_rd_fifo_counts => c3_p2_rd_count,
p3_mcb_cmd_en_o => c3_p3_cmd_en,
p3_mcb_cmd_instr_o => c3_p3_cmd_instr,
p3_mcb_cmd_bl_o => c3_p3_cmd_bl,
p3_mcb_cmd_addr_o => c3_p3_cmd_byte_addr,
p3_mcb_cmd_full_i => c3_p3_cmd_full,
p3_mcb_wr_en_o => c3_p3_wr_en,
p3_mcb_wr_mask_o => c3_p3_wr_mask,
p3_mcb_wr_data_o => c3_p3_wr_data,
p3_mcb_wr_full_i => c3_p3_wr_full,
p3_mcb_wr_fifo_counts => c3_p3_wr_count
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr2_model_c3 port map(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_rdqs => mcb3_dram_dm_vector ,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
rdqs_n => open,
odt => mcb3_dram_odt
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3200;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3200.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 13;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_MEM_BURST_LEN : integer := 4;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_SIMULATION : string := "TRUE";
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p2_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000");
constant C3_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p3_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000006ff", x"06ffffff");
constant C3_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"f8000000");
constant C3_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000");
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component ddr2ram is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic; c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_wr_clk : in std_logic;
c3_p3_wr_en : in std_logic;
c3_p3_wr_mask : in std_logic_vector(3 downto 0);
c3_p3_wr_data : in std_logic_vector(31 downto 0);
c3_p3_wr_full : out std_logic;
c3_p3_wr_empty : out std_logic;
c3_p3_wr_count : out std_logic_vector(6 downto 0);
c3_p3_wr_underrun : out std_logic;
c3_p3_wr_error : out std_logic
);
end component;
component ddr2_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_rdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
rdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic
);
end component;
component memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p3_mcb_cmd_en_o : out std_logic;
p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p3_mcb_cmd_full_i : in std_logic;
p3_mcb_wr_en_o : out std_logic;
p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
p3_mcb_wr_data_o : out std_logic_vector(31 downto 0);
p3_mcb_wr_full_i : in std_logic;
p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_cmp_error : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal c3_p2_cmd_en : std_logic;
signal c3_p2_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p2_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p2_cmd_empty : std_logic;
signal c3_p2_cmd_full : std_logic;
signal c3_p2_rd_en : std_logic;
signal c3_p2_rd_data : std_logic_vector(31 downto 0);
signal c3_p2_rd_full : std_logic;
signal c3_p2_rd_empty : std_logic;
signal c3_p2_rd_count : std_logic_vector(6 downto 0);
signal c3_p2_rd_overflow : std_logic;
signal c3_p2_rd_error : std_logic;
signal c3_p3_cmd_en : std_logic;
signal c3_p3_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p3_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p3_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p3_cmd_empty : std_logic;
signal c3_p3_cmd_full : std_logic;
signal c3_p3_wr_en : std_logic;
signal c3_p3_wr_mask : std_logic_vector(3 downto 0);
signal c3_p3_wr_data : std_logic_vector(31 downto 0);
signal c3_p3_wr_full : std_logic;
signal c3_p3_wr_empty : std_logic;
signal c3_p3_wr_count : std_logic_vector(6 downto 0);
signal c3_p3_wr_underrun : std_logic;
signal c3_p3_wr_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
signal rzq3 : std_logic;
signal zio3 : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
error <= c3_error;
calib_done <= c3_calib_done;
-- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
zio_pulldown3 : PULLDOWN port map(O => zio3);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : ddr2ram generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => rzq3,
mcb3_zio => zio3,
c3_p2_cmd_clk => (c3_clk0),
c3_p2_cmd_en => c3_p2_cmd_en,
c3_p2_cmd_instr => c3_p2_cmd_instr,
c3_p2_cmd_bl => c3_p2_cmd_bl,
c3_p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
c3_p2_cmd_empty => c3_p2_cmd_empty,
c3_p2_cmd_full => c3_p2_cmd_full,
c3_p2_rd_clk => (c3_clk0),
c3_p2_rd_en => c3_p2_rd_en,
c3_p2_rd_data => c3_p2_rd_data,
c3_p2_rd_full => c3_p2_rd_full,
c3_p2_rd_empty => c3_p2_rd_empty,
c3_p2_rd_count => c3_p2_rd_count,
c3_p2_rd_overflow => c3_p2_rd_overflow,
c3_p2_rd_error => c3_p2_rd_error,
c3_p3_cmd_clk => (c3_clk0),
c3_p3_cmd_en => c3_p3_cmd_en,
c3_p3_cmd_instr => c3_p3_cmd_instr,
c3_p3_cmd_bl => c3_p3_cmd_bl,
c3_p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
c3_p3_cmd_empty => c3_p3_cmd_empty,
c3_p3_cmd_full => c3_p3_cmd_full,
c3_p3_wr_clk => (c3_clk0),
c3_p3_wr_en => c3_p3_wr_en,
c3_p3_wr_mask => c3_p3_wr_mask,
c3_p3_wr_data => c3_p3_wr_data,
c3_p3_wr_full => c3_p3_wr_full,
c3_p3_wr_empty => c3_p3_wr_empty,
c3_p3_wr_count => c3_p3_wr_count,
c3_p3_wr_underrun => c3_p3_wr_underrun,
c3_p3_wr_error => c3_p3_wr_error
);
-- user interface
memc3_tb_top_inst : memc3_tb_top generic map
(
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_p2_BEGIN_ADDRESS => C3_p2_BEGIN_ADDRESS,
C_p2_DATA_MODE => C3_p2_DATA_MODE,
C_p2_END_ADDRESS => C3_p2_END_ADDRESS,
C_p2_PRBS_EADDR_MASK_POS => C3_p2_PRBS_EADDR_MASK_POS,
C_p2_PRBS_SADDR_MASK_POS => C3_p2_PRBS_SADDR_MASK_POS,
C_p3_BEGIN_ADDRESS => C3_p3_BEGIN_ADDRESS,
C_p3_DATA_MODE => C3_p3_DATA_MODE,
C_p3_END_ADDRESS => C3_p3_END_ADDRESS,
C_p3_PRBS_EADDR_MASK_POS => C3_p3_PRBS_EADDR_MASK_POS,
C_p3_PRBS_SADDR_MASK_POS => C3_p3_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c3_clk0,
rst0 => c3_rst0,
calib_done => c3_calib_done,
cmp_error => c3_cmp_error,
error => c3_error,
error_status => c3_error_status,
vio_modify_enable => c3_vio_modify_enable,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
p2_mcb_cmd_en_o => c3_p2_cmd_en,
p2_mcb_cmd_instr_o => c3_p2_cmd_instr,
p2_mcb_cmd_bl_o => c3_p2_cmd_bl,
p2_mcb_cmd_addr_o => c3_p2_cmd_byte_addr,
p2_mcb_cmd_full_i => c3_p2_cmd_full,
p2_mcb_rd_en_o => c3_p2_rd_en,
p2_mcb_rd_data_i => c3_p2_rd_data,
p2_mcb_rd_empty_i => c3_p2_rd_empty,
p2_mcb_rd_fifo_counts => c3_p2_rd_count,
p3_mcb_cmd_en_o => c3_p3_cmd_en,
p3_mcb_cmd_instr_o => c3_p3_cmd_instr,
p3_mcb_cmd_bl_o => c3_p3_cmd_bl,
p3_mcb_cmd_addr_o => c3_p3_cmd_byte_addr,
p3_mcb_cmd_full_i => c3_p3_cmd_full,
p3_mcb_wr_en_o => c3_p3_wr_en,
p3_mcb_wr_mask_o => c3_p3_wr_mask,
p3_mcb_wr_data_o => c3_p3_wr_data,
p3_mcb_wr_full_i => c3_p3_wr_full,
p3_mcb_wr_fifo_counts => c3_p3_wr_count
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr2_model_c3 port map(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_rdqs => mcb3_dram_dm_vector ,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
rdqs_n => open,
odt => mcb3_dram_odt
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3200;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3200.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 13;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_MEM_BURST_LEN : integer := 4;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_SIMULATION : string := "TRUE";
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p2_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000");
constant C3_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p3_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000006ff", x"06ffffff");
constant C3_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffff800", x"f8000000");
constant C3_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000500", x"05000000");
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component ddr2ram is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic; c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_wr_clk : in std_logic;
c3_p3_wr_en : in std_logic;
c3_p3_wr_mask : in std_logic_vector(3 downto 0);
c3_p3_wr_data : in std_logic_vector(31 downto 0);
c3_p3_wr_full : out std_logic;
c3_p3_wr_empty : out std_logic;
c3_p3_wr_count : out std_logic_vector(6 downto 0);
c3_p3_wr_underrun : out std_logic;
c3_p3_wr_error : out std_logic
);
end component;
component ddr2_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_rdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
rdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic
);
end component;
component memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p2_mcb_cmd_en_o : out std_logic;
p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p2_mcb_cmd_full_i : in std_logic;
p2_mcb_rd_en_o : out std_logic;
p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
p2_mcb_rd_empty_i : in std_logic;
p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p3_mcb_cmd_en_o : out std_logic;
p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p3_mcb_cmd_full_i : in std_logic;
p3_mcb_wr_en_o : out std_logic;
p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
p3_mcb_wr_data_o : out std_logic_vector(31 downto 0);
p3_mcb_wr_full_i : in std_logic;
p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_cmp_error : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal c3_p2_cmd_en : std_logic;
signal c3_p2_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p2_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p2_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p2_cmd_empty : std_logic;
signal c3_p2_cmd_full : std_logic;
signal c3_p2_rd_en : std_logic;
signal c3_p2_rd_data : std_logic_vector(31 downto 0);
signal c3_p2_rd_full : std_logic;
signal c3_p2_rd_empty : std_logic;
signal c3_p2_rd_count : std_logic_vector(6 downto 0);
signal c3_p2_rd_overflow : std_logic;
signal c3_p2_rd_error : std_logic;
signal c3_p3_cmd_en : std_logic;
signal c3_p3_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p3_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p3_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p3_cmd_empty : std_logic;
signal c3_p3_cmd_full : std_logic;
signal c3_p3_wr_en : std_logic;
signal c3_p3_wr_mask : std_logic_vector(3 downto 0);
signal c3_p3_wr_data : std_logic_vector(31 downto 0);
signal c3_p3_wr_full : std_logic;
signal c3_p3_wr_empty : std_logic;
signal c3_p3_wr_count : std_logic_vector(6 downto 0);
signal c3_p3_wr_underrun : std_logic;
signal c3_p3_wr_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
signal rzq3 : std_logic;
signal zio3 : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
error <= c3_error;
calib_done <= c3_calib_done;
-- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
zio_pulldown3 : PULLDOWN port map(O => zio3);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : ddr2ram generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => rzq3,
mcb3_zio => zio3,
c3_p2_cmd_clk => (c3_clk0),
c3_p2_cmd_en => c3_p2_cmd_en,
c3_p2_cmd_instr => c3_p2_cmd_instr,
c3_p2_cmd_bl => c3_p2_cmd_bl,
c3_p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
c3_p2_cmd_empty => c3_p2_cmd_empty,
c3_p2_cmd_full => c3_p2_cmd_full,
c3_p2_rd_clk => (c3_clk0),
c3_p2_rd_en => c3_p2_rd_en,
c3_p2_rd_data => c3_p2_rd_data,
c3_p2_rd_full => c3_p2_rd_full,
c3_p2_rd_empty => c3_p2_rd_empty,
c3_p2_rd_count => c3_p2_rd_count,
c3_p2_rd_overflow => c3_p2_rd_overflow,
c3_p2_rd_error => c3_p2_rd_error,
c3_p3_cmd_clk => (c3_clk0),
c3_p3_cmd_en => c3_p3_cmd_en,
c3_p3_cmd_instr => c3_p3_cmd_instr,
c3_p3_cmd_bl => c3_p3_cmd_bl,
c3_p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
c3_p3_cmd_empty => c3_p3_cmd_empty,
c3_p3_cmd_full => c3_p3_cmd_full,
c3_p3_wr_clk => (c3_clk0),
c3_p3_wr_en => c3_p3_wr_en,
c3_p3_wr_mask => c3_p3_wr_mask,
c3_p3_wr_data => c3_p3_wr_data,
c3_p3_wr_full => c3_p3_wr_full,
c3_p3_wr_empty => c3_p3_wr_empty,
c3_p3_wr_count => c3_p3_wr_count,
c3_p3_wr_underrun => c3_p3_wr_underrun,
c3_p3_wr_error => c3_p3_wr_error
);
-- user interface
memc3_tb_top_inst : memc3_tb_top generic map
(
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_p2_BEGIN_ADDRESS => C3_p2_BEGIN_ADDRESS,
C_p2_DATA_MODE => C3_p2_DATA_MODE,
C_p2_END_ADDRESS => C3_p2_END_ADDRESS,
C_p2_PRBS_EADDR_MASK_POS => C3_p2_PRBS_EADDR_MASK_POS,
C_p2_PRBS_SADDR_MASK_POS => C3_p2_PRBS_SADDR_MASK_POS,
C_p3_BEGIN_ADDRESS => C3_p3_BEGIN_ADDRESS,
C_p3_DATA_MODE => C3_p3_DATA_MODE,
C_p3_END_ADDRESS => C3_p3_END_ADDRESS,
C_p3_PRBS_EADDR_MASK_POS => C3_p3_PRBS_EADDR_MASK_POS,
C_p3_PRBS_SADDR_MASK_POS => C3_p3_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c3_clk0,
rst0 => c3_rst0,
calib_done => c3_calib_done,
cmp_error => c3_cmp_error,
error => c3_error,
error_status => c3_error_status,
vio_modify_enable => c3_vio_modify_enable,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
p2_mcb_cmd_en_o => c3_p2_cmd_en,
p2_mcb_cmd_instr_o => c3_p2_cmd_instr,
p2_mcb_cmd_bl_o => c3_p2_cmd_bl,
p2_mcb_cmd_addr_o => c3_p2_cmd_byte_addr,
p2_mcb_cmd_full_i => c3_p2_cmd_full,
p2_mcb_rd_en_o => c3_p2_rd_en,
p2_mcb_rd_data_i => c3_p2_rd_data,
p2_mcb_rd_empty_i => c3_p2_rd_empty,
p2_mcb_rd_fifo_counts => c3_p2_rd_count,
p3_mcb_cmd_en_o => c3_p3_cmd_en,
p3_mcb_cmd_instr_o => c3_p3_cmd_instr,
p3_mcb_cmd_bl_o => c3_p3_cmd_bl,
p3_mcb_cmd_addr_o => c3_p3_cmd_byte_addr,
p3_mcb_cmd_full_i => c3_p3_cmd_full,
p3_mcb_wr_en_o => c3_p3_wr_en,
p3_mcb_wr_mask_o => c3_p3_wr_mask,
p3_mcb_wr_data_o => c3_p3_wr_data,
p3_mcb_wr_full_i => c3_p3_wr_full,
p3_mcb_wr_fifo_counts => c3_p3_wr_count
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr2_model_c3 port map(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_rdqs => mcb3_dram_dm_vector ,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
rdqs_n => open,
odt => mcb3_dram_odt
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 16:24:43 05/12/2013
-- Design Name:
-- Module Name: pid_controller - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.utils_pack.all ;
-- gain are fixed point values 8 bit integer part, 8 bit fractionnal part
entity pid_controller is
generic(CLK_PERIOD_NS : positive := 10;
CTRL_PERIOD_NS : positive := 1000000;
CMD_WIDTH : positive := 8;
CMD_OFFSET : positive := 127);
port(clk, resetn : in std_logic ;
en, reset : in std_logic ;
speed_input : in signed(15 downto 0);
P, I, D : in signed(15 downto 0);
ENC_A : in std_logic ;
ENC_B : in std_logic ;
encoder_count : out signed(15 downto 0);
command : out std_logic_vector(CMD_WIDTH-1 downto 0)
);
end pid_controller;
architecture Behavioral of pid_controller is
constant clk_tick_per_period : integer := CTRL_PERIOD_NS/CLK_PERIOD_NS;
constant command_max : integer := (2**command'length)-1 ;
signal clk_tick_counter : std_logic_vector(nbit(clk_tick_per_period) downto 0);
signal speed_input_latched, encoder_value, encoder_value_latched : signed(15 downto 0) ;
signal error, error_grad, error_sum, last_error : signed(15 downto 0) ;
signal error_sum_enlarged : signed(31 downto 0) ;
signal std_encoder_value : std_logic_vector(15 downto 0) ;
signal command_temp, command_offset : signed(31 downto 0);
signal P_contrib, I_contrib, D_contrib : signed(31 downto 0);
signal reset_encoder : std_logic ;
signal ENC_A_OLD, ENC_A_RE : std_logic ;
signal error_32, error_sum_32 : signed(31 downto 0);
begin
process(clk, resetn)
begin
if resetn = '0' then
ENC_A_OLD <= '0';
elsif clk'event and clk = '1' then
ENC_A_OLD <= ENC_A ;
end if ;
end process ;
ENC_A_RE <= (ENC_A and (NOT ENC_A_OLD)) and en;
encoder_chan0 : up_down_counter
generic map(NBIT => 16)
port map( clk => clk,
resetn => resetn,
sraz => reset_encoder,
en => ENC_A_RE , -- must detect rising edge
load => '0',
up_downn => ENC_B,
E => (others => '0'),
Q => std_encoder_value
);
encoder_value <= signed(std_encoder_value) ;
process(clk, resetn)
begin
if resetn = '0' then
clk_tick_counter <= (others => '0');
elsif clk'event and clk = '1' then
if clk_tick_counter = clk_tick_per_period then
clk_tick_counter <= (others => '0');
else
clk_tick_counter <= clk_tick_counter + 1 ;
end if ;
end if ;
end process ;
process(clk, resetn)
begin
if resetn = '0' then
encoder_value_latched <= (others => '0');
speed_input_latched <= (others => '0');
last_error <= (others => '0');
elsif clk'event and clk = '1' then
if clk_tick_counter = clk_tick_per_period then
encoder_value_latched <= encoder_value ;
speed_input_latched <= speed_input ;
last_error <= error ;
end if ;
end if ;
end process ;
reset_encoder <= '1' when clk_tick_counter = clk_tick_per_period else
'0' ;
error <= speed_input_latched - encoder_value_latched ;
-- derivative term
error_grad <= error - last_error ;
error_32 <= RESIZE(error, 32) ;
error_sum_32 <= RESIZE(error_sum, 32) ;
error_sum_enlarged <= error_sum_32 + error_32 ;
integral_term_latch:process(clk, resetn)
begin
if resetn = '0' then
error_sum <= (others => '0');
elsif clk'event and clk = '1' then
if clk_tick_counter = 0 then
if error_sum_enlarged > (2**15 - 1) then -- handling saturation
error_sum <= X"7FFF" ;
elsif error_sum_enlarged < (-(2**15)) then
error_sum <= X"8000" ;
else
error_sum <= error_sum + error ;
end if ;
end if ;
end if ;
end process ;
contrib_latch :process(clk, resetn)
begin
if resetn = '0' then
P_contrib <= (others => '0');
I_contrib <= (others => '0');
D_contrib <= (others => '0');
elsif clk'event and clk = '1' then
P_contrib <= P*error ;
I_contrib <= I*error_sum ;
D_contrib <= D*error_grad ;
end if ;
end process ;
command_temp <= P_contrib + I_contrib + D_contrib ; -- need adder tree
command_offset <= command_temp + to_signed((CMD_OFFSET*(2**16)), 32) ;
command <= (others => '1') when command_offset(31 downto 16) > command_max else
(others => '0') when command_offset(31 downto 16) < 0 else
std_logic_vector(command_offset((15+CMD_WIDTH) downto 16));
end Behavioral;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 16:24:43 05/12/2013
-- Design Name:
-- Module Name: pid_controller - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.utils_pack.all ;
-- gain are fixed point values 8 bit integer part, 8 bit fractionnal part
entity pid_controller is
generic(CLK_PERIOD_NS : positive := 10;
CTRL_PERIOD_NS : positive := 1000000;
CMD_WIDTH : positive := 8;
CMD_OFFSET : positive := 127);
port(clk, resetn : in std_logic ;
en, reset : in std_logic ;
speed_input : in signed(15 downto 0);
P, I, D : in signed(15 downto 0);
ENC_A : in std_logic ;
ENC_B : in std_logic ;
encoder_count : out signed(15 downto 0);
command : out std_logic_vector(CMD_WIDTH-1 downto 0)
);
end pid_controller;
architecture Behavioral of pid_controller is
constant clk_tick_per_period : integer := CTRL_PERIOD_NS/CLK_PERIOD_NS;
constant command_max : integer := (2**command'length)-1 ;
signal clk_tick_counter : std_logic_vector(nbit(clk_tick_per_period) downto 0);
signal speed_input_latched, encoder_value, encoder_value_latched : signed(15 downto 0) ;
signal error, error_grad, error_sum, last_error : signed(15 downto 0) ;
signal error_sum_enlarged : signed(31 downto 0) ;
signal std_encoder_value : std_logic_vector(15 downto 0) ;
signal command_temp, command_offset : signed(31 downto 0);
signal P_contrib, I_contrib, D_contrib : signed(31 downto 0);
signal reset_encoder : std_logic ;
signal ENC_A_OLD, ENC_A_RE : std_logic ;
signal error_32, error_sum_32 : signed(31 downto 0);
begin
process(clk, resetn)
begin
if resetn = '0' then
ENC_A_OLD <= '0';
elsif clk'event and clk = '1' then
ENC_A_OLD <= ENC_A ;
end if ;
end process ;
ENC_A_RE <= (ENC_A and (NOT ENC_A_OLD)) and en;
encoder_chan0 : up_down_counter
generic map(NBIT => 16)
port map( clk => clk,
resetn => resetn,
sraz => reset_encoder,
en => ENC_A_RE , -- must detect rising edge
load => '0',
up_downn => ENC_B,
E => (others => '0'),
Q => std_encoder_value
);
encoder_value <= signed(std_encoder_value) ;
process(clk, resetn)
begin
if resetn = '0' then
clk_tick_counter <= (others => '0');
elsif clk'event and clk = '1' then
if clk_tick_counter = clk_tick_per_period then
clk_tick_counter <= (others => '0');
else
clk_tick_counter <= clk_tick_counter + 1 ;
end if ;
end if ;
end process ;
process(clk, resetn)
begin
if resetn = '0' then
encoder_value_latched <= (others => '0');
speed_input_latched <= (others => '0');
last_error <= (others => '0');
elsif clk'event and clk = '1' then
if clk_tick_counter = clk_tick_per_period then
encoder_value_latched <= encoder_value ;
speed_input_latched <= speed_input ;
last_error <= error ;
end if ;
end if ;
end process ;
reset_encoder <= '1' when clk_tick_counter = clk_tick_per_period else
'0' ;
error <= speed_input_latched - encoder_value_latched ;
-- derivative term
error_grad <= error - last_error ;
error_32 <= RESIZE(error, 32) ;
error_sum_32 <= RESIZE(error_sum, 32) ;
error_sum_enlarged <= error_sum_32 + error_32 ;
integral_term_latch:process(clk, resetn)
begin
if resetn = '0' then
error_sum <= (others => '0');
elsif clk'event and clk = '1' then
if clk_tick_counter = 0 then
if error_sum_enlarged > (2**15 - 1) then -- handling saturation
error_sum <= X"7FFF" ;
elsif error_sum_enlarged < (-(2**15)) then
error_sum <= X"8000" ;
else
error_sum <= error_sum + error ;
end if ;
end if ;
end if ;
end process ;
contrib_latch :process(clk, resetn)
begin
if resetn = '0' then
P_contrib <= (others => '0');
I_contrib <= (others => '0');
D_contrib <= (others => '0');
elsif clk'event and clk = '1' then
P_contrib <= P*error ;
I_contrib <= I*error_sum ;
D_contrib <= D*error_grad ;
end if ;
end process ;
command_temp <= P_contrib + I_contrib + D_contrib ; -- need adder tree
command_offset <= command_temp + to_signed((CMD_OFFSET*(2**16)), 32) ;
command <= (others => '1') when command_offset(31 downto 16) > command_max else
(others => '0') when command_offset(31 downto 16) < 0 else
std_logic_vector(command_offset((15+CMD_WIDTH) downto 16));
end Behavioral;
|
--
-- This file is part of top_chenillard
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity chenillard is
port(
clk : in std_logic;
reset : in std_logic;
button : in std_logic;
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
led4 : out std_logic
);
end chenillard;
architecture Behavioral of chenillard is
type state_type is (e1,e2,e3,e4,e5,e6);
signal state,next_state : state_type;
begin
--state register
process(clk,reset)
begin
if reset = '1' then
state <= e1;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
--state transition
process(state)
begin
case state is
when e1 => next_state <= e2;
when e2 => next_state <= e3;
when e3 => next_state <= e4;
when e4 => next_state <= e5;
when e5 => next_state <= e6;
when e6 => next_state <= e1;
end case;
end process;
--output function
led1 <= '1' when state = e1 else '0';
led2 <= '1' when state = e2 or state = e6 else '0';
led3 <= '1' when state = e3 or state = e5 else '0';
led4 <= '1' when state = e4 else '0';
end Behavioral;
|
-- ==================================================================
-- >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- ------------------------------------------------------------------
-- Copyright (c) 2013 by Lattice Semiconductor Corporation
-- ALL RIGHTS RESERVED
-- ------------------------------------------------------------------
--
-- Permission:
--
-- Lattice SG Pte. Ltd. grants permission to use this code
-- pursuant to the terms of the Lattice Reference Design License Agreement.
--
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice provides no warranty
-- regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--
-- Lattice SG Pte. Ltd.
-- 101 Thomson Road, United Square #07-02
-- Singapore 307591
--
--
-- TEL: 1-800-Lattice (USA and Canada)
-- +65-6631-2000 (Singapore)
-- +1-503-268-8001 (other locations)
--
-- web: http:--www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
-- Code Revision History :
-- --------------------------------------------------------------------
-- Ver: | Author |Mod. Date |Changes Made:
-- V1.0 |K.P. | 7/09 | Initial ver for VHDL
-- | converted from LSC ref design RD1046
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2c_master_byte_ctrl is
port (
clk : in std_logic; -- master clock
rst : in std_logic; -- synchronous active high reset
nReset : in std_logic; -- asynchronous active low reset
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- control inputs
start : in std_logic;
stop : in std_logic;
read : in std_logic;
write : in std_logic;
ack_in : in std_logic;
din : in std_logic_vector(7 downto 0);
-- status outputs
cmd_ack : out std_logic;
ack_out : out std_logic; -- i2c clock line input
dout : out std_logic_vector(7 downto 0);
i2c_al : in std_logic;
-- signals for bit_controller
core_cmd : out std_logic_vector(3 downto 0);
core_txd : out std_logic;
core_rxd : in std_logic;
core_ack : in std_logic
);
end;
architecture arch of i2c_master_byte_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "1000";
constant ST_IDLE : std_logic_vector(4 downto 0) := "00000";
constant ST_START : std_logic_vector(4 downto 0) := "00001";
constant ST_READ : std_logic_vector(4 downto 0) := "00010";
constant ST_WRITE : std_logic_vector(4 downto 0) := "00100";
constant ST_ACK : std_logic_vector(4 downto 0) := "01000";
constant ST_STOP : std_logic_vector(4 downto 0) := "10000";
signal c_state : std_logic_vector(4 downto 0);
signal go : std_logic;
signal dcnt : std_logic_vector(2 downto 0);
signal cnt_done : std_logic;
signal sr : std_logic_vector(7 downto 0); --8bit shift register
signal shift, ld : std_logic;
signal cmd_ack_int : std_logic;
begin
go <= '1' when (((read = '1') OR (write = '1') OR (stop = '1')) AND (cmd_ack_int = '0')) else '0';
dout <= sr;
-- generate shift register
process(clk,nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif rising_edge(clk) then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= sr(6 downto 0) & core_rxd;
end if;
end if;
end process;
-- generate counter
process(clk,nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif rising_edge(clk) then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= "111";
elsif (shift = '1') then
dcnt <= dcnt - '1';
end if;
end if;
end process;
cnt_done <= '1' when (dcnt = "000") else '0';
-- state machine
process(clk,nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
cmd_ack_int <= '0';
c_state <= ST_IDLE;
ack_out <= '0';
elsif rising_edge(clk) then
if ((rst = '1') OR (i2c_al = '1')) then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
cmd_ack_int <= '0';
c_state <= ST_IDLE;
ack_out <= '0';
else
-- initially reset all signals
core_txd <= sr(7);
shift <= '0';
ld <= '0';
cmd_ack_int <= '0';
case (c_state) is
when ST_IDLE =>
if (go = '1') then
if (start = '1') then
c_state <= ST_START;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= ST_READ;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= ST_WRITE;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= ST_STOP;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when ST_START =>
if (core_ack = '1') then
if (read = '1') then
c_state <= ST_READ;
core_cmd <= I2C_CMD_READ;
else
c_state <= ST_WRITE;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when ST_WRITE =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= ST_ACK;
core_cmd <= I2C_CMD_READ;
else
c_state <= ST_WRITE; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when ST_READ =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= ST_ACK;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= ST_READ; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
shift <= '1';
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when ST_ACK =>
if (core_ack = '1') then
if (stop = '1') then
c_state <= ST_STOP;
core_cmd <= I2C_CMD_STOP;
else
c_state <= ST_IDLE;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
cmd_ack_int <= '1';
end if;
-- assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when ST_STOP =>
if (core_ack = '1') then
c_state <= ST_IDLE;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
cmd_ack_int <= '1';
end if;
when others => NULL;
end case;
end if;
end if;
end process;
cmd_ack <= cmd_ack_int;
end arch;
|
-- ==================================================================
-- >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- ------------------------------------------------------------------
-- Copyright (c) 2013 by Lattice Semiconductor Corporation
-- ALL RIGHTS RESERVED
-- ------------------------------------------------------------------
--
-- Permission:
--
-- Lattice SG Pte. Ltd. grants permission to use this code
-- pursuant to the terms of the Lattice Reference Design License Agreement.
--
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice provides no warranty
-- regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--
-- Lattice SG Pte. Ltd.
-- 101 Thomson Road, United Square #07-02
-- Singapore 307591
--
--
-- TEL: 1-800-Lattice (USA and Canada)
-- +65-6631-2000 (Singapore)
-- +1-503-268-8001 (other locations)
--
-- web: http:--www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
-- Code Revision History :
-- --------------------------------------------------------------------
-- Ver: | Author |Mod. Date |Changes Made:
-- V1.0 |K.P. | 7/09 | Initial ver for VHDL
-- | converted from LSC ref design RD1046
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2c_master_byte_ctrl is
port (
clk : in std_logic; -- master clock
rst : in std_logic; -- synchronous active high reset
nReset : in std_logic; -- asynchronous active low reset
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- control inputs
start : in std_logic;
stop : in std_logic;
read : in std_logic;
write : in std_logic;
ack_in : in std_logic;
din : in std_logic_vector(7 downto 0);
-- status outputs
cmd_ack : out std_logic;
ack_out : out std_logic; -- i2c clock line input
dout : out std_logic_vector(7 downto 0);
i2c_al : in std_logic;
-- signals for bit_controller
core_cmd : out std_logic_vector(3 downto 0);
core_txd : out std_logic;
core_rxd : in std_logic;
core_ack : in std_logic
);
end;
architecture arch of i2c_master_byte_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "1000";
constant ST_IDLE : std_logic_vector(4 downto 0) := "00000";
constant ST_START : std_logic_vector(4 downto 0) := "00001";
constant ST_READ : std_logic_vector(4 downto 0) := "00010";
constant ST_WRITE : std_logic_vector(4 downto 0) := "00100";
constant ST_ACK : std_logic_vector(4 downto 0) := "01000";
constant ST_STOP : std_logic_vector(4 downto 0) := "10000";
signal c_state : std_logic_vector(4 downto 0);
signal go : std_logic;
signal dcnt : std_logic_vector(2 downto 0);
signal cnt_done : std_logic;
signal sr : std_logic_vector(7 downto 0); --8bit shift register
signal shift, ld : std_logic;
signal cmd_ack_int : std_logic;
begin
go <= '1' when (((read = '1') OR (write = '1') OR (stop = '1')) AND (cmd_ack_int = '0')) else '0';
dout <= sr;
-- generate shift register
process(clk,nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif rising_edge(clk) then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= sr(6 downto 0) & core_rxd;
end if;
end if;
end process;
-- generate counter
process(clk,nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif rising_edge(clk) then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= "111";
elsif (shift = '1') then
dcnt <= dcnt - '1';
end if;
end if;
end process;
cnt_done <= '1' when (dcnt = "000") else '0';
-- state machine
process(clk,nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
cmd_ack_int <= '0';
c_state <= ST_IDLE;
ack_out <= '0';
elsif rising_edge(clk) then
if ((rst = '1') OR (i2c_al = '1')) then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
cmd_ack_int <= '0';
c_state <= ST_IDLE;
ack_out <= '0';
else
-- initially reset all signals
core_txd <= sr(7);
shift <= '0';
ld <= '0';
cmd_ack_int <= '0';
case (c_state) is
when ST_IDLE =>
if (go = '1') then
if (start = '1') then
c_state <= ST_START;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= ST_READ;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= ST_WRITE;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= ST_STOP;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when ST_START =>
if (core_ack = '1') then
if (read = '1') then
c_state <= ST_READ;
core_cmd <= I2C_CMD_READ;
else
c_state <= ST_WRITE;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when ST_WRITE =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= ST_ACK;
core_cmd <= I2C_CMD_READ;
else
c_state <= ST_WRITE; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when ST_READ =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= ST_ACK;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= ST_READ; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
shift <= '1';
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when ST_ACK =>
if (core_ack = '1') then
if (stop = '1') then
c_state <= ST_STOP;
core_cmd <= I2C_CMD_STOP;
else
c_state <= ST_IDLE;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
cmd_ack_int <= '1';
end if;
-- assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when ST_STOP =>
if (core_ack = '1') then
c_state <= ST_IDLE;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
cmd_ack_int <= '1';
end if;
when others => NULL;
end case;
end if;
end if;
end process;
cmd_ack <= cmd_ack_int;
end arch;
|
-------------------------------------------------------------------------------
-- Title : Abstract Memory-Mapped Interface
-- Project :
-------------------------------------------------------------------------------
-- File : AbstractMmPkg.vhd
-- Author : Rob Gaddi <[email protected]>
-- Company : Highland Technology, Inc.
-- Created : 20-Nov-2017
-- Last update: 2017-11-25
-- Platform : Simulation
-- Standard : VHDL-2008
-------------------------------------------------------------------------------
-- Description: Support package for abstract memory-mapped interface BFMs.
-------------------------------------------------------------------------------
-- Revision History:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.AlertLogPkg.all;
use osvvm.TbUtilPkg.all;
use osvvm.ResolutionPkg.all;
package AbstractMmPkg is
-----------------------------------------------------------------------
-- Constants and Types
-----------------------------------------------------------------------
type AlertLogIDArrayType is array(integer range <>) of AlertLogIDType;
function alert_resolver(ta: AlertLogIDArrayType) return AlertLogIDType;
subtype ResolvedAlert is alert_resolver AlertLogIDType;
-- Transaction types
type TransactionType_unresolved is (
NONE,
SINGLE,
LINEAR_BURST,
CONSTANT_BURST,
CYCLE_BURST,
BURST_DATA,
PARAM
);
type TransactionArrayType is array(integer range <>) of TransactionType_unresolved;
function resolved(ta: TransactionArrayType) return TransactionType_unresolved;
subtype TransactionType is resolved TransactionType_unresolved;
type AbstractMmRecType is record
writedata : std_logic_vector;
readdata : std_logic_vector;
address : unsigned;
byteen : std_logic_vector;
write : std_logic;
burstlen : integer_max;
trans : TransactionType;
addressiswords : std_logic;
alert : ResolvedAlert;
rdy : std_logic;
ack : std_logic;
end record AbstractMmRecType;
constant AMR_READ: std_logic := '0';
constant AMR_WRITE: std_logic := '1';
constant AMR_ADDRESS_BYTES : std_logic := '0';
constant AMR_ADDRESS_WORDS : std_logic := '1';
constant ALRT : AlertLogIDType := GetAlertLogID("AbstractMmPkg");
-----------------------------------------------------------------------
-- Driver Functions
-----------------------------------------------------------------------
-- AmrRead (single read)
procedure AmrRead(
data: out std_logic_vector;
addr: in unsigned;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrRead(
data: out std_logic_vector;
addr: in std_logic_vector;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrRead(
data: out std_logic_vector;
addr: in natural;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrRead(
data: out std_logic_vector;
addr: in unsigned;
signal rec: inout AbstractMmRecType
);
procedure AmrRead(
data: out std_logic_vector;
addr: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrRead(
data: out std_logic_vector;
addr: in natural;
signal rec: inout AbstractMmRecType
);
-- AmrWrite (single write)
procedure AmrWrite(
data: in std_logic_vector;
addr: in unsigned;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrWrite(
data: in std_logic_vector;
addr: in std_logic_vector;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrWrite(
data: in std_logic_vector;
addr: in natural;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrWrite(
data: in std_logic_vector;
addr: in unsigned;
signal rec: inout AbstractMmRecType
);
procedure AmrWrite(
data: in std_logic_vector;
addr: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrWrite(
data: in std_logic_vector;
addr: in natural;
signal rec: inout AbstractMmRecType
);
-- AmrAssert (single assert)
procedure AmrAssert(
data: in std_logic_vector;
addr: in unsigned;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrAssert(
data: in std_logic_vector;
addr: in std_logic_vector;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrAssert(
data: in std_logic_vector;
addr: in natural;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrAssert(
data: in std_logic_vector;
addr: in unsigned;
signal rec: inout AbstractMmRecType
);
procedure AmrAssert(
data: in std_logic_vector;
addr: in std_logic_vector;
signal rec: inout AbstractMmRecType
);
procedure AmrAssert(
data: in std_logic_vector;
addr: in natural;
signal rec: inout AbstractMmRecType
);
-----------------------------------------------------------------------
-- Model Support Functions
-----------------------------------------------------------------------
procedure InterpretByteEnable(
rec : in AbstractMmRecType;
width : out natural;
align : out natural
);
function GetByteAddress(rec: in AbstractMmRecType; unalign: boolean := false) return unsigned;
function GetWordAddress(rec: in AbstractMmRecType) return unsigned;
-----------------------------------------------------------------------
-- Utility Functions
-----------------------------------------------------------------------
-- Initialization
procedure InitializeAmr(signal rec: out AbstractMmRecType);
-- function INIT_AMR(datalen, addrlen : positive) return AbstractMmRecType;
-- function INIT_AMR(datalen, addrlen, belen : positive) return AbstractMmRecType;
-- Selecting word/byte addressing
procedure SetAddressWords(signal rec: inout AbstractMmRecType);
procedure SetAddressBytes(signal rec: inout AbstractMmRecType);
-- Overriding the default alert
procedure OverrideAlert(signal rec: inout AbstractMmRecType; alert: AlertLogIDType);
end package AbstractMmPkg;
package body AbstractMmPkg is
procedure InitializeAmr(signal rec: out AbstractMmRecType) is
variable local : AbstractMmRecType(
writedata(rec.writedata'range),
readdata(rec.readdata'range),
address(rec.address'range),
byteen(rec.byteen'range)
);
constant WD : std_logic_vector(rec.writedata'range) := (others => 'Z');
constant RD : std_logic_vector(rec.readdata'range) := (others => 'Z');
constant AD : unsigned(rec.address'range) := (others => 'Z');
constant BE : std_logic_vector(rec.byteen'range) := (others => 'Z');
begin
local := (
writedata => WD,
readdata => RD,
address => AD,
byteen => BE,
write => 'Z',
burstlen => integer'left,
trans => NONE,
addressiswords => 'Z',
alert => ALRT,
rdy => 'Z',
ack => 'Z'
);
rec <= local;
end procedure InitializeAmr;
--function INIT_AMR(
-- datalen, addrlen : positive
--) return AbstractMmRecType is
-- constant belen : positive := datalen / 8;
--begin
-- return INIT_AMR(datalen, addrlen, belen);
--end function INIT_AMR;
--function INIT_AMR(
-- datalen, addrlen, belen: positive
--) return AbstractMmRecType is
--begin
-- return (
-- writedata => (datalen downto 1 => 'Z'),
-- readdata => (datalen downto 1 => 'Z'),
-- address => (addrlen downto 1 => 'Z'),
-- byteen => (belen downto 1 => 'Z'),
-- write => 'Z',
-- burstlen => integer'left,
-- trans => NONE,
-- addressiswords => 'Z',
-- alert => ALRT,
-- rdy => 'Z',
-- ack => 'Z'
-- );
--end function INIT_AMR;
procedure SetAddressWords(signal rec: inout AbstractMmRecType) is
begin
rec.addressiswords <= AMR_ADDRESS_WORDS;
end procedure SetAddressWords;
procedure SetAddressBytes(signal rec: inout AbstractMmRecType) is
begin
rec.addressiswords <= AMR_ADDRESS_BYTES;
end procedure SetAddressBytes;
-----------------------------------------------------------------------
-- AmrRead
-----------------------------------------------------------------------
procedure AmrRead(
data: out std_logic_vector;
addr: in unsigned;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
constant WD : std_logic_vector(rec.writedata'range) := (others => 'X');
begin
rec.writedata <= WD;
rec.address <= RESIZE(addr, rec.address'length);
rec.byteen <= byteen;
rec.write <= AMR_READ;
rec.burstlen <= 1;
rec.trans <= SINGLE;
RequestTransaction(rec.rdy, rec.ack);
data := rec.readdata;
end procedure AmrRead;
procedure AmrRead(
data: out std_logic_vector;
addr: in std_logic_vector;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
begin
AmrRead(data, UNSIGNED(addr), byteen, rec);
end procedure AmrRead;
procedure AmrRead(
data: out std_logic_vector;
addr: in natural;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
begin
AmrRead(data, TO_UNSIGNED(addr, rec.address'length), byteen, rec);
end procedure AmrRead;
procedure AmrRead(
data: out std_logic_vector;
addr: in unsigned;
signal rec: inout AbstractMmRecType
) is
variable byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrRead(data, addr, byteen, rec);
end procedure AmrRead;
procedure AmrRead(
data: out std_logic_vector;
addr: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
variable byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrRead(data, UNSIGNED(addr), byteen, rec);
end procedure AmrRead;
procedure AmrRead(
data: out std_logic_vector;
addr: in natural;
signal rec: inout AbstractMmRecType
) is
variable byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrRead(data, TO_UNSIGNED(addr, rec.address'length), byteen, rec);
end procedure AmrRead;
-----------------------------------------------------------------------
-- AmrWrite (single write)
-----------------------------------------------------------------------
procedure AmrWrite(
data: in std_logic_vector;
addr: in unsigned;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
begin
rec.writedata <= data;
rec.address <= RESIZE(addr, rec.address'length);
rec.byteen <= byteen;
rec.write <= AMR_WRITE;
rec.burstlen <= 1;
rec.trans <= SINGLE;
RequestTransaction(rec.rdy, rec.ack);
end procedure AmrWrite;
procedure AmrWrite(
data: in std_logic_vector;
addr: in std_logic_vector;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is begin
AmrWrite(data, UNSIGNED(addr), byteen, rec);
end procedure AmrWrite;
procedure AmrWrite(
data: in std_logic_vector;
addr: in natural;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is begin
AmrWrite(data, TO_UNSIGNED(addr, rec.address'length), byteen, rec);
end procedure AmrWrite;
procedure AmrWrite(
data: in std_logic_vector;
addr: in unsigned;
signal rec: inout AbstractMmRecType
) is
constant byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrWrite(data, addr, byteen, rec);
end procedure AmrWrite;
procedure AmrWrite(
data: in std_logic_vector;
addr: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
constant byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrWrite(data, UNSIGNED(addr), byteen, rec);
end procedure AmrWrite;
procedure AmrWrite(
data: in std_logic_vector;
addr: in natural;
signal rec: inout AbstractMmRecType
) is
constant byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrWrite(data, TO_UNSIGNED(addr, rec.address'length), byteen, rec);
end procedure AmrWrite;
-----------------------------------------------------------------------
-- AmrAssert (single assert)
-----------------------------------------------------------------------
procedure AmrAssert(
data: in std_logic_vector;
addr: in unsigned;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
variable readdata : std_logic_vector(data'range);
begin
AmrRead(readdata, addr, byteen, rec);
--AffirmIfEqual(rec.alert, readdata, data, "Assert @ 0x" & TO_HSTRING(addr));
end procedure AmrAssert;
procedure AmrAssert(
data: in std_logic_vector;
addr: in std_logic_vector;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is begin
AmrAssert(data, UNSIGNED(addr), byteen, rec);
end procedure AmrAssert;
procedure AmrAssert(
data: in std_logic_vector;
addr: in natural;
byteen: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is begin
AmrAssert(data, TO_UNSIGNED(addr, rec.address'length), byteen, rec);
end procedure AmrAssert;
procedure AmrAssert(
data: in std_logic_vector;
addr: in unsigned;
signal rec: inout AbstractMmRecType
) is
constant byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrAssert(data, addr, byteen, rec);
end procedure AmrAssert;
procedure AmrAssert(
data: in std_logic_vector;
addr: in std_logic_vector;
signal rec: inout AbstractMmRecType
) is
constant byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrAssert(data, UNSIGNED(addr), byteen, rec);
end procedure AmrAssert;
procedure AmrAssert(
data: in std_logic_vector;
addr: in natural;
signal rec: inout AbstractMmRecType
) is
constant byteen : std_logic_vector(rec.byteen'range) := (others => '1');
begin
AmrAssert(data, TO_UNSIGNED(addr, rec.address'length), byteen, rec);
end procedure AmrAssert;
-----------------------------------------------------------------------
-- Utility Functions
-----------------------------------------------------------------------
-- Turn a number into the number of bits needed to represent it.
function clog2(x : positive) return natural is
variable y : natural := 1;
begin
for log in 0 to 255 loop
if y >= x then
return log;
end if;
y := y * 2;
end loop;
return natural'right;
end function clog2;
-- Allow only 1 entry to be other than NONE.
function resolved(ta: TransactionArrayType) return TransactionType_unresolved is
variable r : TransactionType_unresolved := NONE;
variable t : TransactionType_unresolved;
begin
for idx in ta'range loop
t := ta(idx);
if t /= NONE then
assert r = NONE
report "Multiple non-NONE transaction types."
severity failure;
r := t;
end if;
end loop;
return r;
end function resolved;
-- Allow up to 1 entry to be other than our local ALRT, in which
-- case it wins.
function alert_resolver(ta: AlertLogIDArrayType) return AlertLogIDType is
variable r : AlertLogIDType := ALRT;
variable t : AlertLogIDType;
begin
for idx in ta'range loop
t := ta(idx);
if (t /= ALRT) and (t >= ALERTLOG_BASE_ID) then
assert r = ALRT
report "Multiple alerts provided."
severity failure;
r := t;
end if;
end loop;
return r;
end function alert_resolver;
procedure InterpretByteEnable(
rec : in AbstractMmRecType;
width : out natural;
align : out natural
) is
alias byteen : std_logic_vector(rec.byteen'range) is rec.byteen;
alias LA : AlertLogIDType is rec.alert;
variable first, last: integer;
variable found : boolean := false;
begin
if (and byteen) = '1' then
-- Try to provide fast resolution for the most common case.
width := byteen'length;
align := 0;
else
-- Alright, do it the hard way. Scan for contiguous enables.
for i in byteen'low to byteen'high loop
if byteen(i) = '1' then
found := true;
first := i;
exit;
end if;
end loop;
if not found then
-- No byte enables are set
Alert(LA, "No byte enables set.", WARNING);
width := 0;
align := 0;
else
last := first;
for i in first+1 to byteen'high loop
if byteen(i) = '1' then
last := i;
else
exit;
end if;
end loop;
if last /= byteen'high then
for i in last+1 to byteen'high loop
if byteen(i) = '1' then
Alert(LA, "Non-contiguous byte enables " & TO_STRING(byteen), WARNING);
exit;
end if;
end loop;
end if;
width := last-first+1;
align := first;
end if;
end if;
end procedure InterpretByteEnable;
function GetByteAddress(rec: in AbstractMmRecType; unalign: boolean := false) return unsigned is
variable padding : unsigned(clog2(rec.byteen'length)-1 downto 0);
variable alignment : integer := integer'left;
begin
case rec.addressiswords is
when AMR_ADDRESS_BYTES =>
return rec.address;
when AMR_ADDRESS_WORDS =>
if unalign then
for i in rec.byteen'low to rec.byteen'high loop
if rec.byteen(i) = '1' then
alignment := i;
exit;
end if;
end loop;
if alignment /= integer'left then
report "All bytes disabled." severity warning;
alignment := 0;
end if;
padding := TO_UNSIGNED(alignment, padding'length);
else
padding := (others => '0');
end if;
return rec.address & PADDING;
when others =>
report "Byte/word addressing not defined." severity failure;
return (rec.address'range => 'X');
end case;
end function GetByteAddress;
function GetWordAddress(rec: in AbstractMmRecType) return unsigned is
variable padding : unsigned(clog2(rec.byteen'length)-1 downto 0);
variable alignment, width : integer;
begin
case rec.addressiswords is
when AMR_ADDRESS_BYTES =>
return rec.address(rec.address'high downto padding'length);
when AMR_ADDRESS_WORDS =>
return rec.address;
when others =>
report "Byte/word addressing not defined." severity failure;
return (rec.address'range => 'X');
end case;
end function GetWordAddress;
procedure OverrideAlert(signal rec: inout AbstractMmRecType; alert: AlertLogIDType) is
begin
rec.alert <= alert;
end procedure OverrideAlert;
end package body AbstractMmPkg;
|
library IEEE;
use IEEE.std_logic_1164.all;
-- Barrel shifter de N bits (default = 4)
entity barrel_shifterNb is
-- Cantidad de bits
generic (N: NATURAL := 4);
port (
to_left : in std_logic;
M : in natural;
a : in std_logic_vector(N-1 downto 0);
o : out std_logic_vector(N-1 downto 0)
);
end;
architecture barrel_shifterNb_arq of barrel_shifterNb is
-- Señal con cada corrido posible simultáneamente
type t_shifts is array(natural range<>) of std_logic_vector(N-1 downto 0);
signal shs : t_shifts(0 to N);
begin
shs(0) <= a;
barrsh: for i in 1 to N generate
shs(i) <= shs(i-1)(N-2 downto 0) & '0' when to_left = '1' else -- Lleno
shs(i-1)(N-1) & shs(i-1)(N-1 downto 1); -- Extiendo
end generate;
-- Agarro el que quiero
o <= shs(M);
end barrel_shifterNb_arq;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
generic map(
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map
(
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2016
-- Thomas B. Preusser <[email protected]>
-------------------------------------------------------------------------------
-- This testbench is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
entity queens_slice_tb is
end queens_slice_tb;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture tb of queens_slice_tb is
constant L : natural := 2; -- pre-placed rings:
-- testbench only supports 2 currently
type tTest is record
cnt : positive;
bh : positive;
bv : positive;
bu : positive;
bd : positive;
end record tTest;
type tTests is array (natural range<>) of tTest;
function selectTests(s : positive) return tTests is
constant TESTS_8 : tTests := (
( 1 , 10,12,27,41),
( 1 , 10,12,82,25),
( 1 , 10,3,25,82),
( 1 , 10,3,41,27),
( 1 , 10,6,67,78),
( 1 , 10,6,78,67),
( 1 , 11,11,114,106),
( 1 , 11,11,116,102),
( 1 , 11,11,22,103),
( 1 , 11,11,23,102),
( 1 , 11,11,39,106),
( 1 , 11,11,49,108),
( 1 , 11,11,52,103),
( 1 , 11,11,70,108),
( 1 , 11,13,102,116),
( 1 , 11,13,102,23),
( 1 , 11,13,103,22),
( 1 , 11,13,103,52),
( 1 , 11,13,106,114),
( 1 , 11,13,106,39),
( 1 , 11,13,108,49),
( 1 , 11,13,108,70),
( 1 , 11,14,87,82),
( 1 , 11,7,82,87),
( 1 , 12,10,108,41),
( 1 , 12,10,37,25),
( 1 , 12,5,25,37),
( 1 , 12,5,41,108),
( 1 , 13,11,115,22),
( 1 , 13,11,115,52),
( 1 , 13,11,27,49),
( 1 , 13,11,27,70),
( 1 , 13,11,43,114),
( 1 , 13,11,43,39),
( 1 , 13,11,51,116),
( 1 , 13,11,51,23),
( 1 , 13,13,114,43),
( 1 , 13,13,116,51),
( 1 , 13,13,22,115),
( 1 , 13,13,23,51),
( 1 , 13,13,39,43),
( 1 , 13,13,49,27),
( 1 , 13,13,52,115),
( 1 , 13,13,70,27),
( 1 , 13,14,37,117),
( 1 , 13,7,117,37),
( 1 , 14,11,117,82),
( 1 , 14,13,82,117),
( 1 , 15,15,119,99),
( 1 , 15,15,99,119),
( 1 , 2,2,25,80),
( 1 , 2,2,76,80),
( 1 , 2,4,80,25),
( 1 , 2,4,80,76),
( 1 , 3,10,74,27),
( 1 , 3,10,76,82),
( 1 , 3,5,27,74),
( 1 , 3,5,82,76),
( 1 , 4,2,5,25),
( 1 , 4,2,5,76),
( 1 , 4,4,25,5),
( 1 , 4,4,76,5),
( 1 , 5,12,74,108),
( 1 , 5,12,76,37),
( 1 , 5,3,108,74),
( 1 , 5,3,37,76),
( 1 , 5,6,57,97),
( 1 , 5,6,97,57),
( 1 , 6,10,57,67),
( 1 , 6,10,97,78),
( 1 , 6,5,67,57),
( 1 , 6,5,78,97),
( 1 , 6,9,105,20),
( 1 , 6,9,106,88),
( 1 , 6,9,13,43),
( 1 , 6,9,20,105),
( 1 , 6,9,20,75),
( 1 , 6,9,43,13),
( 1 , 6,9,75,20),
( 1 , 6,9,88,106),
( 1 , 7,11,37,87),
( 1 , 7,13,87,37),
( 1 , 9,6,105,20),
( 1 , 9,6,106,13),
( 1 , 9,6,13,106),
( 1 , 9,6,20,105),
( 1 , 9,6,20,75),
( 1 , 9,6,43,88),
( 1 , 9,6,75,20),
( 1 , 9,6,88,43)
);
constant TESTS_9 : tTests := (
( 1 , 10,12,243,133),
( 1 , 10,12,243,257),
( 1 , 10,12,257,414),
( 1 , 10,12,322,414),
( 1 , 10,17,108,325),
( 1 , 10,17,325,108),
( 1 , 10,17,365,68),
( 1 , 10,17,68,365),
( 1 , 10,20,147,41),
( 1 , 10,20,149,281),
( 1 , 10,20,275,344),
( 1 , 10,20,296,402),
( 1 , 10,20,305,338),
( 1 , 10,20,53,401),
( 1 , 10,5,281,149),
( 1 , 10,5,338,305),
( 1 , 10,5,344,275),
( 1 , 10,5,401,53),
( 1 , 10,5,402,296),
( 1 , 10,5,41,147),
( 1 , 10,6,133,243),
( 1 , 10,6,257,243),
( 1 , 10,6,414,257),
( 1 , 10,6,414,322),
( 1 , 11,13,193,247),
( 1 , 11,13,199,181),
( 1 , 11,13,203,226),
( 1 , 11,13,449,181),
( 1 , 11,13,451,118),
( 1 , 11,14,167,211),
( 1 , 11,14,211,167),
( 1 , 11,14,211,417),
( 1 , 11,14,417,211),
( 1 , 11,19,452,109),
( 1 , 11,22,118,451),
( 1 , 11,22,181,199),
( 1 , 11,22,181,449),
( 1 , 11,22,226,203),
( 1 , 11,22,247,193),
( 1 , 11,25,109,452),
( 1 , 12,10,133,414),
( 1 , 12,10,257,414),
( 1 , 12,10,414,133),
( 1 , 12,10,414,257),
( 1 , 12,17,300,305),
( 1 , 12,17,305,300),
( 1 , 12,17,306,37),
( 1 , 12,17,37,306),
( 1 , 12,18,260,437),
( 1 , 12,18,284,389),
( 1 , 12,18,388,374),
( 1 , 12,20,237,259),
( 1 , 12,5,259,237),
( 1 , 12,9,374,388),
( 1 , 12,9,389,284),
( 1 , 12,9,437,260),
( 1 , 13,11,262,247),
( 1 , 13,11,263,181),
( 1 , 13,11,391,118),
( 1 , 13,11,422,226),
( 1 , 13,11,454,181),
( 1 , 13,19,138,174),
( 1 , 13,19,214,71),
( 1 , 13,19,313,420),
( 1 , 13,19,342,353),
( 1 , 13,21,133,379),
( 1 , 13,21,203,43),
( 1 , 13,21,205,331),
( 1 , 13,21,331,205),
( 1 , 13,21,334,355),
( 1 , 13,21,355,334),
( 1 , 13,21,379,133),
( 1 , 13,21,43,203),
( 1 , 13,25,174,138),
( 1 , 13,25,353,342),
( 1 , 13,25,420,313),
( 1 , 13,25,71,214),
( 1 , 13,26,118,391),
( 1 , 13,26,181,263),
( 1 , 13,26,181,454),
( 1 , 13,26,226,422),
( 1 , 13,26,247,262),
( 1 , 13,28,171,139),
( 1 , 13,28,323,477),
( 1 , 13,28,67,491),
( 1 , 13,7,139,171),
( 1 , 13,7,477,323),
( 1 , 13,7,491,67),
( 1 , 14,11,267,211),
( 1 , 14,11,406,167),
( 1 , 14,11,406,417),
( 1 , 14,11,458,211),
( 1 , 14,19,421,404),
( 1 , 14,19,83,331),
( 1 , 14,25,331,83),
( 1 , 14,25,404,421),
( 1 , 14,26,167,406),
( 1 , 14,26,211,267),
( 1 , 14,26,211,458),
( 1 , 14,26,417,406),
( 1 , 1,4,49,73),
( 1 , 1,4,73,49),
( 1 , 15,23,455,359),
( 1 , 15,29,359,455),
( 1 , 16,4,280,292),
( 1 , 16,4,292,280),
( 1 , 17,10,108,325),
( 1 , 17,10,325,108),
( 1 , 17,10,365,68),
( 1 , 17,10,68,365),
( 1 , 17,12,105,305),
( 1 , 17,12,153,37),
( 1 , 17,12,281,300),
( 1 , 17,12,328,306),
( 1 , 17,6,300,281),
( 1 , 17,6,305,105),
( 1 , 17,6,306,328),
( 1 , 17,6,37,153),
( 1 , 18,12,113,389),
( 1 , 18,12,65,437),
( 1 , 18,12,67,374),
( 1 , 18,20,165,25),
( 1 , 18,20,165,49),
( 1 , 18,24,101,356),
( 1 , 18,24,149,88),
( 1 , 18,3,356,101),
( 1 , 18,3,88,149),
( 1 , 18,5,25,165),
( 1 , 18,5,49,165),
( 1 , 18,6,374,67),
( 1 , 18,6,389,113),
( 1 , 18,6,437,65),
( 1 , 19,11,71,109),
( 1 , 19,13,162,174),
( 1 , 19,13,213,353),
( 1 , 19,13,214,71),
( 1 , 19,13,313,420),
( 1 , 19,14,331,404),
( 1 , 19,14,404,331),
( 1 , 19,21,181,204),
( 1 , 19,21,204,181),
( 1 , 19,22,174,162),
( 1 , 19,22,353,213),
( 1 , 19,22,420,313),
( 1 , 19,22,71,214),
( 1 , 19,26,109,71),
( 1 , 20,10,281,338),
( 1 , 20,10,338,281),
( 1 , 20,10,344,401),
( 1 , 20,10,401,344),
( 1 , 20,10,402,41),
( 1 , 20,10,41,402),
( 1 , 20,12,366,259),
( 1 , 20,18,330,25),
( 1 , 20,18,330,49),
( 1 , 20,6,259,366),
( 1 , 20,9,25,330),
( 1 , 20,9,49,330),
( 1 , 21,13,229,355),
( 1 , 21,13,322,379),
( 1 , 21,13,358,331),
( 1 , 21,13,397,334),
( 1 , 21,13,421,205),
( 1 , 21,13,422,43),
( 1 , 21,13,424,203),
( 1 , 21,13,445,133),
( 1 , 21,19,102,181),
( 1 , 21,19,346,204),
( 1 , 21,22,133,445),
( 1 , 21,22,203,424),
( 1 , 21,22,205,421),
( 1 , 21,22,331,358),
( 1 , 21,22,334,397),
( 1 , 21,22,355,229),
( 1 , 21,22,379,322),
( 1 , 21,22,43,422),
( 1 , 21,25,181,102),
( 1 , 21,25,204,346),
( 1 , 22,11,142,203),
( 1 , 22,11,220,451),
( 1 , 22,11,346,199),
( 1 , 22,11,346,449),
( 1 , 22,11,478,193),
( 1 , 22,19,234,162),
( 1 , 22,19,269,213),
( 1 , 22,19,452,214),
( 1 , 22,19,75,313),
( 1 , 22,21,229,397),
( 1 , 22,21,322,445),
( 1 , 22,21,358,421),
( 1 , 22,21,397,229),
( 1 , 22,21,421,358),
( 1 , 22,21,422,424),
( 1 , 22,21,424,422),
( 1 , 22,21,445,322),
( 1 , 22,25,162,234),
( 1 , 22,25,213,269),
( 1 , 22,25,214,452),
( 1 , 22,25,313,75),
( 1 , 22,26,193,478),
( 1 , 22,26,199,346),
( 1 , 22,26,203,142),
( 1 , 22,26,449,346),
( 1 , 22,26,451,220),
( 1 , 22,28,375,389),
( 1 , 22,28,418,426),
( 1 , 22,28,431,388),
( 1 , 22,7,388,431),
( 1 , 22,7,389,375),
( 1 , 22,7,426,418),
( 1 , 23,15,455,359),
( 1 , 23,23,103,423),
( 1 , 23,23,460,423),
( 1 , 23,29,423,103),
( 1 , 23,29,423,460),
( 1 , 23,30,359,455),
( 1 , 2,4,138,42),
( 1 , 24,18,332,356),
( 1 , 24,18,338,88),
( 1 , 2,4,42,138),
( 1 , 24,9,356,332),
( 1 , 24,9,88,338),
( 1 , 25,11,364,452),
( 1 , 25,13,234,138),
( 1 , 25,13,269,342),
( 1 , 25,13,452,214),
( 1 , 25,13,75,313),
( 1 , 25,14,421,83),
( 1 , 25,14,83,421),
( 1 , 25,21,102,346),
( 1 , 25,21,346,102),
( 1 , 25,22,138,234),
( 1 , 25,22,214,452),
( 1 , 25,22,313,75),
( 1 , 25,22,342,269),
( 1 , 25,26,452,364),
( 1 , 26,13,142,422),
( 1 , 26,13,220,391),
( 1 , 26,13,346,263),
( 1 , 26,13,346,454),
( 1 , 26,13,478,262),
( 1 , 26,14,267,406),
( 1 , 26,14,406,267),
( 1 , 26,14,406,458),
( 1 , 26,14,458,406),
( 1 , 26,19,364,71),
( 1 , 26,22,262,478),
( 1 , 26,22,263,346),
( 1 , 26,22,391,220),
( 1 , 26,22,422,142),
( 1 , 26,22,454,346),
( 1 , 26,25,71,364),
( 1 , 27,27,103,103),
( 1 , 27,27,103,460),
( 1 , 27,27,108,455),
( 1 , 27,27,198,365),
( 1 , 27,27,365,198),
( 1 , 27,27,455,108),
( 1 , 27,27,460,103),
( 1 , 27,27,460,460),
( 1 , 28,13,388,491),
( 1 , 28,13,389,477),
( 1 , 28,13,426,139),
( 1 , 28,22,139,426),
( 1 , 28,22,477,389),
( 1 , 28,22,491,388),
( 1 , 29,15,461,455),
( 1 , 29,23,459,103),
( 1 , 29,23,459,460),
( 1 , 29,29,103,459),
( 1 , 29,29,460,459),
( 1 , 29,30,455,461),
( 1 , 30,23,461,455),
( 1 , 30,29,455,461),
( 1 , 3,18,52,149),
( 1 , 3,18,77,101),
( 1 , 3,9,101,77),
( 1 , 3,9,149,52),
( 1 , 4,1,280,73),
( 1 , 4,1,292,49),
( 1 , 4,16,49,292),
( 1 , 4,16,73,280),
( 1 , 4,2,162,42),
( 1 , 4,2,168,138),
( 1 , 4,8,138,168),
( 1 , 4,8,42,162),
( 1 , 5,10,147,296),
( 1 , 5,10,149,305),
( 1 , 5,10,275,53),
( 1 , 5,10,296,147),
( 1 , 5,10,305,149),
( 1 , 5,10,53,275),
( 1 , 5,12,385,237),
( 1 , 5,18,280,165),
( 1 , 5,18,304,165),
( 1 , 5,6,237,385),
( 1 , 5,9,165,280),
( 1 , 5,9,165,304),
( 1 , 6,10,243,257),
( 1 , 6,10,243,322),
( 1 , 6,10,257,243),
( 1 , 6,10,322,243),
( 1 , 6,17,105,281),
( 1 , 6,17,153,328),
( 1 , 6,17,281,105),
( 1 , 6,17,328,153),
( 1 , 6,18,221,67),
( 1 , 6,18,323,113),
( 1 , 6,18,347,65),
( 1 , 6,20,385,366),
( 1 , 6,5,366,385),
( 1 , 6,9,113,323),
( 1 , 6,9,65,347),
( 1 , 6,9,67,221),
( 1 , 7,13,375,323),
( 1 , 7,13,418,171),
( 1 , 7,13,431,67),
( 1 , 7,22,171,418),
( 1 , 7,22,323,375),
( 1 , 7,22,67,431),
( 1 , 8,4,162,168),
( 1 , 8,4,168,162),
( 1 , 9,12,221,388),
( 1 , 9,12,323,284),
( 1 , 9,12,347,260),
( 1 , 9,20,280,330),
( 1 , 9,20,304,330),
( 1 , 9,24,52,338),
( 1 , 9,24,77,332),
( 1 , 9,3,332,77),
( 1 , 9,3,338,52),
( 1 , 9,5,330,280),
( 1 , 9,5,330,304),
( 1 , 9,6,260,347),
( 1 , 9,6,284,323),
( 1 , 9,6,388,221)
);
constant TESTS_11 : tTests := (
( 1 , 18,5,4424,167 ),
( 1 , 18,5,4676,5280 ),
( 1 , 18,5,6736,1160 ),
( 2 , 18,65,4256,676 ),
( 2 , 18,65,676,4256 ),
( 1 , 18,66,4232,708 ),
( 1 , 18,66,568,2193 ),
( 1 , 18,66,660,4177 ),
( 1 , 18,66,676,4672 ),
( 2 , 20,34,2570,680 ),
( 1 , 20,34,4369,5285 ),
( 1 , 20,34,4529,5125 ),
( 1 , 20,34,4618,708 ),
( 1 , 20,34,5125,4529 ),
( 1 , 20,34,5285,4369 ),
( 2 , 20,34,680,2570 ),
( 1 , 20,3,4688,167 ),
( 1 , 20,3,4688,646 ),
( 1 , 20,34,708,4618 ),
( 1 , 97,26,6409,2404 ),
( 1 , 97,28,4882,7330 ),
( 2 , 26,81,2374,4379 ),
( 1 , 26,81,2438,4395 ),
( 1 , 26,81,2441,2439 ),
( 1 , 26,81,3336,6371 ),
( 1 , 41,84,2318,203 ),
( 2 , 41,84,2326,4427 ),
( 1 , 44,81,6371,534 ),
( 1 , 44,81,6801,3122 ),
( 2 , 44,81,6929,3154 ),
( 1 , 44,81,7218,4658 ),
( 1 , 44,81,741,1038 ),
( 1 , 65,24,2145,2340 ),
( 2 , 65,36,4256,1192 ),
( 2 , 65,36,676,161 ),
( 1 , 65,40,2097,2224 ),
( 1 , 65,40,418,4482 ),
( 1 , 66,10,1232,1569 )
);
constant TESTS_12 : tTests := (
( 2 , 75,165,787,4891 ),
( 2 , 76,196,10914,21521 ),
( 2 , 76,35,21521,10914 ),
( 2 , 77,170,10531,5661 ),
( 2 , 77,85,5661,10531 ),
( 2 , 80,12,12648,20489 ),
( 3 , 80,12,24804,18438 ),
( 2 , 80,20,26784,22660 ),
( 2 , 80,40,22660,26784 ),
( 3 , 80,48,18438,24804 ),
( 2 , 80,48,20489,12648 ),
( 2 , 82,104,13857,18701 ),
( 2 , 82,168,7316,16458 ),
( 2 , 82,21,16458,7316 ),
( 2 , 82,22,18701,13857 ),
( 2 , 82,42,22532,18074 ),
( 2 , 82,74,13872,18693 ),
( 2 , 82,74,13872,20553 ),
( 2 , 82,82,18693,13872 ),
( 2 , 82,82,20553,13872 ),
( 2 , 82,84,18074,22532 ),
( 2 , 84,11,20805,2586 ),
( 2 , 84,137,22820,10337 ),
( 2 , 84,145,10337,22820 ),
( 2 , 84,162,9377,27684 ),
( 2 , 84,208,2586,20805 ),
( 2 , 84,69,27684,9377 ),
( 2 , 84,74,22532,11441 ),
( 2 , 84,82,11441,22532 ),
( 2 , 85,108,22042,11292 ),
( 2 , 85,178,10531,23604 ),
( 2 , 85,54,11292,22042 ),
( 2 , 85,77,23604,10531 ),
( 2 , 88,100,5149,10409 ),
( 2 , 88,38,10409,5149 ),
( 2 , 90,195,20805,9778 ),
( 2 , 90,195,9778,20805 ),
( 2 , 98,104,21777,11304 ),
( 2 , 98,148,4441,25106 ),
( 2 , 98,22,11304,21777 ),
( 2 , 98,41,25106,4441 ),
( 2 , 98,44,21785,18474 ),
( 2 , 98,52,18474,21785 ),
( 1 , 99,116,19754,21529 ),
( 1 , 99,120,15379,18740 ),
( 1 , 99,120,6419,27700 ),
( 1 , 99,150,26154,17701 ),
( 1 , 99,150,27696,6449 ),
( 1 , 99,150,28977,9769 ),
( 1 , 99,156,18701,23122 ),
( 1 , 99,165,17225,18713 ),
( 1 , 99,165,18713,17225 ),
( 1 , 99,170,25393,13353 ),
( 1 , 99,172,17677,27218 ),
( 1 , 99,172,22809,19017 ),
( 1 , 99,172,23576,27233 ),
( 1 , 99,180,13105,25626 ),
( 1 , 99,180,17677,27192 ),
( 1 , 99,180,19740,25129 ),
( 1 , 99,198,17177,17993 ),
( 1 , 99,198,17177,18737 ),
( 1 , 99,204,17176,27700 ),
( 1 , 99,204,4889,11313 ),
( 1 , 99,212,11801,4401 ),
( 1 , 99,212,11824,21554 ),
( 1 , 99,212,19760,21546 ),
( 1 , 99,212,3608,20787 ),
( 1 , 99,216,22050,19021 ),
( 1 , 99,27,19021,22050 ),
( 1 , 99,30,18740,15379 ),
( 1 , 99,30,27700,6419 ),
( 1 , 99,43,20787,3608 ),
( 1 , 99,43,21546,19760 ),
( 1 , 99,43,21554,11824 ),
( 1 , 99,43,4401,11801 ),
( 1 , 99,45,25129,19740 ),
( 1 , 99,45,25626,13105 )
);
begin
case s is
when 8 => return TESTS_8;
when 9 => return TESTS_9;
when 11 => return TESTS_11;
when 12 => return TESTS_12;
when others => null;
end case;
report "Unsupported problem size "&integer'image(s)&'.'
severity failure;
end;
component queens_slice
generic (
N : positive; -- size of field
L : positive -- number of preplaced columns
);
port (
clk : IN std_logic;
rst : IN std_logic;
start : IN std_logic;
BH_l : IN std_logic_vector(0 to N-2*L-1);
BU_l : IN std_logic_vector(0 to 2*N-4*L-2);
BD_l : IN std_logic_vector(0 to 2*N-4*L-2);
BV_l : IN std_logic_vector(0 to N-2*L-1);
sol : OUT std_logic;
done : OUT std_logic
);
end component;
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
genSizes: for s in 8 to 12 generate
genFilter: if s /= 10 generate
constant TESTS : tTests := selectTests(s);
--Inputs
signal clk : std_logic;
signal rst : std_logic;
signal start : std_logic;
signal bh : std_logic_vector(0 to s-2*L-1);
signal bv : std_logic_vector(0 to s-2*L-1);
signal bu : std_logic_vector(0 to 2*s-4*L-2);
signal bd : std_logic_vector(0 to 2*s-4*L-2);
--Outputs
signal sol : std_logic;
signal done : std_logic;
-- Test Control
signal nxt : boolean;
begin
dut: queens_slice
generic map (
N => s,
L => L
)
port map (
clk => clk,
rst => rst,
start => start,
BH_l => bh,
BV_l => bv,
BU_l => bu,
BD_l => bd,
sol => sol,
done => done
);
-- Stimuli
process
procedure cycle is
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end;
begin
rst <= '1';
cycle;
rst <= '0';
start <= '0';
cycle;
for i in TESTS'range loop
bh <= std_logic_vector(to_unsigned(TESTS(i).bh, bh'length));
bv <= std_logic_vector(to_unsigned(TESTS(i).bv, bv'length));
bu <= std_logic_vector(to_unsigned(TESTS(i).bu, bu'length));
bd <= std_logic_vector(to_unsigned(TESTS(i).bd, bd'length));
start <= '1';
cycle;
bh <= (others => '-');
bv <= (others => '-');
bu <= (others => '-');
bd <= (others => '-');
start <= '0';
loop
cycle;
exit when nxt;
end loop;
end loop;
wait; -- forever
end process;
-- Checker
process
variable err : natural;
variable cnt : natural;
begin
err := 0;
for i in TESTS'range loop
nxt <= true;
wait until rising_edge(clk) and start = '1';
nxt <= false;
cnt := 0;
loop
wait until rising_edge(clk);
if sol = '1' then
cnt := cnt + 1;
end if;
exit when done = '1';
end loop;
if cnt /= TESTS(i).cnt then
report "Result mismatch in test case #"&integer'image(i)&": "&
integer'image(TESTS(i).cnt)&" -> "&integer'image(cnt)
severity error;
err := err + 1;
end if;
end loop;
if err = 0 then
report "Test [N="&integer'image(s)&", L="&integer'image(L)&"] completed successfully." severity note;
else
report "Test [N="&integer'image(s)&", L="&integer'image(L)&"] completed with "&integer'image(err)&" ERRORS." severity note;
end if;
end process;
end generate;
end generate;
end tb;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for di_tnrc
--
-- Generated
-- by: lutscher
-- on: Tue Jun 23 14:19:39 2009
-- cmd: /home/lutscher/work/MIX/mix_1.pl di_tnr.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author$
-- $Id$
-- $Date$
-- $Log$
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.109 2008/04/01 12:48:34 wig Exp
--
-- Generator: mix_1.pl Version: Revision: 1.3 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration di_tnrc_struct_conf / di_tnrc
--
configuration di_tnrc_struct_conf of di_tnrc is
for struct
-- Generated Configuration
end for;
end di_tnrc_struct_conf;
--
-- End of Generated Configuration di_tnrc_struct_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21.09.2020 23:17:28
-- Design Name:
-- Module Name: buffered_spi_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity buffered_spi_tb is
-- Port ( );
end buffered_spi_tb;
architecture Behavioral of buffered_spi_tb is
component buffered_spi is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
avalon_read : in STD_LOGIC;
avalon_write : in STD_LOGIC;
avalon_address : in STD_LOGIC_VECTOR (13 downto 0);
avalon_waitrequest : out std_logic := '0';
avalon_writedata : in STD_LOGIC_VECTOR (15 downto 0);
avalon_readdata : out STD_LOGIC_VECTOR (15 downto 0);
avalon_readdatavalid : out std_logic := '0';
spi_mosi : out STD_LOGIC;
spi_clk : out STD_LOGIC;
spi_miso : in STD_LOGIC;
spi_cs : out STD_LOGIC);
end component;
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal avalon_read : std_logic := '0';
signal avalon_write : std_logic := '0';
signal avalon_waitrequest : std_logic := '0';
signal avalon_address : std_logic_vector(13 downto 0) := (others => '0');
signal avalon_writedata : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_readdata : std_logic_vector(15 downto 0) := (others => '0');
signal avalon_readdatavalid : std_logic := '0';
signal spi_mosi : std_logic := '0';
signal spi_clk : std_logic := '0';
signal spi_miso : std_logic := '0';
signal spi_cs : std_logic := '0';
procedure write_avalon_16 (addry : in std_logic_vector(13 downto 0);
datty : in std_logic_vector(15 downto 0);
signal Ava_Ad : out std_logic_vector(13 downto 0);
signal Ava_Da : out std_logic_vector(15 downto 0);
signal Ava_Wri : out std_logic
) is
begin
Ava_Ad <= addry;
Ava_Da <= datty;
wait for 10 ns;
Ava_Wri <= '1';
wait for 10 ns;
Ava_Wri <= '0';
wait for 10 ns;
end write_avalon_16;
procedure read_avalon_16 (addry : in std_logic_vector(13 downto 0);
signal Ava_Ad : out std_logic_vector(13 downto 0);
signal Ava_Re : out std_logic
) is
begin
Ava_Ad <= addry;
wait for 10 ns;
Ava_Re <= '1';
wait for 10 ns;
Ava_Re <= '0';
wait for 10 ns;
end read_avalon_16;
begin
--clock <= not clock after 4310 ps; --116 MHz clock
clock <= not clock after 5000 ps; --100 MHz clock
UUT: buffered_spi
port map(
clock => clock,
reset => reset,
avalon_read => avalon_read,
avalon_write => avalon_write,
avalon_address => avalon_address,
avalon_waitrequest => avalon_waitrequest,
avalon_writedata => avalon_writedata,
avalon_readdata => avalon_readdata,
avalon_readdatavalid => avalon_readdatavalid,
spi_mosi => spi_mosi,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_cs => spi_cs
);
process
begin
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for 300 ns;
reset <= '1';
wait for 300 ns;
--write
write_avalon_16("10"&X"001",X"0200",avalon_address,avalon_writedata,avalon_write); --len
wait for 100 ns;
--write_avalon_16("10"&X"003",X"0000",avalon_address,avalon_writedata,avalon_write); --cs
--write_avalon_16("10"&X"003",X"0010",avalon_address,avalon_writedata,avalon_write); --cs, /10 clock
--write_avalon_16("10"&X"003",X"0020",avalon_address,avalon_writedata,avalon_write); --cs, /12 clock
write_avalon_16("10"&X"003",X"0030",avalon_address,avalon_writedata,avalon_write); --cs, /16 clock
wait for 100 ns;
write_avalon_16("10"&X"004",X"0000",avalon_address,avalon_writedata,avalon_write); --delay
wait for 100 ns;
write_avalon_16("10"&X"005",X"0000",avalon_address,avalon_writedata,avalon_write); --bufselect
wait for 100 ns;
for i in 0 to 511 loop
write_avalon_16(std_logic_vector(to_unsigned(i,14)),std_logic_vector(to_unsigned(i*3,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+2048,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+4096,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
write_avalon_16(std_logic_vector(to_unsigned(i+6144,14)),std_logic_vector(to_unsigned(0,16)),avalon_address,avalon_writedata,avalon_write);
end loop;
wait for 100 ns;
--read
wait for 500 ns;
read_avalon_16("00"&X"312",avalon_address,avalon_read);
wait for 500 ns;
--start spi
write_avalon_16("10"&X"000",X"0001",avalon_address,avalon_writedata,avalon_write);
--toggle miso
for i in 0 to 5000 loop
spi_miso <= not spi_miso;
--wait for 320 ns;
wait for 160 ns;
end loop;
--switch to buf2
write_avalon_16("10"&X"005",X"0001",avalon_address,avalon_writedata,avalon_write); --bufselect
--start spi
write_avalon_16("10"&X"000",X"0001",avalon_address,avalon_writedata,avalon_write);
wait;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc608.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:42 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:01 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:20 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00608ent IS
END c03s04b01x00p01n01i00608ent;
ARCHITECTURE c03s04b01x00p01n01i00608arch OF c03s04b01x00p01n01i00608ent IS
constant C4 : severity_level := note;
type severity_level_vector is array (natural range <>) of severity_level;
subtype severity_level_vector_st is severity_level_vector(0 to 15);
type severity_level_vector_st_file is file of severity_level_vector_st;
constant C27 : severity_level_vector_st := (others => C4);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : severity_level_vector_st_file open read_mode is "iofile.29";
variable v : severity_level_vector_st;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C27) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00608"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00608 - File reading operation (severity_level_vector_st file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00608arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc608.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:42 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:01 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:20 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00608ent IS
END c03s04b01x00p01n01i00608ent;
ARCHITECTURE c03s04b01x00p01n01i00608arch OF c03s04b01x00p01n01i00608ent IS
constant C4 : severity_level := note;
type severity_level_vector is array (natural range <>) of severity_level;
subtype severity_level_vector_st is severity_level_vector(0 to 15);
type severity_level_vector_st_file is file of severity_level_vector_st;
constant C27 : severity_level_vector_st := (others => C4);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : severity_level_vector_st_file open read_mode is "iofile.29";
variable v : severity_level_vector_st;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C27) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00608"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00608 - File reading operation (severity_level_vector_st file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00608arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc608.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:42 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:01 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:20 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00608ent IS
END c03s04b01x00p01n01i00608ent;
ARCHITECTURE c03s04b01x00p01n01i00608arch OF c03s04b01x00p01n01i00608ent IS
constant C4 : severity_level := note;
type severity_level_vector is array (natural range <>) of severity_level;
subtype severity_level_vector_st is severity_level_vector(0 to 15);
type severity_level_vector_st_file is file of severity_level_vector_st;
constant C27 : severity_level_vector_st := (others => C4);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : severity_level_vector_st_file open read_mode is "iofile.29";
variable v : severity_level_vector_st;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C27) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00608"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00608 - File reading operation (severity_level_vector_st file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00608arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/17/2013 07:39:31 PM
-- Design Name:
-- Module Name: sdram_buffer_fifo_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY sdram_buffer_fifo_tb IS
END sdram_buffer_fifo_tb;
ARCHITECTURE Behavioral OF sdram_buffer_fifo_tb IS
CONSTANT INDATA_WIDTH : positive := 256;
CONSTANT OUTDATA_WIDTH : positive := 32;
CONSTANT APP_ADDR_WIDTH : positive := 5;
CONSTANT APP_DATA_WIDTH : positive := 512;
CONSTANT APP_MASK_WIDTH : positive := 64;
CONSTANT APP_ADDR_BURST : positive := 2;
COMPONENT sdram_buffer_fifo IS
GENERIC (
INDATA_WIDTH : positive := 128;
OUTDATA_WIDTH : positive := 32;
APP_ADDR_WIDTH : positive := 28;
APP_DATA_WIDTH : positive := 512;
APP_MASK_WIDTH : positive := 64;
APP_ADDR_BURST : positive := 8
);
PORT (
CLK : IN std_logic; -- MIG UI_CLK
RESET : IN std_logic;
--
APP_ADDR : OUT std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
APP_CMD : OUT std_logic_vector(2 DOWNTO 0);
APP_EN : OUT std_logic;
APP_RDY : IN std_logic;
APP_WDF_DATA : OUT std_logic_vector(APP_DATA_WIDTH-1 DOWNTO 0);
APP_WDF_END : OUT std_logic;
APP_WDF_MASK : OUT std_logic_vector(APP_MASK_WIDTH-1 DOWNTO 0);
APP_WDF_WREN : OUT std_logic;
APP_WDF_RDY : IN std_logic;
APP_RD_DATA : IN std_logic_vector(APP_DATA_WIDTH-1 DOWNTO 0);
APP_RD_DATA_END : IN std_logic;
APP_RD_DATA_VALID : IN std_logic;
--
CTRL_RESET : IN std_logic;
WR_START : IN std_logic;
WR_ADDR_BEGIN : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
WR_STOP : IN std_logic;
WR_WRAP_AROUND : IN std_logic;
POST_TRIGGER : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
WR_BUSY : OUT std_logic;
WR_POINTER : OUT std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
TRIGGER_POINTER : OUT std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
WR_WRAPPED : OUT std_logic;
RD_START : IN std_logic;
RD_ADDR_BEGIN : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
RD_ADDR_END : IN std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
RD_BUSY : OUT std_logic;
--
DATA_FIFO_RESET : IN std_logic;
INDATA_FIFO_WRCLK : IN std_logic;
INDATA_FIFO_Q : IN std_logic_vector(INDATA_WIDTH-1 DOWNTO 0);
INDATA_FIFO_FULL : OUT std_logic;
INDATA_FIFO_WREN : IN std_logic;
--
OUTDATA_FIFO_RDCLK : IN std_logic;
OUTDATA_FIFO_Q : OUT std_logic_vector(OUTDATA_WIDTH-1 DOWNTO 0);
OUTDATA_FIFO_EMPTY : OUT std_logic;
OUTDATA_FIFO_RDEN : IN std_logic
);
END COMPONENT;
SIGNAL CLK : std_logic := '0';
SIGNAL RESET : std_logic := '0';
--
SIGNAL APP_ADDR : std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
SIGNAL APP_CMD : std_logic_vector(2 DOWNTO 0);
SIGNAL APP_EN : std_logic;
SIGNAL APP_RDY : std_logic := '0';
SIGNAL APP_WDF_DATA : std_logic_vector(APP_DATA_WIDTH-1 DOWNTO 0);
SIGNAL APP_WDF_END : std_logic;
SIGNAL APP_WDF_MASK : std_logic_vector(APP_MASK_WIDTH-1 DOWNTO 0);
SIGNAL APP_WDF_WREN : std_logic;
SIGNAL APP_WDF_RDY : std_logic := '0';
SIGNAL APP_RD_DATA : std_logic_vector(APP_DATA_WIDTH-1 DOWNTO 0);
SIGNAL APP_RD_DATA_END : std_logic;
SIGNAL APP_RD_DATA_VALID : std_logic := '0';
--
SIGNAL CTRL_RESET : std_logic := '0';
SIGNAL WR_START : std_logic := '0';
SIGNAL WR_ADDR_BEGIN : std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
SIGNAL WR_STOP : std_logic := '0';
SIGNAL WR_WRAP_AROUND : std_logic := '0';
SIGNAL POST_TRIGGER : std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL WR_BUSY : std_logic := '0';
SIGNAL WR_POINTER : std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
SIGNAL TRIGGER_POINTER : std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
SIGNAL WR_WRAPPED : std_logic := '0';
SIGNAL RD_START : std_logic := '0';
SIGNAL RD_ADDR_BEGIN : std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
SIGNAL RD_ADDR_END : std_logic_vector(APP_ADDR_WIDTH-1 DOWNTO 0);
SIGNAL RD_BUSY : std_logic := '0';
--
SIGNAL DATA_FIFO_RESET : std_logic;
SIGNAL INDATA_FIFO_WRCLK : std_logic;
SIGNAL INDATA_FIFO_Q : std_logic_vector(INDATA_WIDTH-1 DOWNTO 0);
SIGNAL INDATA_FIFO_FULL : std_logic;
SIGNAL INDATA_FIFO_WREN : std_logic := '0';
--
SIGNAL OUTDATA_FIFO_RDCLK : std_logic;
SIGNAL OUTDATA_FIFO_Q : std_logic_vector(OUTDATA_WIDTH-1 DOWNTO 0);
SIGNAL OUTDATA_FIFO_EMPTY : std_logic := '0';
SIGNAL OUTDATA_FIFO_RDEN : std_logic := '0';
-- Clock period definitions
CONSTANT CLK_period : time := 5 ns;
CONSTANT INDATA_FIFO_WRCLK_period : time := 4 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : sdram_buffer_fifo
GENERIC MAP (
INDATA_WIDTH => INDATA_WIDTH,
OUTDATA_WIDTH => OUTDATA_WIDTH,
APP_ADDR_WIDTH => APP_ADDR_WIDTH,
APP_DATA_WIDTH => APP_DATA_WIDTH,
APP_MASK_WIDTH => APP_MASK_WIDTH,
APP_ADDR_BURST => APP_ADDR_BURST
)
PORT MAP (
CLK => CLK,
RESET => RESET,
--
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_RDY => APP_RDY,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_WDF_RDY => APP_WDF_RDY,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
--
CTRL_RESET => CTRL_RESET,
WR_START => WR_START,
WR_ADDR_BEGIN => WR_ADDR_BEGIN,
WR_STOP => WR_STOP,
WR_WRAP_AROUND => WR_WRAP_AROUND,
POST_TRIGGER => POST_TRIGGER,
WR_BUSY => WR_BUSY,
WR_POINTER => WR_POINTER,
TRIGGER_POINTER => TRIGGER_POINTER,
WR_WRAPPED => WR_WRAPPED,
RD_START => RD_START,
RD_ADDR_BEGIN => RD_ADDR_BEGIN,
RD_ADDR_END => RD_ADDR_END,
RD_BUSY => RD_BUSY,
--
DATA_FIFO_RESET => DATA_FIFO_RESET,
INDATA_FIFO_WRCLK => INDATA_FIFO_WRCLK,
INDATA_FIFO_Q => INDATA_FIFO_Q,
INDATA_FIFO_FULL => INDATA_FIFO_FULL,
INDATA_FIFO_WREN => INDATA_FIFO_WREN,
--
OUTDATA_FIFO_RDCLK => OUTDATA_FIFO_RDCLK,
OUTDATA_FIFO_Q => OUTDATA_FIFO_Q,
OUTDATA_FIFO_EMPTY => OUTDATA_FIFO_EMPTY,
OUTDATA_FIFO_RDEN => OUTDATA_FIFO_RDEN
);
-- Clock process definitions
CLK_process : PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_period/2;
CLK <= '1';
WAIT FOR CLK_period/2;
END PROCESS;
INDATA_FIFO_WRCLK_process : PROCESS
BEGIN
INDATA_FIFO_WRCLK <= '0';
WAIT FOR INDATA_FIFO_WRCLK_period/2;
INDATA_FIFO_WRCLK <= '1';
WAIT FOR INDATA_FIFO_WRCLK_period/2;
END PROCESS;
PROCESS (INDATA_FIFO_WRCLK, RESET)
BEGIN
IF RESET = '1' THEN
INDATA_FIFO_Q <= (OTHERS => '0');
ELSIF rising_edge(INDATA_FIFO_WRCLK) THEN
INDATA_FIFO_Q <= std_logic_vector(unsigned(INDATA_FIFO_Q) + 1);
END IF;
END PROCESS;
PROCESS (CLK, RESET)
BEGIN
IF RESET = '1' THEN
APP_RD_DATA <= (OTHERS => '0');
ELSIF rising_edge(CLK) THEN
APP_RD_DATA <= std_logic_vector(unsigned(APP_RD_DATA) + 1);
END IF;
END PROCESS;
OUTDATA_FIFO_RDEN <= '0';
-- Stimulus process
stim_proc : PROCESS
BEGIN
-- hold reset state
RESET <= '0';
WAIT FOR 15 ns;
RESET <= '1';
WAIT FOR CLK_period*3;
RESET <= '0';
WAIT FOR CLK_period*5;
--
WAIT FOR CLK_period*5;
INDATA_FIFO_WREN <= '1';
--
WAIT FOR CLK_period*20;
--
WR_WRAP_AROUND <= '1';
WAIT FOR CLK_period*0.8;
WR_ADDR_BEGIN <= "00010";
WR_START <= '1';
WAIT FOR CLK_period*2.2;
WR_START <= '0';
--
WAIT FOR CLK_period*2.5;
APP_RDY <= '1';
APP_WDF_RDY <= '1';
--
WAIT FOR CLK_period*5;
POST_TRIGGER <= "00110";
WAIT FOR CLK_period*0.8;
WR_STOP <= '1';
WAIT FOR CLK_period*2.2;
WR_STOP <= '0';
--
APP_WDF_RDY <= '1';
WAIT FOR CLK_period*14;
APP_RDY <= '0';
WAIT FOR CLK_period*5;
APP_RDY <= '0';
WAIT FOR CLK_period*1;
APP_RDY <= '0';
WAIT FOR CLK_period*1;
APP_RDY <= '1';
--
WAIT FOR CLK_period*10;
RD_ADDR_BEGIN <= "00010";
RD_ADDR_END <= "01110";
WAIT FOR CLK_period*5.8;
RD_START <= '1';
WAIT FOR CLK_period*2.2;
RD_START <= '0';
--
WAIT FOR CLK_period*5;
APP_RD_DATA_VALID <= '1' AFTER 0.1ns;
WAIT FOR CLK_period*0.8;
WR_STOP <= '1';
--WR_WRAP_AROUND <= '0';
--WR_START <= '1';
WAIT FOR CLK_period*2.2;
WR_STOP <= '0';
--WR_START <= '0';
APP_RD_DATA_VALID <= '0' AFTER 0.1ns;
--
WAIT FOR CLK_period*4;
APP_RD_DATA_VALID <= '1' AFTER 0.1ns;
--
WAIT;
END PROCESS;
END Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity STEP_MOD is
generic (
-- IO-REQ: 19 DWORD
WB_CONF_OFFSET: std_logic_vector(15 downto 2) := "00000000000000";
WB_CONF_DATA: std_logic_vector(15 downto 0) := "0000000000000101";
WB_ADDR_OFFSET: std_logic_vector(15 downto 2) := "00000000000000"
);
port (
OUT_EN: in std_logic;
IDLE: out std_logic;
WB_CLK: in std_logic;
WB_RST: in std_logic;
WB_ADDR: in std_logic_vector(15 downto 2);
WB_DATA_OUT: out std_logic_vector(31 downto 0);
WB_DATA_IN: in std_logic_vector(31 downto 0);
WB_STB_RD: in std_logic;
WB_STB_WR: in std_logic;
SV : inout std_logic_vector(10 downto 3)
);
end;
architecture rtl of STEP_MOD is
signal wb_data_mux : std_logic_vector(31 downto 0);
signal step_len: std_logic_vector(31 downto 0);
signal dir_hold_dly: std_logic_vector(31 downto 0);
signal dir_setup_dly: std_logic_vector(31 downto 0);
signal targetvel_a: std_logic_vector(31 downto 0);
signal deltalim_a: std_logic_vector(31 downto 0);
signal pos_capt_a: std_logic;
signal pos_hi_a: std_logic_vector(31 downto 0);
signal pos_lo_a: std_logic_vector(31 downto 0);
signal idle_a: std_logic;
signal targetvel_b: std_logic_vector(31 downto 0);
signal deltalim_b: std_logic_vector(31 downto 0);
signal pos_capt_b: std_logic;
signal pos_hi_b: std_logic_vector(31 downto 0);
signal pos_lo_b: std_logic_vector(31 downto 0);
signal idle_b: std_logic;
signal targetvel_c: std_logic_vector(31 downto 0);
signal deltalim_c: std_logic_vector(31 downto 0);
signal pos_capt_c: std_logic;
signal pos_hi_c: std_logic_vector(31 downto 0);
signal pos_lo_c: std_logic_vector(31 downto 0);
signal idle_c: std_logic;
signal targetvel_d: std_logic_vector(31 downto 0);
signal deltalim_d: std_logic_vector(31 downto 0);
signal pos_capt_d: std_logic;
signal pos_hi_d: std_logic_vector(31 downto 0);
signal pos_lo_d: std_logic_vector(31 downto 0);
signal idle_d: std_logic;
begin
----------------------------------------------------------
--- bus logic
----------------------------------------------------------
P_WB_RD : process(WB_ADDR)
begin
pos_capt_a <= '0';
pos_capt_b <= '0';
pos_capt_c <= '0';
pos_capt_d <= '0';
case WB_ADDR is
when WB_CONF_OFFSET =>
wb_data_mux(15 downto 0) <= WB_CONF_DATA;
wb_data_mux(31 downto 16) <= WB_ADDR_OFFSET & "00";
when WB_ADDR_OFFSET =>
wb_data_mux <= step_len;
when WB_ADDR_OFFSET + 1 =>
wb_data_mux <= dir_hold_dly;
when WB_ADDR_OFFSET + 2 =>
wb_data_mux <= dir_setup_dly;
when WB_ADDR_OFFSET + 3 =>
wb_data_mux <= targetvel_a;
when WB_ADDR_OFFSET + 4 =>
wb_data_mux <= deltalim_a;
when WB_ADDR_OFFSET + 5 =>
pos_capt_a <= WB_STB_RD;
wb_data_mux <= pos_hi_a;
when WB_ADDR_OFFSET + 6 =>
wb_data_mux <= pos_lo_a;
when WB_ADDR_OFFSET + 7 =>
wb_data_mux <= targetvel_b;
when WB_ADDR_OFFSET + 8 =>
wb_data_mux <= deltalim_b;
when WB_ADDR_OFFSET + 9 =>
pos_capt_b <= WB_STB_RD;
wb_data_mux <= pos_hi_b;
when WB_ADDR_OFFSET + 10 =>
wb_data_mux <= pos_lo_b;
when WB_ADDR_OFFSET + 11 =>
wb_data_mux <= targetvel_c;
when WB_ADDR_OFFSET + 12 =>
wb_data_mux <= deltalim_c;
when WB_ADDR_OFFSET + 13 =>
pos_capt_c <= WB_STB_RD;
wb_data_mux <= pos_hi_c;
when WB_ADDR_OFFSET + 14 =>
wb_data_mux <= pos_lo_c;
when WB_ADDR_OFFSET + 15 =>
wb_data_mux <= targetvel_d;
when WB_ADDR_OFFSET + 16 =>
wb_data_mux <= deltalim_d;
when WB_ADDR_OFFSET + 17 =>
pos_capt_d <= WB_STB_RD;
wb_data_mux <= pos_hi_d;
when WB_ADDR_OFFSET + 18 =>
wb_data_mux <= pos_lo_d;
when others =>
wb_data_mux <= (others => '0');
end case;
end process;
P_WB_RD_REG : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
WB_DATA_OUT <= (others => '0');
elsif rising_edge(WB_CLK) then
if WB_STB_RD = '1' then
WB_DATA_OUT <= wb_data_mux;
end if;
end if;
end process;
P_PE_REG_WR : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
step_len <= (others => '0');
dir_hold_dly <= (others => '0');
dir_setup_dly <= (others => '0');
targetvel_a <= (others => '0');
deltalim_a <= (others => '0');
targetvel_b <= (others => '0');
deltalim_b <= (others => '0');
targetvel_c <= (others => '0');
deltalim_c <= (others => '0');
targetvel_d <= (others => '0');
deltalim_d <= (others => '0');
elsif rising_edge(WB_CLK) then
if WB_STB_WR = '1' then
case WB_ADDR is
when WB_ADDR_OFFSET =>
step_len <= WB_DATA_IN;
when WB_ADDR_OFFSET + 1 =>
dir_hold_dly <= WB_DATA_IN;
when WB_ADDR_OFFSET + 2 =>
dir_setup_dly <= WB_DATA_IN;
when WB_ADDR_OFFSET + 3 =>
targetvel_a <= WB_DATA_IN;
when WB_ADDR_OFFSET + 4 =>
deltalim_a <= WB_DATA_IN;
when WB_ADDR_OFFSET + 7 =>
targetvel_b <= WB_DATA_IN;
when WB_ADDR_OFFSET + 8 =>
deltalim_b <= WB_DATA_IN;
when WB_ADDR_OFFSET + 11 =>
targetvel_c <= WB_DATA_IN;
when WB_ADDR_OFFSET + 12 =>
deltalim_c <= WB_DATA_IN;
when WB_ADDR_OFFSET + 15 =>
targetvel_d <= WB_DATA_IN;
when WB_ADDR_OFFSET + 16 =>
deltalim_d <= WB_DATA_IN;
when others =>
end case;
end if;
end if;
end process;
----------------------------------------------------------
--- stepgen instances
----------------------------------------------------------
IDLE <= idle_a and idle_b and idle_c and idle_d;
U_STEP_A: entity work.STEP_CHAN
port map (
RESET => WB_RST,
CLK => WB_CLK,
pos_capt => pos_capt_a,
pos_hi => pos_hi_a,
pos_lo => pos_lo_a,
targetvel => targetvel_a,
deltalim => deltalim_a,
step_len => step_len,
dir_hold_dly => dir_hold_dly,
dir_setup_dly => dir_setup_dly,
OUT_EN => OUT_EN,
IDLE => idle_a,
STP_OUT => SV(10),
STP_DIR => SV(9)
);
U_STEP_B: entity work.STEP_CHAN
port map (
RESET => WB_RST,
CLK => WB_CLK,
pos_capt => pos_capt_b,
pos_hi => pos_hi_b,
pos_lo => pos_lo_b,
targetvel => targetvel_b,
deltalim => deltalim_b,
step_len => step_len,
dir_hold_dly => dir_hold_dly,
dir_setup_dly => dir_setup_dly,
OUT_EN => OUT_EN,
IDLE => idle_b,
STP_OUT => SV(8),
STP_DIR => SV(7)
);
U_STEP_C: entity work.STEP_CHAN
port map (
RESET => WB_RST,
CLK => WB_CLK,
pos_capt => pos_capt_c,
pos_hi => pos_hi_c,
pos_lo => pos_lo_c,
targetvel => targetvel_c,
deltalim => deltalim_c,
step_len => step_len,
dir_hold_dly => dir_hold_dly,
dir_setup_dly => dir_setup_dly,
OUT_EN => OUT_EN,
IDLE => idle_c,
STP_OUT => SV(6),
STP_DIR => SV(5)
);
U_STEP_D: entity work.STEP_CHAN
port map (
RESET => WB_RST,
CLK => WB_CLK,
pos_capt => pos_capt_d,
pos_hi => pos_hi_d,
pos_lo => pos_lo_d,
targetvel => targetvel_d,
deltalim => deltalim_d,
step_len => step_len,
dir_hold_dly => dir_hold_dly,
dir_setup_dly => dir_setup_dly,
OUT_EN => OUT_EN,
IDLE => idle_d,
STP_OUT => SV(4),
STP_DIR => SV(3)
);
end;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Video_Memory_tb_checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.Video_Memory_TB_PKG.ALL;
ENTITY Video_Memory_TB_CHECKER IS
GENERIC (
WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END Video_Memory_TB_CHECKER;
ARCHITECTURE CHECKER_ARCH OF Video_Memory_TB_CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DGEN_INST:ENTITY work.Video_Memory_TB_DGEN
GENERIC MAP (
DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.logic_pkg.all;
architecture rtl of lfsr_inferred is
subtype state_type is std_ulogic_vector(state_bits-1 downto 0);
constant taps : state_type := lfsr_taps(state_bits);
type comb_type is record
state_next : state_type;
end record;
signal c : comb_type;
type reg_type is record
state : state_type;
end record;
signal r, r_next : reg_type;
begin
-- Galois style
state_next_gen : for n in state_bits-2 downto 0 generate
tap : if taps(n) = '1' generate
c.state_next(n) <= r.state(n+1) xor r.state(0);
end generate;
no_tap : if taps(n) = '0' generate
c.state_next(n) <= r.state(n+1);
end generate;
end generate;
c.state_next(state_bits-1) <= r.state(0);
with en select
r_next.state <= c.state_next when '1',
r.state when '0',
(others => 'X') when others;
output <= r.state(0);
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '1' =>
r <= r_next;
when '0' =>
r.state(0) <= '1';
r.state(state_bits-1 downto 1) <= (others => '0');
when others =>
r <= (state => (others => 'X'));
end case;
end if;
end process;
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_eb_fifo_counted_resized_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE k7_eb_fifo_counted_resized_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT k7_eb_fifo_counted_resized_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_eb_fifo_counted_resized_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_eb_fifo_counted_resized_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT k7_eb_fifo_counted_resized_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_eb_fifo_counted_resized_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_eb_fifo_counted_resized_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(15-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(15-1 DOWNTO 0);
VALID : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END k7_eb_fifo_counted_resized_pkg;
PACKAGE BODY k7_eb_fifo_counted_resized_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END k7_eb_fifo_counted_resized_pkg;
|
-------------------------------------------------------------------------
---- ----
---- Company: University of Bonn ----
---- Engineer: John Bieling ----
---- ----
-------------------------------------------------------------------------
---- ----
---- Copyright (C) 2015 John Bieling ----
---- ----
---- This program is free software; you can redistribute it and/or ----
---- modify it under the terms of the GNU General Public License as ----
---- published by the Free Software Foundation; either version 3 of ----
---- the License, or (at your option) any later version. ----
---- ----
---- This program is distributed in the hope that it will be useful, ----
---- but WITHOUT ANY WARRANTY; without even the implied warranty of ----
---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----
---- GNU General Public License for more details. ----
---- ----
---- You should have received a copy of the GNU General Public ----
---- License along with this program; if not, see ----
---- <http://www.gnu.org/licenses>. ----
---- ----
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity standard_fifo_poll is
Port (readrequest : in STD_LOGIC;
CLK : in STD_LOGIC;
fifo_data : in STD_LOGIC_VECTOR (31 downto 0);
fifo_read : out STD_LOGIC;
fifo_valid : in STD_LOGIC;
reset : in STD_LOGIC;
fifo_value : out STD_LOGIC_VECTOR (31 downto 0));
end standard_fifo_poll;
architecture Behavioral of standard_fifo_poll is
signal fifo_read_was_invalid : STD_LOGIC;
signal buffered_value : STD_LOGIC_VECTOR (31 downto 0);
signal pollstage : STD_LOGIC_VECTOR (3 downto 0);
begin
process (CLK) begin
if (rising_edge(CLK)) then
-- only in pollstage 0001 and if we need to get a new fifo value, we set fifo_read to 1, otherwise always 0
fifo_read <= '0';
if (reset = '1') then
pollstage <= "0000";
else
case pollstage is
-- idle state, initiate fifo_read if requested
when "0001" => if (readrequest = '1' OR fifo_read_was_invalid = '1') then
fifo_read <= '1';
pollstage <= "0010";
end if;
-- waitstate
when "0010" => pollstage <= "0100";
-- evaluate, if the read was valid
-- if so, put the read value into the output buffer
-- otherwise set the output buffer to zero
-- the fifo_read_was_invalid flag will cause the system to re-read the fifo
when "0100" => pollstage <= "1000";
if (fifo_valid = '1') then
buffered_value <= fifo_data;
fifo_read_was_invalid <= '0';
else
buffered_value <= (others => '0');
fifo_read_was_invalid <= '1';
end if;
-- buffered value contains the current fifo value (or empty if no value could be read)
-- we only overwrite the readout register, if there is no active read
when "1000" => if (readrequest = '0') then
fifo_value <= buffered_value;
pollstage <= "0001";
end if;
when others => pollstage <= "0001";
fifo_value <= (others => '0');
fifo_read_was_invalid <= '1';
end case;
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Top level for the OV7670 camera project.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ov7670_top is
Port (
clk100 : in STD_LOGIC;
OV7670_SIOC : out STD_LOGIC;
OV7670_SIOD : inout STD_LOGIC;
OV7670_RESET : out STD_LOGIC;
OV7670_PWDN : out STD_LOGIC;
OV7670_VSYNC : in STD_LOGIC;
OV7670_HREF : in STD_LOGIC;
OV7670_PCLK : in STD_LOGIC;
OV7670_XCLK : out STD_LOGIC;
OV7670_D : in STD_LOGIC_VECTOR(7 downto 0);
LED : out STD_LOGIC_VECTOR(7 downto 0);
vga_red : out STD_LOGIC_VECTOR(3 downto 0);
vga_green : out STD_LOGIC_VECTOR(3 downto 0);
vga_blue : out STD_LOGIC_VECTOR(3 downto 0);
vga_hsync : out STD_LOGIC;
vga_vsync : out STD_LOGIC;
btn : in STD_LOGIC
);
end ov7670_top;
architecture Behavioral of ov7670_top is
COMPONENT debounce
PORT(
clk : IN std_logic;
i : IN std_logic;
o : OUT std_logic
);
END COMPONENT;
component clocking
port
(-- Clock in ports
CLK_100 : in std_logic;
-- Clock out ports
CLK_50 : out std_logic;
CLK_25 : out std_logic
);
end component;
COMPONENT ov7670_controller
PORT(
clk : IN std_logic;
resend: IN std_logic;
config_finished : out std_logic;
siod : INOUT std_logic;
sioc : OUT std_logic;
reset : OUT std_logic;
pwdn : OUT std_logic;
xclk : OUT std_logic
);
END COMPONENT;
COMPONENT blk_mem_gen_0
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;
COMPONENT ov7670_capture
PORT(
pclk : IN std_logic;
vsync : IN std_logic;
href : IN std_logic;
d : IN std_logic_vector(7 downto 0);
addr : OUT std_logic_vector(18 downto 0);
dout : OUT std_logic_vector(11 downto 0);
we : OUT std_logic
);
END COMPONENT;
COMPONENT vga
PORT(
clk25 : IN std_logic;
vga_red : OUT std_logic_vector(3 downto 0);
vga_green : OUT std_logic_vector(3 downto 0);
vga_blue : OUT std_logic_vector(3 downto 0);
vga_hsync : OUT std_logic;
vga_vsync : OUT std_logic;
frame_addr : OUT std_logic_vector(18 downto 0);
frame_pixel : IN std_logic_vector(11 downto 0)
);
END COMPONENT;
signal frame_addr : std_logic_vector(18 downto 0);
signal frame_pixel : std_logic_vector(11 downto 0);
signal capture_addr : std_logic_vector(18 downto 0);
signal capture_data : std_logic_vector(11 downto 0);
signal capture_we : std_logic_vector(0 downto 0);
signal resend : std_logic;
signal config_finished : std_logic;
signal clk_feedback : std_logic;
signal clk50u : std_logic;
signal clk50 : std_logic;
signal clk25u : std_logic;
signal clk25 : std_logic;
signal buffered_pclk : std_logic;
begin
btn_debounce: debounce PORT MAP(
clk => clk50,
i => btn,
o => resend
);
Inst_vga: vga PORT MAP(
clk25 => clk25,
vga_red => vga_red,
vga_green => vga_green,
vga_blue => vga_blue,
vga_hsync => vga_hsync,
vga_vsync => vga_vsync,
frame_addr => frame_addr,
frame_pixel => frame_pixel
);
fb : blk_mem_gen_0
PORT MAP (
clka => OV7670_PCLK,
wea => capture_we,
addra => capture_addr,
dina => capture_data,
clkb => clk50,
addrb => frame_addr,
doutb => frame_pixel
);
led <= "0000000" & config_finished;
capture: ov7670_capture PORT MAP(
pclk => OV7670_PCLK,
vsync => OV7670_VSYNC,
href => OV7670_HREF,
d => OV7670_D,
addr => capture_addr,
dout => capture_data,
we => capture_we(0)
);
controller: ov7670_controller PORT MAP(
clk => clk50,
sioc => ov7670_sioc,
resend => resend,
config_finished => config_finished,
siod => ov7670_siod,
pwdn => OV7670_PWDN,
reset => OV7670_RESET,
xclk => OV7670_XCLK
);
your_instance_name : clocking
port map
(-- Clock in ports
CLK_100 => CLK100,
-- Clock out ports
CLK_50 => CLK50,
CLK_25 => CLK25);
end Behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RSL is port(
S : in std_logic;
R : in std_logic;
Q : out std_logic;
nQ : out std_logic
);
end RSL;
architecture structual of RSL is
component NOR2 is port(
a, b: in std_logic;
z: out std_logic);
end component;
component REP is port(
a: in std_logic;
z: out std_logic);
end component;
signal pointQ, pointNQ : std_logic;
begin
M1 : NOR2 port map (S, pointQ, pointNQ);
M2 : REP port map (pointNQ, nQ);
M3 : NOR2 port map (pointNQ, R, pointQ);
M4 : REP port map (pointQ, Q);
end structual; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity noc_interface is
generic(
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8;
use_vc : integer := 0
);
port(
--clk, reset
clk : in std_logic;
rst : in std_logic;
--user sending interface
send_data : in std_logic_vector(data_width-1 downto 0);
dest_addr : in std_logic_vector(addr_width-1 downto 0);
set_tail_flit : in std_logic;
send_flit : in std_logic;
ready_to_send : out std_logic;
--user receiving interface
recv_data : out std_logic_vector(data_width-1 downto 0);
src_addr : out std_logic_vector(addr_width-1 downto 0);
is_tail_flit : out std_logic;
data_in_buffer : out std_logic_vector(num_vc-1 downto 0);
dequeue : in std_logic_vector(num_vc-1 downto 0);
select_vc_read : in std_logic_vector(vc_sel_width-1 downto 0);
--interface to network
send_putFlit_flit_in : out std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
EN_send_putFlit : out std_logic;
EN_send_getNonFullVCs : out std_logic;
send_getNonFullVCs : in std_logic_vector(num_vc-1 downto 0);
EN_recv_getFlit : out std_logic;
recv_getFlit : in std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
recv_putNonFullVCs_nonFullVCs : out std_logic_vector(num_vc-1 downto 0);
EN_recv_putNonFullVCs : out std_logic;
recv_info_getRecvPortID : in std_logic_vector(addr_width-1 downto 0)
);
end entity noc_interface;
architecture structural of noc_interface is
--fifo buffer for reciving
component fifo_buffer is
generic(
word_len : integer := 64;
buff_len : integer := 8
);
port(
write_data : in std_logic_vector(word_len-1 downto 0);
read_data : out std_logic_vector(word_len-1 downto 0);
buffer_full : out std_logic;
buffer_empty : out std_logic;
enqueue : in std_logic;
dequeue : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component fifo_buffer;
type fifo_io is array(num_vc-1 downto 0) of std_logic_vector(vc_sel_width+data_width+addr_width+1 downto 0);
signal write_vc, read_vc: fifo_io;
signal buffer_full_vc, buffer_empty_vc, enqueue_vc, dequeue_vc: std_logic_vector(num_vc-1 downto 0);
signal receive_vc: std_logic_vector(vc_sel_width-1 downto 0);
-- priority encoder
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
signal selected_vc : std_logic_vector(vc_sel_width-1 downto 0);
--constants to parse flits
constant data_msb : integer := data_width-1;
constant data_lsb : integer := 0;
constant vc_msb : integer := vc_sel_width+data_width-1;
constant vc_lsb : integer := data_width;
constant addr_msb : integer := vc_sel_width+data_width+addr_width-1;
constant addr_lsb : integer := vc_sel_width+data_width;
constant is_tail_index : integer := vc_sel_width+data_width+addr_width;
constant is_valid_index : integer := vc_sel_width+data_width+addr_width+1;
constant flit_size : integer := vc_sel_width+data_width+addr_width+2;
begin
---------------------------------------------------------------------------
--RECEIVE SIDE ------------------------------------------------------------
---------------------------------------------------------------------------
-- create and map 1 buffer for each VC
receive_buffer: for i in num_vc-1 downto 0 generate
signal vc_select : integer;
signal flit_valid : std_logic;
begin
ur_i: fifo_buffer generic map(data_width+addr_width+vc_sel_width+2, flit_buff_depth)
port map(write_vc(i), read_vc(i), buffer_full_vc(i), buffer_empty_vc(i),
enqueue_vc(i), dequeue_vc(i), clk, rst);
vc_select <= to_integer(unsigned(recv_getFlit(vc_msb downto vc_lsb)));
flit_valid <= recv_getFlit(is_valid_index);
write_vc(i) <= recv_getFlit when i = vc_select else std_logic_vector(to_unsigned(0,flit_size));
enqueue_vc(i) <= flit_valid when i = vc_select else '0';
end generate;
-- IO for receive side of controller
EN_recv_getFlit <= '1'; -- always read to receive flits as long as buffers aren't full
recv_putNonFullVCs_nonFullVCs <= not buffer_full_vc;
data_in_buffer <= not buffer_empty_vc;
recv_data <= read_vc(to_integer(unsigned(select_vc_read)))(data_msb downto data_lsb);
dequeue_vc <= dequeue;
is_tail_flit <= read_vc(to_integer(unsigned(select_vc_read)))(is_tail_index);
src_addr <= read_vc(to_integer(unsigned(select_vc_read)))(addr_msb downto addr_lsb);
EN_recv_putNonFullVCs <= '1'; -- readme is not clear about what this does, assuming it is not need for peek flow control
---------------------------------------------------------------------------
--SEND SIDE ---------------------------------------------------------------
---------------------------------------------------------------------------
-------- priority encoder to determine which vc to use
------us_0: priority_encoder generic map(vc_sel_width)
------ port map(send_getNonFullVCs, selected_vc);
------
------
-------- IO for sending side of controller
------send_putFlit_flit_in <= send_flit & set_tail_flit & dest_addr & selected_vc & send_data;
--------ready_to_send <= '0' when to_integer(unsigned(send_getNonFullVCs)) = 0 else '1';
--------ready_to_send <= or_reduce(send_getNonFullVCs);
------EN_send_putFlit <= send_flit;
------EN_send_getNonFullVCs <= '1'; --always read to recieve credits
------
------
-- temp version which only sends on a selected vc
-- priority encoder to determine which vc to use
selected_vc <= std_logic_vector(to_unsigned(use_vc, vc_sel_width));
-- IO for sending side of controller
send_putFlit_flit_in <= send_flit & set_tail_flit & dest_addr & selected_vc & send_data;
ready_to_send <= send_getNonFullVCs(use_vc);
EN_send_putFlit <= send_flit;
EN_send_getNonFullVCs <= '1'; --always read to recieve credits
end architecture structural;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(11-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0);
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 256,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 10,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : pcie_data_rec_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
-----------------------------------------------------------------------------------------------------------
--
-- REGISTER FILE
--
-- The register file is a read/write memory, made up of 8 32-bit general purpose registers.
-- It can be addressed by different resources in a concurrent enviroment.
-- This model is a 3-read and 11-write ports
--
-- Created by Claudio Brunelli, 2004
--
-----------------------------------------------------------------------------------------------------------
--Copyright (c) 2004, Tampere University of Technology.
--All rights reserved.
--Redistribution and use in source and binary forms, with or without modification,
--are permitted provided that the following conditions are met:
--* Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--* Neither the name of Tampere University of Technology nor the names of its
-- contributors may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--THIS HARDWARE DESCRIPTION OR SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
--CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND NONINFRINGEMENT AND
--FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
--OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
--EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
--PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
--BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--ARISING IN ANY WAY OUT OF THE USE OF THIS HARDWARE DESCRIPTION OR SOFTWARE, EVEN
--IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.std_logic_1164.all;
use work.cop_definitions.all;
package milk_regfile is
component Milk_RFile
port( clk : in Std_logic;
reset : in Std_logic;
enable : in Std_logic;
coffee_out : out std_logic_vector(word_width-1 downto 0);
rs1 : in rf_addr;
rs1_out : out std_logic_vector(word_width-1 downto 0);
rs2 : in rf_addr;
rs2_out : out std_logic_vector(word_width-1 downto 0);
rcoffee_we : in std_logic;
rcoffee_in : in rf_addr;
coffee_in : in std_logic_vector(word_width-1 downto 0);
rd_we_1 : in std_logic;
rd_1 : in rf_addr;
d1_in : in std_logic_vector(word_width-1 downto 0);
rd_we_2 : in std_logic;
rd_2 : in rf_addr;
d2_in : in std_logic_vector(word_width-1 downto 0);
rd_we_3 : in std_logic;
rd_3 : in rf_addr;
d3_in : in std_logic_vector(word_width-1 downto 0);
rd_we_4 : in std_logic;
rd_4 : in rf_addr;
d4_in : in std_logic_vector(word_width-1 downto 0);
rd_we_5 : in std_logic;
rd_5 : in rf_addr;
d5_in : in std_logic_vector(word_width-1 downto 0);
rd_we_6 : in std_logic;
rd_6 : in rf_addr;
d6_in : in std_logic_vector(word_width-1 downto 0);
rd_we_7 : in std_logic;
rd_7 : in rf_addr;
d7_in : in std_logic_vector(word_width-1 downto 0);
rd_we_8 : in std_logic;
rd_8 : in rf_addr;
d8_in : in std_logic_vector(word_width-1 downto 0);
rd_we_9 : in std_logic;
rd_9 : in rf_addr;
d9_in : in std_logic_vector(word_width-1 downto 0);
next_lock_vector : in Std_logic_vector(RF_width-1 downto 0);
exc_doublewrite : out std_logic);
end component;
end milk_regfile;
package body milk_regfile is
end milk_regfile;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
use work.cop_components.all;
use work.milk_regfile.all;
entity Milk_Rfile is
port( clk : in Std_logic;
reset : in Std_logic;
enable : in Std_logic;
coffee_out : out std_logic_vector(word_width-1 downto 0);
rs1 : in rf_addr;
rs1_out : out std_logic_vector(word_width-1 downto 0);
rs2 : in rf_addr;
rs2_out : out std_logic_vector(word_width-1 downto 0);
rcoffee_we : in std_logic;
rcoffee_in : in rf_addr;
coffee_in : in std_logic_vector(word_width-1 downto 0);
rd_we_1 : in std_logic;
rd_1 : in rf_addr;
d1_in : in std_logic_vector(word_width-1 downto 0);
rd_we_2 : in std_logic;
rd_2 : in rf_addr;
d2_in : in std_logic_vector(word_width-1 downto 0);
rd_we_3 : in std_logic;
rd_3 : in rf_addr;
d3_in : in std_logic_vector(word_width-1 downto 0);
rd_we_4 : in std_logic;
rd_4 : in rf_addr;
d4_in : in std_logic_vector(word_width-1 downto 0);
rd_we_5 : in std_logic;
rd_5 : in rf_addr;
d5_in : in std_logic_vector(word_width-1 downto 0);
rd_we_6 : in std_logic;
rd_6 : in rf_addr;
d6_in : in std_logic_vector(word_width-1 downto 0);
rd_we_7 : in std_logic;
rd_7 : in rf_addr;
d7_in : in std_logic_vector(word_width-1 downto 0);
rd_we_8 : in std_logic;
rd_8 : in rf_addr;
d8_in : in std_logic_vector(word_width-1 downto 0);
rd_we_9 : in std_logic;
rd_9 : in rf_addr;
d9_in : in std_logic_vector(word_width-1 downto 0);
next_lock_vector : in Std_logic_vector(RF_width-1 downto 0);
exc_doublewrite : out std_logic );
end Milk_Rfile;
-----------------------------------------------------------------------------------
architecture rtl of Milk_Rfile is
type bus32x8 is array (7 downto 0) of Std_logic_vector(31 downto 0);
signal reg_in,reg_out : bus32x8;
signal coffeeout3,rs1out3,rs2out3 : std_logic_vector(word_width-1 downto 0);
signal wrbck_enabled_1,wrbck_enabled_2,wrbck_enabled_3,wrbck_enabled_4,
wrbck_enabled_5,wrbck_enabled_6,wrbck_enabled_7,wrbck_enabled_8,
wrbck_enabled_9,coffee_wr_enabled,
rd_8_1,rd_8_2,rd_8_3,rd_8_4,rd_8_5,rd_8_6,rd_8_7,rd_8_8,rd_8_9,rcoffee_in_8,
reg_we,wr_enable : std_logic_vector(RF_width-1 downto 0);
begin
----------------------------------------------------------
REGISTERS:for i in 0 to 7 generate
rx : we_register port map (clk => clk,reset => reset,we => wr_enable(i),
data_in => reg_in(i),data_out => reg_out(i) );
end generate Registers;
----------------------------------------------------------
-- Reg_file Reads from 3state busses
coffee_out <= coffeeout3;
rs1_out <= rs1out3;
rs2_out <= rs2out3;
----------------------------------------------------------
-- 3state bus handling:
COFFEEOUT_3STATEBUS: for i in 0 to 7 generate
process(rcoffee_in,reg_out,reg_in,reg_we,next_lock_vector)
begin
if ((i = Conv_integer(unsigned(rcoffee_in))) and (next_lock_vector(i) = '0')) then
if (reg_we(i) = '1') then
coffeeout3 <= reg_in(i);
else
coffeeout3 <= reg_out(i);
end if;
else
coffeeout3 <= (others => 'Z');
end if;
end process;
end generate COFFEEOUT_3STATEBUS;
RS1_3STATEBUS: for i in 0 to 7 generate
process(rs1,reg_out)
begin
if i = Conv_integer(unsigned(rs1)) then
rs1out3 <= reg_out(i);
else
rs1out3 <= (others => 'Z');
end if;
end process;
end generate RS1_3STATEBUS;
RS2_3STATEBUS: for i in 0 to 7 generate
process(rs2,reg_out)
begin
if i = Conv_integer(unsigned(rs2)) then
rs2out3 <= reg_out(i);
else
rs2out3 <= (others => 'Z');
end if;
end process;
end generate RS2_3STATEBUS;
----------------------------------------------------------
-- Reg_file writes. One is coming from the milk datapath
-- and one from Coffee
WRBCK_DATA_DEC_1: decoder3_8 port map(dec_addr => rd_1,dec_out => rd_8_1);
WRBCK_DATA_DEC_2: decoder3_8 port map(dec_addr => rd_2,dec_out => rd_8_2);
WRBCK_DATA_DEC_3: decoder3_8 port map(dec_addr => rd_3,dec_out => rd_8_3);
WRBCK_DATA_DEC_4: decoder3_8 port map(dec_addr => rd_4,dec_out => rd_8_4);
WRBCK_DATA_DEC_5: decoder3_8 port map(dec_addr => rd_5,dec_out => rd_8_5);
WRBCK_DATA_DEC_6: decoder3_8 port map(dec_addr => rd_6,dec_out => rd_8_6);
WRBCK_DATA_DEC_7: decoder3_8 port map(dec_addr => rd_7,dec_out => rd_8_7);
WRBCK_DATA_DEC_8: decoder3_8 port map(dec_addr => rd_8,dec_out => rd_8_8);
WRBCK_DATA_DEC_9: decoder3_8 port map(dec_addr => rd_9,dec_out => rd_8_9);
COFFEE_IN_DEC : decoder3_8 port map(dec_addr => rcoffee_in,dec_out => rcoffee_in_8);
REGFILE_WRITE : process(rd_8_1,rd_8_2,rd_8_3,rd_8_4,rd_8_5,rd_8_6,rd_8_7,rd_8_8,rd_8_9,rcoffee_in_8,
d1_in,d2_in,d3_in,d4_in,d5_in,d6_in,d7_in,d8_in,d9_in,coffee_in,
rd_we_1,rd_we_2,rd_we_3,rd_we_4,rd_we_5,rd_we_6,rd_we_7,rd_we_8,rd_we_9,rcoffee_we,
wrbck_enabled_1,wrbck_enabled_2,wrbck_enabled_3,wrbck_enabled_4,wrbck_enabled_5,wrbck_enabled_6,
wrbck_enabled_7,wrbck_enabled_8,wrbck_enabled_9,coffee_wr_enabled,
reg_we,enable)
begin
for i in 0 to 7 loop
wrbck_enabled_1(i) <= (rd_8_1(i) and rd_we_1);
wrbck_enabled_2(i) <= (rd_8_2(i) and rd_we_2);
wrbck_enabled_3(i) <= (rd_8_3(i) and rd_we_3);
wrbck_enabled_4(i) <= (rd_8_4(i) and rd_we_4);
wrbck_enabled_5(i) <= (rd_8_5(i) and rd_we_5);
wrbck_enabled_6(i) <= (rd_8_6(i) and rd_we_6);
wrbck_enabled_7(i) <= (rd_8_7(i) and rd_we_7);
wrbck_enabled_8(i) <= (rd_8_8(i) and rd_we_8);
wrbck_enabled_9(i) <= (rd_8_9(i) and rd_we_9);
coffee_wr_enabled(i) <= (rcoffee_in_8(i) and rcoffee_we);
reg_we(i) <= ( coffee_wr_enabled(i) or wrbck_enabled_1(i) or wrbck_enabled_2(i) or wrbck_enabled_3(i) or
wrbck_enabled_4(i) or wrbck_enabled_5(i) or wrbck_enabled_6(i) or wrbck_enabled_7(i)
or wrbck_enabled_8(i) or wrbck_enabled_9(i));
wr_enable(i) <= ( enable and reg_we(i) );
if ( wrbck_enabled_1(i) = '1' ) then
reg_in(i) <= d1_in;
elsif ( wrbck_enabled_2(i) = '1' ) then
reg_in(i) <= d2_in;
elsif ( wrbck_enabled_3(i) = '1' ) then
reg_in(i) <= d3_in;
elsif ( wrbck_enabled_4(i) = '1' ) then
reg_in(i) <= d4_in;
elsif ( wrbck_enabled_5(i) = '1' ) then
reg_in(i) <= d5_in;
elsif ( wrbck_enabled_6(i) = '1' ) then
reg_in(i) <= d6_in;
elsif ( wrbck_enabled_7(i) = '1' ) then
reg_in(i) <= d7_in;
elsif ( wrbck_enabled_8(i) = '1' ) then
reg_in(i) <= d8_in;
elsif ( wrbck_enabled_9(i) = '1' ) then
reg_in(i) <= d9_in;
else
reg_in(i) <= coffee_in;
end if;
end loop;
end process;
exc_doublewrite <= '0';
end rtl;
|
entity tb_insert01 is
end tb_insert01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_insert01 is
signal a : std_logic_vector (3 downto 0);
signal b : std_logic;
signal o0, o1, o2, o3 : std_logic_vector (3 downto 0);
begin
dut: entity work.insert01
port map (a, b, o0, o1, o2, o3);
process
begin
a <= "0111";
b <= '0';
wait for 1 ns;
assert o0 = "0110" severity failure;
assert o1 = "0101" severity failure;
assert o2 = "0011" severity failure;
assert o3 = "0111" severity failure;
wait;
end process;
end behav;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use WORK.useful_functions_pkg.all;
entity regfile is
generic (
NWP : integer := 2;
NRP : integer := 3;
AW : integer := 10;
DW : integer := 16
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
we_v : in std_logic_vector(NWP-1 downto 0);
re_v : in std_logic_vector(NRP-1 downto 0);
waddr_v : in std_logic_vector(NWP*AW-1 downto 0);
raddr_v : in std_logic_vector(NRP*AW-1 downto 0);
input_data_v : in std_logic_vector(NWP*DW-1 downto 0);
ram_output_v : out std_logic_vector(NRP*DW-1 downto 0)
);
end regfile;
architecture rtl of regfile is
component regfile_core
generic (
AW : integer := 5;
DW : integer := 32
);
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
we : in std_logic;
re : in std_logic;
waddr : in std_logic_vector(AW-1 downto 0);
raddr : in std_logic_vector(AW-1 downto 0);
input_data : in std_logic_vector(DW-1 downto 0);
ram_output : out std_logic_vector(DW-1 downto 0)
);
end component;
constant NREGS : integer := 2**AW;
type banksel_type is array (NRP-1 downto 0) of std_logic_vector(log2c(NWP)-1 downto 0);
signal banksel_v : std_logic_vector(NRP*log2c(NWP)-1 downto 0);
signal ia_sel : banksel_type;
signal ram_output_i : std_logic_vector((NRP*NWP*DW)-1 downto 0);
begin
nwp_nrp_bram_instance_0 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(0),
re => re_v(0),
waddr => waddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
raddr => raddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
input_data => input_data_v(DW*(0+1)-1 downto DW*0),
ram_output => ram_output_i(DW*((0*NRP+0)+1)-1 downto DW*(0*NRP+0))
);
nwp_nrp_bram_instance_3 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(1),
re => re_v(0),
waddr => waddr_v(AW*(1+1)-log2c(NWP)-1 downto AW*1),
raddr => raddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
input_data => input_data_v(DW*(1+1)-1 downto DW*1),
ram_output => ram_output_i(DW*((1*NRP+0)+1)-1 downto DW*(1*NRP+0))
);
nwp_nrp_bram_instance_1 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(0),
re => re_v(1),
waddr => waddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
raddr => raddr_v(AW*(1+1)-log2c(NWP)-1 downto AW*1),
input_data => input_data_v(DW*(0+1)-1 downto DW*0),
ram_output => ram_output_i(DW*((0*NRP+1)+1)-1 downto DW*(0*NRP+1))
);
nwp_nrp_bram_instance_4 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(1),
re => re_v(1),
waddr => waddr_v(AW*(1+1)-log2c(NWP)-1 downto AW*1),
raddr => raddr_v(AW*(1+1)-log2c(NWP)-1 downto AW*1),
input_data => input_data_v(DW*(1+1)-1 downto DW*1),
ram_output => ram_output_i(DW*((1*NRP+1)+1)-1 downto DW*(1*NRP+1))
);
nwp_nrp_bram_instance_2 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(0),
re => re_v(2),
waddr => waddr_v(AW*(0+1)-log2c(NWP)-1 downto AW*0),
raddr => raddr_v(AW*(2+1)-log2c(NWP)-1 downto AW*2),
input_data => input_data_v(DW*(0+1)-1 downto DW*0),
ram_output => ram_output_i(DW*((0*NRP+2)+1)-1 downto DW*(0*NRP+2))
);
nwp_nrp_bram_instance_5 : entity WORK.regfile_core(READ_ASYNC)
generic map (
AW => AW-log2c(NWP),
DW => DW
)
port map (
clock => clock,
reset => reset,
enable => enable,
we => we_v(1),
re => re_v(2),
waddr => waddr_v(AW*(1+1)-log2c(NWP)-1 downto AW*1),
raddr => raddr_v(AW*(2+1)-log2c(NWP)-1 downto AW*2),
input_data => input_data_v(DW*(1+1)-1 downto DW*1),
ram_output => ram_output_i(DW*((1*NRP+2)+1)-1 downto DW*(1*NRP+2))
);
banksel_v(log2c(NWP)*(0+1)-1 downto log2c(NWP)*0) <= raddr_v(AW*(0+1)-1 downto AW*(0+1)-log2c(NWP));
banksel_v(log2c(NWP)*(1+1)-1 downto log2c(NWP)*1) <= raddr_v(AW*(1+1)-1 downto AW*(1+1)-log2c(NWP));
banksel_v(log2c(NWP)*(2+1)-1 downto log2c(NWP)*2) <= raddr_v(AW*(2+1)-1 downto AW*(2+1)-log2c(NWP));
process (ram_output_i, banksel_v)
variable ia_sel_part : integer range 0 to NWP-1;
begin
ia_sel(0) <= banksel_v(log2c(NWP)*(0+1)-1 downto log2c(NWP)*0);
ia_sel_part := conv_integer(ia_sel(0));
case ia_sel_part is
when 0 => ram_output_v(DW*(0+1)-1 downto DW*0) <= ram_output_i(DW*(0+0*NRP+1)-1 downto DW*(0+0*NRP));
when 1 => ram_output_v(DW*(0+1)-1 downto DW*0) <= ram_output_i(DW*(0+1*NRP+1)-1 downto DW*(0+1*NRP));
when others => ram_output_v(DW*(0+1)-1 downto DW*0) <= (others => '0');
end case;
end process;
process (ram_output_i, banksel_v)
variable ia_sel_part : integer range 0 to NWP-1;
begin
ia_sel(1) <= banksel_v(log2c(NWP)*(1+1)-1 downto log2c(NWP)*1);
ia_sel_part := conv_integer(ia_sel(1));
case ia_sel_part is
when 0 => ram_output_v(DW*(1+1)-1 downto DW*1) <= ram_output_i(DW*(1+0*NRP+1)-1 downto DW*(1+0*NRP));
when 1 => ram_output_v(DW*(1+1)-1 downto DW*1) <= ram_output_i(DW*(1+1*NRP+1)-1 downto DW*(1+1*NRP));
when others => ram_output_v(DW*(1+1)-1 downto DW*1) <= (others => '0');
end case;
end process;
process (ram_output_i, banksel_v)
variable ia_sel_part : integer range 0 to NWP-1;
begin
ia_sel(2) <= banksel_v(log2c(NWP)*(2+1)-1 downto log2c(NWP)*2);
ia_sel_part := conv_integer(ia_sel(2));
case ia_sel_part is
when 0 => ram_output_v(DW*(2+1)-1 downto DW*2) <= ram_output_i(DW*(2+0*NRP+1)-1 downto DW*(2+0*NRP));
when 1 => ram_output_v(DW*(2+1)-1 downto DW*2) <= ram_output_i(DW*(2+1*NRP+1)-1 downto DW*(2+1*NRP));
when others => ram_output_v(DW*(2+1)-1 downto DW*2) <= (others => '0');
end case;
end process;
end rtl;
|
entity wait20 is
end entity;
architecture test of wait20 is
signal x : bit_vector(1 to 3);
begin
main: process is
begin
x <= "010" after 2 ns, "101" after 4 ns, "111" after 6 ns;
wait on x(2) for 10 ns; -- Splits the nexus
assert now = 2 ns;
assert x = "010";
wait for 3 ns;
assert x = "101";
wait for 2 ns;
assert x = "111";
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
package ARITHMETIC is
-- integer definitions
type t_int is range -2 ** 20 to 2 ** 20 ;
subtype st_int is t_int range 2 ** 15 downto -2 ** 20 ;
subtype intt is integer range -2 ** 20 to 2 ** 20 ;
subtype intst is integer range 2 ** 15 downto -2 ** 20 ;
constant c_int_1 : integer := 10 ;
constant c_int_2 : integer := -7 ;
constant c_t_int_1 : t_int := 500 ;
constant c_intt_1 : intt := 500 ;
constant c_t_int_2 : t_int := -3 ;
constant c_intt_2 : intt := -3 ;
constant c_st_int_1 : st_int := 5 ;
constant c_intst_1 : intst := 5 ;
constant c_st_int_2 : st_int := -400 ;
constant c_intst_2 : intst := -400 ;
constant ans_int1 : integer := 0 ;
constant ans_int2 : t_int := 7 ;
constant ans_int3 : st_int := -5 ;
-- physical type definitions
type t_phys is range -2 ** 20 to 2 ** 20
units
ones ;
tens = 10 ones ;
hundreds = 10 tens ;
five_hundreds = 50 tens ;
end units ;
subtype st_phys is t_phys range 2 ** 15 * ones downto -2 ** 20 * ones ;
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 10 fs ;
constant c_t_phys_1 : t_phys := 5 hundreds ;
constant c_t_phys_2 : t_phys := (-3) * ones ;
constant c_st_phys_1 : st_phys := 5 ones ;
constant c_st_phys_2 : st_phys := (-4) * 10 ones ;
constant ans_phys1 : time := 999990 fs ;
constant ans_phys2 : t_phys := 7 ones ;
constant ans_phys3 : t_phys := -5 * 1 ones ;
-- real
type t_real is range -2.0E20 to 2.0E20 ;
subtype st_real is t_real range 2.0E15 downto -2.0E20 ;
subtype realt is real range -2.0E20 to 2.0E20 ;
subtype realst is real range 2.0E15 downto -2.0E20 ;
constant c_real_1 : real := 10.5 ;
constant c_real_2 : real := -7.3 ;
constant c_t_real_1 : t_real := 500.0 ;
constant c_realt_1 : realt := 500.0 ;
constant c_t_real_2 : t_real := -3.5 ;
constant c_realt_2 : realt := -3.5 ;
constant c_st_real_1 : st_real := 5.9 ;
constant c_realst_1 : realst := 5.9 ;
constant c_st_real_2 : st_real := -400.1 ;
constant c_realst_2 : realst := -400.1 ;
constant ans_real1 : real := 0.0 ;
constant ans_real2 : t_real := 9.0 ;
constant ans_real3 : t_real := -6.8 ;
constant acceptable_error : real := 0.001 ;
constant t_acceptable_error : t_real := 0.001 ;
end ARITHMETIC ;
|
entity SUB is
port (I:in integer;O:out integer);
end SUB;
architecture MODEL of SUB is
begin
process(I)
procedure PROC_A(I:in integer;O:out integer) is
procedure PROC_B(I:in integer;O:out integer) is
begin
O := I+1;
end procedure;
begin
PROC_B(I,O);
end procedure;
begin
PROC_A(I,O);
end process;
end MODEL;
entity TOP is
end TOP;
architecture MODEL of TOP is
component SUB is
port (I:in integer;O:out integer);
end component;
signal A_I, A_O : integer;
signal B_I, B_O : integer;
begin
A: SUB port map(I => A_I, O => A_O);
B: SUB port map(I => B_I, O => B_O);
end MODEL;
|
entity SUB is
port (I:in integer;O:out integer);
end SUB;
architecture MODEL of SUB is
begin
process(I)
procedure PROC_A(I:in integer;O:out integer) is
procedure PROC_B(I:in integer;O:out integer) is
begin
O := I+1;
end procedure;
begin
PROC_B(I,O);
end procedure;
begin
PROC_A(I,O);
end process;
end MODEL;
entity TOP is
end TOP;
architecture MODEL of TOP is
component SUB is
port (I:in integer;O:out integer);
end component;
signal A_I, A_O : integer;
signal B_I, B_O : integer;
begin
A: SUB port map(I => A_I, O => A_O);
B: SUB port map(I => B_I, O => B_O);
end MODEL;
|
entity SUB is
port (I:in integer;O:out integer);
end SUB;
architecture MODEL of SUB is
begin
process(I)
procedure PROC_A(I:in integer;O:out integer) is
procedure PROC_B(I:in integer;O:out integer) is
begin
O := I+1;
end procedure;
begin
PROC_B(I,O);
end procedure;
begin
PROC_A(I,O);
end process;
end MODEL;
entity TOP is
end TOP;
architecture MODEL of TOP is
component SUB is
port (I:in integer;O:out integer);
end component;
signal A_I, A_O : integer;
signal B_I, B_O : integer;
begin
A: SUB port map(I => A_I, O => A_O);
B: SUB port map(I => B_I, O => B_O);
end MODEL;
|
entity SUB is
port (I:in integer;O:out integer);
end SUB;
architecture MODEL of SUB is
begin
process(I)
procedure PROC_A(I:in integer;O:out integer) is
procedure PROC_B(I:in integer;O:out integer) is
begin
O := I+1;
end procedure;
begin
PROC_B(I,O);
end procedure;
begin
PROC_A(I,O);
end process;
end MODEL;
entity TOP is
end TOP;
architecture MODEL of TOP is
component SUB is
port (I:in integer;O:out integer);
end component;
signal A_I, A_O : integer;
signal B_I, B_O : integer;
begin
A: SUB port map(I => A_I, O => A_O);
B: SUB port map(I => B_I, O => B_O);
end MODEL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc832.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s03b00x00p02n01i00832ent IS
END c01s03b00x00p02n01i00832ent;
ARCHITECTURE c01s03b00x00p02n01i00832arch OF c01s03b00x00p02n01i00832ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s03b00x00p02n01i00832 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b00x00p02n01i00832arch;
use work.all;
configuration C of c01s03b00x00p02n01i00832ent is
for c01s03b00x00p02n01i00832arch
use WORK.all ;
end for ;
end C -- Failure_here
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc832.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s03b00x00p02n01i00832ent IS
END c01s03b00x00p02n01i00832ent;
ARCHITECTURE c01s03b00x00p02n01i00832arch OF c01s03b00x00p02n01i00832ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s03b00x00p02n01i00832 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b00x00p02n01i00832arch;
use work.all;
configuration C of c01s03b00x00p02n01i00832ent is
for c01s03b00x00p02n01i00832arch
use WORK.all ;
end for ;
end C -- Failure_here
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc832.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s03b00x00p02n01i00832ent IS
END c01s03b00x00p02n01i00832ent;
ARCHITECTURE c01s03b00x00p02n01i00832arch OF c01s03b00x00p02n01i00832ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s03b00x00p02n01i00832 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b00x00p02n01i00832arch;
use work.all;
configuration C of c01s03b00x00p02n01i00832ent is
for c01s03b00x00p02n01i00832arch
use WORK.all ;
end for ;
end C -- Failure_here
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY BSA16bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC
);
END BSA16bits;
architecture strc_BSA16bits of BSA16bits is
SIGNAL Cin_temp, Cout_temp, Cout_sig, done: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(15 DOWNTO 0);
Component Reg1Bit
PORT (
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end component;
Component Reg16Bit
PORT (
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end component;
begin
Reg_A: Reg16Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg16Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cin_temp,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg16Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
process(clk,rst,done)
variable counter: integer range 0 to 16 := 0;
begin
if rst = '1' then
Cin_temp <= '0';
elsif (clk='1' and clk'event) then
Out_sig(counter) <= (A_sig(counter) XOR B_sig(counter)) XOR Cin_temp;
Cin_temp <= (A_sig(counter) AND B_sig(counter)) OR (Cin_temp AND A_sig(counter)) OR (Cin_temp AND B_sig(counter));
counter := counter + 1;
end if;
end process;
end strc_BSA16bits; |
entity tb_memmux04 is
end tb_memmux04;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_memmux04 is
signal wen : std_logic;
signal waddr : std_logic_vector (3 downto 0);
signal wdat : std_logic_vector (31 downto 0);
signal raddr : std_logic_vector (3 downto 0);
signal rsel : std_logic_vector (1 downto 0);
signal rdat : std_logic_vector (7 downto 0);
signal clk : std_logic;
begin
dut : entity work.memmux04
port map (
wen => wen,
waddr => waddr,
wdat => wdat,
raddr => raddr,
rsel => rsel,
rdat => rdat,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
variable v : std_logic_vector(3 downto 0);
variable s : std_logic_vector(1 downto 0);
begin
wen <= '1';
waddr <= x"0";
wdat <= x"0123_5670";
pulse;
wen <= '1';
waddr <= x"1";
wdat <= x"1234_6781";
raddr <= x"0";
rsel <= "00";
pulse;
assert rdat = x"70" severity failure;
-- Fill the memory.
for i in 0 to 15 loop
wen <= '1';
v := std_logic_vector (to_unsigned (i, 4));
waddr <= v;
wdat (3 downto 0) <= v;
wdat (7 downto 4) <= x"0";
wdat (11 downto 8) <= v;
wdat (15 downto 12) <= x"1";
wdat (19 downto 16) <= v;
wdat (23 downto 20) <= x"2";
wdat (27 downto 24) <= v;
wdat (31 downto 28) <= x"3";
pulse;
end loop;
-- Check the memory.
wen <= '0';
for i in 0 to 15 loop
v := std_logic_vector (to_unsigned (i, 4));
raddr <= v;
for j in 0 to 3 loop
s := std_logic_vector (to_unsigned (j, 2));
rsel <= s;
pulse;
assert rdat (3 downto 0) = v severity failure;
assert rdat (5 downto 4) = s severity failure;
end loop;
end loop;
wait;
end process;
end behav;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cgw3GuE4OtC0IUw7+yMxDTN+4pNVdM8tAj8kSKcbsNleCUPqVHXpjBFwe4VrchpyKU86Gdy4uDW/
kzhQRRQ6qA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
iiCeUnr4B989JXGojk4b1VpHQmYbCPhpYXkCZ2KA6WP4Gjbc4ANKW3V1KGoKZmskwy/dV+pASPVM
lne2WbtMXbobjQ3oQvWYDTMvnFOW7QrLP1ddPNwPdSw220PmA00r5U0N4fuYc5tIMDPiAifsDJxh
PawTp8BEfvzW33HhKcU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
T/TRcsuoNriz40oyUS9kgh/jnanfbp8x0m+HnCN6fx2ZbO6AxukBPpD5CfqR/GdOlUBnv4lx5406
ugj/r0FYFS1WV+9m1JcEeq7KieJC1WNHKe0Q0ZsB+F1jKH38JgdzVqJYhGGq4qyBH5HDPrdJ4dDH
I7wDVYAVYd1wnbH472CpC0MLwQ12bwr6jwRpVKuJSTh2e5WQUKkPo2J7iR8e8uCc3pGZC/HxvjSP
VhnTBn0Xrov3KfnBYQZWjd54LAGrAoc80sp2SC7+oumgXJ4tujSIA0ztFiXrCz+DgrjF3u3WSPGU
lJvOFZVTncgTurXBJaGhrc+iFX15ubfbOYp3kw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kXpGxhM3q4K7zqELQ9SObxjj1wGRQ3iXws/lHPiYG51OzWIbZPCmJRy56DZC220ICfLV0Wyctb+E
XDVtgugXMyc7gPtIxjjB4sruy8UTUgYwPzlWUn4jBsIUMxMReQiJHGp8FSDoihvKiq/mYku4U18L
RUIMMNkseLAo+emDRak=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WX6DyP4kE1c4FlpGcQgQ5lexlCnZzJyGnfy9qw7D/ZHsHkxJlHdveg0K5igWqyMGX7FdJXRsE6jm
My2uUGjEpJoYgEysbjhu4pCZNk3H75B0R/1mmqpVuKFE3/a2pZSvXeFrAp/qmEJiem9fvU4cfAqi
kzp2vN8Y9viUYGKxz+8JYESfC86GST/di35HeR1zb9HTQxf7obJTNmpTWnhuabba//U0cdjX7iMZ
inatYqcOk/BRZCGjFLS3seTfMETE6Q1I+ZSCb9Sp0MDNovB42wDek+ZSqOM+cJI12WkkJFAezie8
QoeBrNjQxe5sbiwt6FBwwd+Yc7s82xfeN9H50w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13728)
`protect data_block
CWXbS0QaDIakLe4/IDCP5+SfM81GnGxs+zSpKZ6mIQkaE6A7nHLFY01OrOR0RfEsR4k2rNtQAEuz
sLb0g0247j6b5SE3jEZu2ardgUPT/BCYdYeIYtk6VWSQP8pzI5w/g+tdPnzWJfehU24HZ0O6+zt0
WpoikTh+itDqaQAG3DQXBxfxIBCpYoxR2/Xzbd9yeihvuBOICTHhnQUh44cdk3LY6mK8ZKrG9C3T
CPMHc/nbFGdaNHISmcEBLU6/CaS5v9Azfbeq3RybtLYFnvtcfwX7rT0WvvZzqVB4U84iQA+E7Mpd
WAigfc+Y+z4E9+fNUyBwe13TVzcYqTc7e+NaNBS1SORBUf19rcenP/EWhLRhOkrr5e0dy/4aoV8f
h5wZCMWfoCYNtN4SmyGOIAXvnut34vhj32H239a15ORxxoh0JN7ubzVCA0jo1oVx4lyCqEZ1ePVP
/bVslc6CJy/INg6IfHY/uNkjMiIuM3GSmgebwk472pVdLsN1CztXnLvo8R0Q+Ho8ypNPsyt9JoS0
c0wTV1/lXM36pP2QbQBEdtJ6CnMqwbxEKi3xNHIY+qxqBOr1PKD8H0C16B0EQTEIt4jXWg++r12D
InjHdWiwroVG92q+SFJuIblbmxYslTVIkn5o3QnNEo+K3c9TLyMvLTONbXBGWl2/zlvNxOFtp64v
ypqExIhkLwgHZUgezgKovT+3OQA2rjb53HmMoEURhx1BPXFX/zniGK3VS29jLWDJ6kZBLqdnCFow
rZI5rN8gvJdAfkt2Ey8NwbKVbGENdF7KcqMNHzzBhVrjyecOqMLOUBOFlMWEnuNS5AOjR9CKGSBx
sdc4SK/HjWHbXyLlcvERQ0qb6XYZf5cE/Irt9d96XFpaZBooVv+sTYWsX+6gJgjoiRJ2SSb5KCDf
Gz1Ypm+3s6tjF5RJZhfKdsJxSIOoEttwYnc1v8ioAJ57yOdnLxASraefMZGoEigEyrp6CfxKm38a
HZtxRm+CgqYg+psXtuxDBJeXXIWoPEhzMEWarjdRNBHkIYzfEUDeGUogIv2RSoI8KW3qkbEMm1KM
/ty1CfUmjNUppEoplsdHwOXA0U2VPt+xqyz5VZd1MHXCO3MqnnYfKy9liQ/rlE97ZywCq4ViTPT/
7PbroLVufXNtnfrmPESvI+Wi3wFw2jw3qh+IDskCkawdB7+zZWfsJWnzILozKkyFYAOcIVvU1Lgc
1cdYnRFMj0yBmx2hm/9JQWPcWnUJ1tKBd+zRpJSJ5I4rwe6H1wswPKaoFrML7QV3MQxX94Qh/Dbx
1LDDZ7eyW423PUFeiC17jwCkJb4Z1SAVN05CkNgiTJp+jbqvRcGXik5gqNPoxoDv69mvjK75lIWW
uBjCPDzOxfrR3nBH0EpvchVJkWGBrDoTiigOhWqSEl+inaXVpmL4CFXS1pWGz+joCykKu3cWCk5L
ITi6/hSiWSYPuPR7VQ3R36Sr65qPmUKwiPtb6SU0WtKvlqJdUYkhgN3bNH+uSw/+KLCEdDF/sXi2
hqi+Deywn4YHYUXuG01usH4zktrPnYSKEvrawMlYeTvvWyVgUh5GHHXzKVKFZZQLNK8195SEkxpG
SjALlHrgihjZtvRS5ImX8O0LYQSD0v9a8dJqyKNeHx0F5AOm9i6ql5eL19qseW1GMb4G5nsK4+xQ
c+hPi8nERRi/8BjF1CyYyRY2OHQd5tUr7ZG/GBaRe0nzH041zpbpFwjXDRfo4NsG8Fjoi5ARfFQJ
yV8wqVd4e68p1syr44tLuQ4Q3bg0ubbdvm5MjkLZuaquR2OmmNJMpyqyX9kSSS2sHEMAopBcSfcw
RrFFbwr+SsE8eGvrN6IReW7YboE5IbUlSavJ5ssGiy8Q+AjgYGLhMpZrAv3yW/4VIX+Z87WeR9fQ
Bn1XvDNcmTzTT6aBqCrFh+0u+Xv9v6kwKAt9J02JHQZ4GCn7hL7wd3OAVyMEgq2gq5+9ri60jqL/
HyB1YFPt9RT2jAHferjAsXBCBAH6JuOQepti5ZHHN7+/tT0//DO5E7cDi2Np+tadpGzOcCNTV1Em
Tc9ZYBpCBIJidVUK3/0IOgteMt/CsBXm9eVM8rhCkCX39GXogZACrO16SHHQTjofH/gSrym0HaT7
cOcU/mI4p+lLy9uVpMC7t02yjcrkkkmghTvzjzPb09sPU8buhBJwF92bTG3aKkQe5Wg5oLTxhTZy
J6ngaAdZxjUYkq/Coeq4+wnCOON3PHxvjuLPLMCoUmwl/6dSNsrT3Ef9xcOz4Sm20e89E8xtg3Bj
txqcAlqjem0vLIrLiF5TsuZ4h+ZgZBQprcFNHK1Bg5j2n/+NUOg7w4RcmQHlymrFaeIKF7HChsv8
pqgN6IFTnmNF6Jvcl0vHwViBeDbnC39NeYYKGA5PfqicPHaw3uJ3zjn+nuPeEsz04Qe6OVgjBOkN
OXzT/hKBbxhRWgj+atg1LJSATmJuylY4d4ArlH5HbwG2lmUq99DKYBDg4mMxTc7jyAAcFgDuUZuO
LxY5ZeT4IjWB3kRyA3M93FZ6AKzHgtsBM+x/wvD28c6Zt5kfxVs69mKZ3owgd4tdp5+tgVn/kPpk
LvlO8vNxQ3AknIotWp0a0hcwtO6C2jfQXzHQWBQJrAMmXFk4vLToHCheIhfrLj2zAEvG2sxLHBt/
3AHIxBJr1RW45Uc3BaOjYDhrbodlQJlFXWzvXftuwTSAmzoEXAIykHkJOPSAP/NIh8XV9mGTg1Lt
mgg6jW8qMzIL8I2UNdA1MKy1s86m1wwjNGcf0/Q2kLnSSgzTuv8z0Z1/ZetRWQidKlGW4YMqtDds
5Dm4JrfMgQ+XJDUF9q+/wK2BIBHU5aCF/omvnr5LGINGb8ISVGp6rSN+YvYae29BANnjR9JKyu/g
Lw7z2OHhzntr77/xZGhnHdjZXiroCDveLsRVOvYerQ6f+gW+uaxjrFRNc9vB54xouw416A0JMbJu
3f1dcYq25q88lBnEsFNpNGcEkX942eAysT0tBl6B7yprzbCwgc64fSKLnmgaADBsgTwDkzwa2rNA
WBq9R7av0JeBYBfZV7mxTkq/7PG/me2Zm7MpyiI4oUjlUgMOfydwqR5JcnBC6tzY0yEaHtNROYD8
16gfMgMmjQPBKU8eqdop+aTZmdRGwe+WmTdCRakzJOI7ur1eE1RcCfV/mwExM+B3r78QtBOxteA4
AgQ7liA1Yq7wpwjhZrEYKUDGiMH9pNVF/d342Ah9Q7wTNv76syVooCfGnmWAl9c3i0Jw/8jfN3rZ
qEiuZWc+sNi18ZvPdVcKYcyRh78ulf8aCT4b4FhUuAhpR1ra2kvqmX4/287+UlD9Cvj+Llz7ukVh
S7lci3aCka2VjcvZD8z1LWSKrm9YgpFwCZUgwMsQcnqB5uT6zhPTnMcXhOgDW5PsoK+dSq2NqGlx
58/iKxP0uyU7Q8nVbedoCLnwEbUBJAdtp2lgmMXNxu5+JntV9ste0hTjWn0F9bpI0tyrZXWUYvnH
mLNBwAYf6+oggqViJmyOq4DFVI5PTZUFsuERNflhtu5Ou8JIZQ9ojw6HZRfXqAxQUpnNeCuO5SzF
THHW1yn3oBGVF3pNvo0My6eOvzD/FY7sJ6XeYFFQQ5D2Bar2wCm7qe3rmmHki4x5IL1rRVomFk87
BI17rFcE2ElA3v5zY+neOjH0KOXK0oFOZV2HWNP7qEK6HhELRnMJKUVcd7Y6JGo+INaz0EFuC/tl
71GyAYRxIQUd4uqHnhKHFXr++531FYTzeN9JRkbGcosRGTu4sOW68fSiu1IyoGDPoovFt1QxNWxk
XTsGJAP+Fv5Y6fsCkiaQSC/zBfbjWSYMpbL0ev+cX53/alDPJmVi1HoVM/whIzMH4Tg3GxvflovO
fbqGjcsbmddSWmn2hB8Lkt+vDlrpVF1t3q4cT8+wFgm/6Q/C/RIQhBChOUZLz7V2BZv4bVbEw+Hn
qbJnOr8KwoRT9DkcwKz/PeTXkNJebH+hVZU9H/E5VTXmXNZPT2DJ2XG/gDBc5AHfznydbQJmkg/z
/7J7NRb8n+MxGKE5cnBRh7+7rLo4poYiXQDPND0bZJ6mqrs1JvB3445uet+A7vGVcj6zqZSfmLIb
T5Lu2GOrewyNKyBZqKp9fI4vwzs3KXTLVs2kdt/cYWz+jP9JCFoehMm/y6fJfDwxZ51Nk5QVhLdC
obZoSyVk0iddhXXsgZq46sEwMPQU0mdvBCAqSRbggyPw+GABJhX971FAbBWsaLhNdKWaKtveHi98
k9F6cFtjFz8Vg8ad94pWEcDUJxmdOHzI2fe8c7yzDhG07YgALmmBgZE37y4GhJgA1OIEMSrOU3+e
PvPQP3UnVoggwcHNAYlOozBA685Be8haXACMOv4DCvOAKNQ5m5o8lI5t4CLrYy6q+F+n4/xzj42b
JZvjXUkRn2NXH9+N88K7Rw9F17uTBlLx0koxaHcGdNI4u2SdLBlDY/yYL32lnodW8QIHakQ0FETv
dmPGHK+dQYDo7qPQEqaHd4NiQay8zawB9ivxV5PokfQK94k1RkaVWj1rXRx/9913HleZ3cJYhJ7n
4VPfwWphuJCr12uJkFXVg+MK3Pj1pdJ6MKMXzED5q/byCXUyTo+ZxmHkIndOIzUo6zGa2eHCUicp
Uv46xobbE24ReyvirVX++RGprqj75nkGgZifEN7IMAUxbziG/h/4B7OcJRr1IDv47FUxknw1K+eJ
HUuUuI9APbQ0WVcwAfMz+RY02mUtM+TZWgqbysmuEaFZSAt96woHLditOUl6z2ArU4nU88lt7Ul+
br2JTLFhRFy01gHl/3rFAZ1qePyft0eiEASkece6k8Y+GC9rj3gHalwji85LDxWFCNy14o/DqO61
8Q7RGVMQX3Exv673sjnrtaAH4BDBRBuoUrXHxjVuejH6kSIUfn7nNzDmYO2qWvNqYmBTPTOsNlsz
yqAWH/Drz9uYe0CYBL+ixKg4Pey/HjY7rKL6divCnWTHkcPBx4qaK/a9CktXrLBYmBamsJJQFY8T
9SWfgTPG9LUXdlsWK0lt/fRFEIp9ryFDY76M4fd05c7Q7MWLPbiOCTHTj1MBn9c33TD/2a+lWrC4
0+vnu2aX6HtiUMfMbLo1rPrzUcEm5YWuFaQb5iip4Nww8jE45neb2mLKhU9YwprC0pifX8ZSLbZ8
fgm/yUH1TE+o3syGuPLMQRh7/EBtqF+B9c0Tsck1r2VdcoVvCaRO3oqDOl6E7nphgT/TyWQviVAJ
9JHgwyYqDDHP1qW//68hSv90Pp5Anl+MqOomhjsG/kIlZIVw3hH10yeGUbOtLhgYZmhT2bw6ztGZ
P2qrBqhqhBT0+c4hLdGb/j0D7Z+BUS3fzAsw348NxPEf7Xpwl06v8ptwmxEn/1sLihhoPyRFrFor
Wr/JRTCt53uXR+f1Hq40iW/WA0dfiu+amdr/xOr9iceyW1llGhIUO2rqWxE/S6rRA1pRGQIgSUXe
0W3nXGCKSMb2ELtaqkAI8S+yVm0CcUezwjDVgLbZfDTRu4oOfGik4YR8XS3ssUPGUfFmOnHGs4tg
UK1U46nr6EYgQYjrbkHlMfEKx/MnxV5VFJZI5Cpxb+iF5LHZSnSDJ+Vbc+g5bjIZaP7RXt4O0ZSx
gXM6fQzrcSiNdQE71/p6/sX5b9VmoX24uQGwHkdH6VLk74hn1qPAIXfB+cUAyaHZZ6pdUYB51WRT
XawDTFsvMhxS3uO4pfV5EKh8As+NTmAerhauRgAIZ/BNoweEHICr0A2CYQcLCCp+fwzam97OD5ed
PvEym/QI7Gq2yEU0bCp4WsWZzl6ssStuagxXMFUM4lCag4KlCSb6F1rSeLZTPcv9AKdpf02Llw7u
JGjXVFtDqwLNFS7qj073QiQqAVA+AXNX8YpwL05BK13kARbJYH3z6H7FRlf88s61vTkrddS32GeS
fITZ2y4Vd4QeeMrwOPKdlRUvXMGjIIZAFtQAtzMmZO/64I/t1nY/Lo9h6GQm0YtXIMph5vwFIYyd
f4VzVZxBQMzWjt82w3SuiXvijs+3cfdhtYuTxhwLoC0G2P5BllH9mtguKm9kh+FkPEKlhC5kPnnU
roZ+scA16ZvayMwt88ID4Vz4gyxHt1RmzdoCa5uLDUqCimh7c59FBtZpd5gP1SmrNN5Xp7MeKdcL
DqpIV5ghJMkVoNV5klApi2jxf+poL+hLYlWKM0KN2PJm+nJ4Fvw6YDVHhwzkCoAoSpHCLeLWZaRI
CgJUMqxMux2UnvA6DDRk62OB3BOzPKEmlJNWHd4TJWLrydTlu5Ei8m3IhZR76dxxZ4agas//9ug+
GEnyy5FqPbBgrCn9yX1cQq9VduIGTspQ1en/WCooDoV63bLgJ22Ff7U4+WoCgoKDtevGgB0Z6R10
leBdjtWWGX2tuOps8eiwsgA/8P7R1/V9ZhyZEpIJL0b+/26aHGRhe209ls6wtDl9P49hWMHJvIUj
IqJZshwZBt6aEWsTw2gLBo/IjPZn9EwoMog2RXBu98Sy+IGvdPx16pNh+XQnoQKipNdkmsxCPRdW
G03hQUGwjAo4wqz+aNA6aqDBHD6Fgx8z/xoa2FuFDIiS/V92lfSHJ820dtC/OPGfn54ghEtF328N
Ye75BAngOpKXUAj2x4Ju5ulXn7l9NjQBqsOIg9QgusAUNIYSqY4Vv9F2mkCupr35e3ApmEEKat/v
epAVqYg15rJZTSQIcqW7TQ+leh54yDW0ERwT1XwUdTuSG8uN4OV2jp36KLUoi619XYExly6OrRsk
HNZeMnDiLr5Wgd6NIBMGovGI4/ZMQK91IUcy+SXFb6kcUsshRCVGuoModCdxx+Gu1oF9Z0JhbWLL
zuItrsCg08oxTIfiwm7HfopBzP3LotABatCQkVNAzrcyNdttXzCVe8G1lET8DjfQQrXo0FFaIROf
JwUl2zbfJVXSSK7KWTW92wpJR/kQxij1Jd3/L+4yaqXEapxwqPvOD7JcdzP4z4Htn/h4XmeA9+r8
2GoT/FkyNArohQ6i3GbbCT7tzb5yznf3ANeHzgzhd+WOCXi+w/DMpadhyR0RFowVntsGojBiKYFT
+tZ4xmPr/WfHVxnuUv3wPv8lUW321488f8B0Bl9AGC662D1Pn70IrUbkziya3jOjYWbkjj32Ng9y
33VZj5NPioxWA3dZOGuNDSWD68BDcY3z/Juhc6z7wkD94gMP0cPCGPww4mc5vaHOAhnr0Hy6yznE
rzUH1QyIz0agjivB32t2i2PgjRVNG+SdMWgy9QSp8kiMiBRQ+1sFGuvc7lKjcNEI7VVzCVheJ73V
KKoHO961vHkG82VpYNZWvxSCNoxierSfKtKFWH99IrZIPMRBKhQpS91yoSV/Cdb5bBtLiV60OVIl
6q96DZ1C4JTSpghPA92e2DDqQQoGrS/dGvt1qUa642LrsloqM1Ouc2OWoIi5P6j2gUk/SSgKcHvf
C2yuQ8g/6APaMaoUjBx16wIGvN/znvM93PhQXHbaG/fFvfcvSbv1tDrH5Vketr1yqyI4UWs3NUU4
/MAR3tfcUXjxxKMkXUaGYkxz2roqZuoV+W2d6nts/h0ArMmlXfR23Vg+L7ZeNPyrXVInrSoQfjNo
j5OldZmF0oEkTiiO8UMDxXtejs4Uwopn6WIfjjIaa71x6rr2qKyyeRTinXDCpa9bIGa0aLavatFf
Szeub0rpfwseMmDZljowi9aD9bCiOTOjobuDg4zdY/EpEkfmHAY511x0pC3pFlnEjKZR37Wnw3ts
yKvPczuprX5lU66vakhaP4w62qkfe8XVvwJ8/98UVS0zO+56vujzrDkxsZAqzqdsWpSegABdgUHK
RhWmFwSK1+fXn3Xv/8Q1xlMZdbfwAJQRllh+BErroZL2SbAmlQ70eFbrfKi897p/GQJOpgunm4C9
G63YRYduxEnMOzQixbCmTEw0wA8u0/VatmNRPWvkous2qDvne9LBd+pWv96IpSYXn5I5mGOnPWeO
zYpuLDE9Y6ol934E+iOABux2ryg2KjdQERHZ7qp1fwZ5otXKeNW5CWlENzIicdmOhZBaMa9pkSvH
Dx+Vzu0YCq6s7hmkPRrEF7GIYg5CFRomHI4rC6+E5tDC6zWDWQlxOV7JpYmBFHnOEd+EF7hjw+LA
uPq0FMtDwh0e7eKYeCD/PVoLj58fpaaS7LLqhWVJI3zOqCjih3wAdQDUAK4RHCCg5Y2qXQZS/Hkw
r4vcfF7bJXU2+RGumm0hFOfzI3ol0VF37f4UI5dpHKRKzUUQyzCPf+C51cFe0gnt3NmsmGUji9Or
5LJa/PCvMUO2rq7usDElUsgD1SR6ec4eLXeZ6+TJrhXq9xUq/eLth6/gDQjQf8i+TxXvB1RRE7A9
zYyxv/ZjuVx9GeOErBZhR+VloLNPxsRtAw/ppoEYo3NtM704kuj5fo375ZIue+OLGol9EYlidmIw
w9jDlHMNZPErBSZl2mq8QtSeypbWZXxk2vjdtJyJCUTduCjlGZNacbBkygkPA6QdWvYR9XQ1RDHT
2Nm9zU/fKCTolAeeCzHoZAA2Ry6jJfXHdHMvEaeQbLc6wuQVE9xNp1wN6kMapyXjCEtlN5qHzEgR
2gbGhWVlDI1OgwEtCTVSTQAO2yJd1W8chTksBui4OlZDPYg5M12YxY3GgFOkac4M/ZMhY22D8JZC
L3akZY+DDExcZjic9ToHHknIaC6GTDV+TM855jKQvD+p2fuCP7PlDrscbZPTuR4cRqHuCDNlINmA
lEgeJTBLEL2F+6ifjyxVJkf7KubWl2RM9X2XtzODrB6L/p8biZnQGzl/dr/80hEVdr5SdAnK2P/t
L7/d304c07aJbbNtIKTSo1t77J9KjiVuOKg+UNJhKgtV2ijIIgld9hPF1rj67Ldp37+KS/LhklRZ
csc9fJIVlZ4V3tW1hXa4p/IHLgc7+glmV2qwoyyMGdzpychbpTzBL2aJvFaMH5p6Jy8lpAfppO+t
pMZueoDvbA95PW4pB6LBlrQuCmDC1oMH2NkzHQHbcj+Y2wZEWb3fcWnvRStVmv8yZuyh5kq8Bkcl
MW4istdeloQbEePha4kafopdNr9OCFagkY3YU9UokpdCoqktvEZay6SkihtN32DyBr8DqUp2UBSx
1cvSq5VFEwOFQ9I728LghMMUd8NYR3W/ieWkLfI2KxS3fFXSumXgwxLuzfYkORckhF3XCRvaP/UX
E0BwjZzF0RcF9IOVs4dchA2WCXPZvlmtxA60YHeYlkWkfWl+LRPM3PM6aYYpHGlE6o0SUDLFb75E
FA3lMpmOWuGE25az2xO9oL5CMwZSsV76WK4583o9HjqsI1/JASnK1dl+rXwztPO7FsCH4Fu8HC2S
zx7YGwn8x739dckIHhK14G39TukDOA7Vr0pYac+xQ7PxeysIK1HWRGMdHLhTC77LXgLxFsoEbA8+
E1AWxl1+53z/r2gRCvTZ5LsPrteCiFQkRV40UIaYurBp+mOnCybJZ5dvQ5KovQFf/BNazHw0xjBS
s1XamTZmjwk7KSTFxg7598oMxkbrnFP0QCRMGA8FIq0Th8tm2qF1clZd4uwndkmGVGFoZc3bVors
xM40v1BNPQPrv2DWFEjGXtCAeF5RY85ATLAIHydt3nfxVSvZUhUqJEj7wAQ9jeh3GcQ52xw3h/Mj
H6slMkO1ruxa3L4lP5UhqLMW63JkVNYF8Q/pDbu/2znjC7J8PYB49Lvl8GqqfXwkRKxE2RMqRofC
ys54GNQCWnAdkHuxbyxD2fG1Vw3uhkY1wWJcbbDVCtmUMv97Zl96q3u69IxaIh8ByuorTT2MN0Wo
nnN5NNTTK4cF0G7WhU4o92+oM9kLKY9sDyHH0XfRHUHfcwEdFkIZ1rj5/ZqtY5ILKe6bnYrXldLx
GBaju8hb5U/dvXSWFgeDwVD1JjaRmAER2TkbHplnE0nshU0IZt7OsGzin8Qj0u5KD0YoFAufE5fK
oyTFMLJH7ECXo86Yzn7fsYtOIPP1cM97CPNsauhBzM8AMPLHk/z5imO4oDr5FY8kmTvt7nr46sQa
H9yL/zhUC1H3cASagqtrs5GsjD7HCJr/uY1/8QPtyIsgeDflr37qNH5v8RyBIgLBzYStTgrS41uk
oa3NRxfOwfWEyGUlk1GPcgnl31KduycVJe+06AlvtL+9DkH3Xlb2ULbF7LiRXFlW/ST3incEv8gy
WAQgGJuEKhzCtL3ZT2quRg0Bz73J+Mzp8zWtgr7DLTnB3R99oQtCcWTkq9y+xbDOWqpx3q3l/52K
SuS/Kq3bkRIAjAiO69MLPwmkuVZ6/sVstzsZRfuzibcouNj2fAJLyi4rWDQ+bUgXnP4zPrWnRGJ1
oQSj7gzGl2dCM6OwEeNfnjCqwzztn/hg5HBPmwUCt75UroPkHPf3UGnyb677DCUn27Kf+uTgYqIU
jwI46jKKJLSBFQrneSkcPnDjRsfHyoY2YkCLaJTgdeVfx3JnlOuA/xyHq1LLn2il5HD/UsHqLJqD
r6aWZdWopLSw7QzQ1YBgEF9WvyL0Hs7A+ssEjNUH/QgUn9ps2ywXsX5yJ61CPXrTc3CvpGLVf14n
r/FiyZL2sKM0g3x5TDZkUaEniaW1pawhRuxJ/Xasy9iYHVhVlP1PkzVsQvcvlBOpIPkrXAdM2vQL
aHztAqwwYX5K/sX0Laaduwu+klohPNKYoMC19fK/OYPImOcxGAwnUGBVyDqU/1aIOUOBrFe0/TFk
un87ffLDGUHQJywxGd6UAcAHvlQwzg7FkSgjjTH1Bm8BKxfW5MlRXw4q6AWXBEjyDQiVLpjtBHga
EssLUC6omGC9sMhL8D6Sl5A9qiS69v3nv30elIsDbtMZwwGo1R150mwx6HDZ6GWzMM7GE3wAPqRy
YP+dfuluQSK1jaT3FE8pxY17c8ZlM/VOEP7Q156yZ9WhVOJ/MbGQ/OnsG4sgkRddS8xhsvoXDBOK
LnFevE4Jp27zb8wRjNSn5zLY4h0cBD4ir0rklP+65aIZSp3YMhPtm24jCGHvwBiSpXnoeR3fqoPn
kKFVwRPd/Z/8tyE7wWry5Y1kEMdq8pvvtv97KHOHasM9CgSawPAt8oxOGm64Uo4gKgx1R86e/YzF
n25HJX5PHzz/QzPds/zMU1ICuE8WSDDCmw3Cagrxn7h0clfv4zaPz2/Y9/CyhMNep5y4e3/PHFRA
OtYWEtjswC59jLfYuUM/dpu6sj7KWPnho2g7J/UOg/S263P6CDasrMDFWIi6NCvtKSka9jdg1w7e
Nm00fy4/YGsqAegCVSRpegndgSCT9iMwSsfR4l7eyS8Faa5eSjWvIcY2WWByQNAJ6vN+juv6BNA/
0DpVbUmQ7AF5D6rLqb5PU/GtMqTi05YH2dOCXG5YrFizxRPGpVteE85s8DOtGLs/UZvIc9ZFTo7D
duSKImwxSmKmahJzaIXIXc3qAhRpGEP8tVdbIAhW9r2IUF13h4fYVrK7eA9j1pkjWZ6D3B9OYehm
teGQn3peiTV7MmSiXX/LC9mgm4mXzMY0ud+2UMTF74HsLgGr6YZ0OrXqMsTD0+/8QT/BR3/sFQwh
2zI2i7hLWjt5+7NQP/Dd+tyeJt/P+Cwkf1hW44boKjpTEFBmmArNQq4AdpiW7xWOgsH4Ql+NBWfT
zWiODiJg4buxa7F4bjQwJUyknG+WMPlG5qCODFnetJINBSn0aD8CRGpFrvGVhPbp3rYQIqzJLPKp
KjzeU423o3eHOLRwwc7n5I8CY7O+nGoS+Wd9rsRkECwUKUa3dCAc1WxS5jV7NYynX4OHEcKZQekZ
O8kXZp46u79QyQpGIAvPZIFYSLLclyIdSZXREmd86K7QnjKKMUjV9XGGto6VUv7ZCM1xzE+utnUK
i8tru4AH1NmoPBSvCdWTLAetR4EGOuJWpKheSD/Bt76KC0V7tzjcftm1pauAls9hQXf8KpHUqjo5
KhBmbRZZ5kqs0BqxL0sKkWuyPpyRArdXAm13EHdGeYyYdzru1+z6oQyIXOW2yJVejaRh0HOvA3rv
w4RFjsnfBtHx6fVFORm3RsK77/37stKbN7pHmZOe5xRfXeeZOMYjgQG21wbzDWD92+gWxNW4LcD8
Grd0yaP34Lm44ckfR3cXHPXafRmLURfw8V6YzExBjjuBvGkv6vCBF/8xshXEjG9W8nnQw8DPav7n
PTmmbCIXMBy3jdd8APpaNqWSqfA0lq57QNRfAuE7eue8Oqiv/8WviNWWQR+NggBOzsht4nnzTFXP
qjL/X0GlPhyYKjfuU299d30Vk8X/yftDSP0gddJJ7Yp8IciMx3F0XwRL6e6A3jAS3uBkfrUCGup0
ExO4QFNW9tzRqbAxgzJVY82WF63L0CCUhxnsKK6iT37UYpreObQM8iBTiXI69GjTCKc0uQh+pBN8
8EcQhdK3gzFojLu6pGK/1J1pSo1QtghNAwTC2ap6lk3hJju/nT6yUWiuNh8p6SXvSkGLTs/F+WIW
CRqeH91u5qcXduxFA2vVJy17ymFjaek8vStGeAhzZIe62U6k9QsRuZKU9Z00OGZhgefnFp8ATWaW
0d/xhQh6JxakcUBdAvgJ62Ji4jwm0XM6rZKpCr4966CYsTb8iXMpW2cepHmwpdc7/Ui6Hnr5CxQ+
ZSxrs7qKoXvmrW47UD1TygXxuH1eErSWSSzGqWZ/2gHxAgoAsD7NAN/VhR+KIM8hPAOv97hv3la8
LGJcNDnxvVILp7HH0ySIi46A1HJ7zyRQYyB29KyB23UljI76HDej5Hq+JUJlGh394kkkqfANddyU
efRauLKL0HLt3vyWfg4IS9Vag+1xHtab3SeAn1+4x5u42POZPzBaAdukOvzUAnLScghi0ZL5AJ33
9hdp5zSZumqNQFq2q35wYgsCFM+XnaA9yf9N3mU31GoocdeB/woH6Tw5VK2uDiXuLrcQtcFy0Nsd
dwXbk8AmcDRcTrD+CmWCrZhIYjUS+iTWYvsXL+Ufql0P3//WTKOOakPAItpL0Ni7yhQakdb+j63p
bpQ6H/yBcQEDh5bJVUrQlISVHCjv82MjbVShVgM18N7O3So6u5VBlF6KVHBISX1rVs6m417N0zRB
F/uHO4N+I+pmFqCeJD2kVHabWI2Zf7VKmhN+cyfLKYtJF4u5jd+veozvCi4gTOKJz9QiLZb5g2U/
WfJl82A3tQzj1/YWH6QRtpmGE2DtTTiKd1erv3SMo8k0MnQRqeTC2jeK2Zx5gBp8QE4wPj/JZTCb
yjGqlJ+DVCKIz0oPxqRZTlm1IGkjjukaCRKpEh5Ri6qvn1kGRWf834nHIT8P3rhrtv9hTHyyHj1U
KonD4iaDUd8vxf64UhayndCqamI2jcPiksfQKSFZZ135LFkKSRZMrbMFZHuxNd/TdEeJjbA/tMj8
/ix5E/SGqDm+vyLYctBO9h/nQrjY5Oggonkn/Z6cJlLlHqMDemnwbxAkOQpqVmg+gSD8bbzHz+IU
VHCGtpc/0xkCWcmMPH/K2gC3qRQOF8/wfvxrS+WC13FBrs6tReiTuCYU8607yUlXxwdZGk9DUytR
dBE1hf6Q6ukMdqjXikhTsf2gQAvhm0BgcQxYOe84mTEwjX6YpVS1UROdGyGOLcDxu55hM1lzNAf7
0z8Jrg9Jsv/kV5kOOVyh5djOJnRRShxw5GB/8Cz7ejt/E4FjrgK9rRa8G24EBKH6ZTeHTtKCZ5QT
VuPlcnOH1o+P/h8h7qQK38eV5P1j6aPZlein6Tky/kyLRqMKkn0Wy5k7HlbXrU6HjwFphV+hr2tD
n7YC6W3EVRqgKTRV/I8NL0LSGMOJrx1u1zLXunOYnwr7kn3ncIgNGU5DdhhPjxR2hnCbhL1yNesI
wdFKcDobF57S6Ug76+x+UvotmQQo9vzLbGQ3FYd+1iboKwa5wKKc4dCVGAVFi/oto7BWBTs3cQ8j
JPxxz7/LP4Ts5YzE11suyTaTLi2IY2WpCXwa/Bd5JCF5RPATAQKi1ARijgYbRcVrPn0YmRnG9mhW
qhV8TZrEcAUtmpYmCKgu9Y9qt6UcRTocxsqGNgIilnJUqfpR9812Tb9ThnTGg0qrCtmQZis3Js1B
bgm+4Hp0pzZUWRSSkNhHN9ggnF9y0OMO0mgVo1nJD0HcvKnrVUbOv7HpUNUwZYBNtdNollCx8/Sb
CWA4U67YPgWZd1PUcbO2dtVWOZlx+IZgJQVMGKjLFzh0N+8gpb12yocNm1GrHxcVpWGVkOh6WHZZ
kRBNiDKvBj3UuMFgo9jOhJ+J4ZrSHyaLNpaLRAkO/jCd9vfM1uquS9jGw2AXb/E95aw2c/jL7NF4
ME5dWtjRUt++EojL/UjGDdsn+ExNOL1KiG5TjWeTyxsIAO2nRJUjfPIe8zZ7QWRtj1du+0UwOw0c
mD9p2VCLZlAdBEhzsQV6WO2mh9Cr6ngoUcCMR7ghLYP3YUJ2Zt01cnOl7AmY2S37esm/DO5hT8aM
kqY80UU8lXXK1O9SKaMspcw1FmoKVmwVCsMKwz6ztHODNCePpTof49SruufmMvAmzczJjiYaxpEh
zyQ4N+B1GkknYBbo3wlxW7ID2CMbg7s5XfBwpSXKk8fUew2tq9d00/iJ178hd8ezHE4GPC5VC/4G
IGxXYNCfjOgoYtEDGXnVLdEjWaY+KiImHpp/E6hcEj0IozS4F2IeVBb/kkBFiIDoMQ3mibl+845G
+xgzCU12P/iMv4Wjq8mQVgoONrSxZ8sXRqjyPMntWXIJkyYhNFirnfsl/UfZKIepshzrKowYBASX
zmJa6VJglFIhHd1G1kQsk59oAUeuqDNmX8kFiSsjrjXdXpNlzuCLEqzbJVHIVlLPOthuMp6Z9avS
qzGTzL9N9mI2mOZA8wKxzWJ6zYFd581pAxdvSUMWla2GxV7084yWAofRqTnmQJizjK56G+XJo0Pg
KJB0URYZPyxZOku/BAdF4htF4Z++fKb0mmsL65I5QjvZ9YrhWF2UlbT618GSvMXX6wl2kvOIlp8P
3YaN4R3MM8DzbV1hM6vW2nF4MMyofj0wa8niV9cTX0uJE+TGGg4zWHHgSrTAW32rHgAtuKJCDaE2
+C1x3nr60NSLeaPpQkln2MyHYm9c8btmCh/ljmxG+6kQ15XGqPG44XP+dW1Y7f7QF+KLZaBlnPL7
Jd596nWqxuWZvNGExkKoZascTDZCr79UGuH6k1/feJcAD0mrltefNpnraMJSH88VhlbBpPf5vvv9
YB4MDXDbUWLf1L68heSCz9x1E69+gcL0vuKMtTQj29iIXOkxGnLGq3Qqan0IbfbCBtFMJ1jG3xMF
stTsqI5p3iW2TL/MODOZHyPNx2bD6/aImAD0DPsnUx/NTuaE6IpfLpy31LRDqH8w554x/wTO7BnO
acgEgWGy0CZ+6qe4eTB9yp2VOZjalEXq1v5Fi0t9NeRBnMSXj198rEbVojAATRWB14pQxxX4oum/
kPpTPyPOfCtc8RsednacL7ngIx0iKRV0krMMPceySq7inoFCL0E6UBoFacyFOoHcifsSyxY8EG4l
3Cwf1yhAbw4RID822X9au59T0uDEwFVWeNEIXQZlbdfPuZSdwzMSTCMHxBRtjkYSMCshzMuFpVoV
rMhWMx1y0gelwR+jnfueWsRo2ubbboAS3AuqniuXUbldZYI0QMptrKAjsDL4v4XkVRIDxoswzlFa
xVXZAutZR/yKFsQiJDTWpkygRSBq5ue7LhSEwI2v35ngMlnE2EZWY2J2s3XSy2HUJMRsTI8Nu7c8
ie0imTZYtNa3/b5IzX1hDAhqT2yH0d4LNukr6u0zRUYipvDZOEmQp5Kee6/5uKQbTS3kvsNqZriK
0ykIPsb06QmiQiOlSTCW5swraq4O69A9FHgOjuHDYVfMMKZozHdRNq2e2crxxRGAm7rF/wm6jQq9
albed8ySim6Xuankg/6mNTexunOoM9XlZU4ySjNicgN3mEcCF8JtKzFYkC49nltpBG5PSGzxt4ZE
qvEGSgHDHPj5HgNNtYFlWUMzCix6czZjC/3THiEDqKXiaWVDkIGHm+KVCWZh0yfQ4eTurNo1gmN5
rubmdzzEAs6ObTWHcuCp4mjpItiR1Xsp8m1MmcFcmzUrYkZl25aYaUJWcqjINYX+37Cas1XFlVhM
+E9OwFL1ATxkpJJIFOXBLy4hRTk0pPJuXAfSR6hECMQalaZfRXpOHuxexdOs3IFhTg98lVHjbey9
ZQCi4WigBc8WN1O9ucyuaKHcit4lf4mbpzNHOKx9EvzBU4zIheHIdQ+XeIrnq6DJzxFOjEHsiz8l
+3ZS0EtE6HDHftl4hEdaQ2LtsZKRkr4FVv+c/9YII4l8J8ds4sRkcGBNyuRkngOw/nUKSWfvLGj5
ztgC0mL6ZUD2jPZNdMjuF49KyqJ5foDT77Jn1UPMFf0jlpIrlonU+EBIqiSASWSWKwT0N7qqaxf8
XP80CrYKSY4R2kLgmaBRY+okh+0JJHvuKwjuijItxz6fOtN1AO3YNNdn07W1jhmJIC5+S5HlMb14
hfJL+fI17VqrRGJK84EK5FD5HpYB4w9HxDHVEuREonWolNiVw5xbqctOAUhM9cTgpULpNz8AnJJu
+tfjTgK9xfwZCNiU17gYC9I6MLP670VMSyMJvNDhRj9Xmi+XhEbnCULK89/18N92YW3vUIx2XmPk
up8KJd06DBBT0A7PgNa2T96w/kEan0L8YpnQvNxqJMqT8q7k6nz1zhV3GnQQ3Hf1WzZBqyQ1E1rn
+oGyKtIKe2qTPavbGAbUVe2bKpI3P0nzPkje5UmnOY1HWgX1jlmlftWHiMIwsp8CufHYSLQ/yZrF
E6a3I4YOdu7GwKxrAb0xqh8CsVbMhONzyIR49lu+gd4k7kGHC6qb0f4GnziwvoV8+kukFzqUFEaY
nJMCONIwNsPGmFQmhTjiPHPHKVBNf8/ZP+NFGo2SseyMUQymBjKZiM5DUNXUHPoKEEFXUpP3NeFy
fkLP1zQ61OXeQTg3iLIy4m0Je06rgd/xJ+4CIBmzx4ebcc85MUFbYwgCiSMBrbbvdxiZ8PAPOOwL
y9Cx5ijKesN/EsrHAdis5mkO4i9IL4rWm7nCMmBqBvgGV2v+P+nRhL0gPL+1TfhIoHTKqgUowHKM
lpM7sRWSOKgZn/lbCIjZiZmt4DsK10SUjl946UIDucXTaCmGYdNYLeTgtACV68MhbVRCPAScLM32
jXAZGw0YABZTs3LCQa1Acwz7Rukn9N2MyK02fLf3aXdGMOqpXFq8lFaxW4YAMDFwXN3b5D47m+Nd
mi/UnJeVBJN5QJsVf9HSmYkpyW9MTYjYlrDo66XfdQnGHCCU329y0fIXqnkMe00igFRumm1MGbif
Dm+MGhJdq1/fweIj6j3hvtaAo8mvzaAP/tVOsFmbJtRsl/VhgoYOPv8aIlfmfk8A7xw6J5gXwi9K
6SxuSwtp1xdxnB7AdgJ9aWPXAb9zzZnmmXcEY/F3tt1t2ZSNzRpn/Dwr0R1xKZHG4XjxF8wU3mK7
vbCh0i3nVQ/Kwn4JFATYvVHbaXKFMxLv9Y+gk6zuqMYgUfi50o84q3XLVbLr8C6PayLLHHrZ3KxZ
PxPx8jeZogyohUdcGN3xGvrVNhGkeFsye8E0LM4zZd8YmUitU6F7m9EXJckj5tqcGlxI1xaSIzDn
6H4UK35RuJdS3BvPkeUoVePke53EwuZ4FUxFUktgwnV2GM1bQmzA/5wDX5ez7A54W1T7S0FNiWG4
9Gs1RMEWsX/x+3u9TBFnU9DfDeUdqRJp6gK7R/jxjTY7ogcezDoYj9SjULJhL/P3vOo2rKM9SFVT
boMP8Y5YXsXS/f7KvbZIRn2+ZPBoVFVRsh8P1pAWuk05m2UcmW7R5zavi6K2yCMKXrBaLL3rm7XY
Y8kFTkGlwZh9UGAN4pb56UpDy+uJXhTrL0xQpt8fBlOtuHNpd6WnhySQNpx2BQjeo0x80m7eVV/+
AgyVD9qfo9/d9AzpGBwYlKZ5mTYqiAofb+0e4WaACJ+CUfiKtnM8oTH2CUZsjBgOgAux0uflgC58
DvQxfyqF47cpKE9/zF9Zy3CsMKzV4/QUmXBhS478BcMg874u7Ls5ba0CwEx8fsEzda44I1pLFQeu
BAVbKfp9SX18wW7dn8SLQGLiwvn0f/6/q5JH0GxMtXZVKhHsFkT2JPkLDyTtkIHhQMey0awLjG+L
ZCY211AEbIrtfmZ49r3VAPxRENzEaWq7dPa3vHUzz2vo37GQyBBlnPZBY7WkWSDqu56I3pQSu4vp
aSAC6Zt8nIZkaeXrVPn169DvrJnPvWtlkdztlYFV0/VOYvM0fGzsBbF6+Uhypl+A
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cgw3GuE4OtC0IUw7+yMxDTN+4pNVdM8tAj8kSKcbsNleCUPqVHXpjBFwe4VrchpyKU86Gdy4uDW/
kzhQRRQ6qA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
iiCeUnr4B989JXGojk4b1VpHQmYbCPhpYXkCZ2KA6WP4Gjbc4ANKW3V1KGoKZmskwy/dV+pASPVM
lne2WbtMXbobjQ3oQvWYDTMvnFOW7QrLP1ddPNwPdSw220PmA00r5U0N4fuYc5tIMDPiAifsDJxh
PawTp8BEfvzW33HhKcU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
T/TRcsuoNriz40oyUS9kgh/jnanfbp8x0m+HnCN6fx2ZbO6AxukBPpD5CfqR/GdOlUBnv4lx5406
ugj/r0FYFS1WV+9m1JcEeq7KieJC1WNHKe0Q0ZsB+F1jKH38JgdzVqJYhGGq4qyBH5HDPrdJ4dDH
I7wDVYAVYd1wnbH472CpC0MLwQ12bwr6jwRpVKuJSTh2e5WQUKkPo2J7iR8e8uCc3pGZC/HxvjSP
VhnTBn0Xrov3KfnBYQZWjd54LAGrAoc80sp2SC7+oumgXJ4tujSIA0ztFiXrCz+DgrjF3u3WSPGU
lJvOFZVTncgTurXBJaGhrc+iFX15ubfbOYp3kw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kXpGxhM3q4K7zqELQ9SObxjj1wGRQ3iXws/lHPiYG51OzWIbZPCmJRy56DZC220ICfLV0Wyctb+E
XDVtgugXMyc7gPtIxjjB4sruy8UTUgYwPzlWUn4jBsIUMxMReQiJHGp8FSDoihvKiq/mYku4U18L
RUIMMNkseLAo+emDRak=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WX6DyP4kE1c4FlpGcQgQ5lexlCnZzJyGnfy9qw7D/ZHsHkxJlHdveg0K5igWqyMGX7FdJXRsE6jm
My2uUGjEpJoYgEysbjhu4pCZNk3H75B0R/1mmqpVuKFE3/a2pZSvXeFrAp/qmEJiem9fvU4cfAqi
kzp2vN8Y9viUYGKxz+8JYESfC86GST/di35HeR1zb9HTQxf7obJTNmpTWnhuabba//U0cdjX7iMZ
inatYqcOk/BRZCGjFLS3seTfMETE6Q1I+ZSCb9Sp0MDNovB42wDek+ZSqOM+cJI12WkkJFAezie8
QoeBrNjQxe5sbiwt6FBwwd+Yc7s82xfeN9H50w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13728)
`protect data_block
CWXbS0QaDIakLe4/IDCP5+SfM81GnGxs+zSpKZ6mIQkaE6A7nHLFY01OrOR0RfEsR4k2rNtQAEuz
sLb0g0247j6b5SE3jEZu2ardgUPT/BCYdYeIYtk6VWSQP8pzI5w/g+tdPnzWJfehU24HZ0O6+zt0
WpoikTh+itDqaQAG3DQXBxfxIBCpYoxR2/Xzbd9yeihvuBOICTHhnQUh44cdk3LY6mK8ZKrG9C3T
CPMHc/nbFGdaNHISmcEBLU6/CaS5v9Azfbeq3RybtLYFnvtcfwX7rT0WvvZzqVB4U84iQA+E7Mpd
WAigfc+Y+z4E9+fNUyBwe13TVzcYqTc7e+NaNBS1SORBUf19rcenP/EWhLRhOkrr5e0dy/4aoV8f
h5wZCMWfoCYNtN4SmyGOIAXvnut34vhj32H239a15ORxxoh0JN7ubzVCA0jo1oVx4lyCqEZ1ePVP
/bVslc6CJy/INg6IfHY/uNkjMiIuM3GSmgebwk472pVdLsN1CztXnLvo8R0Q+Ho8ypNPsyt9JoS0
c0wTV1/lXM36pP2QbQBEdtJ6CnMqwbxEKi3xNHIY+qxqBOr1PKD8H0C16B0EQTEIt4jXWg++r12D
InjHdWiwroVG92q+SFJuIblbmxYslTVIkn5o3QnNEo+K3c9TLyMvLTONbXBGWl2/zlvNxOFtp64v
ypqExIhkLwgHZUgezgKovT+3OQA2rjb53HmMoEURhx1BPXFX/zniGK3VS29jLWDJ6kZBLqdnCFow
rZI5rN8gvJdAfkt2Ey8NwbKVbGENdF7KcqMNHzzBhVrjyecOqMLOUBOFlMWEnuNS5AOjR9CKGSBx
sdc4SK/HjWHbXyLlcvERQ0qb6XYZf5cE/Irt9d96XFpaZBooVv+sTYWsX+6gJgjoiRJ2SSb5KCDf
Gz1Ypm+3s6tjF5RJZhfKdsJxSIOoEttwYnc1v8ioAJ57yOdnLxASraefMZGoEigEyrp6CfxKm38a
HZtxRm+CgqYg+psXtuxDBJeXXIWoPEhzMEWarjdRNBHkIYzfEUDeGUogIv2RSoI8KW3qkbEMm1KM
/ty1CfUmjNUppEoplsdHwOXA0U2VPt+xqyz5VZd1MHXCO3MqnnYfKy9liQ/rlE97ZywCq4ViTPT/
7PbroLVufXNtnfrmPESvI+Wi3wFw2jw3qh+IDskCkawdB7+zZWfsJWnzILozKkyFYAOcIVvU1Lgc
1cdYnRFMj0yBmx2hm/9JQWPcWnUJ1tKBd+zRpJSJ5I4rwe6H1wswPKaoFrML7QV3MQxX94Qh/Dbx
1LDDZ7eyW423PUFeiC17jwCkJb4Z1SAVN05CkNgiTJp+jbqvRcGXik5gqNPoxoDv69mvjK75lIWW
uBjCPDzOxfrR3nBH0EpvchVJkWGBrDoTiigOhWqSEl+inaXVpmL4CFXS1pWGz+joCykKu3cWCk5L
ITi6/hSiWSYPuPR7VQ3R36Sr65qPmUKwiPtb6SU0WtKvlqJdUYkhgN3bNH+uSw/+KLCEdDF/sXi2
hqi+Deywn4YHYUXuG01usH4zktrPnYSKEvrawMlYeTvvWyVgUh5GHHXzKVKFZZQLNK8195SEkxpG
SjALlHrgihjZtvRS5ImX8O0LYQSD0v9a8dJqyKNeHx0F5AOm9i6ql5eL19qseW1GMb4G5nsK4+xQ
c+hPi8nERRi/8BjF1CyYyRY2OHQd5tUr7ZG/GBaRe0nzH041zpbpFwjXDRfo4NsG8Fjoi5ARfFQJ
yV8wqVd4e68p1syr44tLuQ4Q3bg0ubbdvm5MjkLZuaquR2OmmNJMpyqyX9kSSS2sHEMAopBcSfcw
RrFFbwr+SsE8eGvrN6IReW7YboE5IbUlSavJ5ssGiy8Q+AjgYGLhMpZrAv3yW/4VIX+Z87WeR9fQ
Bn1XvDNcmTzTT6aBqCrFh+0u+Xv9v6kwKAt9J02JHQZ4GCn7hL7wd3OAVyMEgq2gq5+9ri60jqL/
HyB1YFPt9RT2jAHferjAsXBCBAH6JuOQepti5ZHHN7+/tT0//DO5E7cDi2Np+tadpGzOcCNTV1Em
Tc9ZYBpCBIJidVUK3/0IOgteMt/CsBXm9eVM8rhCkCX39GXogZACrO16SHHQTjofH/gSrym0HaT7
cOcU/mI4p+lLy9uVpMC7t02yjcrkkkmghTvzjzPb09sPU8buhBJwF92bTG3aKkQe5Wg5oLTxhTZy
J6ngaAdZxjUYkq/Coeq4+wnCOON3PHxvjuLPLMCoUmwl/6dSNsrT3Ef9xcOz4Sm20e89E8xtg3Bj
txqcAlqjem0vLIrLiF5TsuZ4h+ZgZBQprcFNHK1Bg5j2n/+NUOg7w4RcmQHlymrFaeIKF7HChsv8
pqgN6IFTnmNF6Jvcl0vHwViBeDbnC39NeYYKGA5PfqicPHaw3uJ3zjn+nuPeEsz04Qe6OVgjBOkN
OXzT/hKBbxhRWgj+atg1LJSATmJuylY4d4ArlH5HbwG2lmUq99DKYBDg4mMxTc7jyAAcFgDuUZuO
LxY5ZeT4IjWB3kRyA3M93FZ6AKzHgtsBM+x/wvD28c6Zt5kfxVs69mKZ3owgd4tdp5+tgVn/kPpk
LvlO8vNxQ3AknIotWp0a0hcwtO6C2jfQXzHQWBQJrAMmXFk4vLToHCheIhfrLj2zAEvG2sxLHBt/
3AHIxBJr1RW45Uc3BaOjYDhrbodlQJlFXWzvXftuwTSAmzoEXAIykHkJOPSAP/NIh8XV9mGTg1Lt
mgg6jW8qMzIL8I2UNdA1MKy1s86m1wwjNGcf0/Q2kLnSSgzTuv8z0Z1/ZetRWQidKlGW4YMqtDds
5Dm4JrfMgQ+XJDUF9q+/wK2BIBHU5aCF/omvnr5LGINGb8ISVGp6rSN+YvYae29BANnjR9JKyu/g
Lw7z2OHhzntr77/xZGhnHdjZXiroCDveLsRVOvYerQ6f+gW+uaxjrFRNc9vB54xouw416A0JMbJu
3f1dcYq25q88lBnEsFNpNGcEkX942eAysT0tBl6B7yprzbCwgc64fSKLnmgaADBsgTwDkzwa2rNA
WBq9R7av0JeBYBfZV7mxTkq/7PG/me2Zm7MpyiI4oUjlUgMOfydwqR5JcnBC6tzY0yEaHtNROYD8
16gfMgMmjQPBKU8eqdop+aTZmdRGwe+WmTdCRakzJOI7ur1eE1RcCfV/mwExM+B3r78QtBOxteA4
AgQ7liA1Yq7wpwjhZrEYKUDGiMH9pNVF/d342Ah9Q7wTNv76syVooCfGnmWAl9c3i0Jw/8jfN3rZ
qEiuZWc+sNi18ZvPdVcKYcyRh78ulf8aCT4b4FhUuAhpR1ra2kvqmX4/287+UlD9Cvj+Llz7ukVh
S7lci3aCka2VjcvZD8z1LWSKrm9YgpFwCZUgwMsQcnqB5uT6zhPTnMcXhOgDW5PsoK+dSq2NqGlx
58/iKxP0uyU7Q8nVbedoCLnwEbUBJAdtp2lgmMXNxu5+JntV9ste0hTjWn0F9bpI0tyrZXWUYvnH
mLNBwAYf6+oggqViJmyOq4DFVI5PTZUFsuERNflhtu5Ou8JIZQ9ojw6HZRfXqAxQUpnNeCuO5SzF
THHW1yn3oBGVF3pNvo0My6eOvzD/FY7sJ6XeYFFQQ5D2Bar2wCm7qe3rmmHki4x5IL1rRVomFk87
BI17rFcE2ElA3v5zY+neOjH0KOXK0oFOZV2HWNP7qEK6HhELRnMJKUVcd7Y6JGo+INaz0EFuC/tl
71GyAYRxIQUd4uqHnhKHFXr++531FYTzeN9JRkbGcosRGTu4sOW68fSiu1IyoGDPoovFt1QxNWxk
XTsGJAP+Fv5Y6fsCkiaQSC/zBfbjWSYMpbL0ev+cX53/alDPJmVi1HoVM/whIzMH4Tg3GxvflovO
fbqGjcsbmddSWmn2hB8Lkt+vDlrpVF1t3q4cT8+wFgm/6Q/C/RIQhBChOUZLz7V2BZv4bVbEw+Hn
qbJnOr8KwoRT9DkcwKz/PeTXkNJebH+hVZU9H/E5VTXmXNZPT2DJ2XG/gDBc5AHfznydbQJmkg/z
/7J7NRb8n+MxGKE5cnBRh7+7rLo4poYiXQDPND0bZJ6mqrs1JvB3445uet+A7vGVcj6zqZSfmLIb
T5Lu2GOrewyNKyBZqKp9fI4vwzs3KXTLVs2kdt/cYWz+jP9JCFoehMm/y6fJfDwxZ51Nk5QVhLdC
obZoSyVk0iddhXXsgZq46sEwMPQU0mdvBCAqSRbggyPw+GABJhX971FAbBWsaLhNdKWaKtveHi98
k9F6cFtjFz8Vg8ad94pWEcDUJxmdOHzI2fe8c7yzDhG07YgALmmBgZE37y4GhJgA1OIEMSrOU3+e
PvPQP3UnVoggwcHNAYlOozBA685Be8haXACMOv4DCvOAKNQ5m5o8lI5t4CLrYy6q+F+n4/xzj42b
JZvjXUkRn2NXH9+N88K7Rw9F17uTBlLx0koxaHcGdNI4u2SdLBlDY/yYL32lnodW8QIHakQ0FETv
dmPGHK+dQYDo7qPQEqaHd4NiQay8zawB9ivxV5PokfQK94k1RkaVWj1rXRx/9913HleZ3cJYhJ7n
4VPfwWphuJCr12uJkFXVg+MK3Pj1pdJ6MKMXzED5q/byCXUyTo+ZxmHkIndOIzUo6zGa2eHCUicp
Uv46xobbE24ReyvirVX++RGprqj75nkGgZifEN7IMAUxbziG/h/4B7OcJRr1IDv47FUxknw1K+eJ
HUuUuI9APbQ0WVcwAfMz+RY02mUtM+TZWgqbysmuEaFZSAt96woHLditOUl6z2ArU4nU88lt7Ul+
br2JTLFhRFy01gHl/3rFAZ1qePyft0eiEASkece6k8Y+GC9rj3gHalwji85LDxWFCNy14o/DqO61
8Q7RGVMQX3Exv673sjnrtaAH4BDBRBuoUrXHxjVuejH6kSIUfn7nNzDmYO2qWvNqYmBTPTOsNlsz
yqAWH/Drz9uYe0CYBL+ixKg4Pey/HjY7rKL6divCnWTHkcPBx4qaK/a9CktXrLBYmBamsJJQFY8T
9SWfgTPG9LUXdlsWK0lt/fRFEIp9ryFDY76M4fd05c7Q7MWLPbiOCTHTj1MBn9c33TD/2a+lWrC4
0+vnu2aX6HtiUMfMbLo1rPrzUcEm5YWuFaQb5iip4Nww8jE45neb2mLKhU9YwprC0pifX8ZSLbZ8
fgm/yUH1TE+o3syGuPLMQRh7/EBtqF+B9c0Tsck1r2VdcoVvCaRO3oqDOl6E7nphgT/TyWQviVAJ
9JHgwyYqDDHP1qW//68hSv90Pp5Anl+MqOomhjsG/kIlZIVw3hH10yeGUbOtLhgYZmhT2bw6ztGZ
P2qrBqhqhBT0+c4hLdGb/j0D7Z+BUS3fzAsw348NxPEf7Xpwl06v8ptwmxEn/1sLihhoPyRFrFor
Wr/JRTCt53uXR+f1Hq40iW/WA0dfiu+amdr/xOr9iceyW1llGhIUO2rqWxE/S6rRA1pRGQIgSUXe
0W3nXGCKSMb2ELtaqkAI8S+yVm0CcUezwjDVgLbZfDTRu4oOfGik4YR8XS3ssUPGUfFmOnHGs4tg
UK1U46nr6EYgQYjrbkHlMfEKx/MnxV5VFJZI5Cpxb+iF5LHZSnSDJ+Vbc+g5bjIZaP7RXt4O0ZSx
gXM6fQzrcSiNdQE71/p6/sX5b9VmoX24uQGwHkdH6VLk74hn1qPAIXfB+cUAyaHZZ6pdUYB51WRT
XawDTFsvMhxS3uO4pfV5EKh8As+NTmAerhauRgAIZ/BNoweEHICr0A2CYQcLCCp+fwzam97OD5ed
PvEym/QI7Gq2yEU0bCp4WsWZzl6ssStuagxXMFUM4lCag4KlCSb6F1rSeLZTPcv9AKdpf02Llw7u
JGjXVFtDqwLNFS7qj073QiQqAVA+AXNX8YpwL05BK13kARbJYH3z6H7FRlf88s61vTkrddS32GeS
fITZ2y4Vd4QeeMrwOPKdlRUvXMGjIIZAFtQAtzMmZO/64I/t1nY/Lo9h6GQm0YtXIMph5vwFIYyd
f4VzVZxBQMzWjt82w3SuiXvijs+3cfdhtYuTxhwLoC0G2P5BllH9mtguKm9kh+FkPEKlhC5kPnnU
roZ+scA16ZvayMwt88ID4Vz4gyxHt1RmzdoCa5uLDUqCimh7c59FBtZpd5gP1SmrNN5Xp7MeKdcL
DqpIV5ghJMkVoNV5klApi2jxf+poL+hLYlWKM0KN2PJm+nJ4Fvw6YDVHhwzkCoAoSpHCLeLWZaRI
CgJUMqxMux2UnvA6DDRk62OB3BOzPKEmlJNWHd4TJWLrydTlu5Ei8m3IhZR76dxxZ4agas//9ug+
GEnyy5FqPbBgrCn9yX1cQq9VduIGTspQ1en/WCooDoV63bLgJ22Ff7U4+WoCgoKDtevGgB0Z6R10
leBdjtWWGX2tuOps8eiwsgA/8P7R1/V9ZhyZEpIJL0b+/26aHGRhe209ls6wtDl9P49hWMHJvIUj
IqJZshwZBt6aEWsTw2gLBo/IjPZn9EwoMog2RXBu98Sy+IGvdPx16pNh+XQnoQKipNdkmsxCPRdW
G03hQUGwjAo4wqz+aNA6aqDBHD6Fgx8z/xoa2FuFDIiS/V92lfSHJ820dtC/OPGfn54ghEtF328N
Ye75BAngOpKXUAj2x4Ju5ulXn7l9NjQBqsOIg9QgusAUNIYSqY4Vv9F2mkCupr35e3ApmEEKat/v
epAVqYg15rJZTSQIcqW7TQ+leh54yDW0ERwT1XwUdTuSG8uN4OV2jp36KLUoi619XYExly6OrRsk
HNZeMnDiLr5Wgd6NIBMGovGI4/ZMQK91IUcy+SXFb6kcUsshRCVGuoModCdxx+Gu1oF9Z0JhbWLL
zuItrsCg08oxTIfiwm7HfopBzP3LotABatCQkVNAzrcyNdttXzCVe8G1lET8DjfQQrXo0FFaIROf
JwUl2zbfJVXSSK7KWTW92wpJR/kQxij1Jd3/L+4yaqXEapxwqPvOD7JcdzP4z4Htn/h4XmeA9+r8
2GoT/FkyNArohQ6i3GbbCT7tzb5yznf3ANeHzgzhd+WOCXi+w/DMpadhyR0RFowVntsGojBiKYFT
+tZ4xmPr/WfHVxnuUv3wPv8lUW321488f8B0Bl9AGC662D1Pn70IrUbkziya3jOjYWbkjj32Ng9y
33VZj5NPioxWA3dZOGuNDSWD68BDcY3z/Juhc6z7wkD94gMP0cPCGPww4mc5vaHOAhnr0Hy6yznE
rzUH1QyIz0agjivB32t2i2PgjRVNG+SdMWgy9QSp8kiMiBRQ+1sFGuvc7lKjcNEI7VVzCVheJ73V
KKoHO961vHkG82VpYNZWvxSCNoxierSfKtKFWH99IrZIPMRBKhQpS91yoSV/Cdb5bBtLiV60OVIl
6q96DZ1C4JTSpghPA92e2DDqQQoGrS/dGvt1qUa642LrsloqM1Ouc2OWoIi5P6j2gUk/SSgKcHvf
C2yuQ8g/6APaMaoUjBx16wIGvN/znvM93PhQXHbaG/fFvfcvSbv1tDrH5Vketr1yqyI4UWs3NUU4
/MAR3tfcUXjxxKMkXUaGYkxz2roqZuoV+W2d6nts/h0ArMmlXfR23Vg+L7ZeNPyrXVInrSoQfjNo
j5OldZmF0oEkTiiO8UMDxXtejs4Uwopn6WIfjjIaa71x6rr2qKyyeRTinXDCpa9bIGa0aLavatFf
Szeub0rpfwseMmDZljowi9aD9bCiOTOjobuDg4zdY/EpEkfmHAY511x0pC3pFlnEjKZR37Wnw3ts
yKvPczuprX5lU66vakhaP4w62qkfe8XVvwJ8/98UVS0zO+56vujzrDkxsZAqzqdsWpSegABdgUHK
RhWmFwSK1+fXn3Xv/8Q1xlMZdbfwAJQRllh+BErroZL2SbAmlQ70eFbrfKi897p/GQJOpgunm4C9
G63YRYduxEnMOzQixbCmTEw0wA8u0/VatmNRPWvkous2qDvne9LBd+pWv96IpSYXn5I5mGOnPWeO
zYpuLDE9Y6ol934E+iOABux2ryg2KjdQERHZ7qp1fwZ5otXKeNW5CWlENzIicdmOhZBaMa9pkSvH
Dx+Vzu0YCq6s7hmkPRrEF7GIYg5CFRomHI4rC6+E5tDC6zWDWQlxOV7JpYmBFHnOEd+EF7hjw+LA
uPq0FMtDwh0e7eKYeCD/PVoLj58fpaaS7LLqhWVJI3zOqCjih3wAdQDUAK4RHCCg5Y2qXQZS/Hkw
r4vcfF7bJXU2+RGumm0hFOfzI3ol0VF37f4UI5dpHKRKzUUQyzCPf+C51cFe0gnt3NmsmGUji9Or
5LJa/PCvMUO2rq7usDElUsgD1SR6ec4eLXeZ6+TJrhXq9xUq/eLth6/gDQjQf8i+TxXvB1RRE7A9
zYyxv/ZjuVx9GeOErBZhR+VloLNPxsRtAw/ppoEYo3NtM704kuj5fo375ZIue+OLGol9EYlidmIw
w9jDlHMNZPErBSZl2mq8QtSeypbWZXxk2vjdtJyJCUTduCjlGZNacbBkygkPA6QdWvYR9XQ1RDHT
2Nm9zU/fKCTolAeeCzHoZAA2Ry6jJfXHdHMvEaeQbLc6wuQVE9xNp1wN6kMapyXjCEtlN5qHzEgR
2gbGhWVlDI1OgwEtCTVSTQAO2yJd1W8chTksBui4OlZDPYg5M12YxY3GgFOkac4M/ZMhY22D8JZC
L3akZY+DDExcZjic9ToHHknIaC6GTDV+TM855jKQvD+p2fuCP7PlDrscbZPTuR4cRqHuCDNlINmA
lEgeJTBLEL2F+6ifjyxVJkf7KubWl2RM9X2XtzODrB6L/p8biZnQGzl/dr/80hEVdr5SdAnK2P/t
L7/d304c07aJbbNtIKTSo1t77J9KjiVuOKg+UNJhKgtV2ijIIgld9hPF1rj67Ldp37+KS/LhklRZ
csc9fJIVlZ4V3tW1hXa4p/IHLgc7+glmV2qwoyyMGdzpychbpTzBL2aJvFaMH5p6Jy8lpAfppO+t
pMZueoDvbA95PW4pB6LBlrQuCmDC1oMH2NkzHQHbcj+Y2wZEWb3fcWnvRStVmv8yZuyh5kq8Bkcl
MW4istdeloQbEePha4kafopdNr9OCFagkY3YU9UokpdCoqktvEZay6SkihtN32DyBr8DqUp2UBSx
1cvSq5VFEwOFQ9I728LghMMUd8NYR3W/ieWkLfI2KxS3fFXSumXgwxLuzfYkORckhF3XCRvaP/UX
E0BwjZzF0RcF9IOVs4dchA2WCXPZvlmtxA60YHeYlkWkfWl+LRPM3PM6aYYpHGlE6o0SUDLFb75E
FA3lMpmOWuGE25az2xO9oL5CMwZSsV76WK4583o9HjqsI1/JASnK1dl+rXwztPO7FsCH4Fu8HC2S
zx7YGwn8x739dckIHhK14G39TukDOA7Vr0pYac+xQ7PxeysIK1HWRGMdHLhTC77LXgLxFsoEbA8+
E1AWxl1+53z/r2gRCvTZ5LsPrteCiFQkRV40UIaYurBp+mOnCybJZ5dvQ5KovQFf/BNazHw0xjBS
s1XamTZmjwk7KSTFxg7598oMxkbrnFP0QCRMGA8FIq0Th8tm2qF1clZd4uwndkmGVGFoZc3bVors
xM40v1BNPQPrv2DWFEjGXtCAeF5RY85ATLAIHydt3nfxVSvZUhUqJEj7wAQ9jeh3GcQ52xw3h/Mj
H6slMkO1ruxa3L4lP5UhqLMW63JkVNYF8Q/pDbu/2znjC7J8PYB49Lvl8GqqfXwkRKxE2RMqRofC
ys54GNQCWnAdkHuxbyxD2fG1Vw3uhkY1wWJcbbDVCtmUMv97Zl96q3u69IxaIh8ByuorTT2MN0Wo
nnN5NNTTK4cF0G7WhU4o92+oM9kLKY9sDyHH0XfRHUHfcwEdFkIZ1rj5/ZqtY5ILKe6bnYrXldLx
GBaju8hb5U/dvXSWFgeDwVD1JjaRmAER2TkbHplnE0nshU0IZt7OsGzin8Qj0u5KD0YoFAufE5fK
oyTFMLJH7ECXo86Yzn7fsYtOIPP1cM97CPNsauhBzM8AMPLHk/z5imO4oDr5FY8kmTvt7nr46sQa
H9yL/zhUC1H3cASagqtrs5GsjD7HCJr/uY1/8QPtyIsgeDflr37qNH5v8RyBIgLBzYStTgrS41uk
oa3NRxfOwfWEyGUlk1GPcgnl31KduycVJe+06AlvtL+9DkH3Xlb2ULbF7LiRXFlW/ST3incEv8gy
WAQgGJuEKhzCtL3ZT2quRg0Bz73J+Mzp8zWtgr7DLTnB3R99oQtCcWTkq9y+xbDOWqpx3q3l/52K
SuS/Kq3bkRIAjAiO69MLPwmkuVZ6/sVstzsZRfuzibcouNj2fAJLyi4rWDQ+bUgXnP4zPrWnRGJ1
oQSj7gzGl2dCM6OwEeNfnjCqwzztn/hg5HBPmwUCt75UroPkHPf3UGnyb677DCUn27Kf+uTgYqIU
jwI46jKKJLSBFQrneSkcPnDjRsfHyoY2YkCLaJTgdeVfx3JnlOuA/xyHq1LLn2il5HD/UsHqLJqD
r6aWZdWopLSw7QzQ1YBgEF9WvyL0Hs7A+ssEjNUH/QgUn9ps2ywXsX5yJ61CPXrTc3CvpGLVf14n
r/FiyZL2sKM0g3x5TDZkUaEniaW1pawhRuxJ/Xasy9iYHVhVlP1PkzVsQvcvlBOpIPkrXAdM2vQL
aHztAqwwYX5K/sX0Laaduwu+klohPNKYoMC19fK/OYPImOcxGAwnUGBVyDqU/1aIOUOBrFe0/TFk
un87ffLDGUHQJywxGd6UAcAHvlQwzg7FkSgjjTH1Bm8BKxfW5MlRXw4q6AWXBEjyDQiVLpjtBHga
EssLUC6omGC9sMhL8D6Sl5A9qiS69v3nv30elIsDbtMZwwGo1R150mwx6HDZ6GWzMM7GE3wAPqRy
YP+dfuluQSK1jaT3FE8pxY17c8ZlM/VOEP7Q156yZ9WhVOJ/MbGQ/OnsG4sgkRddS8xhsvoXDBOK
LnFevE4Jp27zb8wRjNSn5zLY4h0cBD4ir0rklP+65aIZSp3YMhPtm24jCGHvwBiSpXnoeR3fqoPn
kKFVwRPd/Z/8tyE7wWry5Y1kEMdq8pvvtv97KHOHasM9CgSawPAt8oxOGm64Uo4gKgx1R86e/YzF
n25HJX5PHzz/QzPds/zMU1ICuE8WSDDCmw3Cagrxn7h0clfv4zaPz2/Y9/CyhMNep5y4e3/PHFRA
OtYWEtjswC59jLfYuUM/dpu6sj7KWPnho2g7J/UOg/S263P6CDasrMDFWIi6NCvtKSka9jdg1w7e
Nm00fy4/YGsqAegCVSRpegndgSCT9iMwSsfR4l7eyS8Faa5eSjWvIcY2WWByQNAJ6vN+juv6BNA/
0DpVbUmQ7AF5D6rLqb5PU/GtMqTi05YH2dOCXG5YrFizxRPGpVteE85s8DOtGLs/UZvIc9ZFTo7D
duSKImwxSmKmahJzaIXIXc3qAhRpGEP8tVdbIAhW9r2IUF13h4fYVrK7eA9j1pkjWZ6D3B9OYehm
teGQn3peiTV7MmSiXX/LC9mgm4mXzMY0ud+2UMTF74HsLgGr6YZ0OrXqMsTD0+/8QT/BR3/sFQwh
2zI2i7hLWjt5+7NQP/Dd+tyeJt/P+Cwkf1hW44boKjpTEFBmmArNQq4AdpiW7xWOgsH4Ql+NBWfT
zWiODiJg4buxa7F4bjQwJUyknG+WMPlG5qCODFnetJINBSn0aD8CRGpFrvGVhPbp3rYQIqzJLPKp
KjzeU423o3eHOLRwwc7n5I8CY7O+nGoS+Wd9rsRkECwUKUa3dCAc1WxS5jV7NYynX4OHEcKZQekZ
O8kXZp46u79QyQpGIAvPZIFYSLLclyIdSZXREmd86K7QnjKKMUjV9XGGto6VUv7ZCM1xzE+utnUK
i8tru4AH1NmoPBSvCdWTLAetR4EGOuJWpKheSD/Bt76KC0V7tzjcftm1pauAls9hQXf8KpHUqjo5
KhBmbRZZ5kqs0BqxL0sKkWuyPpyRArdXAm13EHdGeYyYdzru1+z6oQyIXOW2yJVejaRh0HOvA3rv
w4RFjsnfBtHx6fVFORm3RsK77/37stKbN7pHmZOe5xRfXeeZOMYjgQG21wbzDWD92+gWxNW4LcD8
Grd0yaP34Lm44ckfR3cXHPXafRmLURfw8V6YzExBjjuBvGkv6vCBF/8xshXEjG9W8nnQw8DPav7n
PTmmbCIXMBy3jdd8APpaNqWSqfA0lq57QNRfAuE7eue8Oqiv/8WviNWWQR+NggBOzsht4nnzTFXP
qjL/X0GlPhyYKjfuU299d30Vk8X/yftDSP0gddJJ7Yp8IciMx3F0XwRL6e6A3jAS3uBkfrUCGup0
ExO4QFNW9tzRqbAxgzJVY82WF63L0CCUhxnsKK6iT37UYpreObQM8iBTiXI69GjTCKc0uQh+pBN8
8EcQhdK3gzFojLu6pGK/1J1pSo1QtghNAwTC2ap6lk3hJju/nT6yUWiuNh8p6SXvSkGLTs/F+WIW
CRqeH91u5qcXduxFA2vVJy17ymFjaek8vStGeAhzZIe62U6k9QsRuZKU9Z00OGZhgefnFp8ATWaW
0d/xhQh6JxakcUBdAvgJ62Ji4jwm0XM6rZKpCr4966CYsTb8iXMpW2cepHmwpdc7/Ui6Hnr5CxQ+
ZSxrs7qKoXvmrW47UD1TygXxuH1eErSWSSzGqWZ/2gHxAgoAsD7NAN/VhR+KIM8hPAOv97hv3la8
LGJcNDnxvVILp7HH0ySIi46A1HJ7zyRQYyB29KyB23UljI76HDej5Hq+JUJlGh394kkkqfANddyU
efRauLKL0HLt3vyWfg4IS9Vag+1xHtab3SeAn1+4x5u42POZPzBaAdukOvzUAnLScghi0ZL5AJ33
9hdp5zSZumqNQFq2q35wYgsCFM+XnaA9yf9N3mU31GoocdeB/woH6Tw5VK2uDiXuLrcQtcFy0Nsd
dwXbk8AmcDRcTrD+CmWCrZhIYjUS+iTWYvsXL+Ufql0P3//WTKOOakPAItpL0Ni7yhQakdb+j63p
bpQ6H/yBcQEDh5bJVUrQlISVHCjv82MjbVShVgM18N7O3So6u5VBlF6KVHBISX1rVs6m417N0zRB
F/uHO4N+I+pmFqCeJD2kVHabWI2Zf7VKmhN+cyfLKYtJF4u5jd+veozvCi4gTOKJz9QiLZb5g2U/
WfJl82A3tQzj1/YWH6QRtpmGE2DtTTiKd1erv3SMo8k0MnQRqeTC2jeK2Zx5gBp8QE4wPj/JZTCb
yjGqlJ+DVCKIz0oPxqRZTlm1IGkjjukaCRKpEh5Ri6qvn1kGRWf834nHIT8P3rhrtv9hTHyyHj1U
KonD4iaDUd8vxf64UhayndCqamI2jcPiksfQKSFZZ135LFkKSRZMrbMFZHuxNd/TdEeJjbA/tMj8
/ix5E/SGqDm+vyLYctBO9h/nQrjY5Oggonkn/Z6cJlLlHqMDemnwbxAkOQpqVmg+gSD8bbzHz+IU
VHCGtpc/0xkCWcmMPH/K2gC3qRQOF8/wfvxrS+WC13FBrs6tReiTuCYU8607yUlXxwdZGk9DUytR
dBE1hf6Q6ukMdqjXikhTsf2gQAvhm0BgcQxYOe84mTEwjX6YpVS1UROdGyGOLcDxu55hM1lzNAf7
0z8Jrg9Jsv/kV5kOOVyh5djOJnRRShxw5GB/8Cz7ejt/E4FjrgK9rRa8G24EBKH6ZTeHTtKCZ5QT
VuPlcnOH1o+P/h8h7qQK38eV5P1j6aPZlein6Tky/kyLRqMKkn0Wy5k7HlbXrU6HjwFphV+hr2tD
n7YC6W3EVRqgKTRV/I8NL0LSGMOJrx1u1zLXunOYnwr7kn3ncIgNGU5DdhhPjxR2hnCbhL1yNesI
wdFKcDobF57S6Ug76+x+UvotmQQo9vzLbGQ3FYd+1iboKwa5wKKc4dCVGAVFi/oto7BWBTs3cQ8j
JPxxz7/LP4Ts5YzE11suyTaTLi2IY2WpCXwa/Bd5JCF5RPATAQKi1ARijgYbRcVrPn0YmRnG9mhW
qhV8TZrEcAUtmpYmCKgu9Y9qt6UcRTocxsqGNgIilnJUqfpR9812Tb9ThnTGg0qrCtmQZis3Js1B
bgm+4Hp0pzZUWRSSkNhHN9ggnF9y0OMO0mgVo1nJD0HcvKnrVUbOv7HpUNUwZYBNtdNollCx8/Sb
CWA4U67YPgWZd1PUcbO2dtVWOZlx+IZgJQVMGKjLFzh0N+8gpb12yocNm1GrHxcVpWGVkOh6WHZZ
kRBNiDKvBj3UuMFgo9jOhJ+J4ZrSHyaLNpaLRAkO/jCd9vfM1uquS9jGw2AXb/E95aw2c/jL7NF4
ME5dWtjRUt++EojL/UjGDdsn+ExNOL1KiG5TjWeTyxsIAO2nRJUjfPIe8zZ7QWRtj1du+0UwOw0c
mD9p2VCLZlAdBEhzsQV6WO2mh9Cr6ngoUcCMR7ghLYP3YUJ2Zt01cnOl7AmY2S37esm/DO5hT8aM
kqY80UU8lXXK1O9SKaMspcw1FmoKVmwVCsMKwz6ztHODNCePpTof49SruufmMvAmzczJjiYaxpEh
zyQ4N+B1GkknYBbo3wlxW7ID2CMbg7s5XfBwpSXKk8fUew2tq9d00/iJ178hd8ezHE4GPC5VC/4G
IGxXYNCfjOgoYtEDGXnVLdEjWaY+KiImHpp/E6hcEj0IozS4F2IeVBb/kkBFiIDoMQ3mibl+845G
+xgzCU12P/iMv4Wjq8mQVgoONrSxZ8sXRqjyPMntWXIJkyYhNFirnfsl/UfZKIepshzrKowYBASX
zmJa6VJglFIhHd1G1kQsk59oAUeuqDNmX8kFiSsjrjXdXpNlzuCLEqzbJVHIVlLPOthuMp6Z9avS
qzGTzL9N9mI2mOZA8wKxzWJ6zYFd581pAxdvSUMWla2GxV7084yWAofRqTnmQJizjK56G+XJo0Pg
KJB0URYZPyxZOku/BAdF4htF4Z++fKb0mmsL65I5QjvZ9YrhWF2UlbT618GSvMXX6wl2kvOIlp8P
3YaN4R3MM8DzbV1hM6vW2nF4MMyofj0wa8niV9cTX0uJE+TGGg4zWHHgSrTAW32rHgAtuKJCDaE2
+C1x3nr60NSLeaPpQkln2MyHYm9c8btmCh/ljmxG+6kQ15XGqPG44XP+dW1Y7f7QF+KLZaBlnPL7
Jd596nWqxuWZvNGExkKoZascTDZCr79UGuH6k1/feJcAD0mrltefNpnraMJSH88VhlbBpPf5vvv9
YB4MDXDbUWLf1L68heSCz9x1E69+gcL0vuKMtTQj29iIXOkxGnLGq3Qqan0IbfbCBtFMJ1jG3xMF
stTsqI5p3iW2TL/MODOZHyPNx2bD6/aImAD0DPsnUx/NTuaE6IpfLpy31LRDqH8w554x/wTO7BnO
acgEgWGy0CZ+6qe4eTB9yp2VOZjalEXq1v5Fi0t9NeRBnMSXj198rEbVojAATRWB14pQxxX4oum/
kPpTPyPOfCtc8RsednacL7ngIx0iKRV0krMMPceySq7inoFCL0E6UBoFacyFOoHcifsSyxY8EG4l
3Cwf1yhAbw4RID822X9au59T0uDEwFVWeNEIXQZlbdfPuZSdwzMSTCMHxBRtjkYSMCshzMuFpVoV
rMhWMx1y0gelwR+jnfueWsRo2ubbboAS3AuqniuXUbldZYI0QMptrKAjsDL4v4XkVRIDxoswzlFa
xVXZAutZR/yKFsQiJDTWpkygRSBq5ue7LhSEwI2v35ngMlnE2EZWY2J2s3XSy2HUJMRsTI8Nu7c8
ie0imTZYtNa3/b5IzX1hDAhqT2yH0d4LNukr6u0zRUYipvDZOEmQp5Kee6/5uKQbTS3kvsNqZriK
0ykIPsb06QmiQiOlSTCW5swraq4O69A9FHgOjuHDYVfMMKZozHdRNq2e2crxxRGAm7rF/wm6jQq9
albed8ySim6Xuankg/6mNTexunOoM9XlZU4ySjNicgN3mEcCF8JtKzFYkC49nltpBG5PSGzxt4ZE
qvEGSgHDHPj5HgNNtYFlWUMzCix6czZjC/3THiEDqKXiaWVDkIGHm+KVCWZh0yfQ4eTurNo1gmN5
rubmdzzEAs6ObTWHcuCp4mjpItiR1Xsp8m1MmcFcmzUrYkZl25aYaUJWcqjINYX+37Cas1XFlVhM
+E9OwFL1ATxkpJJIFOXBLy4hRTk0pPJuXAfSR6hECMQalaZfRXpOHuxexdOs3IFhTg98lVHjbey9
ZQCi4WigBc8WN1O9ucyuaKHcit4lf4mbpzNHOKx9EvzBU4zIheHIdQ+XeIrnq6DJzxFOjEHsiz8l
+3ZS0EtE6HDHftl4hEdaQ2LtsZKRkr4FVv+c/9YII4l8J8ds4sRkcGBNyuRkngOw/nUKSWfvLGj5
ztgC0mL6ZUD2jPZNdMjuF49KyqJ5foDT77Jn1UPMFf0jlpIrlonU+EBIqiSASWSWKwT0N7qqaxf8
XP80CrYKSY4R2kLgmaBRY+okh+0JJHvuKwjuijItxz6fOtN1AO3YNNdn07W1jhmJIC5+S5HlMb14
hfJL+fI17VqrRGJK84EK5FD5HpYB4w9HxDHVEuREonWolNiVw5xbqctOAUhM9cTgpULpNz8AnJJu
+tfjTgK9xfwZCNiU17gYC9I6MLP670VMSyMJvNDhRj9Xmi+XhEbnCULK89/18N92YW3vUIx2XmPk
up8KJd06DBBT0A7PgNa2T96w/kEan0L8YpnQvNxqJMqT8q7k6nz1zhV3GnQQ3Hf1WzZBqyQ1E1rn
+oGyKtIKe2qTPavbGAbUVe2bKpI3P0nzPkje5UmnOY1HWgX1jlmlftWHiMIwsp8CufHYSLQ/yZrF
E6a3I4YOdu7GwKxrAb0xqh8CsVbMhONzyIR49lu+gd4k7kGHC6qb0f4GnziwvoV8+kukFzqUFEaY
nJMCONIwNsPGmFQmhTjiPHPHKVBNf8/ZP+NFGo2SseyMUQymBjKZiM5DUNXUHPoKEEFXUpP3NeFy
fkLP1zQ61OXeQTg3iLIy4m0Je06rgd/xJ+4CIBmzx4ebcc85MUFbYwgCiSMBrbbvdxiZ8PAPOOwL
y9Cx5ijKesN/EsrHAdis5mkO4i9IL4rWm7nCMmBqBvgGV2v+P+nRhL0gPL+1TfhIoHTKqgUowHKM
lpM7sRWSOKgZn/lbCIjZiZmt4DsK10SUjl946UIDucXTaCmGYdNYLeTgtACV68MhbVRCPAScLM32
jXAZGw0YABZTs3LCQa1Acwz7Rukn9N2MyK02fLf3aXdGMOqpXFq8lFaxW4YAMDFwXN3b5D47m+Nd
mi/UnJeVBJN5QJsVf9HSmYkpyW9MTYjYlrDo66XfdQnGHCCU329y0fIXqnkMe00igFRumm1MGbif
Dm+MGhJdq1/fweIj6j3hvtaAo8mvzaAP/tVOsFmbJtRsl/VhgoYOPv8aIlfmfk8A7xw6J5gXwi9K
6SxuSwtp1xdxnB7AdgJ9aWPXAb9zzZnmmXcEY/F3tt1t2ZSNzRpn/Dwr0R1xKZHG4XjxF8wU3mK7
vbCh0i3nVQ/Kwn4JFATYvVHbaXKFMxLv9Y+gk6zuqMYgUfi50o84q3XLVbLr8C6PayLLHHrZ3KxZ
PxPx8jeZogyohUdcGN3xGvrVNhGkeFsye8E0LM4zZd8YmUitU6F7m9EXJckj5tqcGlxI1xaSIzDn
6H4UK35RuJdS3BvPkeUoVePke53EwuZ4FUxFUktgwnV2GM1bQmzA/5wDX5ez7A54W1T7S0FNiWG4
9Gs1RMEWsX/x+3u9TBFnU9DfDeUdqRJp6gK7R/jxjTY7ogcezDoYj9SjULJhL/P3vOo2rKM9SFVT
boMP8Y5YXsXS/f7KvbZIRn2+ZPBoVFVRsh8P1pAWuk05m2UcmW7R5zavi6K2yCMKXrBaLL3rm7XY
Y8kFTkGlwZh9UGAN4pb56UpDy+uJXhTrL0xQpt8fBlOtuHNpd6WnhySQNpx2BQjeo0x80m7eVV/+
AgyVD9qfo9/d9AzpGBwYlKZ5mTYqiAofb+0e4WaACJ+CUfiKtnM8oTH2CUZsjBgOgAux0uflgC58
DvQxfyqF47cpKE9/zF9Zy3CsMKzV4/QUmXBhS478BcMg874u7Ls5ba0CwEx8fsEzda44I1pLFQeu
BAVbKfp9SX18wW7dn8SLQGLiwvn0f/6/q5JH0GxMtXZVKhHsFkT2JPkLDyTtkIHhQMey0awLjG+L
ZCY211AEbIrtfmZ49r3VAPxRENzEaWq7dPa3vHUzz2vo37GQyBBlnPZBY7WkWSDqu56I3pQSu4vp
aSAC6Zt8nIZkaeXrVPn169DvrJnPvWtlkdztlYFV0/VOYvM0fGzsBbF6+Uhypl+A
`protect end_protected
|
-------------------------------------------------------------------------------
--! @project Serialized hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity OutputGenerator is
port(
In0 : in std_logic_vector(63 downto 0);
DataIn : in std_logic_vector(63 downto 0);
Size : in std_logic_vector(2 downto 0);
Activate : in std_logic;
Out0 : out std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(63 downto 0));
end entity OutputGenerator;
architecture structural of OutputGenerator is
constant ALLZERO : std_logic_vector(63 downto 0) := (others => '0');
signal Temp0,Temp1,Temp2 : std_logic_vector(63 downto 0);
begin
Gen: process(In0,DataIn,Size,Activate,Temp0,Temp1,Temp2) is
-- Truncator0&1
procedure doTruncate0 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(63 downto 0);
signal Size : in std_logic_vector(2 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(63 downto 0)) is
variable ActSize : std_logic_vector(3 downto 0);
begin
ActSize(3) := Activate;
ActSize(2 downto 0) := Size;
-- if inactive it lets everything trough, if active it lets the first blocksize bits trough
logic: case ActSize is
when "1001" =>
Output(63 downto 56) <= Input(63 downto 56);
Output(55) <= '1';
Output(54 downto 0) <= ALLZERO(54 downto 0);
when "1010" =>
Output(63 downto 48) <= Input(63 downto 48);
Output(47) <= '1';
Output(46 downto 0) <= ALLZERO(46 downto 0);
when "1011" =>
Output(63 downto 40) <= Input(63 downto 40);
Output(39) <= '1';
Output(38 downto 0) <= ALLZERO(38 downto 0);
when "1100" =>
Output(63 downto 32) <= Input(63 downto 32);
Output(31) <= '1';
Output(30 downto 0) <= ALLZERO(30 downto 0);
when "1101" =>
Output(63 downto 24) <= Input(63 downto 24);
Output(23) <= '1';
Output(22 downto 0) <= ALLZERO(22 downto 0);
when "1110" =>
Output(63 downto 16) <= Input(63 downto 16);
Output(15) <= '1';
Output(14 downto 0) <= ALLZERO(14 downto 0);
when "1111" =>
Output(63 downto 8) <= Input(63 downto 8);
Output(7) <= '1';
Output(6 downto 0) <= ALLZERO(6 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate0;
-- Truncator2
procedure doTruncate2 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(63 downto 0);
signal Size : in std_logic_vector(2 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(63 downto 0)) is
variable ActSize : std_logic_vector(3 downto 0);
begin
ActSize(3) := Activate;
ActSize(2 downto 0) := Size;
-- if inactive it lets everything trough, if active it blocks the first blocksize bits
logic: case ActSize is
when "1000" =>
Output <= ALLZERO;
when "1001" =>
Output(63 downto 56) <= ALLZERO(63 downto 56);
Output(55 downto 0) <= Input(55 downto 0);
when "1010" =>
Output(63 downto 48) <= ALLZERO(63 downto 48);
Output(47 downto 0) <= Input(47 downto 0);
when "1011" =>
Output(63 downto 40) <= ALLZERO(63 downto 40);
Output(39 downto 0) <= Input(39 downto 0);
when "1100" =>
Output(63 downto 32) <= ALLZERO(63 downto 32);
Output(31 downto 0) <= Input(31 downto 0);
when "1101" =>
Output(63 downto 24) <= ALLZERO(63 downto 24);
Output(23 downto 0) <= Input(23 downto 0);
when "1110" =>
Output(63 downto 16) <= ALLZERO(63 downto 16);
Output(15 downto 0) <= Input(15 downto 0);
when "1111" =>
Output(63 downto 8) <= ALLZERO(63 downto 8);
Output(7 downto 0) <= Input(7 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate2;
begin
-- DataOut
DataOut <= In0 xor DataIn;
-- Stateupdate
doTruncate0(DataIn,Size,Activate,Temp0);
Temp1 <= In0;
doTruncate2(Temp1,Size,Activate,Temp2);
Out0 <= Temp0 xor Temp2;
end process Gen;
end architecture structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity screen_position_gen is
port (
-- inputs
nrst : in std_logic;
clk108 : in std_logic;
vblank : in std_logic;
in_line_change : in std_logic;
in_page_change : in std_logic;
in_column : in integer range 0 to 1279;
in_column_change : in std_logic;
-- outputs
segment : out integer range 0 to 15;
segment_change : out std_logic;
subsegment : out integer range 0 to 3;
subsegment_change : out std_logic;
line : out integer range 0 to 15;
out_line_change : out std_logic;
out_column : out integer range 0 to 1279;
out_column_mod_8 : out integer range 0 to 7;
out_column_div_8 : out integer range 0 to 159;
out_column_change : out std_logic;
out_page_change : out std_logic;
active_pixgen_source : out PIXGEN_SOURCE_T
);
end screen_position_gen;
architecture behavioral of screen_position_gen is
signal internal_segment : integer range 0 to 15;
signal internal_subsegment : integer range 0 to 3;
signal internal_line : integer range 0 to 15;
signal next_segment : integer range 0 to 15;
signal next_subsegment : integer range 0 to 3;
signal next_line : integer range 0 to 15;
begin
segment <= internal_segment;
subsegment <= internal_subsegment;
line <= internal_line;
-- This process calculates next_line, next_subsegment, next_segment signals
process (in_line_change, in_page_change, internal_segment, internal_subsegment, internal_line) is
begin
if in_page_change = '1' then
next_line <= 0;
next_subsegment <= 0;
next_segment <= 0;
else
if in_line_change = '1' then
if internal_line = 15 then
next_line <= 0;
if internal_subsegment = 3 then
next_subsegment <= 0;
if internal_segment = 15 then
next_segment <= 0;
else
next_segment <= internal_segment + 1;
end if;
else
next_subsegment <= internal_subsegment + 1;
next_segment <= internal_segment;
end if;
else
next_line <= internal_line + 1;
next_subsegment <= internal_subsegment;
next_segment <= internal_segment;
end if;
else
next_line <= internal_line;
next_subsegment <= internal_subsegment;
next_segment <= internal_segment;
end if;
end if;
end process;
-- This proces generates all output signals
process (clk108, nrst) is
begin
if nrst = '0' then
elsif rising_edge (clk108) then
internal_line <= next_line;
internal_subsegment <= next_subsegment;
internal_segment <= next_segment;
out_line_change <= in_line_change;
if internal_subsegment /= next_subsegment then
subsegment_change <= '1';
else
subsegment_change <= '0';
end if;
if internal_segment /= next_segment then
segment_change <= '1';
else
segment_change <= '0';
end if;
out_column <= in_column;
out_column_mod_8 <= in_column mod 8;
out_column_div_8 <= in_column / 8;
out_column_change <= in_column_change;
out_page_change <= in_page_change;
if vblank = '1' then
active_pixgen_source <= BLANK_PIXGEN_T;
elsif next_segment < 14 then
if next_subsegment /= 3 then
active_pixgen_source <= TRACE_PIXGEN_T;
else
active_pixgen_source <= TIME_BASE_PIXGEN_T;
end if;
else
active_pixgen_source <= SETTINGS_PIXGEN_T;
end if;
end if;
end process;
end architecture behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
USE ieee.numeric_std.all;
entity memory is
port(
clk : IN STD_LOGIC;
reset: IN STD_LOGIC;
new_data: IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(17 downto 0); -- data input
data_out : OUT STD_LOGIC_VECTOR(17 downto 0); -- data output
ready : OUT STD_LOGIC
);
end memory;
architecture logic of memory is
type machine is(collect, send, save);
signal state : machine;
signal save_val_sig : STD_LOGIC;
signal zero_level_sig : STD_LOGIC_VECTOR(27 downto 0);
signal difference : STD_LOgic_vector(27 downto 0);
signal ready_sig : STD_LOGIC; -- end of collecting and averaging
signal data : STD_LOGIC_VECTOR(27 downto 0); -- internal data vector
signal data_processed : STD_LOGIC_VECTOR(17 downto 0); -- data to send to output
begin
process (clk, reset)
variable count : INTEGER; -- vector of averages count
begin
if reset = '1' then
data <= (others =>'0');
data_processed <= (others =>'0');
count := 0;
ready_sig <= '0';
save_val_sig <= '1';
state <= collect;
elsif clk'event and clk = '1' then
case state is
when collect =>
if new_data = '1' then
--data <= std_logic_vector(signed(data) + signed(data_in)); -- data + data_in;
data <= data + data_in;
--count <= std_logic_vector(unsigned(count) + unsigned(1)); --count++
count := count + 1;
ready_sig <= '0';
if count = 1023 then --kiedy zbierze 1024 prołbki
count := 0; --wyczyść count
if save_val_sig = '1' then
state <= save;
end if;
state <= send; --przejdĹş do stanu send
end if;
end if;
when send =>
if data(9) = '1' then --jeżeli 10 bit jest 1 to po dzieleniu dodaj 1 bo zaokrÄ…glenia
--data_processed <= (data srl 10) + conv_std_logic_vector(1, 18);
difference <= data - zero_level_sig; --(27 downto 10) + 1;
data_processed <= difference(27 downto 10) + 1;
else
difference <= data - zero_level_sig; --(27 downto 10) + 1;
data_processed <= difference(27 downto 10);
end if;
data <= (others =>'0'); --wyczysc dane wewnetrzne
ready_sig <= '1'; --wystaw 1 na ready
state <= collect;
when save =>
zero_level_sig <= data;
data <= (others =>'0'); --wyczysc dane wewnetrzne
state <= collect;
save_val_sig <= '0';
end case;
end if;
end process;
data_out <= data_processed; --przypisanie na wyjscie
ready <= ready_sig;
end logic;
|
entity crash_entity is end entity;
architecture default of crash_entity is
type rec is record
v : natural;
end record;
attribute s : rec;
function func return boolean is
begin
return s.v = 0;
end function;
begin
end architecture;
|
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