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------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncreg
-- File: syncreg.vhd
-- Author: Aeroflex Gaisler AB
-- Description: Technology wrapper for sync registers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity syncreg is
generic (
tech : integer := 0;
stages : integer range 1 to 5 := 2
);
port (
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic
);
end;
architecture tmap of syncreg is
begin
sync0 : if has_syncreg(tech) = 0 generate
--syncreg : block
-- signal c : std_logic_vector(stages-1 downto 0);
--begin
-- x0 : process(clk)
-- begin
-- if rising_edge(clk) then
-- for i in 0 to stages-1 loop
-- c(i) <= d;
-- if i /= 0 then c(i) = c(i-1); end if;
-- end loop;
-- end if;
-- end process;
-- q <= c(stages-1);
--end block syncreg;
syncreg : block
signal c : std_logic_vector(stages downto 0);
begin
c(0) <= d;
syncregs : for i in 1 to stages generate
dff : grdff
generic map(tech => tech)
port map(clk => clk, d => c(i-1), q => c(i));
end generate;
q <= c(stages);
end block syncreg;
end generate;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ToPixelWinner is
Port (
DataIn : in STD_LOGIC_VECTOR (107 downto 0);
Column : in STD_LOGIC_VECTOR (6 downto 0);
PixelOut : out STD_LOGIC
);
end ToPixelWinner;
architecture Behavioral of ToPixelWinner is
begin
--Select pixel data in accordance to column
process(DataIn,Column)
begin
if Column = "0000001" then
PixelOut <= DataIn(107);
elsif
Column = "0000010" then
PixelOut <= DataIn(106);
elsif
Column = "0000011" then
PixelOut <= DataIn(105);
elsif
Column = "0000100" then
PixelOut <= DataIn(104);
elsif
Column = "0000101" then
PixelOut <= DataIn(103);
elsif
Column = "0000110" then
PixelOut <= DataIn(102);
elsif
Column = "0000111" then
PixelOut <= DataIn(101);
elsif
Column = "0001000" then
PixelOut <= DataIn(100);
elsif
Column = "0001001" then
PixelOut <= DataIn(99);
elsif
Column = "0001010" then
PixelOut <= DataIn(98);
elsif
Column = "0001011" then
PixelOut <= DataIn(97);
elsif
Column = "0001100" then
PixelOut <= DataIn(96);
elsif
Column = "0001101" then
PixelOut <= DataIn(95);
elsif
Column = "0001110" then
PixelOut <= DataIn(94);
elsif
Column = "0001111" then
PixelOut <= DataIn(93);
elsif
Column = "0010000" then
PixelOut <= DataIn(92);
elsif
Column = "0010001" then
PixelOut <= DataIn(91);
elsif
Column = "0010010" then
PixelOut <= DataIn(90);
elsif
Column = "0010011" then
PixelOut <= DataIn(89);
elsif
Column = "0010100" then
PixelOut <= DataIn(88);
elsif
Column = "0010101" then
PixelOut <= DataIn(87);
elsif
Column = "0010110" then
PixelOut <= DataIn(86);
elsif
Column = "0010111" then
PixelOut <= DataIn(85);
elsif
Column = "0011000" then
PixelOut <= DataIn(84);
elsif
Column = "0011001" then
PixelOut <= DataIn(83);
elsif
Column = "0011010" then
PixelOut <= DataIn(82);
elsif
Column = "0011011" then
PixelOut <= DataIn(81);
elsif
Column = "0011100" then
PixelOut <= DataIn(80);
elsif
Column = "0011101" then
PixelOut <= DataIn(79);
elsif
Column = "0011110" then
PixelOut <= DataIn(78);
elsif
Column = "0011111" then
PixelOut <= DataIn(77);
elsif
Column = "0100000" then
PixelOut <= DataIn(76);
elsif
Column = "0100001" then
PixelOut <= DataIn(75);
elsif
Column = "0100010" then
PixelOut <= DataIn(74);
elsif
Column = "0100011" then
PixelOut <= DataIn(73);
elsif
Column = "0100100" then
PixelOut <= DataIn(72);
elsif
Column = "0100101" then
PixelOut <= DataIn(71);
elsif
Column = "0100110" then
PixelOut <= DataIn(70);
elsif
Column = "0100111" then
PixelOut <= DataIn(69);
elsif
Column = "0101000" then
PixelOut <= DataIn(68);
elsif
Column = "0101001" then
PixelOut <= DataIn(67);
elsif
Column = "0101010" then
PixelOut <= DataIn(66);
elsif
Column = "0101011" then
PixelOut <= DataIn(65);
elsif
Column = "0101100" then
PixelOut <= DataIn(64);
elsif
Column = "0101101" then
PixelOut <= DataIn(63);
elsif
Column = "0101110" then
PixelOut <= DataIn(62);
elsif
Column = "0101111" then
PixelOut <= DataIn(61);
elsif
Column = "0110000" then
PixelOut <= DataIn(60);
elsif
Column = "0110001" then
PixelOut <= DataIn(59);
elsif
Column = "0110010" then
PixelOut <= DataIn(58);
elsif
Column = "0110011" then
PixelOut <= DataIn(57);
elsif
Column = "0110100" then
PixelOut <= DataIn(56);
elsif
Column = "0110101" then
PixelOut <= DataIn(55);
elsif
Column = "0110110" then
PixelOut <= DataIn(54);
elsif
Column = "0110111" then
PixelOut <= DataIn(53);
elsif
Column = "0111000" then
PixelOut <= DataIn(52);
elsif
Column = "0111001" then
PixelOut <= DataIn(51);
elsif
Column = "0111010" then
PixelOut <= DataIn(50);
elsif
Column = "0111011" then
PixelOut <= DataIn(49);
elsif
Column = "0111100" then
PixelOut <= DataIn(48);
elsif
Column = "0111101" then
PixelOut <= DataIn(47);
elsif
Column = "0111110" then
PixelOut <= DataIn(46);
elsif
Column = "0111111" then
PixelOut <= DataIn(45);
elsif
Column = "1000000" then
PixelOut <= DataIn(44);
elsif
Column = "1000001" then
PixelOut <= DataIn(43);
elsif
Column = "1000010" then
PixelOut <= DataIn(42);
elsif
Column = "1000011" then
PixelOut <= DataIn(41);
elsif
Column = "1000100" then
PixelOut <= DataIn(40);
elsif
Column = "1000101" then
PixelOut <= DataIn(39);
elsif
Column = "1000110" then
PixelOut <= DataIn(38);
elsif
Column = "1000111" then
PixelOut <= DataIn(37);
elsif
Column = "1001000" then
PixelOut <= DataIn(36);
elsif
Column = "1001001" then
PixelOut <= DataIn(35);
elsif
Column = "1001010" then
PixelOut <= DataIn(34);
elsif
Column = "1001011" then
PixelOut <= DataIn(33);
elsif
Column = "1001100" then
PixelOut <= DataIn(32);
elsif
Column = "1001101" then
PixelOut <= DataIn(31);
elsif
Column = "1001110" then
PixelOut <= DataIn(30);
elsif
Column = "1001111" then
PixelOut <= DataIn(29);
elsif
Column = "1010000" then
PixelOut <= DataIn(28);
elsif
Column = "1010001" then
PixelOut <= DataIn(27);
elsif
Column = "1010010" then
PixelOut <= DataIn(26);
elsif
Column = "1010011" then
PixelOut <= DataIn(25);
elsif
Column = "1010100" then
PixelOut <= DataIn(24);
elsif
Column = "1010101" then
PixelOut <= DataIn(23);
elsif
Column = "1010110" then
PixelOut <= DataIn(22);
elsif
Column = "1010111" then
PixelOut <= DataIn(21);
elsif
Column = "1011000" then
PixelOut <= DataIn(20);
elsif
Column = "1011001" then
PixelOut <= DataIn(19);
elsif
Column = "1011010" then
PixelOut <= DataIn(18);
elsif
Column = "1011011" then
PixelOut <= DataIn(17);
elsif
Column = "1011100" then
PixelOut <= DataIn(16);
elsif
Column = "1011101" then
PixelOut <= DataIn(15);
elsif
Column = "1011110" then
PixelOut <= DataIn(14);
elsif
Column = "1011111" then
PixelOut <= DataIn(13);
elsif
Column = "1100000" then
PixelOut <= DataIn(12);
elsif
Column = "1100001" then
PixelOut <= DataIn(11);
elsif
Column = "1100010" then
PixelOut <= DataIn(10);
elsif
Column = "1100011" then
PixelOut <= DataIn(9);
elsif
Column = "1100100" then
PixelOut <= DataIn(8);
elsif
Column = "1100101" then
PixelOut <= DataIn(7);
elsif
Column = "1100110" then
PixelOut <= DataIn(6);
elsif
Column = "1100111" then
PixelOut <= DataIn(5);
elsif
Column = "1101000" then
PixelOut <= DataIn(4);
elsif
Column = "1101001" then
PixelOut <= DataIn(3);
elsif
Column = "1101010" then
PixelOut <= DataIn(2);
elsif
Column = "1101011" then
PixelOut <= DataIn(1);
else
PixelOut <= DataIn(0);
end if;
end process;
end Behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:FlagReg:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_FlagReg_0_1 IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END RAT_FlagReg_0_1;
ARCHITECTURE RAT_FlagReg_0_1_arch OF RAT_FlagReg_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_FlagReg_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT FlagReg IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END COMPONENT FlagReg;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : FlagReg
PORT MAP (
IN_FLAG => IN_FLAG,
LD => LD,
SET => SET,
CLR => CLR,
CLK => CLK,
OUT_FLAG => OUT_FLAG
);
END RAT_FlagReg_0_1_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:module_ref:FlagReg:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY RAT_FlagReg_0_1 IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END RAT_FlagReg_0_1;
ARCHITECTURE RAT_FlagReg_0_1_arch OF RAT_FlagReg_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_FlagReg_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT FlagReg IS
PORT (
IN_FLAG : IN STD_LOGIC;
LD : IN STD_LOGIC;
SET : IN STD_LOGIC;
CLR : IN STD_LOGIC;
CLK : IN STD_LOGIC;
OUT_FLAG : OUT STD_LOGIC
);
END COMPONENT FlagReg;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK";
BEGIN
U0 : FlagReg
PORT MAP (
IN_FLAG => IN_FLAG,
LD => LD,
SET => SET,
CLR => CLR,
CLK => CLK,
OUT_FLAG => OUT_FLAG
);
END RAT_FlagReg_0_1_arch;
|
--**********************************************************************************************
-- Components declarations for JTAG OCD and "Flash" Programmer
-- Version 0.2A
-- Modified 31.05.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGCompPack is
component OCDProgTCK is port(
-- JTAG related inputs/outputs
TRSTn : in std_logic; -- Optional
TMS : in std_logic;
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TDO_OE : out std_logic;
-- From/To cp2 clock domain("Flash" programmer)
FlEEPrgAdr : out std_logic_vector(15 downto 0);
FlPrgRdData : in std_logic_vector(15 downto 0);
EEPrgRdData : in std_logic_vector(7 downto 0);
FlEEPrgWrData : out std_logic_vector(15 downto 0);
ChipEraseStart : out std_logic;
ChipEraseDone : in std_logic;
ProgEnable : out std_logic;
FlWrMStart : out std_logic; -- Multiple
FlWrSStart : out std_logic; -- Single
FlRdMStart : out std_logic; -- Multiple
FlRdSStart : out std_logic; -- Single
EEWrStart : out std_logic;
EERdStart : out std_logic;
TAPCtrlTLR : out std_logic; -- TAP Controller is in the Test-Logic/Reset state
-- CPU reset
jtag_rst : out std_logic
);
end component;
component OCDProgcp2 is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
-- From/To TCK clock domain("Flash" programmer)
FlEEPrgAdr : in std_logic_vector(15 downto 0);
FlPrgRdData : out std_logic_vector(15 downto 0);
EEPrgRdData : out std_logic_vector(7 downto 0);
FlEEPrgWrData : in std_logic_vector(15 downto 0);
ChipEraseStart : in std_logic;
ChipEraseDone : out std_logic;
ProgEnable : in std_logic;
FlWrMStart : in std_logic; -- Multiple
FlWrSStart : in std_logic; -- Single
FlRdMStart : in std_logic; -- Multiple
FlRdSStart : in std_logic; -- Single
EEWrStart : in std_logic;
EERdStart : in std_logic;
TAPCtrlTLR : in std_logic; -- TAP Controller is in the Test-Logic/Reset state
-- From the core
PC : in std_logic_vector(15 downto 0);
-- To the PM("Flash")
pm_adr : out std_logic_vector(15 downto 0);
pm_h_we : out std_logic;
pm_l_we : out std_logic;
pm_dout : in std_logic_vector(15 downto 0);
pm_din : out std_logic_vector(15 downto 0);
-- To the "EEPROM"
EEPrgSel : out std_logic;
EEAdr : out std_logic_vector(11 downto 0);
EEWrData : out std_logic_vector(7 downto 0);
EERdData : in std_logic_vector(7 downto 0);
EEWr : out std_logic
);
end component;
component Resync1b_cp2 is port(
cp2 : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end component;
component Resync1b_TCK is port(
TCK : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end component;
component Resync16b_TCK is port(
TCK : in std_logic;
DIn : in std_logic_vector(15 downto 0);
DOut : out std_logic_vector(15 downto 0)
);
end component;
end JTAGCompPack;
|
--**********************************************************************************************
-- Components declarations for JTAG OCD and "Flash" Programmer
-- Version 0.2A
-- Modified 31.05.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGCompPack is
component OCDProgTCK is port(
-- JTAG related inputs/outputs
TRSTn : in std_logic; -- Optional
TMS : in std_logic;
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TDO_OE : out std_logic;
-- From/To cp2 clock domain("Flash" programmer)
FlEEPrgAdr : out std_logic_vector(15 downto 0);
FlPrgRdData : in std_logic_vector(15 downto 0);
EEPrgRdData : in std_logic_vector(7 downto 0);
FlEEPrgWrData : out std_logic_vector(15 downto 0);
ChipEraseStart : out std_logic;
ChipEraseDone : in std_logic;
ProgEnable : out std_logic;
FlWrMStart : out std_logic; -- Multiple
FlWrSStart : out std_logic; -- Single
FlRdMStart : out std_logic; -- Multiple
FlRdSStart : out std_logic; -- Single
EEWrStart : out std_logic;
EERdStart : out std_logic;
TAPCtrlTLR : out std_logic; -- TAP Controller is in the Test-Logic/Reset state
-- CPU reset
jtag_rst : out std_logic
);
end component;
component OCDProgcp2 is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
-- From/To TCK clock domain("Flash" programmer)
FlEEPrgAdr : in std_logic_vector(15 downto 0);
FlPrgRdData : out std_logic_vector(15 downto 0);
EEPrgRdData : out std_logic_vector(7 downto 0);
FlEEPrgWrData : in std_logic_vector(15 downto 0);
ChipEraseStart : in std_logic;
ChipEraseDone : out std_logic;
ProgEnable : in std_logic;
FlWrMStart : in std_logic; -- Multiple
FlWrSStart : in std_logic; -- Single
FlRdMStart : in std_logic; -- Multiple
FlRdSStart : in std_logic; -- Single
EEWrStart : in std_logic;
EERdStart : in std_logic;
TAPCtrlTLR : in std_logic; -- TAP Controller is in the Test-Logic/Reset state
-- From the core
PC : in std_logic_vector(15 downto 0);
-- To the PM("Flash")
pm_adr : out std_logic_vector(15 downto 0);
pm_h_we : out std_logic;
pm_l_we : out std_logic;
pm_dout : in std_logic_vector(15 downto 0);
pm_din : out std_logic_vector(15 downto 0);
-- To the "EEPROM"
EEPrgSel : out std_logic;
EEAdr : out std_logic_vector(11 downto 0);
EEWrData : out std_logic_vector(7 downto 0);
EERdData : in std_logic_vector(7 downto 0);
EEWr : out std_logic
);
end component;
component Resync1b_cp2 is port(
cp2 : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end component;
component Resync1b_TCK is port(
TCK : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end component;
component Resync16b_TCK is port(
TCK : in std_logic;
DIn : in std_logic_vector(15 downto 0);
DOut : out std_logic_vector(15 downto 0)
);
end component;
end JTAGCompPack;
|
--**********************************************************************************************
-- Components declarations for JTAG OCD and "Flash" Programmer
-- Version 0.2A
-- Modified 31.05.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGCompPack is
component OCDProgTCK is port(
-- JTAG related inputs/outputs
TRSTn : in std_logic; -- Optional
TMS : in std_logic;
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TDO_OE : out std_logic;
-- From/To cp2 clock domain("Flash" programmer)
FlEEPrgAdr : out std_logic_vector(15 downto 0);
FlPrgRdData : in std_logic_vector(15 downto 0);
EEPrgRdData : in std_logic_vector(7 downto 0);
FlEEPrgWrData : out std_logic_vector(15 downto 0);
ChipEraseStart : out std_logic;
ChipEraseDone : in std_logic;
ProgEnable : out std_logic;
FlWrMStart : out std_logic; -- Multiple
FlWrSStart : out std_logic; -- Single
FlRdMStart : out std_logic; -- Multiple
FlRdSStart : out std_logic; -- Single
EEWrStart : out std_logic;
EERdStart : out std_logic;
TAPCtrlTLR : out std_logic; -- TAP Controller is in the Test-Logic/Reset state
-- CPU reset
jtag_rst : out std_logic
);
end component;
component OCDProgcp2 is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
-- From/To TCK clock domain("Flash" programmer)
FlEEPrgAdr : in std_logic_vector(15 downto 0);
FlPrgRdData : out std_logic_vector(15 downto 0);
EEPrgRdData : out std_logic_vector(7 downto 0);
FlEEPrgWrData : in std_logic_vector(15 downto 0);
ChipEraseStart : in std_logic;
ChipEraseDone : out std_logic;
ProgEnable : in std_logic;
FlWrMStart : in std_logic; -- Multiple
FlWrSStart : in std_logic; -- Single
FlRdMStart : in std_logic; -- Multiple
FlRdSStart : in std_logic; -- Single
EEWrStart : in std_logic;
EERdStart : in std_logic;
TAPCtrlTLR : in std_logic; -- TAP Controller is in the Test-Logic/Reset state
-- From the core
PC : in std_logic_vector(15 downto 0);
-- To the PM("Flash")
pm_adr : out std_logic_vector(15 downto 0);
pm_h_we : out std_logic;
pm_l_we : out std_logic;
pm_dout : in std_logic_vector(15 downto 0);
pm_din : out std_logic_vector(15 downto 0);
-- To the "EEPROM"
EEPrgSel : out std_logic;
EEAdr : out std_logic_vector(11 downto 0);
EEWrData : out std_logic_vector(7 downto 0);
EERdData : in std_logic_vector(7 downto 0);
EEWr : out std_logic
);
end component;
component Resync1b_cp2 is port(
cp2 : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end component;
component Resync1b_TCK is port(
TCK : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end component;
component Resync16b_TCK is port(
TCK : in std_logic;
DIn : in std_logic_vector(15 downto 0);
DOut : out std_logic_vector(15 downto 0)
);
end component;
end JTAGCompPack;
|
--**********************************************************************************************
-- Components declarations for JTAG OCD and "Flash" Programmer
-- Version 0.2A
-- Modified 31.05.2006
-- Designed by Ruslan Lepetenok
--**********************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package JTAGCompPack is
component OCDProgTCK is port(
-- JTAG related inputs/outputs
TRSTn : in std_logic; -- Optional
TMS : in std_logic;
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TDO_OE : out std_logic;
-- From/To cp2 clock domain("Flash" programmer)
FlEEPrgAdr : out std_logic_vector(15 downto 0);
FlPrgRdData : in std_logic_vector(15 downto 0);
EEPrgRdData : in std_logic_vector(7 downto 0);
FlEEPrgWrData : out std_logic_vector(15 downto 0);
ChipEraseStart : out std_logic;
ChipEraseDone : in std_logic;
ProgEnable : out std_logic;
FlWrMStart : out std_logic; -- Multiple
FlWrSStart : out std_logic; -- Single
FlRdMStart : out std_logic; -- Multiple
FlRdSStart : out std_logic; -- Single
EEWrStart : out std_logic;
EERdStart : out std_logic;
TAPCtrlTLR : out std_logic; -- TAP Controller is in the Test-Logic/Reset state
-- CPU reset
jtag_rst : out std_logic
);
end component;
component OCDProgcp2 is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
-- From/To TCK clock domain("Flash" programmer)
FlEEPrgAdr : in std_logic_vector(15 downto 0);
FlPrgRdData : out std_logic_vector(15 downto 0);
EEPrgRdData : out std_logic_vector(7 downto 0);
FlEEPrgWrData : in std_logic_vector(15 downto 0);
ChipEraseStart : in std_logic;
ChipEraseDone : out std_logic;
ProgEnable : in std_logic;
FlWrMStart : in std_logic; -- Multiple
FlWrSStart : in std_logic; -- Single
FlRdMStart : in std_logic; -- Multiple
FlRdSStart : in std_logic; -- Single
EEWrStart : in std_logic;
EERdStart : in std_logic;
TAPCtrlTLR : in std_logic; -- TAP Controller is in the Test-Logic/Reset state
-- From the core
PC : in std_logic_vector(15 downto 0);
-- To the PM("Flash")
pm_adr : out std_logic_vector(15 downto 0);
pm_h_we : out std_logic;
pm_l_we : out std_logic;
pm_dout : in std_logic_vector(15 downto 0);
pm_din : out std_logic_vector(15 downto 0);
-- To the "EEPROM"
EEPrgSel : out std_logic;
EEAdr : out std_logic_vector(11 downto 0);
EEWrData : out std_logic_vector(7 downto 0);
EERdData : in std_logic_vector(7 downto 0);
EEWr : out std_logic
);
end component;
component Resync1b_cp2 is port(
cp2 : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end component;
component Resync1b_TCK is port(
TCK : in std_logic;
DIn : in std_logic;
DOut : out std_logic
);
end component;
component Resync16b_TCK is port(
TCK : in std_logic;
DIn : in std_logic_vector(15 downto 0);
DOut : out std_logic_vector(15 downto 0)
);
end component;
end JTAGCompPack;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and functions
-- associated to the PoC.fifo namespace
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library poc;
use PoC.utils.all;
package fifo is
-- Minimal FIFO with single clock to decouple enable domains.
component fifo_glue
generic (
D_BITS : positive -- Data Width
);
port (
-- Control
clk : in std_logic; -- Clock
rst : in std_logic; -- Synchronous Reset
-- Input
put : in std_logic; -- Put Value
di : in std_logic_vector(D_BITS - 1 downto 0); -- Data Input
ful : out std_logic; -- Full
-- Output
vld : out std_logic; -- Data Available
do : out std_logic_vector(D_BITS - 1 downto 0); -- Data Output
got : in std_logic -- Data Consumed
);
end component;
-- Minimal Local-Link-FIFO with single clock and first-word-fall-through mode.
component fifo_ll_glue
generic (
D_BITS : positive;
FRAME_USER_BITS : natural;
REGISTER_PATH : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
-- in port
sof_in : in std_logic;
data_in : in std_logic_vector(D_BITS downto 1);
frame_data_in : in std_logic_vector(imax(1, FRAME_USER_BITS) downto 1);
eof_in : in std_logic;
src_rdy_in : in std_logic;
dst_rdy_in : out std_logic;
-- out port
sof_out : out std_logic;
data_out : out std_logic_vector(D_BITS downto 1);
frame_data_out : out std_logic_vector(imax(1, FRAME_USER_BITS) downto 1);
eof_out : out std_logic;
src_rdy_out : out std_logic;
dst_rdy_out : in std_logic
);
end component;
-- Simple FIFO backed by a shift register.
component fifo_shift
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive -- Minimum FIFO Size in Words
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
ful : out std_logic; -- Capacity Exhausted
-- Reading Interface
got : in std_logic; -- Read Done Strobe
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
vld : out std_logic -- Data Valid
);
end component;
-- Full-fledged FIFO with single clock domain using on-chip RAM.
component fifo_cc_got
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0);
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0)
);
end component;
component fifo_dc_got_sm
generic (
D_BITS : positive;
MIN_DEPTH : positive);
port (
clk_wr : in std_logic;
rst_wr : in std_logic;
put : in std_logic;
din : in std_logic_vector(D_BITS - 1 downto 0);
full : out std_logic;
clk_rd : in std_logic;
rst_rd : in std_logic;
got : in std_logic;
valid : out std_logic;
dout : out std_logic_vector(D_BITS - 1 downto 0));
end component;
component fifo_ic_got
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Write Interface
clk_wr : in std_logic;
rst_wr : in std_logic;
put : in std_logic;
din : in std_logic_vector(D_BITS - 1 downto 0);
full : out std_logic;
estate_wr : out std_logic_vector(imax(ESTATE_WR_BITS - 1, 0) downto 0);
-- Read Interface
clk_rd : in std_logic;
rst_rd : in std_logic;
got : in std_logic;
valid : out std_logic;
dout : out std_logic_vector(D_BITS - 1 downto 0);
fstate_rd : out std_logic_vector(imax(FSTATE_RD_BITS - 1, 0) downto 0)
);
end component;
component fifo_cc_got_tempput
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0);
commit : in std_logic;
rollback : in std_logic;
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0)
);
end component;
component fifo_cc_got_tempgot is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0);
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0);
commit : in std_logic;
rollback : in std_logic
);
end component;
end package;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Steffen Koehler
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: VHDL package for component declarations, types and functions
-- associated to the PoC.fifo namespace
--
-- Description:
-- ------------------------------------
-- For detailed documentation see below.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library poc;
use PoC.utils.all;
package fifo is
-- Minimal FIFO with single clock to decouple enable domains.
component fifo_glue
generic (
D_BITS : positive -- Data Width
);
port (
-- Control
clk : in std_logic; -- Clock
rst : in std_logic; -- Synchronous Reset
-- Input
put : in std_logic; -- Put Value
di : in std_logic_vector(D_BITS - 1 downto 0); -- Data Input
ful : out std_logic; -- Full
-- Output
vld : out std_logic; -- Data Available
do : out std_logic_vector(D_BITS - 1 downto 0); -- Data Output
got : in std_logic -- Data Consumed
);
end component;
-- Minimal Local-Link-FIFO with single clock and first-word-fall-through mode.
component fifo_ll_glue
generic (
D_BITS : positive;
FRAME_USER_BITS : natural;
REGISTER_PATH : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
-- in port
sof_in : in std_logic;
data_in : in std_logic_vector(D_BITS downto 1);
frame_data_in : in std_logic_vector(imax(1, FRAME_USER_BITS) downto 1);
eof_in : in std_logic;
src_rdy_in : in std_logic;
dst_rdy_in : out std_logic;
-- out port
sof_out : out std_logic;
data_out : out std_logic_vector(D_BITS downto 1);
frame_data_out : out std_logic_vector(imax(1, FRAME_USER_BITS) downto 1);
eof_out : out std_logic;
src_rdy_out : out std_logic;
dst_rdy_out : in std_logic
);
end component;
-- Simple FIFO backed by a shift register.
component fifo_shift
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive -- Minimum FIFO Size in Words
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
ful : out std_logic; -- Capacity Exhausted
-- Reading Interface
got : in std_logic; -- Read Done Strobe
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
vld : out std_logic -- Data Valid
);
end component;
-- Full-fledged FIFO with single clock domain using on-chip RAM.
component fifo_cc_got
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0);
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0)
);
end component;
component fifo_dc_got_sm
generic (
D_BITS : positive;
MIN_DEPTH : positive);
port (
clk_wr : in std_logic;
rst_wr : in std_logic;
put : in std_logic;
din : in std_logic_vector(D_BITS - 1 downto 0);
full : out std_logic;
clk_rd : in std_logic;
rst_rd : in std_logic;
got : in std_logic;
valid : out std_logic;
dout : out std_logic_vector(D_BITS - 1 downto 0));
end component;
component fifo_ic_got
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Write Interface
clk_wr : in std_logic;
rst_wr : in std_logic;
put : in std_logic;
din : in std_logic_vector(D_BITS - 1 downto 0);
full : out std_logic;
estate_wr : out std_logic_vector(imax(ESTATE_WR_BITS - 1, 0) downto 0);
-- Read Interface
clk_rd : in std_logic;
rst_rd : in std_logic;
got : in std_logic;
valid : out std_logic;
dout : out std_logic_vector(D_BITS - 1 downto 0);
fstate_rd : out std_logic_vector(imax(FSTATE_RD_BITS - 1, 0) downto 0)
);
end component;
component fifo_cc_got_tempput
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0);
commit : in std_logic;
rollback : in std_logic;
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0)
);
end component;
component fifo_cc_got_tempgot is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive; -- Minimum FIFO Depth
DATA_REG : boolean := false; -- Store Data Content in Registers
STATE_REG : boolean := false; -- Registered Full/Empty Indicators
OUTPUT_REG : boolean := false; -- Registered FIFO Output
ESTATE_WR_BITS : natural := 0; -- Empty State Bits
FSTATE_RD_BITS : natural := 0 -- Full State Bits
);
port (
-- Global Reset and Clock
rst, clk : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS - 1 downto 0); -- Input Data
full : out std_logic;
estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS - 1) downto 0);
-- Reading Interface
got : in std_logic; -- Read Completed
dout : out std_logic_vector(D_BITS - 1 downto 0); -- Output Data
valid : out std_logic;
fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS - 1) downto 0);
commit : in std_logic;
rollback : in std_logic
);
end component;
end package;
|
-----------------------------------------------
-- Module Name: HexDigSSegCntrl - control --
-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.Hex4Digs_2_SSeg_Package.all;
entity HexDigSSegCntrl is
port ( clock : in std_logic;
sws : in std_logic_vector (2 downto 0);
anodes : out std_logic_vector (3 downto 0);
cathodes : out std_logic_vector (7 downto 0));
end HexDigSSegCntrl;
architecture control of HexDigSSegCntrl is
signal cntr : std_logic_vector (3 downto 0);
signal sw0 : std_logic;
signal csws : std_logic_vector (1 downto 0);
signal en : std_logic;
signal clk : std_logic;
constant TC5Hz : integer := 56; -- TC for 5 Hz clock
constant TC16Hz : integer := 42; -- TC for 16 Hz clock
constant TC30Hz : integer := 36; -- TC for 30 Hz clock
constant TC312Hz : integer := 20; -- TC for 312 Hz clock
signal clk5Hz : std_logic := '0'; -- 5Hz clock
signal clk16Hz : std_logic := '0'; -- 16Hz clock
signal clk30Hz : std_logic := '0'; -- 30Hz clock
signal clk312Hz : std_logic := '0'; -- 312Hz clock
signal c0, c1, c2, c3 : integer range 0 to 15;
begin
sw0 <= sws(0);
csws(0) <= sws(1);
csws(1) <= sws(2);
c5Hz: CDiv port map (clock, TC5Hz, clk5Hz);
c16Hz: CDiv port map (clock, TC16Hz, clk16Hz);
c30Hz: CDiv port map (clock, TC30Hz, clk30Hz);
c312Hz: CDiv port map (clock, TC312Hz, clk312Hz);
HexDs: Hex4Digs_2_SSeg port map (clock, clk, sw0, cntr, anodes, cathodes);
process (csws, clk5Hz, clk16Hz, clk30Hz, clk312Hz) -- control clocks
begin
case csws is
when "00" =>
clk <= clk5Hz;
when "01" =>
clk <= clk16Hz;
when "10" =>
clk <= clk30Hz;
when others =>
clk <= clk312Hz;
end case;
end process;
process (clk)
begin
if rising_edge(clk) then
en <= not en;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if en = '1' then
c0 <= c0 + 1;
cntr(0) <= '1';
if (c0 = 15) then
c1 <= c1 + 1;
cntr(1) <= '1';
if (c1 = 15) then
c2 <= c2 + 1;
cntr(2) <= '1';
if (c2 = 15) then
c3 <= c3 + 1;
cntr(3) <= '1';
end if;
end if;
end if;
else
cntr <= "0000";
end if;
end if;
end process;
end control;
|
-------------------------------------------------------------------------------
-- Title : Wishbone Packet Fabric buffered packet sink
-- Project : WR Cores Collection
-------------------------------------------------------------------------------
-- File : xwb_fabric_sink.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-16
-- Last update: 2012-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A simple WB packet streaming sink with builtin FIFO buffer.
-- Outputs a trivial interface (start-of-packet, end-of-packet, data-valid)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-16 1.0 twlostow Created
-------------------------------------------------------------------------------
--
-- Modified by Lucas Russo <[email protected]> for multiple width support
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.wb_stream_generic_pkg.all;
entity xwb_stream_sink_gen is
generic (
--g_wbs_adr_width : natural := c_wbs_adr4_width;
g_wbs_interface_width : t_wbs_interface_width := LARGE1
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O.
-- Only the used interface must be connected. The others can be left unconnected
-- 16-bit interface
snk16_i : in t_wbs_sink_in16 := cc_dummy_snk_in16;
snk16_o : out t_wbs_sink_out16;
-- 32-bit interface
snk32_i : in t_wbs_sink_in32 := cc_dummy_snk_in32;
snk32_o : out t_wbs_sink_out32;
-- 64-bit interface
snk64_i : in t_wbs_sink_in64 := cc_dummy_snk_in64;
snk64_o : out t_wbs_sink_out64;
-- 128-bit interface
snk128_i : in t_wbs_sink_in128 := cc_dummy_snk_in128;
snk128_o : out t_wbs_sink_out128;
-- Decoded & buffered logic
-- Only the used interface must be connected. The others can be left unconnected
-- 16-bit interface
adr16_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat16_o : out std_logic_vector(c_wbs_dat16_width-1 downto 0);
sel16_o : out std_logic_vector(c_wbs_sel16_width-1 downto 0);
-- 32-bit interface
adr32_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat32_o : out std_logic_vector(c_wbs_dat32_width-1 downto 0);
sel32_o : out std_logic_vector(c_wbs_sel32_width-1 downto 0);
-- 64-bit interface
adr64_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat64_o : out std_logic_vector(c_wbs_dat64_width-1 downto 0);
sel64_o : out std_logic_vector(c_wbs_sel64_width-1 downto 0);
-- 128-bit interface
adr128_o : out std_logic_vector(c_wbs_adr4_width-1 downto 0);
dat128_o : out std_logic_vector(c_wbs_dat128_width-1 downto 0);
sel128_o : out std_logic_vector(c_wbs_sel128_width-1 downto 0);
-- Common lines
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
dreq_i : in std_logic := '0'
);
end xwb_stream_sink_gen;
architecture rtl of xwb_stream_sink_gen is
signal snk_cyc_int : std_logic;
signal snk_stb_int : std_logic;
signal snk_we_int : std_logic;
signal snk_ack_int : std_logic;
signal snk_stall_int : std_logic;
signal snk_err_int : std_logic;
signal snk_rty_int : std_logic;
begin
-----------------------------
-- Wishbone Streaming Interface selection
-----------------------------
gen_16_bit_interface : if g_wbs_interface_width = NARROW2 generate
snk_cyc_int <= snk16_i.cyc;
snk_stb_int <= snk16_i.stb;
snk_we_int <= snk16_i.we;
snk16_o.ack <= snk_ack_int;
snk16_o.stall <= snk_stall_int;
snk16_o.err <= snk_err_int;
snk16_o.rty <= snk_rty_int;
end generate;
gen_32_bit_interface : if g_wbs_interface_width = NARROW1 generate
snk_cyc_int <= snk32_i.cyc;
snk_stb_int <= snk32_i.stb;
snk_we_int <= snk32_i.we;
snk32_o.ack <= snk_ack_int;
snk32_o.stall <= snk_stall_int;
snk32_o.err <= snk_err_int;
snk32_o.rty <= snk_rty_int;
end generate;
gen_64_bit_interface : if g_wbs_interface_width = LARGE1 generate
snk_cyc_int <= snk64_i.cyc;
snk_stb_int <= snk64_i.stb;
snk_we_int <= snk64_i.we;
snk64_o.ack <= snk_ack_int;
snk64_o.stall <= snk_stall_int;
snk64_o.err <= snk_err_int;
snk64_o.rty <= snk_rty_int;
end generate;
gen_128_bit_interface : if g_wbs_interface_width = LARGE2 generate
snk_cyc_int <= snk128_i.cyc;
snk_stb_int <= snk128_i.stb;
snk_we_int <= snk128_i.we;
snk128_o.ack <= snk_ack_int;
snk128_o.stall <= snk_stall_int;
snk128_o.err <= snk_err_int;
snk128_o.rty <= snk_rty_int;
end generate;
cmp_wb_stream_sink_gen : wb_stream_sink_gen
generic map (
--g_wbs_adr_width : natural := c_wbs_adr4_width;
g_wbs_interface_width => g_wbs_interface_width
)
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
-- Wishbone Streaming Interface I/O.
-- Only the used interface should be connected. The others can be left unconnected
-- 16-bit interface
snk_adr16_i => snk16_i.adr,
snk_dat16_i => snk16_i.dat,
snk_sel16_i => snk16_i.sel,
-- 32-bit interface
snk_adr32_i => snk32_i.adr,
snk_dat32_i => snk32_i.dat,
snk_sel32_i => snk32_i.sel,
-- 64-bit interface
snk_adr64_i => snk64_i.adr,
snk_dat64_i => snk64_i.dat,
snk_sel64_i => snk64_i.sel,
-- 128-bit interface
snk_adr128_i => snk128_i.adr,
snk_dat128_i => snk128_i.dat,
snk_sel128_i => snk128_i.sel,
-- Common Wishbone Streaming lines
snk_cyc_i => snk_cyc_int,
snk_stb_i => snk_stb_int,
snk_we_i => snk_we_int,
snk_ack_o => snk_ack_int,
snk_stall_o => snk_stall_int,
snk_err_o => snk_err_int,
snk_rty_o => snk_rty_int,
-- Decoded & buffered logic
-- Only the used interface must be connected. The others can be left unconnected
-- 16-bit interface
adr16_o => adr16_o,
dat16_o => dat16_o,
sel16_o => sel16_o,
-- 32-bit interface ,
adr32_o => adr32_o,
dat32_o => dat32_o,
sel32_o => sel32_o,
-- 64-bit interface ,
adr64_o => adr64_o,
dat64_o => dat64_o,
sel64_o => sel64_o,
-- 128-bit interface
adr128_o => adr128_o,
dat128_o => dat128_o,
sel128_o => sel128_o,
-- Common lines
dvalid_o => dvalid_o,
sof_o => sof_o,
eof_o => eof_o,
error_o => error_o,
dreq_i => dreq_i
);
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbmst
-- File: ahbmst.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Generic AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbmst is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in ahb_dma_in_type;
dmao : out ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture rtl of ahbmst is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, 0),
others => zero32);
type reg_type is record
start : std_ulogic;
retry : std_ulogic;
grant : std_ulogic;
active : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type := ('0', '0', '0', '0');
signal r, rin : reg_type;
begin
comb : process(ahbi, dmai, rst, r)
variable v : reg_type;
variable ready : std_ulogic;
variable retry : std_ulogic;
variable mexc : std_ulogic;
variable inc : std_logic_vector(5 downto 0); -- address increment
variable haddr : std_logic_vector(31 downto 0); -- AHB address
variable hwdata : std_logic_vector(AHBDW-1 downto 0); -- AHB write data
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable newaddr : std_logic_vector(9 downto 0); -- next sequential address
variable hbusreq : std_ulogic; -- bus request
variable hprot : std_logic_vector(3 downto 0); -- transfer type
variable xhirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; ready := '0'; mexc := '0'; retry := '0'; inc := (others => '0');
hprot := conv_std_logic_vector(chprot, 4); -- non-cached supervisor data
xhirq := (others => '0'); xhirq(hirq) := dmai.irq;
haddr := dmai.address; hbusreq := dmai.start;
hwdata := dmai.wdata;
newaddr := dmai.address(9 downto 0);
if INCADDR > 0 then
inc(conv_integer(dmai.size)) := '1';
newaddr := haddr(9 downto 0) + inc;
end if;
if dmai.burst = '0' then hburst := HBURST_SINGLE;
else hburst := HBURST_INCR; end if;
if dmai.start = '1' then
if (r.active and dmai.burst and not r.retry) = '1' then
haddr(9 downto 0) := newaddr;
if dmai.busy = '1' then htrans := HTRANS_BUSY;
else htrans := HTRANS_SEQ; end if;
hburst := HBURST_INCR;
else htrans := HTRANS_NONSEQ; end if;
else htrans := HTRANS_IDLE; end if;
if r.active = '1' then
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => ready := '1';
when HRESP_RETRY | HRESP_SPLIT=> retry := '1';
when others => ready := '1'; mexc := '1';
end case;
end if;
if ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT)) then
v.retry := not ahbi.hready;
else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
v.start := '0';
if ahbi.hready = '1' then
v.grant := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) or (htrans = HTRANS_BUSY) then
v.active := r.grant; v.start := r.grant;
else
v.active := '0';
end if;
end if;
if (not RESET_ALL) and (rst = '0') then
v.retry := RES.retry; v.active := RES.active;
end if;
rin <= v;
ahbo.haddr <= haddr;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq;
ahbo.hwdata <= hwdata;
ahbo.hconfig <= hconfig;
ahbo.hlock <= '0';
ahbo.hwrite <= dmai.write;
ahbo.hsize <= dmai.size;
ahbo.hburst <= hburst;
ahbo.hprot <= hprot;
ahbo.hirq <= xhirq;
ahbo.hindex <= hindex;
dmao.start <= r.start;
dmao.active <= r.active;
dmao.ready <= ready;
dmao.mexc <= mexc;
dmao.retry <= retry;
dmao.haddr <= newaddr;
dmao.rdata <= ahbi.hrdata;
end process;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean;
function is_illegal(inst: std_logic_vector(7 downto 0)) return boolean;
function do_bypass_shift(inst : std_logic_vector(7 downto 0)) return std_logic;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector;
constant c_stack_idx_brk : std_logic_vector(1 downto 0) := "00";
constant c_stack_idx_jsr : std_logic_vector(1 downto 0) := "01";
constant c_stack_idx_rti : std_logic_vector(1 downto 0) := "10";
constant c_stack_idx_rts : std_logic_vector(1 downto 0) := "11";
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean;
-- function load_a (inst: std_logic_vector(7 downto 0)) return boolean;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean;
function affect_registers(inst: std_logic_vector(7 downto 0)) return boolean;
type t_result_select is (alu, shift, impl, row0, none);
function flags_from(inst : std_logic_vector(7 downto 0)) return t_result_select;
end;
package body pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X11X | 1101
if inst(3 downto 2)="11" then
return true;
elsif inst(4 downto 2)="110" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(7 downto 6)="01" and inst(3 downto 0)=X"C" and inst(4) = '0';
end function;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210 = 1XX000X0
if inst(7)='1' and inst(4 downto 2)="000" and inst(0)='0' then
return true;
-- 76543210 = XXX010X1
elsif inst(4 downto 2)="010" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X100
return inst(3 downto 0)=X"8" or inst(3 downto 0)=X"A";
end function;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210
-- 0xx0x000 => 00, 08, 20, 28, 40, 48, 60, 68
-- BRK,PHP,JSR,PLP,RTI,PHA,RTS,PLA
return inst(7)='0' and inst(4)='0' and inst(2 downto 0)="000";
end function;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- we already know it's a stack operation, so only the direction is important
return inst(5)='0';
end function;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(3 downto 2)="01" then
return true;
elsif inst(3 downto 2)="00" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(3 downto 2)="00" and inst(0)='1');
end function;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(4 downto 0)="10000");
end function;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(7 downto 5)="100" then
if inst(2) = '1' or inst(0) = '1' then
return true;
end if;
end if;
return false;
end function;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 0--0101-
return (inst(7)='0' and inst(4 downto 1) = "0101");
-- -- 16, 1e
-- -- 1--0 10-- => 8[89AB], A[89AB], C[89AB], E[89AB]
-- if inst(7)='1' and inst(4 downto 2)="010" then
-- return false;
-- end if;
-- return (inst(1)='1');
end function;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- if inst(7)='0' and inst(4 downto 1)="0101" then
-- return false;
-- end if;
return (inst(0)='1');
end function;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return not is_store(inst) and not is_rmw(inst);
end function;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(1)='1' and inst(7 downto 6)/="10";
end function;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return is_jump(inst) and inst(5)='0';
end function;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(4)='1';
end function;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
return inst(6 downto 5);
end function;
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(4)='1' and inst(2)='0' and inst(0)='1' then -- XXX1X0X1
return true;
elsif inst(7 downto 6)="10" and inst(2 downto 1)="11" then -- 10XXX11X
return true;
end if;
return false;
end function;
function load_a (inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst = X"68");
end function;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 0XXXXXX1 or alu operations "lo"
-- 1X100001 or alu operations "hi" (except store and cmp)
-- 0XX01010 (implied) (shift select by 'is_shift'!)
return (inst(7)='0' and inst(4 downto 0)="01010") or
(inst(7)='0' and inst(0)='1') or
(inst(7)='1' and inst(0)='1' and inst(5)='1');
end function;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX1X or 1100101- (for SAX #)
if inst(7 downto 1)="1100101" then
return true;
end if;
return inst(7 downto 5)="101" and inst(1)='1' and not is_implied(inst);
end function;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX00
return inst(7 downto 5)="101" and inst(1 downto 0)="00" and not is_implied(inst) and not is_relative(inst);
end function;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
-- 00 = none, 01 = memory, 10 = A, 11 = A & M
if inst = X"AB" then -- LAX #$
return "00"; -- special case
elsif inst(4 downto 1)="0101" and inst(7)='0' then -- 0xx0101x: 0A, 0B, 2A, 2B, 4A, 4B, 6A, 6B
return inst(1 downto 0); -- 10 or 11
end if;
return "01";
end function;
function is_illegal (inst: std_logic_vector(7 downto 0)) return boolean is
type t_my16bit_array is array(natural range <>) of std_logic_vector(15 downto 0);
constant c_illegal_map : t_my16bit_array(0 to 15) := (
X"989C", X"9C9C", X"888C", X"9C9C", X"889C", X"9C9C", X"889C", X"9C9C",
X"8A8D", X"D88C", X"8888", X"888C", X"888C", X"9C9C", X"888C", X"9C9C" );
variable row : std_logic_vector(15 downto 0);
begin
row := c_illegal_map(to_integer(unsigned(inst(7 downto 4))));
return (row(to_integer(unsigned(inst(3 downto 0)))) = '1');
end function;
function flags_from(inst : std_logic_vector(7 downto 0)) return t_result_select is
begin
-- special case for ANC/ALR
if inst = X"0B" or inst = X"2B" or inst = X"4B" then
return shift;
-- special case for LAS (value and flags are calculated in implied handler)
elsif inst = X"BB" then
return impl;
-- special case for ANE (value and flags are calculated in implied handler, using set A)
elsif inst = X"8B" then
return impl;
elsif is_store(inst) then
return none;
elsif inst(0) = '1' then
return alu;
elsif is_shift(inst) then
return shift;
elsif (inst(3 downto 0) = X"0" or inst(3 downto 0) = X"4" or inst(3 downto 0) = X"C") and inst(4)='0' then
return row0;
elsif is_implied(inst) then
return impl;
elsif inst(7 downto 5) = "101" then -- load
return shift;
end if;
return none;
end function;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 1-00101- 8A,8B,CA,CB
return inst(5 downto 1)="00101" and inst(7)='1';
end function;
function affect_registers(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if is_implied(inst) then
return true;
end if;
if (inst(7)='0' or inst(6)='1') and inst(2 downto 0) = "110" then
return false;
end if;
-- 7 downto 5 = 000 001 010 011 110 111
-- 2 downto 0 = 110
-- should not be true for 06 26 46 66 C6 E6
-- should not be true for 16 36 56 76 D6 F6
-- should not be true for 0E 2E 4E 6E CE EE
-- should not be true for 1E 3E 5E 7E DE FE
if is_stack(inst) or is_relative(inst) then
return false;
end if;
return true;
end function;
function do_bypass_shift(inst : std_logic_vector(7 downto 0)) return std_logic is
begin
-- may be optimized
if inst = X"0B" or inst = X"2B" then
return '1';
end if;
return '0';
end function;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo is
generic (
type T;
DEPTH : positive );
port (
clk : in std_logic;
pop : in std_logic;
push : in std_logic;
full : out std_logic;
valid : out std_logic;
din : in T;
dout : out T );
end entity;
architecture test of fifo is
type fifo_data_t is array (0 to DEPTH - 1) of T;
signal wptr, rptr : natural := 1;
signal data : fifo_data_t;
begin
full <= '1' when (wptr + 1) mod DEPTH = rptr else '0';
valid <= '1' when wptr /= rptr else '0';
dout <= data(rptr);
behav: process (clk) is
begin
if rising_edge(clk) then
if push = '1' then
assert full = '0';
data(wptr) <= din;
wptr <= (wptr + 1) mod DEPTH;
end if;
if pop = '1' then
assert valid = '1';
rptr <= (rptr + 1) mod DEPTH;
end if;
end if;
end process;
end architecture;
-------------------------------------------------------------------------------
entity gentype1 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of gentype1 is
signal clk : std_logic;
signal pop : std_logic;
signal push : std_logic;
signal din : integer;
signal dout : integer;
signal full : std_logic;
signal valid : std_logic;
procedure pulse (signal clk : out std_logic) is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
end procedure;
begin
u: entity work.fifo
generic map ( T => integer, depth => 4 )
port map (
clk => clk,
pop => pop,
push => push,
din => din,
dout => dout,
full => full,
valid => valid );
main: process is
begin
wait for 1 ns;
assert full = '0';
assert valid = '0';
din <= 5;
push <= '1';
pulse(clk);
assert full = '0';
assert valid = '1';
assert dout = 5;
din <= 7;
pulse(clk);
assert full = '0';
assert valid = '1';
assert dout = 5;
push <= '0';
pop <= '1';
pulse(clk);
assert full = '0';
assert valid = '1';
assert dout = 7;
pulse(clk);
assert full = '0';
assert valid = '0';
wait;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_4_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_4_e-e.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_4_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_4_e
--
entity inst_4_e is
-- Generics:
-- No Generated Generics for Entity inst_4_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_4_e
end inst_4_e;
--
-- End of Generated Entity inst_4_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- axi_sg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
-- Description: This entity is the top level entity for the AXI Scatter Gather
-- Engine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_1_11.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/1/10 v1_00_a
-- ^^^^^^
-- CR567661
-- Remapped interrupt threshold control to be driven based on whether update
-- engine is included or not.
-- ~~~~~~
-- GAB 7/27/10 v1_00_a
-- ^^^^^^
-- CR569609
-- Remove double driven signal for exclude update engine mode
-- ~~~~~~
-- GAB 8/12/10 v1_00_a
-- ^^^^^^
-- CR572013
-- Added ability to disable threshold count reset on delay timer timeout in
-- order to match legacy SDMA operation.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- Added ch1_aclk and ch2_aclk to allow for asynchronous operation
-- Added C_ACLK_IS_ASYNC parameter to set mode of clock synchronization
-- ~~~~~~
-- GAB 10/21/10 v2_01_a
-- ^^^^^^
-- Rolled version to v2_01_a
-- Updated to axi_datamover_v3_00_a
-- Updated tstrb ports to tkeep ports
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- Updated AXI Datamover to incorperate new ports and ***_TDATA_WIDTH parameters
-- ~~~~~~
-- GAB 2/2/11 v2_02_a
-- ^^^^^^
-- Update to AXI Datamover v2_01_a
-- ~~~~~~
-- GAB 6/13/11 v3_00_a
-- ^^^^^^
-- Update to AXI Datamover v3_00_a
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream out for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_DESC_UPDATE : integer range 0 to 1 := 1;
-- Include or Exclude Scatter Gather Descriptor Update
-- 0 = Exclude Descriptor Update
-- 1 = Include Descriptor Update
C_INCLUDE_INTRPT : integer range 0 to 1 := 1;
-- Include/Exclude interrupt logic coalescing
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
dm_resetn : in std_logic ; --
--
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_bvalid : in std_logic ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rlast : in std_logic ; --
m_axi_sg_rvalid : in std_logic ; --
m_axi_sg_rready : out std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
--
--
-- Channel 1 Interrupt Coalescing Signals --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ; --
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
--
--
-- Channel 1 AXI Update Stream In --
s_axis_ch1_updt_aclk : in std_logic ; --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
--
-- Channel 2 Interrupt Coalescing Signals --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
--
-- Channel 2 AXI Update Stream In --
s_axis_ch2_updt_aclk : in std_logic ; --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
--
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--
-- Error addresses --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant AXI_LITE_MODE : integer := 2; -- DataMover Lite Mode
constant EXCLUDE : integer := 0; -- Define Exclude as 0
constant NEVER_HALT : std_logic := '0'; -- Never halt sg datamover
-- Always include descriptor fetch (use lite datamover)
constant INCLUDE_DESC_FETCH : integer := AXI_LITE_MODE;
-- Selectable include descriptor update (use lite datamover)
constant INCLUDE_DESC_UPDATE : integer := AXI_LITE_MODE * C_INCLUDE_DESC_UPDATE;
-- Always allow address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- If async mode and number of descriptors to fetch is zero then set number
-- of descriptors to fetch as 1.
constant SG_FTCH_DESC2QUEUE : integer := max2(C_SG_FTCH_DESC2QUEUE,C_AXIS_IS_ASYNC);
constant SG_UPDT_DESC2QUEUE : integer := max2(C_SG_UPDT_DESC2QUEUE,C_AXIS_IS_ASYNC);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- DataMover MM2S Fetch Command Stream Signals
signal s_axis_ftch_cmd_tvalid : std_logic := '0';
signal s_axis_ftch_cmd_tready : std_logic := '0';
signal s_axis_ftch_cmd_tdata : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover MM2S Fetch Status Stream Signals
signal m_axis_ftch_sts_tvalid : std_logic := '0';
signal m_axis_ftch_sts_tready : std_logic := '0';
signal m_axis_ftch_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_ftch_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
-- DataMover MM2S Fetch Stream Signals
signal m_axis_mm2s_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_tkeep : std_logic_vector
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_mm2s_tlast : std_logic := '0';
signal m_axis_mm2s_tvalid : std_logic := '0';
signal m_axis_mm2s_tready : std_logic := '0';
-- DataMover S2MM Update Command Stream Signals
signal s_axis_updt_cmd_tvalid : std_logic := '0';
signal s_axis_updt_cmd_tready : std_logic := '0';
signal s_axis_updt_cmd_tdata : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover S2MM Update Status Stream Signals
signal m_axis_updt_sts_tvalid : std_logic := '0';
signal m_axis_updt_sts_tready : std_logic := '0';
signal m_axis_updt_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_updt_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
-- DataMover S2MM Update Stream Signals
signal s_axis_s2mm_tdata : std_logic_vector
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_tkeep : std_logic_vector
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0) := (others => '1');
signal s_axis_s2mm_tlast : std_logic := '0';
signal s_axis_s2mm_tvalid : std_logic := '0';
signal s_axis_s2mm_tready : std_logic := '0';
-- Channel 1 internals
signal ch1_ftch_active : std_logic := '0';
signal ch1_ftch_queue_empty : std_logic := '0';
signal ch1_ftch_queue_full : std_logic := '0';
signal ch1_nxtdesc_wren : std_logic := '0';
signal ch1_updt_active : std_logic := '0';
signal ch1_updt_queue_empty : std_logic := '0';
signal ch1_updt_curdesc_wren : std_logic := '0';
signal ch1_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_updt_ioc : std_logic := '0';
signal ch1_updt_ioc_irq_set_i : std_logic := '0';
signal ch1_dma_interr : std_logic := '0';
signal ch1_dma_slverr : std_logic := '0';
signal ch1_dma_decerr : std_logic := '0';
signal ch1_dma_interr_set_i : std_logic := '0';
signal ch1_dma_slverr_set_i : std_logic := '0';
signal ch1_dma_decerr_set_i : std_logic := '0';
signal ch1_updt_done : std_logic := '0';
signal ch1_ftch_pause : std_logic := '0';
-- Channel 2 internals
signal ch2_ftch_active : std_logic := '0';
signal ch2_ftch_queue_empty : std_logic := '0';
signal ch2_ftch_queue_full : std_logic := '0';
signal ch2_nxtdesc_wren : std_logic := '0';
signal ch2_updt_active : std_logic := '0';
signal ch2_updt_queue_empty : std_logic := '0';
signal ch2_updt_curdesc_wren : std_logic := '0';
signal ch2_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch2_updt_ioc : std_logic := '0';
signal ch2_updt_ioc_irq_set_i : std_logic := '0';
signal ch2_dma_interr : std_logic := '0';
signal ch2_dma_slverr : std_logic := '0';
signal ch2_dma_decerr : std_logic := '0';
signal ch2_dma_interr_set_i : std_logic := '0';
signal ch2_dma_slverr_set_i : std_logic := '0';
signal ch2_dma_decerr_set_i : std_logic := '0';
signal ch2_updt_done : std_logic := '0';
signal ch2_ftch_pause : std_logic := '0';
signal nxtdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ftch_cmnd_wr : std_logic := '0';
signal ftch_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
signal ftch_stale_desc : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal ch1_irqthresh_decr : std_logic := '0'; --CR567661
signal ch2_irqthresh_decr : std_logic := '0'; --CR567661
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
ftch_error <= ftch_error_i;
-- Always valid therefore fix to '1'
s_axis_s2mm_tkeep <= (others => '1');
-- Drive interrupt on complete set out
--ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i; -- CR567661
--ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i; -- CR567661
ch1_dma_interr_set <= ch1_dma_interr_set_i;
ch1_dma_slverr_set <= ch1_dma_slverr_set_i;
ch1_dma_decerr_set <= ch1_dma_decerr_set_i;
ch2_dma_interr_set <= ch2_dma_interr_set_i;
ch2_dma_slverr_set <= ch2_dma_slverr_set_i;
ch2_dma_decerr_set <= ch2_dma_decerr_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Manager
-------------------------------------------------------------------------------
I_SG_FETCH_MNGR : entity axi_vdma_v6_2_8.axi_sg_ftch_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,
ch1_updt_done => ch1_updt_done ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_curdesc => ch1_curdesc ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,
ch2_updt_done => ch2_updt_done ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_curdesc => ch2_curdesc ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
mm2s_err => mm2s_err ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
updt_error => updt_error_i ,
ftch_error => ftch_error_i ,
ftch_error_addr => ftch_error_addr
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Queue
-------------------------------------------------------------------------------
I_SG_FETCH_QUEUE : entity axi_vdma_v6_2_8.axi_sg_ftch_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_desc_flush => ch1_desc_flush ,
ch1_ftch_active => ch1_ftch_active ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control
ch2_ftch_active => ch2_ftch_active ,
ch2_desc_flush => ch2_desc_flush ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => m_axis_ch1_ftch_aclk ,
m_axis_ch1_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_ch1_ftch_tlast ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => m_axis_ch2_ftch_aclk ,
m_axis_ch2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_ch2_ftch_tlast
);
-- Include Scatter Gather Descriptor Update logic
GEN_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 1 generate
begin
-- CR567661
-- Route update version of IOC set to threshold
-- counter decrement control
ch1_irqthresh_decr <= ch1_updt_ioc_irq_set_i;
ch2_irqthresh_decr <= ch2_updt_ioc_irq_set_i;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i;
ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Update Manager
-------------------------------------------------------------------------------
I_SG_UPDATE_MNGR : entity axi_vdma_v6_2_8.axi_sg_updt_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
ch1_updt_interr_set => ch1_updt_interr_set ,
ch1_updt_slverr_set => ch1_updt_slverr_set ,
ch1_updt_decerr_set => ch1_updt_decerr_set ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
ch2_updt_interr_set => ch2_updt_interr_set ,
ch2_updt_slverr_set => ch2_updt_slverr_set ,
ch2_updt_decerr_set => ch2_updt_decerr_set ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
s2mm_err => s2mm_err ,
ftch_error => ftch_error_i ,
updt_error => updt_error_i ,
updt_error_addr => updt_error_addr
);
-------------------------------------------------------------------------------
-- Scatter Gather Update Queue
-------------------------------------------------------------------------------
I_SG_UPDATE_QUEUE : entity axi_vdma_v6_2_8.axi_sg_updt_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Channel 1 Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
-- Channel 2 Control
ch2_updt_active => ch2_updt_active ,
ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
-- Channel 2 Update Descriptor Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
-- S2MM Stream Out To DataMover
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => s_axis_ch1_updt_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => s_axis_ch2_updt_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis_ch2_updtsts_tlast => s_axis_ch2_updtsts_tlast
);
end generate GEN_DESC_UPDATE;
-- Exclude Scatter Gather Descriptor Update logic
GEN_NO_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 0 generate
begin
ch1_updt_idle <= '1';
ch1_updt_active <= '0';
-- ch1_updt_ioc_irq_set <= '0';--CR#569609
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set_i <= '0';
ch1_dma_slverr_set_i <= '0';
ch1_dma_decerr_set_i <= '0';
ch1_updt_done <= '1'; -- Always done
ch2_updt_idle <= '1';
ch2_updt_active <= '0';
-- ch2_updt_ioc_irq_set <= '0'; --CR#569609
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set_i <= '0';
ch2_dma_slverr_set_i <= '0';
ch2_dma_decerr_set_i <= '0';
ch2_updt_done <= '1'; -- Always done
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
m_axis_updt_sts_tready <= '0';
updt_error_i <= '0';
updt_error_addr <= (others => '0');
ch1_updt_curdesc_wren <= '0';
ch1_updt_curdesc <= (others => '0');
ch1_updt_queue_empty <= '0';
ch1_updt_ioc <= '0';
ch1_dma_interr <= '0';
ch1_dma_slverr <= '0';
ch1_dma_decerr <= '0';
ch2_updt_curdesc_wren <= '0';
ch2_updt_curdesc <= (others => '0');
ch2_updt_queue_empty <= '0';
ch2_updt_ioc <= '0';
ch2_dma_interr <= '0';
ch2_dma_slverr <= '0';
ch2_dma_decerr <= '0';
s_axis_s2mm_tdata <= (others => '0');
s_axis_s2mm_tlast <= '0';
s_axis_s2mm_tvalid <= '0';
s_axis_ch1_updtptr_tready <= '0';
s_axis_ch2_updtptr_tready <= '0';
s_axis_ch1_updtsts_tready <= '0';
s_axis_ch2_updtsts_tready <= '0';
-- CR567661
-- Route packet eof to threshold counter decrement control
ch1_irqthresh_decr <= ch1_packet_eof;
ch2_irqthresh_decr <= ch2_packet_eof;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_packet_eof;
ch2_updt_ioc_irq_set <= ch2_packet_eof;
end generate GEN_NO_DESC_UPDATE;
-------------------------------------------------------------------------------
-- Scatter Gather Interrupt Coalescing
-------------------------------------------------------------------------------
GEN_INTERRUPT_LOGIC : if C_INCLUDE_INTRPT = 1 generate
begin
I_AXI_SG_INTRPT : entity axi_vdma_v6_2_8.axi_sg_intrpt
generic map(
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_INCLUDE_DLYTMR => C_INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ch1_irqthresh_decr => ch1_irqthresh_decr , -- CR567661
ch1_irqthresh_rstdsbl => ch1_irqthresh_rstdsbl , -- CR572013
ch1_dlyirq_dsble => ch1_dlyirq_dsble ,
ch1_irqdelay_wren => ch1_irqdelay_wren ,
ch1_irqdelay => ch1_irqdelay ,
ch1_irqthresh_wren => ch1_irqthresh_wren ,
ch1_irqthresh => ch1_irqthresh ,
ch1_packet_sof => ch1_packet_sof ,
ch1_packet_eof => ch1_packet_eof ,
ch1_ioc_irq_set => ch1_ioc_irq_set ,
ch1_dly_irq_set => ch1_dly_irq_set ,
ch1_irqdelay_status => ch1_irqdelay_status ,
ch1_irqthresh_status => ch1_irqthresh_status ,
ch2_irqthresh_decr => ch2_irqthresh_decr , -- CR567661
ch2_irqthresh_rstdsbl => ch2_irqthresh_rstdsbl , -- CR572013
ch2_dlyirq_dsble => ch2_dlyirq_dsble ,
ch2_irqdelay_wren => ch2_irqdelay_wren ,
ch2_irqdelay => ch2_irqdelay ,
ch2_irqthresh_wren => ch2_irqthresh_wren ,
ch2_irqthresh => ch2_irqthresh ,
ch2_packet_sof => ch2_packet_sof ,
ch2_packet_eof => ch2_packet_eof ,
ch2_ioc_irq_set => ch2_ioc_irq_set ,
ch2_dly_irq_set => ch2_dly_irq_set ,
ch2_irqdelay_status => ch2_irqdelay_status ,
ch2_irqthresh_status => ch2_irqthresh_status
);
end generate GEN_INTERRUPT_LOGIC;
GEN_NO_INTRPT_LOGIC : if C_INCLUDE_INTRPT = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_NO_INTRPT_LOGIC;
-------------------------------------------------------------------------------
-- Scatter Gather DataMover Lite
-------------------------------------------------------------------------------
I_SG_AXI_DATAMOVER : entity axi_datamover_v5_1_11.axi_datamover
generic map(
C_INCLUDE_MM2S => INCLUDE_DESC_FETCH, -- Lite
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_MM2S_STSFIFO => 0, -- Exclude
C_MM2S_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_MM2S_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_MM2S_DRE => 0, -- No DRE
C_MM2S_BURST_SIZE => 16, -- Set to Min
C_MM2S_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_MM2S_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_INCLUDE_S2MM => INCLUDE_DESC_UPDATE, -- Lite
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_S_AXIS_S2MM_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_S2MM_STSFIFO => 0, -- Exclude
C_S2MM_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_S2MM_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_S2MM_DRE => 0, -- No DRE
C_S2MM_BURST_SIZE => 16, -- Set to Min;
C_S2MM_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_S2MM_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aresetn => dm_resetn ,
mm2s_halt => NEVER_HALT ,
mm2s_halt_cmplt => open ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => m_axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_ftch_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Datamover v4_032_a addional signals not needed for SG
--sg_ctl => (others => '0') ,
m_axi_mm2s_aruser => open ,
m_axi_s2mm_awuser => open ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_sg_araddr ,
m_axi_mm2s_arlen => m_axi_sg_arlen ,
m_axi_mm2s_arsize => m_axi_sg_arsize ,
m_axi_mm2s_arburst => m_axi_sg_arburst ,
m_axi_mm2s_arprot => m_axi_sg_arprot ,
m_axi_mm2s_arcache => m_axi_sg_arcache ,
m_axi_mm2s_arvalid => m_axi_sg_arvalid ,
m_axi_mm2s_arready => m_axi_sg_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_sg_rdata ,
m_axi_mm2s_rresp => m_axi_sg_rresp ,
m_axi_mm2s_rlast => m_axi_sg_rlast ,
m_axi_mm2s_rvalid => m_axi_sg_rvalid ,
m_axi_mm2s_rready => m_axi_sg_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_sg_aclk ,
m_axi_s2mm_aresetn => dm_resetn ,
s2mm_halt => NEVER_HALT ,
s2mm_halt_cmplt => open ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => m_axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_updt_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_updt_sts_tkeep ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_sg_awaddr ,
m_axi_s2mm_awlen => m_axi_sg_awlen ,
m_axi_s2mm_awsize => m_axi_sg_awsize ,
m_axi_s2mm_awburst => m_axi_sg_awburst ,
m_axi_s2mm_awprot => m_axi_sg_awprot ,
m_axi_s2mm_awcache => m_axi_sg_awcache ,
m_axi_s2mm_awvalid => m_axi_sg_awvalid ,
m_axi_s2mm_awready => m_axi_sg_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_sg_wdata ,
m_axi_s2mm_wstrb => m_axi_sg_wstrb ,
m_axi_s2mm_wlast => m_axi_sg_wlast ,
m_axi_s2mm_wvalid => m_axi_sg_wvalid ,
m_axi_s2mm_wready => m_axi_sg_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_sg_bresp ,
m_axi_s2mm_bvalid => m_axi_sg_bvalid ,
m_axi_s2mm_bready => m_axi_sg_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
-- Description: This entity is the top level entity for the AXI Scatter Gather
-- Engine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_1_11.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/1/10 v1_00_a
-- ^^^^^^
-- CR567661
-- Remapped interrupt threshold control to be driven based on whether update
-- engine is included or not.
-- ~~~~~~
-- GAB 7/27/10 v1_00_a
-- ^^^^^^
-- CR569609
-- Remove double driven signal for exclude update engine mode
-- ~~~~~~
-- GAB 8/12/10 v1_00_a
-- ^^^^^^
-- CR572013
-- Added ability to disable threshold count reset on delay timer timeout in
-- order to match legacy SDMA operation.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- Added ch1_aclk and ch2_aclk to allow for asynchronous operation
-- Added C_ACLK_IS_ASYNC parameter to set mode of clock synchronization
-- ~~~~~~
-- GAB 10/21/10 v2_01_a
-- ^^^^^^
-- Rolled version to v2_01_a
-- Updated to axi_datamover_v3_00_a
-- Updated tstrb ports to tkeep ports
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- Updated AXI Datamover to incorperate new ports and ***_TDATA_WIDTH parameters
-- ~~~~~~
-- GAB 2/2/11 v2_02_a
-- ^^^^^^
-- Update to AXI Datamover v2_01_a
-- ~~~~~~
-- GAB 6/13/11 v3_00_a
-- ^^^^^^
-- Update to AXI Datamover v3_00_a
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream out for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_DESC_UPDATE : integer range 0 to 1 := 1;
-- Include or Exclude Scatter Gather Descriptor Update
-- 0 = Exclude Descriptor Update
-- 1 = Include Descriptor Update
C_INCLUDE_INTRPT : integer range 0 to 1 := 1;
-- Include/Exclude interrupt logic coalescing
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
dm_resetn : in std_logic ; --
--
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_bvalid : in std_logic ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rlast : in std_logic ; --
m_axi_sg_rvalid : in std_logic ; --
m_axi_sg_rready : out std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
--
--
-- Channel 1 Interrupt Coalescing Signals --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ; --
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
--
--
-- Channel 1 AXI Update Stream In --
s_axis_ch1_updt_aclk : in std_logic ; --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
--
-- Channel 2 Interrupt Coalescing Signals --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
--
-- Channel 2 AXI Update Stream In --
s_axis_ch2_updt_aclk : in std_logic ; --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
--
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--
-- Error addresses --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant AXI_LITE_MODE : integer := 2; -- DataMover Lite Mode
constant EXCLUDE : integer := 0; -- Define Exclude as 0
constant NEVER_HALT : std_logic := '0'; -- Never halt sg datamover
-- Always include descriptor fetch (use lite datamover)
constant INCLUDE_DESC_FETCH : integer := AXI_LITE_MODE;
-- Selectable include descriptor update (use lite datamover)
constant INCLUDE_DESC_UPDATE : integer := AXI_LITE_MODE * C_INCLUDE_DESC_UPDATE;
-- Always allow address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- If async mode and number of descriptors to fetch is zero then set number
-- of descriptors to fetch as 1.
constant SG_FTCH_DESC2QUEUE : integer := max2(C_SG_FTCH_DESC2QUEUE,C_AXIS_IS_ASYNC);
constant SG_UPDT_DESC2QUEUE : integer := max2(C_SG_UPDT_DESC2QUEUE,C_AXIS_IS_ASYNC);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- DataMover MM2S Fetch Command Stream Signals
signal s_axis_ftch_cmd_tvalid : std_logic := '0';
signal s_axis_ftch_cmd_tready : std_logic := '0';
signal s_axis_ftch_cmd_tdata : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover MM2S Fetch Status Stream Signals
signal m_axis_ftch_sts_tvalid : std_logic := '0';
signal m_axis_ftch_sts_tready : std_logic := '0';
signal m_axis_ftch_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_ftch_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
-- DataMover MM2S Fetch Stream Signals
signal m_axis_mm2s_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_tkeep : std_logic_vector
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_mm2s_tlast : std_logic := '0';
signal m_axis_mm2s_tvalid : std_logic := '0';
signal m_axis_mm2s_tready : std_logic := '0';
-- DataMover S2MM Update Command Stream Signals
signal s_axis_updt_cmd_tvalid : std_logic := '0';
signal s_axis_updt_cmd_tready : std_logic := '0';
signal s_axis_updt_cmd_tdata : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover S2MM Update Status Stream Signals
signal m_axis_updt_sts_tvalid : std_logic := '0';
signal m_axis_updt_sts_tready : std_logic := '0';
signal m_axis_updt_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_updt_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
-- DataMover S2MM Update Stream Signals
signal s_axis_s2mm_tdata : std_logic_vector
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_tkeep : std_logic_vector
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0) := (others => '1');
signal s_axis_s2mm_tlast : std_logic := '0';
signal s_axis_s2mm_tvalid : std_logic := '0';
signal s_axis_s2mm_tready : std_logic := '0';
-- Channel 1 internals
signal ch1_ftch_active : std_logic := '0';
signal ch1_ftch_queue_empty : std_logic := '0';
signal ch1_ftch_queue_full : std_logic := '0';
signal ch1_nxtdesc_wren : std_logic := '0';
signal ch1_updt_active : std_logic := '0';
signal ch1_updt_queue_empty : std_logic := '0';
signal ch1_updt_curdesc_wren : std_logic := '0';
signal ch1_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_updt_ioc : std_logic := '0';
signal ch1_updt_ioc_irq_set_i : std_logic := '0';
signal ch1_dma_interr : std_logic := '0';
signal ch1_dma_slverr : std_logic := '0';
signal ch1_dma_decerr : std_logic := '0';
signal ch1_dma_interr_set_i : std_logic := '0';
signal ch1_dma_slverr_set_i : std_logic := '0';
signal ch1_dma_decerr_set_i : std_logic := '0';
signal ch1_updt_done : std_logic := '0';
signal ch1_ftch_pause : std_logic := '0';
-- Channel 2 internals
signal ch2_ftch_active : std_logic := '0';
signal ch2_ftch_queue_empty : std_logic := '0';
signal ch2_ftch_queue_full : std_logic := '0';
signal ch2_nxtdesc_wren : std_logic := '0';
signal ch2_updt_active : std_logic := '0';
signal ch2_updt_queue_empty : std_logic := '0';
signal ch2_updt_curdesc_wren : std_logic := '0';
signal ch2_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch2_updt_ioc : std_logic := '0';
signal ch2_updt_ioc_irq_set_i : std_logic := '0';
signal ch2_dma_interr : std_logic := '0';
signal ch2_dma_slverr : std_logic := '0';
signal ch2_dma_decerr : std_logic := '0';
signal ch2_dma_interr_set_i : std_logic := '0';
signal ch2_dma_slverr_set_i : std_logic := '0';
signal ch2_dma_decerr_set_i : std_logic := '0';
signal ch2_updt_done : std_logic := '0';
signal ch2_ftch_pause : std_logic := '0';
signal nxtdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ftch_cmnd_wr : std_logic := '0';
signal ftch_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
signal ftch_stale_desc : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal ch1_irqthresh_decr : std_logic := '0'; --CR567661
signal ch2_irqthresh_decr : std_logic := '0'; --CR567661
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
ftch_error <= ftch_error_i;
-- Always valid therefore fix to '1'
s_axis_s2mm_tkeep <= (others => '1');
-- Drive interrupt on complete set out
--ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i; -- CR567661
--ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i; -- CR567661
ch1_dma_interr_set <= ch1_dma_interr_set_i;
ch1_dma_slverr_set <= ch1_dma_slverr_set_i;
ch1_dma_decerr_set <= ch1_dma_decerr_set_i;
ch2_dma_interr_set <= ch2_dma_interr_set_i;
ch2_dma_slverr_set <= ch2_dma_slverr_set_i;
ch2_dma_decerr_set <= ch2_dma_decerr_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Manager
-------------------------------------------------------------------------------
I_SG_FETCH_MNGR : entity axi_vdma_v6_2_8.axi_sg_ftch_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,
ch1_updt_done => ch1_updt_done ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_curdesc => ch1_curdesc ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,
ch2_updt_done => ch2_updt_done ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_curdesc => ch2_curdesc ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
mm2s_err => mm2s_err ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
updt_error => updt_error_i ,
ftch_error => ftch_error_i ,
ftch_error_addr => ftch_error_addr
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Queue
-------------------------------------------------------------------------------
I_SG_FETCH_QUEUE : entity axi_vdma_v6_2_8.axi_sg_ftch_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_desc_flush => ch1_desc_flush ,
ch1_ftch_active => ch1_ftch_active ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control
ch2_ftch_active => ch2_ftch_active ,
ch2_desc_flush => ch2_desc_flush ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => m_axis_ch1_ftch_aclk ,
m_axis_ch1_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_ch1_ftch_tlast ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => m_axis_ch2_ftch_aclk ,
m_axis_ch2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_ch2_ftch_tlast
);
-- Include Scatter Gather Descriptor Update logic
GEN_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 1 generate
begin
-- CR567661
-- Route update version of IOC set to threshold
-- counter decrement control
ch1_irqthresh_decr <= ch1_updt_ioc_irq_set_i;
ch2_irqthresh_decr <= ch2_updt_ioc_irq_set_i;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i;
ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Update Manager
-------------------------------------------------------------------------------
I_SG_UPDATE_MNGR : entity axi_vdma_v6_2_8.axi_sg_updt_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
ch1_updt_interr_set => ch1_updt_interr_set ,
ch1_updt_slverr_set => ch1_updt_slverr_set ,
ch1_updt_decerr_set => ch1_updt_decerr_set ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
ch2_updt_interr_set => ch2_updt_interr_set ,
ch2_updt_slverr_set => ch2_updt_slverr_set ,
ch2_updt_decerr_set => ch2_updt_decerr_set ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
s2mm_err => s2mm_err ,
ftch_error => ftch_error_i ,
updt_error => updt_error_i ,
updt_error_addr => updt_error_addr
);
-------------------------------------------------------------------------------
-- Scatter Gather Update Queue
-------------------------------------------------------------------------------
I_SG_UPDATE_QUEUE : entity axi_vdma_v6_2_8.axi_sg_updt_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Channel 1 Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
-- Channel 2 Control
ch2_updt_active => ch2_updt_active ,
ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
-- Channel 2 Update Descriptor Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
-- S2MM Stream Out To DataMover
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => s_axis_ch1_updt_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => s_axis_ch2_updt_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis_ch2_updtsts_tlast => s_axis_ch2_updtsts_tlast
);
end generate GEN_DESC_UPDATE;
-- Exclude Scatter Gather Descriptor Update logic
GEN_NO_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 0 generate
begin
ch1_updt_idle <= '1';
ch1_updt_active <= '0';
-- ch1_updt_ioc_irq_set <= '0';--CR#569609
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set_i <= '0';
ch1_dma_slverr_set_i <= '0';
ch1_dma_decerr_set_i <= '0';
ch1_updt_done <= '1'; -- Always done
ch2_updt_idle <= '1';
ch2_updt_active <= '0';
-- ch2_updt_ioc_irq_set <= '0'; --CR#569609
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set_i <= '0';
ch2_dma_slverr_set_i <= '0';
ch2_dma_decerr_set_i <= '0';
ch2_updt_done <= '1'; -- Always done
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
m_axis_updt_sts_tready <= '0';
updt_error_i <= '0';
updt_error_addr <= (others => '0');
ch1_updt_curdesc_wren <= '0';
ch1_updt_curdesc <= (others => '0');
ch1_updt_queue_empty <= '0';
ch1_updt_ioc <= '0';
ch1_dma_interr <= '0';
ch1_dma_slverr <= '0';
ch1_dma_decerr <= '0';
ch2_updt_curdesc_wren <= '0';
ch2_updt_curdesc <= (others => '0');
ch2_updt_queue_empty <= '0';
ch2_updt_ioc <= '0';
ch2_dma_interr <= '0';
ch2_dma_slverr <= '0';
ch2_dma_decerr <= '0';
s_axis_s2mm_tdata <= (others => '0');
s_axis_s2mm_tlast <= '0';
s_axis_s2mm_tvalid <= '0';
s_axis_ch1_updtptr_tready <= '0';
s_axis_ch2_updtptr_tready <= '0';
s_axis_ch1_updtsts_tready <= '0';
s_axis_ch2_updtsts_tready <= '0';
-- CR567661
-- Route packet eof to threshold counter decrement control
ch1_irqthresh_decr <= ch1_packet_eof;
ch2_irqthresh_decr <= ch2_packet_eof;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_packet_eof;
ch2_updt_ioc_irq_set <= ch2_packet_eof;
end generate GEN_NO_DESC_UPDATE;
-------------------------------------------------------------------------------
-- Scatter Gather Interrupt Coalescing
-------------------------------------------------------------------------------
GEN_INTERRUPT_LOGIC : if C_INCLUDE_INTRPT = 1 generate
begin
I_AXI_SG_INTRPT : entity axi_vdma_v6_2_8.axi_sg_intrpt
generic map(
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_INCLUDE_DLYTMR => C_INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ch1_irqthresh_decr => ch1_irqthresh_decr , -- CR567661
ch1_irqthresh_rstdsbl => ch1_irqthresh_rstdsbl , -- CR572013
ch1_dlyirq_dsble => ch1_dlyirq_dsble ,
ch1_irqdelay_wren => ch1_irqdelay_wren ,
ch1_irqdelay => ch1_irqdelay ,
ch1_irqthresh_wren => ch1_irqthresh_wren ,
ch1_irqthresh => ch1_irqthresh ,
ch1_packet_sof => ch1_packet_sof ,
ch1_packet_eof => ch1_packet_eof ,
ch1_ioc_irq_set => ch1_ioc_irq_set ,
ch1_dly_irq_set => ch1_dly_irq_set ,
ch1_irqdelay_status => ch1_irqdelay_status ,
ch1_irqthresh_status => ch1_irqthresh_status ,
ch2_irqthresh_decr => ch2_irqthresh_decr , -- CR567661
ch2_irqthresh_rstdsbl => ch2_irqthresh_rstdsbl , -- CR572013
ch2_dlyirq_dsble => ch2_dlyirq_dsble ,
ch2_irqdelay_wren => ch2_irqdelay_wren ,
ch2_irqdelay => ch2_irqdelay ,
ch2_irqthresh_wren => ch2_irqthresh_wren ,
ch2_irqthresh => ch2_irqthresh ,
ch2_packet_sof => ch2_packet_sof ,
ch2_packet_eof => ch2_packet_eof ,
ch2_ioc_irq_set => ch2_ioc_irq_set ,
ch2_dly_irq_set => ch2_dly_irq_set ,
ch2_irqdelay_status => ch2_irqdelay_status ,
ch2_irqthresh_status => ch2_irqthresh_status
);
end generate GEN_INTERRUPT_LOGIC;
GEN_NO_INTRPT_LOGIC : if C_INCLUDE_INTRPT = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_NO_INTRPT_LOGIC;
-------------------------------------------------------------------------------
-- Scatter Gather DataMover Lite
-------------------------------------------------------------------------------
I_SG_AXI_DATAMOVER : entity axi_datamover_v5_1_11.axi_datamover
generic map(
C_INCLUDE_MM2S => INCLUDE_DESC_FETCH, -- Lite
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_MM2S_STSFIFO => 0, -- Exclude
C_MM2S_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_MM2S_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_MM2S_DRE => 0, -- No DRE
C_MM2S_BURST_SIZE => 16, -- Set to Min
C_MM2S_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_MM2S_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_INCLUDE_S2MM => INCLUDE_DESC_UPDATE, -- Lite
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_S_AXIS_S2MM_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_S2MM_STSFIFO => 0, -- Exclude
C_S2MM_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_S2MM_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_S2MM_DRE => 0, -- No DRE
C_S2MM_BURST_SIZE => 16, -- Set to Min;
C_S2MM_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_S2MM_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aresetn => dm_resetn ,
mm2s_halt => NEVER_HALT ,
mm2s_halt_cmplt => open ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => m_axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_ftch_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Datamover v4_032_a addional signals not needed for SG
--sg_ctl => (others => '0') ,
m_axi_mm2s_aruser => open ,
m_axi_s2mm_awuser => open ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_sg_araddr ,
m_axi_mm2s_arlen => m_axi_sg_arlen ,
m_axi_mm2s_arsize => m_axi_sg_arsize ,
m_axi_mm2s_arburst => m_axi_sg_arburst ,
m_axi_mm2s_arprot => m_axi_sg_arprot ,
m_axi_mm2s_arcache => m_axi_sg_arcache ,
m_axi_mm2s_arvalid => m_axi_sg_arvalid ,
m_axi_mm2s_arready => m_axi_sg_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_sg_rdata ,
m_axi_mm2s_rresp => m_axi_sg_rresp ,
m_axi_mm2s_rlast => m_axi_sg_rlast ,
m_axi_mm2s_rvalid => m_axi_sg_rvalid ,
m_axi_mm2s_rready => m_axi_sg_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_sg_aclk ,
m_axi_s2mm_aresetn => dm_resetn ,
s2mm_halt => NEVER_HALT ,
s2mm_halt_cmplt => open ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => m_axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_updt_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_updt_sts_tkeep ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_sg_awaddr ,
m_axi_s2mm_awlen => m_axi_sg_awlen ,
m_axi_s2mm_awsize => m_axi_sg_awsize ,
m_axi_s2mm_awburst => m_axi_sg_awburst ,
m_axi_s2mm_awprot => m_axi_sg_awprot ,
m_axi_s2mm_awcache => m_axi_sg_awcache ,
m_axi_s2mm_awvalid => m_axi_sg_awvalid ,
m_axi_s2mm_awready => m_axi_sg_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_sg_wdata ,
m_axi_s2mm_wstrb => m_axi_sg_wstrb ,
m_axi_s2mm_wlast => m_axi_sg_wlast ,
m_axi_s2mm_wvalid => m_axi_sg_wvalid ,
m_axi_s2mm_wready => m_axi_sg_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_sg_bresp ,
m_axi_s2mm_bvalid => m_axi_sg_bvalid ,
m_axi_s2mm_bready => m_axi_sg_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
-- Description: This entity is the top level entity for the AXI Scatter Gather
-- Engine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_1_11.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/1/10 v1_00_a
-- ^^^^^^
-- CR567661
-- Remapped interrupt threshold control to be driven based on whether update
-- engine is included or not.
-- ~~~~~~
-- GAB 7/27/10 v1_00_a
-- ^^^^^^
-- CR569609
-- Remove double driven signal for exclude update engine mode
-- ~~~~~~
-- GAB 8/12/10 v1_00_a
-- ^^^^^^
-- CR572013
-- Added ability to disable threshold count reset on delay timer timeout in
-- order to match legacy SDMA operation.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- Added ch1_aclk and ch2_aclk to allow for asynchronous operation
-- Added C_ACLK_IS_ASYNC parameter to set mode of clock synchronization
-- ~~~~~~
-- GAB 10/21/10 v2_01_a
-- ^^^^^^
-- Rolled version to v2_01_a
-- Updated to axi_datamover_v3_00_a
-- Updated tstrb ports to tkeep ports
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- Updated AXI Datamover to incorperate new ports and ***_TDATA_WIDTH parameters
-- ~~~~~~
-- GAB 2/2/11 v2_02_a
-- ^^^^^^
-- Update to AXI Datamover v2_01_a
-- ~~~~~~
-- GAB 6/13/11 v3_00_a
-- ^^^^^^
-- Update to AXI Datamover v3_00_a
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream out for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_DESC_UPDATE : integer range 0 to 1 := 1;
-- Include or Exclude Scatter Gather Descriptor Update
-- 0 = Exclude Descriptor Update
-- 1 = Include Descriptor Update
C_INCLUDE_INTRPT : integer range 0 to 1 := 1;
-- Include/Exclude interrupt logic coalescing
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
dm_resetn : in std_logic ; --
--
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_bvalid : in std_logic ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rlast : in std_logic ; --
m_axi_sg_rvalid : in std_logic ; --
m_axi_sg_rready : out std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
--
--
-- Channel 1 Interrupt Coalescing Signals --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ; --
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
--
--
-- Channel 1 AXI Update Stream In --
s_axis_ch1_updt_aclk : in std_logic ; --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
--
-- Channel 2 Interrupt Coalescing Signals --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
--
-- Channel 2 AXI Update Stream In --
s_axis_ch2_updt_aclk : in std_logic ; --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
--
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--
-- Error addresses --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant AXI_LITE_MODE : integer := 2; -- DataMover Lite Mode
constant EXCLUDE : integer := 0; -- Define Exclude as 0
constant NEVER_HALT : std_logic := '0'; -- Never halt sg datamover
-- Always include descriptor fetch (use lite datamover)
constant INCLUDE_DESC_FETCH : integer := AXI_LITE_MODE;
-- Selectable include descriptor update (use lite datamover)
constant INCLUDE_DESC_UPDATE : integer := AXI_LITE_MODE * C_INCLUDE_DESC_UPDATE;
-- Always allow address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- If async mode and number of descriptors to fetch is zero then set number
-- of descriptors to fetch as 1.
constant SG_FTCH_DESC2QUEUE : integer := max2(C_SG_FTCH_DESC2QUEUE,C_AXIS_IS_ASYNC);
constant SG_UPDT_DESC2QUEUE : integer := max2(C_SG_UPDT_DESC2QUEUE,C_AXIS_IS_ASYNC);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- DataMover MM2S Fetch Command Stream Signals
signal s_axis_ftch_cmd_tvalid : std_logic := '0';
signal s_axis_ftch_cmd_tready : std_logic := '0';
signal s_axis_ftch_cmd_tdata : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover MM2S Fetch Status Stream Signals
signal m_axis_ftch_sts_tvalid : std_logic := '0';
signal m_axis_ftch_sts_tready : std_logic := '0';
signal m_axis_ftch_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_ftch_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
-- DataMover MM2S Fetch Stream Signals
signal m_axis_mm2s_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_tkeep : std_logic_vector
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_mm2s_tlast : std_logic := '0';
signal m_axis_mm2s_tvalid : std_logic := '0';
signal m_axis_mm2s_tready : std_logic := '0';
-- DataMover S2MM Update Command Stream Signals
signal s_axis_updt_cmd_tvalid : std_logic := '0';
signal s_axis_updt_cmd_tready : std_logic := '0';
signal s_axis_updt_cmd_tdata : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover S2MM Update Status Stream Signals
signal m_axis_updt_sts_tvalid : std_logic := '0';
signal m_axis_updt_sts_tready : std_logic := '0';
signal m_axis_updt_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_updt_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
-- DataMover S2MM Update Stream Signals
signal s_axis_s2mm_tdata : std_logic_vector
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_tkeep : std_logic_vector
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0) := (others => '1');
signal s_axis_s2mm_tlast : std_logic := '0';
signal s_axis_s2mm_tvalid : std_logic := '0';
signal s_axis_s2mm_tready : std_logic := '0';
-- Channel 1 internals
signal ch1_ftch_active : std_logic := '0';
signal ch1_ftch_queue_empty : std_logic := '0';
signal ch1_ftch_queue_full : std_logic := '0';
signal ch1_nxtdesc_wren : std_logic := '0';
signal ch1_updt_active : std_logic := '0';
signal ch1_updt_queue_empty : std_logic := '0';
signal ch1_updt_curdesc_wren : std_logic := '0';
signal ch1_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_updt_ioc : std_logic := '0';
signal ch1_updt_ioc_irq_set_i : std_logic := '0';
signal ch1_dma_interr : std_logic := '0';
signal ch1_dma_slverr : std_logic := '0';
signal ch1_dma_decerr : std_logic := '0';
signal ch1_dma_interr_set_i : std_logic := '0';
signal ch1_dma_slverr_set_i : std_logic := '0';
signal ch1_dma_decerr_set_i : std_logic := '0';
signal ch1_updt_done : std_logic := '0';
signal ch1_ftch_pause : std_logic := '0';
-- Channel 2 internals
signal ch2_ftch_active : std_logic := '0';
signal ch2_ftch_queue_empty : std_logic := '0';
signal ch2_ftch_queue_full : std_logic := '0';
signal ch2_nxtdesc_wren : std_logic := '0';
signal ch2_updt_active : std_logic := '0';
signal ch2_updt_queue_empty : std_logic := '0';
signal ch2_updt_curdesc_wren : std_logic := '0';
signal ch2_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch2_updt_ioc : std_logic := '0';
signal ch2_updt_ioc_irq_set_i : std_logic := '0';
signal ch2_dma_interr : std_logic := '0';
signal ch2_dma_slverr : std_logic := '0';
signal ch2_dma_decerr : std_logic := '0';
signal ch2_dma_interr_set_i : std_logic := '0';
signal ch2_dma_slverr_set_i : std_logic := '0';
signal ch2_dma_decerr_set_i : std_logic := '0';
signal ch2_updt_done : std_logic := '0';
signal ch2_ftch_pause : std_logic := '0';
signal nxtdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ftch_cmnd_wr : std_logic := '0';
signal ftch_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
signal ftch_stale_desc : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal ch1_irqthresh_decr : std_logic := '0'; --CR567661
signal ch2_irqthresh_decr : std_logic := '0'; --CR567661
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
ftch_error <= ftch_error_i;
-- Always valid therefore fix to '1'
s_axis_s2mm_tkeep <= (others => '1');
-- Drive interrupt on complete set out
--ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i; -- CR567661
--ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i; -- CR567661
ch1_dma_interr_set <= ch1_dma_interr_set_i;
ch1_dma_slverr_set <= ch1_dma_slverr_set_i;
ch1_dma_decerr_set <= ch1_dma_decerr_set_i;
ch2_dma_interr_set <= ch2_dma_interr_set_i;
ch2_dma_slverr_set <= ch2_dma_slverr_set_i;
ch2_dma_decerr_set <= ch2_dma_decerr_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Manager
-------------------------------------------------------------------------------
I_SG_FETCH_MNGR : entity axi_vdma_v6_2_8.axi_sg_ftch_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,
ch1_updt_done => ch1_updt_done ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_curdesc => ch1_curdesc ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,
ch2_updt_done => ch2_updt_done ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_curdesc => ch2_curdesc ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
mm2s_err => mm2s_err ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
updt_error => updt_error_i ,
ftch_error => ftch_error_i ,
ftch_error_addr => ftch_error_addr
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Queue
-------------------------------------------------------------------------------
I_SG_FETCH_QUEUE : entity axi_vdma_v6_2_8.axi_sg_ftch_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_desc_flush => ch1_desc_flush ,
ch1_ftch_active => ch1_ftch_active ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control
ch2_ftch_active => ch2_ftch_active ,
ch2_desc_flush => ch2_desc_flush ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => m_axis_ch1_ftch_aclk ,
m_axis_ch1_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_ch1_ftch_tlast ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => m_axis_ch2_ftch_aclk ,
m_axis_ch2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_ch2_ftch_tlast
);
-- Include Scatter Gather Descriptor Update logic
GEN_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 1 generate
begin
-- CR567661
-- Route update version of IOC set to threshold
-- counter decrement control
ch1_irqthresh_decr <= ch1_updt_ioc_irq_set_i;
ch2_irqthresh_decr <= ch2_updt_ioc_irq_set_i;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i;
ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Update Manager
-------------------------------------------------------------------------------
I_SG_UPDATE_MNGR : entity axi_vdma_v6_2_8.axi_sg_updt_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
ch1_updt_interr_set => ch1_updt_interr_set ,
ch1_updt_slverr_set => ch1_updt_slverr_set ,
ch1_updt_decerr_set => ch1_updt_decerr_set ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
ch2_updt_interr_set => ch2_updt_interr_set ,
ch2_updt_slverr_set => ch2_updt_slverr_set ,
ch2_updt_decerr_set => ch2_updt_decerr_set ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
s2mm_err => s2mm_err ,
ftch_error => ftch_error_i ,
updt_error => updt_error_i ,
updt_error_addr => updt_error_addr
);
-------------------------------------------------------------------------------
-- Scatter Gather Update Queue
-------------------------------------------------------------------------------
I_SG_UPDATE_QUEUE : entity axi_vdma_v6_2_8.axi_sg_updt_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Channel 1 Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
-- Channel 2 Control
ch2_updt_active => ch2_updt_active ,
ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
-- Channel 2 Update Descriptor Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
-- S2MM Stream Out To DataMover
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => s_axis_ch1_updt_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => s_axis_ch2_updt_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis_ch2_updtsts_tlast => s_axis_ch2_updtsts_tlast
);
end generate GEN_DESC_UPDATE;
-- Exclude Scatter Gather Descriptor Update logic
GEN_NO_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 0 generate
begin
ch1_updt_idle <= '1';
ch1_updt_active <= '0';
-- ch1_updt_ioc_irq_set <= '0';--CR#569609
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set_i <= '0';
ch1_dma_slverr_set_i <= '0';
ch1_dma_decerr_set_i <= '0';
ch1_updt_done <= '1'; -- Always done
ch2_updt_idle <= '1';
ch2_updt_active <= '0';
-- ch2_updt_ioc_irq_set <= '0'; --CR#569609
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set_i <= '0';
ch2_dma_slverr_set_i <= '0';
ch2_dma_decerr_set_i <= '0';
ch2_updt_done <= '1'; -- Always done
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
m_axis_updt_sts_tready <= '0';
updt_error_i <= '0';
updt_error_addr <= (others => '0');
ch1_updt_curdesc_wren <= '0';
ch1_updt_curdesc <= (others => '0');
ch1_updt_queue_empty <= '0';
ch1_updt_ioc <= '0';
ch1_dma_interr <= '0';
ch1_dma_slverr <= '0';
ch1_dma_decerr <= '0';
ch2_updt_curdesc_wren <= '0';
ch2_updt_curdesc <= (others => '0');
ch2_updt_queue_empty <= '0';
ch2_updt_ioc <= '0';
ch2_dma_interr <= '0';
ch2_dma_slverr <= '0';
ch2_dma_decerr <= '0';
s_axis_s2mm_tdata <= (others => '0');
s_axis_s2mm_tlast <= '0';
s_axis_s2mm_tvalid <= '0';
s_axis_ch1_updtptr_tready <= '0';
s_axis_ch2_updtptr_tready <= '0';
s_axis_ch1_updtsts_tready <= '0';
s_axis_ch2_updtsts_tready <= '0';
-- CR567661
-- Route packet eof to threshold counter decrement control
ch1_irqthresh_decr <= ch1_packet_eof;
ch2_irqthresh_decr <= ch2_packet_eof;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_packet_eof;
ch2_updt_ioc_irq_set <= ch2_packet_eof;
end generate GEN_NO_DESC_UPDATE;
-------------------------------------------------------------------------------
-- Scatter Gather Interrupt Coalescing
-------------------------------------------------------------------------------
GEN_INTERRUPT_LOGIC : if C_INCLUDE_INTRPT = 1 generate
begin
I_AXI_SG_INTRPT : entity axi_vdma_v6_2_8.axi_sg_intrpt
generic map(
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_INCLUDE_DLYTMR => C_INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ch1_irqthresh_decr => ch1_irqthresh_decr , -- CR567661
ch1_irqthresh_rstdsbl => ch1_irqthresh_rstdsbl , -- CR572013
ch1_dlyirq_dsble => ch1_dlyirq_dsble ,
ch1_irqdelay_wren => ch1_irqdelay_wren ,
ch1_irqdelay => ch1_irqdelay ,
ch1_irqthresh_wren => ch1_irqthresh_wren ,
ch1_irqthresh => ch1_irqthresh ,
ch1_packet_sof => ch1_packet_sof ,
ch1_packet_eof => ch1_packet_eof ,
ch1_ioc_irq_set => ch1_ioc_irq_set ,
ch1_dly_irq_set => ch1_dly_irq_set ,
ch1_irqdelay_status => ch1_irqdelay_status ,
ch1_irqthresh_status => ch1_irqthresh_status ,
ch2_irqthresh_decr => ch2_irqthresh_decr , -- CR567661
ch2_irqthresh_rstdsbl => ch2_irqthresh_rstdsbl , -- CR572013
ch2_dlyirq_dsble => ch2_dlyirq_dsble ,
ch2_irqdelay_wren => ch2_irqdelay_wren ,
ch2_irqdelay => ch2_irqdelay ,
ch2_irqthresh_wren => ch2_irqthresh_wren ,
ch2_irqthresh => ch2_irqthresh ,
ch2_packet_sof => ch2_packet_sof ,
ch2_packet_eof => ch2_packet_eof ,
ch2_ioc_irq_set => ch2_ioc_irq_set ,
ch2_dly_irq_set => ch2_dly_irq_set ,
ch2_irqdelay_status => ch2_irqdelay_status ,
ch2_irqthresh_status => ch2_irqthresh_status
);
end generate GEN_INTERRUPT_LOGIC;
GEN_NO_INTRPT_LOGIC : if C_INCLUDE_INTRPT = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_NO_INTRPT_LOGIC;
-------------------------------------------------------------------------------
-- Scatter Gather DataMover Lite
-------------------------------------------------------------------------------
I_SG_AXI_DATAMOVER : entity axi_datamover_v5_1_11.axi_datamover
generic map(
C_INCLUDE_MM2S => INCLUDE_DESC_FETCH, -- Lite
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_MM2S_STSFIFO => 0, -- Exclude
C_MM2S_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_MM2S_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_MM2S_DRE => 0, -- No DRE
C_MM2S_BURST_SIZE => 16, -- Set to Min
C_MM2S_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_MM2S_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_INCLUDE_S2MM => INCLUDE_DESC_UPDATE, -- Lite
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_S_AXIS_S2MM_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_S2MM_STSFIFO => 0, -- Exclude
C_S2MM_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_S2MM_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_S2MM_DRE => 0, -- No DRE
C_S2MM_BURST_SIZE => 16, -- Set to Min;
C_S2MM_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_S2MM_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aresetn => dm_resetn ,
mm2s_halt => NEVER_HALT ,
mm2s_halt_cmplt => open ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => m_axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_ftch_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Datamover v4_032_a addional signals not needed for SG
--sg_ctl => (others => '0') ,
m_axi_mm2s_aruser => open ,
m_axi_s2mm_awuser => open ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_sg_araddr ,
m_axi_mm2s_arlen => m_axi_sg_arlen ,
m_axi_mm2s_arsize => m_axi_sg_arsize ,
m_axi_mm2s_arburst => m_axi_sg_arburst ,
m_axi_mm2s_arprot => m_axi_sg_arprot ,
m_axi_mm2s_arcache => m_axi_sg_arcache ,
m_axi_mm2s_arvalid => m_axi_sg_arvalid ,
m_axi_mm2s_arready => m_axi_sg_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_sg_rdata ,
m_axi_mm2s_rresp => m_axi_sg_rresp ,
m_axi_mm2s_rlast => m_axi_sg_rlast ,
m_axi_mm2s_rvalid => m_axi_sg_rvalid ,
m_axi_mm2s_rready => m_axi_sg_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_sg_aclk ,
m_axi_s2mm_aresetn => dm_resetn ,
s2mm_halt => NEVER_HALT ,
s2mm_halt_cmplt => open ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => m_axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_updt_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_updt_sts_tkeep ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_sg_awaddr ,
m_axi_s2mm_awlen => m_axi_sg_awlen ,
m_axi_s2mm_awsize => m_axi_sg_awsize ,
m_axi_s2mm_awburst => m_axi_sg_awburst ,
m_axi_s2mm_awprot => m_axi_sg_awprot ,
m_axi_s2mm_awcache => m_axi_sg_awcache ,
m_axi_s2mm_awvalid => m_axi_sg_awvalid ,
m_axi_s2mm_awready => m_axi_sg_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_sg_wdata ,
m_axi_s2mm_wstrb => m_axi_sg_wstrb ,
m_axi_s2mm_wlast => m_axi_sg_wlast ,
m_axi_s2mm_wvalid => m_axi_sg_wvalid ,
m_axi_s2mm_wready => m_axi_sg_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_sg_bresp ,
m_axi_s2mm_bvalid => m_axi_sg_bvalid ,
m_axi_s2mm_bready => m_axi_sg_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
-- Description: This entity is the top level entity for the AXI Scatter Gather
-- Engine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd
-- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_1_11.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/1/10 v1_00_a
-- ^^^^^^
-- CR567661
-- Remapped interrupt threshold control to be driven based on whether update
-- engine is included or not.
-- ~~~~~~
-- GAB 7/27/10 v1_00_a
-- ^^^^^^
-- CR569609
-- Remove double driven signal for exclude update engine mode
-- ~~~~~~
-- GAB 8/12/10 v1_00_a
-- ^^^^^^
-- CR572013
-- Added ability to disable threshold count reset on delay timer timeout in
-- order to match legacy SDMA operation.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- Added ch1_aclk and ch2_aclk to allow for asynchronous operation
-- Added C_ACLK_IS_ASYNC parameter to set mode of clock synchronization
-- ~~~~~~
-- GAB 10/21/10 v2_01_a
-- ^^^^^^
-- Rolled version to v2_01_a
-- Updated to axi_datamover_v3_00_a
-- Updated tstrb ports to tkeep ports
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- Updated AXI Datamover to incorperate new ports and ***_TDATA_WIDTH parameters
-- ~~~~~~
-- GAB 2/2/11 v2_02_a
-- ^^^^^^
-- Update to AXI Datamover v2_01_a
-- ~~~~~~
-- GAB 6/13/11 v3_00_a
-- ^^^^^^
-- Update to AXI Datamover v3_00_a
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_sg_pkg.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream out for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_DESC_UPDATE : integer range 0 to 1 := 1;
-- Include or Exclude Scatter Gather Descriptor Update
-- 0 = Exclude Descriptor Update
-- 1 = Include Descriptor Update
C_INCLUDE_INTRPT : integer range 0 to 1 := 1;
-- Include/Exclude interrupt logic coalescing
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
dm_resetn : in std_logic ; --
--
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_bvalid : in std_logic ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rlast : in std_logic ; --
m_axi_sg_rvalid : in std_logic ; --
m_axi_sg_rready : out std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
--
--
-- Channel 1 Interrupt Coalescing Signals --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ; --
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
--
--
-- Channel 1 AXI Update Stream In --
s_axis_ch1_updt_aclk : in std_logic ; --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
--
-- Channel 2 Interrupt Coalescing Signals --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
--
-- Channel 2 AXI Update Stream In --
s_axis_ch2_updt_aclk : in std_logic ; --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
--
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--
-- Error addresses --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant AXI_LITE_MODE : integer := 2; -- DataMover Lite Mode
constant EXCLUDE : integer := 0; -- Define Exclude as 0
constant NEVER_HALT : std_logic := '0'; -- Never halt sg datamover
-- Always include descriptor fetch (use lite datamover)
constant INCLUDE_DESC_FETCH : integer := AXI_LITE_MODE;
-- Selectable include descriptor update (use lite datamover)
constant INCLUDE_DESC_UPDATE : integer := AXI_LITE_MODE * C_INCLUDE_DESC_UPDATE;
-- Always allow address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- If async mode and number of descriptors to fetch is zero then set number
-- of descriptors to fetch as 1.
constant SG_FTCH_DESC2QUEUE : integer := max2(C_SG_FTCH_DESC2QUEUE,C_AXIS_IS_ASYNC);
constant SG_UPDT_DESC2QUEUE : integer := max2(C_SG_UPDT_DESC2QUEUE,C_AXIS_IS_ASYNC);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- DataMover MM2S Fetch Command Stream Signals
signal s_axis_ftch_cmd_tvalid : std_logic := '0';
signal s_axis_ftch_cmd_tready : std_logic := '0';
signal s_axis_ftch_cmd_tdata : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover MM2S Fetch Status Stream Signals
signal m_axis_ftch_sts_tvalid : std_logic := '0';
signal m_axis_ftch_sts_tready : std_logic := '0';
signal m_axis_ftch_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_ftch_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
-- DataMover MM2S Fetch Stream Signals
signal m_axis_mm2s_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_tkeep : std_logic_vector
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_mm2s_tlast : std_logic := '0';
signal m_axis_mm2s_tvalid : std_logic := '0';
signal m_axis_mm2s_tready : std_logic := '0';
-- DataMover S2MM Update Command Stream Signals
signal s_axis_updt_cmd_tvalid : std_logic := '0';
signal s_axis_updt_cmd_tready : std_logic := '0';
signal s_axis_updt_cmd_tdata : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover S2MM Update Status Stream Signals
signal m_axis_updt_sts_tvalid : std_logic := '0';
signal m_axis_updt_sts_tready : std_logic := '0';
signal m_axis_updt_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_updt_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
-- DataMover S2MM Update Stream Signals
signal s_axis_s2mm_tdata : std_logic_vector
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_tkeep : std_logic_vector
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0) := (others => '1');
signal s_axis_s2mm_tlast : std_logic := '0';
signal s_axis_s2mm_tvalid : std_logic := '0';
signal s_axis_s2mm_tready : std_logic := '0';
-- Channel 1 internals
signal ch1_ftch_active : std_logic := '0';
signal ch1_ftch_queue_empty : std_logic := '0';
signal ch1_ftch_queue_full : std_logic := '0';
signal ch1_nxtdesc_wren : std_logic := '0';
signal ch1_updt_active : std_logic := '0';
signal ch1_updt_queue_empty : std_logic := '0';
signal ch1_updt_curdesc_wren : std_logic := '0';
signal ch1_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_updt_ioc : std_logic := '0';
signal ch1_updt_ioc_irq_set_i : std_logic := '0';
signal ch1_dma_interr : std_logic := '0';
signal ch1_dma_slverr : std_logic := '0';
signal ch1_dma_decerr : std_logic := '0';
signal ch1_dma_interr_set_i : std_logic := '0';
signal ch1_dma_slverr_set_i : std_logic := '0';
signal ch1_dma_decerr_set_i : std_logic := '0';
signal ch1_updt_done : std_logic := '0';
signal ch1_ftch_pause : std_logic := '0';
-- Channel 2 internals
signal ch2_ftch_active : std_logic := '0';
signal ch2_ftch_queue_empty : std_logic := '0';
signal ch2_ftch_queue_full : std_logic := '0';
signal ch2_nxtdesc_wren : std_logic := '0';
signal ch2_updt_active : std_logic := '0';
signal ch2_updt_queue_empty : std_logic := '0';
signal ch2_updt_curdesc_wren : std_logic := '0';
signal ch2_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch2_updt_ioc : std_logic := '0';
signal ch2_updt_ioc_irq_set_i : std_logic := '0';
signal ch2_dma_interr : std_logic := '0';
signal ch2_dma_slverr : std_logic := '0';
signal ch2_dma_decerr : std_logic := '0';
signal ch2_dma_interr_set_i : std_logic := '0';
signal ch2_dma_slverr_set_i : std_logic := '0';
signal ch2_dma_decerr_set_i : std_logic := '0';
signal ch2_updt_done : std_logic := '0';
signal ch2_ftch_pause : std_logic := '0';
signal nxtdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ftch_cmnd_wr : std_logic := '0';
signal ftch_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
signal ftch_stale_desc : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal ch1_irqthresh_decr : std_logic := '0'; --CR567661
signal ch2_irqthresh_decr : std_logic := '0'; --CR567661
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
ftch_error <= ftch_error_i;
-- Always valid therefore fix to '1'
s_axis_s2mm_tkeep <= (others => '1');
-- Drive interrupt on complete set out
--ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i; -- CR567661
--ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i; -- CR567661
ch1_dma_interr_set <= ch1_dma_interr_set_i;
ch1_dma_slverr_set <= ch1_dma_slverr_set_i;
ch1_dma_decerr_set <= ch1_dma_decerr_set_i;
ch2_dma_interr_set <= ch2_dma_interr_set_i;
ch2_dma_slverr_set <= ch2_dma_slverr_set_i;
ch2_dma_decerr_set <= ch2_dma_decerr_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Manager
-------------------------------------------------------------------------------
I_SG_FETCH_MNGR : entity axi_vdma_v6_2_8.axi_sg_ftch_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,
ch1_updt_done => ch1_updt_done ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_curdesc => ch1_curdesc ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,
ch2_updt_done => ch2_updt_done ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_curdesc => ch2_curdesc ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
mm2s_err => mm2s_err ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
updt_error => updt_error_i ,
ftch_error => ftch_error_i ,
ftch_error_addr => ftch_error_addr
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Queue
-------------------------------------------------------------------------------
I_SG_FETCH_QUEUE : entity axi_vdma_v6_2_8.axi_sg_ftch_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_desc_flush => ch1_desc_flush ,
ch1_ftch_active => ch1_ftch_active ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control
ch2_ftch_active => ch2_ftch_active ,
ch2_desc_flush => ch2_desc_flush ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => m_axis_ch1_ftch_aclk ,
m_axis_ch1_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_ch1_ftch_tlast ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => m_axis_ch2_ftch_aclk ,
m_axis_ch2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_ch2_ftch_tlast
);
-- Include Scatter Gather Descriptor Update logic
GEN_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 1 generate
begin
-- CR567661
-- Route update version of IOC set to threshold
-- counter decrement control
ch1_irqthresh_decr <= ch1_updt_ioc_irq_set_i;
ch2_irqthresh_decr <= ch2_updt_ioc_irq_set_i;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i;
ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Update Manager
-------------------------------------------------------------------------------
I_SG_UPDATE_MNGR : entity axi_vdma_v6_2_8.axi_sg_updt_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
ch1_updt_interr_set => ch1_updt_interr_set ,
ch1_updt_slverr_set => ch1_updt_slverr_set ,
ch1_updt_decerr_set => ch1_updt_decerr_set ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
ch2_updt_interr_set => ch2_updt_interr_set ,
ch2_updt_slverr_set => ch2_updt_slverr_set ,
ch2_updt_decerr_set => ch2_updt_decerr_set ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
s2mm_err => s2mm_err ,
ftch_error => ftch_error_i ,
updt_error => updt_error_i ,
updt_error_addr => updt_error_addr
);
-------------------------------------------------------------------------------
-- Scatter Gather Update Queue
-------------------------------------------------------------------------------
I_SG_UPDATE_QUEUE : entity axi_vdma_v6_2_8.axi_sg_updt_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Channel 1 Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
-- Channel 2 Control
ch2_updt_active => ch2_updt_active ,
ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
-- Channel 2 Update Descriptor Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
-- S2MM Stream Out To DataMover
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => s_axis_ch1_updt_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => s_axis_ch2_updt_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_ch2_updtsts_tready ,
s_axis_ch2_updtsts_tlast => s_axis_ch2_updtsts_tlast
);
end generate GEN_DESC_UPDATE;
-- Exclude Scatter Gather Descriptor Update logic
GEN_NO_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 0 generate
begin
ch1_updt_idle <= '1';
ch1_updt_active <= '0';
-- ch1_updt_ioc_irq_set <= '0';--CR#569609
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set_i <= '0';
ch1_dma_slverr_set_i <= '0';
ch1_dma_decerr_set_i <= '0';
ch1_updt_done <= '1'; -- Always done
ch2_updt_idle <= '1';
ch2_updt_active <= '0';
-- ch2_updt_ioc_irq_set <= '0'; --CR#569609
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set_i <= '0';
ch2_dma_slverr_set_i <= '0';
ch2_dma_decerr_set_i <= '0';
ch2_updt_done <= '1'; -- Always done
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
m_axis_updt_sts_tready <= '0';
updt_error_i <= '0';
updt_error_addr <= (others => '0');
ch1_updt_curdesc_wren <= '0';
ch1_updt_curdesc <= (others => '0');
ch1_updt_queue_empty <= '0';
ch1_updt_ioc <= '0';
ch1_dma_interr <= '0';
ch1_dma_slverr <= '0';
ch1_dma_decerr <= '0';
ch2_updt_curdesc_wren <= '0';
ch2_updt_curdesc <= (others => '0');
ch2_updt_queue_empty <= '0';
ch2_updt_ioc <= '0';
ch2_dma_interr <= '0';
ch2_dma_slverr <= '0';
ch2_dma_decerr <= '0';
s_axis_s2mm_tdata <= (others => '0');
s_axis_s2mm_tlast <= '0';
s_axis_s2mm_tvalid <= '0';
s_axis_ch1_updtptr_tready <= '0';
s_axis_ch2_updtptr_tready <= '0';
s_axis_ch1_updtsts_tready <= '0';
s_axis_ch2_updtsts_tready <= '0';
-- CR567661
-- Route packet eof to threshold counter decrement control
ch1_irqthresh_decr <= ch1_packet_eof;
ch2_irqthresh_decr <= ch2_packet_eof;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_packet_eof;
ch2_updt_ioc_irq_set <= ch2_packet_eof;
end generate GEN_NO_DESC_UPDATE;
-------------------------------------------------------------------------------
-- Scatter Gather Interrupt Coalescing
-------------------------------------------------------------------------------
GEN_INTERRUPT_LOGIC : if C_INCLUDE_INTRPT = 1 generate
begin
I_AXI_SG_INTRPT : entity axi_vdma_v6_2_8.axi_sg_intrpt
generic map(
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_INCLUDE_DLYTMR => C_INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ch1_irqthresh_decr => ch1_irqthresh_decr , -- CR567661
ch1_irqthresh_rstdsbl => ch1_irqthresh_rstdsbl , -- CR572013
ch1_dlyirq_dsble => ch1_dlyirq_dsble ,
ch1_irqdelay_wren => ch1_irqdelay_wren ,
ch1_irqdelay => ch1_irqdelay ,
ch1_irqthresh_wren => ch1_irqthresh_wren ,
ch1_irqthresh => ch1_irqthresh ,
ch1_packet_sof => ch1_packet_sof ,
ch1_packet_eof => ch1_packet_eof ,
ch1_ioc_irq_set => ch1_ioc_irq_set ,
ch1_dly_irq_set => ch1_dly_irq_set ,
ch1_irqdelay_status => ch1_irqdelay_status ,
ch1_irqthresh_status => ch1_irqthresh_status ,
ch2_irqthresh_decr => ch2_irqthresh_decr , -- CR567661
ch2_irqthresh_rstdsbl => ch2_irqthresh_rstdsbl , -- CR572013
ch2_dlyirq_dsble => ch2_dlyirq_dsble ,
ch2_irqdelay_wren => ch2_irqdelay_wren ,
ch2_irqdelay => ch2_irqdelay ,
ch2_irqthresh_wren => ch2_irqthresh_wren ,
ch2_irqthresh => ch2_irqthresh ,
ch2_packet_sof => ch2_packet_sof ,
ch2_packet_eof => ch2_packet_eof ,
ch2_ioc_irq_set => ch2_ioc_irq_set ,
ch2_dly_irq_set => ch2_dly_irq_set ,
ch2_irqdelay_status => ch2_irqdelay_status ,
ch2_irqthresh_status => ch2_irqthresh_status
);
end generate GEN_INTERRUPT_LOGIC;
GEN_NO_INTRPT_LOGIC : if C_INCLUDE_INTRPT = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_NO_INTRPT_LOGIC;
-------------------------------------------------------------------------------
-- Scatter Gather DataMover Lite
-------------------------------------------------------------------------------
I_SG_AXI_DATAMOVER : entity axi_datamover_v5_1_11.axi_datamover
generic map(
C_INCLUDE_MM2S => INCLUDE_DESC_FETCH, -- Lite
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_MM2S_STSFIFO => 0, -- Exclude
C_MM2S_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_MM2S_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_MM2S_DRE => 0, -- No DRE
C_MM2S_BURST_SIZE => 16, -- Set to Min
C_MM2S_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_MM2S_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_INCLUDE_S2MM => INCLUDE_DESC_UPDATE, -- Lite
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_S_AXIS_S2MM_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_S2MM_STSFIFO => 0, -- Exclude
C_S2MM_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_S2MM_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_S2MM_DRE => 0, -- No DRE
C_S2MM_BURST_SIZE => 16, -- Set to Min;
C_S2MM_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_S2MM_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aresetn => dm_resetn ,
mm2s_halt => NEVER_HALT ,
mm2s_halt_cmplt => open ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => m_axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_ftch_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Datamover v4_032_a addional signals not needed for SG
--sg_ctl => (others => '0') ,
m_axi_mm2s_aruser => open ,
m_axi_s2mm_awuser => open ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_sg_araddr ,
m_axi_mm2s_arlen => m_axi_sg_arlen ,
m_axi_mm2s_arsize => m_axi_sg_arsize ,
m_axi_mm2s_arburst => m_axi_sg_arburst ,
m_axi_mm2s_arprot => m_axi_sg_arprot ,
m_axi_mm2s_arcache => m_axi_sg_arcache ,
m_axi_mm2s_arvalid => m_axi_sg_arvalid ,
m_axi_mm2s_arready => m_axi_sg_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_sg_rdata ,
m_axi_mm2s_rresp => m_axi_sg_rresp ,
m_axi_mm2s_rlast => m_axi_sg_rlast ,
m_axi_mm2s_rvalid => m_axi_sg_rvalid ,
m_axi_mm2s_rready => m_axi_sg_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_sg_aclk ,
m_axi_s2mm_aresetn => dm_resetn ,
s2mm_halt => NEVER_HALT ,
s2mm_halt_cmplt => open ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => m_axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_updt_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_updt_sts_tkeep ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_sg_awaddr ,
m_axi_s2mm_awlen => m_axi_sg_awlen ,
m_axi_s2mm_awsize => m_axi_sg_awsize ,
m_axi_s2mm_awburst => m_axi_sg_awburst ,
m_axi_s2mm_awprot => m_axi_sg_awprot ,
m_axi_s2mm_awcache => m_axi_sg_awcache ,
m_axi_s2mm_awvalid => m_axi_sg_awvalid ,
m_axi_s2mm_awready => m_axi_sg_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_sg_wdata ,
m_axi_s2mm_wstrb => m_axi_sg_wstrb ,
m_axi_s2mm_wlast => m_axi_sg_wlast ,
m_axi_s2mm_wvalid => m_axi_sg_wvalid ,
m_axi_s2mm_wready => m_axi_sg_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_sg_bresp ,
m_axi_s2mm_bvalid => m_axi_sg_bvalid ,
m_axi_s2mm_bready => m_axi_sg_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nor2to1 is
port (
A: in std_logic;
B: in std_logic;
Z: out std_logic
);
end nor2to1;
architecture behavioral of nor2to1 is
begin
Z <= A nor B;
end behavioral; |
entity tb_arr06 is
end tb_arr06;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_arr06 is
signal clk : std_logic;
signal val : std_logic_vector(7 downto 0);
signal res : std_logic_vector(7 downto 0);
signal par : std_logic;
begin
dut: entity work.arr06
port map (clk => clk, val => val, res => res, par => par);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
val <= x"a0";
pulse;
val <= x"71";
pulse;
val <= x"82";
pulse;
val <= x"23";
pulse;
val <= x"fe";
pulse;
assert res = x"a0" severity failure;
val <= x"e4";
pulse;
assert res = x"71" severity failure;
val <= x"c5";
pulse;
assert res = x"82" severity failure;
val <= x"f6";
pulse;
assert res = x"23" severity failure;
val <= x"57";
pulse;
assert res = x"fe" severity failure;
wait;
end process;
end behav;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlx-r.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
use work.alu_types.all,
work.reg_file_types.all;
architecture rtl of dlx is
component alu is
port ( s1 : in dlx_word;
s2 : in dlx_word;
result : out dlx_word;
func : in alu_func;
zero, negative, overflow : out std_logic );
end component alu;
component reg_file is
port ( a1 : in reg_file_addr;
q1 : out dlx_word;
a2 : in reg_file_addr;
q2 : out dlx_word;
a3 : in reg_file_addr;
d3 : in dlx_word;
write_en : in std_logic );
end component reg_file;
component latch is
port ( d : in dlx_word;
q : out dlx_word;
latch_en : in std_logic );
end component latch;
component ir_extender is
port ( d : in dlx_word;
q : out dlx_word;
immed_size_26 : in std_logic;
immed_unsigned : in std_logic;
immed_en : in std_logic );
end component ir_extender;
component reg_multiple_out is
generic ( num_outputs : positive );
port ( d : in dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs) );
end component reg_multiple_out;
component reg_multiple_plus_one_out is
generic ( num_outputs : positive );
port ( d : in dlx_word;
q0 : out dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs) );
end component reg_multiple_plus_one_out;
component reg_multiple_plus_one_out_reset is
generic ( num_outputs : positive );
port ( d : in dlx_word;
q0 : out dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs);
reset : in std_logic );
end component reg_multiple_plus_one_out_reset;
component mux2 is
port ( i0, i1 : in dlx_word;
y : out dlx_word;
sel : in std_logic);
end component mux2;
component controller is
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
width : out dlx_mem_width;
write_enable : out std_logic;
mem_enable : out std_logic;
ifetch : out std_logic;
ready : in std_logic;
alu_in_latch_en : out std_logic;
alu_function : out alu_func;
alu_zero, alu_negative, alu_overflow : in std_logic;
reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr;
reg_write : out std_logic;
c_latch_en : out std_logic;
a_latch_en, a_out_en : out std_logic;
b_latch_en, b_out_en : out std_logic;
temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic;
iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic;
pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic;
mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic;
mem_addr_mux_sel : out std_logic;
mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic;
mdr_mux_sel : out std_logic;
ir_latch_en : out std_logic;
ir_immed1_size_26, ir_immed2_size_26 : out std_logic;
ir_immed1_unsigned, ir_immed2_unsigned : out std_logic;
ir_immed1_en, ir_immed2_en : out std_logic;
current_instruction : in dlx_word;
mem_addr : std_logic_vector(1 downto 0);
const1, const2 : out dlx_word );
end component controller;
signal s1_bus, s2_bus : dlx_word;
signal dest_bus : dlx_word;
signal alu_in1, alu_in2 : dlx_word;
signal reg_file_out1, reg_file_out2, reg_file_in : dlx_word;
signal mdr_in : dlx_word;
signal current_instruction : dlx_word;
signal pc_to_mem : dlx_address;
signal mar_to_mem : dlx_address;
signal alu_in_latch_en : std_logic;
signal alu_function : alu_func;
signal alu_zero, alu_negative, alu_overflow : std_logic;
signal reg_s1_addr, reg_s2_addr, reg_dest_addr : reg_file_addr;
signal reg_write : std_logic;
signal a_out_en, a_latch_en : std_logic;
signal b_out_en, b_latch_en : std_logic;
signal c_latch_en : std_logic;
signal temp_out_en1, temp_out_en2, temp_latch_en : std_logic;
signal iar_out_en1, iar_out_en2, iar_latch_en : std_logic;
signal pc_out_en1, pc_out_en2, pc_latch_en : std_logic;
signal mar_out_en1, mar_out_en2, mar_latch_en : std_logic;
signal mem_addr_mux_sel : std_logic;
signal mdr_out_en1, mdr_out_en2, mdr_out_en3, mdr_latch_en : std_logic;
signal mdr_mux_sel : std_logic;
signal ir_latch_en : std_logic;
signal ir_immed1_size_26, ir_immed2_size_26 : std_logic;
signal ir_immed1_unsigned, ir_immed2_unsigned : std_logic;
signal ir_immed1_en, ir_immed2_en : std_logic;
begin
alu_s1_reg : component latch
port map ( d => s1_bus, q => alu_in1, latch_en => alu_in_latch_en );
alu_s2_reg : component latch
port map ( d => s2_bus, q => alu_in2, latch_en => alu_in_latch_en );
the_alu : component alu
port map ( s1 => alu_in1, s2 => alu_in2, result => dest_bus,
func => alu_function,
zero => alu_zero, negative => alu_negative, overflow => alu_overflow );
the_reg_file : component reg_file
port map ( a1 => reg_s1_addr, q1 => reg_file_out1,
a2 => reg_s2_addr, q2 => reg_file_out2,
a3 => reg_dest_addr, d3 => reg_file_in,
write_en => reg_write );
c_reg : component latch
port map ( d => dest_bus, q => reg_file_in, latch_en => c_latch_en );
a_reg : component reg_multiple_out
generic map ( num_outputs => 1 )
port map ( d => reg_file_out1, q(1) => s1_bus,
latch_en => a_latch_en, out_en(1) => a_out_en );
b_reg : component reg_multiple_out
generic map ( num_outputs => 1 )
port map ( d => reg_file_out2, q(1) => s2_bus,
latch_en => b_latch_en, out_en(1) => b_out_en );
temp_reg : component reg_multiple_out
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus,
latch_en => temp_latch_en,
out_en(1) => temp_out_en1, out_en(2) => temp_out_en2 );
iar_reg : component reg_multiple_out
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus,
latch_en => iar_latch_en,
out_en(1) => iar_out_en1, out_en(2) => iar_out_en2 );
pc_reg : component reg_multiple_plus_one_out_reset
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => pc_to_mem,
latch_en => pc_latch_en,
out_en(1) => pc_out_en1, out_en(2) => pc_out_en2,
reset => reset );
mar_reg : component reg_multiple_plus_one_out
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => mar_to_mem,
latch_en => mar_latch_en,
out_en(1) => mar_out_en1, out_en(2) => mar_out_en2 );
mem_addr_mux : component mux2
port map ( i0 => pc_to_mem, i1 => mar_to_mem, y => a,
sel => mem_addr_mux_sel );
mdr_reg : component reg_multiple_out
generic map ( num_outputs => 3 )
port map ( d => mdr_in, q(1) => s1_bus, q(2) => s2_bus, q(3) => d,
latch_en => mdr_latch_en,
out_en(1) => mdr_out_en1, out_en(2) => mdr_out_en2,
out_en(3) => mdr_out_en3 );
mdr_mux : component mux2
port map ( i0 => dest_bus, i1 => d, y => mdr_in,
sel => mdr_mux_sel );
instr_reg : component latch
port map ( d => d, q => current_instruction,
latch_en => ir_latch_en );
ir_extender1 : component ir_extender
port map ( d => current_instruction, q => s1_bus,
immed_size_26 => ir_immed1_size_26,
immed_unsigned => ir_immed1_unsigned,
immed_en => ir_immed1_en );
ir_extender2 : component ir_extender
port map ( d => current_instruction, q => s2_bus,
immed_size_26 => ir_immed2_size_26,
immed_unsigned => ir_immed2_unsigned,
immed_en => ir_immed2_en );
the_controller : component controller
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt,
width => width, write_enable => write_enable, mem_enable => mem_enable,
ifetch => ifetch, ready => ready,
alu_in_latch_en => alu_in_latch_en, alu_function => alu_function,
alu_zero => alu_zero, alu_negative => alu_negative,
alu_overflow => alu_overflow,
reg_s1_addr => reg_s1_addr, reg_s2_addr => reg_s2_addr,
reg_dest_addr => reg_dest_addr, reg_write => reg_write,
c_latch_en => c_latch_en,
a_latch_en => a_latch_en, a_out_en => a_out_en,
b_latch_en => b_latch_en, b_out_en => b_out_en,
temp_latch_en => temp_latch_en,
temp_out_en1 => temp_out_en1, temp_out_en2 => temp_out_en2,
iar_latch_en => iar_latch_en,
iar_out_en1 => iar_out_en1, iar_out_en2 => iar_out_en2,
pc_latch_en => pc_latch_en,
pc_out_en1 => pc_out_en1, pc_out_en2 => pc_out_en2,
mem_addr_mux_sel => mem_addr_mux_sel, mar_latch_en => mar_latch_en,
mar_out_en1 => mar_out_en1, mar_out_en2 => mar_out_en2,
mdr_mux_sel => mdr_mux_sel, mdr_latch_en => mdr_latch_en,
mdr_out_en1 => mdr_out_en1, mdr_out_en2 => mdr_out_en2,
mdr_out_en3 => mdr_out_en3,
ir_latch_en => ir_latch_en,
ir_immed1_size_26 => ir_immed1_size_26,
ir_immed2_size_26 => ir_immed2_size_26,
ir_immed1_unsigned => ir_immed1_unsigned,
ir_immed2_unsigned => ir_immed2_unsigned,
ir_immed1_en => ir_immed1_en, ir_immed2_en => ir_immed2_en,
current_instruction => current_instruction,
mem_addr => mar_to_mem(1 downto 0),
const1 => s1_bus, const2 => s2_bus );
end architecture rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlx-r.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
use work.alu_types.all,
work.reg_file_types.all;
architecture rtl of dlx is
component alu is
port ( s1 : in dlx_word;
s2 : in dlx_word;
result : out dlx_word;
func : in alu_func;
zero, negative, overflow : out std_logic );
end component alu;
component reg_file is
port ( a1 : in reg_file_addr;
q1 : out dlx_word;
a2 : in reg_file_addr;
q2 : out dlx_word;
a3 : in reg_file_addr;
d3 : in dlx_word;
write_en : in std_logic );
end component reg_file;
component latch is
port ( d : in dlx_word;
q : out dlx_word;
latch_en : in std_logic );
end component latch;
component ir_extender is
port ( d : in dlx_word;
q : out dlx_word;
immed_size_26 : in std_logic;
immed_unsigned : in std_logic;
immed_en : in std_logic );
end component ir_extender;
component reg_multiple_out is
generic ( num_outputs : positive );
port ( d : in dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs) );
end component reg_multiple_out;
component reg_multiple_plus_one_out is
generic ( num_outputs : positive );
port ( d : in dlx_word;
q0 : out dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs) );
end component reg_multiple_plus_one_out;
component reg_multiple_plus_one_out_reset is
generic ( num_outputs : positive );
port ( d : in dlx_word;
q0 : out dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs);
reset : in std_logic );
end component reg_multiple_plus_one_out_reset;
component mux2 is
port ( i0, i1 : in dlx_word;
y : out dlx_word;
sel : in std_logic);
end component mux2;
component controller is
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
width : out dlx_mem_width;
write_enable : out std_logic;
mem_enable : out std_logic;
ifetch : out std_logic;
ready : in std_logic;
alu_in_latch_en : out std_logic;
alu_function : out alu_func;
alu_zero, alu_negative, alu_overflow : in std_logic;
reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr;
reg_write : out std_logic;
c_latch_en : out std_logic;
a_latch_en, a_out_en : out std_logic;
b_latch_en, b_out_en : out std_logic;
temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic;
iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic;
pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic;
mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic;
mem_addr_mux_sel : out std_logic;
mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic;
mdr_mux_sel : out std_logic;
ir_latch_en : out std_logic;
ir_immed1_size_26, ir_immed2_size_26 : out std_logic;
ir_immed1_unsigned, ir_immed2_unsigned : out std_logic;
ir_immed1_en, ir_immed2_en : out std_logic;
current_instruction : in dlx_word;
mem_addr : std_logic_vector(1 downto 0);
const1, const2 : out dlx_word );
end component controller;
signal s1_bus, s2_bus : dlx_word;
signal dest_bus : dlx_word;
signal alu_in1, alu_in2 : dlx_word;
signal reg_file_out1, reg_file_out2, reg_file_in : dlx_word;
signal mdr_in : dlx_word;
signal current_instruction : dlx_word;
signal pc_to_mem : dlx_address;
signal mar_to_mem : dlx_address;
signal alu_in_latch_en : std_logic;
signal alu_function : alu_func;
signal alu_zero, alu_negative, alu_overflow : std_logic;
signal reg_s1_addr, reg_s2_addr, reg_dest_addr : reg_file_addr;
signal reg_write : std_logic;
signal a_out_en, a_latch_en : std_logic;
signal b_out_en, b_latch_en : std_logic;
signal c_latch_en : std_logic;
signal temp_out_en1, temp_out_en2, temp_latch_en : std_logic;
signal iar_out_en1, iar_out_en2, iar_latch_en : std_logic;
signal pc_out_en1, pc_out_en2, pc_latch_en : std_logic;
signal mar_out_en1, mar_out_en2, mar_latch_en : std_logic;
signal mem_addr_mux_sel : std_logic;
signal mdr_out_en1, mdr_out_en2, mdr_out_en3, mdr_latch_en : std_logic;
signal mdr_mux_sel : std_logic;
signal ir_latch_en : std_logic;
signal ir_immed1_size_26, ir_immed2_size_26 : std_logic;
signal ir_immed1_unsigned, ir_immed2_unsigned : std_logic;
signal ir_immed1_en, ir_immed2_en : std_logic;
begin
alu_s1_reg : component latch
port map ( d => s1_bus, q => alu_in1, latch_en => alu_in_latch_en );
alu_s2_reg : component latch
port map ( d => s2_bus, q => alu_in2, latch_en => alu_in_latch_en );
the_alu : component alu
port map ( s1 => alu_in1, s2 => alu_in2, result => dest_bus,
func => alu_function,
zero => alu_zero, negative => alu_negative, overflow => alu_overflow );
the_reg_file : component reg_file
port map ( a1 => reg_s1_addr, q1 => reg_file_out1,
a2 => reg_s2_addr, q2 => reg_file_out2,
a3 => reg_dest_addr, d3 => reg_file_in,
write_en => reg_write );
c_reg : component latch
port map ( d => dest_bus, q => reg_file_in, latch_en => c_latch_en );
a_reg : component reg_multiple_out
generic map ( num_outputs => 1 )
port map ( d => reg_file_out1, q(1) => s1_bus,
latch_en => a_latch_en, out_en(1) => a_out_en );
b_reg : component reg_multiple_out
generic map ( num_outputs => 1 )
port map ( d => reg_file_out2, q(1) => s2_bus,
latch_en => b_latch_en, out_en(1) => b_out_en );
temp_reg : component reg_multiple_out
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus,
latch_en => temp_latch_en,
out_en(1) => temp_out_en1, out_en(2) => temp_out_en2 );
iar_reg : component reg_multiple_out
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus,
latch_en => iar_latch_en,
out_en(1) => iar_out_en1, out_en(2) => iar_out_en2 );
pc_reg : component reg_multiple_plus_one_out_reset
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => pc_to_mem,
latch_en => pc_latch_en,
out_en(1) => pc_out_en1, out_en(2) => pc_out_en2,
reset => reset );
mar_reg : component reg_multiple_plus_one_out
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => mar_to_mem,
latch_en => mar_latch_en,
out_en(1) => mar_out_en1, out_en(2) => mar_out_en2 );
mem_addr_mux : component mux2
port map ( i0 => pc_to_mem, i1 => mar_to_mem, y => a,
sel => mem_addr_mux_sel );
mdr_reg : component reg_multiple_out
generic map ( num_outputs => 3 )
port map ( d => mdr_in, q(1) => s1_bus, q(2) => s2_bus, q(3) => d,
latch_en => mdr_latch_en,
out_en(1) => mdr_out_en1, out_en(2) => mdr_out_en2,
out_en(3) => mdr_out_en3 );
mdr_mux : component mux2
port map ( i0 => dest_bus, i1 => d, y => mdr_in,
sel => mdr_mux_sel );
instr_reg : component latch
port map ( d => d, q => current_instruction,
latch_en => ir_latch_en );
ir_extender1 : component ir_extender
port map ( d => current_instruction, q => s1_bus,
immed_size_26 => ir_immed1_size_26,
immed_unsigned => ir_immed1_unsigned,
immed_en => ir_immed1_en );
ir_extender2 : component ir_extender
port map ( d => current_instruction, q => s2_bus,
immed_size_26 => ir_immed2_size_26,
immed_unsigned => ir_immed2_unsigned,
immed_en => ir_immed2_en );
the_controller : component controller
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt,
width => width, write_enable => write_enable, mem_enable => mem_enable,
ifetch => ifetch, ready => ready,
alu_in_latch_en => alu_in_latch_en, alu_function => alu_function,
alu_zero => alu_zero, alu_negative => alu_negative,
alu_overflow => alu_overflow,
reg_s1_addr => reg_s1_addr, reg_s2_addr => reg_s2_addr,
reg_dest_addr => reg_dest_addr, reg_write => reg_write,
c_latch_en => c_latch_en,
a_latch_en => a_latch_en, a_out_en => a_out_en,
b_latch_en => b_latch_en, b_out_en => b_out_en,
temp_latch_en => temp_latch_en,
temp_out_en1 => temp_out_en1, temp_out_en2 => temp_out_en2,
iar_latch_en => iar_latch_en,
iar_out_en1 => iar_out_en1, iar_out_en2 => iar_out_en2,
pc_latch_en => pc_latch_en,
pc_out_en1 => pc_out_en1, pc_out_en2 => pc_out_en2,
mem_addr_mux_sel => mem_addr_mux_sel, mar_latch_en => mar_latch_en,
mar_out_en1 => mar_out_en1, mar_out_en2 => mar_out_en2,
mdr_mux_sel => mdr_mux_sel, mdr_latch_en => mdr_latch_en,
mdr_out_en1 => mdr_out_en1, mdr_out_en2 => mdr_out_en2,
mdr_out_en3 => mdr_out_en3,
ir_latch_en => ir_latch_en,
ir_immed1_size_26 => ir_immed1_size_26,
ir_immed2_size_26 => ir_immed2_size_26,
ir_immed1_unsigned => ir_immed1_unsigned,
ir_immed2_unsigned => ir_immed2_unsigned,
ir_immed1_en => ir_immed1_en, ir_immed2_en => ir_immed2_en,
current_instruction => current_instruction,
mem_addr => mar_to_mem(1 downto 0),
const1 => s1_bus, const2 => s2_bus );
end architecture rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlx-r.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
use work.alu_types.all,
work.reg_file_types.all;
architecture rtl of dlx is
component alu is
port ( s1 : in dlx_word;
s2 : in dlx_word;
result : out dlx_word;
func : in alu_func;
zero, negative, overflow : out std_logic );
end component alu;
component reg_file is
port ( a1 : in reg_file_addr;
q1 : out dlx_word;
a2 : in reg_file_addr;
q2 : out dlx_word;
a3 : in reg_file_addr;
d3 : in dlx_word;
write_en : in std_logic );
end component reg_file;
component latch is
port ( d : in dlx_word;
q : out dlx_word;
latch_en : in std_logic );
end component latch;
component ir_extender is
port ( d : in dlx_word;
q : out dlx_word;
immed_size_26 : in std_logic;
immed_unsigned : in std_logic;
immed_en : in std_logic );
end component ir_extender;
component reg_multiple_out is
generic ( num_outputs : positive );
port ( d : in dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs) );
end component reg_multiple_out;
component reg_multiple_plus_one_out is
generic ( num_outputs : positive );
port ( d : in dlx_word;
q0 : out dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs) );
end component reg_multiple_plus_one_out;
component reg_multiple_plus_one_out_reset is
generic ( num_outputs : positive );
port ( d : in dlx_word;
q0 : out dlx_word;
q : out dlx_word_array(1 to num_outputs);
latch_en : in std_logic;
out_en : in std_logic_vector(1 to num_outputs);
reset : in std_logic );
end component reg_multiple_plus_one_out_reset;
component mux2 is
port ( i0, i1 : in dlx_word;
y : out dlx_word;
sel : in std_logic);
end component mux2;
component controller is
port ( phi1, phi2 : in std_logic;
reset : in std_logic;
halt : out std_logic;
width : out dlx_mem_width;
write_enable : out std_logic;
mem_enable : out std_logic;
ifetch : out std_logic;
ready : in std_logic;
alu_in_latch_en : out std_logic;
alu_function : out alu_func;
alu_zero, alu_negative, alu_overflow : in std_logic;
reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr;
reg_write : out std_logic;
c_latch_en : out std_logic;
a_latch_en, a_out_en : out std_logic;
b_latch_en, b_out_en : out std_logic;
temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic;
iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic;
pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic;
mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic;
mem_addr_mux_sel : out std_logic;
mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic;
mdr_mux_sel : out std_logic;
ir_latch_en : out std_logic;
ir_immed1_size_26, ir_immed2_size_26 : out std_logic;
ir_immed1_unsigned, ir_immed2_unsigned : out std_logic;
ir_immed1_en, ir_immed2_en : out std_logic;
current_instruction : in dlx_word;
mem_addr : std_logic_vector(1 downto 0);
const1, const2 : out dlx_word );
end component controller;
signal s1_bus, s2_bus : dlx_word;
signal dest_bus : dlx_word;
signal alu_in1, alu_in2 : dlx_word;
signal reg_file_out1, reg_file_out2, reg_file_in : dlx_word;
signal mdr_in : dlx_word;
signal current_instruction : dlx_word;
signal pc_to_mem : dlx_address;
signal mar_to_mem : dlx_address;
signal alu_in_latch_en : std_logic;
signal alu_function : alu_func;
signal alu_zero, alu_negative, alu_overflow : std_logic;
signal reg_s1_addr, reg_s2_addr, reg_dest_addr : reg_file_addr;
signal reg_write : std_logic;
signal a_out_en, a_latch_en : std_logic;
signal b_out_en, b_latch_en : std_logic;
signal c_latch_en : std_logic;
signal temp_out_en1, temp_out_en2, temp_latch_en : std_logic;
signal iar_out_en1, iar_out_en2, iar_latch_en : std_logic;
signal pc_out_en1, pc_out_en2, pc_latch_en : std_logic;
signal mar_out_en1, mar_out_en2, mar_latch_en : std_logic;
signal mem_addr_mux_sel : std_logic;
signal mdr_out_en1, mdr_out_en2, mdr_out_en3, mdr_latch_en : std_logic;
signal mdr_mux_sel : std_logic;
signal ir_latch_en : std_logic;
signal ir_immed1_size_26, ir_immed2_size_26 : std_logic;
signal ir_immed1_unsigned, ir_immed2_unsigned : std_logic;
signal ir_immed1_en, ir_immed2_en : std_logic;
begin
alu_s1_reg : component latch
port map ( d => s1_bus, q => alu_in1, latch_en => alu_in_latch_en );
alu_s2_reg : component latch
port map ( d => s2_bus, q => alu_in2, latch_en => alu_in_latch_en );
the_alu : component alu
port map ( s1 => alu_in1, s2 => alu_in2, result => dest_bus,
func => alu_function,
zero => alu_zero, negative => alu_negative, overflow => alu_overflow );
the_reg_file : component reg_file
port map ( a1 => reg_s1_addr, q1 => reg_file_out1,
a2 => reg_s2_addr, q2 => reg_file_out2,
a3 => reg_dest_addr, d3 => reg_file_in,
write_en => reg_write );
c_reg : component latch
port map ( d => dest_bus, q => reg_file_in, latch_en => c_latch_en );
a_reg : component reg_multiple_out
generic map ( num_outputs => 1 )
port map ( d => reg_file_out1, q(1) => s1_bus,
latch_en => a_latch_en, out_en(1) => a_out_en );
b_reg : component reg_multiple_out
generic map ( num_outputs => 1 )
port map ( d => reg_file_out2, q(1) => s2_bus,
latch_en => b_latch_en, out_en(1) => b_out_en );
temp_reg : component reg_multiple_out
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus,
latch_en => temp_latch_en,
out_en(1) => temp_out_en1, out_en(2) => temp_out_en2 );
iar_reg : component reg_multiple_out
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus,
latch_en => iar_latch_en,
out_en(1) => iar_out_en1, out_en(2) => iar_out_en2 );
pc_reg : component reg_multiple_plus_one_out_reset
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => pc_to_mem,
latch_en => pc_latch_en,
out_en(1) => pc_out_en1, out_en(2) => pc_out_en2,
reset => reset );
mar_reg : component reg_multiple_plus_one_out
generic map ( num_outputs => 2 )
port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => mar_to_mem,
latch_en => mar_latch_en,
out_en(1) => mar_out_en1, out_en(2) => mar_out_en2 );
mem_addr_mux : component mux2
port map ( i0 => pc_to_mem, i1 => mar_to_mem, y => a,
sel => mem_addr_mux_sel );
mdr_reg : component reg_multiple_out
generic map ( num_outputs => 3 )
port map ( d => mdr_in, q(1) => s1_bus, q(2) => s2_bus, q(3) => d,
latch_en => mdr_latch_en,
out_en(1) => mdr_out_en1, out_en(2) => mdr_out_en2,
out_en(3) => mdr_out_en3 );
mdr_mux : component mux2
port map ( i0 => dest_bus, i1 => d, y => mdr_in,
sel => mdr_mux_sel );
instr_reg : component latch
port map ( d => d, q => current_instruction,
latch_en => ir_latch_en );
ir_extender1 : component ir_extender
port map ( d => current_instruction, q => s1_bus,
immed_size_26 => ir_immed1_size_26,
immed_unsigned => ir_immed1_unsigned,
immed_en => ir_immed1_en );
ir_extender2 : component ir_extender
port map ( d => current_instruction, q => s2_bus,
immed_size_26 => ir_immed2_size_26,
immed_unsigned => ir_immed2_unsigned,
immed_en => ir_immed2_en );
the_controller : component controller
port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt,
width => width, write_enable => write_enable, mem_enable => mem_enable,
ifetch => ifetch, ready => ready,
alu_in_latch_en => alu_in_latch_en, alu_function => alu_function,
alu_zero => alu_zero, alu_negative => alu_negative,
alu_overflow => alu_overflow,
reg_s1_addr => reg_s1_addr, reg_s2_addr => reg_s2_addr,
reg_dest_addr => reg_dest_addr, reg_write => reg_write,
c_latch_en => c_latch_en,
a_latch_en => a_latch_en, a_out_en => a_out_en,
b_latch_en => b_latch_en, b_out_en => b_out_en,
temp_latch_en => temp_latch_en,
temp_out_en1 => temp_out_en1, temp_out_en2 => temp_out_en2,
iar_latch_en => iar_latch_en,
iar_out_en1 => iar_out_en1, iar_out_en2 => iar_out_en2,
pc_latch_en => pc_latch_en,
pc_out_en1 => pc_out_en1, pc_out_en2 => pc_out_en2,
mem_addr_mux_sel => mem_addr_mux_sel, mar_latch_en => mar_latch_en,
mar_out_en1 => mar_out_en1, mar_out_en2 => mar_out_en2,
mdr_mux_sel => mdr_mux_sel, mdr_latch_en => mdr_latch_en,
mdr_out_en1 => mdr_out_en1, mdr_out_en2 => mdr_out_en2,
mdr_out_en3 => mdr_out_en3,
ir_latch_en => ir_latch_en,
ir_immed1_size_26 => ir_immed1_size_26,
ir_immed2_size_26 => ir_immed2_size_26,
ir_immed1_unsigned => ir_immed1_unsigned,
ir_immed2_unsigned => ir_immed2_unsigned,
ir_immed1_en => ir_immed1_en, ir_immed2_en => ir_immed2_en,
current_instruction => current_instruction,
mem_addr => mar_to_mem(1 downto 0),
const1 => s1_bus, const2 => s2_bus );
end architecture rtl;
|
--************************************************************************************************
-- Component declarations for AVR core
-- Version 2.6A
-- Designed by Ruslan Lepetenok
-- Modified 31.05.2006
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.AVRuCPackage.all;
package AVR_uC_CompPack is
component pport is generic(PPortNum : natural);
port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External connection
portx : out std_logic_vector(7 downto 0);
ddrx : out std_logic_vector(7 downto 0);
pinx : in std_logic_vector(7 downto 0);
irqlines : out std_logic_vector(7 downto 0));
end component;
component external_mux is port (
ramre : in std_logic;
dbus_out : out std_logic_vector (7 downto 0);
ram_data_out : in std_logic_vector (7 downto 0);
io_port_bus : in ext_mux_din_type;
io_port_en_bus : in ext_mux_en_type;
irqack : in std_logic;
irqackad : in std_logic_vector(4 downto 0);
ind_irq_ack : out std_logic_vector(22 downto 0)
);
end component;
component RAMDataReg is port(
ireset : in std_logic;
cp2 : in std_logic;
cpuwait : in std_logic;
RAMDataIn : in std_logic_vector(7 downto 0);
RAMDataOut : out std_logic_vector(7 downto 0)
);
end component;
component Timer_Counter is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
cp2en : in std_logic;
tmr_cp2en : in std_logic;
stopped_mode : in std_logic; -- ??
tmr_running : in std_logic; -- ??
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External inputs/outputs
EXT1 : in std_logic;
EXT2 : in std_logic;
OC0_PWM0 : out std_logic;
OC1A_PWM1A : out std_logic;
OC1B_PWM1B : out std_logic;
OC2_PWM2 : out std_logic;
-- Interrupt related signals
TC0OvfIRQ : out std_logic;
TC0OvfIRQ_Ack : in std_logic;
TC0CmpIRQ : out std_logic;
TC0CmpIRQ_Ack : in std_logic;
TC2OvfIRQ : out std_logic;
TC2OvfIRQ_Ack : in std_logic;
TC2CmpIRQ : out std_logic;
TC2CmpIRQ_Ack : in std_logic;
TC1OvfIRQ : out std_logic;
TC1OvfIRQ_Ack : in std_logic;
TC1CmpAIRQ : out std_logic;
TC1CmpAIRQ_Ack : in std_logic;
TC1CmpBIRQ : out std_logic;
TC1CmpBIRQ_Ack : in std_logic;
TC1ICIRQ : out std_logic;
TC1ICIRQ_Ack : in std_logic;
--Status bits
PWM2bit : out std_logic;
PWM0bit : out std_logic;
PWM10bit : out std_logic;
PWM11bit : out std_logic
);
end component;
COMPONENT ExtIRQ_Controller
PORT(
-- begin Signals required by AVR8 for this core, do not modify.
nReset : in STD_LOGIC;
clk : in STD_LOGIC;
adr : in STD_LOGIC_VECTOR (15 downto 0);
dbus_in : in STD_LOGIC_VECTOR (7 downto 0);
dbus_out : out STD_LOGIC_VECTOR (7 downto 0);
iore : in STD_LOGIC;
iowe : in STD_LOGIC;
out_en : out STD_LOGIC;
-- end Signals required by AVR8 for this core, do not modify.
clken : in STD_LOGIC;
irq_clken : in STD_LOGIC;
extpins : in STD_LOGIC_VECTOR(7 downto 0);
INTx : out STD_LOGIC_VECTOR(7 downto 0)
);
END COMPONENT;
----*************** UART ***************************
--component uart is port(
-- -- AVR Control
-- ireset : in std_logic;
-- cp2 : in std_logic;
-- adr : in std_logic_vector(15 downto 0);
-- dbus_in : in std_logic_vector(7 downto 0);
-- dbus_out : out std_logic_vector(7 downto 0);
-- iore : in std_logic;
-- iowe : in std_logic;
-- out_en : out std_logic;
--
-- --UART
-- rxd : in std_logic;
-- rx_en : out std_logic;
-- txd : out std_logic;
-- tx_en : out std_logic;
--
-- --IRQ
-- txcirq : out std_logic;
-- txc_irqack : in std_logic;
-- udreirq : out std_logic;
-- rxcirq : out std_logic);
--end component;
-- Core itself
component AVR_Core is port(
--Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
-- JTAG OCD support
valid_instr : out std_logic;
insert_nop : in std_logic;
block_irq : in std_logic;
change_flow : out std_logic;
-- Program Memory
pc : out std_logic_vector (15 downto 0);
inst : in std_logic_vector (15 downto 0);
-- I/O control
adr : out std_logic_vector (15 downto 0);
iore : out std_logic;
iowe : out std_logic;
-- Data memory control
ramadr : out std_logic_vector (15 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic;
-- Data paths
dbusin : in std_logic_vector (7 downto 0);
dbusout : out std_logic_vector (7 downto 0);
-- Interrupt
irqlines : in std_logic_vector (22 downto 0);
irqack : out std_logic;
irqackad : out std_logic_vector(4 downto 0);
--Sleep Control
sleepi : out std_logic;
irqok : out std_logic;
globint : out std_logic;
--Watchdog
wdri : out std_logic);
end component;
-- Reset generator
component ResetGenerator is port(
-- Clock inputs
cp2 : in std_logic;
cp64m : in std_logic;
-- Reset inputs
nrst : in std_logic;
npwrrst : in std_logic;
wdovf : in std_logic;
jtagrst : in std_logic;
-- Reset outputs
nrst_cp2 : out std_logic;
nrst_cp64m : out std_logic;
nrst_clksw : out std_logic
);
end component;
-- Components for the simulation only
component PROM is port(
address_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0));
end component;
component DataRAM is
generic(RAMSize :positive);
port (
cp2 : in std_logic;
address : in std_logic_vector (LOG2(RAMSize)-1 downto 0);
ramwe : in std_logic;
din : in std_logic_vector (7 downto 0);
dout : out std_logic_vector (7 downto 0));
end component;
component CPUWaitGenerator is port(
ireset : in std_logic;
cp2 : in std_logic;
ramre : in std_logic;
ramwe : in std_logic;
cpuwait : out std_logic
);
end component;
component ClockSwitch is port(
-- Reset
ireset : in std_logic;
-- Clock input and output
cp2_In : in std_logic;
cp2_Out : out std_logic;
-- Control inputs
sleepi : in std_logic;
irqok : in std_logic;
globint : in std_logic;
sleep_en : in std_logic
);
end component;
-- JTAG
component JTAGOCDPrgTop is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
-- JTAG related inputs/outputs
TRSTn : in std_logic; -- Optional
TMS : in std_logic;
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TDO_OE : out std_logic;
-- From the core
PC : in std_logic_vector(15 downto 0);
-- To the PM("Flash")
pm_adr : out std_logic_vector(15 downto 0);
pm_h_we : out std_logic;
pm_l_we : out std_logic;
pm_dout : in std_logic_vector(15 downto 0);
pm_din : out std_logic_vector(15 downto 0);
-- To the "EEPROM"
EEPrgSel : out std_logic;
EEAdr : out std_logic_vector(11 downto 0);
EEWrData : out std_logic_vector(7 downto 0);
EERdData : in std_logic_vector(7 downto 0);
EEWr : out std_logic;
-- CPU reset
jtag_rst : out std_logic
);
end component;
component uart is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- UART
rxd : in std_logic;
rx_en : out std_logic;
txd : out std_logic;
tx_en : out std_logic;
-- IRQ
txcirq : out std_logic;
txc_irqack : in std_logic;
udreirq : out std_logic;
rxcirq : out std_logic
);
end component;
-- SMBus
--component SMBusMod is port(
-- -- AVR Control
-- ireset : in std_logic;
-- cp2 : in std_logic;
-- adr : in std_logic_vector(15 downto 0);
-- dbus_in : in std_logic_vector(7 downto 0);
-- dbus_out : out std_logic_vector(7 downto 0);
-- iore : in std_logic;
-- iowe : in std_logic;
-- out_en : out std_logic;
-- -- Slave IRQ
-- twiirq : out std_logic;
-- -- Master IRQ
-- msmbirq : out std_logic;
-- -- "Off state" timer IRQ
-- offstirq : out std_logic;
-- offstirq_ack : in std_logic;
-- -- TRI control and data for the slave channel
-- sdain : in std_logic;
-- sdaout : out std_logic;
-- sdaen : out std_logic;
-- sclin : in std_logic;
-- sclout : out std_logic;
-- sclen : out std_logic;
-- -- TRI control and data for the master channel
-- msdain : in std_logic;
-- msdaout : out std_logic;
-- msdaen : out std_logic;
-- msclin : in std_logic;
-- msclout : out std_logic;
-- msclen : out std_logic
-- );
--
--end component;
component FrqDiv is port(
clk_in : in std_logic;
clk_out : out std_logic
);
end component;
end AVR_uC_CompPack;
|
--************************************************************************************************
-- Component declarations for AVR core
-- Version 2.6A
-- Designed by Ruslan Lepetenok
-- Modified 31.05.2006
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.AVRuCPackage.all;
package AVR_uC_CompPack is
component pport is generic(PPortNum : natural);
port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External connection
portx : out std_logic_vector(7 downto 0);
ddrx : out std_logic_vector(7 downto 0);
pinx : in std_logic_vector(7 downto 0);
irqlines : out std_logic_vector(7 downto 0));
end component;
component external_mux is port (
ramre : in std_logic;
dbus_out : out std_logic_vector (7 downto 0);
ram_data_out : in std_logic_vector (7 downto 0);
io_port_bus : in ext_mux_din_type;
io_port_en_bus : in ext_mux_en_type;
irqack : in std_logic;
irqackad : in std_logic_vector(4 downto 0);
ind_irq_ack : out std_logic_vector(22 downto 0)
);
end component;
component RAMDataReg is port(
ireset : in std_logic;
cp2 : in std_logic;
cpuwait : in std_logic;
RAMDataIn : in std_logic_vector(7 downto 0);
RAMDataOut : out std_logic_vector(7 downto 0)
);
end component;
component Timer_Counter is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
cp2en : in std_logic;
tmr_cp2en : in std_logic;
stopped_mode : in std_logic; -- ??
tmr_running : in std_logic; -- ??
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External inputs/outputs
EXT1 : in std_logic;
EXT2 : in std_logic;
OC0_PWM0 : out std_logic;
OC1A_PWM1A : out std_logic;
OC1B_PWM1B : out std_logic;
OC2_PWM2 : out std_logic;
-- Interrupt related signals
TC0OvfIRQ : out std_logic;
TC0OvfIRQ_Ack : in std_logic;
TC0CmpIRQ : out std_logic;
TC0CmpIRQ_Ack : in std_logic;
TC2OvfIRQ : out std_logic;
TC2OvfIRQ_Ack : in std_logic;
TC2CmpIRQ : out std_logic;
TC2CmpIRQ_Ack : in std_logic;
TC1OvfIRQ : out std_logic;
TC1OvfIRQ_Ack : in std_logic;
TC1CmpAIRQ : out std_logic;
TC1CmpAIRQ_Ack : in std_logic;
TC1CmpBIRQ : out std_logic;
TC1CmpBIRQ_Ack : in std_logic;
TC1ICIRQ : out std_logic;
TC1ICIRQ_Ack : in std_logic;
--Status bits
PWM2bit : out std_logic;
PWM0bit : out std_logic;
PWM10bit : out std_logic;
PWM11bit : out std_logic
);
end component;
COMPONENT ExtIRQ_Controller
PORT(
-- begin Signals required by AVR8 for this core, do not modify.
nReset : in STD_LOGIC;
clk : in STD_LOGIC;
adr : in STD_LOGIC_VECTOR (15 downto 0);
dbus_in : in STD_LOGIC_VECTOR (7 downto 0);
dbus_out : out STD_LOGIC_VECTOR (7 downto 0);
iore : in STD_LOGIC;
iowe : in STD_LOGIC;
out_en : out STD_LOGIC;
-- end Signals required by AVR8 for this core, do not modify.
clken : in STD_LOGIC;
irq_clken : in STD_LOGIC;
extpins : in STD_LOGIC_VECTOR(7 downto 0);
INTx : out STD_LOGIC_VECTOR(7 downto 0)
);
END COMPONENT;
----*************** UART ***************************
--component uart is port(
-- -- AVR Control
-- ireset : in std_logic;
-- cp2 : in std_logic;
-- adr : in std_logic_vector(15 downto 0);
-- dbus_in : in std_logic_vector(7 downto 0);
-- dbus_out : out std_logic_vector(7 downto 0);
-- iore : in std_logic;
-- iowe : in std_logic;
-- out_en : out std_logic;
--
-- --UART
-- rxd : in std_logic;
-- rx_en : out std_logic;
-- txd : out std_logic;
-- tx_en : out std_logic;
--
-- --IRQ
-- txcirq : out std_logic;
-- txc_irqack : in std_logic;
-- udreirq : out std_logic;
-- rxcirq : out std_logic);
--end component;
-- Core itself
component AVR_Core is port(
--Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
-- JTAG OCD support
valid_instr : out std_logic;
insert_nop : in std_logic;
block_irq : in std_logic;
change_flow : out std_logic;
-- Program Memory
pc : out std_logic_vector (15 downto 0);
inst : in std_logic_vector (15 downto 0);
-- I/O control
adr : out std_logic_vector (15 downto 0);
iore : out std_logic;
iowe : out std_logic;
-- Data memory control
ramadr : out std_logic_vector (15 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic;
-- Data paths
dbusin : in std_logic_vector (7 downto 0);
dbusout : out std_logic_vector (7 downto 0);
-- Interrupt
irqlines : in std_logic_vector (22 downto 0);
irqack : out std_logic;
irqackad : out std_logic_vector(4 downto 0);
--Sleep Control
sleepi : out std_logic;
irqok : out std_logic;
globint : out std_logic;
--Watchdog
wdri : out std_logic);
end component;
-- Reset generator
component ResetGenerator is port(
-- Clock inputs
cp2 : in std_logic;
cp64m : in std_logic;
-- Reset inputs
nrst : in std_logic;
npwrrst : in std_logic;
wdovf : in std_logic;
jtagrst : in std_logic;
-- Reset outputs
nrst_cp2 : out std_logic;
nrst_cp64m : out std_logic;
nrst_clksw : out std_logic
);
end component;
-- Components for the simulation only
component PROM is port(
address_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0));
end component;
component DataRAM is
generic(RAMSize :positive);
port (
cp2 : in std_logic;
address : in std_logic_vector (LOG2(RAMSize)-1 downto 0);
ramwe : in std_logic;
din : in std_logic_vector (7 downto 0);
dout : out std_logic_vector (7 downto 0));
end component;
component CPUWaitGenerator is port(
ireset : in std_logic;
cp2 : in std_logic;
ramre : in std_logic;
ramwe : in std_logic;
cpuwait : out std_logic
);
end component;
component ClockSwitch is port(
-- Reset
ireset : in std_logic;
-- Clock input and output
cp2_In : in std_logic;
cp2_Out : out std_logic;
-- Control inputs
sleepi : in std_logic;
irqok : in std_logic;
globint : in std_logic;
sleep_en : in std_logic
);
end component;
-- JTAG
component JTAGOCDPrgTop is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
-- JTAG related inputs/outputs
TRSTn : in std_logic; -- Optional
TMS : in std_logic;
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TDO_OE : out std_logic;
-- From the core
PC : in std_logic_vector(15 downto 0);
-- To the PM("Flash")
pm_adr : out std_logic_vector(15 downto 0);
pm_h_we : out std_logic;
pm_l_we : out std_logic;
pm_dout : in std_logic_vector(15 downto 0);
pm_din : out std_logic_vector(15 downto 0);
-- To the "EEPROM"
EEPrgSel : out std_logic;
EEAdr : out std_logic_vector(11 downto 0);
EEWrData : out std_logic_vector(7 downto 0);
EERdData : in std_logic_vector(7 downto 0);
EEWr : out std_logic;
-- CPU reset
jtag_rst : out std_logic
);
end component;
component uart is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- UART
rxd : in std_logic;
rx_en : out std_logic;
txd : out std_logic;
tx_en : out std_logic;
-- IRQ
txcirq : out std_logic;
txc_irqack : in std_logic;
udreirq : out std_logic;
rxcirq : out std_logic
);
end component;
-- SMBus
--component SMBusMod is port(
-- -- AVR Control
-- ireset : in std_logic;
-- cp2 : in std_logic;
-- adr : in std_logic_vector(15 downto 0);
-- dbus_in : in std_logic_vector(7 downto 0);
-- dbus_out : out std_logic_vector(7 downto 0);
-- iore : in std_logic;
-- iowe : in std_logic;
-- out_en : out std_logic;
-- -- Slave IRQ
-- twiirq : out std_logic;
-- -- Master IRQ
-- msmbirq : out std_logic;
-- -- "Off state" timer IRQ
-- offstirq : out std_logic;
-- offstirq_ack : in std_logic;
-- -- TRI control and data for the slave channel
-- sdain : in std_logic;
-- sdaout : out std_logic;
-- sdaen : out std_logic;
-- sclin : in std_logic;
-- sclout : out std_logic;
-- sclen : out std_logic;
-- -- TRI control and data for the master channel
-- msdain : in std_logic;
-- msdaout : out std_logic;
-- msdaen : out std_logic;
-- msclin : in std_logic;
-- msclout : out std_logic;
-- msclen : out std_logic
-- );
--
--end component;
component FrqDiv is port(
clk_in : in std_logic;
clk_out : out std_logic
);
end component;
end AVR_uC_CompPack;
|
--************************************************************************************************
-- Component declarations for AVR core
-- Version 2.6A
-- Designed by Ruslan Lepetenok
-- Modified 31.05.2006
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.AVRuCPackage.all;
package AVR_uC_CompPack is
component pport is generic(PPortNum : natural);
port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External connection
portx : out std_logic_vector(7 downto 0);
ddrx : out std_logic_vector(7 downto 0);
pinx : in std_logic_vector(7 downto 0);
irqlines : out std_logic_vector(7 downto 0));
end component;
component external_mux is port (
ramre : in std_logic;
dbus_out : out std_logic_vector (7 downto 0);
ram_data_out : in std_logic_vector (7 downto 0);
io_port_bus : in ext_mux_din_type;
io_port_en_bus : in ext_mux_en_type;
irqack : in std_logic;
irqackad : in std_logic_vector(4 downto 0);
ind_irq_ack : out std_logic_vector(22 downto 0)
);
end component;
component RAMDataReg is port(
ireset : in std_logic;
cp2 : in std_logic;
cpuwait : in std_logic;
RAMDataIn : in std_logic_vector(7 downto 0);
RAMDataOut : out std_logic_vector(7 downto 0)
);
end component;
component Timer_Counter is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
cp2en : in std_logic;
tmr_cp2en : in std_logic;
stopped_mode : in std_logic; -- ??
tmr_running : in std_logic; -- ??
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External inputs/outputs
EXT1 : in std_logic;
EXT2 : in std_logic;
OC0_PWM0 : out std_logic;
OC1A_PWM1A : out std_logic;
OC1B_PWM1B : out std_logic;
OC2_PWM2 : out std_logic;
-- Interrupt related signals
TC0OvfIRQ : out std_logic;
TC0OvfIRQ_Ack : in std_logic;
TC0CmpIRQ : out std_logic;
TC0CmpIRQ_Ack : in std_logic;
TC2OvfIRQ : out std_logic;
TC2OvfIRQ_Ack : in std_logic;
TC2CmpIRQ : out std_logic;
TC2CmpIRQ_Ack : in std_logic;
TC1OvfIRQ : out std_logic;
TC1OvfIRQ_Ack : in std_logic;
TC1CmpAIRQ : out std_logic;
TC1CmpAIRQ_Ack : in std_logic;
TC1CmpBIRQ : out std_logic;
TC1CmpBIRQ_Ack : in std_logic;
TC1ICIRQ : out std_logic;
TC1ICIRQ_Ack : in std_logic;
--Status bits
PWM2bit : out std_logic;
PWM0bit : out std_logic;
PWM10bit : out std_logic;
PWM11bit : out std_logic
);
end component;
COMPONENT ExtIRQ_Controller
PORT(
-- begin Signals required by AVR8 for this core, do not modify.
nReset : in STD_LOGIC;
clk : in STD_LOGIC;
adr : in STD_LOGIC_VECTOR (15 downto 0);
dbus_in : in STD_LOGIC_VECTOR (7 downto 0);
dbus_out : out STD_LOGIC_VECTOR (7 downto 0);
iore : in STD_LOGIC;
iowe : in STD_LOGIC;
out_en : out STD_LOGIC;
-- end Signals required by AVR8 for this core, do not modify.
clken : in STD_LOGIC;
irq_clken : in STD_LOGIC;
extpins : in STD_LOGIC_VECTOR(7 downto 0);
INTx : out STD_LOGIC_VECTOR(7 downto 0)
);
END COMPONENT;
----*************** UART ***************************
--component uart is port(
-- -- AVR Control
-- ireset : in std_logic;
-- cp2 : in std_logic;
-- adr : in std_logic_vector(15 downto 0);
-- dbus_in : in std_logic_vector(7 downto 0);
-- dbus_out : out std_logic_vector(7 downto 0);
-- iore : in std_logic;
-- iowe : in std_logic;
-- out_en : out std_logic;
--
-- --UART
-- rxd : in std_logic;
-- rx_en : out std_logic;
-- txd : out std_logic;
-- tx_en : out std_logic;
--
-- --IRQ
-- txcirq : out std_logic;
-- txc_irqack : in std_logic;
-- udreirq : out std_logic;
-- rxcirq : out std_logic);
--end component;
-- Core itself
component AVR_Core is port(
--Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
-- JTAG OCD support
valid_instr : out std_logic;
insert_nop : in std_logic;
block_irq : in std_logic;
change_flow : out std_logic;
-- Program Memory
pc : out std_logic_vector (15 downto 0);
inst : in std_logic_vector (15 downto 0);
-- I/O control
adr : out std_logic_vector (15 downto 0);
iore : out std_logic;
iowe : out std_logic;
-- Data memory control
ramadr : out std_logic_vector (15 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic;
-- Data paths
dbusin : in std_logic_vector (7 downto 0);
dbusout : out std_logic_vector (7 downto 0);
-- Interrupt
irqlines : in std_logic_vector (22 downto 0);
irqack : out std_logic;
irqackad : out std_logic_vector(4 downto 0);
--Sleep Control
sleepi : out std_logic;
irqok : out std_logic;
globint : out std_logic;
--Watchdog
wdri : out std_logic);
end component;
-- Reset generator
component ResetGenerator is port(
-- Clock inputs
cp2 : in std_logic;
cp64m : in std_logic;
-- Reset inputs
nrst : in std_logic;
npwrrst : in std_logic;
wdovf : in std_logic;
jtagrst : in std_logic;
-- Reset outputs
nrst_cp2 : out std_logic;
nrst_cp64m : out std_logic;
nrst_clksw : out std_logic
);
end component;
-- Components for the simulation only
component PROM is port(
address_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0));
end component;
component DataRAM is
generic(RAMSize :positive);
port (
cp2 : in std_logic;
address : in std_logic_vector (LOG2(RAMSize)-1 downto 0);
ramwe : in std_logic;
din : in std_logic_vector (7 downto 0);
dout : out std_logic_vector (7 downto 0));
end component;
component CPUWaitGenerator is port(
ireset : in std_logic;
cp2 : in std_logic;
ramre : in std_logic;
ramwe : in std_logic;
cpuwait : out std_logic
);
end component;
component ClockSwitch is port(
-- Reset
ireset : in std_logic;
-- Clock input and output
cp2_In : in std_logic;
cp2_Out : out std_logic;
-- Control inputs
sleepi : in std_logic;
irqok : in std_logic;
globint : in std_logic;
sleep_en : in std_logic
);
end component;
-- JTAG
component JTAGOCDPrgTop is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
-- JTAG related inputs/outputs
TRSTn : in std_logic; -- Optional
TMS : in std_logic;
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TDO_OE : out std_logic;
-- From the core
PC : in std_logic_vector(15 downto 0);
-- To the PM("Flash")
pm_adr : out std_logic_vector(15 downto 0);
pm_h_we : out std_logic;
pm_l_we : out std_logic;
pm_dout : in std_logic_vector(15 downto 0);
pm_din : out std_logic_vector(15 downto 0);
-- To the "EEPROM"
EEPrgSel : out std_logic;
EEAdr : out std_logic_vector(11 downto 0);
EEWrData : out std_logic_vector(7 downto 0);
EERdData : in std_logic_vector(7 downto 0);
EEWr : out std_logic;
-- CPU reset
jtag_rst : out std_logic
);
end component;
component uart is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- UART
rxd : in std_logic;
rx_en : out std_logic;
txd : out std_logic;
tx_en : out std_logic;
-- IRQ
txcirq : out std_logic;
txc_irqack : in std_logic;
udreirq : out std_logic;
rxcirq : out std_logic
);
end component;
-- SMBus
--component SMBusMod is port(
-- -- AVR Control
-- ireset : in std_logic;
-- cp2 : in std_logic;
-- adr : in std_logic_vector(15 downto 0);
-- dbus_in : in std_logic_vector(7 downto 0);
-- dbus_out : out std_logic_vector(7 downto 0);
-- iore : in std_logic;
-- iowe : in std_logic;
-- out_en : out std_logic;
-- -- Slave IRQ
-- twiirq : out std_logic;
-- -- Master IRQ
-- msmbirq : out std_logic;
-- -- "Off state" timer IRQ
-- offstirq : out std_logic;
-- offstirq_ack : in std_logic;
-- -- TRI control and data for the slave channel
-- sdain : in std_logic;
-- sdaout : out std_logic;
-- sdaen : out std_logic;
-- sclin : in std_logic;
-- sclout : out std_logic;
-- sclen : out std_logic;
-- -- TRI control and data for the master channel
-- msdain : in std_logic;
-- msdaout : out std_logic;
-- msdaen : out std_logic;
-- msclin : in std_logic;
-- msclout : out std_logic;
-- msclen : out std_logic
-- );
--
--end component;
component FrqDiv is port(
clk_in : in std_logic;
clk_out : out std_logic
);
end component;
end AVR_uC_CompPack;
|
--************************************************************************************************
-- Component declarations for AVR core
-- Version 2.6A
-- Designed by Ruslan Lepetenok
-- Modified 31.05.2006
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.AVRuCPackage.all;
package AVR_uC_CompPack is
component pport is generic(PPortNum : natural);
port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External connection
portx : out std_logic_vector(7 downto 0);
ddrx : out std_logic_vector(7 downto 0);
pinx : in std_logic_vector(7 downto 0);
irqlines : out std_logic_vector(7 downto 0));
end component;
component external_mux is port (
ramre : in std_logic;
dbus_out : out std_logic_vector (7 downto 0);
ram_data_out : in std_logic_vector (7 downto 0);
io_port_bus : in ext_mux_din_type;
io_port_en_bus : in ext_mux_en_type;
irqack : in std_logic;
irqackad : in std_logic_vector(4 downto 0);
ind_irq_ack : out std_logic_vector(22 downto 0)
);
end component;
component RAMDataReg is port(
ireset : in std_logic;
cp2 : in std_logic;
cpuwait : in std_logic;
RAMDataIn : in std_logic_vector(7 downto 0);
RAMDataOut : out std_logic_vector(7 downto 0)
);
end component;
component Timer_Counter is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
cp2en : in std_logic;
tmr_cp2en : in std_logic;
stopped_mode : in std_logic; -- ??
tmr_running : in std_logic; -- ??
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- External inputs/outputs
EXT1 : in std_logic;
EXT2 : in std_logic;
OC0_PWM0 : out std_logic;
OC1A_PWM1A : out std_logic;
OC1B_PWM1B : out std_logic;
OC2_PWM2 : out std_logic;
-- Interrupt related signals
TC0OvfIRQ : out std_logic;
TC0OvfIRQ_Ack : in std_logic;
TC0CmpIRQ : out std_logic;
TC0CmpIRQ_Ack : in std_logic;
TC2OvfIRQ : out std_logic;
TC2OvfIRQ_Ack : in std_logic;
TC2CmpIRQ : out std_logic;
TC2CmpIRQ_Ack : in std_logic;
TC1OvfIRQ : out std_logic;
TC1OvfIRQ_Ack : in std_logic;
TC1CmpAIRQ : out std_logic;
TC1CmpAIRQ_Ack : in std_logic;
TC1CmpBIRQ : out std_logic;
TC1CmpBIRQ_Ack : in std_logic;
TC1ICIRQ : out std_logic;
TC1ICIRQ_Ack : in std_logic;
--Status bits
PWM2bit : out std_logic;
PWM0bit : out std_logic;
PWM10bit : out std_logic;
PWM11bit : out std_logic
);
end component;
COMPONENT ExtIRQ_Controller
PORT(
-- begin Signals required by AVR8 for this core, do not modify.
nReset : in STD_LOGIC;
clk : in STD_LOGIC;
adr : in STD_LOGIC_VECTOR (15 downto 0);
dbus_in : in STD_LOGIC_VECTOR (7 downto 0);
dbus_out : out STD_LOGIC_VECTOR (7 downto 0);
iore : in STD_LOGIC;
iowe : in STD_LOGIC;
out_en : out STD_LOGIC;
-- end Signals required by AVR8 for this core, do not modify.
clken : in STD_LOGIC;
irq_clken : in STD_LOGIC;
extpins : in STD_LOGIC_VECTOR(7 downto 0);
INTx : out STD_LOGIC_VECTOR(7 downto 0)
);
END COMPONENT;
----*************** UART ***************************
--component uart is port(
-- -- AVR Control
-- ireset : in std_logic;
-- cp2 : in std_logic;
-- adr : in std_logic_vector(15 downto 0);
-- dbus_in : in std_logic_vector(7 downto 0);
-- dbus_out : out std_logic_vector(7 downto 0);
-- iore : in std_logic;
-- iowe : in std_logic;
-- out_en : out std_logic;
--
-- --UART
-- rxd : in std_logic;
-- rx_en : out std_logic;
-- txd : out std_logic;
-- tx_en : out std_logic;
--
-- --IRQ
-- txcirq : out std_logic;
-- txc_irqack : in std_logic;
-- udreirq : out std_logic;
-- rxcirq : out std_logic);
--end component;
-- Core itself
component AVR_Core is port(
--Clock and reset
cp2 : in std_logic;
cp2en : in std_logic;
ireset : in std_logic;
-- JTAG OCD support
valid_instr : out std_logic;
insert_nop : in std_logic;
block_irq : in std_logic;
change_flow : out std_logic;
-- Program Memory
pc : out std_logic_vector (15 downto 0);
inst : in std_logic_vector (15 downto 0);
-- I/O control
adr : out std_logic_vector (15 downto 0);
iore : out std_logic;
iowe : out std_logic;
-- Data memory control
ramadr : out std_logic_vector (15 downto 0);
ramre : out std_logic;
ramwe : out std_logic;
cpuwait : in std_logic;
-- Data paths
dbusin : in std_logic_vector (7 downto 0);
dbusout : out std_logic_vector (7 downto 0);
-- Interrupt
irqlines : in std_logic_vector (22 downto 0);
irqack : out std_logic;
irqackad : out std_logic_vector(4 downto 0);
--Sleep Control
sleepi : out std_logic;
irqok : out std_logic;
globint : out std_logic;
--Watchdog
wdri : out std_logic);
end component;
-- Reset generator
component ResetGenerator is port(
-- Clock inputs
cp2 : in std_logic;
cp64m : in std_logic;
-- Reset inputs
nrst : in std_logic;
npwrrst : in std_logic;
wdovf : in std_logic;
jtagrst : in std_logic;
-- Reset outputs
nrst_cp2 : out std_logic;
nrst_cp64m : out std_logic;
nrst_clksw : out std_logic
);
end component;
-- Components for the simulation only
component PROM is port(
address_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0));
end component;
component DataRAM is
generic(RAMSize :positive);
port (
cp2 : in std_logic;
address : in std_logic_vector (LOG2(RAMSize)-1 downto 0);
ramwe : in std_logic;
din : in std_logic_vector (7 downto 0);
dout : out std_logic_vector (7 downto 0));
end component;
component CPUWaitGenerator is port(
ireset : in std_logic;
cp2 : in std_logic;
ramre : in std_logic;
ramwe : in std_logic;
cpuwait : out std_logic
);
end component;
component ClockSwitch is port(
-- Reset
ireset : in std_logic;
-- Clock input and output
cp2_In : in std_logic;
cp2_Out : out std_logic;
-- Control inputs
sleepi : in std_logic;
irqok : in std_logic;
globint : in std_logic;
sleep_en : in std_logic
);
end component;
-- JTAG
component JTAGOCDPrgTop is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
-- JTAG related inputs/outputs
TRSTn : in std_logic; -- Optional
TMS : in std_logic;
TCK : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TDO_OE : out std_logic;
-- From the core
PC : in std_logic_vector(15 downto 0);
-- To the PM("Flash")
pm_adr : out std_logic_vector(15 downto 0);
pm_h_we : out std_logic;
pm_l_we : out std_logic;
pm_dout : in std_logic_vector(15 downto 0);
pm_din : out std_logic_vector(15 downto 0);
-- To the "EEPROM"
EEPrgSel : out std_logic;
EEAdr : out std_logic_vector(11 downto 0);
EEWrData : out std_logic_vector(7 downto 0);
EERdData : in std_logic_vector(7 downto 0);
EEWr : out std_logic;
-- CPU reset
jtag_rst : out std_logic
);
end component;
component uart is port(
-- AVR Control
ireset : in std_logic;
cp2 : in std_logic;
adr : in std_logic_vector(15 downto 0);
dbus_in : in std_logic_vector(7 downto 0);
dbus_out : out std_logic_vector(7 downto 0);
iore : in std_logic;
iowe : in std_logic;
out_en : out std_logic;
-- UART
rxd : in std_logic;
rx_en : out std_logic;
txd : out std_logic;
tx_en : out std_logic;
-- IRQ
txcirq : out std_logic;
txc_irqack : in std_logic;
udreirq : out std_logic;
rxcirq : out std_logic
);
end component;
-- SMBus
--component SMBusMod is port(
-- -- AVR Control
-- ireset : in std_logic;
-- cp2 : in std_logic;
-- adr : in std_logic_vector(15 downto 0);
-- dbus_in : in std_logic_vector(7 downto 0);
-- dbus_out : out std_logic_vector(7 downto 0);
-- iore : in std_logic;
-- iowe : in std_logic;
-- out_en : out std_logic;
-- -- Slave IRQ
-- twiirq : out std_logic;
-- -- Master IRQ
-- msmbirq : out std_logic;
-- -- "Off state" timer IRQ
-- offstirq : out std_logic;
-- offstirq_ack : in std_logic;
-- -- TRI control and data for the slave channel
-- sdain : in std_logic;
-- sdaout : out std_logic;
-- sdaen : out std_logic;
-- sclin : in std_logic;
-- sclout : out std_logic;
-- sclen : out std_logic;
-- -- TRI control and data for the master channel
-- msdain : in std_logic;
-- msdaout : out std_logic;
-- msdaen : out std_logic;
-- msclin : in std_logic;
-- msclout : out std_logic;
-- msclen : out std_logic
-- );
--
--end component;
component FrqDiv is port(
clk_in : in std_logic;
clk_out : out std_logic
);
end component;
end AVR_uC_CompPack;
|
-- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auk_dspip_lib_pkg_hpfir.all;
use work.auk_dspip_math_pkg_hpfir.all;
entity FIR_0002_ast is
generic (
INWIDTH : integer := 13;
FULL_WIDTH : integer := 30;
BANKINWIDTH : integer := 3;
REM_LSB_BIT_g : integer := 0;
REM_LSB_TYPE_g : string := "Truncation";
REM_MSB_BIT_g : integer := 0;
REM_MSB_TYPE_g : string := "Truncation";
PHYSCHANIN : integer := 1;
PHYSCHANOUT : integer := 1;
CHANSPERPHYIN : natural := 1;
CHANSPERPHYOUT : natural := 1;
OUTPUTFIFODEPTH : integer := 8;
USE_PACKETS : integer := 0;
ENABLE_BACKPRESSURE : boolean := false;
LOG2_CHANSPERPHYOUT : natural := log2_ceil_one(1);
NUMCHANS : integer := 1;
DEVICE_FAMILY : string := "Cyclone II"
);
port(
clk : in std_logic;
reset_n : in std_logic;
ast_sink_ready : out std_logic;
ast_source_data : out std_logic_vector((FULL_WIDTH - REM_LSB_BIT_g - REM_MSB_BIT_g) * PHYSCHANOUT - 1 downto 0);
ast_sink_data : in std_logic_vector( (INWIDTH + BANKINWIDTH) * PHYSCHANIN - 1 downto 0);
ast_sink_valid : in std_logic;
ast_source_valid : out std_logic;
ast_source_ready : in std_logic;
ast_source_eop : out std_logic;
ast_source_sop : out std_logic;
ast_source_channel : out std_logic_vector (LOG2_CHANSPERPHYOUT - 1 downto 0);
ast_sink_eop : in std_logic;
ast_sink_sop : in std_logic;
ast_sink_error : in std_logic_vector (1 downto 0);
ast_source_error : out std_logic_vector (1 downto 0)
);
attribute altera_attribute : string;
attribute altera_attribute of FIR_0002_ast:entity is "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 10036";
end FIR_0002_ast;
-- Warnings Suppression On
-- altera message_off 10036
architecture struct of FIR_0002_ast is
constant OUTWIDTH : integer := FULL_WIDTH - REM_LSB_BIT_g - REM_MSB_BIT_g;
signal channel_out : std_logic_vector(LOG2_CHANSPERPHYOUT - 1 downto 0);
signal core_channel_out : std_logic_vector(2 -1 downto 0);
signal at_source_channel : std_logic_vector(2 -1 downto 0);
signal sink_packet_error : std_logic_vector(1 downto 0);
signal data_in : std_logic_vector((INWIDTH + BANKINWIDTH) * PHYSCHANIN - 1 downto 0);
signal data_valid : std_logic_vector(0 downto 0);
signal data_out : std_logic_vector(OUTWIDTH * PHYSCHANOUT -1 downto 0);
signal reset_fir : std_logic;
signal sink_ready_ctrl : std_logic;
signal source_packet_error : std_logic_vector(1 downto 0);
signal source_stall : std_logic;
signal source_valid_ctrl : std_logic;
signal stall : std_logic;
signal valid : std_logic;
signal core_valid : std_logic;
signal enable_in : std_logic_vector(0 downto 0);
signal outp_out : std_logic_vector(OUTWIDTH * PHYSCHANOUT - 1 downto 0);
signal outp_blk_valid : std_logic_vector(PHYSCHANOUT - 1 downto 0);
signal core_out : std_logic_vector(FULL_WIDTH * PHYSCHANOUT - 1 downto 0);
signal core_out_valid : std_logic_vector(0 downto 0);
signal core_out_channel : std_logic_vector(7 downto 0);
signal core_out_channel_0 : std_logic_vector(7 downto 0);
component FIR_0002_rtl is
port (
xIn_v : in std_logic_vector(0 downto 0);
xIn_c : in std_logic_vector(7 downto 0);
xIn_0 : in std_logic_vector(13 - 1 downto 0);
bankIn_0 : in std_logic_vector(3 - 1 downto 0);
xOut_v : out std_logic_vector(0 downto 0);
xOut_c : out std_logic_vector(7 downto 0);
xOut_0 : out std_logic_vector(30 - 1 downto 0);
clk : in std_logic;
areset : in std_logic
);
end component FIR_0002_rtl;
begin
sink : auk_dspip_avalon_streaming_sink_hpfir
generic map (
WIDTH_g => (INWIDTH + BANKINWIDTH) * PHYSCHANIN,
DATA_WIDTH => (INWIDTH + BANKINWIDTH),
DATA_PORT_COUNT => PHYSCHANIN,
PACKET_SIZE_g => CHANSPERPHYIN)
port map (
clk => clk,
reset_n => reset_n,
data => data_in,
data_valid => data_valid,
sink_ready_ctrl => sink_ready_ctrl,
packet_error => sink_packet_error,
at_sink_ready => ast_sink_ready,
at_sink_valid => ast_sink_valid,
at_sink_data => ast_sink_data,
at_sink_sop => ast_sink_sop,
at_sink_eop => ast_sink_eop,
at_sink_error => ast_sink_error);
source : auk_dspip_avalon_streaming_source_hpfir
generic map (
WIDTH_g => OUTWIDTH * PHYSCHANOUT,
DATA_WIDTH => OUTWIDTH,
DATA_PORT_COUNT => PHYSCHANOUT,
FIFO_DEPTH_g => OUTPUTFIFODEPTH,
USE_PACKETS => USE_PACKETS,
HAVE_COUNTER_g => false,
PACKET_SIZE_g => CHANSPERPHYOUT,
COUNTER_LIMIT_g => CHANSPERPHYOUT,
ENABLE_BACKPRESSURE_g => ENABLE_BACKPRESSURE)
port map (
clk => clk,
reset_n => reset_n,
data_in => data_out,
data_count => channel_out,
source_valid_ctrl => source_valid_ctrl,
source_stall => source_stall,
packet_error => source_packet_error,
at_source_ready => ast_source_ready,
at_source_valid => ast_source_valid,
at_source_data => ast_source_data,
at_source_channel => ast_source_channel,
at_source_sop => ast_source_sop,
at_source_eop => ast_source_eop,
at_source_error => ast_source_error);
intf_ctrl : auk_dspip_avalon_streaming_controller_hpfir
port map (
clk => clk,
reset_n => reset_n,
sink_packet_error => sink_packet_error,
source_stall => source_stall,
valid => valid,
reset_design => reset_fir,
sink_ready_ctrl => sink_ready_ctrl,
source_packet_error => source_packet_error,
source_valid_ctrl => source_valid_ctrl,
stall => stall);
hpfircore: FIR_0002_rtl
port map (
xIn_v => data_valid,
xIn_c => "00000000",
xIn_0 => data_in((3 + 13) * 0 + 13 - 1 downto (3 + 13) * 0),
bankIn_0 => data_in((3 + 13) * 0 + (3 + 13) - 1 downto (3 + 13) * 0 + 13),
xOut_v => core_out_valid,
xOut_c => core_out_channel,
xOut_0 => core_out(30 * 0 + 30 - 1 downto 30 * 0),
clk => clk,
areset => reset_fir
);
gen_outp_blk : for i in PHYSCHANOUT-1 downto 0 generate
begin
outp_blk : auk_dspip_roundsat_hpfir
generic map (
IN_WIDTH_g => FULL_WIDTH ,
REM_LSB_BIT_g => REM_LSB_BIT_g ,
REM_LSB_TYPE_g => REM_LSB_TYPE_g ,
REM_MSB_BIT_g => REM_MSB_BIT_g ,
REM_MSB_TYPE_g => REM_MSB_TYPE_g
)
port map (
clk => clk,
reset_n => reset_n,
enable => core_out_valid(0),
datain => core_out(((i*FULL_WIDTH)+FULL_WIDTH-1) downto (i*FULL_WIDTH)),
valid => outp_blk_valid(i),
dataout => outp_out(((i*OUTWIDTH)+OUTWIDTH-1) downto (i*OUTWIDTH))
);
end generate gen_outp_blk;
multi_data_out: for m in PHYSCHANOUT-1 downto 0 generate
data_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH)) <= outp_out(((m*OUTWIDTH)+OUTWIDTH-1) downto (m*OUTWIDTH));
end generate multi_data_out;
channel_pipe_lsb: if REM_LSB_TYPE_g = "Rounding" and REM_LSB_BIT_g > 0 generate
begin
out_lsb_p : process (clk, reset_n)
begin
if reset_n = '0' then
core_out_channel_0 <= (others => '0');
elsif rising_edge(clk) then
core_out_channel_0 <= core_out_channel;
end if;
end process out_lsb_p;
end generate channel_pipe_lsb;
channel_wire_lsb: if REM_LSB_TYPE_g = "Truncation" or REM_LSB_BIT_g = 0 generate
begin
core_out_channel_0 <= core_out_channel;
end generate channel_wire_lsb;
channel_pipe_msb: if REM_MSB_TYPE_g = "Saturating" and REM_MSB_BIT_g > 0 generate
begin
out_p : process (clk, reset_n)
begin
if reset_n = '0' then
channel_out <= (others => '0');
elsif rising_edge(clk) then
channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0);
end if;
end process out_p;
end generate channel_pipe_msb;
channel_wire_msb: if REM_MSB_TYPE_g = "Truncation" or REM_MSB_BIT_g = 0 generate
begin
channel_out <= core_out_channel_0(LOG2_CHANSPERPHYOUT-1 downto 0);
end generate channel_wire_msb;
valid <= outp_blk_valid(0);
enable_in(0) <= not stall;
end struct;
|
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___400.000______0.000______50.0______189.203____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to400_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to400_pll;
architecture xilinx of clk_32to400_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to400_pll,clk_wiz_v3_6,{component_name=clk_32to400_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___400.000______0.000______50.0______189.203____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to400_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to400_pll;
architecture xilinx of clk_32to400_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to400_pll,clk_wiz_v3_6,{component_name=clk_32to400_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___400.000______0.000______50.0______189.203____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to400_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to400_pll;
architecture xilinx of clk_32to400_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to400_pll,clk_wiz_v3_6,{component_name=clk_32to400_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___400.000______0.000______50.0______189.203____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to400_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to400_pll;
architecture xilinx of clk_32to400_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to400_pll,clk_wiz_v3_6,{component_name=clk_32to400_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___400.000______0.000______50.0______189.203____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to400_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to400_pll;
architecture xilinx of clk_32to400_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to400_pll,clk_wiz_v3_6,{component_name=clk_32to400_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___400.000______0.000______50.0______189.203____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to400_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to400_pll;
architecture xilinx of clk_32to400_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to400_pll,clk_wiz_v3_6,{component_name=clk_32to400_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___400.000______0.000______50.0______189.203____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to400_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to400_pll;
architecture xilinx of clk_32to400_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to400_pll,clk_wiz_v3_6,{component_name=clk_32to400_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___400.000______0.000______50.0______189.203____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to400_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to400_pll;
architecture xilinx of clk_32to400_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to400_pll,clk_wiz_v3_6,{component_name=clk_32to400_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___400.000______0.000______50.0______189.203____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to400_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to400_pll;
architecture xilinx of clk_32to400_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to400_pll,clk_wiz_v3_6,{component_name=clk_32to400_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___400.000______0.000______50.0______189.203____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to400_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to400_pll;
architecture xilinx of clk_32to400_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to400_pll,clk_wiz_v3_6,{component_name=clk_32to400_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___400.000______0.000______50.0______189.203____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to400_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to400_pll;
architecture xilinx of clk_32to400_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to400_pll,clk_wiz_v3_6,{component_name=clk_32to400_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___400.000______0.000______50.0______189.203____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to400_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to400_pll;
architecture xilinx of clk_32to400_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to400_pll,clk_wiz_v3_6,{component_name=clk_32to400_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
-- file: clk_32to400_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___400.000______0.000______50.0______189.203____196.077
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_32to400_pll is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end clk_32to400_pll;
architecture xilinx of clk_32to400_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_32to400_pll,clk_wiz_v3_6,{component_name=clk_32to400_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1 <= CLK_IN1;
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
CLK_OUT1 <= clkout0;
end xilinx;
|
library verilog;
use verilog.vl_types.all;
entity quanta_vlg_check_tst is
port(
hex0 : in vl_logic_vector(6 downto 0);
hex1 : in vl_logic_vector(6 downto 0);
hex2 : in vl_logic_vector(6 downto 0);
hex3 : in vl_logic_vector(6 downto 0);
hex4 : in vl_logic_vector(6 downto 0);
hex5 : in vl_logic_vector(6 downto 0);
hex6 : in vl_logic_vector(6 downto 0);
hex7 : in vl_logic_vector(6 downto 0);
pc : in vl_logic_vector(31 downto 0);
sampler_rx : in vl_logic
);
end quanta_vlg_check_tst;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
function pulled_up ( drivers : bit_vector ) return bit is
begin
for index in drivers'range loop
if drivers(index) = '0' then
return '0';
end if;
end loop;
return '1';
end function pulled_up;
type state_type is (init_state, state1, state2, state3);
type state_vector is array (integer range <>) of state_type;
function resolve_state ( drivers : state_vector ) return state_type is
begin
return drivers(drivers'left);
end function resolve_state;
-- code from book:
signal interrupt_request : pulled_up bit bus;
signal stored_state : resolve_state state_type register := init_state;
-- end of code from book
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
function pulled_up ( drivers : bit_vector ) return bit is
begin
for index in drivers'range loop
if drivers(index) = '0' then
return '0';
end if;
end loop;
return '1';
end function pulled_up;
type state_type is (init_state, state1, state2, state3);
type state_vector is array (integer range <>) of state_type;
function resolve_state ( drivers : state_vector ) return state_type is
begin
return drivers(drivers'left);
end function resolve_state;
-- code from book:
signal interrupt_request : pulled_up bit bus;
signal stored_state : resolve_state state_type register := init_state;
-- end of code from book
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_01 is
end entity inline_01;
----------------------------------------------------------------
architecture test of inline_01 is
function pulled_up ( drivers : bit_vector ) return bit is
begin
for index in drivers'range loop
if drivers(index) = '0' then
return '0';
end if;
end loop;
return '1';
end function pulled_up;
type state_type is (init_state, state1, state2, state3);
type state_vector is array (integer range <>) of state_type;
function resolve_state ( drivers : state_vector ) return state_type is
begin
return drivers(drivers'left);
end function resolve_state;
-- code from book:
signal interrupt_request : pulled_up bit bus;
signal stored_state : resolve_state state_type register := init_state;
-- end of code from book
begin
end architecture test;
|
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
-----------------------------------------------------------------------------
-- --
-- Description: Declares utility package for Altera IP support --
-- --
-- --
-- *** USER DESIGNS SHOULD NOT INCLUDE THIS PACKAGE DIRECTLY *** --
-- --
------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
--
-- These routines are used to help SOPC Builder generate VHDL code.
--
-- ----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
package altera_europa_support_lib is
attribute IS_SIGNED : BOOLEAN ;
attribute SYNTHESIS_RETURN : STRING ;
FUNCTION and_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
FUNCTION nand_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
FUNCTION or_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
FUNCTION nor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
FUNCTION xor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
FUNCTION xnor_reduce(arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
FUNCTION A_SRL(arg: std_logic_vector; shift: integer) RETURN std_logic_vector;
FUNCTION A_SLL(arg: std_logic_vector; shift: integer) RETURN std_logic_vector;
FUNCTION A_SRL(arg: std_logic_vector; shift: std_logic_vector) RETURN std_logic_vector;
FUNCTION A_SLL(arg: std_logic_vector; shift: std_logic_vector) RETURN std_logic_vector;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic) RETURN std_logic_vector;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic_vector) RETURN std_logic_vector;
FUNCTION A_WE_StdLogic (select_arg: boolean; then_arg: STD_LOGIC ; else_arg:STD_LOGIC) RETURN STD_LOGIC;
FUNCTION A_WE_StdUlogic (select_arg: boolean; then_arg: STD_ULOGIC; else_arg:STD_ULOGIC) RETURN STD_ULOGIC;
FUNCTION A_WE_StdLogicVector(select_arg: boolean; then_arg: STD_LOGIC_VECTOR; else_arg:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
FUNCTION A_WE_StdUlogicVector(select_arg: boolean; then_arg: STD_ULOGIC_VECTOR; else_arg:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR;
FUNCTION Vector_To_Std_Logic(vector: STD_LOGIC_VECTOR) return Std_Logic;
function TO_STD_LOGIC(arg : BOOLEAN) return STD_LOGIC;
-- Result subtype: STD_LOGIC
-- Result: Converts a BOOLEAN to a STD_LOGIC..
FUNCTION a_rep(arg : STD_LOGIC; repeat : INTEGER) RETURN STD_LOGIC_VECTOR ;
FUNCTION a_rep_vector(arg : STD_LOGIC_VECTOR; repeat : INTEGER) RETURN STD_LOGIC_VECTOR ;
function a_min(L, R: INTEGER) return INTEGER ;
function a_max(L, R: INTEGER) return INTEGER ;
FUNCTION a_ext (arg : STD_LOGIC_VECTOR; size : INTEGER) RETURN STD_LOGIC_VECTOR ;
-------------------------------------------------------
-- Conversions for Verilog $display/$write emulation --
-------------------------------------------------------
-- All required padding is to the left of the value (right justified) to
-- a string that can hold the maximum value of the vector in that radix.
-- When displaying decimal values (e.g. %d), padding is spaces.
-- When displaying other radices (e.g. %h), padding is zeros.
-- There is no padding when a zero is placed after the % (e.g. %0d or %0h).
type pad_type is (pad_none, pad_spaces, pad_zeros);
function to_hex_string(val : std_logic_vector;
pad : pad_type := pad_zeros) return string;
function to_decimal_string(val : integer;
pad : pad_type := pad_spaces) return string;
function to_decimal_string(val : std_logic_vector;
pad : pad_type := pad_spaces) return string;
function to_octal_string(val : std_logic_vector;
pad : pad_type := pad_zeros) return string;
function to_binary_string(val : std_logic_vector;
pad : pad_type := pad_zeros) return string;
function to_hex_string(val : std_logic;
pad : pad_type := pad_zeros) return string;
function to_decimal_string(val : std_logic;
pad : pad_type := pad_spaces) return string;
function to_octal_string(val : std_logic;
pad : pad_type := pad_zeros) return string;
function to_binary_string(val : std_logic;
pad : pad_type := pad_zeros) return string;
end altera_europa_support_lib;
package body altera_europa_support_lib is
--
-- Reducing logical functions.
--
FUNCTION and_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
-- Exemplar synthesis directive attributes for this function
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_AND" ;
BEGIN
result := '1';
FOR i IN arg'RANGE LOOP
result := result AND arg(i);
END LOOP;
RETURN result;
END;
FUNCTION nand_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_NAND" ;
BEGIN
result := NOT and_reduce(arg);
RETURN result;
END;
FUNCTION or_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
-- Exemplar synthesis directive attributes for this function
ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_OR" ;
BEGIN
result := '0';
FOR i IN arg'RANGE LOOP
result := result OR arg(i);
END LOOP;
RETURN result;
END;
FUNCTION nor_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_NOR" ;
BEGIN
result := NOT or_reduce(arg);
RETURN result;
END;
FUNCTION xor_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
-- Exemplar synthesis directive attributes for this function
ATTRIBUTE synthesis_return OF result:VARIABLE IS "REDUCE_XOR" ;
BEGIN
result := '0';
FOR i IN arg'RANGE LOOP
result := result XOR arg(i);
END LOOP;
RETURN result;
END;
FUNCTION xnor_reduce(arg: STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result: STD_LOGIC;
ATTRIBUTE synthesis_RETURN OF result:VARIABLE IS "REDUCE_XNOR" ;
BEGIN
result := NOT xor_reduce(arg);
RETURN result;
END;
function TO_STD_LOGIC(arg : BOOLEAN) return STD_LOGIC is
begin
if(arg = true) then
return('1');
else
return('0');
end if;
end;
FUNCTION A_SRL(arg : STD_LOGIC_VECTOR; shift : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN(A_SRL(arg,conv_integer(shift)));
END;
FUNCTION A_SLL(arg : STD_LOGIC_VECTOR; shift : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN(A_SLL(arg,conv_integer(shift)));
END;
FUNCTION A_SRL(arg : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR(arg'LEFT DOWNTO 0) := (arg'RANGE => '0');
BEGIN
IF ((shift <= arg'LEFT) AND (shift >= 0)) THEN
IF (shift = 0) THEN
result := arg;
ELSE
result(arg'LEFT - shift DOWNTO 0) := arg(arg'LEFT DOWNTO shift);
END IF;
END IF;
RETURN(result);
END;
FUNCTION A_SLL(arg : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR(arg'LEFT DOWNTO 0) := (arg'RANGE => '0');
BEGIN
IF ((shift <= arg'LEFT) AND (shift >= 0)) THEN
IF (shift = 0) THEN
result := arg;
ELSE
result(arg'LEFT DOWNTO shift) := arg(arg'LEFT - shift DOWNTO 0);
END IF;
END IF;
RETURN(result);
END;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic) RETURN std_logic_vector IS
BEGIN
IF a = '1' THEN
return "1";
ELSE
return "0";
END IF;
END;
FUNCTION A_TOSTDLOGICVECTOR(a: std_logic_vector) RETURN std_logic_vector IS
BEGIN
return a;
END;
FUNCTION A_WE_StdLogic (select_arg: boolean; then_arg: STD_LOGIC ; else_arg:STD_LOGIC) RETURN STD_LOGIC IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION A_WE_StdUlogic (select_arg: boolean; then_arg: STD_ULOGIC; else_arg:STD_ULOGIC) RETURN STD_ULOGIC IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION A_WE_StdLogicVector(select_arg: boolean; then_arg: STD_LOGIC_VECTOR; else_arg:STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION A_WE_StdUlogicVector(select_arg: boolean; then_arg: STD_ULOGIC_VECTOR; else_arg:STD_ULOGIC_VECTOR) RETURN STD_ULOGIC_VECTOR IS
BEGIN
IF (select_arg) THEN
return (then_arg);
ELSE
return (else_arg);
END IF;
END;
FUNCTION Vector_To_Std_Logic(vector: STD_LOGIC_VECTOR)
return Std_Logic IS
BEGIN
return (vector(vector'right));
END;
FUNCTION a_rep(arg : STD_LOGIC; repeat : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE result : STD_LOGIC_VECTOR(repeat-1 DOWNTO 0) := (others => '0');
VARIABLE i : integer := 0;
BEGIN
FOR i IN 0 TO (repeat-1) LOOP
result(i) := arg;
end LOOP;
RETURN(result);
END;
FUNCTION a_rep_vector(arg : STD_LOGIC_VECTOR; repeat : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE arg_copy : STD_LOGIC_VECTOR ((arg'length - 1)DOWNTO 0) := arg ;
VARIABLE result : STD_LOGIC_VECTOR(((repeat * (arg_copy'LEFT+1))-1) DOWNTO 0) := (others => '0');
VARIABLE i : integer := 0;
BEGIN
FOR i IN 0 TO (repeat-1) LOOP
result((((arg_copy'left + 1) * i) + arg_copy'left) downto ((arg_copy'left + 1) * i)) := arg_copy(arg_copy'LEFT DOWNTO 0);
end LOOP;
RETURN(result);
END;
-- a_min : return the minimum of two integers;
function a_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- a_max : return the minimum of two integers;
function a_max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
-- a_ext is the Altera version of the EXT function. It is used to both
-- zero-extend a signal to a new length, and to extract a signal of 'size'
-- length from a larger signal.
FUNCTION a_ext (arg : STD_LOGIC_VECTOR; size : INTEGER) RETURN STD_LOGIC_VECTOR IS
VARIABLE arg_copy : STD_LOGIC_VECTOR ((arg'length - 1)DOWNTO 0) := arg ;
VARIABLE result : STD_LOGIC_VECTOR((size-1) DOWNTO 0) := (others => '0');
VARIABLE i : integer := 0;
VARIABLE bits_to_copy : integer := 0;
VARIABLE arg_length : integer := arg'length ;
VARIABLE LSB_bit : integer := 0;
BEGIN
bits_to_copy := a_min(arg_length, size);
FOR i IN 0 TO (bits_to_copy - 1) LOOP
result(i) := arg_copy(i);
end LOOP;
RETURN(result);
END;
-------------------------------------------------------
-- Conversions for Verilog $display/$write emulation --
-------------------------------------------------------
subtype slv4 is std_logic_vector(1 to 4);
subtype slv3 is std_logic_vector(1 to 3);
-- Remove leading zeros. Also changes strings of all 'x' or 'z' to one char.
-- This handles the %0<radix> kind of Verilog syntax in the format string.
-- Examples:
-- input output
-- ----- -----------
-- 001f 1f
-- 0000 0
-- xxxx x
-- zzzz z
-- xxzz xxzz
function do_pad_none(
str_in : string) return string is
variable start : integer;
variable all_x : boolean := true;
variable all_z : boolean := true;
begin
-- Nothing to remove if string isn't at least two characters long.
if (str_in'length < 2) then
return str_in;
end if;
for i in str_in'range loop
case str_in(i) is
when 'X' | 'x' => all_z := false;
when 'Z' | 'z' => all_x := false;
when others => all_x := false; all_z := false;
end case;
end loop;
if (all_x or all_z) then
return str_in(str_in'left to str_in'left);
end if;
-- Find index of first non-zero character.
for i in str_in'range loop
start := i;
exit when (str_in(i) /= '0');
end loop;
return str_in(start to str_in'right);
end do_pad_none;
-- Replace leading zeros with spaces.
-- This handles the %d kind of Verilog syntax in the format string.
function replace_leading_zeros(
str_in : string;
c : character) return string is
variable str_out : string(str_in'range) := str_in;
begin
-- Nothing to replace if string isn't at least two characters long.
if (str_in'length < 2) then
return str_in;
end if;
for i in str_in'range loop
if (str_in(i) = '0') then
str_out(i) := c;
else
exit;
end if;
end loop;
return str_out;
end replace_leading_zeros;
function do_pad(
str : string;
pad : pad_type) return string is
begin
case pad is
when pad_none => return do_pad_none(str);
when pad_spaces => return replace_leading_zeros(str, ' ');
when pad_zeros => return str;
end case;
end do_pad;
function round_up_to_multiple(
val : integer;
size : integer) return integer is
begin
return ((val + size - 1) / size) * size;
end round_up_to_multiple;
function to_hex_string(
val : std_logic_vector;
pad : pad_type := pad_zeros) return string is
variable ext_len : integer := round_up_to_multiple(val'length,4);
variable val_ext : std_logic_vector(1 to ext_len) := (others => '0');
variable ptr : integer range 1 to (ext_len/4)+1 := 1;
variable str : string(1 to ext_len/4) := (others=>'0');
variable found_x : boolean := false;
variable found_z : boolean := false;
begin
val_ext(ext_len-val'length+1 to ext_len) := val;
-- Extend MSB to extended sulv unless it starts with one (unsigned).
-- Done to extend 'x' and 'z'.
if ext_len-val'length > 0 and val(val'left) /= '1' then
val_ext(1 to ext_len-val'length) := (others => val(val'left));
end if;
for i in val_ext'range loop
next when i rem 4 /= 1;
case slv4(to_x01z(val_ext(i to i+3))) is
when "0000" => str(ptr) := '0';
when "0001" => str(ptr) := '1';
when "0010" => str(ptr) := '2';
when "0011" => str(ptr) := '3';
when "0100" => str(ptr) := '4';
when "0101" => str(ptr) := '5';
when "0110" => str(ptr) := '6';
when "0111" => str(ptr) := '7';
when "1000" => str(ptr) := '8';
when "1001" => str(ptr) := '9';
when "1010" => str(ptr) := 'a';
when "1011" => str(ptr) := 'b';
when "1100" => str(ptr) := 'c';
when "1101" => str(ptr) := 'd';
when "1110" => str(ptr) := 'e';
when "1111" => str(ptr) := 'f';
when "XXXX" => str(ptr) := 'x';
when "ZZZZ" => str(ptr) := 'z';
when others =>
for j in 0 to 3 loop
case val_ext(i + j) is
when 'X' => found_x := true;
when 'Z' => found_z := true;
when others => null;
end case;
end loop;
if found_x then
str(ptr) := 'X';
elsif found_z then
str(ptr) := 'Z';
else
str(ptr) := 'X';
end if;
end case;
ptr := ptr + 1;
end loop;
return do_pad(str, pad);
end to_hex_string;
function to_decimal_string(
val : integer;
pad : pad_type := pad_spaces) return string is
variable tmp : integer := val;
variable ptr : integer range 1 to 32 := 32;
variable str : string(1 to 32) := (others=>'0');
begin
if val=0 then
return do_pad("0", pad);
else
while tmp > 0 loop
case tmp rem 10 is
when 0 => str(ptr) := '0';
when 1 => str(ptr) := '1';
when 2 => str(ptr) := '2';
when 3 => str(ptr) := '3';
when 4 => str(ptr) := '4';
when 5 => str(ptr) := '5';
when 6 => str(ptr) := '6';
when 7 => str(ptr) := '7';
when 8 => str(ptr) := '8';
when 9 => str(ptr) := '9';
when others => null;
end case;
tmp := tmp / 10;
ptr := ptr - 1;
end loop;
return do_pad(str(ptr+1 to 32), pad);
end if;
end to_decimal_string;
function to_decimal_string(
val : std_logic_vector;
pad : pad_type := pad_spaces) return string is
variable all_x : boolean := true;
variable all_z : boolean := true;
variable some_x : boolean := false;
variable some_z : boolean := false;
variable fixed_str : string(1 to 1);
begin
for i in val'range loop
case to_x01z(val(i)) is
when 'X' => some_x := true; all_z := false;
when 'Z' => some_z := true; all_x := false;
when others => all_x := false; all_z := false;
end case;
end loop;
if (all_x) then
fixed_str(1) := 'x';
return fixed_str;
elsif (all_z) then
fixed_str(1) := 'z';
return fixed_str;
elsif (some_x) then
fixed_str(1) := 'X';
return fixed_str;
elsif (some_z) then
fixed_str(1) := 'Z';
return fixed_str;
else
return to_decimal_string(conv_integer(val), pad);
end if;
end to_decimal_string;
function to_octal_string(
val : std_logic_vector;
pad : pad_type := pad_zeros) return string is
variable ext_len : integer := round_up_to_multiple(val'length,3);
variable val_ext : std_logic_vector(1 to ext_len) := (others => '0');
variable ptr : integer range 1 to (ext_len/3)+1 := 1;
variable str : string(1 to ext_len/3) := (others=>'0');
variable found_x : boolean := false;
variable found_z : boolean := false;
begin
val_ext(ext_len-val'length+1 to ext_len) := val;
-- Extend MSB to extended sulv unless it starts with one (unsigned).
-- Done to extend 'x' and 'z'.
if ext_len-val'length > 0 and val(val'left) /= '1' then
val_ext(1 to ext_len-val'length) := (others => val(val'left));
end if;
for i in val_ext'range loop
next when i rem 3 /= 1;
case slv3(to_x01z(val_ext(i to i+2))) is
when "000" => str(ptr) := '0';
when "001" => str(ptr) := '1';
when "010" => str(ptr) := '2';
when "011" => str(ptr) := '3';
when "100" => str(ptr) := '4';
when "101" => str(ptr) := '5';
when "110" => str(ptr) := '6';
when "111" => str(ptr) := '7';
when "XXX" => str(ptr) := 'x';
when "ZZZ" => str(ptr) := 'z';
when others =>
for j in 0 to 2 loop
case val_ext(i + j) is
when 'X' => found_x := true;
when 'Z' => found_z := true;
when others => null;
end case;
end loop;
if found_x then
str(ptr) := 'X';
elsif found_z then
str(ptr) := 'Z';
else
str(ptr) := 'X';
end if;
end case;
ptr := ptr + 1;
end loop;
return do_pad(str, pad);
end to_octal_string;
function to_hex_string(
val : std_logic;
pad : pad_type := pad_zeros) return string is
begin
return to_binary_string(val, pad);
end to_hex_string;
function to_decimal_string(
val : std_logic;
pad : pad_type := pad_spaces) return string is
begin
return to_binary_string(val, pad);
end to_decimal_string;
function to_octal_string(
val : std_logic;
pad : pad_type := pad_zeros) return string is
begin
return to_binary_string(val, pad);
end to_octal_string;
function to_binary_string(
val : std_logic;
pad : pad_type := pad_zeros) return string is
variable str : string(1 to 1);
begin
case to_x01z(val) is
when '0' => str(1) := '0';
when '1' => str(1) := '1';
when 'X' => str(1) := 'x';
when 'Z' => str(1) := 'z';
when others => str(1) := 'x';
end case;
return do_pad(str, pad);
end to_binary_string;
function to_binary_string(
val : std_logic_vector;
pad : pad_type := pad_zeros) return string is
variable str : string(1 to val'length) := (others=>'0');
variable ptr : integer := str'left;
begin
for i in val'range loop
str(ptr to ptr) := to_binary_string(val(i));
ptr := ptr + 1;
end loop;
return do_pad(str, pad);
end to_binary_string;
end altera_europa_support_lib;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:07:18 05/29/2014
-- Design Name:
-- Module Name: FSM3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FSM3 is
Port (
reset : in std_logic;
clk : in std_logic;
start: in std_logic;
data_in : in std_logic_vector(3 downto 0);
AVAIL : out std_logic;
DONE : out std_logic;
flag : out std_logic_vector(1 downto 0));
end FSM3;
architecture Behavioral of FSM3 is
type tipoestado is (s0, s1, s2, s3, s4, s5, s6);
signal estado : tipoestado;
begin
process(reset, clk)
variable regd : std_logic_vector(3 downto 0);
variable cont : std_logic_vector(6 downto 0);
begin
if reset = '1' then
estado <= s0;
AVAIL <= '1'; done <= '0'; flag <= "00"; regd := "0000"; cont := "0000000";
elsif (clk'event and clk='1') then
CASE estado IS
WHEN s0 =>
AVAIL <= '1'; done <= '0'; flag <= "00"; regd := "0000"; cont := "0000000"; if start='0'then estado
<= s0; else estado <= s1; end if;
WHEN s1 =>
AVAIL <= '0'; done <= '0'; flag <= "00"; regd := data_in; cont := cont+1;
if (regd = "1011" and cont <= "1000100") then estado <= s2;
elsif cont="1100100" then estado <= s4;
else estado <= s1;
end if;
WHEN s2 => -- achou um valor em <=100
AVAIL <= '0'; done <= '1'; flag <= "01"; estado <= s3;
WHEN s3 =>
AVAIL <= '0'; done <= '1'; flag <= "01"; estado <= s0;
WHEN s4 => -- nao achou valor ate 100 dados
AVAIL <= '0'; done <= '1'; flag <= "00"; estado <= s5;
WHEN s5 =>
AVAIL <= '0'; done <= '1'; flag <= "00"; estado <= s0;
WHEN others =>
AVAIL <= '1'; done <= '0'; flag <= "00"; estado <= s0;
end CASE;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bit_xor is
port (
bit1_in: in std_logic := '0';
bit2_in: in std_logic := '0';
result: out std_logic := '0'
);
end;
architecture bit_xor_arq of bit_xor is
begin
process(bit1_in, bit2_in)
begin
result <= bit1_in xor bit2_in;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is
generic (
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
do_send : in std_logic;
clear_crc : in std_logic;
force_ss : in std_logic;
level_ss : in std_logic;
busy : out std_logic;
rate : in std_logic_vector(8 downto 0);
cpol : in std_logic;
cpha : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
crc_out : out std_logic_vector(7 downto 0);
SPI_SSn : out std_logic;
SPI_CLK : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic );
end spi;
architecture gideon of spi is
signal bit_cnt : std_logic_vector(3 downto 0);
signal delay : std_logic_vector(8 downto 0);
type t_state is (idle, transceive, done, gap);
signal state : t_state;
signal shift : std_logic_vector(7 downto 0) := X"FF";
signal crc : std_logic_vector(6 downto 0) := (others => '0');
begin
process(clock)
procedure update_crc(din : std_logic) is
begin
crc(6 downto 1) <= crc(5 downto 0);
crc(0) <= din xor crc(6);
crc(3) <= crc(2) xor din xor crc(6);
end procedure;
variable s : std_logic;
begin
if rising_edge(clock) then
case state is
when idle =>
SPI_SSn <= '1';
SPI_CLK <= cpol;
delay <= rate;
bit_cnt <= "0000";
if do_send='1' then
busy <= '1';
state <= transceive;
SPI_SSn <= '0';
if cpha='0' then -- output first bit immediately
update_crc(wdata(7));
SPI_MOSI <= wdata(7);
shift <= wdata(6 downto 0) & '0';
else -- output first bit upon shift edge
shift <= wdata;
end if;
end if;
when transceive =>
if delay = 0 then
delay <= rate;
bit_cnt <= bit_cnt + 1;
SPI_CLK <= not bit_cnt(0) xor cpol;
s := cpha xor bit_cnt(0);
if s = '0' then
shift(0) <= SPI_MISO;
end if;
if bit_cnt = "1111" then
state <= done;
else
if s = '1' then
update_crc(shift(7));
SPI_MOSI <= shift(7);
shift <= shift(6 downto 0) & '0';
end if;
end if;
else
delay <= delay - 1;
end if;
when done =>
if delay = 0 then
delay <= rate;
rdata <= shift;
SPI_SSn <= '1';
state <= gap;
else
delay <= delay - 1;
end if;
when gap =>
if delay = 0 then
state <= idle;
busy <= '0';
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if clear_crc='1' then
crc <= (others => '0');
end if;
if reset='1' then
state <= idle;
rdata <= X"00";
busy <= '0';
SPI_MOSI <= '1';
crc <= (others => '0');
end if;
if force_ss='1' then
SPI_SSn <= level_ss;
end if;
end if;
end process;
crc_out <= crc & '1' when g_crc else X"00";
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is
generic (
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
do_send : in std_logic;
clear_crc : in std_logic;
force_ss : in std_logic;
level_ss : in std_logic;
busy : out std_logic;
rate : in std_logic_vector(8 downto 0);
cpol : in std_logic;
cpha : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
crc_out : out std_logic_vector(7 downto 0);
SPI_SSn : out std_logic;
SPI_CLK : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic );
end spi;
architecture gideon of spi is
signal bit_cnt : std_logic_vector(3 downto 0);
signal delay : std_logic_vector(8 downto 0);
type t_state is (idle, transceive, done, gap);
signal state : t_state;
signal shift : std_logic_vector(7 downto 0) := X"FF";
signal crc : std_logic_vector(6 downto 0) := (others => '0');
begin
process(clock)
procedure update_crc(din : std_logic) is
begin
crc(6 downto 1) <= crc(5 downto 0);
crc(0) <= din xor crc(6);
crc(3) <= crc(2) xor din xor crc(6);
end procedure;
variable s : std_logic;
begin
if rising_edge(clock) then
case state is
when idle =>
SPI_SSn <= '1';
SPI_CLK <= cpol;
delay <= rate;
bit_cnt <= "0000";
if do_send='1' then
busy <= '1';
state <= transceive;
SPI_SSn <= '0';
if cpha='0' then -- output first bit immediately
update_crc(wdata(7));
SPI_MOSI <= wdata(7);
shift <= wdata(6 downto 0) & '0';
else -- output first bit upon shift edge
shift <= wdata;
end if;
end if;
when transceive =>
if delay = 0 then
delay <= rate;
bit_cnt <= bit_cnt + 1;
SPI_CLK <= not bit_cnt(0) xor cpol;
s := cpha xor bit_cnt(0);
if s = '0' then
shift(0) <= SPI_MISO;
end if;
if bit_cnt = "1111" then
state <= done;
else
if s = '1' then
update_crc(shift(7));
SPI_MOSI <= shift(7);
shift <= shift(6 downto 0) & '0';
end if;
end if;
else
delay <= delay - 1;
end if;
when done =>
if delay = 0 then
delay <= rate;
rdata <= shift;
SPI_SSn <= '1';
state <= gap;
else
delay <= delay - 1;
end if;
when gap =>
if delay = 0 then
state <= idle;
busy <= '0';
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if clear_crc='1' then
crc <= (others => '0');
end if;
if reset='1' then
state <= idle;
rdata <= X"00";
busy <= '0';
SPI_MOSI <= '1';
crc <= (others => '0');
end if;
if force_ss='1' then
SPI_SSn <= level_ss;
end if;
end if;
end process;
crc_out <= crc & '1' when g_crc else X"00";
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is
generic (
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
do_send : in std_logic;
clear_crc : in std_logic;
force_ss : in std_logic;
level_ss : in std_logic;
busy : out std_logic;
rate : in std_logic_vector(8 downto 0);
cpol : in std_logic;
cpha : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
crc_out : out std_logic_vector(7 downto 0);
SPI_SSn : out std_logic;
SPI_CLK : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic );
end spi;
architecture gideon of spi is
signal bit_cnt : std_logic_vector(3 downto 0);
signal delay : std_logic_vector(8 downto 0);
type t_state is (idle, transceive, done, gap);
signal state : t_state;
signal shift : std_logic_vector(7 downto 0) := X"FF";
signal crc : std_logic_vector(6 downto 0) := (others => '0');
begin
process(clock)
procedure update_crc(din : std_logic) is
begin
crc(6 downto 1) <= crc(5 downto 0);
crc(0) <= din xor crc(6);
crc(3) <= crc(2) xor din xor crc(6);
end procedure;
variable s : std_logic;
begin
if rising_edge(clock) then
case state is
when idle =>
SPI_SSn <= '1';
SPI_CLK <= cpol;
delay <= rate;
bit_cnt <= "0000";
if do_send='1' then
busy <= '1';
state <= transceive;
SPI_SSn <= '0';
if cpha='0' then -- output first bit immediately
update_crc(wdata(7));
SPI_MOSI <= wdata(7);
shift <= wdata(6 downto 0) & '0';
else -- output first bit upon shift edge
shift <= wdata;
end if;
end if;
when transceive =>
if delay = 0 then
delay <= rate;
bit_cnt <= bit_cnt + 1;
SPI_CLK <= not bit_cnt(0) xor cpol;
s := cpha xor bit_cnt(0);
if s = '0' then
shift(0) <= SPI_MISO;
end if;
if bit_cnt = "1111" then
state <= done;
else
if s = '1' then
update_crc(shift(7));
SPI_MOSI <= shift(7);
shift <= shift(6 downto 0) & '0';
end if;
end if;
else
delay <= delay - 1;
end if;
when done =>
if delay = 0 then
delay <= rate;
rdata <= shift;
SPI_SSn <= '1';
state <= gap;
else
delay <= delay - 1;
end if;
when gap =>
if delay = 0 then
state <= idle;
busy <= '0';
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if clear_crc='1' then
crc <= (others => '0');
end if;
if reset='1' then
state <= idle;
rdata <= X"00";
busy <= '0';
SPI_MOSI <= '1';
crc <= (others => '0');
end if;
if force_ss='1' then
SPI_SSn <= level_ss;
end if;
end if;
end process;
crc_out <= crc & '1' when g_crc else X"00";
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is
generic (
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
do_send : in std_logic;
clear_crc : in std_logic;
force_ss : in std_logic;
level_ss : in std_logic;
busy : out std_logic;
rate : in std_logic_vector(8 downto 0);
cpol : in std_logic;
cpha : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
crc_out : out std_logic_vector(7 downto 0);
SPI_SSn : out std_logic;
SPI_CLK : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic );
end spi;
architecture gideon of spi is
signal bit_cnt : std_logic_vector(3 downto 0);
signal delay : std_logic_vector(8 downto 0);
type t_state is (idle, transceive, done, gap);
signal state : t_state;
signal shift : std_logic_vector(7 downto 0) := X"FF";
signal crc : std_logic_vector(6 downto 0) := (others => '0');
begin
process(clock)
procedure update_crc(din : std_logic) is
begin
crc(6 downto 1) <= crc(5 downto 0);
crc(0) <= din xor crc(6);
crc(3) <= crc(2) xor din xor crc(6);
end procedure;
variable s : std_logic;
begin
if rising_edge(clock) then
case state is
when idle =>
SPI_SSn <= '1';
SPI_CLK <= cpol;
delay <= rate;
bit_cnt <= "0000";
if do_send='1' then
busy <= '1';
state <= transceive;
SPI_SSn <= '0';
if cpha='0' then -- output first bit immediately
update_crc(wdata(7));
SPI_MOSI <= wdata(7);
shift <= wdata(6 downto 0) & '0';
else -- output first bit upon shift edge
shift <= wdata;
end if;
end if;
when transceive =>
if delay = 0 then
delay <= rate;
bit_cnt <= bit_cnt + 1;
SPI_CLK <= not bit_cnt(0) xor cpol;
s := cpha xor bit_cnt(0);
if s = '0' then
shift(0) <= SPI_MISO;
end if;
if bit_cnt = "1111" then
state <= done;
else
if s = '1' then
update_crc(shift(7));
SPI_MOSI <= shift(7);
shift <= shift(6 downto 0) & '0';
end if;
end if;
else
delay <= delay - 1;
end if;
when done =>
if delay = 0 then
delay <= rate;
rdata <= shift;
SPI_SSn <= '1';
state <= gap;
else
delay <= delay - 1;
end if;
when gap =>
if delay = 0 then
state <= idle;
busy <= '0';
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if clear_crc='1' then
crc <= (others => '0');
end if;
if reset='1' then
state <= idle;
rdata <= X"00";
busy <= '0';
SPI_MOSI <= '1';
crc <= (others => '0');
end if;
if force_ss='1' then
SPI_SSn <= level_ss;
end if;
end if;
end process;
crc_out <= crc & '1' when g_crc else X"00";
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is
generic (
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
do_send : in std_logic;
clear_crc : in std_logic;
force_ss : in std_logic;
level_ss : in std_logic;
busy : out std_logic;
rate : in std_logic_vector(8 downto 0);
cpol : in std_logic;
cpha : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
crc_out : out std_logic_vector(7 downto 0);
SPI_SSn : out std_logic;
SPI_CLK : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic );
end spi;
architecture gideon of spi is
signal bit_cnt : std_logic_vector(3 downto 0);
signal delay : std_logic_vector(8 downto 0);
type t_state is (idle, transceive, done, gap);
signal state : t_state;
signal shift : std_logic_vector(7 downto 0) := X"FF";
signal crc : std_logic_vector(6 downto 0) := (others => '0');
begin
process(clock)
procedure update_crc(din : std_logic) is
begin
crc(6 downto 1) <= crc(5 downto 0);
crc(0) <= din xor crc(6);
crc(3) <= crc(2) xor din xor crc(6);
end procedure;
variable s : std_logic;
begin
if rising_edge(clock) then
case state is
when idle =>
SPI_SSn <= '1';
SPI_CLK <= cpol;
delay <= rate;
bit_cnt <= "0000";
if do_send='1' then
busy <= '1';
state <= transceive;
SPI_SSn <= '0';
if cpha='0' then -- output first bit immediately
update_crc(wdata(7));
SPI_MOSI <= wdata(7);
shift <= wdata(6 downto 0) & '0';
else -- output first bit upon shift edge
shift <= wdata;
end if;
end if;
when transceive =>
if delay = 0 then
delay <= rate;
bit_cnt <= bit_cnt + 1;
SPI_CLK <= not bit_cnt(0) xor cpol;
s := cpha xor bit_cnt(0);
if s = '0' then
shift(0) <= SPI_MISO;
end if;
if bit_cnt = "1111" then
state <= done;
else
if s = '1' then
update_crc(shift(7));
SPI_MOSI <= shift(7);
shift <= shift(6 downto 0) & '0';
end if;
end if;
else
delay <= delay - 1;
end if;
when done =>
if delay = 0 then
delay <= rate;
rdata <= shift;
SPI_SSn <= '1';
state <= gap;
else
delay <= delay - 1;
end if;
when gap =>
if delay = 0 then
state <= idle;
busy <= '0';
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if clear_crc='1' then
crc <= (others => '0');
end if;
if reset='1' then
state <= idle;
rdata <= X"00";
busy <= '0';
SPI_MOSI <= '1';
crc <= (others => '0');
end if;
if force_ss='1' then
SPI_SSn <= level_ss;
end if;
end if;
end process;
crc_out <= crc & '1' when g_crc else X"00";
end gideon;
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Tests the frequency generator.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PhaseGenerator_Tester is
end entity;
architecture stdarch of PhaseGenerator_Tester is
--------------------
-- Constants
--------------------
constant clk_period: time := 10ns;
constant phase_width: natural := 32;
constant sample_width: natural := 32;
constant phase_increment_1: integer := 16#19999999#; -- needs about 10 clock cycles
constant clk_cycles_per_counter_cycle: integer := 10;
--------------------
-- Inputs
--------------------
signal clk: std_logic := '0';
signal phase_increment: unsigned(phase_width-1 downto 0) :=
to_unsigned(phase_increment_1, phase_width);
signal reset_phase: std_logic := '0';
--------------------
-- Outputs
--------------------
signal frequency_signal: std_logic;
signal phase: unsigned (phase_width-1 downto 0);
--------------------
-- Internals
--------------------
signal run_test: boolean := true;
signal phase_reset_test_has_started: boolean := false;
begin
--------------------------------------------------------------------------------
-- Connections to and from internal signals.
--------------------------------------------------------------------------------
-- Just use the phase´s MSB as a frequency signal.
frequency_signal <= phase(phase'high);
--------------------------------------------------------------------------------
-- UUT instantiation.
--------------------------------------------------------------------------------
uut: entity work.PhaseGenerator
generic map
(
phase_width => phase_width
)
port map
(
clk => clk,
phase_increment => phase_increment,
reset_phase => reset_phase,
phase => phase
);
--------------------------------------------------------------------------------
-- UUT stimulation.
--------------------------------------------------------------------------------
-- Generates the system clock.
clk <= not clk after clk_period/2 when run_test;
-- Stimulates and controls the UUT and the tests at all.
stimulus: process is
constant signal_cycles_to_test: integer := 10;
begin
-- Do the tests for the specified duration.
wait until rising_edge(frequency_signal);
wait for 2*signal_cycles_to_test * (clk_cycles_per_counter_cycle/2) * clk_period;
phase_reset_test_has_started <= true;
wait for 10*clk_period;
wait until falling_edge(clk);
reset_phase <= '1';
wait until falling_edge(clk);
reset_phase <= '0';
wait for 10*clk_period;
-- Stop the tests.
run_test <= false;
wait;
end process;
--------------------------------------------------------------------------------
-- Specifications.
--------------------------------------------------------------------------------
-- Verifies proper frequency signal generation.
must_create_correct_frequency_signal: process is
variable previous_signal: std_logic;
begin
-- The first signal edge comes rather randomly (depending on the phase
-- increment). Thus synchronize to that signal.
wait until rising_edge(frequency_signal);
if not phase_reset_test_has_started then
-- Verify the correct duration of high and the low phase (i.e. the right
-- frequency and the 50% duty cycle). This test might not work exactly for
-- increments that aren´t a power of two.
wait until falling_edge(clk);
previous_signal := frequency_signal;
for clk_cycle in 1 to (clk_cycles_per_counter_cycle/2)-1 loop
wait until falling_edge(clk);
assert (frequency_signal = previous_signal)
report "Signal not changed or changed unexpectedly."
severity error;
end loop;
end if;
end process;
-- Verifies whether the phase is incremented correctly.
must_increment_phase_per_clk_cycle: process is
variable previous_phase: unsigned (phase_width-1 downto 0) := (others => '0');
begin
wait until falling_edge(clk);
if not phase_reset_test_has_started then
assert (phase = previous_phase + to_unsigned(phase_increment_1, phase_width))
report "Phase not incremented as expected." & integer'image(to_integer(previous_phase))
severity error;
previous_phase := phase;
end if;
end process;
-- Verifies correct phase reset.
must_reset_phase_on_request: process is
begin
wait until rising_edge(clk);
wait until falling_edge(clk);
if reset_phase = '1' then
assert (phase = (phase'range => '0'))
report "Phase not reset as expected."
severity error;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_signal is
generic
(
width : integer := 4
);
port
(
input : in std_logic_vector((width - 1) downto 0);
store, update, clear, clock : in std_logic;
output : out std_logic_vector((width + 1) downto 0)
);
end c_signal;
architecture behavior of c_signal is
begin
P0 : process (clock, store, update, input, clear)
variable In_latch : std_logic_Vector((width - 1) downto 0);
variable Out_latch : std_logic_Vector((width - 1) downto 0);
variable out_var : std_logic_Vector((width - 1) downto 0);
variable sig_stable : std_logic;
variable sig_quiet : std_logic;
begin
if (clock = '1' and not clock'STABLE and store = '1') then
In_latch := Input;
sig_quiet := '0';
end if;
if (clock = '1' and not clock'STABLE and update = '1') then
sig_stable := '1';
L1 : for I in width - 1 downto 0 loop
if not (In_latch(I) = Out_latch(I)) then
sig_stable := '0';
exit L1;
end if;
end loop L1;
Out_latch := In_latch;
output((width - 1) downto 0) <= Out_latch;
output(width) <= sig_stable;
output(width + 1) <= sig_quiet;
sig_quiet := '1';
end if;
if (clear = '1') then
L2 : for I in (width - 1) downto 0 loop
In_latch(I) := '0';
Out_latch(I) := '0';
end loop L2;
output((width - 1) downto 0) <= Out_latch;
output(width) <= '1';
output(width + 1) <= '1';
sig_quiet := '1';
end if;
end process P0;
end behavior; |
package my_package is
type my_type_t is record
state : bit_vector;
aux : bit_vector;
end record my_type_t;
type my_array_t is array (natural range <>) of my_type_t;
end package my_package;
-------------------------------------------------------------------------------
entity record38 is
end entity;
use work.my_package.all;
architecture test of record38 is
function init return my_array_t is
begin
return (0 => (state => "101", aux => "1"), 1 => (state => "1", aux => "1"));
end function;
signal s : my_array_t(0 to 0)(state(1 to 3), aux(1 to 1)) := init;
begin
end architecture;
|
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
ENTITY bcd_adder IS
PORT (b_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
a_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
c_in : IN STD_LOGIC;
c_out : OUT STD_LOGIC;
s_out : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;
END bcd_adder;
ARCHITECTURE Behavior OF bcd_adder IS
signal t: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal z: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal a: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal b: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal c1: STD_LOGIC;
BEGIN
process (a_in, b_in) begin
t <= STD_LOGIC_VECTOR(unsigned(a_in) + unsigned(b_in) + (c_in & ""));
if (t > "1001") then
z <= "1010";
c1 <= '1';
else
z <= "0000";
c1 <= '0';
end if;
s_out <= STD_LOGIC_VECTOR(unsigned(t) - unsigned(z));
c_out <= c1;
end process;
END Behavior; |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY mig_wrap_proc_sys_reset_0_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END mig_wrap_proc_sys_reset_0_0;
ARCHITECTURE mig_wrap_proc_sys_reset_0_0_arch OF mig_wrap_proc_sys_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mig_wrap_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF mig_wrap_proc_sys_reset_0_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF mig_wrap_proc_sys_reset_0_0_arch : ARCHITECTURE IS "mig_wrap_proc_sys_reset_0_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF mig_wrap_proc_sys_reset_0_0_arch: ARCHITECTURE IS "mig_wrap_proc_sys_reset_0_0,proc_sys_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=1,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END mig_wrap_proc_sys_reset_0_0_arch;
|
-- $Id: ibdr_rk11.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_rk11 - syn
-- Description: ibus dev(rem): RK11-A/B
--
-- Dependencies: ram_1swar_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2014-06-08 561 14.7 131013 xc6slx16-2 44 139 9 60 s 5.6
-- 2010-10-17 333 12.1 M53d xc3s1000-4 46 248 16 137 s 7.2
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 46 249 16 148 s 7.1
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 36 189 16 111 s 6.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-22 767 1.3.1 don't init N_REGS (vivado fix for fsm inference)
-- 2015-05-01 672 1.3 BUGFIX: interrupt after dreset,seek command start
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-05-24 219 1.0.9 add CE_MSEC input; inc sector counter every msec
-- BUGFIX: sector counter now counts 000,...,013.
-- 2009-05-21 217 1.0.8 cancel pending interrupt requests when IE=0
-- 2009-05-16 216 1.0.7 BUGFIX: correct interrupt on IE 0->1 logic
-- BUGFIX: re-work the seek complete handling
-- 2008-08-22 161 1.0.6 use iblib
-- 2008-05-30 151 1.0.5 BUGFIX: do control reset locally now, add CRDONE
-- 2008-03-30 131 1.0.4 issue interrupt when IDE bit set with GO=0
-- 2008-02-23 118 1.0.3 remove redundant condition in rkda access code
-- fix bug in control reset logic (we's missing)
-- 2008-01-20 113 1.0.2 Fix busy handling when control reset done
-- 2008-01-20 112 1.0.1 Fix scp handling; use BRESET
-- 2008-01-06 111 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_rk11 is -- ibus dev(rem): RK11
-- fixed address: 177400
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end ibdr_rk11;
architecture syn of ibdr_rk11 is
constant ibaddr_rk11 : slv16 := slv(to_unsigned(8#177400#,16));
constant ibaddr_rkds : slv3 := "000"; -- rkds address offset
constant ibaddr_rker : slv3 := "001"; -- rker address offset
constant ibaddr_rkcs : slv3 := "010"; -- rkcs address offset
constant ibaddr_rkwc : slv3 := "011"; -- rkwc address offset
constant ibaddr_rkba : slv3 := "100"; -- rkba address offset
constant ibaddr_rkda : slv3 := "101"; -- rkda address offset
constant ibaddr_rkmr : slv3 := "110"; -- rkmr address offset
constant ibaddr_rkdb : slv3 := "111"; -- rkdb address offset
subtype rkds_ibf_id is integer range 15 downto 13;
constant rkds_ibf_adry : integer := 6;
constant rkds_ibf_scsa : integer := 4;
subtype rkds_ibf_sc is integer range 3 downto 0;
subtype rker_ibf_he is integer range 15 downto 5;
constant rker_ibf_cse : integer := 1;
constant rker_ibf_wce : integer := 0;
constant rkcs_ibf_err : integer := 15;
constant rkcs_ibf_he : integer := 14;
constant rkcs_ibf_scp : integer := 13;
constant rkcs_ibf_maint : integer := 12;
constant rkcs_ibf_rdy : integer := 7;
constant rkcs_ibf_ide : integer := 6;
subtype rkcs_ibf_mex is integer range 5 downto 4;
subtype rkcs_ibf_func is integer range 3 downto 1;
constant rkcs_ibf_go : integer := 0;
subtype rkda_ibf_drsel is integer range 15 downto 13;
subtype rkmr_ibf_rid is integer range 15 downto 13; -- rem id
constant rkmr_ibf_crdone: integer := 11; -- contr. reset done
constant rkmr_ibf_sbclr : integer := 10; -- clear sbusy's
constant rkmr_ibf_creset: integer := 9; -- control reset
constant rkmr_ibf_fdone : integer := 8; -- func done
subtype rkmr_ibf_sdone is integer range 7 downto 0; -- seek done
constant func_creset : slv3 := "000"; -- func: control reset
constant func_write : slv3 := "001"; -- func: write
constant func_read : slv3 := "010"; -- func: read
constant func_wchk : slv3 := "011"; -- func: write check
constant func_seek : slv3 := "100"; -- func: seek
constant func_rchk : slv3 := "101"; -- func: read check
constant func_dreset : slv3 := "110"; -- func: drive reset
constant func_wlock : slv3 := "111"; -- func: write lock
type state_type is (
s_idle,
s_init
);
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
state : state_type; -- state
id : slv3; -- rkds: drive id of search done
sc : slv4; -- rkds: sector counter
cse : slbit; -- rker: check sum error
wce : slbit; -- rker: write check error
he : slbit; -- rkcs: hard error
scp : slbit; -- rkcs: seek complete
maint : slbit; -- rkcs: maintenance mode
rdy : slbit; -- rkcs: control ready
ide : slbit; -- rkcs: interrupt on done enable
drsel : slv3; -- rkda: currently selected drive
fireq : slbit; -- func done interrupt request flag
sireq : slv8; -- seek done interrupt request flags
sbusy : slv8; -- seek busy flags
rid : slv3; -- drive id for rem ds reads
icnt : slv3; -- init state counter
creset : slbit; -- control reset flag
crdone : slbit; -- control reset done since last fdone
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
s_init, -- state
(others=>'0'), -- id
(others=>'0'), -- sc
'0','0', -- cse, wce
'0','0','0', -- he, scp, maint
'1', -- rdy (SET TO 1)
'0', -- ide
(others=>'0'), -- drsel
'0', -- fireq
(others=>'0'), -- sireq
(others=>'0'), -- sbusy
(others=>'0'), -- rid
(others=>'0'), -- icnt
'0','1' -- creset, crdone
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal MEM_1_WE : slbit := '0';
signal MEM_0_WE : slbit := '0';
signal MEM_ADDR : slv4 := (others=>'0');
signal MEM_DIN : slv16 := (others=>'0');
signal MEM_DOUT : slv16 := (others=>'0');
begin
MEM_1 : ram_1swar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_1_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte1),
DO => MEM_DOUT(ibf_byte1));
MEM_0 : ram_1swar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
port map (
CLK => CLK,
WE => MEM_0_WE,
ADDR => MEM_ADDR,
DI => MEM_DIN(ibf_byte0),
DO => MEM_DOUT(ibf_byte0));
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET='1' or R_REGS.creset='1' then
R_REGS <= regs_init;
if R_REGS.creset = '1' then
R_REGS.sbusy <= N_REGS.sbusy;
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, CE_MSEC, IB_MREQ, MEM_DOUT, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibhold : slbit := '0';
variable icrip : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibrem : slbit := '0';
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ibwrem : slbit := '0';
variable ilam : slbit := '0';
variable iscval : slbit := '0';
variable iscid : slv3 := (others=>'0');
variable iei_req : slbit := '0';
variable imem_we0 : slbit := '0';
variable imem_we1 : slbit := '0';
variable imem_addr : slv4 := (others=>'0');
variable imem_din : slv16 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
ibhold := '0';
icrip := '0';
idout := (others=>'0');
ibrem := IB_MREQ.racc or r.maint;
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ibwrem := IB_MREQ.we and ibrem;
ilam := '0';
iscval := '0';
iscid := (others=>'0');
iei_req := '0';
imem_we0 := '0';
imem_we1 := '0';
imem_addr := '0' & IB_MREQ.addr(3 downto 1);
imem_din := IB_MREQ.din;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval = '1' and
IB_MREQ.addr(12 downto 4)=ibaddr_rk11(12 downto 4) then
n.ibsel := '1';
end if;
-- internal state machine (for control reset)
case r.state is
when s_idle =>
null;
when s_init =>
ibhold := r.ibsel; -- hold ibus when controller busy
icrip := '1';
n.icnt := slv(unsigned(r.icnt) + 1);
if unsigned(r.icnt) = 7 then
n.state := s_idle;
end if;
when others => null;
end case;
-- ibus transactions
if r.ibsel='1' and ibhold='0' then -- selected and not holding
idout := MEM_DOUT;
imem_we0 := ibw0;
imem_we1 := ibw1;
case IB_MREQ.addr(3 downto 1) is
when ibaddr_rkds => -- RKDS -- drive status register ----
if ibrem = '0' then
imem_addr := '1' & r.drsel; -- loc read ds data: drsel as addr.
else
imem_addr := '1' & r.rid; -- rem read ds data: rid as addr.
end if;
idout(rkds_ibf_id) := r.id;
if ibrem = '0' then -- loc ? simulate drive sector monitor
if r.sc = MEM_DOUT(rkds_ibf_sc) then
idout(rkds_ibf_scsa) := '1';
else
idout(rkds_ibf_scsa) := '0';
end if;
idout(rkds_ibf_sc) := r.sc;
end if;
if r.sbusy(to_integer(unsigned(imem_addr(2 downto 0))))='1' then
idout(rkds_ibf_adry) := '0'; -- clear drive access rdy
end if;
if ibwrem = '1' then -- rem write ? than update ds data
imem_addr := '1' & IB_MREQ.din(rkds_ibf_id); -- use id field as addr
else -- loc write ?
imem_we0 := '0'; -- suppress we, is read-only
imem_we1 := '0';
end if;
when ibaddr_rker => -- RKER -- error register ------------
idout(4 downto 2) := (others=>'0'); -- unassigned bits
idout(rker_ibf_cse) := r.cse; -- use state bits (cleared at go !)
idout(rker_ibf_wce) := r.wce;
if ibwrem = '1' then -- rem write ?
if unsigned(IB_MREQ.din(rker_ibf_he)) /= 0 then -- hard errors set ?
n.he := '1';
else
n.he := '0';
end if;
n.cse := IB_MREQ.din(rker_ibf_cse); -- mirror cse bit
n.wce := IB_MREQ.din(rker_ibf_wce); -- mirror wce bit
else -- loc write ?
imem_we0 := '0'; -- suppress we, is read-only
imem_we1 := '0';
end if;
when ibaddr_rkcs => -- RKCS -- control status register ---
idout(rkcs_ibf_err) := r.he or r.cse or r.wce;
idout(rkcs_ibf_he) := r.he;
idout(rkcs_ibf_scp) := r.scp;
idout(rkcs_ibf_rdy) := r.rdy;
idout(rkcs_ibf_go) := not r.rdy;
if ibw1 = '1' then
n.maint := IB_MREQ.din(rkcs_ibf_maint); -- mirror maint bit
end if;
if ibw0 = '1' then
n.ide := IB_MREQ.din(rkcs_ibf_ide); -- mirror ide bit
if n.ide = '0' then -- if IE set to 0
n.fireq := '0'; -- cancel all pending
n.sireq := (others=>'0'); -- interrupt requests
end if;
if IB_MREQ.din(rkcs_ibf_go) = '1' then -- GO=1 ?
if r.rdy = '1' then -- ready and GO ?
n.scp := '0'; -- go clears scp !
n.rdy := '0'; -- mark busy
n.cse := '0'; -- clear soft errors
n.wce := '0';
n.fireq := '0'; -- cancel pend. int
if IB_MREQ.din(rkcs_ibf_func)=func_creset then -- control reset?
n.creset := '1'; -- handle locally
else
ilam := '1'; -- issue lam
end if;
if IB_MREQ.din(rkcs_ibf_func)=func_seek or -- if seek
IB_MREQ.din(rkcs_ibf_func)=func_dreset then -- or drive reset
n.sbusy(to_integer(unsigned(r.drsel))) := '1'; -- drive busy
if n.ide = '1' then -- if enabled
n.fireq := '1'; -- interrupt !
end if;
end if;
end if;
else -- GO=0
if r.ide='0' and n.ide='1' and -- if IDE 0->1 transition
r.rdy='1' then -- and controller ready
n.fireq := '1'; -- issue interrupt
end if;
end if;
end if;
when ibaddr_rkda => -- RKDA -- disk address register -----
if ibrem = '0' then -- loc access ?
if r.rdy = '0' then -- controller busy ?
imem_we0 := '0'; -- suppress write
imem_we1 := '0';
end if;
end if;
if imem_we1 = '1' then
n.drsel := IB_MREQ.din(rkda_ibf_drsel); -- mirror drsel bits
end if;
when ibaddr_rkmr => -- RKMR -- maintenance register ------
idout := (others=>'0');
idout(rkmr_ibf_rid) := r.rid;
idout(rkmr_ibf_crdone) := r.crdone;
idout(rkmr_ibf_sdone) := r.sbusy;
if ibwrem = '1' then -- rem write ?
n.rid := IB_MREQ.din(rkmr_ibf_rid);
if r.ide='1' and IB_MREQ.din(rkmr_ibf_sbclr)='0' then
n.sireq := r.sireq or (IB_MREQ.din(rkmr_ibf_sdone) and r.sbusy);
end if;
n.sbusy := r.sbusy and not IB_MREQ.din(rkmr_ibf_sdone);
if IB_MREQ.din(rkmr_ibf_fdone) = '1' then -- func completed
n.rdy := '1';
n.crdone := '0';
if r.ide = '1' then
n.fireq := '1';
end if;
end if;
if IB_MREQ.din(rkmr_ibf_creset) = '1' then -- control reset
n.creset := '1';
end if;
end if;
when others => -- all other regs
null;
end case;
end if;
iscval := '1';
if r.sireq(7) = '1' then iscid := "111";
elsif r.sireq(6) = '1' then iscid := "110";
elsif r.sireq(5) = '1' then iscid := "101";
elsif r.sireq(4) = '1' then iscid := "100";
elsif r.sireq(3) = '1' then iscid := "011";
elsif r.sireq(2) = '1' then iscid := "010";
elsif r.sireq(1) = '1' then iscid := "001";
elsif r.sireq(0) = '1' then iscid := "000";
else
iscval := '0';
end if;
if r.ide = '1' then
if r.fireq='1' or iscval='1' then
iei_req := '1';
end if;
end if;
if EI_ACK = '1' then -- interrupt executed
if r.fireq = '1' then
n.scp := '0'; -- clear scp flag, is command end
n.fireq := '0';
elsif iscval = '1' then -- was a seek done
n.scp := '1'; -- signal seek complete interrupt
n.id := iscid; -- load id
n.sireq(to_integer(unsigned(iscid))) := '0'; -- reset sireq bit
end if;
end if;
if icrip = '1' then -- control reset in progress ?
imem_addr := '0' & r.icnt; -- use icnt as addr
imem_din := (others=>'0'); -- force data to zero
imem_we0 := '1'; -- enable writes
imem_we1 := '1';
end if;
if CE_MSEC = '1' then -- advance sector counter every msec
if unsigned(r.sc) = 8#13# then -- sector counter (count to 8#13#)
n.sc := (others=>'0');
else
n.sc := slv(unsigned(r.sc) + 1);
end if;
end if;
N_REGS <= n;
MEM_0_WE <= imem_we0;
MEM_1_WE <= imem_we1;
MEM_ADDR <= imem_addr;
MEM_DIN <= imem_din;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
RB_LAM <= ilam;
EI_REQ <= iei_req;
end process proc_next;
end syn;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ae_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ae_e-e.vhd,v 1.4 2005/10/06 11:16:07 wig Exp $
-- $Date: 2005/10/06 11:16:07 $
-- $Log: inst_ae_e-e.vhd,v $
-- Revision 1.4 2005/10/06 11:16:07 wig
-- Got testcoverage up, fixed generic problem, prepared report
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ae_e
--
entity inst_ae_e is
-- Generics:
-- No Generated Generics for Entity inst_ae_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ae_e
bus20040728_altop_i : in std_ulogic_vector(7 downto 0);
--!wig: ERROR20050930: p_mix_bus20040728_top_7_4_gi : in std_ulogic_vector(3 downto 0)
p_mix_bus20040728_top_7_0_gi : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_ae_e
);
end inst_ae_e;
--
-- End of Generated Entity inst_ae_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
PACKAGE ldc1000_interface_pkg IS
CONSTANT c_ldc1000_interface_address_width : INTEGER := 4;
COMPONENT ldc1000_interface IS
GENERIC (
BASE_CLK: INTEGER := 250000000;
SCLK_FREQUENCY : INTEGER := 4000000;
UNIQUE_ID: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_ldc1000_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
osl_avs_waitrequest : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_csb : OUT STD_LOGIC;
isl_sdo : IN STD_LOGIC;
osl_sdi : OUT STD_LOGIC;
osl_tbclk : OUT STD_LOGIC
);
END COMPONENT;
CONSTANT c_ldc1000_subtype_id : STD_LOGIC_VECTOR(c_fLink_subtype_length-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(1,c_fLink_subtype_length));
CONSTANT c_ldc1000_interface_version : STD_LOGIC_VECTOR(c_fLink_interface_version_length-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(0,c_fLink_interface_version_length));
END PACKAGE ldc1000_interface_pkg;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.ldc1000_interface_pkg.ALL;
USE work.fLink_definitions.ALL;
USE work.ldc1000_pkg.ALL;
ENTITY ldc1000_interface IS
GENERIC (
BASE_CLK: INTEGER := 250000000;
SCLK_FREQUENCY : INTEGER := 4000000;
UNIQUE_ID: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := (OTHERS => '0')
);
PORT (
isl_clk : IN STD_LOGIC;
isl_reset_n : IN STD_LOGIC;
islv_avs_address : IN STD_LOGIC_VECTOR(c_ldc1000_interface_address_width-1 DOWNTO 0);
isl_avs_read : IN STD_LOGIC;
isl_avs_write : IN STD_LOGIC;
islv_avs_write_data : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
islv_avs_byteenable : IN STD_LOGIC_VECTOR(c_fLink_avs_data_width_in_byte-1 DOWNTO 0);
oslv_avs_read_data : OUT STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0);
osl_avs_waitrequest : OUT STD_LOGIC;
osl_sclk : OUT STD_LOGIC;
oslv_csb : OUT STD_LOGIC;
isl_sdo : IN STD_LOGIC;
osl_sdi : OUT STD_LOGIC;
osl_tbclk : OUT STD_LOGIC
);
CONSTANT c_configuration_address: UNSIGNED(c_ldc1000_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_configuration_address,c_ldc1000_interface_address_width);
CONSTANT c_status_address: UNSIGNED(c_ldc1000_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_status_address,c_ldc1000_interface_address_width);
CONSTANT c_typdef_address : UNSIGNED(c_ldc1000_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_typdef_address,c_ldc1000_interface_address_width);
CONSTANT c_mem_size_address: UNSIGNED(c_ldc1000_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_mem_size_address,c_ldc1000_interface_address_width);
CONSTANT c_number_of_channels_address: UNSIGNED(c_ldc1000_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_channels_address,c_ldc1000_interface_address_width);
CONSTANT c_unique_id_address: UNSIGNED(c_ldc1000_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_unique_id_address,c_ldc1000_interface_address_width);
CONSTANT c_usig_base_clk_address: UNSIGNED(c_ldc1000_interface_address_width-1 DOWNTO 0) := to_unsigned(c_fLink_number_of_std_registers,c_ldc1000_interface_address_width);
CONSTANT c_usig_tbclk_frequency_address: UNSIGNED(c_ldc1000_interface_address_width-1 DOWNTO 0) := c_usig_base_clk_address + 1;
CONSTANT c_usig_Rp_address: UNSIGNED(c_ldc1000_interface_address_width-1 DOWNTO 0) := c_usig_tbclk_frequency_address + 1;
CONSTANT c_usig_min_sens_freq_address: UNSIGNED(c_ldc1000_interface_address_width-1 DOWNTO 0) := c_usig_Rp_address + 1;
CONSTANT c_usig_threshold_address: UNSIGNED(c_ldc1000_interface_address_width-1 DOWNTO 0) := c_usig_min_sens_freq_address + 1;
CONSTANT c_usig_proximity_address: UNSIGNED(c_ldc1000_interface_address_width-1 DOWNTO 0) := c_usig_threshold_address + 1;
CONSTANT c_usig_frequ_cnt_address: UNSIGNED(c_ldc1000_interface_address_width-1 DOWNTO 0) := c_usig_proximity_address + 1;
END ENTITY ldc1000_interface;
ARCHITECTURE rtl OF ldc1000_interface IS
TYPE t_internal_register IS RECORD
global_reset_n : STD_LOGIC;
ldc_reset_n : STD_LOGIC;
config_reg : t_conf_regs;
update_config : STD_LOGIC;
END RECORD;
SIGNAL ri,ri_next : t_internal_register;
SIGNAL out_config : t_conf_regs;
SIGNAL ldc1000_data : t_data_regs;
SIGNAL configuring : STD_LOGIC;
SIGNAL confi_done : STD_LOGIC;
BEGIN
my_ldc1000 : ldc1000
GENERIC MAP (BASE_CLK,SCLK_FREQUENCY)
PORT MAP (isl_clk,ri.ldc_reset_n,
osl_sclk,oslv_csb,isl_sdo,osl_sdi,osl_tbclk,
ri.config_reg,out_config,ldc1000_data,configuring,ri.update_config,confi_done
);
-- cobinatoric process
comb_proc : PROCESS (isl_reset_n,ri,isl_avs_write,islv_avs_address,isl_avs_read,islv_avs_write_data,configuring,out_config,ldc1000_data,islv_avs_byteenable,confi_done)
VARIABLE vi : t_internal_register;
VARIABLE address: UNSIGNED(c_ldc1000_interface_address_width-1 DOWNTO 0) := to_unsigned(0,c_ldc1000_interface_address_width);
BEGIN
-- keep variables stable
vi := ri;
--standard values
oslv_avs_read_data <= (OTHERS => '0');
vi.global_reset_n := '1';
vi.ldc_reset_n := '1';
address := UNSIGNED(islv_avs_address);
vi.update_config := '0';
IF confi_done = '1' THEN
vi.config_reg := out_config;
END IF;
--avalon slave interface write part
IF isl_avs_write = '1' THEN
CASE address IS
WHEN c_configuration_address =>
IF islv_avs_byteenable(0) = '1' THEN
vi.global_reset_n := NOT islv_avs_write_data(c_fLink_reset_bit_num);
vi.update_config := islv_avs_write_data(1);
vi.config_reg.response_time := islv_avs_write_data( 4 DOWNTO 2);
vi.config_reg.amplitude := islv_avs_write_data( 6 DOWNTO 5);
END IF;
IF islv_avs_byteenable(1) = '1' THEN
vi.config_reg.intb_mode := islv_avs_write_data( 10 DOWNTO 8);
vi.config_reg.pwr_mode := islv_avs_write_data(11);
END IF;
WHEN c_usig_tbclk_frequency_address =>
FOR i IN 0 TO c_fLink_avs_data_width_in_byte-1 LOOP
IF islv_avs_byteenable(i) = '1' THEN
vi.config_reg.frequency_divider((i+1)*8-1 DOWNTO 8*i) := UNSIGNED(islv_avs_write_data((i+1)*8-1 DOWNTO 8*i));
END IF;
END LOOP;
WHEN c_usig_Rp_address =>
IF islv_avs_byteenable(0) = '1' THEN
vi.config_reg.rp_min := islv_avs_write_data(7 DOWNTO 0);
END IF;
IF islv_avs_byteenable(1) = '1' THEN
vi.config_reg.rp_max := islv_avs_write_data(15 DOWNTO 8);
END IF;
WHEN c_usig_min_sens_freq_address =>
IF islv_avs_byteenable(0) = '1' THEN
vi.config_reg.min_sens_freq := islv_avs_write_data(7 DOWNTO 0);
END IF;
WHEN c_usig_threshold_address =>
IF islv_avs_byteenable(0) = '1' THEN
vi.config_reg.threshold_low_msb := islv_avs_write_data(7 DOWNTO 0);
END IF;
IF islv_avs_byteenable(1) = '1' THEN
vi.config_reg.threshold_high_msb:= islv_avs_write_data(15 DOWNTO 8);
END IF;
WHEN OTHERS =>
END CASE;
END IF;
--avalon slave interface read part
IF isl_avs_read = '1' THEN
CASE address IS
WHEN c_typdef_address =>
oslv_avs_read_data ((c_fLink_interface_version_length + c_fLink_subtype_length + c_fLink_id_length - 1) DOWNTO
(c_fLink_interface_version_length + c_fLink_subtype_length)) <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_sensor_id,c_fLink_id_length));
oslv_avs_read_data((c_fLink_interface_version_length + c_fLink_subtype_length - 1) DOWNTO c_fLink_interface_version_length) <= c_ldc1000_subtype_id;
oslv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) <= c_ldc1000_interface_version;
WHEN c_mem_size_address =>
oslv_avs_read_data(c_ldc1000_interface_address_width+2) <= '1';
WHEN c_number_of_channels_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(1,c_fLink_avs_data_width));
WHEN c_unique_id_address =>
oslv_avs_read_data <= UNIQUE_ID;
WHEN c_usig_base_clk_address =>
oslv_avs_read_data <= std_logic_vector(to_unsigned(BASE_CLK,c_fLink_avs_data_width));
WHEN c_configuration_address =>
oslv_avs_read_data(0) <= NOT vi.global_reset_n;
oslv_avs_read_data(1) <= vi.update_config;
oslv_avs_read_data(4 DOWNTO 2) <= vi.config_reg.response_time;
oslv_avs_read_data(6 DOWNTO 5) <= vi.config_reg.amplitude;
oslv_avs_read_data(10 DOWNTO 8) <= vi.config_reg.intb_mode;
oslv_avs_read_data(11) <= vi.config_reg.pwr_mode;
WHEN c_status_address =>
oslv_avs_read_data(7 DOWNTO 0) <= vi.config_reg.device_id;
oslv_avs_read_data(8) <= configuring;
oslv_avs_read_data(9) <= ldc1000_data.comperator;
oslv_avs_read_data(10) <= ldc1000_data.wake_up;
oslv_avs_read_data(11) <= ldc1000_data.DRDYB;
oslv_avs_read_data(12) <= ldc1000_data.OSC_dead;
WHEN c_usig_tbclk_frequency_address =>
oslv_avs_read_data <= STD_LOGIC_VECTOR(vi.config_reg.frequency_divider);
WHEN c_usig_Rp_address =>
oslv_avs_read_data(7 DOWNTO 0) <= vi.config_reg.rp_min;
oslv_avs_read_data(15 DOWNTO 8) <= vi.config_reg.rp_max;
WHEN c_usig_min_sens_freq_address =>
oslv_avs_read_data(7 DOWNTO 0) <= vi.config_reg.min_sens_freq;
WHEN c_usig_threshold_address =>
oslv_avs_read_data(7 DOWNTO 0) <= vi.config_reg.threshold_low_msb;
oslv_avs_read_data(15 DOWNTO 8) <= vi.config_reg.threshold_high_msb;
WHEN c_usig_proximity_address =>
oslv_avs_read_data(15 DOWNTO 0) <= ldc1000_data.proximity;
WHEN c_usig_frequ_cnt_address =>
oslv_avs_read_data(23 DOWNTO 0) <= ldc1000_data.frequency_counter;
WHEN OTHERS =>
END CASE;
END IF;
IF isl_reset_n = '0' OR vi.global_reset_n = '0' THEN
vi.ldc_reset_n := '0';
vi.update_config := '0';
vi.config_reg.device_id := (OTHERS => '0');
vi.config_reg.rp_max := (OTHERS => '0');
vi.config_reg.rp_min := (OTHERS => '0');
vi.config_reg.min_sens_freq := (OTHERS => '0');
vi.config_reg.threshold_high_msb := (OTHERS => '0');
vi.config_reg.threshold_low_msb := (OTHERS => '0');
vi.config_reg.amplitude := (OTHERS => '0');
vi.config_reg.response_time := (OTHERS => '0');
vi.config_reg.intb_mode := (OTHERS => '0');
vi.config_reg.frequency_divider := (OTHERS => '0');
vi.config_reg.pwr_mode := '0';
END IF;
--keep variables stable
ri_next <= vi;
END PROCESS comb_proc;
reg_proc : PROCESS (isl_clk)
BEGIN
IF rising_edge(isl_clk) THEN
ri <= ri_next;
END IF;
END PROCESS reg_proc;
osl_avs_waitrequest <= '0';
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tl_car_field is
port(
osc_out: out std_logic;
osc_in: in std_logic;
ext_clk_in: in std_logic;
--
l_lvds_io: inout std_logic;
r_lvds_io: inout std_logic;
--
i2s1_sck: out std_logic;
i2s1_ws: out std_logic;
i2s1_d0: in std_logic;
--i2s1_d1: in std_logic;
i2s2_sck: out std_logic;
i2s2_ws: out std_logic;
i2s2_d0: out std_logic;
i2s2_d1: out std_logic;
--
spi1_clk: in std_logic;
spi1_mosi: in std_logic;
spi1_miso: out std_logic;
spi1_cs0: in std_logic;
spi1_cs2: in std_logic;
spi3_clk: in std_logic;
spi3_mosi: in std_logic;
spi3_miso: out std_logic;
spi3_cs0: in std_logic;
spi3_cs3: in std_logic;
--
test_l1, test_l2, test_m1, test_m2: out std_logic
);
end entity;
architecture a of tl_car_field is
component pll_4 is
port(
CLKI, RST: in std_logic;
CLKOP: out std_logic
);
end component;
component car_clock_gen is
port(
hr_clk, reset: in std_logic;
main_clk, seq_reset, i2s_ws: out std_logic
);
end component;
component car_core is
port(
main_clk, reset, seq_reset, i2s_ws: in std_logic;
--
lvds_io: inout std_logic;
--
i2s_sclk: out std_logic;
i2s_dspk: in std_logic;
i2s_dmic: out std_logic;
--
spi_sck: in std_logic;
spi_mosi: in std_logic;
spi_miso: out std_logic;
spi_cs0: in std_logic;
spi_cs1: in std_logic;
--
test_lrst_pre, test_djb_present: out std_logic
);
end component;
signal hr_clk, main_clk, int_reset, seq_reset: std_logic;
signal i2s_sck, i2s_ws: std_logic;
signal test_counter: unsigned(3 downto 0);
begin
int_reset <= '0';
osc_out <= not osc_in;
test_l1 <= ext_clk_in;
i2s1_sck <= i2s_sck;
i2s2_sck <= i2s_sck;
i2s1_ws <= i2s_ws;
i2s2_ws <= i2s_ws;
-- Testing
process(hr_clk) is begin
if rising_edge(hr_clk) then
test_counter <= test_counter + 1;
end if;
end process;
test_l2 <= test_counter(3);
-- For 48 kHz sampling:
-- 48 kHz sampling * 2 channels * 32 bits = 3.072 MHz I2S bit clock
-- LVDS bit clock = 4x I2S bit clock = 12.288 MHz
-- hr_clk = 4x LVDS bit clock = 49.152 MHz
-- For 96kHz sampling:
-- 96 kHz sampling * 2 channels * 32 bits = 6.144 MHz I2S bit clock
-- LVDS bit clock = 4x I2S bit clock = 24.576 MHz
-- hr_clk = 4x LVDS bit clock = 98.304 MHz
e_pll_4: pll_4 port map (
CLKI => ext_clk_in,
RST => int_reset,
CLKOP => hr_clk
);
e_car_clock_gen: car_clock_gen port map (
hr_clk => hr_clk, reset => int_reset,
main_clk => main_clk, seq_reset => seq_reset, i2s_ws => i2s_ws
);
l_car_core: car_core port map (
main_clk => main_clk, reset => int_reset, seq_reset => seq_reset, i2s_ws => i2s_ws,
lvds_io => l_lvds_io,
i2s_sclk => i2s_sck, i2s_dmic => i2s2_d0, i2s_dspk => i2s1_d0,
spi_sck => spi1_clk,
spi_mosi => spi1_mosi,
spi_miso => spi1_miso,
spi_cs0 => spi1_cs0,
spi_cs1 => spi1_cs2,
test_lrst_pre => test_m1, test_djb_present => test_m2
);
r_car_core: car_core port map (
main_clk => main_clk, reset => int_reset, seq_reset => seq_reset, i2s_ws => i2s_ws,
lvds_io => r_lvds_io,
i2s_sclk => open, i2s_dmic => i2s2_d1, i2s_dspk => i2s1_d0,
spi_sck => spi3_clk,
spi_mosi => spi3_mosi,
spi_miso => spi3_miso,
spi_cs0 => spi3_cs0,
spi_cs1 => spi3_cs3,
test_lrst_pre => open, test_djb_present => open
);
end architecture;
|
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity testina is
end entity;
architecture beh of testina is
component mezzanotte is
port (
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
dout : out std_logic_vector(15 downto 0);
fine : out std_logic
);
end component;
signal din, dout : std_logic_vector(15 downto 0);
signal start, clk, fine : std_logic;
begin
DUT: mezzanotte port map (din, start, clk, dout, fine);
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
start <= '1' after 1 ns, '0' after 11 ns,
'1' after 56 ns, '0' after 66 ns,
'1' after 106 ns, '0' after 116 ns,
'1' after 166 ns, '0' after 176 ns;
din <= conv_std_logic_vector (0, 16) after 11 ns, conv_std_logic_vector (5, 16) after 21 ns, conv_std_logic_vector(7, 16) after 31 ns, -- OP "00" aka AND
conv_std_logic_vector(1, 16) after 66 ns, conv_std_logic_vector(1, 16) after 76 ns, -- OP "01" aka ADR
conv_std_logic_vector(2, 16) after 116 ns, conv_std_logic_vector(7, 16) after 126 ns, conv_std_logic_vector(3, 16) after 136 ns, -- OP "10" aka ADD
conv_std_logic_vector(3, 16) after 176 ns, conv_std_logic_vector(0, 16) after 186 ns, conv_std_logic_vector(0, 16) after 196 ns; -- OP "11" aka MIN
end beh;
|
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity testina is
end entity;
architecture beh of testina is
component mezzanotte is
port (
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
dout : out std_logic_vector(15 downto 0);
fine : out std_logic
);
end component;
signal din, dout : std_logic_vector(15 downto 0);
signal start, clk, fine : std_logic;
begin
DUT: mezzanotte port map (din, start, clk, dout, fine);
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
start <= '1' after 1 ns, '0' after 11 ns,
'1' after 56 ns, '0' after 66 ns,
'1' after 106 ns, '0' after 116 ns,
'1' after 166 ns, '0' after 176 ns;
din <= conv_std_logic_vector (0, 16) after 11 ns, conv_std_logic_vector (5, 16) after 21 ns, conv_std_logic_vector(7, 16) after 31 ns, -- OP "00" aka AND
conv_std_logic_vector(1, 16) after 66 ns, conv_std_logic_vector(1, 16) after 76 ns, -- OP "01" aka ADR
conv_std_logic_vector(2, 16) after 116 ns, conv_std_logic_vector(7, 16) after 126 ns, conv_std_logic_vector(3, 16) after 136 ns, -- OP "10" aka ADD
conv_std_logic_vector(3, 16) after 176 ns, conv_std_logic_vector(0, 16) after 186 ns, conv_std_logic_vector(0, 16) after 196 ns; -- OP "11" aka MIN
end beh;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Fri Oct 16 15:22:50 2015
-- Host : cascade.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.1 (Maipo)
-- Command : write_vhdl -force -mode synth_stub
-- /afs/ece.cmu.edu/usr/cmbarker/Private/Atari7800/maria/maria.srcs/sources_1/ip/dll_img_ram/dll_img_ram_stub.vhdl
-- Design : dll_img_ram
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dll_img_ram is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end dll_img_ram;
architecture stub of dll_img_ram is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[15:0],dina[7:0],douta[7:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_2,Vivado 2015.2";
begin
end;
|
-- Teste geral para a estrutura do Processador Mips8B
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Ieee.Numeric_Std.all;
Entity test_processor is
End Entity test_processor;
Architecture test_general of test_processor is
Component Mips8B is
Port(Reset_n: In Std_Logic;
Clock: In Std_Logic;
MAddr: Out Std_Logic_Vector(7 downto 0);
MCmd: Out Std_Logic_Vector(1 downto 0);
MData: Out Std_Logic_Vector(7 downto 0);
SData: In Std_Logic_Vector(7 downto 0);
SCmdAccept: In Std_Logic);
End Component Mips8B;
Type Memory_Array is Array(Natural Range <>) of Std_Logic_Vector(7 downto 0);
Use Work.MIPS8B_Base.ocpIDLE_little;
Use Work.MIPS8B_Base.ocpWR_little;
Use Work.MIPS8B_Base.ocpRD_little;
Use Work.MIPS8B_Base.ocpNULL_little;
Use Work.MIPS8B_Base.ocpDVA_little;
Signal Reset_n: Std_Logic;
Signal Clock: Std_Logic := '0';
Signal Clock_Mem: Std_Logic := '0';
Signal MAddr: Std_Logic_Vector(7 downto 0);
Signal MCmd: Std_Logic_Vector(1 downto 0);
Signal MData: Std_Logic_Vector(7 downto 0);
Signal SData: Std_Logic_Vector(7 downto 0);
Signal SCmdAccept: Std_Logic;
Begin
Reset_n <= '1', '0' after 20 ns, '1' after 40 ns;
Clock <= not Clock after 10 ns;
Clock_Mem <= not Clock_Mem after 15 ns;
Memory: Process
Variable int_SCmdAccept: Std_Logic;
Variable address: Unsigned(7 downto 0);
Variable mem_int: Memory_Array(0 to 255) := (
"00100000", "00000001", "00000000", "10110100",
"00100000", "00000010", "00000000", "10000000",
"00100000", "00000011", "00000000", "01111111",
"00100000", "00000100", "00000000", "11111111",
"00100000", "00000101", "00000000", "00110101",
"00100000", "00000110", "00000000", "01000000",
"00100000", "00000111", "00000000", "01001000",
"10100000", "00000111", "00000000", "11111000",
"10100000", "00000110", "00000000", "11111001",
"10100000", "00000101", "00000000", "11111010",
"10100000", "00000100", "00000000", "11111011",
"10100000", "00000011", "00000000", "11111100",
"10100000", "00000010", "00000000", "11111101",
"10100000", "00000001", "00000000", "11111110",
"10000000", "00000111", "00000000", "11111100",
"10000000", "00000110", "00000000", "11111000",
"10000000", "00000101", "00000000", "11111001",
"10000000", "00000100", "00000000", "11111010",
"10000000", "00000011", "00000000", "11111011",
"10000000", "00000010", "00000000", "11111110",
"10000000", "00000001", "00000000", "11111101",
"10000000", "00000000", "00000000", "11111100",
"10000000", "00000000", "00000000", "11111000",
"10000000", "00000000", "00000000", "11111001",
"10000000", "00000000", "00000000", "11111010",
"10000000", "00000000", "00000000", "11111011",
"10000000", "00000000", "00000000", "11111110",
"10000000", "00000000", "00000000", "11111101",
"00100000", "00000001", "00000000", "11111011",
"10100000", "00100010", "00000000", "11111000",
"10100000", "00100011", "00000000", "11111001",
"10100000", "00100100", "00000000", "11111010",
"10100000", "00100101", "00000000", "11111011",
"10100000", "00100110", "00000000", "11111100",
"10100000", "00100111", "00000000", "11111101",
"10000000", "00100111", "00000000", "11111100",
"10000000", "00100110", "00000000", "11111000",
"10000000", "00100101", "00000000", "11111001",
"10000000", "00100100", "00000000", "11111010",
"10000000", "00100011", "00000000", "11111011",
"10000000", "00100010", "00000000", "11111110",
Others => "00000000");
Begin
Wait Until Clock_Mem'Event and Clock_Mem='1';
Case MCmd is
When ocpWR_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
mem_int(to_integer(address)) := MData;
Else
int_SCmdAccept := ocpNULL_little;
End If;
SData <= "ZZZZZZZZ";
When ocpRD_little =>
If int_SCmdAccept = ocpNULL_little then
int_SCmdAccept := ocpDVA_little;
address := Unsigned(MAddr);
SData <= mem_int(to_integer(address));
Else
int_SCmdAccept := ocpNULL_little;
End If;
When Others =>
int_SCmdAccept := ocpNULL_little;
SData <= "ZZZZZZZZ";
End Case;
SCmdAccept <= int_SCmdAccept;
End Process Memory;
DUV: Mips8B
Port Map( Reset_n => Reset_n,
Clock => Clock,
MAddr => MAddr,
MCmd => MCmd,
MData => MData,
SData => SData,
SCmdAccept => SCmdAccept);
End Architecture test_general;
Configuration general_test of test_processor is
For test_general
For DUV: Mips8B Use Configuration Work.Mips8B_struct_conf;
End For;
End For;
End Configuration general_test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memmux01 is
port (
wen : std_logic;
addr : std_logic_vector (3 downto 0);
wdat : std_logic;
rdat : out std_logic_vector (15 downto 0);
clk : std_logic;
rst : std_logic);
end memmux01;
architecture rtl of memmux01 is
begin
process (clk)
is
variable mem : std_logic_vector (15 downto 0);
variable ad : natural range 0 to 15;
begin
if rising_edge(clk) then
rdat <= mem;
if rst = '1' then
mem := (others => '0');
else
ad := to_integer(unsigned(addr));
if wen = '1' then
mem (ad) := wdat;
end if;
end if;
end if;
end process;
end rtl;
|
library ieee, altera;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use altera.altera_syn_attributes.all;
entity PZP_MIF is
port (clk: in std_logic;
addr: in natural range 0 to 63;
q: out std_logic_vector (7 downto 0));
end entity;
architecture rtl of PZP_MIF is
type PZP_MIF_t is array (63 downto 0) of std_logic_vector(7 downto 0);
signal rom: PZP_MIF_t;
attribute ram_init_file: string;
attribute ram_init_file of rom: signal is "PZP_MIF.mif";
begin
process(clk)
begin
if(rising_edge(clk)) then
q <= rom(addr);
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lab5 is
port(CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(17 downto 0);
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0); -- The outs go to VGA controller
VGA_HS : out std_logic;
VGA_VS : out std_logic;
VGA_BLANK : out std_logic;
VGA_SYNC : out std_logic;
VGA_CLK : out std_logic);
end lab5;
architecture RTL of lab5 is
begin
end RTL;
|
-- NEED RESULT: ENT00221: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00221: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00221: Wait statement longest static prefix check passed
-- NEED RESULT: ENT00221: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00221
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00221(ARCH00221)
-- ENT00221_Test_Bench(ARCH00221_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00221 is
generic (G : integer) ;
port (
s_st_rec3_vector : inout st_rec3_vector
) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00221 ;
--
--
architecture ARCH00221 of ENT00221 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
case counter is
when 0
=>
s_st_rec3_vector(1).f1 <= transport
c_st_rec3_vector_2(1).f1 ;
s_st_rec3_vector(2).f2 <= transport
c_st_rec3_vector_2(2).f2 after 10 ns ;
wait until s_st_rec3_vector(2).f2 =
c_st_rec3_vector_2(2).f2 ;
Test_Report (
"ENT00221",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3_vector(2).f2 =
c_st_rec3_vector_2(2).f2 )) ;
--
when 1
=>
s_st_rec3_vector(1).f1 <= transport
c_st_rec3_vector_1(1).f1 ;
s_st_rec3_vector(G).f2 <= transport
c_st_rec3_vector_2(G).f2 after 10 ns ;
wait until s_st_rec3_vector(G).f2 =
c_st_rec3_vector_2(G).f2 ;
Test_Report (
"ENT00221",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3_vector(G).f2 =
c_st_rec3_vector_2(G).f2 )) ;
--
when 2
=>
s_st_rec3_vector(1).f1 <= transport
c_st_rec3_vector_2(1).f1 ;
s_st_rec3_vector(CG).f2 <= transport
c_st_rec3_vector_2(CG).f2 after 10 ns ;
wait until s_st_rec3_vector(CG).f2 =
c_st_rec3_vector_2(CG).f2 ;
Test_Report (
"ENT00221",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3_vector(CG).f2 =
c_st_rec3_vector_2(CG).f2 )) ;
--
when 3
=>
s_st_rec3_vector(1).f1 <= transport
c_st_rec3_vector_1(1).f1 ;
s_st_rec3_vector(CG'Attr).f2 <= transport
c_st_rec3_vector_2(CG'Attr).f2 after 10 ns ;
wait until s_st_rec3_vector(CG'Attr).f2 =
c_st_rec3_vector_2(CG'Attr).f2 ;
Test_Report (
"ENT00221",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_rec3_vector(CG'Attr).f2 =
c_st_rec3_vector_2(CG'Attr).f2 )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_rec3_vector = 3 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00221 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00221_Test_Bench is
end ENT00221_Test_Bench ;
--
--
architecture ARCH00221_Test_Bench of ENT00221_Test_Bench is
begin
L1:
block
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
component UUT
generic (G : integer) ;
port (
s_st_rec3_vector : inout st_rec3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00221 ( ARCH00221 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
port map (
s_st_rec3_vector
)
;
end block L1 ;
end ARCH00221_Test_Bench ;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L); -- pragma label minus
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return SIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < SIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= SIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= SIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > SIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > SIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= SIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= SIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
end STD_LOGIC_SIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L); -- pragma label minus
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return SIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < SIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= SIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= SIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > SIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > SIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= SIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= SIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
end STD_LOGIC_SIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L); -- pragma label minus
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return SIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < SIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= SIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= SIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > SIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > SIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= SIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= SIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
end STD_LOGIC_SIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L); -- pragma label minus
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return SIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < SIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= SIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= SIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > SIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > SIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= SIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= SIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
end STD_LOGIC_SIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L); -- pragma label minus
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return SIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < SIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= SIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= SIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > SIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > SIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= SIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= SIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
end STD_LOGIC_SIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L); -- pragma label minus
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return SIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < SIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= SIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= SIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > SIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > SIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= SIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= SIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
end STD_LOGIC_SIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L); -- pragma label minus
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return SIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < SIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= SIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= SIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > SIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > SIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= SIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= SIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
end STD_LOGIC_SIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L); -- pragma label minus
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return SIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < SIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= SIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= SIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > SIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > SIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= SIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= SIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
end STD_LOGIC_SIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L); -- pragma label minus
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return SIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < SIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= SIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= SIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > SIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > SIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= SIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= SIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
end STD_LOGIC_SIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L); -- pragma label minus
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return SIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < SIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= SIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= SIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > SIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > SIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= SIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= SIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
end STD_LOGIC_SIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L); -- pragma label minus
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return SIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < SIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= SIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= SIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > SIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > SIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= SIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= SIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
end STD_LOGIC_SIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L); -- pragma label minus
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return SIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < SIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= SIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= SIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > SIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > SIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= SIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= SIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
end STD_LOGIC_SIGNED;
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L); -- pragma label minus
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return SIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < SIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= SIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= SIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > SIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > SIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= SIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= SIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
end STD_LOGIC_SIGNED;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RxIn_Delay is
port (
-- Common ports
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic;
-- Transaction receive interface
trn_rsof_n : IN std_logic;
trn_reof_n : IN std_logic;
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n : IN std_logic;
trn_rsrc_rdy_n : IN std_logic;
trn_rsrc_dsc_n : IN std_logic;
trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
trn_rdst_rdy_n : OUT std_logic;
Pool_wrBuf_full : IN std_logic;
Link_Buf_full : IN std_logic;
-- Delay for one clock
trn_rsof_n_dly : OUT std_logic;
trn_reof_n_dly : OUT std_logic;
trn_rd_dly : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n_dly : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n_dly : OUT std_logic;
trn_rsrc_rdy_n_dly : OUT std_logic;
trn_rdst_rdy_n_dly : OUT std_logic;
trn_rsrc_dsc_n_dly : OUT std_logic;
trn_rbar_hit_n_dly : OUT std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- TLP resolution
IORd_Type : OUT std_logic;
IOWr_Type : OUT std_logic;
MRd_Type : OUT std_logic_vector(3 downto 0);
MWr_Type : OUT std_logic_vector(1 downto 0);
CplD_Type : OUT std_logic_vector(3 downto 0);
-- From Cpl/D channel
usDMA_dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
dsDMA_dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- To Memory request process modules
Tlp_straddles_4KB : OUT std_logic;
-- To Cpl/D channel
Tlp_has_4KB : OUT std_logic;
Tlp_has_1DW : OUT std_logic;
CplD_is_the_Last : OUT std_logic;
CplD_on_Pool : OUT std_logic;
CplD_on_EB : OUT std_logic;
Req_ID_Match : OUT std_logic;
usDex_Tag_Matched : OUT std_logic;
dsDex_Tag_Matched : OUT std_logic;
CplD_Tag : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Additional
cfg_dcommand : IN std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
localID : IN std_logic_vector(C_ID_WIDTH-1 downto 0)
);
end entity RxIn_Delay;
architecture Behavioral of RxIn_Delay is
-- Max Length Checking
signal Tlp_has_0_Length : std_logic;
signal Tlp_has_1DW_Length_i : std_logic;
signal MaxReadReqSize_Exceeded: std_logic;
signal MaxPayloadSize_Exceeded: std_logic;
signal Tlp_straddles_4KB_i : std_logic;
signal CarryIn_ALC : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto 0);
signal Tlp_has_4KB_i : std_logic;
signal cfg_MRS : std_logic_vector(C_CFG_MRS_BIT_TOP-C_CFG_MRS_BIT_BOT downto 0);
signal cfg_MPS : std_logic_vector(C_CFG_MPS_BIT_TOP-C_CFG_MPS_BIT_BOT downto 0);
signal cfg_MRS_decoded : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
signal cfg_MPS_decoded : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
TYPE CfgThreshold is ARRAY (C_TLP_FLD_WIDTH_OF_LENG-CBIT_SENSE_OF_MAXSIZE downto 0)
of std_logic_vector (C_TLP_FLD_WIDTH_OF_LENG downto 0);
signal MaxSize_Thresholds : CfgThreshold;
-- As one clock of delay
signal trn_rsof_n_r1 : std_logic;
signal trn_reof_n_r1 : std_logic;
signal trn_rrem_n_r1 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_rd_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal trn_rerrfwd_n_r1 : std_logic;
signal trn_rsrc_rdy_n_r1 : std_logic;
signal trn_rdst_rdy_n_i : std_logic;
signal trn_rdst_rdy_n_r1 : std_logic;
signal trn_rsrc_dsc_n_r1 : std_logic;
signal trn_rbar_hit_n_r1 : std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- TLP type decision
signal TLP_is_MRd_BAR0_H3DW : std_logic;
signal TLP_is_MRd_BAR1_H3DW : std_logic;
signal TLP_is_MRd_BAR2_H3DW : std_logic;
signal TLP_is_MRd_BAR3_H3DW : std_logic;
signal TLP_is_MRd_BAR0_H4DW : std_logic;
signal TLP_is_MRd_BAR1_H4DW : std_logic;
signal TLP_is_MRd_BAR2_H4DW : std_logic;
signal TLP_is_MRd_BAR3_H4DW : std_logic;
signal TLP_is_MRdLk_BAR0_H3DW : std_logic;
signal TLP_is_MRdLk_BAR1_H3DW : std_logic;
signal TLP_is_MRdLk_BAR2_H3DW : std_logic;
signal TLP_is_MRdLk_BAR3_H3DW : std_logic;
signal TLP_is_MRdLk_BAR0_H4DW : std_logic;
signal TLP_is_MRdLk_BAR1_H4DW : std_logic;
signal TLP_is_MRdLk_BAR2_H4DW : std_logic;
signal TLP_is_MRdLk_BAR3_H4DW : std_logic;
signal TLP_is_MWr_BAR0_H3DW : std_logic;
signal TLP_is_MWr_BAR1_H3DW : std_logic;
signal TLP_is_MWr_BAR2_H3DW : std_logic;
signal TLP_is_MWr_BAR3_H3DW : std_logic;
signal TLP_is_MWr_BAR0_H4DW : std_logic;
signal TLP_is_MWr_BAR1_H4DW : std_logic;
signal TLP_is_MWr_BAR2_H4DW : std_logic;
signal TLP_is_MWr_BAR3_H4DW : std_logic;
signal TLP_is_IORd_BAR0 : std_logic;
signal TLP_is_IORd_BAR1 : std_logic;
signal TLP_is_IORd_BAR2 : std_logic;
signal TLP_is_IORd_BAR3 : std_logic;
signal TLP_is_IOWr_BAR0 : std_logic;
signal TLP_is_IOWr_BAR1 : std_logic;
signal TLP_is_IOWr_BAR2 : std_logic;
signal TLP_is_IOWr_BAR3 : std_logic;
signal TLP_is_IORd : std_logic;
signal TLP_is_IOWr : std_logic;
signal TLP_is_CplD : std_logic;
signal TLP_is_Cpl : std_logic;
signal TLP_is_CplDLk : std_logic;
signal TLP_is_CplLk : std_logic;
signal TLP_is_MRd_H3DW : std_logic;
signal TLP_is_MRd_H4DW : std_logic;
signal TLP_is_MRdLk_H3DW : std_logic;
signal TLP_is_MRdLk_H4DW : std_logic;
signal TLP_is_MWr_H3DW : std_logic;
signal TLP_is_MWr_H4DW : std_logic;
signal IORd_Type_i : std_logic;
signal IOWr_Type_i : std_logic;
signal MRd_Type_i : std_logic_vector(3 downto 0);
signal MWr_Type_i : std_logic_vector(1 downto 0);
signal CplD_Type_i : std_logic_vector(3 downto 0);
signal Req_ID_Match_i : std_logic;
signal usDex_Tag_Matched_i : std_logic;
signal dsDex_Tag_Matched_i : std_logic;
-----------------------------------------------------------------
-- Inbound DW counter
signal TLP_Payload_Address_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal TLP_DW_Length_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
signal TLP_Address_sig : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto 0);
signal MWr_on_Pool : std_logic;
signal MWr_on_EB : std_logic;
signal CplD_on_Pool_i : std_logic;
signal CplD_on_EB_i : std_logic;
signal CplD_is_the_Last_i : std_logic;
signal CplD_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Counter inside a TLP
type TLPCntStates is ( TK_RST
, TK_Idle
-- , TK_MWr_3Hdr_B
, TK_MWr_3Hdr_C
-- , TK_MWr_4Hdr_B
, TK_MWr_4Hdr_C
-- , TK_MWr_4Hdr_D
-- , TK_CplD_Hdr_B
, TK_CplD_Hdr_C
, TK_Body
);
signal FSM_TLP_Cnt : TLPCntStates;
signal FSM_TLP_Cnt_r1 : TLPCntStates;
-- CplD tag capture FSM (Address at tRAM)
type AddrOnRAM_States is ( AOtSt_RST
, AOtSt_Idle
, AOtSt_HdrA
, AOtSt_HdrB
, AOtSt_Body
);
signal FSM_AOtRAM : AddrOnRAM_States;
begin
trn_rdst_rdy_n <= trn_rdst_rdy_n_i ; -- and trn_rsof_n and trn_rsof_n_r1 ;
-- Delay
trn_rsof_n_dly <= trn_rsof_n_r1 ;
trn_reof_n_dly <= trn_reof_n_r1 ;
trn_rrem_n_dly <= trn_rrem_n_r1 ;
trn_rd_dly <= trn_rd_r1 ;
trn_rerrfwd_n_dly <= trn_rerrfwd_n_r1 ;
trn_rsrc_rdy_n_dly <= trn_rsrc_rdy_n_r1 ;
trn_rdst_rdy_n_dly <= trn_rdst_rdy_n_r1 ; -- trn_rdst_rdy_n_r1 ;
trn_rsrc_dsc_n_dly <= trn_rsrc_dsc_n_r1 ;
trn_rbar_hit_n_dly <= trn_rbar_hit_n_r1 ;
-- TLP resolution
IORd_Type <= '0' ; -- IORd_Type_i ;
IOWr_Type <= '0' ; -- IOWr_Type_i ;
MRd_Type <= MRd_Type_i ;
MWr_Type <= MWr_Type_i ;
CplD_Type <= CplD_Type_i ;
-- To Cpl/D channel
Req_ID_Match <= Req_ID_Match_i ;
usDex_Tag_Matched <= usDex_Tag_Matched_i ;
dsDex_Tag_Matched <= dsDex_Tag_Matched_i ;
CplD_Tag <= CplD_Tag_i ;
CplD_is_the_Last <= CplD_is_the_Last_i ;
CplD_on_Pool <= CplD_on_Pool_i ;
CplD_on_EB <= CplD_on_EB_i ;
Tlp_has_4KB <= Tlp_has_4KB_i ;
Tlp_has_1DW <= Tlp_has_1DW_Length_i ;
Tlp_straddles_4KB <= '0'; --Tlp_straddles_4KB_i ;
-- !! !!
MaxReadReqSize_Exceeded <= '0';
MaxPayloadSize_Exceeded <= '0';
----------------------------------------------
--
-- Synchronous Registered: TLP_DW_Length
-- Tlp_has_4KB
-- Tlp_has_1DW_Length
-- Tlp_has_0_Length
--
FSM_TLP_1ST_DW_Info:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
TLP_DW_Length_i <= (OTHERS => '0');
Tlp_has_4KB_i <= '0';
Tlp_has_1DW_Length_i <= '0';
Tlp_has_0_Length <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rsof_n='0' then
TLP_DW_Length_i <= trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
else
TLP_DW_Length_i <= TLP_DW_Length_i;
end if;
if trn_rsof_n ='0' then
if trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)=C_ALL_ZEROS(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) then
Tlp_has_4KB_i <= '1' ;
else
Tlp_has_4KB_i <= '0' ;
end if;
else
Tlp_has_4KB_i <= Tlp_has_4KB_i ;
end if;
if trn_rsof_n ='0' then
if trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG) then
Tlp_has_1DW_Length_i <= '1';
else
Tlp_has_1DW_Length_i <= '0';
end if;
else
Tlp_has_1DW_Length_i <= Tlp_has_1DW_Length_i;
end if;
if trn_rsof_n ='0' then
if trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
and trn_rd(2)='0' then
Tlp_has_0_Length <= '1';
else
Tlp_has_0_Length <= '0';
end if;
else
Tlp_has_0_Length <= Tlp_has_0_Length;
end if;
end if;
end process;
---- --------------------------------------------------------------------------
-- -- Max Payload Size bits
-- cfg_MPS <= cfg_dcommand(C_CFG_MPS_BIT_TOP downto C_CFG_MPS_BIT_BOT);
--
-- -- Max Read Request Size bits
-- cfg_MRS <= cfg_dcommand(C_CFG_MRS_BIT_TOP downto C_CFG_MRS_BIT_BOT);
--
--
--
-- -- --------------------------------
-- -- Decoding MPS
-- --
-- Trn_Rx_Decoding_MPS:
-- process ( trn_clk )
-- begin
-- if trn_clk'event and trn_clk = '1' then
--
-- case cfg_MPS is
-- when CONV_STD_LOGIC_VECTOR(0, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(1, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(2, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(3, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(4, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(5, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when Others =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- end case;
--
-- end if;
-- end process;
--
--
-- -- --------------------------------
-- -- Decoding MRS
-- --
-- Trn_Rx_Decoding_MRS:
-- process ( trn_clk )
-- begin
-- if trn_clk'event and trn_clk = '1' then
--
-- case cfg_MRS is
-- when CONV_STD_LOGIC_VECTOR(0, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(1, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(2, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(3, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(4, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(5, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when Others =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- end case;
--
-- end if;
-- end process;
--
--
-- -------------------------------------------------------------
-- MaxSize_Thresholds(0) <= (CBIT_SENSE_OF_MAXSIZE=>'1', Others=>'0');
-- Gen_MaxSizes:
-- FOR i IN 1 TO C_TLP_FLD_WIDTH_OF_LENG-CBIT_SENSE_OF_MAXSIZE GENERATE
-- MaxSize_Thresholds(i) <= MaxSize_Thresholds(i-1)(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0)&'0';
-- END GENERATE;
--
-- -- --------------------------------
-- -- Calculation of MPS exceed
-- --
-- Trn_Rx_MaxPayloadSize_Exceeded:
-- process ( trn_clk )
-- begin
-- if trn_clk'event and trn_clk = '1' then
--
-- case cfg_MPS_decoded is
--
---- when CONV_STD_LOGIC_VECTOR(1, 6) => -- MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
---- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
---- MaxPayloadSize_Exceeded <= '1';
---- else
---- MaxPayloadSize_Exceeded <= '0';
---- end if;
--
-- when CONV_STD_LOGIC_VECTOR(2, 6) => -- MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(1) then
-- MaxPayloadSize_Exceeded <= '1';
-- else
-- MaxPayloadSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(4, 6) => -- MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(2) then
-- MaxPayloadSize_Exceeded <= '1';
-- else
-- MaxPayloadSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(8, 6) => -- MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(3) then
-- MaxPayloadSize_Exceeded <= '1';
-- else
-- MaxPayloadSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(16, 6) => -- MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(4) then
-- MaxPayloadSize_Exceeded <= '1';
-- else
-- MaxPayloadSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(32, 6) => -- MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- MaxPayloadSize_Exceeded <= '0'; -- !!
--
-- when OTHERS =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
-- MaxPayloadSize_Exceeded <= '1';
-- else
-- MaxPayloadSize_Exceeded <= '0';
-- end if;
--
-- end case;
--
-- end if;
-- end process;
--
--
-- -- --------------------------------
-- -- Calculation of MRS exceed
-- --
-- Trn_Rx_MaxReadReqSize_Exceeded:
-- process ( trn_clk )
-- begin
-- if trn_clk'event and trn_clk = '1' then
--
-- case cfg_MRS_decoded is
--
---- when CONV_STD_LOGIC_VECTOR(1, 6) => -- MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
---- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
---- MaxReadReqSize_Exceeded <= '1';
---- else
---- MaxReadReqSize_Exceeded <= '0';
---- end if;
--
-- when CONV_STD_LOGIC_VECTOR(2, 6) => -- MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(1) then
-- MaxReadReqSize_Exceeded <= '1';
-- else
-- MaxReadReqSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(4, 6) => -- MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(2) then
-- MaxReadReqSize_Exceeded <= '1';
-- else
-- MaxReadReqSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(8, 6) => -- MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(3) then
-- MaxReadReqSize_Exceeded <= '1';
-- else
-- MaxReadReqSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(16, 6) => -- MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(4) then
-- MaxReadReqSize_Exceeded <= '1';
-- else
-- MaxReadReqSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(32, 6) => -- MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- MaxReadReqSize_Exceeded <= '0'; -- !!
--
-- when OTHERS =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
-- MaxReadReqSize_Exceeded <= '1';
-- else
-- MaxReadReqSize_Exceeded <= '0';
-- end if;
--
-- end case;
--
-- end if;
-- end process;
-- ---------------------------------------------------------
---- Pipelining all trn_rx input signals for one clock
---- to get better timing
----
Trn_Rx_Inputs_Delayed:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
trn_rsof_n_r1 <= trn_rsof_n;
trn_reof_n_r1 <= trn_reof_n;
trn_rrem_n_r1 <= trn_rrem_n;
trn_rd_r1 <= trn_rd;
trn_rerrfwd_n_r1 <= trn_rerrfwd_n;
trn_rsrc_rdy_n_r1 <= trn_rsrc_rdy_n;
trn_rdst_rdy_n_r1 <= trn_rdst_rdy_n_i;
trn_rsrc_dsc_n_r1 <= trn_rsrc_dsc_n;
trn_rbar_hit_n_r1 <= trn_rbar_hit_n;
end if;
end process;
-- -----------------------------------------
-- TLP Types
--
TLP_Decision_Registered:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
TLP_is_MRd_H3DW <= '0';
TLP_is_MRdLk_H3DW <= '0';
TLP_is_MRd_H4DW <= '0';
TLP_is_MRdLk_H4DW <= '0';
TLP_is_MWr_H3DW <= '0';
TLP_is_MWr_H4DW <= '0';
TLP_is_IORd <= '0';
TLP_is_IOWr <= '0';
TLP_is_CplD <= '0';
TLP_is_CplDLk <= '0';
TLP_is_Cpl <= '0';
TLP_is_CplLk <= '0';
elsif trn_clk'event and trn_clk = '1' then
-- IORd
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_IO_REQ
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_IORd <= '1';
else
TLP_is_IORd <= '0';
end if;
-- IOWr
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_WITH_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_IO_REQ
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_IOWr <= '1';
else
TLP_is_IOWr <= '0';
end if;
-- MRd
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_MRd_H3DW <= '1';
else
TLP_is_MRd_H3DW <= '0';
end if;
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT4_NO_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_MRd_H4DW <= '1';
else
TLP_is_MRd_H4DW <= '0';
end if;
-- MRdLk
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ_LK
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_MRdLk_H3DW <= '1';
else
TLP_is_MRdLk_H3DW <= '0';
end if;
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT4_NO_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ_LK
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_MRdLk_H4DW <= '1';
else
TLP_is_MRdLk_H4DW <= '0';
end if;
-- MWr
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_WITH_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_MWr_H3DW <= '1';
else
TLP_is_MWr_H3DW <= '0';
end if;
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT4_WITH_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_MWr_H4DW <= '1';
else
TLP_is_MWr_H4DW <= '0';
end if;
-- CplD, Cpl/CplDLk, CplLk
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_WITH_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION
and trn_rd(C_TLP_EP_BIT) ='0'
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_CplD <= '1';
else
TLP_is_CplD <= '0';
end if;
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_WITH_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION_LK
and trn_rd(C_TLP_EP_BIT) ='0'
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_CplDLk <= '1';
else
TLP_is_CplDLk <= '0';
end if;
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION
and trn_rd(C_TLP_EP_BIT) ='0'
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_Cpl <= '1';
else
TLP_is_Cpl <= '0';
end if;
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION_LK
and trn_rd(C_TLP_EP_BIT) ='0'
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_CplLk <= '1';
else
TLP_is_CplLk <= '0';
end if;
end if;
end process;
-- --------------------------------------------------------------------------
-- TLP_is_IORd <= TLP_is_IORd_BAR0 or TLP_is_IORd_BAR1;
-- TLP_is_IOWr <= TLP_is_IOWr_BAR0 or TLP_is_IOWr_BAR1;
-- TLP_is_MRd_H3DW <= TLP_is_MRd_BAR0_H3DW or TLP_is_MRd_BAR1_H3DW;
-- TLP_is_MRdLk_H3DW <= TLP_is_MRdLk_BAR0_H3DW or TLP_is_MRdLk_BAR1_H3DW;
-- TLP_is_MRd_H4DW <= TLP_is_MRd_BAR0_H4DW or TLP_is_MRd_BAR1_H4DW;
-- TLP_is_MRdLk_H4DW <= TLP_is_MRdLk_BAR0_H4DW or TLP_is_MRdLk_BAR1_H4DW;
-- TLP_is_MWr_H3DW <= TLP_is_MWr_BAR0_H3DW or TLP_is_MWr_BAR1_H3DW;
-- TLP_is_MWr_H4DW <= TLP_is_MWr_BAR0_H4DW or TLP_is_MWr_BAR1_H4DW;
-- --------------------------------------------------------------------------
IORd_Type_i <= TLP_is_IORd and Tlp_has_1DW_Length_i;
IOWr_Type_i <= TLP_is_IOWr and Tlp_has_1DW_Length_i;
MRd_Type_i <= (TLP_is_MRd_H3DW and not MaxReadReqSize_Exceeded)
& (TLP_is_MRdLk_H3DW and not MaxReadReqSize_Exceeded)
& (TLP_is_MRd_H4DW and not MaxReadReqSize_Exceeded)
& (TLP_is_MRdLk_H4DW and not MaxReadReqSize_Exceeded)
;
MWr_Type_i <= (TLP_is_MWr_H3DW and not MaxPayloadSize_Exceeded)
& (TLP_is_MWr_H4DW and not MaxPayloadSize_Exceeded)
;
CplD_Type_i <= (TLP_is_CplD and not MaxPayloadSize_Exceeded)
& (TLP_is_Cpl and not MaxPayloadSize_Exceeded)
& (TLP_is_CplDLk and not MaxPayloadSize_Exceeded)
& (TLP_is_CplLk and not MaxPayloadSize_Exceeded)
;
---------------------------------------------------
--
-- Synchronous Registered: TLP_Header_Resolution
--
FSM_TLP_Header_Resolution:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
FSM_TLP_Cnt <= TK_RST;
TLP_Payload_Address_i <= (OTHERS => '1');
MWr_on_Pool <= '0';
CplD_on_Pool_i <= '0';
CplD_on_EB_i <= '0';
trn_rdst_rdy_n_i <= '1';
elsif trn_clk'event and trn_clk = '1' then
-- States transition
case FSM_TLP_Cnt is
when TK_RST =>
FSM_TLP_Cnt <= TK_Idle;
trn_rdst_rdy_n_i <= '1';
when TK_Idle =>
trn_rdst_rdy_n_i <= '0';
if trn_rsof_n='0' and trn_rsrc_rdy_n='0'
and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="10"
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="00"
then
FSM_TLP_Cnt <= TK_MWr_3Hdr_C;
elsif trn_rsof_n='0' and trn_rsrc_rdy_n='0'
and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="11"
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="00"
then
FSM_TLP_Cnt <= TK_MWr_4Hdr_C;
elsif trn_rsof_n='0' and trn_rsrc_rdy_n='0'
and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="10"
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="01"
then
FSM_TLP_Cnt <= TK_CplD_Hdr_C;
else
FSM_TLP_Cnt <= TK_Idle;
end if;
when TK_MWr_3Hdr_C =>
trn_rdst_rdy_n_i <= '0';
if trn_reof_n='0' and trn_reof_n_r1='1' then -- falling edge
FSM_TLP_Cnt <= TK_Idle;
elsif trn_rsrc_rdy_n='1' then
FSM_TLP_Cnt <= TK_MWr_3Hdr_C;
else
FSM_TLP_Cnt <= TK_Body;
end if;
when TK_MWr_4Hdr_C =>
trn_rdst_rdy_n_i <= '0';
if trn_reof_n='0' and trn_reof_n_r1='1' then -- falling edge
FSM_TLP_Cnt <= TK_Idle;
elsif trn_rsrc_rdy_n='1' then
FSM_TLP_Cnt <= TK_MWr_4Hdr_C;
else
FSM_TLP_Cnt <= TK_Body; -- TK_MWr_4Hdr_D;
end if;
when TK_Cpld_Hdr_C =>
trn_rdst_rdy_n_i <= '0';
if trn_reof_n='0' and trn_reof_n_r1='1' then -- falling edge
FSM_TLP_Cnt <= TK_Idle;
elsif trn_rsrc_rdy_n='1' then
FSM_TLP_Cnt <= TK_Cpld_Hdr_C;
else
FSM_TLP_Cnt <= TK_Body;
end if;
when TK_Body =>
if trn_reof_n='0' and trn_reof_n_r1='1' then -- falling edge
FSM_TLP_Cnt <= TK_Idle;
trn_rdst_rdy_n_i <= '0';
else
FSM_TLP_Cnt <= TK_Body;
trn_rdst_rdy_n_i <= ((MWr_on_Pool or CplD_on_Pool_i) and Pool_wrBuf_full)
or ((MWr_on_EB or CplD_on_EB_i) and Link_Buf_full)
;
end if;
when OTHERS =>
FSM_TLP_Cnt <= TK_RST;
end case;
-- MWr_on_Pool
case FSM_TLP_Cnt is
when TK_RST =>
MWr_on_Pool <= '0';
MWr_on_EB <= '0';
when TK_Idle =>
if trn_rsof_n='0' and trn_rsrc_rdy_n='0'
and trn_rd(C_TLP_FMT_BIT_TOP) = '1'
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="00"
then
MWr_on_Pool <= not trn_rbar_hit_n(CINT_DDR_SPACE_BAR);
MWr_on_EB <= not trn_rbar_hit_n(CINT_FIFO_SPACE_BAR);
else
MWr_on_Pool <= MWr_on_Pool;
MWr_on_EB <= MWr_on_EB;
end if;
when OTHERS =>
MWr_on_Pool <= MWr_on_Pool;
MWr_on_EB <= MWr_on_EB;
end case;
-- CplD_on_Pool
case FSM_TLP_Cnt is
when TK_RST =>
CplD_on_Pool_i <= '0';
CplD_on_EB_i <= '0';
when TK_Idle =>
CplD_on_Pool_i <= '0';
CplD_on_EB_i <= '0';
when TK_CplD_Hdr_C =>
-- if trn_rsof_n='0' and trn_rsrc_rdy_n='0'
-- and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="10"
-- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="01"
-- then
CplD_on_Pool_i <= not trn_rd(C_CPLD_TAG_BIT_TOP) and not trn_rd(C_CPLD_TAG_BIT_TOP-1);
CplD_on_EB_i <= not trn_rd(C_CPLD_TAG_BIT_TOP) and trn_rd(C_CPLD_TAG_BIT_TOP-1);
-- else
-- CplD_on_Pool_i <= CplD_on_Pool_i;
-- CplD_on_EB_i <= CplD_on_EB_i;
-- end if;
when OTHERS =>
CplD_on_Pool_i <= CplD_on_Pool_i;
CplD_on_EB_i <= CplD_on_EB_i;
end case;
-- CplD_Tag
case FSM_TLP_Cnt is
when TK_RST =>
CplD_Tag_i <= (OTHERS => '1');
-- when TK_Idle =>
-- CplD_Tag_i <= CplD_Tag_i;
when TK_CplD_Hdr_C =>
-- if trn_reof_n='0' then
-- CplD_Tag_i <= (OTHERS => '1');
-- els
if trn_rsrc_rdy_n='0' -- and trn_rdst_rdy_n='0'
then
CplD_Tag_i <= trn_rd(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT);
else
CplD_Tag_i <= CplD_Tag_i;
end if;
when OTHERS =>
CplD_Tag_i <= CplD_Tag_i;
end case;
end if;
end process;
---------------------------------------------------
--
-- Synchronous Registered: CplD_is_the_Last
--
Syn_Calc_CplD_is_the_Last:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
CplD_is_the_Last_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rsof_n='0' and trn_rsrc_rdy_n='0' then
if trn_rd(C_TLP_TYPE_BIT_TOP-1)= '1'
and (trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2)=trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)
or trn_rd(1 downto 0)=CONV_STD_LOGIC_VECTOR(1, 2)) -- Zero-length
then
CplD_is_the_Last_i <= '1';
else
CplD_is_the_Last_i <= '0';
end if;
else
CplD_is_the_Last_i <= CplD_is_the_Last_i;
end if;
end if;
end process;
---------------------------------------------------
--
-- Synchronous Delay: FSM_TLP_Cnt
--
SynDelay_FSM_TLP_Cnt:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
FSM_TLP_Cnt_r1 <= FSM_TLP_Cnt;
end if;
end process;
---- --------------------------------------------------------------------------
--
-- TLP_Address_sig <= '0' & trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
--
---------------------------------------------------------------------------------------
---- Calculates the Address-Length combination carry-in
-- TLP_Calc_CarryIn_ALC:
-- process ( trn_clk, trn_reset_n)
-- begin
-- if trn_reset_n = '0' then
-- CarryIn_ALC <= (OTHERS =>'0');
-- elsif trn_clk'event and trn_clk = '1' then
-- CarryIn_ALC <= ('0'& TLP_DW_Length_i) + TLP_Address_sig;
-- end if;
-- end process;
--
--
-- ---------------------------------------------------
-- --
-- -- Synchronous Registered: Tlp_straddles_4KB
-- --
-- FSM_Output_Tlp_straddles_4KB:
-- process ( trn_clk, trn_reset_n)
-- begin
-- if trn_reset_n = '0' then
-- Tlp_straddles_4KB_i <= '0';
--
-- elsif trn_clk'event and trn_clk = '1' then
--
-- case FSM_TLP_Cnt_r1 is
--
-- when TK_RST =>
-- Tlp_straddles_4KB_i <= '0';
--
-- when TK_MWr_3Hdr_C =>
-- if Tlp_has_4KB_i='1'
-- and trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
-- /=C_ALL_ZEROS(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
-- then
-- Tlp_straddles_4KB_i <= '1';
-- else
-- Tlp_straddles_4KB_i <= CarryIn_ALC(C_TLP_FLD_WIDTH_OF_LENG);
-- end if;
--
-- when TK_MWr_4Hdr_D =>
-- if Tlp_has_4KB_i='1'
-- and trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
-- /=C_ALL_ZEROS(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
-- then
-- Tlp_straddles_4KB_i <= '1';
-- else
-- Tlp_straddles_4KB_i <= CarryIn_ALC(C_TLP_FLD_WIDTH_OF_LENG);
-- end if;
--
--
-- when OTHERS =>
-- Tlp_straddles_4KB_i <= Tlp_straddles_4KB_i;
--
-- end case;
--
-- end if;
-- end process;
--
-- ---------------------------------------------------------
-- To Cpl/D channel as indicator when ReqID matched
--
TLP_ReqID_Matched:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
Req_ID_Match_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rd(C_CPLD_REQID_BIT_TOP downto C_CPLD_REQID_BIT_BOT)=localID then
Req_ID_Match_i <= '1';
else
Req_ID_Match_i <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------
-- To Cpl/D channel as indicator when us Tag_Descriptor matched
--
TLP_usDexTag_Matched:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
usDex_Tag_Matched_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rd(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=usDMA_dex_Tag then
usDex_Tag_Matched_i <= '1';
else
usDex_Tag_Matched_i <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------
-- To Cpl/D channel as indicator when ds Tag_Descriptor matched
--
TLP_dsDexTag_Matched:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
dsDex_Tag_Matched_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rd(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=dsDMA_dex_Tag then
dsDex_Tag_Matched_i <= '1';
else
dsDex_Tag_Matched_i <= '0';
end if;
end if;
end process;
end architecture Behavioral;
|
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_163 is
generic(
NUM_BITS : positive := 163
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
x_div_y : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_163 is
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
constant p : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- control signals
signal CASO: std_logic_vector(1 downto 0);
signal c_4, c_5,c_6,a_greater_b,a_eq_b: std_logic;
signal CA, CB : STD_LOGIC_VECTOR(7 downto 0);
signal U, A, V, B,X2, Y2, temp1, toA, toB, toU, toV: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
type CurrentState_type is (END_STATE, LOAD1, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
X2 <= x & '0';
Y2 <= y & '0';
caso <= "01" when (A(0) = '1' and B(0) = '0') or CurrentState = LOAD1 else
"10" when A(0) = '0' else
"11";
c_5 <= '0' when rst = '1' or currentState = LOAD1 else
'1';
c_6 <= '1' when CurrentState = LOAD1 else
'0';
a_greater_b <= '1' when CA > CB else
'0';
a_eq_b <= '1' when A = B else
'0';
--a_eq_b <= '1' when CA = "00000000" else
-- '0';
c_4 <= '0' when CurrentState = Load1 or temp1(0) = '0' else
'1';
celda_reg_A: entity celda_a(behave)
port map( A, B,caso(1), caso(0), toA);
celda_reg_U: entity celda_U(behave)
port map(U, V, caso(1), caso(0), temp1);
celda_reg_mod_P: entity mod_P(behave)
port map(temp1, P, c_4, toU);
celda_reg_B: entity celda_B(behave)
port map(toA,P,Y2,c_5,c_6, toB);
celda_reg_V: entity celda_v(behave)
port map(toU,X2,c_5,c_6,toV);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= (others => '0');
U <= (others => '0');
B <= toB;
V <= toV;
CA <= "10100010" ;
CB <= "10100011" ;
x_div_y <= (others => '0');
done <= '0';
currentState <= LOAD1;
else
case currentState is
-----------------------------------------------------------------------------------
when LOAD1 =>
A <= toA;
U <= toU;
B <= toB;
V <= toV;
currentState <= Cycle;
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
x_div_y <= U(NUM_BITS-1 downto 0);
elsif CASO = "10" then
A <= toA;
CA <= CA-1;
U <= toU;
elsif CASO = "01" then
B <= toB;
CB <= CB -1;
V <= toV;
elsif a_greater_b = '1' then
A <= toA;
CA <= CA-1;
U <= toU;
else
B <= toB;
CB <= CB-1;
V <= toV;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave; |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 01/07/2015 - 19:14
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY INST IS
PORT(
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END INST;
ARCHITECTURE ARC_INST OF INST IS
--DEVE SER 0 TO 255 O ARRAY PARA FACILITAR A LEITURA DO PROGRAMA EM ORDEM CRESCENTE
TYPE MEMORY IS ARRAY (0 TO 255) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL PROGRAM : MEMORY := (X"3C010002",X"20220004",X"01095024", X"01485025" ,X"014a5020",X"01285022",X"0149582a",X"00004820",X"11490002",X"01284820",X"08100006",X"ae2a0000",X"8e300000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000" );
BEGIN
--O FATOR - X"00400000" DEVIDO AO INCIO DAS INSTRUES NO SOFTWARE MARS
OUT_A <= PROGRAM(TO_INTEGER((UNSIGNED(IN_A) - X"00400000") SRL 2));
END ARC_INST;
|
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: [email protected]
-- Date : 01/07/2015 - 19:14
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY INST IS
PORT(
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END INST;
ARCHITECTURE ARC_INST OF INST IS
--DEVE SER 0 TO 255 O ARRAY PARA FACILITAR A LEITURA DO PROGRAMA EM ORDEM CRESCENTE
TYPE MEMORY IS ARRAY (0 TO 255) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL PROGRAM : MEMORY := (X"3C010002",X"20220004",X"01095024", X"01485025" ,X"014a5020",X"01285022",X"0149582a",X"00004820",X"11490002",X"01284820",X"08100006",X"ae2a0000",X"8e300000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000" );
BEGIN
--O FATOR - X"00400000" DEVIDO AO INCIO DAS INSTRUES NO SOFTWARE MARS
OUT_A <= PROGRAM(TO_INTEGER((UNSIGNED(IN_A) - X"00400000") SRL 2));
END ARC_INST;
|
entity MaliDek2 is port (
a0, e: in std_logic;
i0, i1: out std_logic);
end MaliDek2;
architecture arch of MaliDek2 is
begin
i0 <= e and not a0;
i1 <= e and a0;
end arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: uart
-- File: uart.vhd
-- Authors: Jiri Gaisler - Gaisler Research
-- Marko Isomaki - Gaisler Research
-- Description: Asynchronous UART. Implements 8-bit data frame with one stop-bit.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity apbuart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
console : integer := 0;
pirq : integer := 0;
parity : integer := 1;
flow : integer := 1;
fifosize : integer range 1 to 32 := 1;
abits : integer := 8;
sbits : integer range 12 to 32 := 12);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in uart_in_type;
uarto : out uart_out_type);
end;
architecture rtl of apbuart is
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_APBUART, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, cparity, stopbit);
type txfsmtype is (idle, data, cparity, stopbit);
type fifo is array (0 to fifosize - 1) of std_logic_vector(7 downto 0);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
txen : std_ulogic; -- transmitter enabled
rirqen : std_ulogic; -- receiver irq enable
tirqen : std_ulogic; -- transmitter irq enable
parsel : std_ulogic; -- parity select
paren : std_ulogic; -- parity select
flow : std_ulogic; -- flow control enable
loopb : std_ulogic; -- loop back mode enable
debug : std_ulogic; -- debug mode enable
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
tsemptyirqen : std_ulogic; -- generate irq when tx shift register is empty
break : std_ulogic; -- break detected
breakirqen : std_ulogic; -- generate irq when break has been received
ovf : std_ulogic; -- receiver overflow
parerr : std_ulogic; -- parity error
frame : std_ulogic; -- framing error
ctsn : std_logic_vector(1 downto 0); -- clear to send
rtsn : std_ulogic; -- request to send
extclken : std_ulogic; -- use external baud rate clock
extclk : std_ulogic; -- rising edge detect register
rhold : fifo;
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(10 downto 0);
thold : fifo;
irq : std_ulogic; -- tx/rx interrupt (internal)
irqpend : std_ulogic; -- pending irq for delayed rx irq
delayirqen : std_ulogic; -- enable delayed rx irq
tpar : std_ulogic; -- tx data parity (internal)
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_logic_vector(1 downto 0); -- rx delay
dpar : std_ulogic; -- rx data parity (internal)
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(sbits-1 downto 0);
brate : std_logic_vector(sbits-1 downto 0);
rxf : std_logic_vector(4 downto 0); -- rx data filtering buffer
txd : std_ulogic; -- transmitter data
rfifoirqen : std_ulogic; -- receiver fifo interrupt enable
tfifoirqen : std_ulogic; -- transmitter fifo interrupt enable
irqcnt : std_logic_vector(5 downto 0); -- delay counter for rx irq
--fifo counters
rwaddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
rraddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
traddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
twaddr : std_logic_vector(log2x(fifosize) - 1 downto 0);
rcnt : std_logic_vector(log2x(fifosize) downto 0);
tcnt : std_logic_vector(log2x(fifosize) downto 0);
end record;
constant rcntzero : std_logic_vector(log2x(fifosize) downto 0) := (others => '0');
constant addrzero : std_logic_vector(log2x(fifosize)-1 downto 0) := (others => '0');
constant sbitszero : std_logic_vector(sbits-1 downto 0) := (others => '0');
constant fifozero : fifo := (others => (others => '0'));
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : uartregs :=
(rxen => '0', txen => '0', rirqen => '0', tirqen => '0', parsel => '0',
paren => '0', flow => '0', loopb => '0', debug => '0', rsempty => '1',
tsempty => '1', tsemptyirqen => '0', break => '0', breakirqen => '0',
ovf => '0', parerr => '0', frame => '0', ctsn => (others => '0'),
rtsn => '1', extclken => '0', extclk => '0', rhold => fifozero,
rshift => (others => '0'), tshift => (others => '1'), thold => fifozero,
irq => '0', irqpend => '0', delayirqen => '0', tpar => '0', txstate => idle,
txclk => (others => '0'), txtick => '0', rxstate => idle,
rxclk => (others => '0'), rxdb => (others => '0'), dpar => '0',rxtick => '0',
tick => '0', scaler => sbitszero, brate => sbitszero, rxf => (others => '0'),
txd => '0', rfifoirqen => '0', tfifoirqen => '0', irqcnt => (others => '0'),
rwaddr => addrzero, rraddr => addrzero, traddr => addrzero, twaddr => addrzero,
rcnt => rcntzero, tcnt => rcntzero);
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(sbits-1 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable rxd, ctsn : std_ulogic;
variable irq : std_logic_vector(NAHBIRQ-1 downto 0);
variable paddress : std_logic_vector(7 downto 2);
variable v : uartregs;
variable thalffull : std_ulogic;
variable rhalffull : std_ulogic;
variable rfull : std_ulogic;
variable tfull : std_ulogic;
variable dready : std_ulogic;
variable thempty : std_ulogic;
--pragma translate_off
variable L1 : line;
variable CH : character;
variable FIRST : boolean := true;
variable pt : time := 0 ns;
--pragma translate_on
begin
v := r; irq := (others => '0'); irq(pirq) := r.irq;
v.irq := '0'; v.txtick := '0'; v.rxtick := '0'; v.tick := '0';
rdata := (others => '0'); v.rxdb(1) := r.rxdb(0);
dready := '0'; thempty := '1'; thalffull := '1'; rhalffull := '0';
v.ctsn := r.ctsn(0) & uarti.ctsn;
paddress := (others => '0');
paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
if fifosize = 1 then
dready := r.rcnt(0); rfull := dready; tfull := r.tcnt(0);
thempty := not tfull;
else
tfull := r.tcnt(log2x(fifosize)); rfull := r.rcnt(log2x(fifosize));
if (r.rcnt(log2x(fifosize)) or r.rcnt(log2x(fifosize) - 1)) = '1' then
rhalffull := '1';
end if;
if ((r.tcnt(log2x(fifosize)) or r.tcnt(log2x(fifosize) - 1))) = '1' then
thalffull := '0';
end if;
if r.rcnt /= rcntzero then dready := '1'; end if;
if r.tcnt /= rcntzero then thempty := '0'; end if;
end if;
-- scaler
scaler := r.scaler - 1;
if (r.rxen or r.txen) = '1' then
v.scaler := scaler;
v.tick := scaler(sbits-1) and not r.scaler(sbits-1);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- optional external uart clock
v.extclk := uarti.extclk;
if r.extclken = '1' then v.tick := r.extclk and not uarti.extclk; end if;
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddress(7 downto 2) is
when "000000" =>
rdata(7 downto 0) := r.rhold(conv_integer(r.rraddr));
if fifosize = 1 then v.rcnt(0) := '0';
else
if r.rcnt /= rcntzero then
v.rraddr := r.rraddr + 1; v.rcnt := r.rcnt - 1;
end if;
end if;
when "000001" =>
if fifosize /= 1 then
rdata (26 + log2x(fifosize) downto 26) := r.rcnt;
rdata (20 + log2x(fifosize) downto 20) := r.tcnt;
rdata (10 downto 7) := rfull & tfull & rhalffull & thalffull;
end if;
rdata(6 downto 0) := r.frame & r.parerr & r.ovf &
r.break & thempty & r.tsempty & dready;
--pragma translate_off
if CONSOLE = 1 then rdata(2 downto 1) := "11"; end if;
--pragma translate_on
when "000010" =>
if fifosize > 1 then
rdata(31) := '1';
end if;
rdata(14) := r.tsemptyirqen;
rdata(13) := r.delayirqen;
rdata(12) := r.breakirqen;
rdata(11) := r.debug;
if fifosize /= 1 then
rdata(10 downto 9) := r.rfifoirqen & r.tfifoirqen;
end if;
rdata(8 downto 0) := r.extclken & r.loopb &
r.flow & r.paren & r.parsel & r.tirqen & r.rirqen & r.txen & r.rxen;
when "000011" =>
rdata(sbits-1 downto 0) := r.brate;
when "000100" =>
-- Read TX FIFO.
if r.debug = '1' and r.tcnt /= rcntzero then
rdata(7 downto 0) := r.thold(conv_integer(r.traddr));
if fifosize = 1 then
v.tcnt(0) := '0';
else
v.traddr := r.traddr + 1;
v.tcnt := r.tcnt - 1;
end if;
end if;
when others =>
null;
end case;
end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(7 downto 2) is
when "000000" =>
when "000001" =>
v.frame := apbi.pwdata(6);
v.parerr := apbi.pwdata(5);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "000010" =>
v.tsemptyirqen := apbi.pwdata(14);
v.delayirqen := apbi.pwdata(13);
v.breakirqen := apbi.pwdata(12);
v.debug := apbi.pwdata(11);
if fifosize /= 1 then
v.rfifoirqen := apbi.pwdata(10);
v.tfifoirqen := apbi.pwdata(9);
end if;
v.extclken := apbi.pwdata(8);
v.loopb := apbi.pwdata(7);
v.flow := apbi.pwdata(6);
v.paren := apbi.pwdata(5);
v.parsel := apbi.pwdata(4);
v.tirqen := apbi.pwdata(3);
v.rirqen := apbi.pwdata(2);
v.txen := apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "000011" =>
v.brate := apbi.pwdata(sbits-1 downto 0);
v.scaler := apbi.pwdata(sbits-1 downto 0);
when "000100" =>
-- Write RX fifo and generate irq
if flow /= 0 then
v.rhold(conv_integer(r.rwaddr)) := apbi.pwdata(7 downto 0);
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
if r.debug = '1' then
v.irq := v.irq or r.rirqen;
end if;
end if;
when others =>
null;
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk;
v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk;
v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
if (r.rxtick and r.delayirqen) = '1' then
v.irqcnt := v.irqcnt + 1;
end if;
if r.irqcnt(5 downto 4) = "11" then
v.irq := v.irq or (r.delayirqen and r.irqpend); -- make sure no tx irqs are lost !
v.irqpend := '0';
end if;
-- filter rx data
-- v.rxf := r.rxf(6 downto 0) & uarti.rxd;
-- if ((r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) &
-- r.rxf(7)) = r.rxf(6 downto 0))
-- then v.rxdb(0) := r.rxf(7); end if;
v.rxf(1 downto 0) := r.rxf(0) & uarti.rxd; -- meta-stability filter
if r.tick = '1' then
v.rxf(4 downto 2) := r.rxf(3 downto 1);
end if;
v.rxdb(0) := (r.rxf(4) and r.rxf(3)) or (r.rxf(4) and r.rxf(2)) or
(r.rxf(3) and r.rxf(2));
-- loop-back mode
if r.loopb = '1' then
v.rxdb(0) := r.tshift(0); ctsn := dready and not r.rsempty;
elsif (flow = 1) then ctsn := r.ctsn(1); else ctsn := '0'; end if;
rxd := r.rxdb(0);
-- transmitter operation
case r.txstate is
when idle => -- idle state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if ((not r.debug and r.txen and (not thempty) and r.txtick) and
((not ctsn) or not r.flow)) = '1' then
v.txstate := data;
v.tpar := r.parsel; v.tsempty := '0';
v.txclk := "00" & r.tick; v.txtick := '0';
v.tshift := "10" & r.thold(conv_integer(r.traddr)) & '0';
if fifosize = 1 then
v.irq := r.irq or r.tirqen; v.tcnt(0) := '0';
else
v.traddr := r.traddr + 1;
v.tcnt := r.tcnt - 1;
end if;
end if;
when data => -- transmit data frame
if r.txtick = '1' then
v.tpar := r.tpar xor r.tshift(1);
v.tshift := '1' & r.tshift(10 downto 1);
if r.tshift(10 downto 1) = "1111111110" then
if r.paren = '1' then
v.tshift(0) := r.tpar; v.txstate := cparity;
else
v.tshift(0) := '1'; v.txstate := stopbit;
end if;
end if;
end if;
when cparity => -- transmit parity bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := stopbit;
end if;
when stopbit => -- transmit stop bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := idle;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(4 downto 2) is
when "000" =>
if fifosize = 1 then
v.thold(0) := apbi.pwdata(7 downto 0); v.tcnt(0) := '1';
else
v.thold(conv_integer(r.twaddr)) := apbi.pwdata(7 downto 0);
if not (tfull = '1') then
v.twaddr := r.twaddr + 1; v.tcnt := v.tcnt + 1;
end if;
end if;
--pragma translate_off
if CONSOLE = 1 then
if first then L1:= new string'(""); first := false; end if; --'
if apbi.penable'event then --'
CH := character'val(conv_integer(apbi.pwdata(7 downto 0))); --'
if CH = CR then
std.textio.writeline(OUTPUT, L1);
elsif CH /= LF then
std.textio.write(L1,CH);
end if;
pt := now;
end if;
end if;
--pragma translate_on
when others => null;
end case;
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((r.rsempty = '0') and not (rfull = '1')) then
v.rsempty := '1';
v.rhold(conv_integer(r.rwaddr)) := r.rshift;
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
end if;
if (r.rxen and r.rxdb(1) and (not rxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if rxd = '0' then
v.rshift := rxd & r.rshift(7 downto 1); v.rxstate := data;
v.dpar := r.parsel;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd;
v.rshift := rxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
if r.paren = '1' then v.rxstate := cparity;
else v.rxstate := stopbit; v.dpar := '0'; end if;
end if;
end if;
when cparity => -- receive parity bit
if r.rxtick = '1' then
v.dpar := r.dpar xor rxd; v.rxstate := stopbit;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
if r.delayirqen = '0' then
v.irq := v.irq or r.rirqen; -- make sure no tx irqs are lost !
end if;
if rxd = '1' then
if r.delayirqen = '1' then
v.irqpend := r.rirqen; v.irqcnt := (others => '0');
end if;
v.parerr := r.parerr or r.dpar; v.rsempty := r.dpar;
if not (rfull = '1') and (r.dpar = '0') then
v.rsempty := '1';
v.rhold(conv_integer(r.rwaddr)) := r.rshift;
if fifosize = 1 then v.rcnt(0) := '1';
else v.rwaddr := r.rwaddr + 1; v.rcnt := v.rcnt + 1; end if;
end if;
else
if r.rshift = "00000000" then
v.break := '1';
v.irq := v.irq or r.breakirqen;
else v.frame := '1'; end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
end case;
if r.rxtick = '1' then
v.rtsn := (rfull and not r.rsempty) or r.loopb;
end if;
v.txd := r.tshift(0) or r.loopb or r.debug;
if fifosize /= 1 then
if thempty = '0' and v.tcnt = rcntzero then
v.irq := v.irq or r.tirqen;
end if;
v.irq := v.irq or (r.tfifoirqen and r.txen and thalffull);
v.irq := v.irq or (r.rfifoirqen and r.rxen and rhalffull);
if (r.rfifoirqen and r.rxen and rhalffull) = '1' then
v.irqpend := '0';
end if;
end if;
v.irq := v.irq or (r.tsemptyirqen and v.tsempty and not r.tsempty);
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.frame := RES.frame; v.rsempty := RES.rsempty;
v.parerr := RES.parerr; v.ovf := RES.ovf; v.break := RES.break;
v.tsempty := RES.tsempty; v.txen := RES.txen; v.rxen := RES.rxen;
v.txstate := RES.txstate; v.rxstate := RES.rxstate; v.tshift(0) := RES.tshift(0);
v.extclken := RES.extclken; v.rtsn := RES.rtsn; v.flow := RES.flow;
v.txclk := RES.txclk; v.rxclk := RES.rxclk;
v.rcnt := RES.rcnt; v.tcnt := RES.tcnt;
v.rwaddr := RES.rwaddr; v.twaddr := RES.twaddr;
v.rraddr := RES.rraddr; v.traddr := RES.traddr;
v.irqcnt := RES.irqcnt; v.irqpend := RES.irqpend;
end if;
-- update registers
rin <= v;
-- drive outputs
uarto.txd <= r.txd; uarto.rtsn <= r.rtsn;
uarto.scaler <= (others => '0');
uarto.scaler(sbits-1 downto 0) <= r.scaler;
apbo.prdata <= rdata; apbo.pirq <= irq;
apbo.pindex <= pindex;
uarto.txen <= r.txen; uarto.rxen <= r.rxen;
uarto.flow <= '0';
end process;
apbo.pconfig <= pconfig;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
-- Sync. registers not reset
r.ctsn <= rin.ctsn;
r.rxf <= rin.rxf;
end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("apbuart" & tost(pindex) &
": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
", irq " & tost(pirq) & ", scaler bits " & tost(sbits));
-- pragma translate_on
end;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ENTITY ball_wa IS
END ENTITY ball_wa;
ARCHITECTURE simple OF ball_wa IS
QUANTITY v: real;
QUANTITY s: real;
CONSTANT G: real := 9.81;
CONSTANT Air_Res: real := 0.1;
SIGNAL damping: real := -0.7;
signal v_at_impact : real:= 0.0;
signal impact: boolean;
BEGIN
if domain = quiescent_domain use
v == 0.0;
s == 30.0;
elsif impact use
v == damping*v_at_impact;
s == 0.0;
else
s'dot == v;
v'dot == -G;
end use;
process begin
wait until not s'above(0.0);
if v < -1.0e-9 then
v_at_impact <= v;
impact <= true, false after 1 us;
else
damping <= 0.0;
impact <= true;
end if;
end process;
break on impact;
END architecture simple;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ENTITY ball_wa IS
END ENTITY ball_wa;
ARCHITECTURE simple OF ball_wa IS
QUANTITY v: real;
QUANTITY s: real;
CONSTANT G: real := 9.81;
CONSTANT Air_Res: real := 0.1;
SIGNAL damping: real := -0.7;
signal v_at_impact : real:= 0.0;
signal impact: boolean;
BEGIN
if domain = quiescent_domain use
v == 0.0;
s == 30.0;
elsif impact use
v == damping*v_at_impact;
s == 0.0;
else
s'dot == v;
v'dot == -G;
end use;
process begin
wait until not s'above(0.0);
if v < -1.0e-9 then
v_at_impact <= v;
impact <= true, false after 1 us;
else
damping <= 0.0;
impact <= true;
end if;
end process;
break on impact;
END architecture simple;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
ENTITY ball_wa IS
END ENTITY ball_wa;
ARCHITECTURE simple OF ball_wa IS
QUANTITY v: real;
QUANTITY s: real;
CONSTANT G: real := 9.81;
CONSTANT Air_Res: real := 0.1;
SIGNAL damping: real := -0.7;
signal v_at_impact : real:= 0.0;
signal impact: boolean;
BEGIN
if domain = quiescent_domain use
v == 0.0;
s == 30.0;
elsif impact use
v == damping*v_at_impact;
s == 0.0;
else
s'dot == v;
v'dot == -G;
end use;
process begin
wait until not s'above(0.0);
if v < -1.0e-9 then
v_at_impact <= v;
impact <= true, false after 1 us;
else
damping <= 0.0;
impact <= true;
end if;
end process;
break on impact;
END architecture simple;
|
architecture RTL of TxDataStateMachine is
-- States of the TxDataStateMachine
type StatesTX is(stIdle, stLoad, stShift, stParityWrite, stStopWrite);
-- Signal Declartation
-- Signal for the States
signal CurrentState : StatesTX;
signal NextState : StatesTX;
-- Signal for the DataBits
signal DataBitsCounterMax : STD_LOGIC_VECTOR((BitSelCounterSize-1) downto 0);
signal DataBitsCounter : STD_LOGIC_VECTOR((BitSelCounterSize-1) downto 0);
signal ParallelLoadedData : STD_LOGIC_VECTOR((MaxDataWidth-1) downto 0);
--Signals for TxD output
signal TxD_pre : STD_LOGIC;
signal TxDEnable : STD_LOGIC;
signal DataBitsCounterResetEn : STD_LOGIC;
signal DataBitsCounterIncEn : STD_LOGIC;
signal LoadData : STD_LOGIC;
--Signals to generate/manage Parity Bit
signal ParityBit : STD_LOGIC;
signal ParityBitCalcEnable : STD_LOGIC;
signal ParityReset : STD_LOGIC;
begin
StateReg: process(Clk_i, Reset_i_n)
begin
if Reset_i_n ='0' then
CurrentState <= stIdle;
DataBitsCounter <= (others => '0');
ParallelLoadedData <= (others => '0');
elsif rising_edge(Clk_i) then
CurrentState <= NextState;
if DataBitsCounterResetEn = '1' then
DataBitsCounter <= (others => '0');
elsif DataBitsCounterIncEn = '1' then
DataBitsCounter <= std_logic_vector(unsigned(DataBitsCounter) + 1);
end if;
if LoadData = '1' then
ParallelLoadedData <= ParallelData_i;
end if;
end if;
end process StateReg;
CombLogic: process(CurrentState, FifoEmpty_i, ParallelData_i, ParityBit ,ParallelLoadedData ,ParityEvenOdd_i, BaudClk_i, DataBitsCounter, DataBitsCounterMax, ParityOn_i)
variable outputBit : std_logic;
begin
case CurrentState is
when stIdle =>
-- reset counter for next state
DataBitsCounterIncEn <= '0';
DataBitsCounterResetEn <= '1';
-- Set outputs
LoadData <= '0';
BGEnable_o <= '0';
TxDEnable <= '0';
-- Parity
ParityBitCalcEnable <= '0';
ParityReset <= '0';
--Data available?
if FifoEmpty_i = '0' then
--start bit
TxD_pre <= '0';
NextState <= stLoad;
else
TxD_pre <= '1';
NextState <= CurrentState;
end if;
when stLoad =>
-- reset counter for next state
DataBitsCounterIncEn <= '0';
DataBitsCounterResetEn <= '1';
-- outputs
LoadData <= '1';
-- Start BaudClk
BGEnable_o <= '1';
-- Send StartBit
TxD_pre <= '0';
TxDEnable <= '1';
-- Parity
ParityBitCalcEnable <= '0';
ParityReset <= '1';
NextState <= stShift;
-- Start bit is set, baudgen is enabled
-- now reacting on the rising edge of Baudgen
-- First rising edge at Start bit is not seen in next state
-- because of a delay of one clock cycle (Clk_i)
when stShift =>
-- counter
DataBitsCounterResetEn <= '0';
-- outputs
LoadData <= '0';
BGEnable_o <= '1';
TxDEnable <= BaudClk_i;
-- Parity
ParityReset <= '0';
-- prevent from indexing out of bound
if (DataBitsCounter < DatabitsCounterMax) then
outputBit := ParallelLoadedData(to_integer(unsigned(DataBitsCounter)));
else
outputBit := '1';
end if;
--output to write
if BaudClk_i = '1' then
TxD_pre <= outputBit;
-- everything is send
if DataBitsCounter = DataBitsCounterMax then
-- reset counter in state before
DataBitsCounterIncEn <= '0';
ParityBitCalcEnable <= '0';
if ParityOn_i = '1' then
-- parity
NextState <= stParityWrite;
TxD_pre <= ParityBit;
else
-- stop bit
NextState <= stStopWrite;
TxD_pre <= '1';
end if;
else
TxD_pre <= outputBit;
DataBitsCounterIncEn <= '1';
ParityBitCalcEnable <= '1';
NextState <= CurrentState;
end if;
else
TxD_pre <= outputBit;
DataBitsCounterIncEn <= '0';
ParityBitCalcEnable <= '0';
NextState <= CurrentState;
end if;
when stParityWrite =>
-- reset counter for next state
DataBitsCounterIncEn <= '0';
DataBitsCounterResetEn <= '1';
-- set outputs
LoadData <= '0';
BGEnable_o <= '1';
TxDEnable <= BaudClk_i;
-- parity
ParityReset <= '0';
ParityBitCalcEnable <= '0';
-- end of parity bit reached?
if BaudClk_i = '1' then
TxD_pre <= '1';
NextState <= stStopWrite;
else
TxD_pre <= ParityBit;
NextState <= CurrentState;
end if;
when stStopWrite =>
-- reset counter for next state
DataBitsCounterIncEn <= '0';
DataBitsCounterResetEn <= '1';
-- set outputs
LoadData <= '0';
TxDEnable <= BaudClk_i;
-- parity
ParityReset <= '0';
ParityBitCalcEnable <= '0';
if BaudClk_i = '1' then
-- more data to send available
if FifoEmpty_i = '0' then
-- send start bit
TxD_pre <= '0';
BGEnable_o <= '1';
NextState <= stLoad;
else
TxD_pre <= '1';
BGEnable_o <= '0';
NextState <= stIdle;
end if;
else
-- send stop bit
TxD_pre <= '1';
BGEnable_o <= '1';
NextState <= CurrentState;
end if;
end case;
end process CombLogic;
TxDProcess: process (Clk_i, Reset_i_n)
begin
if Reset_i_n = '0' then
TxD_o <= '1';
elsif rising_edge(Clk_i) then
if TxDEnable = '1' then
TxD_o <= TxD_pre;
end if;
end if;
end process TxDProcess;
ParityBitPr: process (Clk_i, Reset_i_n, ParityEvenOdd_i)
begin
if Reset_i_n = '0' then
ParityBit <= '0';
elsif rising_edge(Clk_i) then
if ParityReset = '1' then
if ParityEvenOdd_i = Even then
ParityBit <= '0';
else
ParityBit <= '1';
end if;
elsif ParityBitCalcEnable = '1' then
ParityBit <= ParityBit xor TxD_pre;
else
ParityBit <= ParityBit;
end if;
end if;
end process ParityBitPr;
--combinatory part
LoadData_o <= LoadData;
DataBitsCounterMax <= "0101" when (BitSelect_i = Sel5Bits) else -- 5
"0110" when (BitSelect_i = Sel6Bits) else -- 6
"0111" when (BitSelect_i = Sel7Bits) else -- 7
"1000" when (BitSelect_i = Sel8Bits) else -- 8
"1001" when (BitSelect_i = Sel9Bits) else -- 9
(others => '-');
end RTL;
|
library verilog;
use verilog.vl_types.all;
entity clock is
port(
clk : out vl_logic
);
end clock;
|
library verilog;
use verilog.vl_types.all;
entity clock is
port(
clk : out vl_logic
);
end clock;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.vvc_cmd_pkg.all;
package td_target_support_pkg is
signal global_vvc_ack : std_logic; -- ACK on global triggers
signal global_vvc_busy : std_logic := 'L'; -- ACK on global triggers
shared variable protected_multicast_semaphore : t_protected_semaphore;
shared variable protected_acknowledge_index : t_protected_acknowledge_cmd_idx;
type t_vvc_target_record_unresolved is record -- VVC dedicated to assure signature differences between equal common methods
trigger : std_logic;
vvc_name : string(1 to C_LOG_SCOPE_WIDTH-2); -- as scope is vvc_name & ',' and number
vvc_instance_idx : integer;
vvc_channel : t_channel;
end record;
constant C_VVC_TARGET_RECORD_DEFAULT : t_vvc_target_record_unresolved := (
trigger => 'L',
vvc_name => (others => '?'),
vvc_instance_idx => -1,
vvc_channel => NA
); --
type t_vvc_target_record_drivers is array (natural range <> ) of t_vvc_target_record_unresolved;
function resolved ( input_vector : t_vvc_target_record_drivers) return t_vvc_target_record_unresolved;
subtype t_vvc_target_record is resolved t_vvc_target_record_unresolved;
-------------------------------------------
-- to_string
-------------------------------------------
-- to_string method for VVC name, instance and channel
-- - If channel is set to NA, it will not be included in the string
function to_string(
value : t_vvc_target_record;
vvc_instance : integer := -1;
vvc_channel : t_channel := NA
) return string;
-------------------------------------------
-- format_command_idx
-------------------------------------------
-- Returns an encapsulated command index as string
impure function format_command_idx(
command : t_vvc_cmd_record -- VVC dedicated
) return string;
-------------------------------------------
-- send_command_to_vvc
-------------------------------------------
-- Sends command to VVC and waits for ACK or timeout
-- - Logs with ID_UVVM_SEND_CMD when sending to VVC
-- - Logs with ID_UVVM_CMD_ACK when ACK or timeout occurs
procedure send_command_to_vvc( -- VVC dedicated shared command used shared_vvc_cmd
signal vvc_target : inout t_vvc_target_record;
constant timeout : in time := std.env.resolution_limit
);
-------------------------------------------
-- set_vvc_target_defaults
-------------------------------------------
-- Returns a vvc target record with vvc_name and values specified in C_VVC_TARGET_RECORD_DEFAULT
function set_vvc_target_defaults (
constant vvc_name : in string
) return t_vvc_target_record;
-------------------------------------------
-- set_general_target_and_command_fields
-------------------------------------------
-- Sets target index and channel, and updates shared_vvc_cmd
procedure set_general_target_and_command_fields ( -- VVC dedicated shared command used shared_vvc_cmd
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
);
-------------------------------------------
-- set_general_target_and_command_fields
-------------------------------------------
-- Sets target index and channel, and updates shared_vvc_cmd
procedure set_general_target_and_command_fields ( -- VVC dedicated shared command used shared_vvc_cmd
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
);
-------------------------------------------
-- acknowledge_cmd
-------------------------------------------
-- Drives global_vvc_ack signal (to '1') for 1 delta cycle, then sets it back to 'Z'.
procedure acknowledge_cmd (
signal vvc_ack : inout std_logic;
constant command_idx : in natural
);
end package td_target_support_pkg;
package body td_target_support_pkg is
function resolved ( input_vector : t_vvc_target_record_drivers) return t_vvc_target_record_unresolved is
-- if none of the drives want to drive the target return value of first driver (which we need to drive at least the target name)
constant C_LINE_LENGTH_MAX : natural := 100; -- VVC idx list string length
variable v_result : t_vvc_target_record_unresolved := input_vector(input_vector'low);
variable v_cnt : integer := 0;
variable v_instance_string : string(1 to C_LINE_LENGTH_MAX) := (others => NUL);
variable v_line : line;
variable v_width : integer := 0;
begin
if input_vector'length = 1 then
return input_vector(input_vector'low);
else
for i in input_vector'range loop
-- The VVC is used if instance_idx is not -1 (which is the default value)
if input_vector(i).vvc_instance_idx /= -1 then
-- count the number of sequencer trying to access the VVC
v_cnt := v_cnt + 1;
v_result := input_vector(i);
-- generating string with all instance_idx for report in case of failure
write(v_line, string'(" "));
write(v_line, input_vector(i).vvc_instance_idx);
-- Ensure there is room for the last item and dots
v_width := v_line'length;
if v_width > (C_LINE_LENGTH_MAX-15) then
write(v_line, string'("..."));
exit;
end if;
end if;
end loop;
if v_width > 0 then
v_instance_string(1 to v_width) := v_line.all;
end if;
deallocate(v_line);
check_value(v_cnt < 2, TB_FAILURE, "Arbitration mechanism failed. Check VVC " & to_string(v_result.vvc_name) & " implementation and semaphore handling. Crashing instances with numbers " & v_instance_string(1 to v_width), C_SCOPE, ID_NEVER);
return v_result;
end if;
end resolved;
function to_string(
value : t_vvc_target_record;
vvc_instance : integer := -1;
vvc_channel : t_channel:= NA
) return string is
variable v_instance : integer;
variable v_channel : t_channel;
begin
if vvc_instance = -1 then
v_instance := value.vvc_instance_idx;
else
v_instance := vvc_instance;
end if;
if vvc_channel = NA then
v_channel := value.vvc_channel;
else
v_channel := vvc_channel;
end if;
if v_channel = NA then
return to_string(value.vvc_name) & "," & to_string(v_instance);
else
return to_string(value.vvc_name) & "," & to_string(v_instance) & "," & to_string(v_channel);
end if;
end;
function set_vvc_target_defaults (
constant vvc_name : in string
) return t_vvc_target_record is
variable v_rec : t_vvc_target_record := C_VVC_TARGET_RECORD_DEFAULT;
begin
v_rec.vvc_name := (others => NUL);
v_rec.vvc_name(1 to vvc_name'length) := vvc_name;
return v_rec;
end function;
procedure set_general_target_and_command_fields (
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
) is
begin
-- As shared_vvc_cmd is a shared variable we have to get exclusive access to it. Therefor we have to lock the protected_semaphore here.
-- It is unlocked again in await_cmd_from_sequencer after it is copied localy or in send_command_to_vvc if no VVC acknowledges the command.
-- It is guaranteed that no time delay occurs, only delta cycle delay.
await_semaphore_in_delta_cycles(protected_semaphore);
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
target.vvc_instance_idx <= vvc_instance_idx;
target.vvc_channel <= vvc_channel;
shared_vvc_cmd.proc_call := pad_string(proc_call, NUL, shared_vvc_cmd.proc_call'length);
shared_vvc_cmd.msg := (others => NUL); -- default empty
shared_vvc_cmd.msg(1 to msg'length) := msg;
shared_vvc_cmd.command_type := command_type;
shared_vvc_cmd.operation := operation;
end procedure;
procedure set_general_target_and_command_fields (
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
) is
begin
set_general_target_and_command_fields(target, vvc_instance_idx, NA, proc_call, msg, command_type, operation);
end procedure;
impure function format_command_idx(
command : t_vvc_cmd_record
) return string is
begin
return format_command_idx(command.cmd_idx);
end;
procedure send_command_to_vvc(
signal vvc_target : inout t_vvc_target_record;
constant timeout : in time := std.env.resolution_limit
) is
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT & "(uvvm)";
constant C_CMD_INFO : string := "uvvm cmd " & format_command_idx(shared_cmd_idx+1) & ": ";
variable v_ack_cmd_idx : integer := -1;
variable v_start_time : time;
variable v_local_vvc_cmd : t_vvc_cmd_record;
variable v_local_cmd_idx : integer;
variable v_was_multicast : boolean := false;
begin
check_value((shared_uvvm_state /= IDLE), TB_FAILURE, "UVVM will not work without uvvm_vvc_framework.ti_uvvm_engine instantiated in the test harness", C_SCOPE, ID_NEVER);
-- increment shared_cmd_inx. It is protected by the protected_semaphore and only one sequencer can access the variable at a time.
shared_cmd_idx := shared_cmd_idx + 1;
shared_vvc_cmd.cmd_idx := shared_cmd_idx;
if global_show_msg_for_uvvm_cmd then
log(ID_UVVM_SEND_CMD, to_string(shared_vvc_cmd.proc_call) & ": " & add_msg_delimiter(to_string(shared_vvc_cmd.msg)) & "."
& format_command_idx(shared_cmd_idx), C_SCOPE);
else
log(ID_UVVM_SEND_CMD, to_string(shared_vvc_cmd.proc_call)
& format_command_idx(shared_cmd_idx), C_SCOPE);
end if;
wait for 0 ns;
if (vvc_target.vvc_instance_idx = C_VVCT_ALL_INSTANCES) then
await_semaphore_in_delta_cycles(protected_multicast_semaphore);
if global_vvc_busy /= 'L' then
wait until global_vvc_busy = 'L';
end if;
v_was_multicast := true;
end if;
v_start_time := now;
-- semaphore "protected_semaphore" gets released after "wait for 0 ns" in await_cmd_from_sequencer
-- Before the semaphore is released copy shared_vvc_cmd to local variable, so that the shared_vvc_cmd can be used by other VVCs.
v_local_vvc_cmd := shared_vvc_cmd;
-- copy the shared_cmd_idx as it can be changed during this function after the semaphore is released
v_local_cmd_idx := shared_cmd_idx;
-- trigger the target -> vvc continues in await_cmd_from_sequencer
vvc_target.trigger <= '1';
wait for 0 ns;
-- the default value of vvc_target drives trigger to 'L' again
vvc_target <= set_vvc_target_defaults(vvc_target.vvc_name);
while v_ack_cmd_idx /= v_local_cmd_idx loop
wait until global_vvc_ack = '1' for ((v_start_time + timeout) - now);
v_ack_cmd_idx := protected_acknowledge_index.get_index;
if not (global_vvc_ack'event) then
tb_error("Time out for " & C_CMD_INFO & " '" & to_string(v_local_vvc_cmd.proc_call) & "' while waiting for acknowledge from VVC", C_SCOPE);
-- lock the sequencer for 5 delta cycles as it can take so long to get every VVC in normal mode again
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
-- release the semaphore as no VVC can do this
release_semaphore(protected_semaphore);
return;
end if;
end loop;
if (v_was_multicast = true) then
release_semaphore(protected_multicast_semaphore);
end if;
log(ID_UVVM_CMD_ACK, "ACK received. " & format_command_idx(v_local_cmd_idx), C_SCOPE);
-- clean up and prepare for next
wait for 0 ns; -- wait for executor to stop driving global_vvc_ack
end procedure;
procedure acknowledge_cmd (
signal vvc_ack : inout std_logic;
constant command_idx : in natural
) is
begin
-- Drive ack signal for 1 delta cycle only one command index can be acknowledged simultaneously.
while(protected_acknowledge_index.set_index(command_idx) = false) loop
-- if it can't set the acknowledge_index wait for one delta cycle and try again
wait for 0 ns;
end loop;
vvc_ack <= '1';
wait until vvc_ack = '1';
vvc_ack <= 'Z';
wait for 0 ns;
protected_acknowledge_index.release_index;
end procedure;
end package body td_target_support_pkg;
|
----------------------------------------------------------------------------------
-- eia232.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- EIA232 aka RS232 interface.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity eia232 is
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
Port (
clock : in STD_LOGIC;
reset : in std_logic;
speed : in std_logic_vector (1 downto 0);
rx : in STD_LOGIC;
tx : out STD_LOGIC;
cmd : out STD_LOGIC_VECTOR (39 downto 0);
execute : out STD_LOGIC;
data : in STD_LOGIC_VECTOR (31 downto 0);
send : in STD_LOGIC;
busy : out STD_LOGIC
);
end eia232;
architecture Behavioral of eia232 is
COMPONENT prescaler
generic (
SCALE : integer
);
PORT(
clock : IN std_logic;
reset : IN std_logic;
div : IN std_logic_vector(1 downto 0);
scaled : OUT std_logic
);
END COMPONENT;
COMPONENT receiver
generic (
FREQ : integer;
RATE : integer
);
PORT(
rx : IN std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in STD_LOGIC;
op : out std_logic_vector(7 downto 0);
data : out std_logic_vector(31 downto 0);
execute : out STD_LOGIC
);
END COMPONENT;
COMPONENT transmitter
generic (
FREQ : integer;
RATE : integer
);
PORT(
data : IN std_logic_vector(31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : IN std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in std_logic;
tx : OUT std_logic;
busy : out std_logic
);
END COMPONENT;
constant TRXFREQ : integer := FREQ / SCALE; -- reduced rx & tx clock for receiver and transmitter
signal trxClock, executeReg, executePrev, id, xon, xoff, wrFlags : std_logic;
signal disabledGroupsReg : std_logic_vector(3 downto 0);
signal opcode : std_logic_vector(7 downto 0);
signal opdata : std_logic_vector(31 downto 0);
begin
cmd <= opdata & opcode;
execute <= executeReg;
-- process special uart commands that do not belong in core decoder
process(clock)
begin
if rising_edge(clock) then
id <= '0'; xon <= '0'; xoff <= '0'; wrFlags <= '0';
executePrev <= executeReg;
if executePrev = '0' and executeReg = '1' then
case opcode is
when x"02" => id <= '1';
when x"11" => xon <= '1';
when x"13" => xoff <= '1';
when x"82" => wrFlags <= '1';
when others =>
end case;
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if wrFlags = '1' then
disabledGroupsReg <= opdata(5 downto 2);
end if;
end if;
end process;
Inst_prescaler: prescaler
generic map (
SCALE => SCALE
)
PORT MAP(
clock => clock,
reset => reset,
div => speed,
scaled => trxClock
);
Inst_receiver: receiver
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
rx => rx,
clock => clock,
trxClock => trxClock,
reset => reset,
op => opcode,
data => opdata,
execute => executeReg
);
Inst_transmitter: transmitter
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
data => data,
disabledGroups => disabledGroupsReg,
write => send,
id => id,
xon => xon,
xoff => xoff,
clock => clock,
trxClock => trxClock,
reset => reset,
tx => tx,
busy => busy
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- eia232.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- EIA232 aka RS232 interface.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity eia232 is
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
Port (
clock : in STD_LOGIC;
reset : in std_logic;
speed : in std_logic_vector (1 downto 0);
rx : in STD_LOGIC;
tx : out STD_LOGIC;
cmd : out STD_LOGIC_VECTOR (39 downto 0);
execute : out STD_LOGIC;
data : in STD_LOGIC_VECTOR (31 downto 0);
send : in STD_LOGIC;
busy : out STD_LOGIC
);
end eia232;
architecture Behavioral of eia232 is
COMPONENT prescaler
generic (
SCALE : integer
);
PORT(
clock : IN std_logic;
reset : IN std_logic;
div : IN std_logic_vector(1 downto 0);
scaled : OUT std_logic
);
END COMPONENT;
COMPONENT receiver
generic (
FREQ : integer;
RATE : integer
);
PORT(
rx : IN std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in STD_LOGIC;
op : out std_logic_vector(7 downto 0);
data : out std_logic_vector(31 downto 0);
execute : out STD_LOGIC
);
END COMPONENT;
COMPONENT transmitter
generic (
FREQ : integer;
RATE : integer
);
PORT(
data : IN std_logic_vector(31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : IN std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in std_logic;
tx : OUT std_logic;
busy : out std_logic
);
END COMPONENT;
constant TRXFREQ : integer := FREQ / SCALE; -- reduced rx & tx clock for receiver and transmitter
signal trxClock, executeReg, executePrev, id, xon, xoff, wrFlags : std_logic;
signal disabledGroupsReg : std_logic_vector(3 downto 0);
signal opcode : std_logic_vector(7 downto 0);
signal opdata : std_logic_vector(31 downto 0);
begin
cmd <= opdata & opcode;
execute <= executeReg;
-- process special uart commands that do not belong in core decoder
process(clock)
begin
if rising_edge(clock) then
id <= '0'; xon <= '0'; xoff <= '0'; wrFlags <= '0';
executePrev <= executeReg;
if executePrev = '0' and executeReg = '1' then
case opcode is
when x"02" => id <= '1';
when x"11" => xon <= '1';
when x"13" => xoff <= '1';
when x"82" => wrFlags <= '1';
when others =>
end case;
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if wrFlags = '1' then
disabledGroupsReg <= opdata(5 downto 2);
end if;
end if;
end process;
Inst_prescaler: prescaler
generic map (
SCALE => SCALE
)
PORT MAP(
clock => clock,
reset => reset,
div => speed,
scaled => trxClock
);
Inst_receiver: receiver
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
rx => rx,
clock => clock,
trxClock => trxClock,
reset => reset,
op => opcode,
data => opdata,
execute => executeReg
);
Inst_transmitter: transmitter
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
data => data,
disabledGroups => disabledGroupsReg,
write => send,
id => id,
xon => xon,
xoff => xoff,
clock => clock,
trxClock => trxClock,
reset => reset,
tx => tx,
busy => busy
);
end Behavioral;
|
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