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----------------------------------------------------------------------------------
-- eia232.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- EIA232 aka RS232 interface.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity eia232 is
generic (
FREQ : integer;
SCALE : integer;
RATE : integer
);
Port (
clock : in STD_LOGIC;
reset : in std_logic;
speed : in std_logic_vector (1 downto 0);
rx : in STD_LOGIC;
tx : out STD_LOGIC;
cmd : out STD_LOGIC_VECTOR (39 downto 0);
execute : out STD_LOGIC;
data : in STD_LOGIC_VECTOR (31 downto 0);
send : in STD_LOGIC;
busy : out STD_LOGIC
);
end eia232;
architecture Behavioral of eia232 is
COMPONENT prescaler
generic (
SCALE : integer
);
PORT(
clock : IN std_logic;
reset : IN std_logic;
div : IN std_logic_vector(1 downto 0);
scaled : OUT std_logic
);
END COMPONENT;
COMPONENT receiver
generic (
FREQ : integer;
RATE : integer
);
PORT(
rx : IN std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in STD_LOGIC;
op : out std_logic_vector(7 downto 0);
data : out std_logic_vector(31 downto 0);
execute : out STD_LOGIC
);
END COMPONENT;
COMPONENT transmitter
generic (
FREQ : integer;
RATE : integer
);
PORT(
data : IN std_logic_vector(31 downto 0);
disabledGroups : in std_logic_vector (3 downto 0);
write : IN std_logic;
id : in std_logic;
xon : in std_logic;
xoff : in std_logic;
clock : IN std_logic;
trxClock : IN std_logic;
reset : in std_logic;
tx : OUT std_logic;
busy : out std_logic
);
END COMPONENT;
constant TRXFREQ : integer := FREQ / SCALE; -- reduced rx & tx clock for receiver and transmitter
signal trxClock, executeReg, executePrev, id, xon, xoff, wrFlags : std_logic;
signal disabledGroupsReg : std_logic_vector(3 downto 0);
signal opcode : std_logic_vector(7 downto 0);
signal opdata : std_logic_vector(31 downto 0);
begin
cmd <= opdata & opcode;
execute <= executeReg;
-- process special uart commands that do not belong in core decoder
process(clock)
begin
if rising_edge(clock) then
id <= '0'; xon <= '0'; xoff <= '0'; wrFlags <= '0';
executePrev <= executeReg;
if executePrev = '0' and executeReg = '1' then
case opcode is
when x"02" => id <= '1';
when x"11" => xon <= '1';
when x"13" => xoff <= '1';
when x"82" => wrFlags <= '1';
when others =>
end case;
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if wrFlags = '1' then
disabledGroupsReg <= opdata(5 downto 2);
end if;
end if;
end process;
Inst_prescaler: prescaler
generic map (
SCALE => SCALE
)
PORT MAP(
clock => clock,
reset => reset,
div => speed,
scaled => trxClock
);
Inst_receiver: receiver
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
rx => rx,
clock => clock,
trxClock => trxClock,
reset => reset,
op => opcode,
data => opdata,
execute => executeReg
);
Inst_transmitter: transmitter
generic map (
FREQ => TRXFREQ,
RATE => RATE
)
PORT MAP(
data => data,
disabledGroups => disabledGroupsReg,
write => send,
id => id,
xon => xon,
xoff => xoff,
clock => clock,
trxClock => trxClock,
reset => reset,
tx => tx,
busy => busy
);
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY pattern_gen IS
PORT
( clock_50Mhz, reset, start_PB, start_inc_PB : IN STD_LOGIC;
write_data : OUT STD_LOGIC;
sram_address : OUT STD_LOGIC_VECTOR(17 downto 0);
sram_data : OUT STD_LOGIC_VECTOR(15 downto 0));
END pattern_gen;
ARCHITECTURE behav OF pattern_gen IS
TYPE STATE_TYPE IS (idle, start_gen, start_inc_gen, stop_write);
SIGNAL state: STATE_TYPE;
SIGNAL pattern, pattern_xor : std_logic_vector(15 downto 0);
SIGNAL pattern_inc : std_logic_vector(15 downto 0);
SIGNAL clock_count_500Khz : std_logic_vector(7 downto 0);
SIGNAL clock_count_1Hz : std_logic_vector(27 downto 0);
SIGNAL clock_500Khz : std_logic;
SIGNAL clock_1Hz : std_logic;
BEGIN
PROCESS
BEGIN
WAIT UNTIL clock_50Mhz' EVENT AND clock_50Mhz = '1';
IF reset = '0' THEN
clock_count_500Khz <= X"00";
clock_500Khz <= '0';
ELSE
IF
clock_count_500Khz < 50 THEN
clock_count_500Khz <= clock_count_500Khz + 1;
ELSE
clock_count_500Khz <= X"00";
clock_500Khz <= NOT clock_500Khz;
END IF;
END IF;
END PROCESS;
-- IF (reset = '1') THEN
-- clock_count_1Hz <= X"0000000";
-- clock_1Hz <= '0';
-- ELSE
-- IF
-- clock_count_1Hz < X"17D7840" THEN
-- clock_count_1Hz <= clock_count_1Hz + 1;
-- ELSE
-- clock_count_1Hz <= X"0000000";
-- clock_1Hz <= NOT clock_1Hz;
-- END IF;
-- END IF;
-- END PROCESS;
PROCESS(clock_500Khz, reset)
--PROCESS(clock_1Hz, reset)
variable pattern_temp : std_logic_vector(15 downto 0);
variable pattern_inc_temp : std_logic_vector(15 downto 0);
variable address_temp : std_logic_vector(17 downto 0);
BEGIN
IF (reset = '0') THEN
sram_address <= "000000000000000000";
sram_data <= X"0000";
address_temp := "000000000000000000";
state <= idle;
ELSIF clock_500Khz' EVENT AND clock_500Khz = '1' THEN
--ELSIF clock_1Hz' EVENT AND clock_1Hz = '1' THEN
CASE state IS
WHEN idle =>
pattern <= "1010101010101010";
pattern_inc <= X"FFFF";
sram_address <= "000000000000000000";
sram_data <= X"0000";
address_temp := "000000000000000000";
IF (start_PB='0') THEN
state <= start_gen;
ELSIF(start_inc_PB = '0') THEN
state <= start_inc_gen;
ELSE
state <= idle;
END IF;
WHEN start_gen =>
pattern_xor <= X"FFFF";
write_data <= '1';
pattern_temp := pattern xor pattern_xor;
address_temp := address_temp + 1;
sram_address <= address_temp;
pattern <= pattern_temp;
sram_data <= pattern_temp;
state <= start_gen;
IF(address_temp = X"3FFFF") THEN
state <= stop_write;
END IF;
WHEN start_inc_gen =>
write_data <= '1';
pattern_inc_temp := pattern_inc - 1;
address_temp := address_temp + 1;
sram_address <= address_temp;
pattern_inc <= pattern_inc_temp;
sram_data <= pattern_inc_temp;
state <= start_inc_gen;
IF(address_temp = X"3FFFF") THEN
state <= stop_write;
END IF;
WHEN stop_write =>
write_data <= '0';
state <= idle;
END CASE;
END IF;
END PROCESS;
END behav; |
----------------------------------------------
-- Design Name : Test bench utils for sp_vision
-- File Name : sp_vision_test_pkg.vhd
-- Function : Defines communication functions between imx and fpga
-- Author : Fabien Marteau <[email protected]>
-- Version : 1.00
---------------------------------------------
-----------------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sp_vision_test_pkg is
CONSTANT CS_MIN : time := 13.6 ns;
CONSTANT CLOCK_PERIOD : time := 7.5188 ns;
CONSTANT WE3 : time := 2.25 ns;
CONSTANT WE4 : time := 2.25 ns;
-- write procedures
-- Params :
-- address : Write address
-- value : value to write
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
procedure imx_write(
address : in std_logic_vector (15 downto 0);
value : in std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : out std_logic_vector (15 downto 0);
WSC : natural
);
-- read procedures
-- Params :
-- address : Write address
-- value : value returned
-- gls_clk : clock signal
-- imx_cs_n : Chip select
-- imx_oe_n : Read signal
-- imx_eb3_n : Write signal
-- imx_address : Address signal
-- imx_data : Data signal
-- WSC : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
procedure imx_read(
address : in std_logic_vector (15 downto 0);
signal value : out std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : in std_logic_vector (15 downto 0);
WSC : natural
);
end package sp_vision_test_pkg;
package body sp_vision_test_pkg is
-- Write value from imx
procedure imx_write(
address : in std_logic_vector (15 downto 0);
value : in std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : out std_logic_vector (15 downto 0);
WSC : natural
) is
begin
-- Write value
wait until falling_edge(gls_clk);
wait for 4 ns;
imx_address <= address(12 downto 1);
imx_cs_n <= '0';
imx_eb3_n <= '0';
wait until falling_edge(gls_clk);
wait for 2500 ps;
imx_data <= value;
if WSC <= 1 then
wait until falling_edge(gls_clk);
else
for n in 1 to WSC loop
wait until falling_edge(gls_clk); -- WSC = 2
end loop;
end if;
wait for 1 ns;
imx_cs_n <= '1';
imx_eb3_n <= '1';
imx_address <= (others => 'Z');
imx_data <= (others => 'Z');
end procedure imx_write;
-- Read a value from imx
procedure imx_read(
address : in std_logic_vector (15 downto 0);
signal value : out std_logic_vector (15 downto 0);
signal gls_clk : in std_logic ;
signal imx_cs_n : out std_logic ;
signal imx_oe_n : out std_logic ;
signal imx_eb3_n : out std_logic ;
signal imx_address : out std_logic_vector (12 downto 1);
signal imx_data : in std_logic_vector (15 downto 0);
WSC : natural
) is
begin
-- Read value
wait until falling_edge(gls_clk);
wait for WE3;
imx_address <= address(12 downto 1);
imx_cs_n <= '0';
imx_oe_n <= '0';
wait for CS_MIN; -- minimum chip select time
if WSC > 1 then
for n in 2 to WSC loop
wait until falling_edge(gls_clk);
end loop;
--wait for CLOCK_PERIOD*(WSC-1);
end if;
wait for WE4;
value <= imx_data;
imx_cs_n <= '1';
imx_oe_n <= '1';
imx_address <= (others => 'Z');
end procedure imx_read;
end package body sp_vision_test_pkg;
|
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.types.all;
use work.interfaces.all;
entity memory_tb is
end;
architecture rtl of memory_tb is
component memory is
port( clk : in std_logic;
reset : in std_logic;
input : in memory_in_if;
output : out memory_out_if);
end component;
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal input : memory_in_if;
signal output : memory_out_if;
signal read_data_cmp : byte_t;
signal lineno : integer := 0;
begin
reset_gen : process
begin
reset <= '1';
wait for 40 ns;
reset <= '0';
wait;
end process;
clk_gen : process
begin
if clk = '1' then
clk <= '0';
wait for 10 ns;
else
clk <= '1';
wait for 10 ns;
end if;
end process;
run_test : process(clk, reset)
type state_t is (s0, s1, s2, s3);
variable state : state_t := s0;
file fp : text open read_mode is "/home/stuart/VHDL/gbvhdl/testing/tests/memory.txt";
variable address_s : string(16 downto 1);
variable we_s : string( 1 downto 1);
variable wdata_s : string( 8 downto 1);
variable rdata_s : string( 8 downto 1);
variable dummy : string( 1 downto 1);
variable l : line;
begin
if reset = '1' then
input.address <= (others => '0');
elsif rising_edge(clk) then
case state is
when s0 =>
if endfile(fp) then
state := s3;
else
readline(fp, l);
read(l, address_s);
read(l, dummy);
read(l, we_s);
read(l, dummy);
read(l, wdata_s);
read(l, dummy);
read(l, rdata_s);
if we_s(1) = '1' then
input.we <= '1';
else
input.we <= '0';
end if;
input.address <= to_std_logic_vector(address_s);
input.data <= to_std_logic_vector(wdata_s);
read_data_cmp <= to_std_logic_vector(rdata_s);
state := s1;
end if;
when s1 =>
state := s0;
assert read_data_cmp = output.data;
lineno <= lineno + 1;
when s2 =>
state := s0;
when s3 =>
report "End of simulation" severity failure;
end case;
end if;
end process;
memory_0 : memory
port map (clk, reset, input, output);
end rtl;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 10:54:36 06/19/2012
-- Design Name:
-- Module Name: wishbone_mp_sdram_controller - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_utils_pack.all ;
entity wishbone_mp_sdram_controller is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
NB_PORT : positive := 2;
ACCESS_CACHE_SIZE : positive := 1024 -- expressed in 16bits multiple
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone interface
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- logic interfaces
logic_address : in slv32_array(0 to NB_PORT-1) ; -- mem base address and cache addr
logic_writedata : in slv16_array(0 to NB_PORT-1);
logic_readdata : out slv16_array(0 to NB_PORT-1);
logic_read, logic_write : in std_logic_vector(0 to NB_PORT-1) ;
logic_refresh : in std_logic_vector(0 to NB_PORT-1) ;
cache_available : out std_logic_vector(0 to NB_PORT-1) ;
-- SDRAM interface
cmd_ready : out STD_LOGIC; -- '1' when a new command will be acted on
cmd_enable : in STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr : in STD_LOGIC; -- Is this a write?
cmd_address : in STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
cmd_byte_enable : in STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
cmd_data_in : in STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
data_out : out STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
data_out_ready : out STD_LOGIC -- is new data ready
);
end wishbone_mp_sdram_controller;
architecture RTL of wishbone_mp_sdram_controller is
component data_cache is
generic(PORT_A_WIDTH : positive := 16; PORT_B_WIDTH : positive := 32);
port(
clk, reset : in std_logic ;
port_a_line_number : in std_logic_vector(2 downto 0);
port_b_line_number : in std_logic_vector(2 downto 0);
port_a_line_address : in std_logic_vector(6 downto 0);
port_b_line_address : in std_logic_vector(5 downto 0);
port_a_line_datain : in std_logic_vector(PORT_A_WIDTH-1 downto 0);
port_b_line_datain : in std_logic_vector(PORT_B_WIDTH-1 downto 0);
port_a_line_dataout : out std_logic_vector(PORT_A_WIDTH-1 downto 0);
port_b_line_dataout : out std_logic_vector(PORT_B_WIDTH-1 downto 0);
port_a_write, port_b_write : in std_logic ;
cache_invalid : in std_logic ;
line_dirty : out std_logic_vector(7 downto 0);
line_clean : in std_logic_vector(7 downto 0)
);
end component;
constant ctrl_address_bit : integer := 10 ;
constant line_size : integer := 256 ;
constant cache_line_first_bit_ctrl : integer := nbit(cache_size/4);
constant END_OF_LINE : integer := (cache_size/4) ;
type ctrl_states is (INIT, REFRESH_CACHE, FLUSH_CACHE, OP_END, NEXT_PORT);
-- controller state machine signals
signal current_state, next_state : ctrl_states ;
--cache status for wishbone bus
signal cache_status : std_logic_vector(15 downto 0);
--cache control for wishbone bus
signal cache_ctrl : std_logic_vector(15 downto 0);
-- array of cache events (0 = refresh, 1 = flush)
signal cache_refresh : std_logic_vector(NB_PORT downto 0);
signal cache_flush : std_logic_vector(NB_PORT downto 0);
signal set_wbcache_refresh, set_wbcache_flush : std_logic ;
-- array of cache control signals
signal cache_base_address : slv32_array(0 to NB_PORT); -- where the cache i based in SDRAM
signal cache_line_index, cache_line_addr : slv8_array(0 to NB_PORT); -- control by manager to access cache
signal cache_line_dirty : slv8_array(0 to NB_PORT); -- cache is divided in lines, that can be marked as dirty
signal cache_access_count : slv16_array(0 to NB_PORT); -- counter to start counting from base addr until cache is filled
signal cache_write_data, cache_read_data : slv32_array(0 to NB_PORT); -- data signal from/to cache
signal cache_write : std_logic_vector(0 to NB_PORT); -- write signal to activate write to cache
signal cache_clean : std_logic_vector(0 to NB_PORT);
signal cache_invalid : std_logic_vector(0 to NB_PORT);
begin
gls_resetn <= NOT gls_reset ;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
if wbs_address(ctrl_address_bit) = '1' and wbs_address(1 downto 0) = "00" then -- register to set base mem address
cache_base_address(0)(15 downto 0) <= wbs_writedata ;
elsif wbs_address(ctrl_address_bit) = '1' and wbs_address(1 downto 0) = "01" then
cache_base_address(0)(31 downto 16) <= wbs_writedata ;
elsif wbs_address(ctrl_address_bit) = '1' and wbs_address(1 downto 0) = "10" then
set_wbcache_flush <= wbs_writedata(0);
set_wbcache_refresh <= wbs_writedata(0);
end if ;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
control_latched <= control_data ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
wbs_ack <= read_ack or write_ack;
-- cache banks
-- cache at index 0 is wishbone access cache
cache_i : data_cache
generic map(PORT_A_WIDTH => 16, PORT_B_WIDTH => 32)
port map(
clk => gls_clk ,
reset => gls_reset ,
port_a_line_number => wbs_address(9 downto 7), -- need to compose cache address from access address
port_b_line_number => cache_addr(0)(8 downto 6),
port_a_line_address => wbs_address(6 downto 0), -- need to compose cache address from access address
port_b_line_address => cache_addr(0)(5 downto 0),
port_a_line_datain => wbs_writedata,
port_b_line_datain => cache_write_data(0),
port_a_line_dataout => wbs_readdata,
port_b_line_dataout => cache_read_data(0),
port_a_write => wishbone_write,
port_b_write => cache_write(0),
line_dirty => cache_line_dirty(0),
line_clean => cache_clean(0),
cache_invalid => cache_invalid(0)
);
cache_ctrl_0 : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
cache_flush(0) <= '0' ;
cache_refresh(0) <= '0' ;
elsif rising_edge(gls_clk) then
if set_wbcache_flush= '1' then
cache_flush(0) <= '1' ;
elsif set_wbcache_refresh = '1' then
cache_refresh(0) <= '1';
end if ;
if rst_cache_ctrl(0)= '1' then --handled by controller when operation is done
cache_flush(0) <= '0' ;
cache_refresh(0) <= '0' ;
end if ;
end if;
end process read_bloc;
-- generate cache memory and control for each of the ports
gen_caches : for i in 1 to NB_PORT generate
cache_i : data_cache
generic map(PORT_A_WIDTH => 16, PORT_B_WIDTH => 32)
port map(
clk => gls_clk ,
reset => gls_reset ,
port_a_line_number => logic_address(i-1)(9 downto 7), -- need to compose cache address from access address
port_b_line_number => cache_addr(i)(8 downto 6),
port_a_line_address => logic_address(i-1)(6 downto 0), -- need to compose cache address from access address
port_b_line_address => cache_addr(i)(5 downto 0),
port_a_line_datain => logic_writedata(i-1),
port_b_line_datain => cache_write_data(i),
port_a_line_dataout => logic_readdata(i-1),
port_b_line_dataout => cache_read_data(i),
port_a_write => logic_write,
port_b_write => cache_write(i),
line_dirty => cache_line_dirty(i),
line_clean => cache_clean(i),
cache_invalid => cache_invalid(i)
);
cache_ctrl_i : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
cache_flush(i) <= '0' ;
cache_refresh(i) <= '0' ;
elsif rising_edge(gls_clk) then
if logic_flush(i-1)= '1' then
cache_flush(i) <= '1' ;
cach_base_address(i) <= logic_address(i-1);
elsif logic_refresh(i-1)= '1' then
cache_refresh(i) <= '1' ;
cach_base_address <= logic_address(i-1);
end if ;
if rst_cache_ctrl(i)= '1' then --handled by controller when operation is done
cache_flush(i) <= '0' ;
cache_refresh(i) <= '0' ;
end if ;
end if;
end process read_bloc;
end generate ;
-- current port counter
-- incemented by round robin scheduler after time slot
port_counter : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
port_index <= (others => '0');
elsif rising_edge(gls_clk) then
if reset_port_counter = '1' then
port_index <= (others => '0') ;
elsif en_port_counter = '1' then
port_index <= port_index + 1 ;
end if ;
end if;
end process port_counter;
-- Round robing cache manager
-- capture cache events (flush, refresh) and schedule them on SDRAM memory
-- change of slave whenever the counter reaches the tick (and current transfer has completed).
state_mem : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
current_state <= INIT ;
elsif rising_edge(gls_clk) then
current_state <= next_state ;
end if;
end process state_mem;
current_cache_addr <= cache_addr(conv_integer(port_index)) ;
current_line_index <= line_index(conv_integer(port_index)) ;
current_cache_refresh <= cache_refresh(conv_integer(port_index)) ;
current_cache_dirty <= cache_dirty(conv_integer(port_index)) ;
state_evolve: process(current_state, robin_tick_cnt, cmd_ready)
begin
next_state <= current_state ;
case current_state is
when INIT =>
if current_cache_refresh = '1' then -- cache refresh is manually triggered
next_state <= REFRESH_CACHE ;
elsif current_cache_dirty(conv_integer(current_cache_line_index)) = '1' then -- cache line is dirty, need to flush to memory
next_state <= FLUSH_CACHE ; -- will need to prioritize in the future to make sure cache line is all dirty ...
else
next_state <= NEXT_PORT ;
end if ;
when REFRESH_CACHE =>
if current_cache_addr = END_OF_LINE then -- next line, also need to mark cache line as clean
next_state <= OP_END ; -- cache operation ends for this cache
end if ;
when FLUSH_CACHE =>
if current_cache_addr = END_OF_LINE then -- next-line, also need to mark cache line as clean
next_state <= OP_END ; -- cache operations ends for this cache
end if ;
when OP_END =>
next_state <= NEXT_PORT ;
when NEXT_PORT =>
next_state <= INIT;
when others =>
next_state <= INIT ;
end case ;
end process state_evolve;
-- need to generate some of the logic for each line ...
gen_cleans : for i in 0 to 8 generate
cache_clean(conv_integer(port_index))(i) <= '1' when current_cache_addr = END_OF_LINE and current_state = FLUSH_CACHE and cache_line_index = i else
'1' when current_cache_addr = END_OF_LINE and current_state = REFRESH_CACHE and cache_line_index = i else
'0' ; -- also need to have addresse at right value to clean the right line ...
end generate ;
with current_state select
en_port_counter <= '1' when NEXT_PORT,
'0' when others ;
reset_port_counter <= '1' when port_index = NB_PORT and current_state = NEXT_PORT else
'0' ;
en_line_index <= '1' when current_cache_addr = END_OF_LINE and current_state = FLUSH_CACHE else -- increment line index after line was flushed
'1' when current_cache_addr = END_OF_LINE and current_state = REFRESH_CACHE else -- increment line index after line was refreshed
'1' when cache_refresh(conv_integer(port_index)) = '0' and current_cache_dirty(conv_integer(port_index))(conv_integer(cache_addr(8 downto 6))) = '1' and current_state = INIT else -- increment line index if line needs no-op
'0' ;
with current_state select
load_mem_addr <= '1' when INIT,
'0' when others ;
with current_state select
cm_enable <= '1' when FLUSH_CACHE,
'1' when REFRESH_CACHE,
'0' when others ;
with current_state select
cm_wr <= '1' when FLUSH_CACHE,
'0' when others ;
--mem handling process
cache_operation_proc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
mem_addr <= (others => '0') ;
elsif rising_edge(gls_clk) then
if load_mem_addr = '1' then
mem_addr <= cache_base_addr(port_index) ;
end if ;
if current_state = FLUSH_CACHE then
if cmd_ready = '1' then
mem_addr <= mem_addr + 1 ;
current_cache_addr <= current_cache_addr + 1 ;
end if ;
end if ;
if current_state = REFRESH_CACHE then
if cmd_ready = '1' then
mem_addr <= mem_addr + 1 ;
end if ;
if data_out_ready = '1' then
current_cache_addr <= current_cache_addr + 1 ;
end if ;
end if ;
end if;
end process state_mem;
end RTL;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 10:54:36 06/19/2012
-- Design Name:
-- Module Name: wishbone_mp_sdram_controller - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_utils_pack.all ;
entity wishbone_mp_sdram_controller is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
NB_PORT : positive := 2;
ACCESS_CACHE_SIZE : positive := 1024 -- expressed in 16bits multiple
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone interface
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- logic interfaces
logic_address : in slv32_array(0 to NB_PORT-1) ; -- mem base address and cache addr
logic_writedata : in slv16_array(0 to NB_PORT-1);
logic_readdata : out slv16_array(0 to NB_PORT-1);
logic_read, logic_write : in std_logic_vector(0 to NB_PORT-1) ;
logic_refresh : in std_logic_vector(0 to NB_PORT-1) ;
cache_available : out std_logic_vector(0 to NB_PORT-1) ;
-- SDRAM interface
cmd_ready : out STD_LOGIC; -- '1' when a new command will be acted on
cmd_enable : in STD_LOGIC; -- Set to '1' to issue new command (only acted on when cmd_read = '1')
cmd_wr : in STD_LOGIC; -- Is this a write?
cmd_address : in STD_LOGIC_VECTOR(sdram_address_width-2 downto 0); -- address to read/write
cmd_byte_enable : in STD_LOGIC_VECTOR(3 downto 0); -- byte masks for the write command
cmd_data_in : in STD_LOGIC_VECTOR(31 downto 0); -- data for the write command
data_out : out STD_LOGIC_VECTOR(31 downto 0); -- word read from SDRAM
data_out_ready : out STD_LOGIC -- is new data ready
);
end wishbone_mp_sdram_controller;
architecture RTL of wishbone_mp_sdram_controller is
component data_cache is
generic(PORT_A_WIDTH : positive := 16; PORT_B_WIDTH : positive := 32);
port(
clk, reset : in std_logic ;
port_a_line_number : in std_logic_vector(2 downto 0);
port_b_line_number : in std_logic_vector(2 downto 0);
port_a_line_address : in std_logic_vector(6 downto 0);
port_b_line_address : in std_logic_vector(5 downto 0);
port_a_line_datain : in std_logic_vector(PORT_A_WIDTH-1 downto 0);
port_b_line_datain : in std_logic_vector(PORT_B_WIDTH-1 downto 0);
port_a_line_dataout : out std_logic_vector(PORT_A_WIDTH-1 downto 0);
port_b_line_dataout : out std_logic_vector(PORT_B_WIDTH-1 downto 0);
port_a_write, port_b_write : in std_logic ;
cache_invalid : in std_logic ;
line_dirty : out std_logic_vector(7 downto 0);
line_clean : in std_logic_vector(7 downto 0)
);
end component;
constant ctrl_address_bit : integer := 10 ;
constant line_size : integer := 256 ;
constant cache_line_first_bit_ctrl : integer := nbit(cache_size/4);
constant END_OF_LINE : integer := (cache_size/4) ;
type ctrl_states is (INIT, REFRESH_CACHE, FLUSH_CACHE, OP_END, NEXT_PORT);
-- controller state machine signals
signal current_state, next_state : ctrl_states ;
--cache status for wishbone bus
signal cache_status : std_logic_vector(15 downto 0);
--cache control for wishbone bus
signal cache_ctrl : std_logic_vector(15 downto 0);
-- array of cache events (0 = refresh, 1 = flush)
signal cache_refresh : std_logic_vector(NB_PORT downto 0);
signal cache_flush : std_logic_vector(NB_PORT downto 0);
signal set_wbcache_refresh, set_wbcache_flush : std_logic ;
-- array of cache control signals
signal cache_base_address : slv32_array(0 to NB_PORT); -- where the cache i based in SDRAM
signal cache_line_index, cache_line_addr : slv8_array(0 to NB_PORT); -- control by manager to access cache
signal cache_line_dirty : slv8_array(0 to NB_PORT); -- cache is divided in lines, that can be marked as dirty
signal cache_access_count : slv16_array(0 to NB_PORT); -- counter to start counting from base addr until cache is filled
signal cache_write_data, cache_read_data : slv32_array(0 to NB_PORT); -- data signal from/to cache
signal cache_write : std_logic_vector(0 to NB_PORT); -- write signal to activate write to cache
signal cache_clean : std_logic_vector(0 to NB_PORT);
signal cache_invalid : std_logic_vector(0 to NB_PORT);
begin
gls_resetn <= NOT gls_reset ;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
if wbs_address(ctrl_address_bit) = '1' and wbs_address(1 downto 0) = "00" then -- register to set base mem address
cache_base_address(0)(15 downto 0) <= wbs_writedata ;
elsif wbs_address(ctrl_address_bit) = '1' and wbs_address(1 downto 0) = "01" then
cache_base_address(0)(31 downto 16) <= wbs_writedata ;
elsif wbs_address(ctrl_address_bit) = '1' and wbs_address(1 downto 0) = "10" then
set_wbcache_flush <= wbs_writedata(0);
set_wbcache_refresh <= wbs_writedata(0);
end if ;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
control_latched <= control_data ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
wbs_ack <= read_ack or write_ack;
-- cache banks
-- cache at index 0 is wishbone access cache
cache_i : data_cache
generic map(PORT_A_WIDTH => 16, PORT_B_WIDTH => 32)
port map(
clk => gls_clk ,
reset => gls_reset ,
port_a_line_number => wbs_address(9 downto 7), -- need to compose cache address from access address
port_b_line_number => cache_addr(0)(8 downto 6),
port_a_line_address => wbs_address(6 downto 0), -- need to compose cache address from access address
port_b_line_address => cache_addr(0)(5 downto 0),
port_a_line_datain => wbs_writedata,
port_b_line_datain => cache_write_data(0),
port_a_line_dataout => wbs_readdata,
port_b_line_dataout => cache_read_data(0),
port_a_write => wishbone_write,
port_b_write => cache_write(0),
line_dirty => cache_line_dirty(0),
line_clean => cache_clean(0),
cache_invalid => cache_invalid(0)
);
cache_ctrl_0 : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
cache_flush(0) <= '0' ;
cache_refresh(0) <= '0' ;
elsif rising_edge(gls_clk) then
if set_wbcache_flush= '1' then
cache_flush(0) <= '1' ;
elsif set_wbcache_refresh = '1' then
cache_refresh(0) <= '1';
end if ;
if rst_cache_ctrl(0)= '1' then --handled by controller when operation is done
cache_flush(0) <= '0' ;
cache_refresh(0) <= '0' ;
end if ;
end if;
end process read_bloc;
-- generate cache memory and control for each of the ports
gen_caches : for i in 1 to NB_PORT generate
cache_i : data_cache
generic map(PORT_A_WIDTH => 16, PORT_B_WIDTH => 32)
port map(
clk => gls_clk ,
reset => gls_reset ,
port_a_line_number => logic_address(i-1)(9 downto 7), -- need to compose cache address from access address
port_b_line_number => cache_addr(i)(8 downto 6),
port_a_line_address => logic_address(i-1)(6 downto 0), -- need to compose cache address from access address
port_b_line_address => cache_addr(i)(5 downto 0),
port_a_line_datain => logic_writedata(i-1),
port_b_line_datain => cache_write_data(i),
port_a_line_dataout => logic_readdata(i-1),
port_b_line_dataout => cache_read_data(i),
port_a_write => logic_write,
port_b_write => cache_write(i),
line_dirty => cache_line_dirty(i),
line_clean => cache_clean(i),
cache_invalid => cache_invalid(i)
);
cache_ctrl_i : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
cache_flush(i) <= '0' ;
cache_refresh(i) <= '0' ;
elsif rising_edge(gls_clk) then
if logic_flush(i-1)= '1' then
cache_flush(i) <= '1' ;
cach_base_address(i) <= logic_address(i-1);
elsif logic_refresh(i-1)= '1' then
cache_refresh(i) <= '1' ;
cach_base_address <= logic_address(i-1);
end if ;
if rst_cache_ctrl(i)= '1' then --handled by controller when operation is done
cache_flush(i) <= '0' ;
cache_refresh(i) <= '0' ;
end if ;
end if;
end process read_bloc;
end generate ;
-- current port counter
-- incemented by round robin scheduler after time slot
port_counter : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
port_index <= (others => '0');
elsif rising_edge(gls_clk) then
if reset_port_counter = '1' then
port_index <= (others => '0') ;
elsif en_port_counter = '1' then
port_index <= port_index + 1 ;
end if ;
end if;
end process port_counter;
-- Round robing cache manager
-- capture cache events (flush, refresh) and schedule them on SDRAM memory
-- change of slave whenever the counter reaches the tick (and current transfer has completed).
state_mem : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
current_state <= INIT ;
elsif rising_edge(gls_clk) then
current_state <= next_state ;
end if;
end process state_mem;
current_cache_addr <= cache_addr(conv_integer(port_index)) ;
current_line_index <= line_index(conv_integer(port_index)) ;
current_cache_refresh <= cache_refresh(conv_integer(port_index)) ;
current_cache_dirty <= cache_dirty(conv_integer(port_index)) ;
state_evolve: process(current_state, robin_tick_cnt, cmd_ready)
begin
next_state <= current_state ;
case current_state is
when INIT =>
if current_cache_refresh = '1' then -- cache refresh is manually triggered
next_state <= REFRESH_CACHE ;
elsif current_cache_dirty(conv_integer(current_cache_line_index)) = '1' then -- cache line is dirty, need to flush to memory
next_state <= FLUSH_CACHE ; -- will need to prioritize in the future to make sure cache line is all dirty ...
else
next_state <= NEXT_PORT ;
end if ;
when REFRESH_CACHE =>
if current_cache_addr = END_OF_LINE then -- next line, also need to mark cache line as clean
next_state <= OP_END ; -- cache operation ends for this cache
end if ;
when FLUSH_CACHE =>
if current_cache_addr = END_OF_LINE then -- next-line, also need to mark cache line as clean
next_state <= OP_END ; -- cache operations ends for this cache
end if ;
when OP_END =>
next_state <= NEXT_PORT ;
when NEXT_PORT =>
next_state <= INIT;
when others =>
next_state <= INIT ;
end case ;
end process state_evolve;
-- need to generate some of the logic for each line ...
gen_cleans : for i in 0 to 8 generate
cache_clean(conv_integer(port_index))(i) <= '1' when current_cache_addr = END_OF_LINE and current_state = FLUSH_CACHE and cache_line_index = i else
'1' when current_cache_addr = END_OF_LINE and current_state = REFRESH_CACHE and cache_line_index = i else
'0' ; -- also need to have addresse at right value to clean the right line ...
end generate ;
with current_state select
en_port_counter <= '1' when NEXT_PORT,
'0' when others ;
reset_port_counter <= '1' when port_index = NB_PORT and current_state = NEXT_PORT else
'0' ;
en_line_index <= '1' when current_cache_addr = END_OF_LINE and current_state = FLUSH_CACHE else -- increment line index after line was flushed
'1' when current_cache_addr = END_OF_LINE and current_state = REFRESH_CACHE else -- increment line index after line was refreshed
'1' when cache_refresh(conv_integer(port_index)) = '0' and current_cache_dirty(conv_integer(port_index))(conv_integer(cache_addr(8 downto 6))) = '1' and current_state = INIT else -- increment line index if line needs no-op
'0' ;
with current_state select
load_mem_addr <= '1' when INIT,
'0' when others ;
with current_state select
cm_enable <= '1' when FLUSH_CACHE,
'1' when REFRESH_CACHE,
'0' when others ;
with current_state select
cm_wr <= '1' when FLUSH_CACHE,
'0' when others ;
--mem handling process
cache_operation_proc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
mem_addr <= (others => '0') ;
elsif rising_edge(gls_clk) then
if load_mem_addr = '1' then
mem_addr <= cache_base_addr(port_index) ;
end if ;
if current_state = FLUSH_CACHE then
if cmd_ready = '1' then
mem_addr <= mem_addr + 1 ;
current_cache_addr <= current_cache_addr + 1 ;
end if ;
end if ;
if current_state = REFRESH_CACHE then
if cmd_ready = '1' then
mem_addr <= mem_addr + 1 ;
end if ;
if data_out_ready = '1' then
current_cache_addr <= current_cache_addr + 1 ;
end if ;
end if ;
end if;
end process state_mem;
end RTL;
|
-- This file has been automatically generated by go-iec61499-vhdl and should not be edited by hand
-- Converter written by Hammond Pearce and available at github.com/kiwih/go-iec61499-vhdl
-- This file represents the Composite Function Block for DE2_115
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DE2_115 is
port(
--for clock and reset signal
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
sync : in std_logic;
--special emitted internal variables for child I/O
tx_gpio : out std_logic; --type was BOOL
rx_gpio : in std_logic; --type was BOOL
--for done signal
done : out std_logic
);
end entity;
architecture rtl of DE2_115 is
-- Signals needed for event connections
signal gpio_rx_rd_conn : std_logic;
signal reaction_tx_change_conn : std_logic;
-- Signals needed for data connections
signal gpio_rx_data_conn : std_logic; --type was BOOL
signal reaction_tx_conn : std_logic; --type was BOOL
-- Signals needed for the done signals
signal gpio_done : std_logic;
signal reaction_done : std_logic;
begin
--top level I/O to signals
-- child I/O to signals
gpio : entity work.BFB_GPIO port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
rx_rd_eO => gpio_rx_rd_conn,
--event inputs
tx_rd_eI => reaction_tx_change_conn,
--data outputs
rx_data_O => gpio_rx_data_conn,
--data inputs
tx_data_I => reaction_tx_conn,
--specials
tx_gpio => tx_gpio, --output
rx_gpio => rx_gpio, --input
done => gpio_done
);
reaction : entity work.BFB_Reaction port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
tx_change_eO => reaction_tx_change_conn,
--event inputs
rx_change_eI => gpio_rx_rd_conn,
--data outputs
tx_O => reaction_tx_conn,
--data inputs
rx_I => gpio_rx_data_conn,
done => reaction_done
);
-- done signal
done <= gpio_done and reaction_done;
end rtl;
|
-- This file has been automatically generated by go-iec61499-vhdl and should not be edited by hand
-- Converter written by Hammond Pearce and available at github.com/kiwih/go-iec61499-vhdl
-- This file represents the Composite Function Block for DE2_115
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DE2_115 is
port(
--for clock and reset signal
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
sync : in std_logic;
--special emitted internal variables for child I/O
tx_gpio : out std_logic; --type was BOOL
rx_gpio : in std_logic; --type was BOOL
--for done signal
done : out std_logic
);
end entity;
architecture rtl of DE2_115 is
-- Signals needed for event connections
signal gpio_rx_rd_conn : std_logic;
signal reaction_tx_change_conn : std_logic;
-- Signals needed for data connections
signal gpio_rx_data_conn : std_logic; --type was BOOL
signal reaction_tx_conn : std_logic; --type was BOOL
-- Signals needed for the done signals
signal gpio_done : std_logic;
signal reaction_done : std_logic;
begin
--top level I/O to signals
-- child I/O to signals
gpio : entity work.BFB_GPIO port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
rx_rd_eO => gpio_rx_rd_conn,
--event inputs
tx_rd_eI => reaction_tx_change_conn,
--data outputs
rx_data_O => gpio_rx_data_conn,
--data inputs
tx_data_I => reaction_tx_conn,
--specials
tx_gpio => tx_gpio, --output
rx_gpio => rx_gpio, --input
done => gpio_done
);
reaction : entity work.BFB_Reaction port map(
clk => clk,
reset => reset,
enable => enable,
sync => sync,
--event outputs
tx_change_eO => reaction_tx_change_conn,
--event inputs
rx_change_eI => gpio_rx_rd_conn,
--data outputs
tx_O => reaction_tx_conn,
--data inputs
rx_I => gpio_rx_data_conn,
done => reaction_done
);
-- done signal
done <= gpio_done and reaction_done;
end rtl;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: leon
-- File: leon.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Complete processor
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.tech_map.all;
-- pragma translate_off
use work.debug.all;
-- pragma translate_on
entity leon is
port (
resetn : in std_logic; -- system signals
clk : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0); -- memory bus
---
datain : in std_logic_vector(31 downto 0); -- 32 bits conversion LA
dataout : out std_logic_vector(31 downto 0);
datasel : out std_logic_vector(3 downto 0);
---
ramsn : out std_logic_vector(4 downto 0);
ramoen : out std_logic_vector(4 downto 0);
rwen : inout std_logic_vector(3 downto 0);
romsn : out std_logic_vector(1 downto 0);
iosn : out std_logic;
oen : out std_logic;
read : out std_logic;
writen : inout std_logic;
brdyn : in std_logic;
bexcn : in std_logic;
---
pioo : out std_logic_vector(15 downto 0); -- I/O port 32 bits LA
pioi : in std_logic_vector(15 downto 0);
piod : out std_logic_vector(15 downto 0);
buttons : in std_logic_vector(3 downto 0); -- ddm ports
audioin : in std_logic;
digit0 : out std_logic_vector(6 downto 0);
digit1 : out std_logic_vector(6 downto 0);
audioout : out std_logic;
lr_out : out std_logic;
shift_clk : out std_logic;
mclk : out std_logic;
dispen : out std_logic;
---
wdogn : out std_logic; -- watchdog output
--
dsuen : in std_logic;
dsutx : out std_logic;
dsurx : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
--
test : in std_logic
);
end;
architecture rtl of leon is
component mcore
port (
resetn : in std_logic;
clk : in std_logic;
memi : in memory_in_type;
memo : out memory_out_type;
ioi : in io_in_type;
ioo : out io_out_type;
pcii : in pci_in_type;
pcio : out pci_out_type;
--
ddmi : in ddm_in_type; -- DDM signals LA
ddmo : out ddm_out_type;
--
dsi : in dsuif_in_type;
dso : out dsuif_out_type;
test : in std_logic
);
end component;
signal gnd, clko, resetno : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal ioi : io_in_type;
signal ioo : io_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal dsi : dsuif_in_type;
signal dso : dsuif_out_type;
--
signal ddmi : ddm_in_type; -- DDM signals LA
signal ddmo : ddm_out_type;
--
begin
gnd <= '0';
-- main processor core
mcore0 : mcore
port map (
resetn => resetno, clk => clko,
memi => memi, memo => memo, ioi => ioi, ioo => ioo,
-- pcii => pcii, pcio => pcio, dsi => dsi, dso => dso, test => test
pcii => pcii, pcio => pcio, ddmi => ddmi, ddmo => ddmo,dsi => dsi, dso => dso, test => test -- DDM LA
);
-- pads
-- clk_pad : inpad port map (clk, clko); -- clock
clko <= clk; -- avoid buffering during synthesis
reset_pad : smpad port map (resetn, resetno); -- reset
brdyn_pad : inpad port map (brdyn, memi.brdyn); -- bus ready
bexcn_pad : inpad port map (bexcn, memi.bexcn); -- bus exception
error_pad : odpad generic map (2) port map (ioo.errorn, errorn); -- cpu error mode
--DDM lines
inpad4 : inpad port map (audioin, ddmi.audioin);
inpad5 : inpad port map (buttons(0),ddmi.button0);
inpad6 : inpad port map (buttons(1),ddmi.button1);
inpad7 : inpad port map (buttons(2),ddmi.button2);
inpad8 : inpad port map (buttons(3),ddmi.button3);
-- d_pads: for i in 0 to 31 generate -- data bus
-- d_pad : iopad generic map (3) port map (memo.data(i), memo.bdrive((31-i)/8), memi.data(i), data(i));
-- end generate;
--
dataout <= memo.data; -- databus DDM LA
memi.data <= datain;
datasel <= memo.bdrive;
-- pio_pads : for i in 0 to 15 generate -- parallel I/O port
-- pio_pad : smiopad generic map (2) port map (ioo.piol(i), ioo.piodir(i), ioi.piol(i), pio(i));
-- end generate;
--
pioo <= ioo.piol; -- parallel I/O port DDM
ioi.piol <= pioi;
piod <= ioo.piodir;
rwen(0) <= memo.wrn(0);
memi.wrn(0) <= memo.wrn(0);
rwen(1) <= memo.wrn(1);
memi.wrn(1) <= memo.wrn(1);
rwen(2) <= memo.wrn(2);
memi.wrn(2) <= memo.wrn(2);
rwen(3) <= memo.wrn(3);
memi.wrn(3) <= memo.wrn(3);
-- rwen_pads : for i in 0 to 3 generate -- ram write strobe
-- rwen_pad : iopad generic map (2) port map (memo.wrn(i), gnd, memi.wrn(i), rwen(i));
-- end generate;
--
-- -- I/O write strobe
-- writen_pad : iopad generic map (2) port map (memo.writen, gnd, memi.writen, writen);
--
writen <= memo.writen; -- DDM LA
memi.writen <= memo.writen;
a_pads: for i in 0 to 27 generate -- memory address
a_pad : outpad generic map (3) port map (memo.address(i), address(i));
end generate;
ramsn_pads : for i in 0 to 4 generate -- ram oen/rasn
ramsn_pad : outpad generic map (2) port map (memo.ramsn(i), ramsn(i));
end generate;
ramoen_pads : for i in 0 to 4 generate -- ram chip select
eamoen_pad : outpad generic map (2) port map (memo.ramoen(i), ramoen(i));
end generate;
romsn_pads : for i in 0 to 1 generate -- rom chip select
romsn_pad : outpad generic map (2) port map (memo.romsn(i), romsn(i));
end generate;
read_pad : outpad generic map (2) port map (memo.read, read); -- memory read
oen_pad : outpad generic map (2) port map (memo.oen, oen); -- memory oen
iosn_pad : outpad generic map (2) port map (memo.iosn, iosn); -- I/O select
--
outpadb7: outpad port map (ddmo.shift_clk, shift_clk); -- DDM
outpadb8: outpad port map (ddmo.lr_out, lr_out);
outpadb9: outpad port map (ddmo.audioout, audioout);
outpadb10: for i in 0 to 6 generate
outpad101: outpad port map(ddmo.digit0(i), digit0(i));
end generate;
outpadb11: for i in 0 to 6 generate
outpad111: outpad port map(ddmo.digit1(i), digit1(i));
end generate;
outpadb12: outpad port map (ddmo.mclk, mclk);
dispen <= ddmo.dispen;
--
wd : if WDOGEN generate
wdogn_pad : odpad generic map (2) port map (ioo.wdog, wdogn); -- watchdog output
end generate;
ds : if DEBUG_UNIT generate
dsuen_pad : inpad port map (dsuen, dsi.dsui.dsuen); -- DSU enable
dsutx_pad : outpad generic map (1) port map (dso.dcomo.dsutx, dsutx);
dsurx_pad : inpad port map (dsurx, dsi.dcomi.dsurx); -- DSU receive data
dsubre_pad : inpad port map (dsubre, dsi.dsui.dsubre); -- DSU break
dsuact_pad : outpad generic map (1) port map (dso.dsuo.dsuact, dsuact);
end generate;
end ;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: leon
-- File: leon.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Complete processor
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.tech_map.all;
-- pragma translate_off
use work.debug.all;
-- pragma translate_on
entity leon is
port (
resetn : in std_logic; -- system signals
clk : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0); -- memory bus
---
datain : in std_logic_vector(31 downto 0); -- 32 bits conversion LA
dataout : out std_logic_vector(31 downto 0);
datasel : out std_logic_vector(3 downto 0);
---
ramsn : out std_logic_vector(4 downto 0);
ramoen : out std_logic_vector(4 downto 0);
rwen : inout std_logic_vector(3 downto 0);
romsn : out std_logic_vector(1 downto 0);
iosn : out std_logic;
oen : out std_logic;
read : out std_logic;
writen : inout std_logic;
brdyn : in std_logic;
bexcn : in std_logic;
---
pioo : out std_logic_vector(15 downto 0); -- I/O port 32 bits LA
pioi : in std_logic_vector(15 downto 0);
piod : out std_logic_vector(15 downto 0);
buttons : in std_logic_vector(3 downto 0); -- ddm ports
audioin : in std_logic;
digit0 : out std_logic_vector(6 downto 0);
digit1 : out std_logic_vector(6 downto 0);
audioout : out std_logic;
lr_out : out std_logic;
shift_clk : out std_logic;
mclk : out std_logic;
dispen : out std_logic;
---
wdogn : out std_logic; -- watchdog output
--
dsuen : in std_logic;
dsutx : out std_logic;
dsurx : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
--
test : in std_logic
);
end;
architecture rtl of leon is
component mcore
port (
resetn : in std_logic;
clk : in std_logic;
memi : in memory_in_type;
memo : out memory_out_type;
ioi : in io_in_type;
ioo : out io_out_type;
pcii : in pci_in_type;
pcio : out pci_out_type;
--
ddmi : in ddm_in_type; -- DDM signals LA
ddmo : out ddm_out_type;
--
dsi : in dsuif_in_type;
dso : out dsuif_out_type;
test : in std_logic
);
end component;
signal gnd, clko, resetno : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal ioi : io_in_type;
signal ioo : io_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal dsi : dsuif_in_type;
signal dso : dsuif_out_type;
--
signal ddmi : ddm_in_type; -- DDM signals LA
signal ddmo : ddm_out_type;
--
begin
gnd <= '0';
-- main processor core
mcore0 : mcore
port map (
resetn => resetno, clk => clko,
memi => memi, memo => memo, ioi => ioi, ioo => ioo,
-- pcii => pcii, pcio => pcio, dsi => dsi, dso => dso, test => test
pcii => pcii, pcio => pcio, ddmi => ddmi, ddmo => ddmo,dsi => dsi, dso => dso, test => test -- DDM LA
);
-- pads
-- clk_pad : inpad port map (clk, clko); -- clock
clko <= clk; -- avoid buffering during synthesis
reset_pad : smpad port map (resetn, resetno); -- reset
brdyn_pad : inpad port map (brdyn, memi.brdyn); -- bus ready
bexcn_pad : inpad port map (bexcn, memi.bexcn); -- bus exception
error_pad : odpad generic map (2) port map (ioo.errorn, errorn); -- cpu error mode
--DDM lines
inpad4 : inpad port map (audioin, ddmi.audioin);
inpad5 : inpad port map (buttons(0),ddmi.button0);
inpad6 : inpad port map (buttons(1),ddmi.button1);
inpad7 : inpad port map (buttons(2),ddmi.button2);
inpad8 : inpad port map (buttons(3),ddmi.button3);
-- d_pads: for i in 0 to 31 generate -- data bus
-- d_pad : iopad generic map (3) port map (memo.data(i), memo.bdrive((31-i)/8), memi.data(i), data(i));
-- end generate;
--
dataout <= memo.data; -- databus DDM LA
memi.data <= datain;
datasel <= memo.bdrive;
-- pio_pads : for i in 0 to 15 generate -- parallel I/O port
-- pio_pad : smiopad generic map (2) port map (ioo.piol(i), ioo.piodir(i), ioi.piol(i), pio(i));
-- end generate;
--
pioo <= ioo.piol; -- parallel I/O port DDM
ioi.piol <= pioi;
piod <= ioo.piodir;
rwen(0) <= memo.wrn(0);
memi.wrn(0) <= memo.wrn(0);
rwen(1) <= memo.wrn(1);
memi.wrn(1) <= memo.wrn(1);
rwen(2) <= memo.wrn(2);
memi.wrn(2) <= memo.wrn(2);
rwen(3) <= memo.wrn(3);
memi.wrn(3) <= memo.wrn(3);
-- rwen_pads : for i in 0 to 3 generate -- ram write strobe
-- rwen_pad : iopad generic map (2) port map (memo.wrn(i), gnd, memi.wrn(i), rwen(i));
-- end generate;
--
-- -- I/O write strobe
-- writen_pad : iopad generic map (2) port map (memo.writen, gnd, memi.writen, writen);
--
writen <= memo.writen; -- DDM LA
memi.writen <= memo.writen;
a_pads: for i in 0 to 27 generate -- memory address
a_pad : outpad generic map (3) port map (memo.address(i), address(i));
end generate;
ramsn_pads : for i in 0 to 4 generate -- ram oen/rasn
ramsn_pad : outpad generic map (2) port map (memo.ramsn(i), ramsn(i));
end generate;
ramoen_pads : for i in 0 to 4 generate -- ram chip select
eamoen_pad : outpad generic map (2) port map (memo.ramoen(i), ramoen(i));
end generate;
romsn_pads : for i in 0 to 1 generate -- rom chip select
romsn_pad : outpad generic map (2) port map (memo.romsn(i), romsn(i));
end generate;
read_pad : outpad generic map (2) port map (memo.read, read); -- memory read
oen_pad : outpad generic map (2) port map (memo.oen, oen); -- memory oen
iosn_pad : outpad generic map (2) port map (memo.iosn, iosn); -- I/O select
--
outpadb7: outpad port map (ddmo.shift_clk, shift_clk); -- DDM
outpadb8: outpad port map (ddmo.lr_out, lr_out);
outpadb9: outpad port map (ddmo.audioout, audioout);
outpadb10: for i in 0 to 6 generate
outpad101: outpad port map(ddmo.digit0(i), digit0(i));
end generate;
outpadb11: for i in 0 to 6 generate
outpad111: outpad port map(ddmo.digit1(i), digit1(i));
end generate;
outpadb12: outpad port map (ddmo.mclk, mclk);
dispen <= ddmo.dispen;
--
wd : if WDOGEN generate
wdogn_pad : odpad generic map (2) port map (ioo.wdog, wdogn); -- watchdog output
end generate;
ds : if DEBUG_UNIT generate
dsuen_pad : inpad port map (dsuen, dsi.dsui.dsuen); -- DSU enable
dsutx_pad : outpad generic map (1) port map (dso.dcomo.dsutx, dsutx);
dsurx_pad : inpad port map (dsurx, dsi.dcomi.dsurx); -- DSU receive data
dsubre_pad : inpad port map (dsubre, dsi.dsui.dsubre); -- DSU break
dsuact_pad : outpad generic map (1) port map (dso.dsuo.dsuact, dsuact);
end generate;
end ;
|
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_rxtx_bench
---- Version: 1.0.0
---- Description:
---- Unit level + sub-components testing vhdl ressource
---- 1: generate clock signals
---- 2: generate resets signals
---- 3: generate wb read/write cycles signals
---- 4: generate rx/tx external data and samples signals
---- 5: generate test sequences for sub-components
---- 6: store signals results as ASCII files
-------------------------------
---- Author(s):
---- Guillaume Rembert
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2015/11/18: initial release
---- 2015/12/28: adding random stimuli generation
---- 2016/10/19: adding sub-components (CRC + buffer) test ressources
---- 2016/10/25: adding framer sub-component test ressources + CRC checks
---- 2016/10/27: adding serdes sub-component test ressources
---- 2016/10/30: framer tests improvements
---- 2016/11/04: adding lfsr sub-component test ressources
---- 2016/11/05: adding mapper sub-component test ressources
---- 2016/11/08: adding srrc + filter sub-components test ressources
---- 2016/11/18: adding differential coder + symbols to samples mapper sub-components test ressources
---- 2016/11/20: adding files output for samples to allow external software analysis
---- 2017/15/01: adding convolutional coder
-------------------------------
--TODO: functions for sub-components interactions and checks (wb_read, wb_write, buffer_read, ...)
-- To convert hexa ASCII encoded output files (hex) to binary files (raw wav) : xxd -r -p samples.hex > samples.wav
-- To change endianness: xxd -r -p samples.hex | dd conv=swab of=samples.wav
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library work;
use work.ccsds_rxtx_functions.all;
use work.ccsds_rxtx_parameters.all;
use work.ccsds_rxtx_types.all;
--=============================================================================
-- Entity declaration for ccsds_rxtx_bench - rx/tx unit test tool
--=============================================================================
entity ccsds_rxtx_bench is
generic (
-- system parameters
CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH: integer := RX_PHYS_SIG_QUANT_DEPTH;
CCSDS_RXTX_BENCH_RXTX0_TX_PHYS_SIG_QUANT_DEPTH: integer := TX_PHYS_SIG_QUANT_DEPTH;
CCSDS_RXTX_BENCH_RXTX0_WB_ADDR_BUS_SIZE: integer := RXTX_SYSTEM_WB_ADDR_BUS_SIZE;
CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE: integer := RXTX_SYSTEM_WB_DATA_BUS_SIZE;
CCSDS_RXTX_BENCH_RXTX0_WB_WRITE_CYCLES_MAX: integer := 8;
-- sub-systems parameters
-- BUFFER
CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE : integer := 32;
CCSDS_RXTX_BENCH_BUFFER0_SIZE : integer := 16;
-- CODER DIFFERENTIAL
CCSDS_RXTX_BENCH_CODER_DIFF0_BITS_PER_CODEWORD: integer := 4;
CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE: integer := 32;
-- CODER CONVOLUTIONAL
--TODO: 2 TESTS / ONE STATIC WITH PREDIFINED INPUT/ OUTPUT + ONE DYNAMIC WITH RANDOM DATA
CCSDS_RXTX_BENCH_CODER_CONV0_CONNEXION_VECTORS: std_logic_vector_array := ("1111001", "1011011");
CCSDS_RXTX_BENCH_CODER_CONV0_CONSTRAINT_SIZE: integer := 7;
CCSDS_RXTX_BENCH_CODER_CONV0_DATA_BUS_SIZE: integer := 8; --255
CCSDS_RXTX_BENCH_CODER_CONV0_OPERATING_MODE: integer := 1;
CCSDS_RXTX_BENCH_CODER_CONV0_OUTPUT_INVERSION: boolean_array := (false, true);
CCSDS_RXTX_BENCH_CODER_CONV0_RATE_OUTPUT: integer := 2;
CCSDS_RXTX_BENCH_CODER_CONV0_SEED: std_logic_vector := "000000";
CCSDS_RXTX_BENCH_CODER_CONV0_INPUT: std_logic_vector := "10000000";
CCSDS_RXTX_BENCH_CODER_CONV0_OUTPUT: std_logic_vector := "1011101001001001";
-- CRC
CCSDS_RXTX_BENCH_CRC0_DATA: std_logic_vector := x"313233343536373839";
CCSDS_RXTX_BENCH_CRC0_INPUT_BYTES_REFLECTED: boolean := false;
CCSDS_RXTX_BENCH_CRC0_INPUT_REFLECTED: boolean := false;
CCSDS_RXTX_BENCH_CRC0_LENGTH: integer := 2;
CCSDS_RXTX_BENCH_CRC0_OUTPUT_REFLECTED: boolean := false;
CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL: std_logic_vector := x"1021";
CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL_REFLECTED: boolean := false;
CCSDS_RXTX_BENCH_CRC0_RESULT: std_logic_vector := x"e5cc";
CCSDS_RXTX_BENCH_CRC0_SEED: std_logic_vector := x"ffff";
CCSDS_RXTX_BENCH_CRC0_XOR: std_logic_vector := x"0000";
-- FILTER
CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_BUS_SIZE: integer := 32;
CCSDS_RXTX_BENCH_FILTER0_OFFSET_IQ: boolean := true;
CCSDS_RXTX_BENCH_FILTER0_OVERSAMPLING_RATIO: integer := 4;
CCSDS_RXTX_BENCH_FILTER0_ROLL_OFF: real := 0.5;
CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH: integer := 8;
CCSDS_RXTX_BENCH_FILTER0_TARGET_SNR: real := 40.0;
CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL: integer := 1;
CCSDS_RXTX_BENCH_FILTER0_MODULATION_TYPE: integer := 1;
-- FRAMER
CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE: integer := 32;
CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH: integer := 24;
CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH: integer := 2;
CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH: integer := 6;
CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO: integer := 8;
-- LFSR
CCSDS_RXTX_BENCH_LFSR0_RESULT: std_logic_vector := "1111111101001000000011101100000010011010";
CCSDS_RXTX_BENCH_LFSR0_MEMORY_SIZE: integer := 8;
CCSDS_RXTX_BENCH_LFSR0_MODE: std_logic := '0';
CCSDS_RXTX_BENCH_LFSR0_POLYNOMIAL: std_logic_vector := x"A9";
CCSDS_RXTX_BENCH_LFSR0_SEED: std_logic_vector := x"FF";
-- MAPPER BITS SYMBOLS
CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_BITS_PER_SYMBOL: integer := 2;
CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_BUS_SIZE: integer := 32;
CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_MODULATION_TYPE: integer := 1;
-- MAPPER SYMBOLS SAMPLES
CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_BITS_PER_SYMBOL: integer := 3;
CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_QUANTIZATION_DEPTH: integer := 8;
CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_TARGET_SNR: real := 40.0;
-- SERDES
CCSDS_RXTX_BENCH_SERDES0_DEPTH: integer := 32;
-- SRRC
CCSDS_RXTX_BENCH_SRRC0_APODIZATION_WINDOW_TYPE: integer := 1;
CCSDS_RXTX_BENCH_SRRC0_OVERSAMPLING_RATIO: integer := 8;
CCSDS_RXTX_BENCH_SRRC0_ROLL_OFF: real := 0.5;
CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH: integer := 16;
-- simulation/test parameters
CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_CODER_CONV0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_CODER_CONV0_WORDS_NUMBER: integer := 1000;
CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_CODER_DIFF0_WORDS_NUMBER: integer := 1000;
CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE: integer:= 8;
CCSDS_RXTX_BENCH_CRC0_RANDOM_CHECK_NUMBER: integer:= 25;
CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_FILTER0_SYMBOL_WORDS_NUMBER: integer := 1000;
CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_FRAMER0_FRAME_NUMBER: integer := 25;
CCSDS_RXTX_BENCH_LFSR0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_WORDS_NUMBER: integer := 1000;
CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_WORDS_NUMBER: integer := 1000;
CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD: time := 20 ns;
CCSDS_RXTX_BENCH_RXTX0_WB_TX_WRITE_CYCLE_NUMBER: integer := 5000;
CCSDS_RXTX_BENCH_RXTX0_WB_TX_OVERFLOW: boolean := true;
CCSDS_RXTX_BENCH_SEED: integer := 123456789;
CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_SERDES0_CYCLES_NUMBER: integer := 25;
CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD: time := 10 ns;
CCSDS_RXTX_BENCH_START_BUFFER_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_CODER_CONV_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_CODER_DIFF_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_CRC_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_FILTER_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_FRAMER_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_LFSR_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_MAPPER_BITS_SYMBOLS_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_MAPPER_SYMBOLS_SAMPLES_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION: time := 400 ns;
CCSDS_RXTX_BENCH_START_SERDES_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_SRRC_WAIT_DURATION: time := 2000 ns;
CCSDS_RXTX_BENCH_START_WB_WAIT_DURATION: time := 1600 ns;
CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_ENABLE: boolean := true;
CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_FILES_NAME: string := "samples"
);
end ccsds_rxtx_bench;
--=============================================================================
-- architecture declaration / internal processing
--=============================================================================
architecture behaviour of ccsds_rxtx_bench is
component ccsds_rxtx_top is
port(
wb_ack_o: out std_logic;
wb_adr_i: in std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_ADDR_BUS_SIZE-1 downto 0);
wb_clk_i: in std_logic;
wb_cyc_i: in std_logic;
wb_dat_i: in std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE-1 downto 0);
wb_dat_o: out std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE-1 downto 0);
wb_err_o: out std_logic;
wb_rst_i: in std_logic;
wb_rty_o: out std_logic;
wb_stb_i: in std_logic;
wb_we_i: in std_logic;
rx_clk_i: in std_logic;
rx_sam_i_i: in std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
rx_sam_q_i: in std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
rx_ena_o: out std_logic;
rx_irq_o: out std_logic;
tx_clk_i: in std_logic;
tx_dat_ser_i: in std_logic;
tx_buf_ful_o: out std_logic;
tx_idl_o: out std_logic;
tx_sam_i_o: out std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
tx_sam_q_o: out std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
tx_clk_o: out std_logic;
tx_ena_o: out std_logic
);
end component;
component ccsds_rxtx_buffer is
generic(
CCSDS_RXTX_BUFFER_DATA_BUS_SIZE : integer;
CCSDS_RXTX_BUFFER_SIZE : integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
dat_nxt_i: in std_logic;
rst_i: in std_logic;
buf_emp_o: out std_logic;
buf_ful_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_RXTX_BUFFER_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_tx_coder_convolutional is
generic(
CCSDS_TX_CODER_CONV_CONNEXION_VECTORS: std_logic_vector_array;
CCSDS_TX_CODER_CONV_CONSTRAINT_SIZE: integer;
CCSDS_TX_CODER_CONV_DATA_BUS_SIZE: integer;
CCSDS_TX_CODER_CONV_OPERATING_MODE: integer;
CCSDS_TX_CODER_CONV_OUTPUT_INVERSION: boolean_array;
CCSDS_TX_CODER_CONV_RATE_OUTPUT: integer;
CCSDS_TX_CODER_CONV_SEED: std_logic_vector
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_CODER_CONV_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
bus_o: out std_logic;
dat_o: out std_logic_vector(CCSDS_TX_CODER_CONV_DATA_BUS_SIZE*CCSDS_TX_CODER_CONV_RATE_OUTPUT-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_tx_coder_differential is
generic(
CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD: integer;
CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE: integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_rxtx_crc is
generic(
CCSDS_RXTX_CRC_DATA_LENGTH: integer;
CCSDS_RXTX_CRC_FINAL_XOR: std_logic_vector;
CCSDS_RXTX_CRC_INPUT_BYTES_REFLECTED: boolean;
CCSDS_RXTX_CRC_INPUT_REFLECTED: boolean;
CCSDS_RXTX_CRC_LENGTH: integer;
CCSDS_RXTX_CRC_OUTPUT_REFLECTED: boolean;
CCSDS_RXTX_CRC_POLYNOMIAL: std_logic_vector;
CCSDS_RXTX_CRC_POLYNOMIAL_REFLECTED: boolean;
CCSDS_RXTX_CRC_SEED: std_logic_vector
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_RXTX_CRC_DATA_LENGTH*8-1 downto 0);
nxt_i: in std_logic;
pad_dat_i: in std_logic_vector(CCSDS_RXTX_CRC_LENGTH*8-1 downto 0);
pad_dat_val_i: in std_logic;
rst_i: in std_logic;
crc_o: out std_logic_vector(CCSDS_RXTX_CRC_LENGTH*8-1 downto 0);
dat_o: out std_logic_vector(CCSDS_RXTX_CRC_DATA_LENGTH*8-1 downto 0);
bus_o: out std_logic;
dat_val_o: out std_logic
);
end component;
component ccsds_tx_filter is
generic(
CCSDS_TX_FILTER_OFFSET_IQ: boolean;
CCSDS_TX_FILTER_OVERSAMPLING_RATIO: integer;
CCSDS_TX_FILTER_SIG_QUANT_DEPTH: integer;
CCSDS_TX_FILTER_MODULATION_TYPE: integer;
CCSDS_TX_FILTER_TARGET_SNR: real;
CCSDS_TX_FILTER_BITS_PER_SYMBOL: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
sym_i_i: in std_logic_vector(CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0);
sym_q_i: in std_logic_vector(CCSDS_TX_FILTER_BITS_PER_SYMBOL-1 downto 0);
sym_val_i: in std_logic;
sam_i_o: out std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
sam_q_o: out std_logic_vector(CCSDS_TX_FILTER_SIG_QUANT_DEPTH-1 downto 0);
sam_val_o: out std_logic
);
end component;
component ccsds_tx_framer is
generic (
CCSDS_TX_FRAMER_HEADER_LENGTH: integer;
CCSDS_TX_FRAMER_FOOTER_LENGTH: integer;
CCSDS_TX_FRAMER_DATA_LENGTH: integer;
CCSDS_TX_FRAMER_DATA_BUS_SIZE: integer;
CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
dat_o: out std_logic_vector((CCSDS_TX_FRAMER_HEADER_LENGTH+CCSDS_TX_FRAMER_FOOTER_LENGTH+CCSDS_TX_FRAMER_DATA_LENGTH)*8-1 downto 0);
dat_val_o: out std_logic;
dat_nxt_o: out std_logic;
idl_o: out std_logic
);
end component;
component ccsds_rxtx_lfsr is
generic(
CCSDS_RXTX_LFSR_DATA_BUS_SIZE: integer;
CCSDS_RXTX_LFSR_MEMORY_SIZE: integer;
CCSDS_RXTX_LFSR_MODE: std_logic;
CCSDS_RXTX_LFSR_POLYNOMIAL: std_logic_vector;
CCSDS_RXTX_LFSR_SEED: std_logic_vector
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_RXTX_LFSR_DATA_BUS_SIZE-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_tx_mapper_bits_symbols is
generic(
CCSDS_TX_MAPPER_DATA_BUS_SIZE: integer;
CCSDS_TX_MAPPER_MODULATION_TYPE: integer;
CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer
);
port(
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_MAPPER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
sym_i_o: out std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0);
sym_q_o: out std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0);
sym_val_o: out std_logic
);
end component;
component ccsds_tx_mapper_symbols_samples is
generic(
CCSDS_TX_MAPPER_TARGET_SNR: real;
CCSDS_TX_MAPPER_BITS_PER_SYMBOL: integer;
CCSDS_TX_MAPPER_QUANTIZATION_DEPTH: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
sym_i: in std_logic_vector(CCSDS_TX_MAPPER_BITS_PER_SYMBOL-1 downto 0);
sym_val_i: in std_logic;
sam_val_o: out std_logic;
sam_o: out std_logic_vector(CCSDS_TX_MAPPER_QUANTIZATION_DEPTH-1 downto 0)
);
end component;
component ccsds_rxtx_serdes is
generic (
CCSDS_RXTX_SERDES_DEPTH : integer
);
port(
clk_i: in std_logic;
dat_par_i: in std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0);
dat_par_val_i: in std_logic;
dat_ser_i: in std_logic;
dat_ser_val_i: in std_logic;
rst_i: in std_logic;
bus_o: out std_logic;
dat_par_o: out std_logic_vector(CCSDS_RXTX_SERDES_DEPTH-1 downto 0);
dat_par_val_o: out std_logic;
dat_ser_o: out std_logic;
dat_ser_val_o: out std_logic
);
end component;
component ccsds_rxtx_srrc is
generic(
CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE: integer;
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO: integer;
CCSDS_RXTX_SRRC_ROLL_OFF: real;
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
sam_i: in std_logic_vector(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH-1 downto 0);
sam_val_i: in std_logic;
sam_o: out std_logic_vector(CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH-1 downto 0);
sam_val_o: out std_logic
);
end component;
-- internal constants
constant CCSDS_RXTX_BENCH_FILTER0_MAPPER_CLK_PERIOD: time := CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD*CCSDS_RXTX_BENCH_FILTER0_OVERSAMPLING_RATIO;
constant CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_CLK_PERIOD: time := CCSDS_RXTX_BENCH_FILTER0_MAPPER_CLK_PERIOD * CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_BUS_SIZE * CCSDS_RXTX_BENCH_FILTER0_MODULATION_TYPE / (CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL * 2);
constant CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_CLK_PERIOD: time := CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_CLK_PERIOD * CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_BUS_SIZE * CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_MODULATION_TYPE / (CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_BITS_PER_SYMBOL * 2);
constant CCSDS_RXTX_BENCH_RXTX0_TX_CLK_PERIOD: time := CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD/8;
constant CCSDS_RXTX_BENCH_RXTX0_RX_CLK_PERIOD: time := CCSDS_RXTX_BENCH_RXTX0_TX_CLK_PERIOD;
-- internal variables
signal bench_ena_buffer0_random_data: std_logic := '0';
signal bench_ena_coder_conv0_random_data: std_logic := '0';
signal bench_ena_coder_diff0_random_data: std_logic := '0';
signal bench_ena_crc0_random_data: std_logic := '0';
signal bench_ena_filter0_random_data: std_logic := '0';
signal bench_ena_framer0_random_data: std_logic := '0';
signal bench_ena_mapper_bits_symbols0_random_data: std_logic := '0';
signal bench_ena_mapper_symbols_samples0_random_data: std_logic := '0';
signal bench_ena_rxtx0_random_data: std_logic := '0';
signal bench_ena_serdes0_random_data: std_logic := '0';
file CCSDS_RXTX_BENCH_FILTER0_OUTPUT_CSV_IQ_FILE: text open write_mode is out CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_FILES_NAME & "_filter0_iq.csv";
file CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_IQ_FILE: text open write_mode is out CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_FILES_NAME & "_filter0_iq.hex";
file CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_I_FILE: text open write_mode is out CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_FILES_NAME & "_filter0_i.hex";
file CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_Q_FILE: text open write_mode is out CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_FILES_NAME & "_filter0_q.hex";
file CCSDS_RXTX_BENCH_SRRC0_OUTPUT_HEX_FILE: text open write_mode is out CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_FILES_NAME & "_srrc0.hex";
-- synthetic generated stimuli
--NB: un-initialized on purposes - to allow observation of components default behaviour
-- wishbone bus
signal bench_sti_rxtx0_wb_clk: std_logic;
signal bench_sti_rxtx0_wb_rst: std_logic;
signal bench_sti_rxtx0_wb_adr: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_ADDR_BUS_SIZE-1 downto 0);
signal bench_sti_rxtx0_wb_cyc: std_logic;
signal bench_sti_rxtx0_wb_dat: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE-1 downto 0);
signal bench_sti_rxtx0_wb_random_dat: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE-1 downto 0);
signal bench_sti_rxtx0_wb_stb: std_logic;
signal bench_sti_rxtx0_wb_we: std_logic;
-- rx
signal bench_sti_rxtx0_rx_clk: std_logic;
signal bench_sti_rxtx0_rx_data_next: std_logic;
signal bench_sti_rxtx0_rx_samples_i: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
signal bench_sti_rxtx0_rx_samples_q: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
-- tx
signal bench_sti_rxtx0_tx_clk: std_logic;
signal bench_sti_rxtx0_tx_data_ser: std_logic;
-- buffer
signal bench_sti_buffer0_clk: std_logic;
signal bench_sti_buffer0_rst: std_logic;
signal bench_sti_buffer0_next_data: std_logic;
signal bench_sti_buffer0_data: std_logic_vector(CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE-1 downto 0);
signal bench_sti_buffer0_data_valid: std_logic;
-- coder convolutional
signal bench_sti_coder_conv0_clk: std_logic;
signal bench_sti_coder_conv0_rst: std_logic;
signal bench_sti_coder_conv0_dat: std_logic_vector(CCSDS_RXTX_BENCH_CODER_CONV0_DATA_BUS_SIZE-1 downto 0);
signal bench_sti_coder_conv0_dat_val: std_logic;
-- coder differential
signal bench_sti_coder_diff0_clk: std_logic;
signal bench_sti_coder_diff0_rst: std_logic;
signal bench_sti_coder_diff0_dat: std_logic_vector(CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE-1 downto 0);
signal bench_sti_coder_diff0_dat_val: std_logic;
-- crc
signal bench_sti_crc0_clk: std_logic;
signal bench_sti_crc0_rst: std_logic;
signal bench_sti_crc0_nxt: std_logic;
signal bench_sti_crc0_data: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_DATA'length-1 downto 0);
signal bench_sti_crc0_padding_data_valid: std_logic;
signal bench_sti_crc0_check_nxt: std_logic;
signal bench_sti_crc0_check_data: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8-1 downto 0);
signal bench_sti_crc0_check_padding_data: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_LENGTH*8-1 downto 0);
signal bench_sti_crc0_check_padding_data_valid: std_logic;
signal bench_sti_crc0_random_nxt: std_logic;
signal bench_sti_crc0_random_data: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8-1 downto 0);
signal bench_sti_crc0_random_padding_data_valid: std_logic;
-- filter
signal bench_sti_filter0_clk: std_logic;
signal bench_sti_filter0_rst: std_logic;
signal bench_sti_filter0_sym_i: std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL-1 downto 0);
signal bench_sti_filter0_sym_q: std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL-1 downto 0);
signal bench_sti_filter0_sym_val: std_logic;
signal bench_sti_filter0_mapper_data: std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_BUS_SIZE-1 downto 0);
signal bench_sti_filter0_mapper_clk: std_logic;
signal bench_sti_filter0_mapper_dat_val: std_logic;
-- framer
signal bench_sti_framer0_clk: std_logic;
signal bench_sti_framer0_rst: std_logic;
signal bench_sti_framer0_data_valid: std_logic;
signal bench_sti_framer0_data: std_logic_vector(CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE-1 downto 0);
-- lfsr
signal bench_sti_lfsr0_clk: std_logic;
signal bench_sti_lfsr0_rst: std_logic;
-- mapper bits symbols
signal bench_sti_mapper_bits_symbols0_clk: std_logic;
signal bench_sti_mapper_bits_symbols0_rst: std_logic;
signal bench_sti_mapper_bits_symbols0_data: std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_BUS_SIZE-1 downto 0);
signal bench_sti_mapper_bits_symbols0_dat_val: std_logic;
-- mapper symbols samples
signal bench_sti_mapper_symbols_samples0_clk: std_logic;
signal bench_sti_mapper_symbols_samples0_rst: std_logic;
signal bench_sti_mapper_symbols_samples0_sym: std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_BITS_PER_SYMBOL-1 downto 0);
signal bench_sti_mapper_symbols_samples0_sym_val: std_logic;
-- serdes
signal bench_sti_serdes0_clk: std_logic;
signal bench_sti_serdes0_rst: std_logic;
signal bench_sti_serdes0_data_par_valid: std_logic;
signal bench_sti_serdes0_data_par: std_logic_vector(CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 downto 0);
signal bench_sti_serdes0_data_ser_valid: std_logic;
signal bench_sti_serdes0_data_ser: std_logic;
-- srrc
signal bench_sti_srrc0_clk: std_logic;
signal bench_sti_srrc0_rst: std_logic;
signal bench_sti_srrc0_sam: std_logic_vector(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-1 downto 0);
signal bench_sti_srrc0_sam_val: std_logic;
-- core generated response
-- wishbone bus
signal bench_res_rxtx0_wb_ack: std_logic;
signal bench_res_rxtx0_wb_dat: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE-1 downto 0);
signal bench_res_rxtx0_wb_err: std_logic;
signal bench_res_rxtx0_wb_rty: std_logic;
-- rx
signal bench_res_rxtx0_rx_ena: std_logic;
signal bench_res_rxtx0_rx_irq: std_logic;
-- tx
signal bench_res_rxtx0_tx_clk: std_logic;
signal bench_res_rxtx0_tx_buf_ful: std_logic;
signal bench_res_rxtx0_tx_idl: std_logic;
signal bench_res_rxtx0_tx_samples_i: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_rxtx0_tx_samples_q: std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_TX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_rxtx0_tx_ena: std_logic;
-- buffer
signal bench_res_buffer0_buffer_empty: std_logic;
signal bench_res_buffer0_buffer_full: std_logic;
signal bench_res_buffer0_data: std_logic_vector(CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE-1 downto 0);
signal bench_res_buffer0_data_valid: std_logic;
-- coder convolutional
signal bench_res_coder_conv0_dat: std_logic_vector(CCSDS_RXTX_BENCH_CODER_CONV0_DATA_BUS_SIZE*CCSDS_RXTX_BENCH_CODER_CONV0_RATE_OUTPUT-1 downto 0);
signal bench_res_coder_conv0_dat_val: std_logic;
signal bench_res_coder_conv0_bus: std_logic;
-- coder differential
signal bench_res_coder_diff0_dat: std_logic_vector(CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE-1 downto 0);
signal bench_res_coder_diff0_dat_val: std_logic;
-- crc
signal bench_res_crc0_busy: std_logic;
signal bench_res_crc0_crc: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_LENGTH*8-1 downto 0);
signal bench_res_crc0_data: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_DATA'length-1 downto 0);
signal bench_res_crc0_data_valid: std_logic;
signal bench_res_crc0_check_busy: std_logic;
signal bench_res_crc0_check_crc: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_LENGTH*8-1 downto 0);
signal bench_res_crc0_check_data: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8-1 downto 0);
signal bench_res_crc0_check_data_valid: std_logic;
signal bench_res_crc0_random_busy: std_logic;
signal bench_res_crc0_random_crc: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_LENGTH*8-1 downto 0);
signal bench_res_crc0_random_data: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8-1 downto 0);
signal bench_res_crc0_random_data_valid: std_logic;
-- filter
signal bench_res_filter0_sam_i: std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_filter0_sam_q: std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_filter0_sam_val: std_logic;
signal bench_res_filter0_srrc_sam_i: std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_filter0_srrc_sam_q: std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_filter0_srrc_sam_i_val: std_logic;
signal bench_res_filter0_srrc_sam_q_val: std_logic;
-- framer
signal bench_res_framer0_data_valid: std_logic;
signal bench_res_framer0_dat_nxt: std_logic;
signal bench_res_framer0_idl: std_logic;
signal bench_res_framer0_data: std_logic_vector((CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH)*8-1 downto 0);
-- lfsr
signal bench_res_lfsr0_data_valid: std_logic;
signal bench_res_lfsr0_data: std_logic_vector(CCSDS_RXTX_BENCH_LFSR0_RESULT'length-1 downto 0);
-- mapper bits symbols
signal bench_res_mapper_bits_symbols0_sym_i: std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_BITS_PER_SYMBOL-1 downto 0);
signal bench_res_mapper_bits_symbols0_sym_q: std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_BITS_PER_SYMBOL-1 downto 0);
signal bench_res_mapper_bits_symbols0_sym_val: std_logic;
-- mapper symbols samples
signal bench_res_mapper_symbols_samples0_sam: std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_QUANTIZATION_DEPTH-1 downto 0);
signal bench_res_mapper_symbols_samples0_sam_val: std_logic;
-- serdes
signal bench_res_serdes0_busy: std_logic;
signal bench_res_serdes0_data_par: std_logic_vector(CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 downto 0);
signal bench_res_serdes0_data_par_valid: std_logic;
signal bench_res_serdes0_data_ser: std_logic;
signal bench_res_serdes0_data_ser_valid: std_logic;
-- srrc
signal bench_res_srrc0_sam: std_logic_vector(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_srrc0_sam_val: std_logic;
signal bench_res_srrc1_sam: std_logic_vector(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-1 downto 0);
signal bench_res_srrc1_sam_val: std_logic;
--=============================================================================
-- architecture begin
--=============================================================================
begin
-- Instance(s) of unit under test
rxtx_000: ccsds_rxtx_top
port map(
wb_ack_o => bench_res_rxtx0_wb_ack,
wb_adr_i => bench_sti_rxtx0_wb_adr,
wb_clk_i => bench_sti_rxtx0_wb_clk,
wb_cyc_i => bench_sti_rxtx0_wb_cyc,
wb_dat_i => bench_sti_rxtx0_wb_dat,
wb_dat_o => bench_res_rxtx0_wb_dat,
wb_err_o => bench_res_rxtx0_wb_err,
wb_rst_i => bench_sti_rxtx0_wb_rst,
wb_rty_o => bench_res_rxtx0_wb_rty,
wb_stb_i => bench_sti_rxtx0_wb_stb,
wb_we_i => bench_sti_rxtx0_wb_we,
rx_clk_i => bench_sti_rxtx0_rx_clk,
rx_sam_i_i => bench_sti_rxtx0_rx_samples_i,
rx_sam_q_i => bench_sti_rxtx0_rx_samples_q,
rx_irq_o => bench_res_rxtx0_rx_irq,
rx_ena_o => bench_res_rxtx0_rx_ena,
tx_clk_i => bench_sti_rxtx0_tx_clk,
tx_dat_ser_i => bench_sti_rxtx0_tx_data_ser,
tx_sam_i_o => bench_res_rxtx0_tx_samples_i,
tx_sam_q_o => bench_res_rxtx0_tx_samples_q,
tx_clk_o => bench_res_rxtx0_tx_clk,
tx_buf_ful_o => bench_res_rxtx0_tx_buf_ful,
tx_idl_o => bench_res_rxtx0_tx_idl,
tx_ena_o => bench_res_rxtx0_tx_ena
);
-- Instance(s) of sub-components under test
buffer_000: ccsds_rxtx_buffer
generic map(
CCSDS_RXTX_BUFFER_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE,
CCSDS_RXTX_BUFFER_SIZE => CCSDS_RXTX_BENCH_BUFFER0_SIZE
)
port map(
clk_i => bench_sti_buffer0_clk,
rst_i => bench_sti_buffer0_rst,
dat_val_i => bench_sti_buffer0_data_valid,
dat_i => bench_sti_buffer0_data,
dat_val_o => bench_res_buffer0_data_valid,
buf_emp_o => bench_res_buffer0_buffer_empty,
buf_ful_o => bench_res_buffer0_buffer_full,
dat_nxt_i => bench_sti_buffer0_next_data,
dat_o => bench_res_buffer0_data
);
coder_convolutionial_000: ccsds_tx_coder_convolutional
generic map(
CCSDS_TX_CODER_CONV_CONNEXION_VECTORS => CCSDS_RXTX_BENCH_CODER_CONV0_CONNEXION_VECTORS,
CCSDS_TX_CODER_CONV_CONSTRAINT_SIZE => CCSDS_RXTX_BENCH_CODER_CONV0_CONSTRAINT_SIZE,
CCSDS_TX_CODER_CONV_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_CODER_CONV0_DATA_BUS_SIZE,
CCSDS_TX_CODER_CONV_OPERATING_MODE => CCSDS_RXTX_BENCH_CODER_CONV0_OPERATING_MODE,
CCSDS_TX_CODER_CONV_OUTPUT_INVERSION => CCSDS_RXTX_BENCH_CODER_CONV0_OUTPUT_INVERSION,
CCSDS_TX_CODER_CONV_RATE_OUTPUT => CCSDS_RXTX_BENCH_CODER_CONV0_RATE_OUTPUT,
CCSDS_TX_CODER_CONV_SEED => CCSDS_RXTX_BENCH_CODER_CONV0_SEED
)
port map(
clk_i => bench_sti_coder_conv0_clk,
rst_i => bench_sti_coder_conv0_rst,
dat_val_i => bench_sti_coder_conv0_dat_val,
dat_i => bench_sti_coder_conv0_dat,
bus_o => bench_res_coder_conv0_bus,
dat_val_o => bench_res_coder_conv0_dat_val,
dat_o => bench_res_coder_conv0_dat
);
coder_differential_000: ccsds_tx_coder_differential
generic map(
CCSDS_TX_CODER_DIFF_BITS_PER_CODEWORD => CCSDS_RXTX_BENCH_CODER_DIFF0_BITS_PER_CODEWORD,
CCSDS_TX_CODER_DIFF_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE
)
port map(
clk_i => bench_sti_coder_diff0_clk,
rst_i => bench_sti_coder_diff0_rst,
dat_val_i => bench_sti_coder_diff0_dat_val,
dat_i => bench_sti_coder_diff0_dat,
dat_val_o => bench_res_coder_diff0_dat_val,
dat_o => bench_res_coder_diff0_dat
);
crc_000: ccsds_rxtx_crc
generic map(
CCSDS_RXTX_CRC_DATA_LENGTH => CCSDS_RXTX_BENCH_CRC0_DATA'length/8,
CCSDS_RXTX_CRC_LENGTH => CCSDS_RXTX_BENCH_CRC0_LENGTH,
CCSDS_RXTX_CRC_POLYNOMIAL => CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL,
CCSDS_RXTX_CRC_SEED => CCSDS_RXTX_BENCH_CRC0_SEED,
CCSDS_RXTX_CRC_INPUT_REFLECTED => CCSDS_RXTX_BENCH_CRC0_INPUT_REFLECTED,
CCSDS_RXTX_CRC_INPUT_BYTES_REFLECTED => CCSDS_RXTX_BENCH_CRC0_INPUT_BYTES_REFLECTED,
CCSDS_RXTX_CRC_OUTPUT_REFLECTED => CCSDS_RXTX_BENCH_CRC0_OUTPUT_REFLECTED,
CCSDS_RXTX_CRC_POLYNOMIAL_REFLECTED => CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL_REFLECTED,
CCSDS_RXTX_CRC_FINAL_XOR => CCSDS_RXTX_BENCH_CRC0_XOR
)
port map(
clk_i => bench_sti_crc0_clk,
rst_i => bench_sti_crc0_rst,
nxt_i => bench_sti_crc0_nxt,
bus_o => bench_res_crc0_busy,
dat_i => bench_sti_crc0_data,
pad_dat_i => (others => '0'),
pad_dat_val_i => bench_sti_crc0_padding_data_valid,
crc_o => bench_res_crc0_crc,
dat_o => bench_res_crc0_data,
dat_val_o => bench_res_crc0_data_valid
);
crc_001: ccsds_rxtx_crc
generic map(
CCSDS_RXTX_CRC_DATA_LENGTH => CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE,
CCSDS_RXTX_CRC_LENGTH => CCSDS_RXTX_BENCH_CRC0_LENGTH,
CCSDS_RXTX_CRC_POLYNOMIAL => CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL,
CCSDS_RXTX_CRC_SEED => CCSDS_RXTX_BENCH_CRC0_SEED,
CCSDS_RXTX_CRC_INPUT_REFLECTED => CCSDS_RXTX_BENCH_CRC0_INPUT_REFLECTED,
CCSDS_RXTX_CRC_INPUT_BYTES_REFLECTED => CCSDS_RXTX_BENCH_CRC0_INPUT_BYTES_REFLECTED,
CCSDS_RXTX_CRC_OUTPUT_REFLECTED => CCSDS_RXTX_BENCH_CRC0_OUTPUT_REFLECTED,
CCSDS_RXTX_CRC_POLYNOMIAL_REFLECTED => CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL_REFLECTED,
CCSDS_RXTX_CRC_FINAL_XOR => CCSDS_RXTX_BENCH_CRC0_XOR
)
port map(
clk_i => bench_sti_crc0_clk,
rst_i => bench_sti_crc0_rst,
nxt_i => bench_sti_crc0_random_nxt,
bus_o => bench_res_crc0_random_busy,
dat_i => bench_sti_crc0_random_data,
pad_dat_i => (others => '0'),
pad_dat_val_i => bench_sti_crc0_random_padding_data_valid,
crc_o => bench_res_crc0_random_crc,
dat_o => bench_res_crc0_random_data,
dat_val_o => bench_res_crc0_random_data_valid
);
crc_002: ccsds_rxtx_crc
generic map(
CCSDS_RXTX_CRC_DATA_LENGTH => CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE,
CCSDS_RXTX_CRC_LENGTH => CCSDS_RXTX_BENCH_CRC0_LENGTH,
CCSDS_RXTX_CRC_POLYNOMIAL => CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL,
CCSDS_RXTX_CRC_SEED => CCSDS_RXTX_BENCH_CRC0_SEED,
CCSDS_RXTX_CRC_INPUT_REFLECTED => CCSDS_RXTX_BENCH_CRC0_INPUT_REFLECTED,
CCSDS_RXTX_CRC_INPUT_BYTES_REFLECTED => CCSDS_RXTX_BENCH_CRC0_INPUT_BYTES_REFLECTED,
CCSDS_RXTX_CRC_OUTPUT_REFLECTED => CCSDS_RXTX_BENCH_CRC0_OUTPUT_REFLECTED,
CCSDS_RXTX_CRC_POLYNOMIAL_REFLECTED => CCSDS_RXTX_BENCH_CRC0_POLYNOMIAL_REFLECTED,
CCSDS_RXTX_CRC_FINAL_XOR => CCSDS_RXTX_BENCH_CRC0_XOR
)
port map(
clk_i => bench_sti_crc0_clk,
rst_i => bench_sti_crc0_rst,
nxt_i => bench_sti_crc0_check_nxt,
bus_o => bench_res_crc0_check_busy,
dat_i => bench_sti_crc0_check_data,
pad_dat_val_i => bench_sti_crc0_check_padding_data_valid,
pad_dat_i => bench_sti_crc0_check_padding_data,
crc_o => bench_res_crc0_check_crc,
dat_o => bench_res_crc0_check_data,
dat_val_o => bench_res_crc0_check_data_valid
);
filter000: ccsds_tx_filter
generic map(
CCSDS_TX_FILTER_OVERSAMPLING_RATIO => CCSDS_RXTX_BENCH_FILTER0_OVERSAMPLING_RATIO,
CCSDS_TX_FILTER_OFFSET_IQ => CCSDS_RXTX_BENCH_FILTER0_OFFSET_IQ,
CCSDS_TX_FILTER_SIG_QUANT_DEPTH => CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH,
CCSDS_TX_FILTER_MODULATION_TYPE => CCSDS_RXTX_BENCH_FILTER0_MODULATION_TYPE,
CCSDS_TX_FILTER_TARGET_SNR => CCSDS_RXTX_BENCH_FILTER0_TARGET_SNR,
CCSDS_TX_FILTER_BITS_PER_SYMBOL => CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL
)
port map(
clk_i => bench_sti_filter0_clk,
sym_i_i => bench_sti_filter0_sym_i,
sym_q_i => bench_sti_filter0_sym_q,
sym_val_i => bench_sti_filter0_sym_val,
rst_i => bench_sti_filter0_rst,
sam_val_o => bench_res_filter0_sam_val,
sam_i_o => bench_res_filter0_sam_i,
sam_q_o => bench_res_filter0_sam_q
);
framer_000: ccsds_tx_framer
generic map (
CCSDS_TX_FRAMER_HEADER_LENGTH => CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH,
CCSDS_TX_FRAMER_FOOTER_LENGTH => CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH,
CCSDS_TX_FRAMER_DATA_LENGTH => CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH,
CCSDS_TX_FRAMER_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE,
CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO => CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO
)
port map(
clk_i => bench_sti_framer0_clk,
rst_i => bench_sti_framer0_rst,
dat_val_i => bench_sti_framer0_data_valid,
dat_i => bench_sti_framer0_data,
dat_val_o => bench_res_framer0_data_valid,
dat_o => bench_res_framer0_data,
dat_nxt_o => bench_res_framer0_dat_nxt,
idl_o => bench_res_framer0_idl
);
lfsr_000: ccsds_rxtx_lfsr
generic map(
CCSDS_RXTX_LFSR_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_LFSR0_RESULT'length,
CCSDS_RXTX_LFSR_MEMORY_SIZE => CCSDS_RXTX_BENCH_LFSR0_MEMORY_SIZE,
CCSDS_RXTX_LFSR_MODE => CCSDS_RXTX_BENCH_LFSR0_MODE,
CCSDS_RXTX_LFSR_POLYNOMIAL => CCSDS_RXTX_BENCH_LFSR0_POLYNOMIAL,
CCSDS_RXTX_LFSR_SEED => CCSDS_RXTX_BENCH_LFSR0_SEED
)
port map(
clk_i => bench_sti_lfsr0_clk,
rst_i => bench_sti_lfsr0_rst,
dat_val_o => bench_res_lfsr0_data_valid,
dat_o => bench_res_lfsr0_data
);
mapper_bits_symbols_000: ccsds_tx_mapper_bits_symbols
generic map(
CCSDS_TX_MAPPER_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_BUS_SIZE,
CCSDS_TX_MAPPER_MODULATION_TYPE => CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_MODULATION_TYPE,
CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_BITS_PER_SYMBOL
)
port map(
clk_i => bench_sti_mapper_bits_symbols0_clk,
dat_i => bench_sti_mapper_bits_symbols0_data,
dat_val_i => bench_sti_mapper_bits_symbols0_dat_val,
rst_i => bench_sti_mapper_bits_symbols0_rst,
sym_i_o => bench_res_mapper_bits_symbols0_sym_i,
sym_q_o => bench_res_mapper_bits_symbols0_sym_q,
sym_val_o => bench_res_mapper_bits_symbols0_sym_val
);
mapper_bits_symbols_001: ccsds_tx_mapper_bits_symbols
generic map(
CCSDS_TX_MAPPER_DATA_BUS_SIZE => CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_BUS_SIZE,
CCSDS_TX_MAPPER_MODULATION_TYPE => CCSDS_RXTX_BENCH_FILTER0_MODULATION_TYPE,
CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL
)
port map(
clk_i => bench_sti_filter0_mapper_clk,
dat_i => bench_sti_filter0_mapper_data,
dat_val_i => bench_sti_filter0_mapper_dat_val,
rst_i => bench_sti_filter0_rst,
sym_i_o => bench_sti_filter0_sym_i,
sym_q_o => bench_sti_filter0_sym_q,
sym_val_o => bench_sti_filter0_sym_val
);
mapper_symbols_samples_000: ccsds_tx_mapper_symbols_samples
generic map(
CCSDS_TX_MAPPER_QUANTIZATION_DEPTH => CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_QUANTIZATION_DEPTH,
CCSDS_TX_MAPPER_TARGET_SNR => CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_TARGET_SNR,
CCSDS_TX_MAPPER_BITS_PER_SYMBOL => CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_BITS_PER_SYMBOL
)
port map(
clk_i => bench_sti_mapper_symbols_samples0_clk,
sym_i => bench_sti_mapper_symbols_samples0_sym,
sym_val_i => bench_sti_mapper_symbols_samples0_sym_val,
rst_i => bench_sti_mapper_symbols_samples0_rst,
sam_o => bench_res_mapper_symbols_samples0_sam,
sam_val_o => bench_res_mapper_symbols_samples0_sam_val
);
serdes_000: ccsds_rxtx_serdes
generic map(
CCSDS_RXTX_SERDES_DEPTH => CCSDS_RXTX_BENCH_SERDES0_DEPTH
)
port map(
clk_i => bench_sti_serdes0_clk,
dat_par_i => bench_sti_serdes0_data_par,
dat_par_val_i => bench_sti_serdes0_data_par_valid,
dat_ser_i => bench_sti_serdes0_data_ser,
dat_ser_val_i => bench_sti_serdes0_data_ser_valid,
rst_i => bench_sti_serdes0_rst,
bus_o => bench_res_serdes0_busy,
dat_par_o => bench_res_serdes0_data_par,
dat_par_val_o => bench_res_serdes0_data_par_valid,
dat_ser_o => bench_res_serdes0_data_ser,
dat_ser_val_o => bench_res_serdes0_data_ser_valid
);
srrc_000: ccsds_rxtx_srrc
generic map(
CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE => CCSDS_RXTX_BENCH_SRRC0_APODIZATION_WINDOW_TYPE,
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO => CCSDS_RXTX_BENCH_SRRC0_OVERSAMPLING_RATIO,
CCSDS_RXTX_SRRC_ROLL_OFF => CCSDS_RXTX_BENCH_SRRC0_ROLL_OFF,
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH => CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH
)
port map(
clk_i => bench_sti_srrc0_clk,
sam_i => bench_sti_srrc0_sam,
sam_val_i => bench_sti_srrc0_sam_val,
rst_i => bench_sti_srrc0_rst,
sam_o => bench_res_srrc0_sam,
sam_val_o => bench_res_srrc0_sam_val
);
srrc_001: ccsds_rxtx_srrc
generic map(
CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE => CCSDS_RXTX_BENCH_SRRC0_APODIZATION_WINDOW_TYPE,
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO => CCSDS_RXTX_BENCH_SRRC0_OVERSAMPLING_RATIO,
CCSDS_RXTX_SRRC_ROLL_OFF => CCSDS_RXTX_BENCH_SRRC0_ROLL_OFF,
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH => CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH
)
port map(
clk_i => bench_sti_srrc0_clk,
sam_i => bench_res_srrc0_sam,
sam_val_i => bench_res_srrc0_sam_val,
rst_i => bench_sti_srrc0_rst,
sam_o => bench_res_srrc1_sam,
sam_val_o => bench_res_srrc1_sam_val
);
srrc_002: ccsds_rxtx_srrc
generic map(
CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE => 1,
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO => CCSDS_RXTX_BENCH_FILTER0_OVERSAMPLING_RATIO,
CCSDS_RXTX_SRRC_ROLL_OFF => CCSDS_RXTX_BENCH_FILTER0_ROLL_OFF,
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH => CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH
)
port map(
clk_i => bench_sti_filter0_clk,
sam_i => bench_res_filter0_sam_i,
sam_val_i => bench_res_filter0_sam_val,
rst_i => bench_sti_filter0_rst,
sam_o => bench_res_filter0_srrc_sam_i,
sam_val_o => bench_res_filter0_srrc_sam_i_val
);
srrc_003: ccsds_rxtx_srrc
generic map(
CCSDS_RXTX_SRRC_APODIZATION_WINDOW_TYPE => 1,
CCSDS_RXTX_SRRC_OVERSAMPLING_RATIO => CCSDS_RXTX_BENCH_FILTER0_OVERSAMPLING_RATIO,
CCSDS_RXTX_SRRC_ROLL_OFF => CCSDS_RXTX_BENCH_FILTER0_ROLL_OFF,
CCSDS_RXTX_SRRC_SIG_QUANT_DEPTH => CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH
)
port map(
clk_i => bench_sti_filter0_clk,
sam_i => bench_res_filter0_sam_q,
sam_val_i => bench_res_filter0_sam_val,
rst_i => bench_sti_filter0_rst,
sam_o => bench_res_filter0_srrc_sam_q,
sam_val_o => bench_res_filter0_srrc_sam_q_val
);
--=============================================================================
-- Begin of bench_sti_rxtx0_wb_clkp
-- bench_sti_rxtx0_wb_clk generation
--=============================================================================
-- read:
-- write: bench_sti_rxtx0_wb_clk
-- r/w:
BENCH_STI_RXTX0_WB_CLKP : process
begin
bench_sti_rxtx0_wb_clk <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD/2;
bench_sti_rxtx0_wb_clk <= '0';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_rxtx0_rx_clkp
-- bench_sti_rxtx0_rx_clk generation
--=============================================================================
-- read:
-- write: bench_sti_rxtx0_rx_clk
-- r/w:
BENCH_STI_RXTX0_RX_CLKP : process
begin
bench_sti_rxtx0_rx_clk <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_RX_CLK_PERIOD/2;
bench_sti_rxtx0_rx_clk <= '0';
wait for CCSDS_RXTX_BENCH_RXTX0_RX_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_rxtx0_tx_clkp
-- bench_sti_rxtx0_tx_clk generation
--=============================================================================
-- read:
-- write: bench_sti_rxtx0_tx_clk
-- r/w:
BENCH_STI_RXTX0_TX_CLKP : process
begin
bench_sti_rxtx0_tx_clk <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_TX_CLK_PERIOD/2;
bench_sti_rxtx0_tx_clk <= '0';
wait for CCSDS_RXTX_BENCH_RXTX0_TX_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_buffer0_clkp
-- bench_sti_buffer0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_buffer0_clk
-- r/w:
BENCH_STI_BUFFER0_CLKP : process
begin
bench_sti_buffer0_clk <= '1';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD/2;
bench_sti_buffer0_clk <= '0';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_coder_conv0_clk
-- bench_sti_coder_conv0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_coder_conv0_clk
-- r/w:
BENCH_STI_CODER_CONV0_CLKP : process
begin
bench_sti_coder_conv0_clk <= '1';
wait for CCSDS_RXTX_BENCH_CODER_CONV0_CLK_PERIOD/2;
bench_sti_coder_conv0_clk <= '0';
wait for CCSDS_RXTX_BENCH_CODER_CONV0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_coder_diff0_clk
-- bench_sti_coder_diff0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_coder_diff0_clk
-- r/w:
BENCH_STI_CODER_DIFF0_CLKP : process
begin
bench_sti_coder_diff0_clk <= '1';
wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD/2;
bench_sti_coder_diff0_clk <= '0';
wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_crc0_clkp
-- bench_sti_crc0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_crc0_clk
-- r/w:
BENCH_STI_CRC0_CLKP : process
begin
bench_sti_crc0_clk <= '1';
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD/2;
bench_sti_crc0_clk <= '0';
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_filter0_clkp
-- bench_sti_filter0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_filter0_clk
-- r/w:
BENCH_STI_FILTER0_CLKP : process
begin
bench_sti_filter0_clk <= '1';
wait for CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD/2;
bench_sti_filter0_clk <= '0';
wait for CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_filter0_mapper_clkp
-- bench_sti_filter0_mapper_clk generation
--=============================================================================
-- read:
-- write: bench_sti_filter0_mapper_clk
-- r/w:
BENCH_STI_FILTER0_MAPPER_CLKP : process
begin
bench_sti_filter0_mapper_clk <= '1';
wait for CCSDS_RXTX_BENCH_FILTER0_MAPPER_CLK_PERIOD/2;
bench_sti_filter0_mapper_clk <= '0';
wait for CCSDS_RXTX_BENCH_FILTER0_MAPPER_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_framer0_clkp
-- bench_sti_framer0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_framer0_clk
-- r/w:
BENCH_STI_FRAMER0_CLKP : process
begin
bench_sti_framer0_clk <= '1';
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD/2;
bench_sti_framer0_clk <= '0';
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_lfsr0_clkp
-- bench_sti_lfsr0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_lfsr0_clk
-- r/w:
BENCH_STI_LFSR0_CLKP : process
begin
bench_sti_lfsr0_clk <= '1';
wait for CCSDS_RXTX_BENCH_LFSR0_CLK_PERIOD/2;
bench_sti_lfsr0_clk <= '0';
wait for CCSDS_RXTX_BENCH_LFSR0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_mapper_bits_symbols0_clkp
-- bench_sti_mapper_bits_symbols0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_mapper_bits_symbols0_clk
-- r/w:
BENCH_STI_MAPPER_BITS_SYMBOLS0_CLKP : process
begin
bench_sti_mapper_bits_symbols0_clk <= '1';
wait for CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_CLK_PERIOD/2;
bench_sti_mapper_bits_symbols0_clk <= '0';
wait for CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_mapper_symbols_samples0_clkp
-- bench_sti_mapper_symbols_samples0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_mapper_symbols_samples0_clk
-- r/w:
BENCH_STI_MAPPER_SYMBOLS_SAMPLES0_CLKP : process
begin
bench_sti_mapper_symbols_samples0_clk <= '1';
wait for CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_CLK_PERIOD/2;
bench_sti_mapper_symbols_samples0_clk <= '0';
wait for CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_serdes0_clkp
-- bench_sti_serdes0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_serdes0_clk
-- r/w:
BENCH_STI_SERDES0_CLKP : process
begin
bench_sti_serdes0_clk <= '1';
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
bench_sti_serdes0_clk <= '0';
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_srrc0_clkp
-- bench_sti_srrc0_clk generation
--=============================================================================
-- read:
-- write: bench_sti_srrc0_clk
-- r/w:
BENCH_STI_SRRC0_CLKP : process
begin
bench_sti_srrc0_clk <= '1';
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD/2;
bench_sti_srrc0_clk <= '0';
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD/2;
end process;
--=============================================================================
-- Begin of bench_sti_rxtx0_tx_datap
-- bench_sti_rxtx0_tx_data generation / dephased from 1/2 clk with bench_sti_rxtx0_tx_clk
--=============================================================================
-- read:
-- write: bench_sti_rxtx0_tx_data_ser0
-- r/w:
BENCH_STI_RXTX0_TX_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(1 downto 0);
begin
if (bench_ena_rxtx0_random_data = '1') then
sim_generate_random_std_logic_vector(2,seed1,seed2,random);
bench_sti_rxtx0_tx_data_ser <= random(0);
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_TX_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_buffer0_datap
-- bench_sti_buffer0_data generation
--=============================================================================
-- read: bench_ena_buffer0_random_data
-- write: bench_sti_buffer0_data
-- r/w:
BENCH_STI_BUFFER0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE-1 downto 0);
begin
if (bench_ena_buffer0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE,seed1,seed2,random);
bench_sti_buffer0_data <= random;
end if;
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_coder_conv0_datap
-- bench_sti_coder_conv0_random_data generation
--=============================================================================
-- read: bench_ena_coder_conv0_random_data
-- write: bench_sti_coder_conv0_dat
-- r/w:
BENCH_STI_CODER_CONV0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_CODER_CONV0_DATA_BUS_SIZE-1 downto 0);
begin
-- if (bench_ena_coder_conv0_random_data = '1') then
-- sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_CODER_CONV0_DATA_BUS_SIZE,seed1,seed2,random);
-- bench_sti_coder_conv0_dat <= random;
-- end if;
-- wait for CCSDS_RXTX_BENCH_CODER_CONV0_CLK_PERIOD;
bench_sti_coder_conv0_dat <= CCSDS_RXTX_BENCH_CODER_CONV0_INPUT;
wait;
end process;
--=============================================================================
-- Begin of bench_sti_coder_diff0_datap
-- bench_sti_coder_diff0_random_data generation
--=============================================================================
-- read: bench_ena_coder_diff0_random_data
-- write: bench_sti_coder_diff0_dat
-- r/w:
BENCH_STI_CODER_DIFF0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE-1 downto 0);
begin
if (bench_ena_coder_diff0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_CODER_DIFF0_DATA_BUS_SIZE,seed1,seed2,random);
bench_sti_coder_diff0_dat <= random;
end if;
wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_crc0_datap
-- bench_sti_crc0_random_data generation
--=============================================================================
-- read: bench_ena_crc0_random_data
-- write: bench_sti_crc0_random_data
-- r/w:
BENCH_STI_CRC0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8-1 downto 0);
begin
if (bench_ena_crc0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8,seed1,seed2,random);
bench_sti_crc0_random_data <= random;
end if;
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_filter0_datap
-- bench_sti_filter0_mapper_data generation
--=============================================================================
-- read: bench_ena_filter0_random_data
-- write: bench_sti_filter0_mapper_data
-- r/w:
BENCH_STI_FILTER0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_BUS_SIZE-1 downto 0);
begin
if (bench_ena_filter0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_BUS_SIZE,seed1,seed2,random);
bench_sti_filter0_mapper_data <= random;
end if;
wait for CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_framer0_datap
-- bench_sti_framer0_data generation
--=============================================================================
-- read: bench_ena_framer0_random_data
-- write: bench_sti_framer0_data
-- r/w:
BENCH_STI_FRAMER0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE-1 downto 0);
begin
if (bench_ena_framer0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE,seed1,seed2,random);
bench_sti_framer0_data <= random;
end if;
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_mapper_bits_symbols0_datap
-- bench_sti_mapper_bits_symbols0_data generation
--=============================================================================
-- read: bench_ena_mapper_bits_symbols0_random_data
-- write: bench_sti_mapper_bits_symbols0_data
-- r/w:
BENCH_STI_MAPPER_BITS_SYMBOLS0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_BUS_SIZE-1 downto 0);
begin
if (bench_ena_mapper_bits_symbols0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_BUS_SIZE,seed1,seed2,random);
bench_sti_mapper_bits_symbols0_data <= random;
end if;
wait for CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_mapper_symbols_samples0_datap
-- bench_sti_mapper_symbols_samples0_data generation
--=============================================================================
-- read: bench_ena_mapper_symbols_samples0_random_data
-- write: bench_sti_mapper_symbols_samples0_data
-- r/w:
BENCH_STI_MAPPER_SYMBOLS_SAMPLES0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_BITS_PER_SYMBOL-1 downto 0);
begin
if (bench_ena_mapper_symbols_samples0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_BITS_PER_SYMBOL,seed1,seed2,random);
bench_sti_mapper_symbols_samples0_sym <= random;
end if;
wait for CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_serdes0_datap
-- bench_sti_serdes0_data generation
--=============================================================================
-- read: bench_ena_serdes0_random_data
-- write: bench_sti_serdes0_data_par, bench_sti_serdes0_data_ser
-- r/w:
BENCH_STI_SERDES0_DATAP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random : std_logic_vector(CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 downto 0);
begin
if (bench_ena_serdes0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_SERDES0_DEPTH,seed1,seed2,random);
bench_sti_serdes0_data_par <= random;
bench_sti_serdes0_data_ser <= random(0);
end if;
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_rxtx0_rx_samplesp
-- bench_sti_rxtx0_rx_samples generation
--=============================================================================
-- read: bench_ena_rxtx0_random_data
-- write: bench_sti_rxtx0_rx_samples_i, bench_sti_rxtx0_rx_samples_q
-- r/w:
BENCH_STI_RXTX0_RX_SAMPLESP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random1 : std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
variable random2 : std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH-1 downto 0);
begin
if (bench_ena_rxtx0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH,seed1,seed2,random1);
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_RX_PHYS_SIG_QUANT_DEPTH,seed2,seed1,random2);
bench_sti_rxtx0_rx_samples_i <= random1;
bench_sti_rxtx0_rx_samples_q <= random2;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_RX_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bench_sti_rxtx0_wb_datap
-- bench_sti_rxtx0_wb_random_dat generation
--=============================================================================
-- read: bench_ena_rxtx0_random_data
-- write: bench_sti_rxtx0_wb_random_dat0
-- r/w:
BENCH_STI_RXTX0_WB_DATP : process
variable seed1 : positive := CCSDS_RXTX_BENCH_SEED;
variable seed2 : positive := CCSDS_RXTX_BENCH_SEED*2;
variable random1 : std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE-1 downto 0);
begin
if (bench_ena_rxtx0_random_data = '1') then
sim_generate_random_std_logic_vector(CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE,seed1,seed2,random1);
bench_sti_rxtx0_wb_random_dat <= random1;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
end process;
--=============================================================================
-- Begin of bufferrwp
-- generation of buffer subsystem read-write unit-tests
--=============================================================================
-- read: bench_res_buffer0_buffer_empty, bench_res_buffer0_buffer_full, bench_res_buffer0_data, bench_res_buffer0_data_valid
-- write: bench_sti_buffer0_data_valid, bench_sti_buffer0_next_data, bench_ena_buffer0_random_data
-- r/w:
BUFFERRWP : process
type buffer_array is array (CCSDS_RXTX_BENCH_BUFFER0_SIZE downto 0) of std_logic_vector(CCSDS_RXTX_BENCH_BUFFER0_DATA_BUS_SIZE-1 downto 0);
variable buffer_expected_stored_data: buffer_array := (others => (others => '0'));
variable buffer_content_ok: std_logic := '1';
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
-- check buffer is empty
if (bench_res_buffer0_buffer_empty = '1') then
report "BUFFERRWP: OK - Default state - Buffer is empty" severity note;
else
report "BUFFERRWP: KO - Default state - Buffer is not empty" severity warning;
end if;
-- check buffer is not full
if (bench_res_buffer0_buffer_full = '0')then
report "BUFFERRWP: OK - Default state - Buffer is not full" severity note;
else
report "BUFFERRWP: KO - Default state - Buffer is full" severity warning;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_BUFFER_WAIT_DURATION);
-- initial state tests:
-- check buffer is empty
if (bench_res_buffer0_buffer_empty = '1') then
report "BUFFERRWP: OK - Initial state - Buffer is empty" severity note;
else
report "BUFFERRWP: KO - Initial state - Buffer is not empty" severity warning;
end if;
-- check buffer is not full
if (bench_res_buffer0_buffer_full = '0')then
report "BUFFERRWP: OK - Initial state - Buffer is not full" severity note;
else
report "BUFFERRWP: KO - Initial state - Buffer is full" severity warning;
end if;
-- behaviour tests:
report "BUFFERRWP: START BUFFER READ-WRITE TESTS" severity note;
-- ask for data
bench_sti_buffer0_next_data <= '1';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
if (bench_res_buffer0_data_valid = '0') then
report "BUFFERRWP: OK - No data came out with an empty buffer" severity note;
else
report "BUFFERRWP: KO - Data came out - buffer is empty / incoherent" severity warning;
end if;
bench_sti_buffer0_next_data <= '0';
bench_ena_buffer0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
-- store data
bench_sti_buffer0_data_valid <= '1';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD/2;
buffer_expected_stored_data(0) := bench_sti_buffer0_data;
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD/2;
bench_sti_buffer0_data_valid <= '0';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
if (bench_res_buffer0_buffer_empty = '0') then
report "BUFFERRWP: OK - Buffer is not empty" severity note;
else
report "BUFFERRWP: KO - Buffer should not be empty" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
-- get data
bench_sti_buffer0_next_data <= '1';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
bench_sti_buffer0_next_data <= '0';
if (bench_res_buffer0_data_valid = '1') then
report "BUFFERRWP: OK - Data valid signal received" severity note;
else
report "BUFFERRWP: KO - Data valid signal not received" severity warning;
end if;
if (bench_res_buffer0_data = buffer_expected_stored_data(0)) then
report "BUFFERRWP: OK - Received value is equal to previously stored value" severity note;
else
report "BUFFERRWP: KO - Received value is different from previously stored value" severity warning;
report "Received value:" severity note;
for i in 0 to bench_res_buffer0_data'length-1 loop
report std_logic'image(bench_res_buffer0_data(i));
end loop;
report "Expected value:" severity note;
for i in 0 to buffer_expected_stored_data(0)'length-1 loop
report std_logic'image(buffer_expected_stored_data(0)(i));
end loop;
end if;
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
if (bench_res_buffer0_buffer_empty = '1') then
report "BUFFERRWP: OK - Buffer is empty after reading value" severity note;
else
report "BUFFERRWP: KO - Buffer is not empty" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
-- store lot of data / make the buffer full
bench_sti_buffer0_data_valid <= '1';
for i in 0 to CCSDS_RXTX_BENCH_BUFFER0_SIZE loop
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD/2;
buffer_expected_stored_data(i) := bench_sti_buffer0_data;
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD/2;
if (bench_res_buffer0_buffer_full = '1') then
if (i < CCSDS_RXTX_BENCH_BUFFER0_SIZE) then
report "BUFFERRWP: KO - Buffer is full too early - loop: " & integer'image(i) & " value of the buffer array" severity warning;
else
report "BUFFERRWP: OK - Buffer is full after all write operations" severity note;
end if;
else
if (i = CCSDS_RXTX_BENCH_BUFFER0_SIZE) then
report "BUFFERRWP: KO - Buffer is not full after all write operations" severity note;
end if;
end if;
end loop;
bench_sti_buffer0_data_valid <= '0';
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
bench_ena_buffer0_random_data <= '0';
-- read all data / make the buffer empty
bench_sti_buffer0_next_data <= '1';
for i in 0 to CCSDS_RXTX_BENCH_BUFFER0_SIZE loop
wait for CCSDS_RXTX_BENCH_BUFFER0_CLK_PERIOD;
if (buffer_expected_stored_data(i) /= bench_res_buffer0_data) then
if (i < CCSDS_RXTX_BENCH_BUFFER0_SIZE) then
report "BUFFERRWP: KO - Received value is different from previously stored value - loop: " & integer'image(i) severity warning;
buffer_content_ok := '0';
end if;
end if;
if (i = CCSDS_RXTX_BENCH_BUFFER0_SIZE) and (buffer_content_ok = '1') then
report "BUFFERRWP: OK - Received values are all equal to previously stored values" severity note;
end if;
if (bench_res_buffer0_data_valid = '0') then
if (i < CCSDS_RXTX_BENCH_BUFFER0_SIZE) then
report "BUFFERRWP: KO - Data valid signal not received - loop: " & integer'image(i) severity warning;
end if;
end if;
if (bench_res_buffer0_buffer_empty = '1') then
if (i < CCSDS_RXTX_BENCH_BUFFER0_SIZE) then
report "BUFFERRWP: KO - Data empty signal received too early - loop: " & integer'image(i) severity warning;
else
report "BUFFERRWP: OK - Buffer is empty after all read operations" severity note;
end if;
else
if (i = CCSDS_RXTX_BENCH_BUFFER0_SIZE) then
report "BUFFERRWP: KO - Buffer is not empty after all read operations" severity warning;
end if;
end if;
end loop;
bench_sti_buffer0_next_data <= '0';
-- final state tests:
-- check buffer is empty
if (bench_res_buffer0_buffer_empty = '1') then
report "BUFFERRWP: OK - Final state - Buffer is empty" severity note;
else
report "BUFFERRWP: KO - Final state - Buffer is not empty" severity warning;
end if;
-- check buffer is not full
if (bench_res_buffer0_buffer_full = '0')then
report "BUFFERRWP: OK - Final state - Buffer is not full" severity note;
else
report "BUFFERRWP: KO - Final state - Buffer is full" severity warning;
end if;
report "BUFFERRWP: END BUFFER READ-WRITE TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of coderconvp
-- generation of coder convolutional subsystem unit-tests
--=============================================================================
-- read: bench_res_coder_conv0_dat, bench_res_coder_conv0_dat_val, bench_res_coder_conv0_bus
-- write: bench_ena_coder_conv0_random_data, bench_sti_coder_conv0_dat_val
-- r/w:
CODERCONVP : process
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_coder_conv0_dat_val = '1') then
report "CODERCONVP: KO - Default state - Convolutional coder output data is valid" severity warning;
else
report "CODERCONVP: OK - Default state - Convolutional coder output data is not valid" severity note;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_CODER_CONV_WAIT_DURATION);
-- initial state tests:
if (bench_res_coder_conv0_dat_val = '1') then
report "CODERCONVP: KO - Initial state - Convolutional coder output data is valid" severity warning;
else
report "CODERCONVP: OK - Initial state - Convolutional coder output data is not valid" severity note;
end if;
-- behaviour tests:
report "CODERCONVP: START CONVOLUTIONAL CODER TESTS" severity note;
bench_ena_coder_conv0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_CODER_CONV0_CLK_PERIOD;
for coder_current_check in 0 to CCSDS_RXTX_BENCH_CODER_CONV0_WORDS_NUMBER-1 loop
for coder_current_bit in 0 to CCSDS_RXTX_BENCH_CODER_CONV0_DATA_BUS_SIZE loop
if (coder_current_bit = 0) then
bench_sti_coder_conv0_dat_val <= '1';
else
bench_sti_coder_conv0_dat_val <= '0';
end if;
wait for CCSDS_RXTX_BENCH_CODER_CONV0_CLK_PERIOD;
end loop;
if (bench_res_coder_conv0_dat_val = '0') then
report "CODERCONVP: KO - Convolutional coder output data is not valid" severity warning;
else
if (bench_res_coder_conv0_dat = CCSDS_RXTX_BENCH_CODER_CONV0_OUTPUT) then
report "CODERCONVP: OK - Convolutional coder output data match" severity note;
else
report "CODERCONVP: KO - Convolutional coder output data doesn't match" severity warning;
end if;
end if;
end loop;
bench_ena_coder_conv0_random_data <= '0';
wait for CCSDS_RXTX_BENCH_CODER_CONV0_CLK_PERIOD;
-- final state tests:
if (bench_res_coder_conv0_dat_val = '1') then
report "CODERCONVP: KO - Final state - Convolutional coder output data is valid" severity warning;
else
report "CODERCONVP: OK - Final state - Convolutional coder output data is not valid" severity note;
end if;
report "CODERCONVP: END CONVOLUTIONAL CODER TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of coderdiffp
-- generation of coder differential subsystem unit-tests
--=============================================================================
-- read: bench_res_coder_diff0_dat, bench_res_coder_diff0_dat_val
-- write: bench_ena_coder_diff0_random_data, bench_sti_coder_diff0_dat_val
-- r/w:
CODERDIFFP : process
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_coder_diff0_dat_val = '1') then
report "CODERDIFFP: KO - Default state - Differential coder output data is valid" severity warning;
else
report "CODERDIFFP: OK - Default state - Differential coder output data is not valid" severity note;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_CODER_DIFF_WAIT_DURATION);
-- initial state tests:
if (bench_res_coder_diff0_dat_val = '1') then
report "CODERDIFFP: KO - Initial state - Differential coder output data is valid" severity warning;
else
report "CODERDIFFP: OK - Initial state - Differential coder output data is not valid" severity note;
end if;
-- behaviour tests:
report "CODERDIFFP: START DIFFERENTIAL CODER TESTS" severity note;
bench_ena_coder_diff0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD;
bench_sti_coder_diff0_dat_val <= '1';
wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD*CCSDS_RXTX_BENCH_CODER_DIFF0_WORDS_NUMBER;
bench_sti_coder_diff0_dat_val <= '0';
bench_ena_coder_diff0_random_data <= '0';
wait for CCSDS_RXTX_BENCH_CODER_DIFF0_CLK_PERIOD;
-- final state tests:
if (bench_res_coder_diff0_dat_val = '1') then
report "CODERDIFFP: KO - Final state - Differential coder output data is valid" severity warning;
else
report "CODERDIFFP: OK - Final state - Differential coder output data is not valid" severity note;
end if;
report "CODERDIFFP: END DIFFERENTIAL CODER TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of crcp
-- generation of crc subsystem unit-tests
--=============================================================================
-- read: bench_res_crc0_data, bench_res_crc0_data_valid
-- write: bench_sti_crc0_nxt, bench_sti_crc0_data, bench_ena_crc0_random_data
-- r/w:
CRCP : process
variable crc_random_data_sent: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8-1 downto 0) := (others => '0');
variable crc_random_data_crc: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_LENGTH*8-1 downto 0) := (others => '1');
variable crc_random_data_crc_check: std_logic_vector(CCSDS_RXTX_BENCH_CRC0_LENGTH*8-1 downto 0) := (others => '0');
variable crc_check_ok: std_logic := '1';
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_crc0_data_valid = '1') then
report "CRCP: KO - Default state - CRC output data is valid" severity warning;
else
report "CRCP: OK - Default state - CRC output data is not valid" severity note;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_CRC_WAIT_DURATION);
-- initial state tests:
if (bench_res_crc0_data_valid = '1') then
report "CRCP: KO - Initial state - CRC output data is valid" severity warning;
else
report "CRCP: OK - Initial state - CRC output data is not valid" severity note;
end if;
-- behaviour tests:
report "CRCP: START CRC COMPUTATION TESTS" severity note;
-- present crc test data
bench_sti_crc0_data <= CCSDS_RXTX_BENCH_CRC0_DATA;
-- no specific padding done
bench_sti_crc0_padding_data_valid <= '0';
-- send next crc signal
bench_sti_crc0_nxt <= '1';
-- wait for one clk
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD;
-- stop next signal
bench_sti_crc0_nxt <= '0';
-- remove crc test data
bench_sti_crc0_data <= (others => '0');
if (bench_res_crc0_busy = '0') then
report "CRCP: KO - CRC is not busy" severity warning;
end if;
-- wait for result
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD*(CCSDS_RXTX_BENCH_CRC0_DATA'length+CCSDS_RXTX_BENCH_CRC0_LENGTH*8+1);
if (bench_res_crc0_crc = CCSDS_RXTX_BENCH_CRC0_RESULT) and (bench_res_crc0_data_valid = '1') and (bench_res_crc0_data = CCSDS_RXTX_BENCH_CRC0_DATA) then
report "CRCP: OK - Output CRC is conform to expectations" severity note;
else
report "CRCP: KO - Output CRC is different from expectations" severity warning;
report "Received value:" severity note;
for i in 0 to bench_res_crc0_data'length-1 loop
report std_logic'image(bench_res_crc0_data(i));
end loop;
report "Expected value:" severity note;
for i in 0 to CCSDS_RXTX_BENCH_CRC0_RESULT'length-1 loop
report std_logic'image(CCSDS_RXTX_BENCH_CRC0_RESULT(i));
end loop;
end if;
bench_ena_crc0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD;
for crc_current_check in 0 to CCSDS_RXTX_BENCH_CRC0_RANDOM_CHECK_NUMBER-1 loop
-- present crc random data + store associated crc
-- send next crc signal
bench_sti_crc0_random_nxt <= '1';
-- no specific padding done
bench_sti_crc0_random_padding_data_valid <= '0';
-- wait for one clk and store random data sent
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD/2;
crc_random_data_sent := bench_sti_crc0_random_data;
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD/2;
-- stop next signal
bench_ena_crc0_random_data <= '0';
bench_sti_crc0_random_nxt <= '0';
if (bench_res_crc0_random_busy = '0') then
report "CRCP: KO - random data CRC is not busy" severity warning;
end if;
-- wait for result
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD*(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8+CCSDS_RXTX_BENCH_CRC0_LENGTH*8+1);
if (bench_res_crc0_random_data_valid = '1') then
-- store crc
crc_random_data_crc := bench_res_crc0_random_crc;
else
report "CRCP: KO - random data output CRC is not valid" severity warning;
end if;
-- present crc random data
bench_sti_crc0_check_data <= crc_random_data_sent;
-- present crc as padding value
bench_sti_crc0_check_padding_data <= crc_random_data_crc;
bench_sti_crc0_check_padding_data_valid <= '1';
-- send next crc signal
bench_sti_crc0_check_nxt <= '1';
-- wait for one clk
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD;
-- stop next signal
bench_sti_crc0_check_nxt <= '0';
-- stop padding signal
bench_sti_crc0_check_padding_data_valid <= '0';
if (bench_res_crc0_check_busy = '0') then
report "CRCP: KO - Random data checker CRC is not busy" severity warning;
end if;
-- wait for result
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD*(CCSDS_RXTX_BENCH_CRC0_RANDOM_DATA_BUS_SIZE*8+CCSDS_RXTX_BENCH_CRC0_LENGTH*8+1);
if (bench_res_crc0_check_data_valid = '1') then
-- check output crc resulting is null
if (bench_res_crc0_check_crc = crc_random_data_crc_check) and (bench_res_crc0_check_data = crc_random_data_sent) then
if (crc_current_check = CCSDS_RXTX_BENCH_CRC0_RANDOM_CHECK_NUMBER-1) and (crc_check_ok = '1') then
report "CRCP: OK - Random data checker output CRCs are all null" severity note;
end if;
else
crc_check_ok := '0';
report "CRCP: KO - Random data checker output CRC is not null - loop " & integer'image(crc_current_check) severity warning;
report "Received value:" severity warning;
for i in 0 to bench_res_crc0_check_data'length-1 loop
report std_logic'image(bench_res_crc0_check_data(i)) severity warning;
end loop;
end if;
else
report "CRCP: KO - Output CRC checker is not valid" severity warning;
end if;
bench_ena_crc0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD;
end loop;
bench_ena_crc0_random_data <= '0';
wait for CCSDS_RXTX_BENCH_CRC0_CLK_PERIOD;
-- final state tests:
if (bench_res_crc0_data_valid = '1') then
report "CRCP: KO - Final state - CRC output data is valid" severity warning;
else
report "CRCP: OK - Final state - CRC output data is not valid" severity note;
end if;
report "CRCP: END CRC COMPUTATION TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of filterp
-- generation of filter subsystem unit-tests
--=============================================================================
-- read:
-- write:
-- r/w:
FILTERP : process
variable samples_csv_output: line;
variable samples_hex_output: line;
variable samples_hex_i_output: line;
variable samples_hex_q_output: line;
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_filter0_sam_val = '0') then
report "FILTERP: OK - Default state - Output samples are not valid" severity note;
else
report "FILTERP: KO - Default state - Output samples are valid" severity warning;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_FILTER_WAIT_DURATION);
-- initial state tests:
-- default state tests:
if (bench_res_filter0_sam_val = '0') then
report "FILTERP: OK - Initial state - Output samples are not valid" severity note;
else
report "FILTERP: KO - Initial state - Output samples are valid" severity warning;
end if;
-- behaviour tests:
report "FILTERP: START FILTER TESTS" severity note;
if (CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_ENABLE = true) then
write(samples_csv_output, string'("I samples;Q samples - quantized on " & integer'image(CCSDS_RXTX_BENCH_FILTER0_SIG_QUANT_DEPTH) & " bits / Big-Endian (MSB first) ASCII hexa coded"));
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_CSV_IQ_FILE, samples_csv_output);
end if;
bench_ena_filter0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_CLK_PERIOD;
bench_sti_filter0_mapper_dat_val <= '1';
wait for CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL*CCSDS_RXTX_BENCH_FILTER0_MAPPER_DATA_CLK_PERIOD*CCSDS_RXTX_BENCH_FILTER0_BITS_PER_SYMBOL/CCSDS_RXTX_BENCH_FILTER0_MODULATION_TYPE;
if (CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_ENABLE = true) then
for i in 0 to 200 loop
wait for CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD;
if (bench_res_filter0_sam_val = '1') then
write(samples_csv_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_i) & ";");
write(samples_csv_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_q));
write(samples_hex_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_i));
write(samples_hex_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_q));
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_CSV_IQ_FILE, samples_csv_output);
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_IQ_FILE, samples_hex_output);
write(samples_hex_i_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_i));
write(samples_hex_q_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_q));
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_I_FILE, samples_hex_i_output);
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_Q_FILE, samples_hex_q_output);
else
report "FILTERP: KO - Output samples are not valid" severity warning;
end if;
end loop;
else
wait for 200*CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD;
end if;
if (bench_res_filter0_sam_val = '1') then
report "FILTERP: OK - Output samples are valid" severity note;
else
report "FILTERP: KO - Output samples are not valid" severity warning;
end if;
if (CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_ENABLE = true) then
for i in 0 to CCSDS_RXTX_BENCH_FILTER0_SYMBOL_WORDS_NUMBER-1 loop
for j in 0 to CCSDS_RXTX_BENCH_FILTER0_MAPPER_CLK_PERIOD/CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD-1 loop
wait for CCSDS_RXTX_BENCH_FILTER0_CLK_PERIOD;
if (bench_res_filter0_sam_val = '1') then
write(samples_csv_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_i) & ";");
write(samples_csv_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_q));
write(samples_hex_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_i));
write(samples_hex_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_q));
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_CSV_IQ_FILE, samples_csv_output);
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_IQ_FILE, samples_hex_output);
write(samples_hex_i_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_i));
write(samples_hex_q_output, convert_std_logic_vector_to_hexa_ascii(bench_res_filter0_sam_q));
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_I_FILE, samples_hex_i_output);
writeline(CCSDS_RXTX_BENCH_FILTER0_OUTPUT_HEX_Q_FILE, samples_hex_q_output);
else
report "FILTERP: KO - Output samples are not valid" severity warning;
end if;
end loop;
end loop;
else
wait for CCSDS_RXTX_BENCH_FILTER0_MAPPER_CLK_PERIOD*CCSDS_RXTX_BENCH_FILTER0_SYMBOL_WORDS_NUMBER;
end if;
bench_sti_filter0_mapper_dat_val <= '0';
bench_ena_filter0_random_data <= '0';
wait for CCSDS_RXTX_BENCH_FILTER0_MAPPER_CLK_PERIOD*12;
-- final state tests:
if (bench_res_filter0_sam_val = '0') then
report "FILTERP: OK - Final state - Output samples are not valid" severity note;
else
report "FILTERP: KO - Final state - Output samples are valid" severity warning;
end if;
report "FILTERP: END FILTER TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of framerp
-- generation of framer subsystem unit-tests
--=============================================================================
-- read: bench_res_framer0_data0, bench_res_framer0_data_valid0
-- write: bench_ena_framer0_random_data
-- r/w:
FRAMERP : process
type data_array is array (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE-1 downto 0) of std_logic_vector(CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE-1 downto 0);
type frame_array is array (CCSDS_RXTX_BENCH_FRAMER0_FRAME_NUMBER-1 downto 0) of data_array;
variable framer_expected_data: frame_array := (others => (others => (others => '0')));
variable frame_content_ok: std_logic := '1';
variable nb_data: integer;
variable FRAME_OUTPUT_CYCLES_REQUIRED: integer;
variable FRAME_PROCESSING_CYCLES_REQUIRED: integer := (CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8+1;
constant FRAME_ACQUISITION_CYCLES: integer := (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8-CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)*CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE + 1;
constant FRAME_REPETITION_CYCLES: integer := CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8*CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE;
constant FRAME_ACQUISITION_CYCLES_IDLE: integer := FRAME_REPETITION_CYCLES - FRAME_ACQUISITION_CYCLES;
begin
if (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8 = CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE) and (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO = 1) then
FRAME_OUTPUT_CYCLES_REQUIRED := (CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8+6;
else
FRAME_OUTPUT_CYCLES_REQUIRED := (CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8+5;
end if;
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_FRAMER_WAIT_DURATION);
report "FRAMERP: START FRAMER TESTS" severity note;
-- initial state tests:
bench_ena_framer0_random_data <= '1';
-- check output data is valid and idle only data found
if ((CCSDS_RXTX_BENCH_START_FRAMER_WAIT_DURATION/CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD) < FRAME_OUTPUT_CYCLES_REQUIRED) then
wait for (FRAME_OUTPUT_CYCLES_REQUIRED+1 - ((CCSDS_RXTX_BENCH_START_FRAMER_WAIT_DURATION/CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD) mod FRAME_OUTPUT_CYCLES_REQUIRED))*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
else
wait for (FRAME_REPETITION_CYCLES+1 - (((CCSDS_RXTX_BENCH_START_FRAMER_WAIT_DURATION/CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD) - FRAME_OUTPUT_CYCLES_REQUIRED) mod (FRAME_REPETITION_CYCLES)))*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
end if;
if bench_res_framer0_data_valid = '1' then
if (bench_res_framer0_data((CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8+10 downto (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8) = "11111111110") then
report "FRAMERP: OK - Initial state - Output frame is valid and Only Idle Data flag found" severity note;
else
report "FRAMERP: KO - Initial state - Output frame is valid without sent data - Only Idle Flag not found" severity warning;
end if;
else
report "FRAMERP: KO - Initial state - Output frame is not valid without sent data" severity warning;
end if;
if (bench_res_framer0_dat_nxt = '0') then
report "FRAMERP: KO - Initial state - Next data not requested" severity warning;
else
report "FRAMERP: OK - Initial state - Next data requested" severity note;
end if;
-- behaviour tests:
-- align the end of data to the beginning of a new frame processing cycle
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD*(FRAME_REPETITION_CYCLES - (FRAME_OUTPUT_CYCLES_REQUIRED mod FRAME_REPETITION_CYCLES) + FRAME_ACQUISITION_CYCLES_IDLE);
-- send data for 1 frame
for i in 0 to (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)-1 loop
bench_sti_framer0_data_valid <= '1';
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD/2;
framer_expected_data(0)(i) := bench_sti_framer0_data;
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD/2;
if (i /= (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)-1) then
if (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO /= 1) then
bench_sti_framer0_data_valid <= '0';
wait for (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO-1)*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
end if;
end if;
end loop;
bench_sti_framer0_data_valid <= '0';
bench_ena_framer0_random_data <= '0';
-- wait for footer to be processed
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD*(FRAME_PROCESSING_CYCLES_REQUIRED+4);
if bench_res_framer0_data_valid = '0' then
report "FRAMERP: KO - Output frame is not ready in time" severity warning;
else
report "FRAMERP: OK - Output frame is ready in time" severity note;
-- check frame content is coherent with sent data
for i in 0 to (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)-1 loop
if (bench_res_framer0_data((CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8-CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE*i-1 downto (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8-CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE*(i+1)) /= framer_expected_data(0)(i)) then
report "FRAMERP: KO - Output frame content is not equal to sent data - loop: " & integer'image(i) severity warning;
frame_content_ok := '0';
else
if (i = (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)-1) and (frame_content_ok = '1') then
report "FRAMERP: OK - Output frame is equal to sent data" severity note;
end if;
end if;
end loop;
end if;
-- send data every CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO clk during CCSDS_RXTX_BENCH_FRAMER0_FRAME_NUMBER*frame_processing time, store sent data for first frame and check output frame content
bench_ena_framer0_random_data <= '1';
-- align the end of data to the beginning of a new frame processing cycle
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD*(FRAME_REPETITION_CYCLES - (FRAME_OUTPUT_CYCLES_REQUIRED mod FRAME_REPETITION_CYCLES) + FRAME_ACQUISITION_CYCLES_IDLE);
frame_content_ok := '1';
for f in 0 to (CCSDS_RXTX_BENCH_FRAMER0_FRAME_NUMBER-1) loop
for i in 0 to (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)-1 loop
bench_sti_framer0_data_valid <= '1';
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD/2;
framer_expected_data(f)(i) := bench_sti_framer0_data;
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD/2;
if (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO /= 1) then
bench_sti_framer0_data_valid <= '0';
wait for (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO-1)*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
end if;
end loop;
-- waiting for footer to be processed
for data_packet in 0 to ((FRAME_PROCESSING_CYCLES_REQUIRED-1)/CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO)-1 loop
bench_sti_framer0_data_valid <= '1';
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
if (data_packet /= ((FRAME_PROCESSING_CYCLES_REQUIRED-1)/CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO-1)) then
if (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO /= 1) then
bench_sti_framer0_data_valid <= '0';
wait for (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO-1)*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
end if;
end if;
end loop;
if (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO /= 1) then
bench_sti_framer0_data_valid <= '0';
end if;
wait for 5*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
if bench_res_framer0_data_valid = '0' then
report "FRAMERP: KO - Output frame is not ready in time - frame loop: " & integer'image(f) severity warning;
else
-- check frame content is coherent with sent data
for i in 0 to (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)-1 loop
if (bench_res_framer0_data((CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8-CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE*i-1 downto (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8-CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE*(i+1)) /= framer_expected_data(f)(i)) then
report "FRAMERP: KO - Output frame content is not equal to sent data - frame loop: " & integer'image(f) & " - data loop: " & integer'image(i) severity warning;
frame_content_ok := '0';
else
if (i = (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)-1) and (f = (CCSDS_RXTX_BENCH_FRAMER0_FRAME_NUMBER-1)) and (frame_content_ok = '1') then
report "FRAMERP: OK - Received output frames are all equal to sent data" severity note;
end if;
end if;
end loop;
end if;
if (f /= (CCSDS_RXTX_BENCH_FRAMER0_FRAME_NUMBER-1)) then
-- fill current frame to start with new one
if ((((CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8) mod FRAME_REPETITION_CYCLES) /= 0) then
nb_data := (FRAME_REPETITION_CYCLES - (((CCSDS_RXTX_BENCH_FRAMER0_HEADER_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8) mod FRAME_REPETITION_CYCLES))/CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO;
for i in 0 to nb_data-1 loop
bench_sti_framer0_data_valid <= '1';
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
if (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO /= 1) then
bench_sti_framer0_data_valid <= '0';
wait for (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO-1)*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
end if;
end loop;
-- align the end of data to the beginning of a new frame processing cycle
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD*(2*FRAME_REPETITION_CYCLES - (FRAME_OUTPUT_CYCLES_REQUIRED mod FRAME_REPETITION_CYCLES) + FRAME_ACQUISITION_CYCLES_IDLE - nb_data*CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO);
else
-- align the end of data to the beginning of a new frame processing cycle
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD*(FRAME_REPETITION_CYCLES - (FRAME_OUTPUT_CYCLES_REQUIRED mod FRAME_REPETITION_CYCLES) + FRAME_ACQUISITION_CYCLES_IDLE);
end if;
end if;
end loop;
bench_sti_framer0_data_valid <= '0';
-- wait for last frame to be processed and presented
wait for CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD*(FRAME_REPETITION_CYCLES*(((FRAME_PROCESSING_CYCLES_REQUIRED+1)/FRAME_REPETITION_CYCLES)+4));
-- send data continuously to test full-speed / overflow behaviour
bench_sti_framer0_data_valid <= '1';
wait for (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO*CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO*CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH*8/CCSDS_RXTX_BENCH_FRAMER0_DATA_BUS_SIZE)*CCSDS_RXTX_BENCH_FRAMER0_CLK_PERIOD;
if (CCSDS_RXTX_BENCH_FRAMER0_PARALLELISM_MAX_RATIO /= 1) then
if (bench_res_framer0_dat_nxt = '0') then
report "FRAMERP: OK - Overflow stop next data request" severity note;
else
report "FRAMERP: KO - Overflow doesn't stop next data request" severity warning;
end if;
else
if (bench_res_framer0_dat_nxt = '1') then
report "FRAMERP: OK - Full speed doesn't stop next data request" severity note;
else
report "FRAMERP: KO - Full speed stop next data request" severity warning;
end if;
end if;
bench_sti_framer0_data_valid <= '0';
bench_ena_framer0_random_data <= '0';
-- final state tests:
if bench_res_framer0_data_valid = '1' then
if (bench_res_framer0_data((CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8+10 downto (CCSDS_RXTX_BENCH_FRAMER0_DATA_LENGTH+CCSDS_RXTX_BENCH_FRAMER0_FOOTER_LENGTH)*8) = "11111111110") then
report "FRAMERP: OK - Final state - Output frame is valid and Only Idle Data flag found" severity note;
else
report "FRAMERP: KO - Final state - Output frame is valid without sent data - Only Idle Flag not found" severity warning;
end if;
else
report "FRAMERP: KO - Final state - Output frame is not valid without sent data" severity warning;
end if;
if (bench_res_framer0_dat_nxt = '0') then
report "FRAMERP: KO - Final state - Next data not requested" severity warning;
else
report "FRAMERP: OK - Final state - Next data requested" severity note;
end if;
report "FRAMERP: END FRAMER TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of lfsrp
-- generation of lfsr subsystem unit-tests
--=============================================================================
-- read: bench_res_lfsr0_data, bench_res_lfsr0_data_valid
-- write:
-- r/w:
LFSRP : process
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_LFSR_WAIT_DURATION);
-- initial state tests:
-- behaviour tests:
report "LFSRP: START LFSR TESTS" severity note;
wait for (CCSDS_RXTX_BENCH_LFSR0_RESULT'length)*CCSDS_RXTX_BENCH_LFSR0_CLK_PERIOD;
if (bench_res_lfsr0_data_valid = '1') then
report "LFSRP: OK - LFSR output is valid" severity note;
if (bench_res_lfsr0_data = CCSDS_RXTX_BENCH_LFSR0_RESULT) then
report "LFSRP: OK - LFSR output is equal to expected output" severity note;
else
report "LFSRP: KO - LFSR output is different from expected output" severity warning;
end if;
else
report "LFSRP: KO - LFSR output is not valid" severity warning;
end if;
-- final state tests:
report "LFSRP: END LFSR TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of mapperbitssymbolsp
-- generation of mapper subsystem unit-tests
--=============================================================================
-- read:
-- write: bench_sti_mapper_bits_symbols0_dat_val, bench_sti_mapper_bits_symbols0_dat_val
-- r/w:
MAPPERBITSSYMBOLSP : process
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_mapper_bits_symbols0_sym_val = '1') then
report "MAPPERBITSSYMBOLSP: KO - Default state - Mapper output data is valid" severity warning;
else
report "MAPPERBITSSYMBOLSP: OK - Default state - Mapper output data is not valid" severity note;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_MAPPER_BITS_SYMBOLS_WAIT_DURATION);
-- initial state tests:
if (bench_res_mapper_bits_symbols0_sym_val = '1') then
report "MAPPERBITSSYMBOLSP: KO - Initial state - Mapper output data is valid" severity warning;
else
report "MAPPERBITSSYMBOLSP: OK - Initial state - Mapper output data is not valid" severity note;
end if;
-- behaviour tests:
report "MAPPERBITSSYMBOLSP: START BITS TO SYMBOLS MAPPER TESTS" severity note;
bench_ena_mapper_bits_symbols0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_CLK_PERIOD;
bench_sti_mapper_bits_symbols0_dat_val <= '1';
wait for CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_CLK_PERIOD*CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_BUS_SIZE/CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_BITS_PER_SYMBOL*CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_WORDS_NUMBER;
bench_sti_mapper_bits_symbols0_dat_val <= '0';
bench_ena_mapper_bits_symbols0_random_data <= '0';
wait for CCSDS_RXTX_BENCH_MAPPER_BITS_SYMBOLS0_DATA_CLK_PERIOD;
-- final state tests:
if (bench_res_mapper_bits_symbols0_sym_val = '1') then
report "MAPPERBITSSYMBOLSP: KO - Final state - Mapper output data is valid" severity warning;
else
report "MAPPERBITSSYMBOLSP: OK - Final state - Mapper output data is not valid" severity note;
end if;
report "MAPPERBITSSYMBOLSP: END BITS TO SYMBOLS MAPPER TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of mappersymbolssamplesp
-- generation of mapper subsystem unit-tests
--=============================================================================
-- read:
-- write: bench_sti_mapper_bits_symbols0_dat_val, bench_sti_mapper_bits_symbols0_dat_val
-- r/w:
MAPPERSYMBOLSSAMPLESP : process
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_mapper_symbols_samples0_sam_val = '1') then
report "MAPPERSYMBOLSSAMPLESP: KO - Default state - Mapper output data is valid" severity warning;
else
report "MAPPERSYMBOLSSAMPLESP: OK - Default state - Mapper output data is not valid" severity note;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_MAPPER_SYMBOLS_SAMPLES_WAIT_DURATION);
-- initial state tests:
if (bench_res_mapper_symbols_samples0_sam_val = '1') then
report "MAPPERSYMBOLSSAMPLESP: KO - Initial state - Mapper output data is valid" severity warning;
else
report "MAPPERSYMBOLSSAMPLESP: OK - Initial state - Mapper output data is not valid" severity note;
end if;
-- behaviour tests:
report "MAPPERSYMBOLSSAMPLESP: START SYMBOLS TO SAMPLES MAPPER TESTS" severity note;
bench_ena_mapper_symbols_samples0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_CLK_PERIOD;
bench_sti_mapper_symbols_samples0_sym_val <= '1';
wait for CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_CLK_PERIOD*CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_WORDS_NUMBER;
bench_sti_mapper_symbols_samples0_sym_val <= '0';
bench_ena_mapper_symbols_samples0_random_data <= '0';
wait for CCSDS_RXTX_BENCH_MAPPER_SYMBOLS_SAMPLES0_CLK_PERIOD;
-- final state tests:
if (bench_res_mapper_symbols_samples0_sam_val = '1') then
report "MAPPERSYMBOLSSAMPLESP: KO - Final state - Mapper output data is valid" severity warning;
else
report "MAPPERSYMBOLSSAMPLESP: OK - Final state - Mapper output data is not valid" severity note;
end if;
report "MAPPERSYMBOLSSAMPLESP: END SYMBOLS TO SAMPLES MAPPER TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of serdesp
-- generation of serdes subsystem unit-tests
--=============================================================================
-- read: bench_res_serdes0_data_par_valid, bench_res_serdes0_data_par, bench_res_serdes0_data_ser, bench_res_serdes0_data_ser_valid, bench_res_serdes0_busy
-- write: bench_sti_serdes0_data_par_valid, bench_sti_serdes0_data_ser_valid, bench_ena_serdes0_random_data
-- r/w:
SERDESP : process
variable serdes_expected_output: std_logic_vector(CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 downto 0) := (others => '0');
variable serdes_ok: std_logic := '1';
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
-- check serdes is not valid
if (bench_res_serdes0_data_par_valid = '0') then
report "SERDESP: OK - Default state - Serdes parallel output is not valid" severity note;
else
report "SERDESP: KO - Default state - Serdes parallel output is valid" severity warning;
end if;
if (bench_res_serdes0_data_ser_valid = '0') then
report "SERDESP: OK - Default state - Serdes serial output is not valid" severity note;
else
report "SERDESP: KO - Default state - Serdes serial output is valid" severity warning;
end if;
if (bench_res_serdes0_busy = '0') then
report "SERDESP: OK - Default state - Serdes is not busy" severity note;
else
report "SERDESP: KO - Default state - Serdes is busy" severity warning;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_SERDES_WAIT_DURATION);
-- initial state tests:
-- check serdes is not valid
if (bench_res_serdes0_data_par_valid = '0') then
report "SERDESP: OK - Initial state - Serdes parallel output is not valid" severity note;
else
report "SERDESP: KO - Initial state - Serdes parallel output is valid" severity warning;
end if;
if (bench_res_serdes0_data_ser_valid = '0') then
report "SERDESP: OK - Initial state - Serdes serial output is not valid" severity note;
else
report "SERDESP: KO - Initial state - Serdes serial output is valid" severity warning;
end if;
if (bench_res_serdes0_busy = '0') then
report "SERDESP: OK - Initial state - Serdes is not busy" severity note;
else
report "SERDESP: KO - Initial state - Serdes is busy" severity warning;
end if;
-- behaviour tests:
report "SERDESP: START SERDES TESTS" severity note;
bench_ena_serdes0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD;
-- test par2ser
-- signal valid parallel data input
bench_sti_serdes0_data_par_valid <= '1';
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
serdes_expected_output := bench_sti_serdes0_data_par;
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
bench_sti_serdes0_data_par_valid <= '0';
for bit_pointer in (CCSDS_RXTX_BENCH_SERDES0_DEPTH-1) downto 0 loop
if (bench_res_serdes0_busy = '0') then
report "SERDESP: KO - Serdes is not busy" severity warning;
else
if (bench_res_serdes0_data_ser_valid = '1') then
if (bench_res_serdes0_data_ser /= serdes_expected_output(bit_pointer)) then
serdes_ok := '0';
report "SERDESP: KO - Serdes serialized output data doesn't match expected output - cycle " & integer'image(bit_pointer) severity warning;
report "Expected value: " & std_logic'image(serdes_expected_output(bit_pointer)) severity warning;
report "Received value: " & std_logic'image(bench_res_serdes0_data_ser) severity warning;
else
if (serdes_ok = '1') and (bit_pointer = 0) then
report "SERDESP: OK - Serdes serialized output data match expected output" severity note;
end if;
end if;
else
report "SERDESP: KO - Serdes serialized output data is not valid" severity warning;
end if;
end if;
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD;
end loop;
-- test ser2par
-- signal valid serial data input
serdes_expected_output := (others => '0');
bench_sti_serdes0_data_ser_valid <= '1';
for bit_pointer in (CCSDS_RXTX_BENCH_SERDES0_DEPTH-1) downto 0 loop
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
serdes_expected_output(bit_pointer) := bench_sti_serdes0_data_ser;
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
end loop;
bench_sti_serdes0_data_ser_valid <= '0';
bench_ena_serdes0_random_data <= '0';
if (bench_res_serdes0_data_par_valid = '1') then
report "SERDESP: OK - Serdes parallelized output data is valid" severity note;
if (bench_res_serdes0_data_par = serdes_expected_output) then
report "SERDESP: OK - Serdes parallelized output data match expected output" severity note;
else
report "SERDESP: KO - Serdes parallelized output data doesn't match expected output" severity warning;
report "Expected value:" severity warning;
for bit_pointer in 0 to CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 loop
report std_logic'image(serdes_expected_output(bit_pointer)) severity warning;
end loop;
report "Received value:" severity warning;
for bit_pointer in 0 to CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 loop
report std_logic'image(bench_res_serdes0_data_par(bit_pointer)) severity warning;
end loop;
end if;
else
report "SERDESP: KO - Serdes parallelized output data is not valid" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD;
--TODO: TEST SER2PAR + PAR2SER SIMULTANEOUSLY
-- many par2ser cycles
bench_ena_serdes0_random_data <= '1';
serdes_expected_output := (others => '0');
serdes_ok := '1';
for cycle_number in 0 to CCSDS_RXTX_BENCH_SERDES0_CYCLES_NUMBER-1 loop
for bit_pointer in (CCSDS_RXTX_BENCH_SERDES0_DEPTH-1) downto 0 loop
if (bit_pointer = (CCSDS_RXTX_BENCH_SERDES0_DEPTH-1)) then
-- signal valid parallel data input
bench_sti_serdes0_data_par_valid <= '1';
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
serdes_expected_output := bench_sti_serdes0_data_par;
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
bench_sti_serdes0_data_par_valid <= '0';
else
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD;
end if;
if (bench_res_serdes0_busy = '0') then
report "SERDESP: KO - Serdes is not busy" severity warning;
else
if (bench_res_serdes0_data_ser_valid = '1') then
if (bench_res_serdes0_data_ser /= serdes_expected_output(bit_pointer)) then
serdes_ok := '0';
report "SERDESP: KO - Serdes serialized output data doesn't match expected output - cycle " & integer'image(bit_pointer) severity warning;
report "Expected value: " & std_logic'image(serdes_expected_output(bit_pointer)) severity warning;
report "Received value: " & std_logic'image(bench_res_serdes0_data_ser) severity warning;
else
if (serdes_ok = '1') and (bit_pointer = 0) and (cycle_number = (CCSDS_RXTX_BENCH_SERDES0_CYCLES_NUMBER-1)) then
report "SERDESP: OK - All serdes serialized output data match expected outputs" severity note;
end if;
end if;
else
report "SERDESP: KO - Serdes serialized output data is not valid" severity warning;
end if;
end if;
end loop;
end loop;
-- many par2ser cycles
serdes_expected_output := (others => '0');
serdes_ok := '1';
for cycle_number in 0 to CCSDS_RXTX_BENCH_SERDES0_CYCLES_NUMBER-1 loop
-- signal valid serial data input
bench_sti_serdes0_data_ser_valid <= '1';
for bit_pointer in (CCSDS_RXTX_BENCH_SERDES0_DEPTH-1) downto 0 loop
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
serdes_expected_output(bit_pointer) := bench_sti_serdes0_data_ser;
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD/2;
end loop;
if (bench_res_serdes0_data_par_valid = '1') then
if (bench_res_serdes0_data_par = serdes_expected_output) then
if (cycle_number = (CCSDS_RXTX_BENCH_SERDES0_CYCLES_NUMBER-1)) and (serdes_ok = '1') then
report "SERDESP: OK - All serdes parallelized output data match expected outputs" severity note;
end if;
else
serdes_ok := '0';
report "SERDESP: KO - Serdes parallelized output data doesn't match expected output" severity warning;
report "Expected value:" severity warning;
for bit_pointer in 0 to CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 loop
report std_logic'image(serdes_expected_output(bit_pointer)) severity warning;
end loop;
report "Received value:" severity warning;
for bit_pointer in 0 to CCSDS_RXTX_BENCH_SERDES0_DEPTH-1 loop
report std_logic'image(bench_res_serdes0_data_par(bit_pointer)) severity warning;
end loop;
end if;
else
report "SERDESP: KO - Serdes parallelized output data is not valid" severity warning;
end if;
end loop;
bench_sti_serdes0_data_ser_valid <= '0';
bench_ena_serdes0_random_data <= '0';
wait for CCSDS_RXTX_BENCH_SERDES0_CLK_PERIOD;
-- final state tests:
-- check serdes is not valid
if (bench_res_serdes0_data_par_valid = '0') then
report "SERDESP: OK - Final state - Serdes parallel output is not valid" severity note;
else
report "SERDESP: KO - Final state - Serdes parallel output is valid" severity warning;
end if;
if (bench_res_serdes0_data_ser_valid = '0') then
report "SERDESP: OK - Final state - Serdes serial output is not valid" severity note;
else
report "SERDESP: KO - Final state - Serdes serial output is valid" severity warning;
end if;
if (bench_res_serdes0_busy = '0') then
report "SERDESP: OK - Final state - Serdes is not busy" severity note;
else
report "SERDESP: KO - Final state - Serdes is busy" severity warning;
end if;
report "SERDESP: END SERDES TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of srrcp
-- generation of SRRC subsystem unit-tests
--=============================================================================
-- read:
-- write:
-- r/w:
SRRCP : process
constant srrc_zero: std_logic_vector(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-1 downto 0) := (others => '0');
variable samples_hex_output: line;
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_srrc0_sam_val = '0') then
report "SRRCP: OK - Default state - SRRC samples are not valid" severity note;
else
report "SRRCP: KO - Default state - SRRC samples are valid" severity warning;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_SRRC_WAIT_DURATION);
-- initial state tests:
if (bench_res_srrc0_sam_val = '0') then
report "SRRCP: OK - Initial state - SRRC samples are not valid" severity note;
else
report "SRRCP: KO - Initial state - SRRC samples are valid" severity warning;
end if;
if (bench_res_srrc0_sam = srrc_zero) then
report "SRRCP: OK - Initial state - SRRC samples are null" severity note;
else
report "SRRCP: KO - Initial state - SRRC samples are not null" severity warning;
end if;
-- behaviour tests:
report "SRRCP: START SRRC TESTS" severity note;
bench_sti_srrc0_sam(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-1) <= '0';
bench_sti_srrc0_sam(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-2 downto 0) <= (others => '1');
bench_sti_srrc0_sam_val <= '1';
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
bench_sti_srrc0_sam <= (others => '0');
if (CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_ENABLE = true) then
for i in 0 to 400 loop
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
if (bench_res_srrc0_sam_val = '1') then
write(samples_hex_output, convert_std_logic_vector_to_hexa_ascii(bench_res_srrc0_sam));
writeline(CCSDS_RXTX_BENCH_SRRC0_OUTPUT_HEX_FILE, samples_hex_output);
else
report "SRRCP: KO - SRRC samples are not valid" severity warning;
end if;
end loop;
else
wait for 400*CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
end if;
bench_sti_srrc0_sam(0) <= '1';
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
bench_sti_srrc0_sam <= (others => '0');
if (CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_ENABLE = true) then
for i in 0 to 400 loop
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
if (bench_res_srrc0_sam_val = '1') then
write(samples_hex_output, convert_std_logic_vector_to_hexa_ascii(bench_res_srrc0_sam));
writeline(CCSDS_RXTX_BENCH_SRRC0_OUTPUT_HEX_FILE, samples_hex_output);
else
report "SRRCP: KO - SRRC samples are not valid" severity warning;
end if;
end loop;
else
wait for 400*CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
end if;
bench_sti_srrc0_sam(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-1) <= '1';
bench_sti_srrc0_sam(CCSDS_RXTX_BENCH_SRRC0_SIG_QUANT_DEPTH-2 downto 0) <= (others => '0');
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
bench_sti_srrc0_sam <= (others => '0');
if (CCSDS_RXTX_BENCH_OUTPUT_SIGNALS_ENABLE = true) then
for i in 0 to 400 loop
wait for CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
if (bench_res_srrc0_sam_val = '1') then
write(samples_hex_output, convert_std_logic_vector_to_hexa_ascii(bench_res_srrc0_sam));
writeline(CCSDS_RXTX_BENCH_SRRC0_OUTPUT_HEX_FILE, samples_hex_output);
else
report "SRRCP: KO - SRRC samples are not valid" severity warning;
end if;
end loop;
else
wait for 400*CCSDS_RXTX_BENCH_SRRC0_CLK_PERIOD;
end if;
bench_sti_srrc0_sam_val <= '0';
-- final state tests:
if (bench_res_srrc0_sam_val = '0') then
report "SRRCP: OK - Final state - SRRC samples are not valid" severity note;
else
report "SRRCP: KO - Final state - SRRC samples are valid" severity warning;
end if;
if (bench_res_srrc0_sam = srrc_zero) then
report "SRRCP: OK - Final state - SRRC samples are null" severity note;
else
report "SRRCP: KO - Final state - SRRC samples are not null" severity warning;
end if;
report "SRRCP: END SRRC TESTS" severity note;
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of resetp
-- generation of reset pulses
--=============================================================================
-- read:
-- write: bench_sti_rxtx0_wb_rst, bench_sti_crc0_rst, bench_sti_buffer0_rst, bench_sti_framer0_rst
-- r/w:
RESETP : process
begin
-- let the system free run
wait for CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION;
report "RESETP: START RESET SIGNAL TEST" severity note;
-- send reset signals
bench_sti_rxtx0_wb_rst <= '1';
bench_sti_coder_conv0_rst <= '1';
bench_sti_coder_diff0_rst <= '1';
bench_sti_crc0_rst <= '1';
bench_sti_buffer0_rst <= '1';
bench_sti_filter0_rst <= '1';
bench_sti_framer0_rst <= '1';
bench_sti_lfsr0_rst <= '1';
bench_sti_mapper_bits_symbols0_rst <= '1';
bench_sti_srrc0_rst <= '1';
-- wait for some time
wait for CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION;
report "RESETP: END RESET SIGNAL TEST" severity note;
-- stop reset signals
bench_sti_rxtx0_wb_rst <= '0';
bench_sti_coder_conv0_rst <= '0';
bench_sti_coder_diff0_rst <= '0';
bench_sti_crc0_rst <= '0';
bench_sti_buffer0_rst <= '0';
bench_sti_filter0_rst <= '0';
bench_sti_framer0_rst <= '0';
bench_sti_lfsr0_rst <= '0';
bench_sti_mapper_bits_symbols0_rst <= '0';
bench_sti_srrc0_rst <= '0';
-- do nothing
wait;
end process;
--=============================================================================
-- Begin of wbrwp
-- generation of master wb read / write cycles / aligned with clk0
--=============================================================================
-- read: bench_res_rxtx0_wb_ack0, bench_res_rxtx0_wb_err0, bench_res_rxtx0_wb_rty0, bench_sti_rxtx0_wb_random_dat0
-- write: bench_sti_rxtx0_wb_adr0, bench_sti_rxtx0_wb_cyc0, bench_sti_rxtx0_wb_stb0, bench_sti_rxtx0_wb_we0, bench_sti_rxtx0_wb_dat0, bench_ena_rxtx0_random_data
-- r/w:
WBRWP : process
variable output_done: boolean := false;
begin
-- let the system free run
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2);
-- default state tests:
if (bench_res_rxtx0_wb_ack = '0') then
report "WBRWP: OK - Default state - ACK not enabled" severity note;
else
report "WBRWP: OK - Default state - ACK enabled" severity warning;
end if;
if (bench_res_rxtx0_wb_err = '0') then
report "WBRWP: OK - Default state - ERR not enabled" severity note;
else
report "WBRWP: OK - Default state - ERR enabled" severity warning;
end if;
if (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - Default state - RTY not enabled" severity note;
else
report "WBRWP: OK - Default state - RTY enabled" severity warning;
end if;
-- let the system reset
wait for (CCSDS_RXTX_BENCH_START_FREE_RUN_DURATION/2 + CCSDS_RXTX_BENCH_START_RESET_SIG_DURATION + CCSDS_RXTX_BENCH_START_WB_WAIT_DURATION);
-- initial state tests:
if (bench_res_rxtx0_wb_ack = '0') then
report "WBRWP: OK - Initial state - ACK not enabled" severity note;
else
report "WBRWP: OK - Initial state - ACK enabled" severity warning;
end if;
if (bench_res_rxtx0_wb_err = '0') then
report "WBRWP: OK - Initial state - ERR not enabled" severity note;
else
report "WBRWP: OK - Initial state - ERR enabled" severity warning;
end if;
if (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - Initial state - RTY not enabled" severity note;
else
report "WBRWP: OK - Initial state - RTY enabled" severity warning;
end if;
-- behaviour tests:
report "WBRWP: START WISHBONE BUS READ-WRITE TESTS" severity note;
bench_ena_rxtx0_random_data <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
-- start a basic rx read cycle
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_adr <= "0000";
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '1') and (bench_res_rxtx0_wb_err = '0') and (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - RX read cycle success" severity note;
else
report "WBRWP: KO - RX read cycle fail" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start an error read cycle
bench_sti_rxtx0_wb_adr <= "0001";
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '0') and (bench_res_rxtx0_wb_err = '1') and (bench_res_rxtx0_wb_rty = '1') then
report "WBRWP: OK - Error read cycle success" severity note;
else
report "WBRWP: KO - Error read cycle fail" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start a basic configuration write cycle -> disable rx
bench_sti_rxtx0_wb_we <= '1';
bench_sti_rxtx0_wb_adr <= "0001";
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '1') and (bench_res_rxtx0_wb_err = '0') and (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - RXTX configuration write cycle success (RX disabled)" severity note;
else
report "WBRWP: KO - RXTX configuration write cycle fail" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start a basic configuration write cycle -> disable tx
bench_sti_rxtx0_wb_we <= '1';
bench_sti_rxtx0_wb_adr <= "0010";
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '1') and (bench_res_rxtx0_wb_err = '0') and (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - RXTX configuration write cycle success (TX disabled)" severity note;
else
report "WBRWP: KO - RXTX configuration write cycle fail" severity warning;
end if;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start a basic configuration write cycle -> enable tx + enable internal wb data use for tx
bench_sti_rxtx0_wb_we <= '1';
bench_sti_rxtx0_wb_adr <= "0010";
bench_sti_rxtx0_wb_dat <= "00000000000000000000000000000001";
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '1') and (bench_res_rxtx0_wb_err = '0') and (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - RXTX configuration write cycle success (TX enabled + internal WB data use)" severity note;
else
report "WBRWP: KO - RXTX configuration write cycle fail" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start a basic tx write cycle
bench_sti_rxtx0_wb_we <= '1';
bench_sti_rxtx0_wb_adr <= "0000";
bench_sti_rxtx0_wb_dat <= bench_sti_rxtx0_wb_random_dat;
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '1') and (bench_res_rxtx0_wb_err = '0') and (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - TX write cycle success" severity note;
else
report "WBRWP: KO - TX write cycle fail" severity warning;
end if;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start an error basic tx write cycle (unknown address)
bench_sti_rxtx0_wb_we <= '1';
bench_sti_rxtx0_wb_adr <= "0011";
bench_sti_rxtx0_wb_dat <= bench_sti_rxtx0_wb_random_dat;
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '0') and (bench_res_rxtx0_wb_err = '1') and (bench_res_rxtx0_wb_rty = '1') then
report "WBRWP: OK - Error write cycle success" severity note;
else
report "WBRWP: KO - Error write cycle fail" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start many tx write cycle
for i in 0 to CCSDS_RXTX_BENCH_RXTX0_WB_TX_WRITE_CYCLE_NUMBER-1 loop
bench_sti_rxtx0_wb_we <= '1';
bench_sti_rxtx0_wb_adr <= "0000";
bench_sti_rxtx0_wb_dat <= bench_sti_rxtx0_wb_random_dat;
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_adr <= "0000";
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
if (bench_res_rxtx0_wb_ack = '0') or (bench_res_rxtx0_wb_err = '1') or (bench_res_rxtx0_wb_rty = '1') then
if (CCSDS_RXTX_BENCH_RXTX0_WB_TX_OVERFLOW = true) then
if (output_done = false) then
output_done := true;
report "WBRWP: OK - Many TX write cycles overflow appears after " & integer'image(i) & " WB write cycles (" & integer'image(i*CCSDS_RXTX_BENCH_RXTX0_WB_DATA_BUS_SIZE) & " bits max burst)" severity note;
end if;
else
report "WBRWP: KO - TX write cycle fail: ACK=" & std_logic'image(bench_res_rxtx0_wb_ack) & " ERR=" & std_logic'image(bench_res_rxtx0_wb_err) & " RTY=" & std_logic'image(bench_res_rxtx0_wb_rty) severity warning;
end if;
else
if (i = CCSDS_RXTX_BENCH_RXTX0_WB_TX_WRITE_CYCLE_NUMBER-1) then
report "WBRWP: OK - Many TX write cycles terminated with success" severity note;
end if;
end if;
if (CCSDS_RXTX_BENCH_RXTX0_WB_TX_OVERFLOW = true) then
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
else
wait for (CCSDS_RXTX_BENCH_RXTX0_WB_WRITE_CYCLES_MAX-1)*CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*2 + CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
end if;
end loop;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD*10;
-- start a basic configuration write cycle -> enable tx + external serial data activation
bench_sti_rxtx0_wb_we <= '1';
bench_sti_rxtx0_wb_adr <= "0010";
bench_sti_rxtx0_wb_dat <= "00000000000000000000000000000011";
bench_sti_rxtx0_wb_cyc <= '1';
bench_sti_rxtx0_wb_stb <= '1';
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
if (bench_res_rxtx0_wb_ack = '1') and (bench_res_rxtx0_wb_err = '0') and (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - Basic configuration write cycle success (TX enabled + external serial data input activated)" severity note;
else
report "WBRWP: KO - Basic configuration write cycle fail" severity warning;
end if;
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
bench_sti_rxtx0_wb_cyc <= '0';
bench_sti_rxtx0_wb_stb <= '0';
bench_sti_rxtx0_wb_we <= '0';
bench_sti_rxtx0_wb_dat <= (others => '0');
bench_sti_rxtx0_wb_adr <= "0000";
wait for CCSDS_RXTX_BENCH_RXTX0_WB_CLK_PERIOD;
-- final state tests:
if (bench_res_rxtx0_wb_ack = '0') then
report "WBRWP: OK - Final state - ACK not enabled" severity note;
else
report "WBRWP: OK - Final state - ACK enabled" severity warning;
end if;
if (bench_res_rxtx0_wb_err = '0') then
report "WBRWP: OK - Final state - ERR not enabled" severity note;
else
report "WBRWP: OK - Final state - ERR enabled" severity warning;
end if;
if (bench_res_rxtx0_wb_rty = '0') then
report "WBRWP: OK - Final state - RTY not enabled" severity note;
else
report "WBRWP: OK - Final state - RTY enabled" severity warning;
end if;
report "WBRWP: END WISHBONE BUS READ-WRITE TESTS" severity note;
-- bench_ena_rxtx0_random_data <= '0';
wait;
end process;
end behaviour;
--=============================================================================
-- architecture end
--=============================================================================
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc618.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:44 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:06 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:23 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00618ent IS
END c03s04b01x00p01n01i00618ent;
ARCHITECTURE c03s04b01x00p01n01i00618arch OF c03s04b01x00p01n01i00618ent IS
constant C4 : real := 3.0;
type real_vector is array (natural range <>) of real;
subtype real_vector_st is real_vector(0 to 15);
type real_vector_st_file is file of real_vector_st;
constant C27 : real_vector_st := (others => C4);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : real_vector_st_file open read_mode is "iofile.31";
variable v : real_vector_st;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C27) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00618"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00618 - File reading operation (real_vector_st file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00618arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc618.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:44 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:06 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:23 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00618ent IS
END c03s04b01x00p01n01i00618ent;
ARCHITECTURE c03s04b01x00p01n01i00618arch OF c03s04b01x00p01n01i00618ent IS
constant C4 : real := 3.0;
type real_vector is array (natural range <>) of real;
subtype real_vector_st is real_vector(0 to 15);
type real_vector_st_file is file of real_vector_st;
constant C27 : real_vector_st := (others => C4);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : real_vector_st_file open read_mode is "iofile.31";
variable v : real_vector_st;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C27) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00618"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00618 - File reading operation (real_vector_st file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00618arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc618.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:44 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:06 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:23 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00618ent IS
END c03s04b01x00p01n01i00618ent;
ARCHITECTURE c03s04b01x00p01n01i00618arch OF c03s04b01x00p01n01i00618ent IS
constant C4 : real := 3.0;
type real_vector is array (natural range <>) of real;
subtype real_vector_st is real_vector(0 to 15);
type real_vector_st_file is file of real_vector_st;
constant C27 : real_vector_st := (others => C4);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : real_vector_st_file open read_mode is "iofile.31";
variable v : real_vector_st;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C27) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00618"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00618 - File reading operation (real_vector_st file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00618arch;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(16,16);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(4 DOWNTO 0) <= WRITE_ADDR(4 DOWNTO 0);
READ_ADDR_INT(4 DOWNTO 0) <= READ_ADDR(4 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(16,16);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(4 DOWNTO 0) <= WRITE_ADDR(4 DOWNTO 0);
READ_ADDR_INT(4 DOWNTO 0) <= READ_ADDR(4 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(16,16);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(4 DOWNTO 0) <= WRITE_ADDR(4 DOWNTO 0);
READ_ADDR_INT(4 DOWNTO 0) <= READ_ADDR(4 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(16,16);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(4 DOWNTO 0) <= WRITE_ADDR(4 DOWNTO 0);
READ_ADDR_INT(4 DOWNTO 0) <= READ_ADDR(4 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(16,16);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(4 DOWNTO 0) <= WRITE_ADDR(4 DOWNTO 0);
READ_ADDR_INT(4 DOWNTO 0) <= READ_ADDR(4 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 32 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
|
-- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Mon Mar 17 09:47:36 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim
-- /home/keith/Documents/VHDL-lib/top/lab_2/part_2/ip/clk_video/clk_video_funcsim.vhdl
-- Design : clk_video
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity clk_videoclk_video_clk_wiz is
port (
clk_100MHz : in STD_LOGIC;
clk_193MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end clk_videoclk_video_clk_wiz;
architecture STRUCTURE of clk_videoclk_video_clk_wiz is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal clk_100MHz_clk_video : STD_LOGIC;
signal clk_193MHz_clk_video : STD_LOGIC;
signal clkfbout_buf_clk_video : STD_LOGIC;
signal clkfbout_clk_video : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute box_type : string;
attribute box_type of clkf_buf : label is "PRIMITIVE";
attribute box_type of clkin1_bufg : label is "PRIMITIVE";
attribute box_type of clkout1_buf : label is "PRIMITIVE";
attribute box_type of mmcm_adv_inst : label is "PRIMITIVE";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_video,
O => clkfbout_buf_clk_video
);
clkin1_bufg: unisim.vcomponents.BUFG
port map (
I => clk_100MHz,
O => clk_100MHz_clk_video
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_193MHz_clk_video,
O => clk_193MHz
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.125000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 9.375000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "BUF_IN",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.000000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_video,
CLKFBOUT => clkfbout_clk_video,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_100MHz_clk_video,
CLKIN2 => \<const0>\,
CLKINSEL => \<const1>\,
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_193MHz_clk_video,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6) => \<const0>\,
DADDR(5) => \<const0>\,
DADDR(4) => \<const0>\,
DADDR(3) => \<const0>\,
DADDR(2) => \<const0>\,
DADDR(1) => \<const0>\,
DADDR(0) => \<const0>\,
DCLK => \<const0>\,
DEN => \<const0>\,
DI(15) => \<const0>\,
DI(14) => \<const0>\,
DI(13) => \<const0>\,
DI(12) => \<const0>\,
DI(11) => \<const0>\,
DI(10) => \<const0>\,
DI(9) => \<const0>\,
DI(8) => \<const0>\,
DI(7) => \<const0>\,
DI(6) => \<const0>\,
DI(5) => \<const0>\,
DI(4) => \<const0>\,
DI(3) => \<const0>\,
DI(2) => \<const0>\,
DI(1) => \<const0>\,
DI(0) => \<const0>\,
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => \<const0>\,
LOCKED => locked,
PSCLK => \<const0>\,
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => \<const0>\,
PSINCDEC => \<const0>\,
PWRDWN => \<const0>\,
RST => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity clk_video is
port (
clk_100MHz : in STD_LOGIC;
clk_193MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_video : entity is true;
attribute core_generation_info : string;
attribute core_generation_info of clk_video : entity is "clk_video,clk_wiz_v5_1,{component_name=clk_video,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_video;
architecture STRUCTURE of clk_video is
begin
U0: entity work.clk_videoclk_video_clk_wiz
port map (
clk_100MHz => clk_100MHz,
clk_193MHz => clk_193MHz,
locked => locked
);
end STRUCTURE;
|
-- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Mon Mar 17 09:47:36 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim
-- /home/keith/Documents/VHDL-lib/top/lab_2/part_2/ip/clk_video/clk_video_funcsim.vhdl
-- Design : clk_video
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity clk_videoclk_video_clk_wiz is
port (
clk_100MHz : in STD_LOGIC;
clk_193MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end clk_videoclk_video_clk_wiz;
architecture STRUCTURE of clk_videoclk_video_clk_wiz is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal clk_100MHz_clk_video : STD_LOGIC;
signal clk_193MHz_clk_video : STD_LOGIC;
signal clkfbout_buf_clk_video : STD_LOGIC;
signal clkfbout_clk_video : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute box_type : string;
attribute box_type of clkf_buf : label is "PRIMITIVE";
attribute box_type of clkin1_bufg : label is "PRIMITIVE";
attribute box_type of clkout1_buf : label is "PRIMITIVE";
attribute box_type of mmcm_adv_inst : label is "PRIMITIVE";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_video,
O => clkfbout_buf_clk_video
);
clkin1_bufg: unisim.vcomponents.BUFG
port map (
I => clk_100MHz,
O => clk_100MHz_clk_video
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_193MHz_clk_video,
O => clk_193MHz
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.125000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 9.375000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "BUF_IN",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.000000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_video,
CLKFBOUT => clkfbout_clk_video,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_100MHz_clk_video,
CLKIN2 => \<const0>\,
CLKINSEL => \<const1>\,
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_193MHz_clk_video,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6) => \<const0>\,
DADDR(5) => \<const0>\,
DADDR(4) => \<const0>\,
DADDR(3) => \<const0>\,
DADDR(2) => \<const0>\,
DADDR(1) => \<const0>\,
DADDR(0) => \<const0>\,
DCLK => \<const0>\,
DEN => \<const0>\,
DI(15) => \<const0>\,
DI(14) => \<const0>\,
DI(13) => \<const0>\,
DI(12) => \<const0>\,
DI(11) => \<const0>\,
DI(10) => \<const0>\,
DI(9) => \<const0>\,
DI(8) => \<const0>\,
DI(7) => \<const0>\,
DI(6) => \<const0>\,
DI(5) => \<const0>\,
DI(4) => \<const0>\,
DI(3) => \<const0>\,
DI(2) => \<const0>\,
DI(1) => \<const0>\,
DI(0) => \<const0>\,
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => \<const0>\,
LOCKED => locked,
PSCLK => \<const0>\,
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => \<const0>\,
PSINCDEC => \<const0>\,
PWRDWN => \<const0>\,
RST => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity clk_video is
port (
clk_100MHz : in STD_LOGIC;
clk_193MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_video : entity is true;
attribute core_generation_info : string;
attribute core_generation_info of clk_video : entity is "clk_video,clk_wiz_v5_1,{component_name=clk_video,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_video;
architecture STRUCTURE of clk_video is
begin
U0: entity work.clk_videoclk_video_clk_wiz
port map (
clk_100MHz => clk_100MHz,
clk_193MHz => clk_193MHz,
locked => locked
);
end STRUCTURE;
|
-- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Mon Mar 17 09:47:36 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim
-- /home/keith/Documents/VHDL-lib/top/lab_2/part_2/ip/clk_video/clk_video_funcsim.vhdl
-- Design : clk_video
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity clk_videoclk_video_clk_wiz is
port (
clk_100MHz : in STD_LOGIC;
clk_193MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end clk_videoclk_video_clk_wiz;
architecture STRUCTURE of clk_videoclk_video_clk_wiz is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal clk_100MHz_clk_video : STD_LOGIC;
signal clk_193MHz_clk_video : STD_LOGIC;
signal clkfbout_buf_clk_video : STD_LOGIC;
signal clkfbout_clk_video : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute box_type : string;
attribute box_type of clkf_buf : label is "PRIMITIVE";
attribute box_type of clkin1_bufg : label is "PRIMITIVE";
attribute box_type of clkout1_buf : label is "PRIMITIVE";
attribute box_type of mmcm_adv_inst : label is "PRIMITIVE";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_video,
O => clkfbout_buf_clk_video
);
clkin1_bufg: unisim.vcomponents.BUFG
port map (
I => clk_100MHz,
O => clk_100MHz_clk_video
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_193MHz_clk_video,
O => clk_193MHz
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.125000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 9.375000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "BUF_IN",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.000000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_video,
CLKFBOUT => clkfbout_clk_video,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_100MHz_clk_video,
CLKIN2 => \<const0>\,
CLKINSEL => \<const1>\,
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_193MHz_clk_video,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6) => \<const0>\,
DADDR(5) => \<const0>\,
DADDR(4) => \<const0>\,
DADDR(3) => \<const0>\,
DADDR(2) => \<const0>\,
DADDR(1) => \<const0>\,
DADDR(0) => \<const0>\,
DCLK => \<const0>\,
DEN => \<const0>\,
DI(15) => \<const0>\,
DI(14) => \<const0>\,
DI(13) => \<const0>\,
DI(12) => \<const0>\,
DI(11) => \<const0>\,
DI(10) => \<const0>\,
DI(9) => \<const0>\,
DI(8) => \<const0>\,
DI(7) => \<const0>\,
DI(6) => \<const0>\,
DI(5) => \<const0>\,
DI(4) => \<const0>\,
DI(3) => \<const0>\,
DI(2) => \<const0>\,
DI(1) => \<const0>\,
DI(0) => \<const0>\,
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => \<const0>\,
LOCKED => locked,
PSCLK => \<const0>\,
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => \<const0>\,
PSINCDEC => \<const0>\,
PWRDWN => \<const0>\,
RST => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity clk_video is
port (
clk_100MHz : in STD_LOGIC;
clk_193MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_video : entity is true;
attribute core_generation_info : string;
attribute core_generation_info of clk_video : entity is "clk_video,clk_wiz_v5_1,{component_name=clk_video,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_video;
architecture STRUCTURE of clk_video is
begin
U0: entity work.clk_videoclk_video_clk_wiz
port map (
clk_100MHz => clk_100MHz,
clk_193MHz => clk_193MHz,
locked => locked
);
end STRUCTURE;
|
library verilog;
use verilog.vl_types.all;
entity dps_lsflags is
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iRESET_SYNC : in vl_logic;
iSCI_VALID : in vl_logic;
iSCI_SCITIE : in vl_logic;
iSCI_SCIRIE : in vl_logic;
iREAD_VALID : in vl_logic;
oLSFLAGS_VALID : out vl_logic;
oLSFLAGS : out vl_logic_vector(31 downto 0)
);
end dps_lsflags;
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY PI_Controller IS
PORT ( error : IN INTEGER ;
control : OUT INTEGER;
clk : in std_logic;
reset : in std_logic) ;
END PI_Controller;
architecture Behavioral of PI_Controller is
signal u1: std_logic_vector(15 downto 0);
constant k1: std_logic_vector( 6 downto 0 ) := "1101011";
begin
process( clk)
begin
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity solver is
port (
clk: in std_logic;
reset: in std_logic;
sat: out std_logic;
unsat: out std_logic
);
end solver;
architecture behavioral of solver is
{% for var in variables %}
component control_{{ var.name }}
port (
clk: in std_logic;
reset: in std_logic;
lclear: out std_logic;
lchange: out std_logic;
lcontra: out std_logic;
gclear: in std_logic;
gchange: in std_logic;
gcontra: in std_logic;
{% for var2 in variables -%}
{{ var2.name }}: inout std_logic_vector(0 to 1);
{% endfor %}
eil: in std_logic;
eol: out std_logic;
eir: in std_logic;
eor: out std_logic;
ldebug_num_decisions: out integer;
ldebug_num_conflicts: out integer;
ldebug_num_backtracks: out integer
);
end component;
for control_{{ var.name }}_0: control_{{ var.name }} use entity work.control_{{ var.name }};
signal lclear_{{ var.name }}, lchange_{{ var.name }}, lcontra_{{ var.name }}: std_logic;
signal {{ var.name }}: std_logic_vector(0 to 1);
signal channel_{{ loop.index }}_0, channel_{{ loop.index }}_1: std_logic;
signal ldebug_num_decisions_{{ var.name }}, ldebug_num_conflicts_{{ var.name }}, ldebug_num_backtracks_{{ var.name }}: integer;
{% endfor %}
signal gclear, gchange, gcontra: std_logic;
signal is_sat, is_unsat: std_logic;
signal gdebug_num_decisions, gdebug_num_conflicts, gdebug_num_backtracks, gdebug_counter: integer;
begin
{% for var in variables %}
control_{{ var.name }}_0: control_{{ var.name }} port map (
clk => clk,
reset => reset,
lclear => lclear_{{ var.name }},
lchange => lchange_{{ var.name }},
lcontra => lcontra_{{ var.name }},
gclear => gclear,
gchange => gchange,
gcontra => gcontra,
{% for var2 in variables -%}
{{ var2.name }} => {{ var2.name }},
{% endfor %}
{% if loop.index > 1 %}
eil => channel_{{ loop.index-1 }}_0,
eol => channel_{{ loop.index-1 }}_1,
{% else %}
eil => '1',
eol => is_unsat,
{% endif %}
{% if loop.index < len_variables %}
eor => channel_{{ loop.index }}_0,
eir => channel_{{ loop.index }}_1,
{% else %}
eor => is_sat,
eir => '0',
{% endif %}
ldebug_num_decisions => ldebug_num_decisions_{{ var.name }},
ldebug_num_conflicts => ldebug_num_conflicts_{{ var.name }},
ldebug_num_backtracks => ldebug_num_backtracks_{{ var.name }}
);
{% endfor %}
gclear <= {% for var in variables %} lclear_{{ var.name }} or{% endfor %} '0';
gchange <= {% for var in variables %} lchange_{{ var.name }} or{% endfor %} '0';
gcontra <= {% for var in variables %} lcontra_{{ var.name }} or{% endfor %} '0';
sat <= is_sat;
unsat <= is_unsat;
process (clk, reset)
begin
if (reset='1') then
gdebug_num_decisions <= 0;
gdebug_num_conflicts <= 0;
gdebug_num_backtracks <= 0;
gdebug_counter <= 0;
else
if (gdebug_counter >= 8192) or (is_sat='1') or (is_unsat='1') then
gdebug_num_decisions <= {% for var in variables %} ldebug_num_decisions_{{ var.name }} {% if not loop.last %}+{% endif %}{% endfor %};
gdebug_num_conflicts <= {% for var in variables %} ldebug_num_conflicts_{{ var.name }} {% if not loop.last %}+{% endif %}{% endfor %};
gdebug_num_backtracks <= {% for var in variables %} ldebug_num_backtracks_{{ var.name }} {% if not loop.last %}+{% endif %}{% endfor %};
report "STATS " & integer'image(gdebug_num_decisions) & " " & integer'image(gdebug_num_conflicts) & " " & integer'image(gdebug_num_backtracks);
gdebug_counter <= 0;
else
gdebug_counter <= gdebug_counter + 1;
end if;
if (is_sat='1') then
report "RESULT SAT";
{% for var in variables %}
if ({{ var.name }}="10") then
report "VALUE {{ var.name }}";
elsif ({{ var.name }}="01") then
report "VALUE -{{ var.name }}";
end if;
{% endfor %}
elsif (is_unsat='1') then
report "RESULT UNSAT";
end if;
end if;
end process;
end behavioral; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:17:32 01/16/2016
-- Design Name:
-- Module Name: nodeController - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity nodeCounter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
countOut : out unsigned (1 downto 0));
end nodeCounter;
architecture Behavioral of nodeCounter is
signal internal: unsigned(1 downto 0);
begin -- architecture arch
process(clk, rst)
begin
if(rst = '1') then
internal <= (others => '0');
elsif(clk'event and clk='1') then
if(enable='1') then
internal <= internal + 1;
end if;
end if;
end process;
countOut <= internal;
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNAY7DSXYU is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000000000101";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNAY7DSXYU is
Begin
-- Constant
output <= "0000000000000101";
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity priority_encoder is
generic(
encoded_word_size : integer := 2
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end entity priority_encoder;
architecture rtl of priority_encoder is
signal any_previous : std_logic_vector(2**encoded_word_size-1 downto 0);
signal highest_bit_only : std_logic_vector(2**encoded_word_size-1 downto 0);
type encoded_sig_type is array(2**encoded_word_size-1 downto 0) of std_logic_vector(encoded_word_size-1 downto 0);
signal encoded_sig : encoded_sig_type;
begin
--- -- Convert to a one hot encoding
--- highest_bit_only(2**encoded_word_size-1) <= input(2**encoded_word_size-1);
--- any_previous(2**encoded_word_size-1) <= input(2**encoded_word_size-1);
--- one_hot_gen: for i in 2**encoded_word_size-2 downto 0 generate
--- begin
--- any_previous(i) <= input(i) or any_previous(i+1);
--- highest_bit_only(i) <= input(i) and not any_previous(i+1);
--- end generate;
---
--- -- create lookup table to convert from one hot to bin
--- -- will be sparse, but I'll trust the compiler for now
--- one_hot_to_bin <= (others => (others => '0'));
--- encode_lut: for i in encoded_word_size-1 downto 0 generate
--- constant output_value : std_logic_vector := std_logic_vector(to_unsigned(i,encoded_word_size));
--- constant lut_index : integer := 2**i;
--- begin
--- one_hot_to_bin(lut_index) <= output_value;
--- end generate;
---
--- -- output
--- output <= one_hot_to_bin(to_integer(unsigned(highest_bit_only)));
--process(input)
-- variable keep_looking : std_logic := '1';
--begin
-- for i in 2**encoded_word_size-1 downto 0 loop
-- if input(i) = '1' and keep_looking = '1' then
-- output <= std_logic_vector(to_unsigned(i, encoded_word_size));
-- keep_looking := '0';
-- end if;
-- end loop;
--end process;
any_previous(2**encoded_word_size-1) <= input(2**encoded_word_size-1);
encoded_sig(2**encoded_word_size-1) <= std_logic_vector(to_unsigned(2**encoded_word_size-1, encoded_word_size));
encode: for i in 2**encoded_word_size-2 downto 0 generate
begin
any_previous(i) <= input(i) or any_previous(i+1);
encoded_sig(i) <= std_logic_vector(to_unsigned(i, encoded_word_size)) when any_previous(i+1) = '0' else encoded_sig(i+1);
end generate;
output <= encoded_sig(0);
end architecture rtl; |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0;
USE axi_bram_ctrl_v4_0.axi_bram_ctrl;
ENTITY design_1_axi_bram_ctrl_1_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_bram_ctrl_1_0;
ARCHITECTURE design_1_axi_bram_ctrl_1_0_arch OF design_1_axi_bram_ctrl_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 2048,
C_BRAM_ADDR_WIDTH => 11,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_bram_ctrl_1_0_arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research
-- Description: Combined LEON3 debug support and AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity dsu3x is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type;
hclken : in std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of dsu3x is
constant TBUFABITS : integer := log2(kbytes) + 6;
constant NBITS : integer := log2x(ncpu);
constant PROC_H : integer := 24+NBITS-1;
constant PROC_L : integer := 24;
constant AREA_H : integer := 23;
constant AREA_L : integer := 20;
constant HBITS : integer := 28;
constant DSU3_VERSION : integer := 1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON3DSU, 0, DSU3_VERSION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
others => zero32);
type slv_reg_type is record
hsel : std_ulogic;
haddr : std_logic_vector(PROC_H downto 0);
hwrite : std_ulogic;
hwdata : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hready : std_ulogic;
hready2 : std_ulogic;
end record;
constant slv_reg_none : slv_reg_type := (
hsel => '0',
haddr => (others => '0'),
hwrite => '0',
hwdata => (others => '0'),
hrdata => (others => '0'),
hready => '1',
hready2 => '1'
);
type reg_type is record
slv : slv_reg_type;
en : std_logic_vector(0 to NCPU-1);
te : std_logic_vector(0 to NCPU-1);
be : std_logic_vector(0 to NCPU-1);
bw : std_logic_vector(0 to NCPU-1);
bs : std_logic_vector(0 to NCPU-1);
bx : std_logic_vector(0 to NCPU-1);
bz : std_logic_vector(0 to NCPU-1);
halt : std_logic_vector(0 to NCPU-1);
reset : std_logic_vector(0 to NCPU-1);
bn : std_logic_vector(NCPU-1 downto 0);
ss : std_logic_vector(NCPU-1 downto 0);
bmsk : std_logic_vector(NCPU-1 downto 0);
dmsk : std_logic_vector(NCPU-1 downto 0);
cnt : std_logic_vector(2 downto 0);
dsubre : std_logic_vector(2 downto 0);
dsuen : std_logic_vector(2 downto 0);
act : std_ulogic;
timer : std_logic_vector(tbits-1 downto 0);
pwd : std_logic_vector(NCPU-1 downto 0);
tstop : std_ulogic;
end record;
constant RRES : reg_type := (
slv => slv_reg_none,
en => (others => '0'),
te => (others => '0'),
be => (others => '0'),
bw => (others => '0'),
bs => (others => '0'),
bx => (others => '0'),
bz => (others => '0'),
halt => (others => '0'),
reset => (others => '0'),
bn => (others => '0'),
ss => (others => '0'),
bmsk => (others => '0'),
dmsk => (others => '0'),
cnt => (others => '0'),
dsubre => (others => '0'),
dsuen => (others => '0'),
act => '0',
timer => (others => '0'),
pwd => (others => '0'),
tstop => '0'
);
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
end record;
constant trace_break_none : trace_break_reg := (
addr => (others => '0'),
mask => (others => '0'),
read => '0',
write => '0'
);
type t_reg_type is record
haddr : std_logic_vector(31 downto 0);
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
hmastlock : std_logic;
hsel : std_logic;
ahbactive : std_logic;
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
enable : std_logic; -- trace enable
bphit : std_logic; -- AHB breakpoint hit
bphit2 : std_logic; -- delayed bphit
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
tbwr : std_logic; -- trace buffer write enable
break : std_logic; -- break CPU when AHB tracing stops
end record;
constant TRES : t_reg_type := (
haddr => (others => '0'),
hwrite => '0',
htrans => (others => '0'),
hsize => (others => '0'),
hburst => (others => '0'),
hwdata => (others => '0'),
hmaster => (others => '0'),
hmastlock => '0',
hsel => '0',
ahbactive => '0',
aindex => (others => '0'),
enable => '0',
bphit => '0',
bphit2 => '0',
dcnten => '0',
delaycnt => (others => '0'),
tbreg1 => trace_break_none,
tbreg2 => trace_break_none,
tbwr => '0',
break => '0'
);
type hclk_reg_type is record
irq : std_ulogic;
oen : std_ulogic;
end record;
constant hclk_reg_none : hclk_reg_type := (
irq => '0', oen => '0'
);
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant TRACEN : boolean := (kbytes /= 0);
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal tr, trin : t_reg_type;
signal r, rin : reg_type;
signal rh, rhin : hclk_reg_type;
signal ahbsi2, tahbsi2 : ahb_slv_in_type;
signal hrdata2x : std_logic_vector(31 downto 0);
begin
comb: process(rst, r, ahbsi, ahbsi2, tahbsi2, dbgi, dsui, ahbmi, tr, tbo, hclken, rh, hrdata2x)
variable v : reg_type;
variable iuacc : std_ulogic;
variable dbgmode, tstop : std_ulogic;
variable rawindex : integer range 0 to (2**NBITS)-1;
variable index : natural range 0 to NCPU-1;
variable hasel1 : std_logic_vector(AREA_H-1 downto AREA_L);
variable hasel2 : std_logic_vector(6 downto 2);
variable tv : t_reg_type;
variable vabufi : tracebuf_in_type;
variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable cpwd : std_logic_vector(15 downto 0);
variable hrdata : std_logic_vector(31 downto 0);
variable bphit1, bphit2 : std_ulogic;
variable vh : hclk_reg_type;
begin
v := r;
iuacc := '0'; --v.slv.hready := '0';
dbgmode := '0'; tstop := '1';
v.dsubre := r.dsubre(1 downto 0) & dsui.break;
v.dsuen := r.dsuen(1 downto 0) & dsui.enable;
hrdata := r.slv.hrdata;
tv := tr; vabufi.enable := '0'; tv.bphit := '0'; tv.tbwr := '0';
if (clk2x /= 0) then tv.bphit2 := tr.bphit; else tv.bphit2 := '0'; end if;
vabufi.data := (others => '0'); vabufi.addr := (others => '0');
vabufi.write := (others => '0'); aindex := (others => '0');
hirq := (others => '0'); v.reset := (others => '0');
if TRACEN then
aindex := tr.aindex + 1;
if (clk2x /= 0) then vh.irq := tr.bphit or tr.bphit2; hirq(irq) := rh.irq;
else hirq(irq) := tr.bphit; end if;
end if;
if hclken = '1' then
v.slv.hready := '0'; v.act := '0';
end if;
-- check for AHB watchpoints
bphit1 := '0'; bphit2 := '0';
if TRACEN and ((tahbsi2.hready and tr.ahbactive) = '1') then
if ((((tr.tbreg1.addr xor tr.haddr(31 downto 2)) and tr.tbreg1.mask) = zero32(29 downto 0)) and
(((tr.tbreg1.read and not tr.hwrite) or (tr.tbreg1.write and tr.hwrite)) = '1'))
then bphit1 := '1'; end if;
if ((((tr.tbreg2.addr xor tr.haddr(31 downto 2)) and tr.tbreg2.mask) = zero32(29 downto 0)) and
(((tr.tbreg2.read and not tr.hwrite) or (tr.tbreg2.write and tr.hwrite)) = '1'))
then bphit2 := '1'; end if;
if (bphit1 or bphit2) = '1' then
if ((tr.enable and not r.act) = '1') and (tr.dcnten = '0') and
(tr.delaycnt /= zero32(TBUFABITS-1 downto 0))
then tv.dcnten := '1';
else tv.enable := '0'; tv.bphit := tr.break; end if;
end if;
end if;
-- generate AHB buffer inputs
vabufi.write := "0000";
if TRACEN then
if (tr.enable = '1') and (r.act = '0') then
vabufi.addr(TBUFABITS-1 downto 0) := tr.aindex;
vabufi.data(127) := bphit1 or bphit2;
vabufi.data(96+tbits-1 downto 96) := r.timer;
vabufi.data(94 downto 80) := ahbmi.hirq(15 downto 1);
vabufi.data(79) := tr.hwrite;
vabufi.data(78 downto 77) := tr.htrans;
vabufi.data(76 downto 74) := tr.hsize;
vabufi.data(73 downto 71) := tr.hburst;
vabufi.data(70 downto 67) := tr.hmaster;
vabufi.data(66) := tr.hmastlock;
vabufi.data(65 downto 64) := ahbmi.hresp;
if tr.hwrite = '1' then
vabufi.data(63 downto 32) := ahbsi2.hwdata(31 downto 0);
else
vabufi.data(63 downto 32) := ahbmi.hrdata(31 downto 0);
end if;
vabufi.data(31 downto 0) := tr.haddr;
else
vabufi.addr(TBUFABITS-1 downto 0) := tr.haddr(TBUFABITS+3 downto 4);
vabufi.data := ahbsi2.hwdata(31 downto 0) & ahbsi2.hwdata(31 downto 0) & ahbsi2.hwdata(31 downto 0) & ahbsi2.hwdata(31 downto 0);
end if;
-- write trace buffer
if (tr.enable and not r.act) = '1' then
if (tr.ahbactive and ahbsi2.hready) = '1' then
tv.aindex := aindex; tv.tbwr := '1';
vabufi.enable := '1'; vabufi.write := "1111";
end if;
end if;
-- trace buffer delay counter handling
if (tr.dcnten = '1') then
if (tr.delaycnt = zero32(TBUFABITS-1 downto 0)) then
tv.enable := '0'; tv.dcnten := '0'; tv.bphit := tr.break;
end if;
if tr.tbwr = '1' then tv.delaycnt := tr.delaycnt - 1; end if;
end if;
-- save AHB transfer parameters
if (tahbsi2.hready = '1' ) then
tv.haddr := tahbsi2.haddr; tv.hwrite := tahbsi2.hwrite; tv.htrans := tahbsi2.htrans;
tv.hsize := tahbsi2.hsize; tv.hburst := tahbsi2.hburst;
tv.hmaster := tahbsi2.hmaster; tv.hmastlock := tahbsi2.hmastlock;
end if;
if tr.hsel = '1' then tv.hwdata := tahbsi2.hwdata(31 downto 0); end if;
if tahbsi2.hready = '1' then
tv.hsel := tahbsi2.hsel(hindex);
tv.ahbactive := tahbsi2.htrans(1);
end if;
end if;
if r.slv.hsel = '1' then
if (clk2x = 0) then
v.cnt := r.cnt - 1;
else
if (r.cnt /= "111") or (hclken = '1') then v.cnt := r.cnt - 1; end if;
end if;
end if;
if (r.slv.hready and hclken) = '1' then
v.slv.hsel := '0'; --v.slv.act := '0';
end if;
for i in 0 to NCPU-1 loop
if dbgi(i).dsumode = '1' then
if r.dmsk(i) = '0' then
dbgmode := '1';
if hclken = '1' then v.act := '1'; end if;
end if;
v.bn(i) := '1';
else
tstop := '0';
end if;
end loop;
if tstop = '0' then v.timer := r.timer + 1; end if;
if (clk2x /= 0) then
if hclken = '1' then v.tstop := tstop; end if;
tstop := r.tstop;
end if;
cpwd := (others => '0');
for i in 0 to NCPU-1 loop
v.bn(i) := v.bn(i) or (dbgmode and r.bmsk(i)) or (r.dsubre(1) and not r.dsubre(2));
if TRACEN then v.bn(i) := v.bn(i) or (tr.bphit and not r.ss(i) and not r.act); end if;
v.pwd(i) := dbgi(i).idle and (not dbgi(i).ipend) and not v.bn(i);
end loop;
cpwd(NCPU-1 downto 0) := r.pwd;
if (ahbsi2.hready and ahbsi2.hsel(hindex)) = '1' then
if (ahbsi2.htrans(1) = '1') then
v.slv.hsel := '1';
v.slv.haddr := ahbsi2.haddr(PROC_H downto 0);
v.slv.hwrite := ahbsi2.hwrite;
v.cnt := "111";
end if;
end if;
for i in 0 to NCPU-1 loop
v.en(i) := r.dsuen(2) and dbgi(i).dsu;
end loop;
rawindex := conv_integer(r.slv.haddr(PROC_H downto PROC_L));
if ncpu = 1 then index := 0; else
if rawindex > ncpu then index := ncpu-1; else index := rawindex; end if;
end if;
hasel1 := r.slv.haddr(AREA_H-1 downto AREA_L);
hasel2 := r.slv.haddr(6 downto 2);
if r.slv.hsel = '1' then
case hasel1 is
when "000" => -- DSU registers
if r.cnt(2 downto 0) = "110" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
hrdata := (others => '0');
case hasel2 is
when "00000" =>
if r.slv.hwrite = '1' then
if hclken = '1' then
v.te(index) := ahbsi2.hwdata(0);
v.be(index) := ahbsi2.hwdata(1);
v.bw(index) := ahbsi2.hwdata(2);
v.bs(index) := ahbsi2.hwdata(3);
v.bx(index) := ahbsi2.hwdata(4);
v.bz(index) := ahbsi2.hwdata(5);
v.reset(index) := ahbsi2.hwdata(9);
v.halt(index) := ahbsi2.hwdata(10);
else v.reset := r.reset; end if;
end if;
hrdata(0) := r.te(index);
hrdata(1) := r.be(index);
hrdata(2) := r.bw(index);
hrdata(3) := r.bs(index);
hrdata(4) := r.bx(index);
hrdata(5) := r.bz(index);
hrdata(6) := dbgi(index).dsumode;
hrdata(7) := r.dsuen(2);
hrdata(8) := r.dsubre(2);
hrdata(9) := not dbgi(index).error;
hrdata(10) := dbgi(index).halt;
hrdata(11) := dbgi(index).pwd;
when "00010" => -- timer
if r.slv.hwrite = '1' then
if hclken = '1' then
v.timer := ahbsi2.hwdata(tbits-1 downto 0);
else v.timer := r.timer; end if;
end if;
hrdata(tbits-1 downto 0) := r.timer;
when "01000" =>
if r.slv.hwrite = '1' then
if hclken = '1' then
v.bn := ahbsi2.hwdata(NCPU-1 downto 0);
v.ss := ahbsi2.hwdata(16+NCPU-1 downto 16);
else v.bn := r.bn; v.ss := r.ss; end if;
end if;
hrdata(NCPU-1 downto 0) := r.bn;
hrdata(16+NCPU-1 downto 16) := r.ss;
when "01001" =>
if (r.slv.hwrite and hclken) = '1' then
v.bmsk(NCPU-1 downto 0) := ahbsi2.hwdata(NCPU-1 downto 0);
v.dmsk(NCPU-1 downto 0) := ahbsi2.hwdata(NCPU-1+16 downto 16);
end if;
hrdata(NCPU-1 downto 0) := r.bmsk;
hrdata(NCPU-1+16 downto 16) := r.dmsk;
when "10000" =>
if TRACEN then
hrdata((TBUFABITS + 15) downto 16) := tr.delaycnt;
hrdata(2 downto 0) := tr.break & tr.dcnten & tr.enable;
if r.slv.hwrite = '1' then
if hclken = '1' then
tv.delaycnt := ahbsi2.hwdata((TBUFABITS+ 15) downto 16);
tv.break := ahbsi2.hwdata(2);
tv.dcnten := ahbsi2.hwdata(1);
tv.enable := ahbsi2.hwdata(0);
else
tv.delaycnt := tr.delaycnt; tv.break := tr.break;
tv.dcnten := tr.dcnten; tv.enable := tr.enable;
end if;
end if;
end if;
when "10001" =>
if TRACEN then
hrdata((TBUFABITS - 1 + 4) downto 4) := tr.aindex;
if r.slv.hwrite = '1' then
if hclken = '1' then
tv.aindex := ahbsi2.hwdata((TBUFABITS - 1 + 4) downto 4);
else tv.aindex := tr.aindex; end if;
end if;
end if;
when "10100" =>
if TRACEN then
hrdata(31 downto 2) := tr.tbreg1.addr;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg1.addr := ahbsi2.hwdata(31 downto 2);
end if;
end if;
when "10101" =>
if TRACEN then
hrdata := tr.tbreg1.mask & tr.tbreg1.read & tr.tbreg1.write;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg1.mask := ahbsi2.hwdata(31 downto 2);
tv.tbreg1.read := ahbsi2.hwdata(1);
tv.tbreg1.write := ahbsi2.hwdata(0);
end if;
end if;
when "10110" =>
if TRACEN then
hrdata(31 downto 2) := tr.tbreg2.addr;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg2.addr := ahbsi2.hwdata(31 downto 2);
end if;
end if;
when "10111" =>
if TRACEN then
hrdata := tr.tbreg2.mask & tr.tbreg2.read & tr.tbreg2.write;
if (r.slv.hwrite and hclken) = '1' then
tv.tbreg2.mask := ahbsi2.hwdata(31 downto 2);
tv.tbreg2.read := ahbsi2.hwdata(1);
tv.tbreg2.write := ahbsi2.hwdata(0);
end if;
end if;
when others =>
end case;
when "010" => -- AHB tbuf
if TRACEN then
if r.cnt(2 downto 0) = "101" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
vabufi.enable := not (tr.enable and not r.act);
case tr.haddr(3 downto 2) is
when "00" =>
hrdata := tbo.data(127 downto 96);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(3) := vabufi.enable and v.slv.hready;
end if;
when "01" =>
hrdata := tbo.data(95 downto 64);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(2) := vabufi.enable and v.slv.hready;
end if;
when "10" =>
hrdata := tbo.data(63 downto 32);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(1) := vabufi.enable and v.slv.hready;
end if;
when others =>
hrdata := tbo.data(31 downto 0);
if (r.slv.hwrite and hclken) = '1' then
vabufi.write(0) := vabufi.enable and v.slv.hready;
end if;
end case;
else
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "011" | "001" => -- IU reg file, IU tbuf
iuacc := '1';
hrdata := dbgi(index).data;
if r.cnt(2 downto 0) = "101" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "100" => -- IU reg access
iuacc := '1';
hrdata := dbgi(index).data;
if r.cnt(1 downto 0) = "11" then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
when "111" => -- DSU ASI
if r.cnt(2 downto 1) = "11" then iuacc := '1'; else iuacc := '0'; end if;
if (dbgi(index).crdy = '1') or (r.cnt = "000") then
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end if;
hrdata := dbgi(index).data;
when others =>
if hclken = '1' then v.slv.hready := '1'; else v.slv.hready2 := '1'; end if;
end case;
if (r.slv.hready and hclken and not v.slv.hsel) = '1' then v.slv.hready := '0'; end if;
if (clk2x /= 0) and (r.slv.hready2 and hclken) = '1' then v.slv.hready := '1'; end if;
end if;
if r.slv.hsel = '1' then
if (r.slv.hwrite and hclken) = '1' then v.slv.hwdata := ahbsi2.hwdata(31 downto 0); end if;
if (clk2x = 0) or ((r.slv.hready or r.slv.hready2) = '0') then
v.slv.hrdata := hrdata;
end if;
end if;
if ((ahbsi2.hready and ahbsi2.hsel(hindex)) = '1') and (ahbsi2.htrans(1) = '0') then
if (clk2x = 0) or (r.slv.hsel = '0') then
v.slv.hready := '1';
end if;
end if;
if (clk2x /= 0) and (r.slv.hready = '1') then v.slv.hready2 := '0'; end if;
if v.slv.hsel = '0' then v.slv.hready := '1'; end if;
vh.oen := '0';
if (clk2x /= 0) then
if (hclken and r.slv.hsel and (r.slv.hready2 or v.slv.hready)) = '1'
then vh.oen := '1'; end if;
if (r.slv.hsel = '1') and (r.cnt = "111") and (hclken = '0') then iuacc := '0'; end if;
end if;
if (not RESET_ALL) and (rst = '0') then
v.bn := (others => r.dsubre(2)); v.bmsk := (others => '0');
v.dmsk := (others => '0');
v.ss := (others => '0'); v.timer := (others => '0'); v.slv.hsel := '0';
for i in 0 to NCPU-1 loop
v.bw(i) := r.dsubre(2); v.be(i) := r.dsubre(2);
v.bx(i) := r.dsubre(2); v.bz(i) := r.dsubre(2);
v.bs(i) := '0'; v.te(i) := '0';
end loop;
tv.ahbactive := '0'; tv.enable := '0';
tv.hsel := '0'; tv.dcnten := '0';
tv.tbreg1.read := '0'; tv.tbreg1.write := '0';
tv.tbreg2.read := '0'; tv.tbreg2.write := '0';
v.slv.hready := '1'; v.halt := (others => '0');
v.act := '0'; v.tstop := '0';
end if;
vabufi.enable := vabufi.enable and not ahbsi.scanen;
vabufi.diag := ahbsi.testen & "000";
rin <= v; trin <= tv; tbi <= vabufi;
for i in 0 to NCPU-1 loop
dbgo(i).tenable <= r.te(i);
dbgo(i).dsuen <= r.en(i);
dbgo(i).dbreak <= r.bn(i); -- or (dbgmode and r.bmsk(i));
if conv_integer(r.slv.haddr(PROC_H downto PROC_L)) = i then
dbgo(i).denable <= iuacc;
else
dbgo(i).denable <= '0';
end if;
dbgo(i).step <= r.ss(i);
dbgo(i).berror <= r.be(i);
dbgo(i).bsoft <= r.bs(i);
dbgo(i).bwatch <= r.bw(i);
dbgo(i).btrapa <= r.bx(i);
dbgo(i).btrape <= r.bz(i);
dbgo(i).daddr <= r.slv.haddr(PROC_L-1 downto 2);
dbgo(i).ddata <= r.slv.hwdata(31 downto 0);
dbgo(i).dwrite <= r.slv.hwrite;
dbgo(i).halt <= r.halt(i);
dbgo(i).reset <= r.reset(i);
dbgo(i).timer(tbits-1 downto 0) <= r.timer;
dbgo(i).timer(30 downto tbits) <= (others => '0');
end loop;
ahbso.hconfig <= hconfig;
ahbso.hresp <= HRESP_OKAY;
ahbso.hready <= r.slv.hready;
if (clk2x = 0) then
ahbso.hrdata <= ahbdrivedata(r.slv.hrdata);
else
ahbso.hrdata <= ahbdrivedata(hrdata2x);
end if;
ahbso.hsplit <= (others => '0');
ahbso.hirq <= hirq;
ahbso.hindex <= hindex;
dsuo.active <= r.act;
dsuo.tstop <= tstop;
dsuo.pwd <= cpwd;
rhin <= vh;
end process;
comb2gen0 : if (clk2x /= 0) generate
-- register i/f
gen0 : for i in ahbsi.hsel'range generate
ag0 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hsel(i), hclken, ahbsi2.hsel(i));
end generate;
gen1 : for i in ahbsi.haddr'range generate
ag1 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.haddr(i), hclken, ahbsi2.haddr(i));
end generate;
ag2 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwrite, hclken, ahbsi2.hwrite);
gen3 : for i in ahbsi.htrans'range generate
ag3 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.htrans(i), hclken, ahbsi2.htrans(i));
end generate;
gen4 : for i in ahbsi.hwdata'range generate
ag4 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwdata(i), hclken, ahbsi2.hwdata(i));
end generate;
ag5 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hready, hclken, ahbsi2.hready);
-- not used by register i/f:
ahbsi2.hsize <= (others => '0');
ahbsi2.hburst <= (others => '0');
ahbsi2.hprot <= (others => '0');
ahbsi2.hmaster <= (others => '0');
ahbsi2.hmastlock <= '0';
ahbsi2.hmbsel <= (others => '0');
ahbsi2.hirq <= (others => '0');
ahbsi2.testen <= '0';
ahbsi2.testrst <= '0';
ahbsi2.scanen <= '0';
ahbsi2.testoen <= '0';
-- trace buffer:
gen6 : for i in tahbsi.haddr'range generate
ag6 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.haddr(i), hclken, tahbsi2.haddr(i));
end generate;
ag7 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hwrite, hclken, tahbsi2.hwrite);
gen8 : for i in tahbsi.htrans'range generate
ag8 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.htrans(i), hclken, tahbsi2.htrans(i));
end generate;
gen9 : for i in tahbsi.hsize'range generate
ag9 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hsize(i), hclken, tahbsi2.hsize(i));
end generate;
gen10 : for i in tahbsi.hburst'range generate
a10 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hburst(i), hclken, tahbsi2.hburst(i));
end generate;
gen11 : for i in tahbsi.hwdata'range generate
ag11 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hwdata(i), hclken, tahbsi2.hwdata(i));
end generate;
ag12 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hready, hclken, tahbsi2.hready);
gen12 : for i in tahbsi.hmaster'range generate
ag12 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hmaster(i), hclken, tahbsi2.hmaster(i));
end generate;
ag13 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hmastlock, hclken, tahbsi2.hmastlock);
gen14 : for i in tahbsi.hsel'range generate
ag14 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hsel(i), hclken, tahbsi2.hsel(i));
end generate;
-- not used by trace buffer:
tahbsi2.hprot <= (others => '0');
tahbsi2.hmbsel <= (others => '0');
tahbsi2.hirq <= (others => '0');
tahbsi2.testen <= '0';
tahbsi2.testrst <= '0';
tahbsi2.scanen <= '0';
tahbsi2.testoen <= '0';
gen15 : for i in hrdata2x'range generate
ag15 : clkand generic map (tech => 0, ren => 0) port map (r.slv.hrdata(i), rh.oen, hrdata2x(i));
end generate;
reg2 : process(hclk)
begin
if rising_edge(hclk) then rh <= rhin; end if;
end process;
end generate;
comb2gen1 : if (clk2x = 0) generate
ahbsi2 <= ahbsi; rh.irq <= '0'; rh.oen <= '0'; hrdata2x <= (others => '0');
tahbsi2 <= tahbsi;
end generate;
reg : process(cpuclk)
begin
if rising_edge(cpuclk) then
r <= rin;
if RESET_ALL and (rst = '0') then
r <= RRES;
for i in 0 to NCPU-1 loop
r.bn(i) <= r.dsubre(2); r.bw(i) <= r.dsubre(2);
r.be(i) <= r.dsubre(2); r.bx(i) <= r.dsubre(2);
r.bz(i) <= r.dsubre(2);
end loop;
r.dsubre <= rin.dsubre; -- Sync. regs.
r.dsuen <= rin.dsuen;
r.en <= rin.en;
end if;
end if;
end process;
tb0 : if TRACEN generate
treg : process(cpuclk)
begin
if rising_edge(cpuclk) then
tr <= trin;
if RESET_ALL and (rst = '0') then tr <= TRES; end if;
end if;
end process;
mem0 : tbufmem
generic map (tech => tech, tbuf => kbytes, testen => testen) port map (cpuclk, tbi, tbo);
-- pragma translate_off
bootmsg : report_version
generic map ("dsu3_" & tost(hindex) &
": LEON3 Debug support unit + AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end generate;
notb : if not TRACEN generate
-- pragma translate_off
bootmsg : report_version
generic map ("dsu3_" & tost(hindex) &
": LEON3 Debug support unit");
-- pragma translate_on
end generate;
end;
|
architecture RTL of FIFO is
type memory is array (natural range<>) of std_logic_vector(3 downto 0);
type memory is array (natural range<>, natural range <>) of std_logic_vector(3 downto 0);
begin
end architecture RTL;
|
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity counter_tb is
end;
architecture counter_tb of counter_tb is
component counter
port ( count : out std_logic_vector(3 downto 0);
clk : in std_logic;
enable: in std_logic;
reset : in std_logic);
end component ;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal enable : std_logic := '0';
signal count : std_logic_vector(3 downto 0);
begin
dut : counter
port map (
count => count,
clk => clk,
enable=> enable,
reset => reset );
clock : process
begin
wait for 1 ns; clk <= not clk;
end process clock;
stimulus : process
begin
wait for 5 ns; reset <= '1';
wait for 4 ns; reset <= '0';
wait for 4 ns; enable <= '1';
wait;
end process stimulus;
monitor : process (clk)
variable c_str : line;
begin
if (clk = '1' and clk'event) then
write(c_str,count);
assert false report time'image(now) &
": Current Count Value : " & c_str.all
severity note;
deallocate(c_str);
end if;
end process monitor;
end counter_tb;
|
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity counter_tb is
end;
architecture counter_tb of counter_tb is
component counter
port ( count : out std_logic_vector(3 downto 0);
clk : in std_logic;
enable: in std_logic;
reset : in std_logic);
end component ;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal enable : std_logic := '0';
signal count : std_logic_vector(3 downto 0);
begin
dut : counter
port map (
count => count,
clk => clk,
enable=> enable,
reset => reset );
clock : process
begin
wait for 1 ns; clk <= not clk;
end process clock;
stimulus : process
begin
wait for 5 ns; reset <= '1';
wait for 4 ns; reset <= '0';
wait for 4 ns; enable <= '1';
wait;
end process stimulus;
monitor : process (clk)
variable c_str : line;
begin
if (clk = '1' and clk'event) then
write(c_str,count);
assert false report time'image(now) &
": Current Count Value : " & c_str.all
severity note;
deallocate(c_str);
end if;
end process monitor;
end counter_tb;
|
-- TIMER.VHD (a peripheral module for SCOMP)
-- 2003.04.24
--
-- Timer returns a 16 bit counter value with a resolution of the CLOCK period.
-- Writing any value to timer resets to 0x0000, but the timer continues to run.
-- The counter value rolls over to 0x0000 after a clock tick at 0xFFFF.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CTIMER IS
PORT(CLOCK,
RESETN,
CS : IN STD_LOGIC;
IO_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
INT : OUT STD_LOGIC );
END CTIMER;
ARCHITECTURE a OF CTIMER IS
SIGNAL COUNT : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL TRIGVAL : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
-- Use value from SCOMP as trigger value
PROCESS (CS, RESETN)
BEGIN
IF RESETN = '0' THEN
TRIGVAL <= x"0000";
ELSIF RISING_EDGE(CS) THEN
TRIGVAL <= IO_DATA;
END IF;
END PROCESS;
-- Count up until reaching trigger value, then reset.
PROCESS (CLOCK, RESETN, CS)
BEGIN
IF (RESETN = '0') OR (CS = '1') THEN
COUNT <= x"0000";
ELSIF (FALLING_EDGE(CLOCK)) THEN
IF TRIGVAL = x"0000" THEN
INT <= '0';
ELSIF COUNT = TRIGVAL THEN
COUNT <= x"0001";
INT <= '1';
ELSE
COUNT <= COUNT + 1;
INT <= '0';
END IF;
END IF;
END PROCESS;
END a;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- dvb_ts_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity dvb_ts_0 is
port (
address : in std_logic_vector(8 downto 0) := (others => '0'); -- avalon_slave_0.address
byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
write : in std_logic := '0'; -- .write
readdata : out std_logic_vector(31 downto 0); -- .readdata
read : in std_logic := '0'; -- .read
waitrequest : out std_logic; -- .waitrequest
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
interrupt : out std_logic; -- conduit_end.export
cam_bypass : in std_logic := '0'; -- .export
dvb_in0_dsop : in std_logic := '0'; -- .export
dvb_in0_data : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
dvb_in0_dval : in std_logic := '0'; -- .export
dvb_in1_dsop : in std_logic := '0'; -- .export
dvb_in1_data : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
dvb_in1_dval : in std_logic := '0'; -- .export
dvb_in2_dsop : in std_logic := '0'; -- .export
dvb_in2_data : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
dvb_in2_dval : in std_logic := '0'; -- .export
cam_baseclk : in std_logic := '0'; -- .export
cam_mclki : out std_logic; -- .export
cam_mdi : out std_logic_vector(7 downto 0); -- .export
cam_mival : out std_logic; -- .export
cam_mistrt : out std_logic; -- .export
cam_mclko : in std_logic := '0'; -- .export
cam_mdo : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
cam_mostrt : in std_logic := '0'; -- .export
cam_moval : in std_logic := '0'; -- .export
dvb_out_dsop : out std_logic; -- .export
dvb_out_dval : out std_logic; -- .export
dvb_out_data : out std_logic_vector(7 downto 0) -- .export
);
end entity dvb_ts_0;
architecture rtl of dvb_ts_0 is
component dvb_ts is
port (
address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
read : in std_logic := 'X'; -- read
waitrequest : out std_logic; -- waitrequest
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
interrupt : out std_logic; -- export
cam_bypass : in std_logic := 'X'; -- export
dvb_in0_dsop : in std_logic := 'X'; -- export
dvb_in0_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
dvb_in0_dval : in std_logic := 'X'; -- export
dvb_in1_dsop : in std_logic := 'X'; -- export
dvb_in1_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
dvb_in1_dval : in std_logic := 'X'; -- export
dvb_in2_dsop : in std_logic := 'X'; -- export
dvb_in2_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
dvb_in2_dval : in std_logic := 'X'; -- export
cam_baseclk : in std_logic := 'X'; -- export
cam_mclki : out std_logic; -- export
cam_mdi : out std_logic_vector(7 downto 0); -- export
cam_mival : out std_logic; -- export
cam_mistrt : out std_logic; -- export
cam_mclko : in std_logic := 'X'; -- export
cam_mdo : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
cam_mostrt : in std_logic := 'X'; -- export
cam_moval : in std_logic := 'X'; -- export
dvb_out_dsop : out std_logic; -- export
dvb_out_dval : out std_logic; -- export
dvb_out_data : out std_logic_vector(7 downto 0) -- export
);
end component dvb_ts;
begin
dvb_ts_0 : component dvb_ts
port map (
address => address, -- avalon_slave_0.address
byteenable => byteenable, -- .byteenable
writedata => writedata, -- .writedata
write => write, -- .write
readdata => readdata, -- .readdata
read => read, -- .read
waitrequest => waitrequest, -- .waitrequest
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
interrupt => interrupt, -- conduit_end.export
cam_bypass => cam_bypass, -- .export
dvb_in0_dsop => dvb_in0_dsop, -- .export
dvb_in0_data => dvb_in0_data, -- .export
dvb_in0_dval => dvb_in0_dval, -- .export
dvb_in1_dsop => dvb_in1_dsop, -- .export
dvb_in1_data => dvb_in1_data, -- .export
dvb_in1_dval => dvb_in1_dval, -- .export
dvb_in2_dsop => dvb_in2_dsop, -- .export
dvb_in2_data => dvb_in2_data, -- .export
dvb_in2_dval => dvb_in2_dval, -- .export
cam_baseclk => cam_baseclk, -- .export
cam_mclki => cam_mclki, -- .export
cam_mdi => cam_mdi, -- .export
cam_mival => cam_mival, -- .export
cam_mistrt => cam_mistrt, -- .export
cam_mclko => cam_mclko, -- .export
cam_mdo => cam_mdo, -- .export
cam_mostrt => cam_mostrt, -- .export
cam_moval => cam_moval, -- .export
dvb_out_dsop => dvb_out_dsop, -- .export
dvb_out_dval => dvb_out_dval, -- .export
dvb_out_data => dvb_out_data -- .export
);
end architecture rtl; -- of dvb_ts_0
|
-- Copyright (c) 2015 by David Goncalves <[email protected]>
-- See LICENCE.txt for details
--
-- clock signals where syncronization and distribuion are needed
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity clock is
port (
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_6mhz : out STD_LOGIC;
decimation_clk : out STD_LOGIC
);
end clock;
architecture RTL of clock is
component dcm_6
port (
CLK_IN1 : in STD_LOGIC;
CLK_ADC : out STD_LOGIC;
DEC_CLK : out STD_LOGIC;
RESET : in STD_LOGIC
);
end component;
signal dec_clk_i : STD_LOGIC;
signal toggle : STD_LOGIC;
signal counter : integer range 0 to 42 := 0;
begin
sample_clock : dcm_6
port map(
CLK_IN1 => clk_in,
CLK_ADC => clk_6mhz,
DEC_CLK => dec_clk_i,
RESET => reset
);
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- NOTE: In addition to being a VVC for the SBI, this module is also used as a template
-- and a well commented example of the VVC structure and functionality
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.sbi_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--=================================================================================================
entity sbi_vvc is
generic (
GC_ADDR_WIDTH : integer range 1 to C_VVC_CMD_ADDR_MAX_LENGTH := 8; -- SBI address bus
GC_DATA_WIDTH : integer range 1 to C_VVC_CMD_DATA_MAX_LENGTH := 32; -- SBI data bus
GC_INSTANCE_IDX : natural := 1; -- Instance index for this SBI_VVCT instance
GC_SBI_CONFIG : t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT; -- Behavior specification for BFM
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning
);
port (
clk : in std_logic;
sbi_vvc_master_if : inout t_sbi_if := init_sbi_if_signals(GC_ADDR_WIDTH, GC_DATA_WIDTH)
);
begin
-- Check the interface widths to assure that the interface was correctly set up
assert (sbi_vvc_master_if.addr'length = GC_ADDR_WIDTH) report "sbi_vvc_master_if.addr'length =/ GC_ADDR_WIDTH" severity failure;
assert (sbi_vvc_master_if.wdata'length = GC_DATA_WIDTH) report "sbi_vvc_master_if.wdata'length =/ GC_DATA_WIDTH" severity failure;
assert (sbi_vvc_master_if.rdata'length = GC_DATA_WIDTH) report "sbi_vvc_master_if.rdata'length =/ GC_DATA_WIDTH" severity failure;
end entity sbi_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of sbi_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_sbi_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_sbi_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_sbi_transaction_info(GC_INSTANCE_IDX);
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_SBI_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, shared_vvc_cmd, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
variable v_normalised_addr : unsigned(GC_ADDR_WIDTH-1 downto 0) := (others => '0');
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Set the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
v_prev_command_was_bfm_access := v_command_is_bfm_access; -- save for inter_bfm_delay
if v_cmd.operation = WRITE or v_cmd.operation = READ or v_cmd.operation = CHECK or v_cmd.operation = POLL_UNTIL then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_prev_command_was_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when WRITE =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_write() called with to wide addrress. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "sbi_write() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_write(addr_value => v_normalised_addr,
data_value => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when READ =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_read() called with to wide addrress. " & v_cmd.msg);
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_read(addr_value => v_normalised_addr,
data_value => v_read_data(GC_DATA_WIDTH - 1 downto 0),
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data);
when CHECK =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_check() called with to wide addrress. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "sbi_check() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_check(addr_value => v_normalised_addr,
data_exp => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when POLL_UNTIL =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "sbi_poll_until() called with to wide addrress. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "sbi_poll_until() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
sbi_poll_until(addr_value => v_normalised_addr,
data_exp => v_normalised_data,
max_polls => v_cmd.max_polls,
timeout => v_cmd.timeout,
msg => format_msg(v_cmd),
clk => clk,
sbi_if => sbi_vvc_master_if,
terminate_loop => terminate_current_cmd.is_active,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
entity c_nor is
generic
(
width : integer := 1
);
port
(
input1 : std_logic_vector((width - 1) downto 0);
input2 : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_nor;
architecture behavior of c_nor is
begin
P0 : process (input1, input2)
variable result : std_logic_vector(width - 1 downto 0);
begin
outer : for n in width - 1 downto 0 loop
result(n) := input1(n) nor input2(n);
end loop outer;
output <= result;
end process P0;
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
entity c_nor is
generic
(
width : integer := 1
);
port
(
input1 : std_logic_vector((width - 1) downto 0);
input2 : std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_nor;
architecture behavior of c_nor is
begin
P0 : process (input1, input2)
variable result : std_logic_vector(width - 1 downto 0);
begin
outer : for n in width - 1 downto 0 loop
result(n) := input1(n) nor input2(n);
end loop outer;
output <= result;
end process P0;
end behavior; |
--------------------------------------------------------------------------
-- Company: Gruppo IV - Sistemi Embedded 2016-17
-- Engineer: Colella Gianni, Guida Ciro, Lombardi Daniele
--
-- Create Date: 10.05.2017 12:24:39
-- Module Name: gpio - Dataflow
-- Target Devices: Zynq Z-7010
-- Tool Versions: Vivado 2016.4
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity gpio is
Port ( pad_out : in STD_LOGIC;
pad_rw_n : in STD_LOGIC;
pad_en : in STD_LOGIC;
pad_in : out STD_LOGIC;
pad : inout STD_LOGIC);
end gpio;
architecture DataFlow of gpio is
begin
pad_in <= pad when pad_en='1' else '0';
pad <= 'Z' when pad_rw_n = '0' else pad_out and pad_en;
end DataFlow;
|
package pack is
type rec is record
x, y : natural;
end record;
type rec_array is array (natural range <>) of rec;
function rec_array_to_int (r : rec_array) return natural;
function int_to_rec_array (x : natural) return rec_array;
end package;
package body pack is
function rec_array_to_int (r : rec_array) return natural is
variable sum : natural;
begin
for i in r'range loop
sum := sum + r(i).x + r(i).y;
end loop;
return sum;
end function;
function int_to_rec_array (x : natural) return rec_array is
variable r : rec_array(1 to 3);
begin
for i in 1 to 3 loop
r(i).x := x / i;
r(i).y := x * i;
end loop;
return r;
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
port (
i1 : in rec_array(1 to 3);
i2 : in natural );
end entity;
architecture test of sub is
begin
p1: process is
begin
assert i1 = (1 to 3 => (0, 0));
assert i2 = 0;
wait for 0 ns;
assert i1 = ((10, 10), (5, 20), (3, 30));
assert i2 = 21;
wait for 2 ns;
assert i2 = 22;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack.all;
entity conv8 is
end entity;
architecture test of conv8 is
signal s1 : natural;
signal s2 : rec_array(1 to 3);
begin
uut: entity work.sub
port map (
i1 => int_to_rec_array(s1),
i2 => rec_array_to_int(s2) );
main: process is
begin
s2 <= ((1, 2), (3, 4), (5, 6));
s1 <= 10;
wait for 1 ns;
s2(2).y <= 5;
wait;
end process;
end architecture;
|
package DW_Foundation_arith is
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: delayLineBRAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY delayLineBRAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE delayLineBRAM_synth_ARCH OF delayLineBRAM_synth IS
COMPONENT delayLineBRAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(16 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 17,
READ_WIDTH => 17 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: delayLineBRAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: delayLineBRAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY delayLineBRAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE delayLineBRAM_synth_ARCH OF delayLineBRAM_synth IS
COMPONENT delayLineBRAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(16 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(16 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 17,
READ_WIDTH => 17 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: delayLineBRAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 10;
constant AMPL_WIDTH : integer := 12;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(522,AMPL_WIDTH),
conv_std_logic_vector(534,AMPL_WIDTH),
conv_std_logic_vector(546,AMPL_WIDTH),
conv_std_logic_vector(558,AMPL_WIDTH),
conv_std_logic_vector(570,AMPL_WIDTH),
conv_std_logic_vector(582,AMPL_WIDTH),
conv_std_logic_vector(594,AMPL_WIDTH),
conv_std_logic_vector(606,AMPL_WIDTH),
conv_std_logic_vector(618,AMPL_WIDTH),
conv_std_logic_vector(630,AMPL_WIDTH),
conv_std_logic_vector(642,AMPL_WIDTH),
conv_std_logic_vector(654,AMPL_WIDTH),
conv_std_logic_vector(666,AMPL_WIDTH),
conv_std_logic_vector(678,AMPL_WIDTH),
conv_std_logic_vector(690,AMPL_WIDTH),
conv_std_logic_vector(701,AMPL_WIDTH),
conv_std_logic_vector(713,AMPL_WIDTH),
conv_std_logic_vector(725,AMPL_WIDTH),
conv_std_logic_vector(737,AMPL_WIDTH),
conv_std_logic_vector(748,AMPL_WIDTH),
conv_std_logic_vector(760,AMPL_WIDTH),
conv_std_logic_vector(772,AMPL_WIDTH),
conv_std_logic_vector(783,AMPL_WIDTH),
conv_std_logic_vector(795,AMPL_WIDTH),
conv_std_logic_vector(807,AMPL_WIDTH),
conv_std_logic_vector(818,AMPL_WIDTH),
conv_std_logic_vector(830,AMPL_WIDTH),
conv_std_logic_vector(841,AMPL_WIDTH),
conv_std_logic_vector(852,AMPL_WIDTH),
conv_std_logic_vector(864,AMPL_WIDTH),
conv_std_logic_vector(875,AMPL_WIDTH),
conv_std_logic_vector(887,AMPL_WIDTH),
conv_std_logic_vector(898,AMPL_WIDTH),
conv_std_logic_vector(909,AMPL_WIDTH),
conv_std_logic_vector(920,AMPL_WIDTH),
conv_std_logic_vector(932,AMPL_WIDTH),
conv_std_logic_vector(943,AMPL_WIDTH),
conv_std_logic_vector(954,AMPL_WIDTH),
conv_std_logic_vector(965,AMPL_WIDTH),
conv_std_logic_vector(976,AMPL_WIDTH),
conv_std_logic_vector(987,AMPL_WIDTH),
conv_std_logic_vector(998,AMPL_WIDTH),
conv_std_logic_vector(1009,AMPL_WIDTH),
conv_std_logic_vector(1020,AMPL_WIDTH),
conv_std_logic_vector(1031,AMPL_WIDTH),
conv_std_logic_vector(1042,AMPL_WIDTH),
conv_std_logic_vector(1052,AMPL_WIDTH),
conv_std_logic_vector(1063,AMPL_WIDTH),
conv_std_logic_vector(1074,AMPL_WIDTH),
conv_std_logic_vector(1085,AMPL_WIDTH),
conv_std_logic_vector(1095,AMPL_WIDTH),
conv_std_logic_vector(1106,AMPL_WIDTH),
conv_std_logic_vector(1116,AMPL_WIDTH),
conv_std_logic_vector(1127,AMPL_WIDTH),
conv_std_logic_vector(1137,AMPL_WIDTH),
conv_std_logic_vector(1148,AMPL_WIDTH),
conv_std_logic_vector(1158,AMPL_WIDTH),
conv_std_logic_vector(1168,AMPL_WIDTH),
conv_std_logic_vector(1179,AMPL_WIDTH),
conv_std_logic_vector(1189,AMPL_WIDTH),
conv_std_logic_vector(1199,AMPL_WIDTH),
conv_std_logic_vector(1209,AMPL_WIDTH),
conv_std_logic_vector(1219,AMPL_WIDTH),
conv_std_logic_vector(1229,AMPL_WIDTH),
conv_std_logic_vector(1239,AMPL_WIDTH),
conv_std_logic_vector(1249,AMPL_WIDTH),
conv_std_logic_vector(1259,AMPL_WIDTH),
conv_std_logic_vector(1269,AMPL_WIDTH),
conv_std_logic_vector(1279,AMPL_WIDTH),
conv_std_logic_vector(1289,AMPL_WIDTH),
conv_std_logic_vector(1299,AMPL_WIDTH),
conv_std_logic_vector(1308,AMPL_WIDTH),
conv_std_logic_vector(1318,AMPL_WIDTH),
conv_std_logic_vector(1328,AMPL_WIDTH),
conv_std_logic_vector(1337,AMPL_WIDTH),
conv_std_logic_vector(1347,AMPL_WIDTH),
conv_std_logic_vector(1356,AMPL_WIDTH),
conv_std_logic_vector(1365,AMPL_WIDTH),
conv_std_logic_vector(1375,AMPL_WIDTH),
conv_std_logic_vector(1384,AMPL_WIDTH),
conv_std_logic_vector(1393,AMPL_WIDTH),
conv_std_logic_vector(1402,AMPL_WIDTH),
conv_std_logic_vector(1411,AMPL_WIDTH),
conv_std_logic_vector(1421,AMPL_WIDTH),
conv_std_logic_vector(1430,AMPL_WIDTH),
conv_std_logic_vector(1439,AMPL_WIDTH),
conv_std_logic_vector(1447,AMPL_WIDTH),
conv_std_logic_vector(1456,AMPL_WIDTH),
conv_std_logic_vector(1465,AMPL_WIDTH),
conv_std_logic_vector(1474,AMPL_WIDTH),
conv_std_logic_vector(1483,AMPL_WIDTH),
conv_std_logic_vector(1491,AMPL_WIDTH),
conv_std_logic_vector(1500,AMPL_WIDTH),
conv_std_logic_vector(1508,AMPL_WIDTH),
conv_std_logic_vector(1517,AMPL_WIDTH),
conv_std_logic_vector(1525,AMPL_WIDTH),
conv_std_logic_vector(1533,AMPL_WIDTH),
conv_std_logic_vector(1542,AMPL_WIDTH),
conv_std_logic_vector(1550,AMPL_WIDTH),
conv_std_logic_vector(1558,AMPL_WIDTH),
conv_std_logic_vector(1566,AMPL_WIDTH),
conv_std_logic_vector(1574,AMPL_WIDTH),
conv_std_logic_vector(1582,AMPL_WIDTH),
conv_std_logic_vector(1590,AMPL_WIDTH),
conv_std_logic_vector(1598,AMPL_WIDTH),
conv_std_logic_vector(1606,AMPL_WIDTH),
conv_std_logic_vector(1614,AMPL_WIDTH),
conv_std_logic_vector(1621,AMPL_WIDTH),
conv_std_logic_vector(1629,AMPL_WIDTH),
conv_std_logic_vector(1637,AMPL_WIDTH),
conv_std_logic_vector(1644,AMPL_WIDTH),
conv_std_logic_vector(1652,AMPL_WIDTH),
conv_std_logic_vector(1659,AMPL_WIDTH),
conv_std_logic_vector(1666,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1681,AMPL_WIDTH),
conv_std_logic_vector(1688,AMPL_WIDTH),
conv_std_logic_vector(1695,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1709,AMPL_WIDTH),
conv_std_logic_vector(1716,AMPL_WIDTH),
conv_std_logic_vector(1723,AMPL_WIDTH),
conv_std_logic_vector(1729,AMPL_WIDTH),
conv_std_logic_vector(1736,AMPL_WIDTH),
conv_std_logic_vector(1743,AMPL_WIDTH),
conv_std_logic_vector(1749,AMPL_WIDTH),
conv_std_logic_vector(1756,AMPL_WIDTH),
conv_std_logic_vector(1762,AMPL_WIDTH),
conv_std_logic_vector(1769,AMPL_WIDTH),
conv_std_logic_vector(1775,AMPL_WIDTH),
conv_std_logic_vector(1781,AMPL_WIDTH),
conv_std_logic_vector(1787,AMPL_WIDTH),
conv_std_logic_vector(1793,AMPL_WIDTH),
conv_std_logic_vector(1799,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1811,AMPL_WIDTH),
conv_std_logic_vector(1817,AMPL_WIDTH),
conv_std_logic_vector(1823,AMPL_WIDTH),
conv_std_logic_vector(1828,AMPL_WIDTH),
conv_std_logic_vector(1834,AMPL_WIDTH),
conv_std_logic_vector(1840,AMPL_WIDTH),
conv_std_logic_vector(1845,AMPL_WIDTH),
conv_std_logic_vector(1850,AMPL_WIDTH),
conv_std_logic_vector(1856,AMPL_WIDTH),
conv_std_logic_vector(1861,AMPL_WIDTH),
conv_std_logic_vector(1866,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1876,AMPL_WIDTH),
conv_std_logic_vector(1881,AMPL_WIDTH),
conv_std_logic_vector(1886,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1896,AMPL_WIDTH),
conv_std_logic_vector(1901,AMPL_WIDTH),
conv_std_logic_vector(1905,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1914,AMPL_WIDTH),
conv_std_logic_vector(1919,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 10;
constant AMPL_WIDTH : integer := 12;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(100,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(213,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(238,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(263,AMPL_WIDTH),
conv_std_logic_vector(275,AMPL_WIDTH),
conv_std_logic_vector(288,AMPL_WIDTH),
conv_std_logic_vector(300,AMPL_WIDTH),
conv_std_logic_vector(313,AMPL_WIDTH),
conv_std_logic_vector(325,AMPL_WIDTH),
conv_std_logic_vector(338,AMPL_WIDTH),
conv_std_logic_vector(350,AMPL_WIDTH),
conv_std_logic_vector(362,AMPL_WIDTH),
conv_std_logic_vector(375,AMPL_WIDTH),
conv_std_logic_vector(387,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(436,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(461,AMPL_WIDTH),
conv_std_logic_vector(473,AMPL_WIDTH),
conv_std_logic_vector(485,AMPL_WIDTH),
conv_std_logic_vector(497,AMPL_WIDTH),
conv_std_logic_vector(510,AMPL_WIDTH),
conv_std_logic_vector(522,AMPL_WIDTH),
conv_std_logic_vector(534,AMPL_WIDTH),
conv_std_logic_vector(546,AMPL_WIDTH),
conv_std_logic_vector(558,AMPL_WIDTH),
conv_std_logic_vector(570,AMPL_WIDTH),
conv_std_logic_vector(582,AMPL_WIDTH),
conv_std_logic_vector(594,AMPL_WIDTH),
conv_std_logic_vector(606,AMPL_WIDTH),
conv_std_logic_vector(618,AMPL_WIDTH),
conv_std_logic_vector(630,AMPL_WIDTH),
conv_std_logic_vector(642,AMPL_WIDTH),
conv_std_logic_vector(654,AMPL_WIDTH),
conv_std_logic_vector(666,AMPL_WIDTH),
conv_std_logic_vector(678,AMPL_WIDTH),
conv_std_logic_vector(690,AMPL_WIDTH),
conv_std_logic_vector(701,AMPL_WIDTH),
conv_std_logic_vector(713,AMPL_WIDTH),
conv_std_logic_vector(725,AMPL_WIDTH),
conv_std_logic_vector(737,AMPL_WIDTH),
conv_std_logic_vector(748,AMPL_WIDTH),
conv_std_logic_vector(760,AMPL_WIDTH),
conv_std_logic_vector(772,AMPL_WIDTH),
conv_std_logic_vector(783,AMPL_WIDTH),
conv_std_logic_vector(795,AMPL_WIDTH),
conv_std_logic_vector(807,AMPL_WIDTH),
conv_std_logic_vector(818,AMPL_WIDTH),
conv_std_logic_vector(830,AMPL_WIDTH),
conv_std_logic_vector(841,AMPL_WIDTH),
conv_std_logic_vector(852,AMPL_WIDTH),
conv_std_logic_vector(864,AMPL_WIDTH),
conv_std_logic_vector(875,AMPL_WIDTH),
conv_std_logic_vector(887,AMPL_WIDTH),
conv_std_logic_vector(898,AMPL_WIDTH),
conv_std_logic_vector(909,AMPL_WIDTH),
conv_std_logic_vector(920,AMPL_WIDTH),
conv_std_logic_vector(932,AMPL_WIDTH),
conv_std_logic_vector(943,AMPL_WIDTH),
conv_std_logic_vector(954,AMPL_WIDTH),
conv_std_logic_vector(965,AMPL_WIDTH),
conv_std_logic_vector(976,AMPL_WIDTH),
conv_std_logic_vector(987,AMPL_WIDTH),
conv_std_logic_vector(998,AMPL_WIDTH),
conv_std_logic_vector(1009,AMPL_WIDTH),
conv_std_logic_vector(1020,AMPL_WIDTH),
conv_std_logic_vector(1031,AMPL_WIDTH),
conv_std_logic_vector(1042,AMPL_WIDTH),
conv_std_logic_vector(1052,AMPL_WIDTH),
conv_std_logic_vector(1063,AMPL_WIDTH),
conv_std_logic_vector(1074,AMPL_WIDTH),
conv_std_logic_vector(1085,AMPL_WIDTH),
conv_std_logic_vector(1095,AMPL_WIDTH),
conv_std_logic_vector(1106,AMPL_WIDTH),
conv_std_logic_vector(1116,AMPL_WIDTH),
conv_std_logic_vector(1127,AMPL_WIDTH),
conv_std_logic_vector(1137,AMPL_WIDTH),
conv_std_logic_vector(1148,AMPL_WIDTH),
conv_std_logic_vector(1158,AMPL_WIDTH),
conv_std_logic_vector(1168,AMPL_WIDTH),
conv_std_logic_vector(1179,AMPL_WIDTH),
conv_std_logic_vector(1189,AMPL_WIDTH),
conv_std_logic_vector(1199,AMPL_WIDTH),
conv_std_logic_vector(1209,AMPL_WIDTH),
conv_std_logic_vector(1219,AMPL_WIDTH),
conv_std_logic_vector(1229,AMPL_WIDTH),
conv_std_logic_vector(1239,AMPL_WIDTH),
conv_std_logic_vector(1249,AMPL_WIDTH),
conv_std_logic_vector(1259,AMPL_WIDTH),
conv_std_logic_vector(1269,AMPL_WIDTH),
conv_std_logic_vector(1279,AMPL_WIDTH),
conv_std_logic_vector(1289,AMPL_WIDTH),
conv_std_logic_vector(1299,AMPL_WIDTH),
conv_std_logic_vector(1308,AMPL_WIDTH),
conv_std_logic_vector(1318,AMPL_WIDTH),
conv_std_logic_vector(1328,AMPL_WIDTH),
conv_std_logic_vector(1337,AMPL_WIDTH),
conv_std_logic_vector(1347,AMPL_WIDTH),
conv_std_logic_vector(1356,AMPL_WIDTH),
conv_std_logic_vector(1365,AMPL_WIDTH),
conv_std_logic_vector(1375,AMPL_WIDTH),
conv_std_logic_vector(1384,AMPL_WIDTH),
conv_std_logic_vector(1393,AMPL_WIDTH),
conv_std_logic_vector(1402,AMPL_WIDTH),
conv_std_logic_vector(1411,AMPL_WIDTH),
conv_std_logic_vector(1421,AMPL_WIDTH),
conv_std_logic_vector(1430,AMPL_WIDTH),
conv_std_logic_vector(1439,AMPL_WIDTH),
conv_std_logic_vector(1447,AMPL_WIDTH),
conv_std_logic_vector(1456,AMPL_WIDTH),
conv_std_logic_vector(1465,AMPL_WIDTH),
conv_std_logic_vector(1474,AMPL_WIDTH),
conv_std_logic_vector(1483,AMPL_WIDTH),
conv_std_logic_vector(1491,AMPL_WIDTH),
conv_std_logic_vector(1500,AMPL_WIDTH),
conv_std_logic_vector(1508,AMPL_WIDTH),
conv_std_logic_vector(1517,AMPL_WIDTH),
conv_std_logic_vector(1525,AMPL_WIDTH),
conv_std_logic_vector(1533,AMPL_WIDTH),
conv_std_logic_vector(1542,AMPL_WIDTH),
conv_std_logic_vector(1550,AMPL_WIDTH),
conv_std_logic_vector(1558,AMPL_WIDTH),
conv_std_logic_vector(1566,AMPL_WIDTH),
conv_std_logic_vector(1574,AMPL_WIDTH),
conv_std_logic_vector(1582,AMPL_WIDTH),
conv_std_logic_vector(1590,AMPL_WIDTH),
conv_std_logic_vector(1598,AMPL_WIDTH),
conv_std_logic_vector(1606,AMPL_WIDTH),
conv_std_logic_vector(1614,AMPL_WIDTH),
conv_std_logic_vector(1621,AMPL_WIDTH),
conv_std_logic_vector(1629,AMPL_WIDTH),
conv_std_logic_vector(1637,AMPL_WIDTH),
conv_std_logic_vector(1644,AMPL_WIDTH),
conv_std_logic_vector(1652,AMPL_WIDTH),
conv_std_logic_vector(1659,AMPL_WIDTH),
conv_std_logic_vector(1666,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1681,AMPL_WIDTH),
conv_std_logic_vector(1688,AMPL_WIDTH),
conv_std_logic_vector(1695,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1709,AMPL_WIDTH),
conv_std_logic_vector(1716,AMPL_WIDTH),
conv_std_logic_vector(1723,AMPL_WIDTH),
conv_std_logic_vector(1729,AMPL_WIDTH),
conv_std_logic_vector(1736,AMPL_WIDTH),
conv_std_logic_vector(1743,AMPL_WIDTH),
conv_std_logic_vector(1749,AMPL_WIDTH),
conv_std_logic_vector(1756,AMPL_WIDTH),
conv_std_logic_vector(1762,AMPL_WIDTH),
conv_std_logic_vector(1769,AMPL_WIDTH),
conv_std_logic_vector(1775,AMPL_WIDTH),
conv_std_logic_vector(1781,AMPL_WIDTH),
conv_std_logic_vector(1787,AMPL_WIDTH),
conv_std_logic_vector(1793,AMPL_WIDTH),
conv_std_logic_vector(1799,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1811,AMPL_WIDTH),
conv_std_logic_vector(1817,AMPL_WIDTH),
conv_std_logic_vector(1823,AMPL_WIDTH),
conv_std_logic_vector(1828,AMPL_WIDTH),
conv_std_logic_vector(1834,AMPL_WIDTH),
conv_std_logic_vector(1840,AMPL_WIDTH),
conv_std_logic_vector(1845,AMPL_WIDTH),
conv_std_logic_vector(1850,AMPL_WIDTH),
conv_std_logic_vector(1856,AMPL_WIDTH),
conv_std_logic_vector(1861,AMPL_WIDTH),
conv_std_logic_vector(1866,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1876,AMPL_WIDTH),
conv_std_logic_vector(1881,AMPL_WIDTH),
conv_std_logic_vector(1886,AMPL_WIDTH),
conv_std_logic_vector(1891,AMPL_WIDTH),
conv_std_logic_vector(1896,AMPL_WIDTH),
conv_std_logic_vector(1901,AMPL_WIDTH),
conv_std_logic_vector(1905,AMPL_WIDTH),
conv_std_logic_vector(1910,AMPL_WIDTH),
conv_std_logic_vector(1914,AMPL_WIDTH),
conv_std_logic_vector(1919,AMPL_WIDTH),
conv_std_logic_vector(1923,AMPL_WIDTH),
conv_std_logic_vector(1927,AMPL_WIDTH),
conv_std_logic_vector(1932,AMPL_WIDTH),
conv_std_logic_vector(1936,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1944,AMPL_WIDTH),
conv_std_logic_vector(1948,AMPL_WIDTH),
conv_std_logic_vector(1951,AMPL_WIDTH),
conv_std_logic_vector(1955,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1966,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1973,AMPL_WIDTH),
conv_std_logic_vector(1976,AMPL_WIDTH),
conv_std_logic_vector(1979,AMPL_WIDTH),
conv_std_logic_vector(1983,AMPL_WIDTH),
conv_std_logic_vector(1986,AMPL_WIDTH),
conv_std_logic_vector(1989,AMPL_WIDTH),
conv_std_logic_vector(1992,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2005,AMPL_WIDTH),
conv_std_logic_vector(2008,AMPL_WIDTH),
conv_std_logic_vector(2010,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2015,AMPL_WIDTH),
conv_std_logic_vector(2017,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2021,AMPL_WIDTH),
conv_std_logic_vector(2023,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2027,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2030,AMPL_WIDTH),
conv_std_logic_vector(2032,AMPL_WIDTH),
conv_std_logic_vector(2033,AMPL_WIDTH),
conv_std_logic_vector(2035,AMPL_WIDTH),
conv_std_logic_vector(2036,AMPL_WIDTH),
conv_std_logic_vector(2037,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2039,AMPL_WIDTH),
conv_std_logic_vector(2040,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2042,AMPL_WIDTH),
conv_std_logic_vector(2043,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2045,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2046,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_srvr.vhd,v 1.5 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.5 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use qsim.qsim_types.all, random.random.all;
entity server is
generic ( name : string;
distribution : distribution_type;
mean_service_time : time;
seed : seed_type;
time_unit : delay_length := ns;
info_file_name : string := "info_file.dat" );
port ( in_arc : in arc_type;
in_ready : out boolean;
out_arc : out arc_type;
info_detail : in info_detail_type );
end entity server;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_srvr.vhd,v 1.5 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.5 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use qsim.qsim_types.all, random.random.all;
entity server is
generic ( name : string;
distribution : distribution_type;
mean_service_time : time;
seed : seed_type;
time_unit : delay_length := ns;
info_file_name : string := "info_file.dat" );
port ( in_arc : in arc_type;
in_ready : out boolean;
out_arc : out arc_type;
info_detail : in info_detail_type );
end entity server;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_srvr.vhd,v 1.5 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.5 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use qsim.qsim_types.all, random.random.all;
entity server is
generic ( name : string;
distribution : distribution_type;
mean_service_time : time;
seed : seed_type;
time_unit : delay_length := ns;
info_file_name : string := "info_file.dat" );
port ( in_arc : in arc_type;
in_ready : out boolean;
out_arc : out arc_type;
info_detail : in info_detail_type );
end entity server;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
-- Title : Flat Memory Model package
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This package implements a memory model that can be used
-- as or in bus functional models. It implements different
-- banks, such that only one package is needed for all memories
-- in the whole project. These banks are dynamic, just like
-- the contents of the memories. Internally, this memory model
-- is 32-bit, but can be accessed by means of functions and
-- procedures that exist in various widths.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
use work.tl_string_util_pkg.all;
package tl_flat_memory_model_pkg is
constant c_fm_max_bank : integer := 255;
constant c_fm_max_sector : integer := 65535;
constant c_fm_sector_size : integer := 16384;
subtype t_byte is std_logic_vector(7 downto 0);
type flat_mem_sector_t is array(0 to c_fm_sector_size-1) of integer; -- each sector is 64kB
type flat_mem_sector_p is access flat_mem_sector_t;
type flat_mem_bank_t is array(0 to c_fm_max_sector) of flat_mem_sector_p; -- there are 64k sectors (4 GB)
type flat_mem_bank_p is access flat_mem_bank_t;
-- we need to use a handle rather than a pointer, because we can't pass pointers in function calls
-- Hence, we don't use a linked list, but an array.
type flat_mem_object_t is record
path : string(1 to 256);
name : string(1 to 128);
bank : flat_mem_bank_p;
end record;
type flat_mem_object_p is access flat_mem_object_t;
type flat_mem_array_t is array(1 to c_fm_max_bank) of flat_mem_object_p;
subtype h_mem_object is integer range 0 to c_fm_max_bank;
---------------------------------------------------------------------------
shared variable flat_memories : flat_mem_array_t := (others => null);
---------------------------------------------------------------------------
procedure register_mem_model(
path : string;
named : string;
variable handle : out h_mem_object);
procedure bind_mem_model (
named : string;
variable handle : out h_mem_object);
---------------------------------------------------------------------------
-- Low level calls
impure function read_memory(
bank : integer;
sector : integer;
entry : integer)
return integer;
procedure write_memory(
bank : integer;
sector : integer;
entry : integer;
data : integer);
procedure clear_memory(
bank : integer);
procedure clean_up;
-- 32-bit address/data access calls
impure function read_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0));
procedure write_memory_be(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0));
-- 16-bit address/data access calls
impure function read_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(15 downto 0));
-- 8-bit address/data access calls
impure function read_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(7 downto 0));
-- integer direct access calls
impure function read_memory_int(
bank : integer;
address : integer )
return integer;
procedure write_memory_int(
bank : integer;
address : integer;
data : integer );
-- File Access Procedures
procedure load_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0));
procedure save_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer);
procedure load_memory_hex(
filename : string;
bank : integer);
procedure save_memory_hex(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer);
end package;
package body tl_flat_memory_model_pkg is
-- Memory model module registration into array
procedure register_mem_model(
path : string;
named : string;
variable handle : out h_mem_object) is
begin
handle := 0;
L1 : for i in flat_memories'range loop
if flat_memories(i) = null then
-- report "my name is "& named;
handle := i;
flat_memories(i) := new flat_mem_object_t;
flat_memories(i).path(path'range) := path;
flat_memories(i).name(named'range) := named;
flat_memories(i).bank := new flat_mem_bank_t;
exit L1;
end if;
end loop;
end procedure register_mem_model;
-- Memory model module binding
procedure bind_mem_model (
named : string;
variable handle : out h_mem_object) is
begin
handle := 0;
wait for 1 ns;
L1 : for i in flat_memories'range loop
if flat_memories(i) /= null then
if flat_memories(i).name(named'range) = named or
flat_memories(i).path(named'range) = named then
handle := i;
return;
end if;
end if;
end loop;
report "Can't find memory model '"&named&"'."
severity failure;
end procedure bind_mem_model;
-- Base calls
impure function read_memory(
bank : integer;
sector : integer;
entry : integer) return integer is
begin
if flat_memories(bank) = null then
return 0;
end if;
if flat_memories(bank).bank(sector) = null then
return 0;
end if;
return flat_memories(bank).bank(sector).all(entry);
end function read_memory;
procedure write_memory(
bank : integer;
sector : integer;
entry : integer;
data : integer) is
begin
if flat_memories(bank) = null then
flat_memories(bank) := new flat_mem_object_t;
flat_memories(bank).bank(0 to c_fm_max_sector) := (others => null);
end if;
if flat_memories(bank).bank(sector) = null then
flat_memories(bank).bank(sector) := new flat_mem_sector_t;
flat_memories(bank).bank(sector).all(0 to c_fm_sector_size-1) := (others => 0);
end if;
flat_memories(bank).bank(sector).all(entry) := data;
end procedure write_memory;
procedure clear_memory(bank : integer) is
begin
if flat_memories(bank) /= null then
for i in flat_memories(bank).bank'range loop
if flat_memories(bank).bank(i) /= null then
deallocate(flat_memories(bank).bank(i));
end if;
end loop;
deallocate(flat_memories(bank));
flat_memories(bank) := null;
end if;
end procedure clear_memory;
procedure clean_up is
begin
for i in flat_memories'range loop
clear_memory(i);
end loop;
end procedure clean_up;
-- 32-bit address/data access calls
impure function read_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
return std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
end function read_memory_32;
procedure write_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0))
is
variable sector_idx : integer;
variable entry_idx : integer;
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
write_memory(bank, sector_idx, entry_idx, to_integer(signed(data)));
end procedure write_memory_32;
procedure write_memory_be(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0))
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
variable L : line;
begin
--write_s(L, "Writing " & vec_to_hex(data, 8) & " to location " & vec_to_hex(address, 8));
--writeline(output, L);
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
for i in be'range loop
if to_x01(be(i)) = '1' then
read_data(7+8*i downto 8*i) := data(7+8*i downto 8*i);
end if;
end loop;
write_memory(bank, sector_idx, entry_idx, to_integer(signed(read_data)));
end procedure write_memory_be;
-- 16-bit address/data access calls
impure function read_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
if address(1) = '0' then
return read_data(15 downto 0);
else
return read_data(31 downto 16);
end if;
end function read_memory_16;
procedure write_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(15 downto 0))
is
variable be_temp : std_logic_vector(3 downto 0);
variable write_data : std_logic_vector(31 downto 0);
begin
write_data := data & data;
be_temp := address(1) & address(1) & not address(1) & not address(1);
write_memory_be(bank, address, write_data, be_temp);
end procedure write_memory_16;
-- 8-bit address/data access calls
impure function read_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
case address(1 downto 0) is
when "11" =>
return read_data(31 downto 24);
when "01" =>
return read_data(15 downto 8);
when "10" =>
return read_data(23 downto 16);
when others =>
return read_data(7 downto 0);
end case;
end function read_memory_8;
procedure write_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(7 downto 0))
is
variable be_temp : std_logic_vector(3 downto 0) := (others => '0');
variable write_data : std_logic_vector(31 downto 0);
begin
write_data := data & data & data & data;
be_temp(to_integer(unsigned(address(1 downto 0)))) := '1';
write_memory_be(bank, address, write_data, be_temp);
end procedure write_memory_8;
-- Integer direct procedures
impure function read_memory_int(
bank : integer;
address : integer )
return integer is
variable sect, index : integer;
begin
sect := address / c_fm_sector_size;
index := address mod c_fm_sector_size;
return read_memory(bank, sect, index);
end function read_memory_int;
procedure write_memory_int(
bank : integer;
address : integer;
data : integer ) is
variable sect, index : integer;
begin
sect := address / c_fm_sector_size;
index := address mod c_fm_sector_size;
write_memory(bank, sect, index, data);
end procedure write_memory_int;
-- File access procedures
-- not a public procedure.
procedure read_binary_file(
file myfile : t_binary_file;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
variable myrec : inout t_binary_file_rec)
is
variable addr : unsigned(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable i : integer;
variable sector_idx : integer;
variable entry_idx : integer;
begin
addr := unsigned(startaddr);
if startaddr(1 downto 0) = "00" then
sector_idx := to_integer(addr(31 downto 16));
entry_idx := to_integer(addr(15 downto 2));
aligned : while true loop
if EndFile(myfile) then
exit aligned;
end if;
read(myfile, i);
write_memory(bank, sector_idx, entry_idx, i);
if entry_idx = c_fm_sector_size-1 then
entry_idx := 0;
if sector_idx = c_fm_max_sector then
sector_idx := 0;
else
sector_idx := sector_idx + 1;
end if;
else
entry_idx := entry_idx + 1;
end if;
end loop;
else
unaligned : while true loop
if EndFile(myfile) and myrec.Offset = 0 then
exit unaligned;
end if;
read_byte(myfile, data, myrec);
write_memory_8(bank, std_logic_vector(addr), data);
addr := addr + 1;
end loop;
end if;
end read_binary_file;
-- not a public procedure
procedure read_hex_file (
file myfile : text;
bank : integer)
is
variable L : line;
variable addr : unsigned(31 downto 0) := (others => '0');
variable c : character;
variable data : t_byte;
variable sum : unsigned(7 downto 0);
variable rectype : t_byte;
variable tmp_addr : std_logic_vector(15 downto 0);
variable fileend : boolean;
variable linenr : integer := 0;
variable len : integer;
begin
outer : while true loop
if EndFile(myfile) then
report "Missing end of file record."
severity warning;
return;
end if;
-- search for lines starting with ':'
start : while true loop
readline(myfile, L);
linenr := linenr + 1;
read(L, c);
if c = ':' then
exit start;
end if;
end loop;
-- parse the rest of the line
sum := X"00";
get_byte_from_file(myfile, L, fileend, data);
len := to_integer(unsigned(data));
get_byte_from_file(myfile, L, fileend, tmp_addr(15 downto 8));
get_byte_from_file(myfile, L, fileend, tmp_addr(7 downto 0));
get_byte_from_file(myfile, L, fileend, rectype);
sum := sum - (unsigned(data) + unsigned(tmp_addr(15 downto 8)) + unsigned(tmp_addr(7 downto 0)) + unsigned(rectype));
case rectype is
when X"00" => -- data record
addr(15 downto 0) := unsigned(tmp_addr);
for i in 0 to len-1 loop
get_byte_from_file(myfile, L, fileend, data);
sum := sum - unsigned(data);
write_memory_8(bank, std_logic_vector(addr), data);
addr := addr + 1;
end loop;
when X"01" => -- end of file record
return;
when X"04" => -- extended linear address record
get_byte_from_file(myfile, L, fileend, data);
addr(31 downto 24) := unsigned(data);
sum := sum - addr(31 downto 24);
get_byte_from_file(myfile, L, fileend, data);
addr(23 downto 16) := unsigned(data);
sum := sum - addr(23 downto 16);
when others =>
report "Unexpected record type " & vec_to_hex(rectype, 2)
severity warning;
return;
end case;
-- check checksum
get_byte_from_file(myfile, L, fileend, data);
assert sum = unsigned(data)
report "Warning: Checksum incorrect at line: " & integer'image(linenr)
severity warning;
end loop;
end read_hex_file;
-- public procedure:
procedure load_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0))
is
variable stat : file_open_status;
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
begin
-- open file
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
init_record(myrec);
read_binary_file (myfile, bank, address, myrec);
file_close(myfile);
end load_memory;
-- public procedure:
procedure load_memory_hex(
filename : string;
bank : integer)
is
variable stat : file_open_status;
file myfile : text;
begin
-- open file
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file (myfile, bank);
file_close(myfile);
end load_memory_hex;
-- not a public procedure.
procedure write_binary_file(
file myfile : t_binary_file;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
length : integer;
variable myrec : inout t_binary_file_rec)
is
variable addr : unsigned(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable i : integer;
variable sector_idx : integer;
variable entry_idx : integer;
variable remaining : integer;
begin
addr := unsigned(startaddr);
if startaddr(1 downto 0) = "00" then
sector_idx := to_integer(addr(31 downto 16));
entry_idx := to_integer(addr(15 downto 2));
remaining := (length + 3) / 4;
aligned : while remaining > 0 loop
i := read_memory(bank, sector_idx, entry_idx);
write(myfile, i);
remaining := remaining - 1;
if entry_idx = c_fm_sector_size-1 then
if sector_idx = c_fm_max_sector then
sector_idx := 0;
else
sector_idx := sector_idx + 1;
end if;
else
entry_idx := entry_idx + 1;
end if;
end loop;
else
remaining := length;
unaligned : while remaining > 0 loop
data := read_memory_8(bank, std_logic_vector(addr));
write_byte(myfile, data, myrec);
addr := addr + 1;
remaining := remaining - 1;
end loop;
purge(myfile, myrec);
end if;
end write_binary_file;
-- not a public procedure.
procedure write_hex_file(
file myfile : text;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
length : integer)
is
variable addr : std_logic_vector(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable sector_idx : integer;
variable entry_idx : integer;
variable remaining : integer;
variable maxlen : integer;
variable sum : unsigned(7 downto 0);
variable L : line;
variable prev_hi : std_logic_vector(31 downto 16) := (others => '-');
begin
addr := startaddr;
remaining := length;
unaligned : while remaining > 0 loop
-- check if we need to write a new extended address record
if addr(31 downto 16) /= prev_hi then
write_string(L, ":02000004");
write(L, vec_to_hex(addr(31 downto 16), 4));
write(L, vec_to_hex(std_logic_vector(X"FA" - unsigned(addr(31 downto 24)) - unsigned(addr(23 downto 16))), 2));
writeline(myfile, L);
prev_hi := addr(31 downto 16);
end if;
-- check for maximum length (until 64k boundary)
maxlen := to_integer(X"10000" - unsigned(X"0" & addr(15 downto 0)));
if maxlen > 16 then maxlen := 16; end if;
-- create data record
sum := X"00";
write(L, ':');
write(L, vec_to_hex(std_logic_vector(to_unsigned(maxlen, 8)), 2));
write(L, vec_to_hex(addr(15 downto 0), 4));
write_string(L, "00");
sum := sum - maxlen;
sum := sum - unsigned(addr(15 downto 8));
sum := sum - unsigned(addr(7 downto 0));
for i in 1 to maxlen loop
data := read_memory_8(bank, addr);
sum := sum - unsigned(data);
write(L, vec_to_hex(data, 2));
addr := std_logic_vector(unsigned(addr) + 1);
end loop;
remaining := remaining - maxlen;
write(L, vec_to_hex(std_logic_vector(sum), 2));
writeline(myfile, L);
end loop;
write_string(L, ":00000001");
writeline(myfile, L);
end write_hex_file;
-- public procedure:
procedure save_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer)
is
variable stat : file_open_status;
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
begin
-- open file
file_open(stat, myfile, filename, write_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for writing."
severity failure;
init_record(myrec);
write_binary_file (myfile, bank, address, length, myrec);
file_close(myfile);
end save_memory;
-- public procedure:
procedure save_memory_hex(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer)
is
variable stat : file_open_status;
file myfile : text;
begin
-- open file
file_open(stat, myfile, filename, write_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for writing."
severity failure;
write_hex_file (myfile, bank, address, length);
file_close(myfile);
end save_memory_hex;
end;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
-- Title : Flat Memory Model package
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This package implements a memory model that can be used
-- as or in bus functional models. It implements different
-- banks, such that only one package is needed for all memories
-- in the whole project. These banks are dynamic, just like
-- the contents of the memories. Internally, this memory model
-- is 32-bit, but can be accessed by means of functions and
-- procedures that exist in various widths.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
use work.tl_string_util_pkg.all;
package tl_flat_memory_model_pkg is
constant c_fm_max_bank : integer := 255;
constant c_fm_max_sector : integer := 65535;
constant c_fm_sector_size : integer := 16384;
subtype t_byte is std_logic_vector(7 downto 0);
type flat_mem_sector_t is array(0 to c_fm_sector_size-1) of integer; -- each sector is 64kB
type flat_mem_sector_p is access flat_mem_sector_t;
type flat_mem_bank_t is array(0 to c_fm_max_sector) of flat_mem_sector_p; -- there are 64k sectors (4 GB)
type flat_mem_bank_p is access flat_mem_bank_t;
-- we need to use a handle rather than a pointer, because we can't pass pointers in function calls
-- Hence, we don't use a linked list, but an array.
type flat_mem_object_t is record
path : string(1 to 256);
name : string(1 to 128);
bank : flat_mem_bank_p;
end record;
type flat_mem_object_p is access flat_mem_object_t;
type flat_mem_array_t is array(1 to c_fm_max_bank) of flat_mem_object_p;
subtype h_mem_object is integer range 0 to c_fm_max_bank;
---------------------------------------------------------------------------
shared variable flat_memories : flat_mem_array_t := (others => null);
---------------------------------------------------------------------------
procedure register_mem_model(
path : string;
named : string;
variable handle : out h_mem_object);
procedure bind_mem_model (
named : string;
variable handle : out h_mem_object);
---------------------------------------------------------------------------
-- Low level calls
impure function read_memory(
bank : integer;
sector : integer;
entry : integer)
return integer;
procedure write_memory(
bank : integer;
sector : integer;
entry : integer;
data : integer);
procedure clear_memory(
bank : integer);
procedure clean_up;
-- 32-bit address/data access calls
impure function read_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0));
procedure write_memory_be(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0));
-- 16-bit address/data access calls
impure function read_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(15 downto 0));
-- 8-bit address/data access calls
impure function read_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(7 downto 0));
-- integer direct access calls
impure function read_memory_int(
bank : integer;
address : integer )
return integer;
procedure write_memory_int(
bank : integer;
address : integer;
data : integer );
-- File Access Procedures
procedure load_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0));
procedure save_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer);
procedure load_memory_hex(
filename : string;
bank : integer);
procedure save_memory_hex(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer);
end package;
package body tl_flat_memory_model_pkg is
-- Memory model module registration into array
procedure register_mem_model(
path : string;
named : string;
variable handle : out h_mem_object) is
begin
handle := 0;
L1 : for i in flat_memories'range loop
if flat_memories(i) = null then
-- report "my name is "& named;
handle := i;
flat_memories(i) := new flat_mem_object_t;
flat_memories(i).path(path'range) := path;
flat_memories(i).name(named'range) := named;
flat_memories(i).bank := new flat_mem_bank_t;
exit L1;
end if;
end loop;
end procedure register_mem_model;
-- Memory model module binding
procedure bind_mem_model (
named : string;
variable handle : out h_mem_object) is
begin
handle := 0;
wait for 1 ns;
L1 : for i in flat_memories'range loop
if flat_memories(i) /= null then
if flat_memories(i).name(named'range) = named or
flat_memories(i).path(named'range) = named then
handle := i;
return;
end if;
end if;
end loop;
report "Can't find memory model '"&named&"'."
severity failure;
end procedure bind_mem_model;
-- Base calls
impure function read_memory(
bank : integer;
sector : integer;
entry : integer) return integer is
begin
if flat_memories(bank) = null then
return 0;
end if;
if flat_memories(bank).bank(sector) = null then
return 0;
end if;
return flat_memories(bank).bank(sector).all(entry);
end function read_memory;
procedure write_memory(
bank : integer;
sector : integer;
entry : integer;
data : integer) is
begin
if flat_memories(bank) = null then
flat_memories(bank) := new flat_mem_object_t;
flat_memories(bank).bank(0 to c_fm_max_sector) := (others => null);
end if;
if flat_memories(bank).bank(sector) = null then
flat_memories(bank).bank(sector) := new flat_mem_sector_t;
flat_memories(bank).bank(sector).all(0 to c_fm_sector_size-1) := (others => 0);
end if;
flat_memories(bank).bank(sector).all(entry) := data;
end procedure write_memory;
procedure clear_memory(bank : integer) is
begin
if flat_memories(bank) /= null then
for i in flat_memories(bank).bank'range loop
if flat_memories(bank).bank(i) /= null then
deallocate(flat_memories(bank).bank(i));
end if;
end loop;
deallocate(flat_memories(bank));
flat_memories(bank) := null;
end if;
end procedure clear_memory;
procedure clean_up is
begin
for i in flat_memories'range loop
clear_memory(i);
end loop;
end procedure clean_up;
-- 32-bit address/data access calls
impure function read_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
return std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
end function read_memory_32;
procedure write_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0))
is
variable sector_idx : integer;
variable entry_idx : integer;
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
write_memory(bank, sector_idx, entry_idx, to_integer(signed(data)));
end procedure write_memory_32;
procedure write_memory_be(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0))
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
variable L : line;
begin
--write_s(L, "Writing " & vec_to_hex(data, 8) & " to location " & vec_to_hex(address, 8));
--writeline(output, L);
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
for i in be'range loop
if to_x01(be(i)) = '1' then
read_data(7+8*i downto 8*i) := data(7+8*i downto 8*i);
end if;
end loop;
write_memory(bank, sector_idx, entry_idx, to_integer(signed(read_data)));
end procedure write_memory_be;
-- 16-bit address/data access calls
impure function read_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
if address(1) = '0' then
return read_data(15 downto 0);
else
return read_data(31 downto 16);
end if;
end function read_memory_16;
procedure write_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(15 downto 0))
is
variable be_temp : std_logic_vector(3 downto 0);
variable write_data : std_logic_vector(31 downto 0);
begin
write_data := data & data;
be_temp := address(1) & address(1) & not address(1) & not address(1);
write_memory_be(bank, address, write_data, be_temp);
end procedure write_memory_16;
-- 8-bit address/data access calls
impure function read_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
case address(1 downto 0) is
when "11" =>
return read_data(31 downto 24);
when "01" =>
return read_data(15 downto 8);
when "10" =>
return read_data(23 downto 16);
when others =>
return read_data(7 downto 0);
end case;
end function read_memory_8;
procedure write_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(7 downto 0))
is
variable be_temp : std_logic_vector(3 downto 0) := (others => '0');
variable write_data : std_logic_vector(31 downto 0);
begin
write_data := data & data & data & data;
be_temp(to_integer(unsigned(address(1 downto 0)))) := '1';
write_memory_be(bank, address, write_data, be_temp);
end procedure write_memory_8;
-- Integer direct procedures
impure function read_memory_int(
bank : integer;
address : integer )
return integer is
variable sect, index : integer;
begin
sect := address / c_fm_sector_size;
index := address mod c_fm_sector_size;
return read_memory(bank, sect, index);
end function read_memory_int;
procedure write_memory_int(
bank : integer;
address : integer;
data : integer ) is
variable sect, index : integer;
begin
sect := address / c_fm_sector_size;
index := address mod c_fm_sector_size;
write_memory(bank, sect, index, data);
end procedure write_memory_int;
-- File access procedures
-- not a public procedure.
procedure read_binary_file(
file myfile : t_binary_file;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
variable myrec : inout t_binary_file_rec)
is
variable addr : unsigned(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable i : integer;
variable sector_idx : integer;
variable entry_idx : integer;
begin
addr := unsigned(startaddr);
if startaddr(1 downto 0) = "00" then
sector_idx := to_integer(addr(31 downto 16));
entry_idx := to_integer(addr(15 downto 2));
aligned : while true loop
if EndFile(myfile) then
exit aligned;
end if;
read(myfile, i);
write_memory(bank, sector_idx, entry_idx, i);
if entry_idx = c_fm_sector_size-1 then
entry_idx := 0;
if sector_idx = c_fm_max_sector then
sector_idx := 0;
else
sector_idx := sector_idx + 1;
end if;
else
entry_idx := entry_idx + 1;
end if;
end loop;
else
unaligned : while true loop
if EndFile(myfile) and myrec.Offset = 0 then
exit unaligned;
end if;
read_byte(myfile, data, myrec);
write_memory_8(bank, std_logic_vector(addr), data);
addr := addr + 1;
end loop;
end if;
end read_binary_file;
-- not a public procedure
procedure read_hex_file (
file myfile : text;
bank : integer)
is
variable L : line;
variable addr : unsigned(31 downto 0) := (others => '0');
variable c : character;
variable data : t_byte;
variable sum : unsigned(7 downto 0);
variable rectype : t_byte;
variable tmp_addr : std_logic_vector(15 downto 0);
variable fileend : boolean;
variable linenr : integer := 0;
variable len : integer;
begin
outer : while true loop
if EndFile(myfile) then
report "Missing end of file record."
severity warning;
return;
end if;
-- search for lines starting with ':'
start : while true loop
readline(myfile, L);
linenr := linenr + 1;
read(L, c);
if c = ':' then
exit start;
end if;
end loop;
-- parse the rest of the line
sum := X"00";
get_byte_from_file(myfile, L, fileend, data);
len := to_integer(unsigned(data));
get_byte_from_file(myfile, L, fileend, tmp_addr(15 downto 8));
get_byte_from_file(myfile, L, fileend, tmp_addr(7 downto 0));
get_byte_from_file(myfile, L, fileend, rectype);
sum := sum - (unsigned(data) + unsigned(tmp_addr(15 downto 8)) + unsigned(tmp_addr(7 downto 0)) + unsigned(rectype));
case rectype is
when X"00" => -- data record
addr(15 downto 0) := unsigned(tmp_addr);
for i in 0 to len-1 loop
get_byte_from_file(myfile, L, fileend, data);
sum := sum - unsigned(data);
write_memory_8(bank, std_logic_vector(addr), data);
addr := addr + 1;
end loop;
when X"01" => -- end of file record
return;
when X"04" => -- extended linear address record
get_byte_from_file(myfile, L, fileend, data);
addr(31 downto 24) := unsigned(data);
sum := sum - addr(31 downto 24);
get_byte_from_file(myfile, L, fileend, data);
addr(23 downto 16) := unsigned(data);
sum := sum - addr(23 downto 16);
when others =>
report "Unexpected record type " & vec_to_hex(rectype, 2)
severity warning;
return;
end case;
-- check checksum
get_byte_from_file(myfile, L, fileend, data);
assert sum = unsigned(data)
report "Warning: Checksum incorrect at line: " & integer'image(linenr)
severity warning;
end loop;
end read_hex_file;
-- public procedure:
procedure load_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0))
is
variable stat : file_open_status;
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
begin
-- open file
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
init_record(myrec);
read_binary_file (myfile, bank, address, myrec);
file_close(myfile);
end load_memory;
-- public procedure:
procedure load_memory_hex(
filename : string;
bank : integer)
is
variable stat : file_open_status;
file myfile : text;
begin
-- open file
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file (myfile, bank);
file_close(myfile);
end load_memory_hex;
-- not a public procedure.
procedure write_binary_file(
file myfile : t_binary_file;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
length : integer;
variable myrec : inout t_binary_file_rec)
is
variable addr : unsigned(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable i : integer;
variable sector_idx : integer;
variable entry_idx : integer;
variable remaining : integer;
begin
addr := unsigned(startaddr);
if startaddr(1 downto 0) = "00" then
sector_idx := to_integer(addr(31 downto 16));
entry_idx := to_integer(addr(15 downto 2));
remaining := (length + 3) / 4;
aligned : while remaining > 0 loop
i := read_memory(bank, sector_idx, entry_idx);
write(myfile, i);
remaining := remaining - 1;
if entry_idx = c_fm_sector_size-1 then
if sector_idx = c_fm_max_sector then
sector_idx := 0;
else
sector_idx := sector_idx + 1;
end if;
else
entry_idx := entry_idx + 1;
end if;
end loop;
else
remaining := length;
unaligned : while remaining > 0 loop
data := read_memory_8(bank, std_logic_vector(addr));
write_byte(myfile, data, myrec);
addr := addr + 1;
remaining := remaining - 1;
end loop;
purge(myfile, myrec);
end if;
end write_binary_file;
-- not a public procedure.
procedure write_hex_file(
file myfile : text;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
length : integer)
is
variable addr : std_logic_vector(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable sector_idx : integer;
variable entry_idx : integer;
variable remaining : integer;
variable maxlen : integer;
variable sum : unsigned(7 downto 0);
variable L : line;
variable prev_hi : std_logic_vector(31 downto 16) := (others => '-');
begin
addr := startaddr;
remaining := length;
unaligned : while remaining > 0 loop
-- check if we need to write a new extended address record
if addr(31 downto 16) /= prev_hi then
write_string(L, ":02000004");
write(L, vec_to_hex(addr(31 downto 16), 4));
write(L, vec_to_hex(std_logic_vector(X"FA" - unsigned(addr(31 downto 24)) - unsigned(addr(23 downto 16))), 2));
writeline(myfile, L);
prev_hi := addr(31 downto 16);
end if;
-- check for maximum length (until 64k boundary)
maxlen := to_integer(X"10000" - unsigned(X"0" & addr(15 downto 0)));
if maxlen > 16 then maxlen := 16; end if;
-- create data record
sum := X"00";
write(L, ':');
write(L, vec_to_hex(std_logic_vector(to_unsigned(maxlen, 8)), 2));
write(L, vec_to_hex(addr(15 downto 0), 4));
write_string(L, "00");
sum := sum - maxlen;
sum := sum - unsigned(addr(15 downto 8));
sum := sum - unsigned(addr(7 downto 0));
for i in 1 to maxlen loop
data := read_memory_8(bank, addr);
sum := sum - unsigned(data);
write(L, vec_to_hex(data, 2));
addr := std_logic_vector(unsigned(addr) + 1);
end loop;
remaining := remaining - maxlen;
write(L, vec_to_hex(std_logic_vector(sum), 2));
writeline(myfile, L);
end loop;
write_string(L, ":00000001");
writeline(myfile, L);
end write_hex_file;
-- public procedure:
procedure save_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer)
is
variable stat : file_open_status;
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
begin
-- open file
file_open(stat, myfile, filename, write_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for writing."
severity failure;
init_record(myrec);
write_binary_file (myfile, bank, address, length, myrec);
file_close(myfile);
end save_memory;
-- public procedure:
procedure save_memory_hex(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer)
is
variable stat : file_open_status;
file myfile : text;
begin
-- open file
file_open(stat, myfile, filename, write_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for writing."
severity failure;
write_hex_file (myfile, bank, address, length);
file_close(myfile);
end save_memory_hex;
end;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
-- Title : Flat Memory Model package
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This package implements a memory model that can be used
-- as or in bus functional models. It implements different
-- banks, such that only one package is needed for all memories
-- in the whole project. These banks are dynamic, just like
-- the contents of the memories. Internally, this memory model
-- is 32-bit, but can be accessed by means of functions and
-- procedures that exist in various widths.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
use work.tl_string_util_pkg.all;
package tl_flat_memory_model_pkg is
constant c_fm_max_bank : integer := 255;
constant c_fm_max_sector : integer := 65535;
constant c_fm_sector_size : integer := 16384;
subtype t_byte is std_logic_vector(7 downto 0);
type flat_mem_sector_t is array(0 to c_fm_sector_size-1) of integer; -- each sector is 64kB
type flat_mem_sector_p is access flat_mem_sector_t;
type flat_mem_bank_t is array(0 to c_fm_max_sector) of flat_mem_sector_p; -- there are 64k sectors (4 GB)
type flat_mem_bank_p is access flat_mem_bank_t;
-- we need to use a handle rather than a pointer, because we can't pass pointers in function calls
-- Hence, we don't use a linked list, but an array.
type flat_mem_object_t is record
path : string(1 to 256);
name : string(1 to 128);
bank : flat_mem_bank_p;
end record;
type flat_mem_object_p is access flat_mem_object_t;
type flat_mem_array_t is array(1 to c_fm_max_bank) of flat_mem_object_p;
subtype h_mem_object is integer range 0 to c_fm_max_bank;
---------------------------------------------------------------------------
shared variable flat_memories : flat_mem_array_t := (others => null);
---------------------------------------------------------------------------
procedure register_mem_model(
path : string;
named : string;
variable handle : out h_mem_object);
procedure bind_mem_model (
named : string;
variable handle : out h_mem_object);
---------------------------------------------------------------------------
-- Low level calls
impure function read_memory(
bank : integer;
sector : integer;
entry : integer)
return integer;
procedure write_memory(
bank : integer;
sector : integer;
entry : integer;
data : integer);
procedure clear_memory(
bank : integer);
procedure clean_up;
-- 32-bit address/data access calls
impure function read_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0));
procedure write_memory_be(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0));
-- 16-bit address/data access calls
impure function read_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(15 downto 0));
-- 8-bit address/data access calls
impure function read_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(7 downto 0));
-- integer direct access calls
impure function read_memory_int(
bank : integer;
address : integer )
return integer;
procedure write_memory_int(
bank : integer;
address : integer;
data : integer );
-- File Access Procedures
procedure load_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0));
procedure save_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer);
procedure load_memory_hex(
filename : string;
bank : integer);
procedure save_memory_hex(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer);
end package;
package body tl_flat_memory_model_pkg is
-- Memory model module registration into array
procedure register_mem_model(
path : string;
named : string;
variable handle : out h_mem_object) is
begin
handle := 0;
L1 : for i in flat_memories'range loop
if flat_memories(i) = null then
-- report "my name is "& named;
handle := i;
flat_memories(i) := new flat_mem_object_t;
flat_memories(i).path(path'range) := path;
flat_memories(i).name(named'range) := named;
flat_memories(i).bank := new flat_mem_bank_t;
exit L1;
end if;
end loop;
end procedure register_mem_model;
-- Memory model module binding
procedure bind_mem_model (
named : string;
variable handle : out h_mem_object) is
begin
handle := 0;
wait for 1 ns;
L1 : for i in flat_memories'range loop
if flat_memories(i) /= null then
if flat_memories(i).name(named'range) = named or
flat_memories(i).path(named'range) = named then
handle := i;
return;
end if;
end if;
end loop;
report "Can't find memory model '"&named&"'."
severity failure;
end procedure bind_mem_model;
-- Base calls
impure function read_memory(
bank : integer;
sector : integer;
entry : integer) return integer is
begin
if flat_memories(bank) = null then
return 0;
end if;
if flat_memories(bank).bank(sector) = null then
return 0;
end if;
return flat_memories(bank).bank(sector).all(entry);
end function read_memory;
procedure write_memory(
bank : integer;
sector : integer;
entry : integer;
data : integer) is
begin
if flat_memories(bank) = null then
flat_memories(bank) := new flat_mem_object_t;
flat_memories(bank).bank(0 to c_fm_max_sector) := (others => null);
end if;
if flat_memories(bank).bank(sector) = null then
flat_memories(bank).bank(sector) := new flat_mem_sector_t;
flat_memories(bank).bank(sector).all(0 to c_fm_sector_size-1) := (others => 0);
end if;
flat_memories(bank).bank(sector).all(entry) := data;
end procedure write_memory;
procedure clear_memory(bank : integer) is
begin
if flat_memories(bank) /= null then
for i in flat_memories(bank).bank'range loop
if flat_memories(bank).bank(i) /= null then
deallocate(flat_memories(bank).bank(i));
end if;
end loop;
deallocate(flat_memories(bank));
flat_memories(bank) := null;
end if;
end procedure clear_memory;
procedure clean_up is
begin
for i in flat_memories'range loop
clear_memory(i);
end loop;
end procedure clean_up;
-- 32-bit address/data access calls
impure function read_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
return std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
end function read_memory_32;
procedure write_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0))
is
variable sector_idx : integer;
variable entry_idx : integer;
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
write_memory(bank, sector_idx, entry_idx, to_integer(signed(data)));
end procedure write_memory_32;
procedure write_memory_be(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0))
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
variable L : line;
begin
--write_s(L, "Writing " & vec_to_hex(data, 8) & " to location " & vec_to_hex(address, 8));
--writeline(output, L);
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
for i in be'range loop
if to_x01(be(i)) = '1' then
read_data(7+8*i downto 8*i) := data(7+8*i downto 8*i);
end if;
end loop;
write_memory(bank, sector_idx, entry_idx, to_integer(signed(read_data)));
end procedure write_memory_be;
-- 16-bit address/data access calls
impure function read_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
if address(1) = '0' then
return read_data(15 downto 0);
else
return read_data(31 downto 16);
end if;
end function read_memory_16;
procedure write_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(15 downto 0))
is
variable be_temp : std_logic_vector(3 downto 0);
variable write_data : std_logic_vector(31 downto 0);
begin
write_data := data & data;
be_temp := address(1) & address(1) & not address(1) & not address(1);
write_memory_be(bank, address, write_data, be_temp);
end procedure write_memory_16;
-- 8-bit address/data access calls
impure function read_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
case address(1 downto 0) is
when "11" =>
return read_data(31 downto 24);
when "01" =>
return read_data(15 downto 8);
when "10" =>
return read_data(23 downto 16);
when others =>
return read_data(7 downto 0);
end case;
end function read_memory_8;
procedure write_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(7 downto 0))
is
variable be_temp : std_logic_vector(3 downto 0) := (others => '0');
variable write_data : std_logic_vector(31 downto 0);
begin
write_data := data & data & data & data;
be_temp(to_integer(unsigned(address(1 downto 0)))) := '1';
write_memory_be(bank, address, write_data, be_temp);
end procedure write_memory_8;
-- Integer direct procedures
impure function read_memory_int(
bank : integer;
address : integer )
return integer is
variable sect, index : integer;
begin
sect := address / c_fm_sector_size;
index := address mod c_fm_sector_size;
return read_memory(bank, sect, index);
end function read_memory_int;
procedure write_memory_int(
bank : integer;
address : integer;
data : integer ) is
variable sect, index : integer;
begin
sect := address / c_fm_sector_size;
index := address mod c_fm_sector_size;
write_memory(bank, sect, index, data);
end procedure write_memory_int;
-- File access procedures
-- not a public procedure.
procedure read_binary_file(
file myfile : t_binary_file;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
variable myrec : inout t_binary_file_rec)
is
variable addr : unsigned(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable i : integer;
variable sector_idx : integer;
variable entry_idx : integer;
begin
addr := unsigned(startaddr);
if startaddr(1 downto 0) = "00" then
sector_idx := to_integer(addr(31 downto 16));
entry_idx := to_integer(addr(15 downto 2));
aligned : while true loop
if EndFile(myfile) then
exit aligned;
end if;
read(myfile, i);
write_memory(bank, sector_idx, entry_idx, i);
if entry_idx = c_fm_sector_size-1 then
entry_idx := 0;
if sector_idx = c_fm_max_sector then
sector_idx := 0;
else
sector_idx := sector_idx + 1;
end if;
else
entry_idx := entry_idx + 1;
end if;
end loop;
else
unaligned : while true loop
if EndFile(myfile) and myrec.Offset = 0 then
exit unaligned;
end if;
read_byte(myfile, data, myrec);
write_memory_8(bank, std_logic_vector(addr), data);
addr := addr + 1;
end loop;
end if;
end read_binary_file;
-- not a public procedure
procedure read_hex_file (
file myfile : text;
bank : integer)
is
variable L : line;
variable addr : unsigned(31 downto 0) := (others => '0');
variable c : character;
variable data : t_byte;
variable sum : unsigned(7 downto 0);
variable rectype : t_byte;
variable tmp_addr : std_logic_vector(15 downto 0);
variable fileend : boolean;
variable linenr : integer := 0;
variable len : integer;
begin
outer : while true loop
if EndFile(myfile) then
report "Missing end of file record."
severity warning;
return;
end if;
-- search for lines starting with ':'
start : while true loop
readline(myfile, L);
linenr := linenr + 1;
read(L, c);
if c = ':' then
exit start;
end if;
end loop;
-- parse the rest of the line
sum := X"00";
get_byte_from_file(myfile, L, fileend, data);
len := to_integer(unsigned(data));
get_byte_from_file(myfile, L, fileend, tmp_addr(15 downto 8));
get_byte_from_file(myfile, L, fileend, tmp_addr(7 downto 0));
get_byte_from_file(myfile, L, fileend, rectype);
sum := sum - (unsigned(data) + unsigned(tmp_addr(15 downto 8)) + unsigned(tmp_addr(7 downto 0)) + unsigned(rectype));
case rectype is
when X"00" => -- data record
addr(15 downto 0) := unsigned(tmp_addr);
for i in 0 to len-1 loop
get_byte_from_file(myfile, L, fileend, data);
sum := sum - unsigned(data);
write_memory_8(bank, std_logic_vector(addr), data);
addr := addr + 1;
end loop;
when X"01" => -- end of file record
return;
when X"04" => -- extended linear address record
get_byte_from_file(myfile, L, fileend, data);
addr(31 downto 24) := unsigned(data);
sum := sum - addr(31 downto 24);
get_byte_from_file(myfile, L, fileend, data);
addr(23 downto 16) := unsigned(data);
sum := sum - addr(23 downto 16);
when others =>
report "Unexpected record type " & vec_to_hex(rectype, 2)
severity warning;
return;
end case;
-- check checksum
get_byte_from_file(myfile, L, fileend, data);
assert sum = unsigned(data)
report "Warning: Checksum incorrect at line: " & integer'image(linenr)
severity warning;
end loop;
end read_hex_file;
-- public procedure:
procedure load_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0))
is
variable stat : file_open_status;
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
begin
-- open file
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
init_record(myrec);
read_binary_file (myfile, bank, address, myrec);
file_close(myfile);
end load_memory;
-- public procedure:
procedure load_memory_hex(
filename : string;
bank : integer)
is
variable stat : file_open_status;
file myfile : text;
begin
-- open file
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file (myfile, bank);
file_close(myfile);
end load_memory_hex;
-- not a public procedure.
procedure write_binary_file(
file myfile : t_binary_file;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
length : integer;
variable myrec : inout t_binary_file_rec)
is
variable addr : unsigned(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable i : integer;
variable sector_idx : integer;
variable entry_idx : integer;
variable remaining : integer;
begin
addr := unsigned(startaddr);
if startaddr(1 downto 0) = "00" then
sector_idx := to_integer(addr(31 downto 16));
entry_idx := to_integer(addr(15 downto 2));
remaining := (length + 3) / 4;
aligned : while remaining > 0 loop
i := read_memory(bank, sector_idx, entry_idx);
write(myfile, i);
remaining := remaining - 1;
if entry_idx = c_fm_sector_size-1 then
if sector_idx = c_fm_max_sector then
sector_idx := 0;
else
sector_idx := sector_idx + 1;
end if;
else
entry_idx := entry_idx + 1;
end if;
end loop;
else
remaining := length;
unaligned : while remaining > 0 loop
data := read_memory_8(bank, std_logic_vector(addr));
write_byte(myfile, data, myrec);
addr := addr + 1;
remaining := remaining - 1;
end loop;
purge(myfile, myrec);
end if;
end write_binary_file;
-- not a public procedure.
procedure write_hex_file(
file myfile : text;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
length : integer)
is
variable addr : std_logic_vector(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable sector_idx : integer;
variable entry_idx : integer;
variable remaining : integer;
variable maxlen : integer;
variable sum : unsigned(7 downto 0);
variable L : line;
variable prev_hi : std_logic_vector(31 downto 16) := (others => '-');
begin
addr := startaddr;
remaining := length;
unaligned : while remaining > 0 loop
-- check if we need to write a new extended address record
if addr(31 downto 16) /= prev_hi then
write_string(L, ":02000004");
write(L, vec_to_hex(addr(31 downto 16), 4));
write(L, vec_to_hex(std_logic_vector(X"FA" - unsigned(addr(31 downto 24)) - unsigned(addr(23 downto 16))), 2));
writeline(myfile, L);
prev_hi := addr(31 downto 16);
end if;
-- check for maximum length (until 64k boundary)
maxlen := to_integer(X"10000" - unsigned(X"0" & addr(15 downto 0)));
if maxlen > 16 then maxlen := 16; end if;
-- create data record
sum := X"00";
write(L, ':');
write(L, vec_to_hex(std_logic_vector(to_unsigned(maxlen, 8)), 2));
write(L, vec_to_hex(addr(15 downto 0), 4));
write_string(L, "00");
sum := sum - maxlen;
sum := sum - unsigned(addr(15 downto 8));
sum := sum - unsigned(addr(7 downto 0));
for i in 1 to maxlen loop
data := read_memory_8(bank, addr);
sum := sum - unsigned(data);
write(L, vec_to_hex(data, 2));
addr := std_logic_vector(unsigned(addr) + 1);
end loop;
remaining := remaining - maxlen;
write(L, vec_to_hex(std_logic_vector(sum), 2));
writeline(myfile, L);
end loop;
write_string(L, ":00000001");
writeline(myfile, L);
end write_hex_file;
-- public procedure:
procedure save_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer)
is
variable stat : file_open_status;
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
begin
-- open file
file_open(stat, myfile, filename, write_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for writing."
severity failure;
init_record(myrec);
write_binary_file (myfile, bank, address, length, myrec);
file_close(myfile);
end save_memory;
-- public procedure:
procedure save_memory_hex(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer)
is
variable stat : file_open_status;
file myfile : text;
begin
-- open file
file_open(stat, myfile, filename, write_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for writing."
severity failure;
write_hex_file (myfile, bank, address, length);
file_close(myfile);
end save_memory_hex;
end;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
-- Title : Flat Memory Model package
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This package implements a memory model that can be used
-- as or in bus functional models. It implements different
-- banks, such that only one package is needed for all memories
-- in the whole project. These banks are dynamic, just like
-- the contents of the memories. Internally, this memory model
-- is 32-bit, but can be accessed by means of functions and
-- procedures that exist in various widths.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
use work.tl_string_util_pkg.all;
package tl_flat_memory_model_pkg is
constant c_fm_max_bank : integer := 255;
constant c_fm_max_sector : integer := 65535;
constant c_fm_sector_size : integer := 16384;
subtype t_byte is std_logic_vector(7 downto 0);
type flat_mem_sector_t is array(0 to c_fm_sector_size-1) of integer; -- each sector is 64kB
type flat_mem_sector_p is access flat_mem_sector_t;
type flat_mem_bank_t is array(0 to c_fm_max_sector) of flat_mem_sector_p; -- there are 64k sectors (4 GB)
type flat_mem_bank_p is access flat_mem_bank_t;
-- we need to use a handle rather than a pointer, because we can't pass pointers in function calls
-- Hence, we don't use a linked list, but an array.
type flat_mem_object_t is record
path : string(1 to 256);
name : string(1 to 128);
bank : flat_mem_bank_p;
end record;
type flat_mem_object_p is access flat_mem_object_t;
type flat_mem_array_t is array(1 to c_fm_max_bank) of flat_mem_object_p;
subtype h_mem_object is integer range 0 to c_fm_max_bank;
---------------------------------------------------------------------------
shared variable flat_memories : flat_mem_array_t := (others => null);
---------------------------------------------------------------------------
procedure register_mem_model(
path : string;
named : string;
variable handle : out h_mem_object);
procedure bind_mem_model (
named : string;
variable handle : out h_mem_object);
---------------------------------------------------------------------------
-- Low level calls
impure function read_memory(
bank : integer;
sector : integer;
entry : integer)
return integer;
procedure write_memory(
bank : integer;
sector : integer;
entry : integer;
data : integer);
procedure clear_memory(
bank : integer);
procedure clean_up;
-- 32-bit address/data access calls
impure function read_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0));
procedure write_memory_be(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0));
-- 16-bit address/data access calls
impure function read_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(15 downto 0));
-- 8-bit address/data access calls
impure function read_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector;
procedure write_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(7 downto 0));
-- integer direct access calls
impure function read_memory_int(
bank : integer;
address : integer )
return integer;
procedure write_memory_int(
bank : integer;
address : integer;
data : integer );
-- File Access Procedures
procedure load_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0));
procedure save_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer);
procedure load_memory_hex(
filename : string;
bank : integer);
procedure save_memory_hex(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer);
end package;
package body tl_flat_memory_model_pkg is
-- Memory model module registration into array
procedure register_mem_model(
path : string;
named : string;
variable handle : out h_mem_object) is
begin
handle := 0;
L1 : for i in flat_memories'range loop
if flat_memories(i) = null then
-- report "my name is "& named;
handle := i;
flat_memories(i) := new flat_mem_object_t;
flat_memories(i).path(path'range) := path;
flat_memories(i).name(named'range) := named;
flat_memories(i).bank := new flat_mem_bank_t;
exit L1;
end if;
end loop;
end procedure register_mem_model;
-- Memory model module binding
procedure bind_mem_model (
named : string;
variable handle : out h_mem_object) is
begin
handle := 0;
wait for 1 ns;
L1 : for i in flat_memories'range loop
if flat_memories(i) /= null then
if flat_memories(i).name(named'range) = named or
flat_memories(i).path(named'range) = named then
handle := i;
return;
end if;
end if;
end loop;
report "Can't find memory model '"&named&"'."
severity failure;
end procedure bind_mem_model;
-- Base calls
impure function read_memory(
bank : integer;
sector : integer;
entry : integer) return integer is
begin
if flat_memories(bank) = null then
return 0;
end if;
if flat_memories(bank).bank(sector) = null then
return 0;
end if;
return flat_memories(bank).bank(sector).all(entry);
end function read_memory;
procedure write_memory(
bank : integer;
sector : integer;
entry : integer;
data : integer) is
begin
if flat_memories(bank) = null then
flat_memories(bank) := new flat_mem_object_t;
flat_memories(bank).bank(0 to c_fm_max_sector) := (others => null);
end if;
if flat_memories(bank).bank(sector) = null then
flat_memories(bank).bank(sector) := new flat_mem_sector_t;
flat_memories(bank).bank(sector).all(0 to c_fm_sector_size-1) := (others => 0);
end if;
flat_memories(bank).bank(sector).all(entry) := data;
end procedure write_memory;
procedure clear_memory(bank : integer) is
begin
if flat_memories(bank) /= null then
for i in flat_memories(bank).bank'range loop
if flat_memories(bank).bank(i) /= null then
deallocate(flat_memories(bank).bank(i));
end if;
end loop;
deallocate(flat_memories(bank));
flat_memories(bank) := null;
end if;
end procedure clear_memory;
procedure clean_up is
begin
for i in flat_memories'range loop
clear_memory(i);
end loop;
end procedure clean_up;
-- 32-bit address/data access calls
impure function read_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
return std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
end function read_memory_32;
procedure write_memory_32(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0))
is
variable sector_idx : integer;
variable entry_idx : integer;
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
write_memory(bank, sector_idx, entry_idx, to_integer(signed(data)));
end procedure write_memory_32;
procedure write_memory_be(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0))
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
variable L : line;
begin
--write_s(L, "Writing " & vec_to_hex(data, 8) & " to location " & vec_to_hex(address, 8));
--writeline(output, L);
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
for i in be'range loop
if to_x01(be(i)) = '1' then
read_data(7+8*i downto 8*i) := data(7+8*i downto 8*i);
end if;
end loop;
write_memory(bank, sector_idx, entry_idx, to_integer(signed(read_data)));
end procedure write_memory_be;
-- 16-bit address/data access calls
impure function read_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
if address(1) = '0' then
return read_data(15 downto 0);
else
return read_data(31 downto 16);
end if;
end function read_memory_16;
procedure write_memory_16(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(15 downto 0))
is
variable be_temp : std_logic_vector(3 downto 0);
variable write_data : std_logic_vector(31 downto 0);
begin
write_data := data & data;
be_temp := address(1) & address(1) & not address(1) & not address(1);
write_memory_be(bank, address, write_data, be_temp);
end procedure write_memory_16;
-- 8-bit address/data access calls
impure function read_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0))
return std_logic_vector
is
variable sector_idx : integer;
variable entry_idx : integer;
variable read_data : std_logic_vector(31 downto 0);
begin
sector_idx := to_integer(unsigned(address(31 downto 16)));
entry_idx := to_integer(unsigned(address(15 downto 2)));
read_data := std_logic_vector(to_signed(read_memory(bank, sector_idx, entry_idx), 32));
case address(1 downto 0) is
when "11" =>
return read_data(31 downto 24);
when "01" =>
return read_data(15 downto 8);
when "10" =>
return read_data(23 downto 16);
when others =>
return read_data(7 downto 0);
end case;
end function read_memory_8;
procedure write_memory_8(
bank : integer;
address : std_logic_vector(31 downto 0);
data : std_logic_vector(7 downto 0))
is
variable be_temp : std_logic_vector(3 downto 0) := (others => '0');
variable write_data : std_logic_vector(31 downto 0);
begin
write_data := data & data & data & data;
be_temp(to_integer(unsigned(address(1 downto 0)))) := '1';
write_memory_be(bank, address, write_data, be_temp);
end procedure write_memory_8;
-- Integer direct procedures
impure function read_memory_int(
bank : integer;
address : integer )
return integer is
variable sect, index : integer;
begin
sect := address / c_fm_sector_size;
index := address mod c_fm_sector_size;
return read_memory(bank, sect, index);
end function read_memory_int;
procedure write_memory_int(
bank : integer;
address : integer;
data : integer ) is
variable sect, index : integer;
begin
sect := address / c_fm_sector_size;
index := address mod c_fm_sector_size;
write_memory(bank, sect, index, data);
end procedure write_memory_int;
-- File access procedures
-- not a public procedure.
procedure read_binary_file(
file myfile : t_binary_file;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
variable myrec : inout t_binary_file_rec)
is
variable addr : unsigned(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable i : integer;
variable sector_idx : integer;
variable entry_idx : integer;
begin
addr := unsigned(startaddr);
if startaddr(1 downto 0) = "00" then
sector_idx := to_integer(addr(31 downto 16));
entry_idx := to_integer(addr(15 downto 2));
aligned : while true loop
if EndFile(myfile) then
exit aligned;
end if;
read(myfile, i);
write_memory(bank, sector_idx, entry_idx, i);
if entry_idx = c_fm_sector_size-1 then
entry_idx := 0;
if sector_idx = c_fm_max_sector then
sector_idx := 0;
else
sector_idx := sector_idx + 1;
end if;
else
entry_idx := entry_idx + 1;
end if;
end loop;
else
unaligned : while true loop
if EndFile(myfile) and myrec.Offset = 0 then
exit unaligned;
end if;
read_byte(myfile, data, myrec);
write_memory_8(bank, std_logic_vector(addr), data);
addr := addr + 1;
end loop;
end if;
end read_binary_file;
-- not a public procedure
procedure read_hex_file (
file myfile : text;
bank : integer)
is
variable L : line;
variable addr : unsigned(31 downto 0) := (others => '0');
variable c : character;
variable data : t_byte;
variable sum : unsigned(7 downto 0);
variable rectype : t_byte;
variable tmp_addr : std_logic_vector(15 downto 0);
variable fileend : boolean;
variable linenr : integer := 0;
variable len : integer;
begin
outer : while true loop
if EndFile(myfile) then
report "Missing end of file record."
severity warning;
return;
end if;
-- search for lines starting with ':'
start : while true loop
readline(myfile, L);
linenr := linenr + 1;
read(L, c);
if c = ':' then
exit start;
end if;
end loop;
-- parse the rest of the line
sum := X"00";
get_byte_from_file(myfile, L, fileend, data);
len := to_integer(unsigned(data));
get_byte_from_file(myfile, L, fileend, tmp_addr(15 downto 8));
get_byte_from_file(myfile, L, fileend, tmp_addr(7 downto 0));
get_byte_from_file(myfile, L, fileend, rectype);
sum := sum - (unsigned(data) + unsigned(tmp_addr(15 downto 8)) + unsigned(tmp_addr(7 downto 0)) + unsigned(rectype));
case rectype is
when X"00" => -- data record
addr(15 downto 0) := unsigned(tmp_addr);
for i in 0 to len-1 loop
get_byte_from_file(myfile, L, fileend, data);
sum := sum - unsigned(data);
write_memory_8(bank, std_logic_vector(addr), data);
addr := addr + 1;
end loop;
when X"01" => -- end of file record
return;
when X"04" => -- extended linear address record
get_byte_from_file(myfile, L, fileend, data);
addr(31 downto 24) := unsigned(data);
sum := sum - addr(31 downto 24);
get_byte_from_file(myfile, L, fileend, data);
addr(23 downto 16) := unsigned(data);
sum := sum - addr(23 downto 16);
when others =>
report "Unexpected record type " & vec_to_hex(rectype, 2)
severity warning;
return;
end case;
-- check checksum
get_byte_from_file(myfile, L, fileend, data);
assert sum = unsigned(data)
report "Warning: Checksum incorrect at line: " & integer'image(linenr)
severity warning;
end loop;
end read_hex_file;
-- public procedure:
procedure load_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0))
is
variable stat : file_open_status;
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
begin
-- open file
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
init_record(myrec);
read_binary_file (myfile, bank, address, myrec);
file_close(myfile);
end load_memory;
-- public procedure:
procedure load_memory_hex(
filename : string;
bank : integer)
is
variable stat : file_open_status;
file myfile : text;
begin
-- open file
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file (myfile, bank);
file_close(myfile);
end load_memory_hex;
-- not a public procedure.
procedure write_binary_file(
file myfile : t_binary_file;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
length : integer;
variable myrec : inout t_binary_file_rec)
is
variable addr : unsigned(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable i : integer;
variable sector_idx : integer;
variable entry_idx : integer;
variable remaining : integer;
begin
addr := unsigned(startaddr);
if startaddr(1 downto 0) = "00" then
sector_idx := to_integer(addr(31 downto 16));
entry_idx := to_integer(addr(15 downto 2));
remaining := (length + 3) / 4;
aligned : while remaining > 0 loop
i := read_memory(bank, sector_idx, entry_idx);
write(myfile, i);
remaining := remaining - 1;
if entry_idx = c_fm_sector_size-1 then
if sector_idx = c_fm_max_sector then
sector_idx := 0;
else
sector_idx := sector_idx + 1;
end if;
else
entry_idx := entry_idx + 1;
end if;
end loop;
else
remaining := length;
unaligned : while remaining > 0 loop
data := read_memory_8(bank, std_logic_vector(addr));
write_byte(myfile, data, myrec);
addr := addr + 1;
remaining := remaining - 1;
end loop;
purge(myfile, myrec);
end if;
end write_binary_file;
-- not a public procedure.
procedure write_hex_file(
file myfile : text;
bank : integer;
startaddr : std_logic_vector(31 downto 0);
length : integer)
is
variable addr : std_logic_vector(31 downto 0);
variable data : std_logic_vector(7 downto 0);
variable sector_idx : integer;
variable entry_idx : integer;
variable remaining : integer;
variable maxlen : integer;
variable sum : unsigned(7 downto 0);
variable L : line;
variable prev_hi : std_logic_vector(31 downto 16) := (others => '-');
begin
addr := startaddr;
remaining := length;
unaligned : while remaining > 0 loop
-- check if we need to write a new extended address record
if addr(31 downto 16) /= prev_hi then
write_string(L, ":02000004");
write(L, vec_to_hex(addr(31 downto 16), 4));
write(L, vec_to_hex(std_logic_vector(X"FA" - unsigned(addr(31 downto 24)) - unsigned(addr(23 downto 16))), 2));
writeline(myfile, L);
prev_hi := addr(31 downto 16);
end if;
-- check for maximum length (until 64k boundary)
maxlen := to_integer(X"10000" - unsigned(X"0" & addr(15 downto 0)));
if maxlen > 16 then maxlen := 16; end if;
-- create data record
sum := X"00";
write(L, ':');
write(L, vec_to_hex(std_logic_vector(to_unsigned(maxlen, 8)), 2));
write(L, vec_to_hex(addr(15 downto 0), 4));
write_string(L, "00");
sum := sum - maxlen;
sum := sum - unsigned(addr(15 downto 8));
sum := sum - unsigned(addr(7 downto 0));
for i in 1 to maxlen loop
data := read_memory_8(bank, addr);
sum := sum - unsigned(data);
write(L, vec_to_hex(data, 2));
addr := std_logic_vector(unsigned(addr) + 1);
end loop;
remaining := remaining - maxlen;
write(L, vec_to_hex(std_logic_vector(sum), 2));
writeline(myfile, L);
end loop;
write_string(L, ":00000001");
writeline(myfile, L);
end write_hex_file;
-- public procedure:
procedure save_memory(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer)
is
variable stat : file_open_status;
file myfile : t_binary_file;
variable myrec : t_binary_file_rec;
begin
-- open file
file_open(stat, myfile, filename, write_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for writing."
severity failure;
init_record(myrec);
write_binary_file (myfile, bank, address, length, myrec);
file_close(myfile);
end save_memory;
-- public procedure:
procedure save_memory_hex(
filename : string;
bank : integer;
address : std_logic_vector(31 downto 0);
length : integer)
is
variable stat : file_open_status;
file myfile : text;
begin
-- open file
file_open(stat, myfile, filename, write_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for writing."
severity failure;
write_hex_file (myfile, bank, address, length);
file_close(myfile);
end save_memory_hex;
end;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: instructionMemory_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY instructionMemory_exdes IS
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END instructionMemory_exdes;
ARCHITECTURE xilinx OF instructionMemory_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT instructionMemory IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : instructionMemory
PORT MAP (
--Port A
ENA => ENA,
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
--------------------------------------------------------------------------------
--Author: Jay Aurabind
--Email : [email protected]
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pulse_counter is
port ( DAT_O : out std_logic_vector(63 downto 0);
ERR_O : out std_logic; --This is '1' if the pulse freq is more than clk freq.
Pulse_I : in std_logic;
CLK_I : in std_logic
);
end pulse_counter;
architecture Behavioral of pulse_counter is
signal Curr_Count,Prev_Count : std_logic_vector(63 downto 0):=(others => '0');
begin
--Increment Curr_Count every clock cycle.This is the max freq which can be measured by the module.
process(CLK_I)
begin
if( CLK_I'event and CLK_I='1' ) then
Curr_Count <= Curr_Count + 1;
end if;
end process;
--Calculate the time period of the pulse input using the current and previous counts.
process(Pulse_I)
begin
if( Pulse_I'event and Pulse_I = '1' ) then
--These different conditions eliminate the count overflow problem
--which can happen once the module is run for a long time.
if( Prev_Count < Curr_Count ) then
DAT_O <= Curr_Count - Prev_Count;
ERR_O <= '0';
elsif( Prev_Count > Curr_Count ) then
--X"F_F" is same as "1111_1111".
--'_' is added for readability.
DAT_O <= X"1_0000_0000_0000" - Prev_Count + Curr_Count;
ERR_O <= '0';
else
DAT_O <= (others => '0');
ERR_O <= '1'; --Error bit is inserted here.
end if;
Prev_Count <= Curr_Count; --Re-setting the Prev_Count.
end if;
end process;
end Behavioral;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- Note: This package will be compiled into every single VVC library.
-- As the type t_vvc_target_record is already compiled into every single VVC library,
-- the type definition will be unique for every library, and thus result in a unique
-- procedure signature for every VVC. Hence the shared variable shared_vvc_cmd will
-- refer to only the shared variable defined in the given library.
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.vvc_cmd_pkg.all; -- shared_vvc_response, t_vvc_result
use work.td_target_support_pkg.all;
package td_vvc_framework_common_methods_pkg is
--======================================================================
-- Common Methods
--======================================================================
-------------------------------------------
-- await_completion
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Awaits completion of all commands in the queue for the specified VVC, or
-- until timeout.
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant timeout : in time;
constant msg : in string := ""
);
-------------------------------------------
-- await_completion
-------------------------------------------
-- See description above
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant timeout : in time;
constant msg : in string := ""
);
-------------------------------------------
-- await_completion
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Awaits completion of the specified command 'wanted_idx' in the queue for the specified VVC, or
-- until timeout.
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := ""
);
-------------------------------------------
-- await_completion
-------------------------------------------
-- See description above
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := ""
);
-------------------------------------------
-- await_any_completion
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Waits for the first of multiple VVCs to finish :
-- - Awaits completion of all commands in the queue for the specified VVC, or
-- - until global_awaiting_completion /= '1' (any of the other involved VVCs completed).
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0
);
-- Overload without vvc_channel
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0
);
-- Overload with wanted_idx
-- - Awaits completion of the specified command 'wanted_idx' in the queue for the specified VVC, or
-- - until global_awaiting_completion /= '1' (any of the other involved VVCs completed).
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0
);
-- Overload without vvc_channel
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0
);
-------------------------------------------
-- disable_log_msg
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Disables the specified msg_id for the VVC
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
);
-------------------------------------------
-- disable_log_msg
-------------------------------------------
-- See description above
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
);
-------------------------------------------
-- enable_log_msg
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Enables the specified msg_id for the VVC
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
);
-------------------------------------------
-- enable_log_msg
-------------------------------------------
-- See description above
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
);
-------------------------------------------
-- flush_command_queue
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Flushes the command queue of the specified VVC
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg : in string := ""
);
-------------------------------------------
-- flush_command_queue
-------------------------------------------
-- See description above
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := ""
);
-------------------------------------------
-- fetch_result
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Fetches result from a VVC
-- - Requires that result is available (i.e. already executed in respective VVC)
-- - Logs with ID ID_UVVM_CMD_RESULT
-- The 'result' parameter is of type t_vvc_result to
-- support that the BFM returns something other than a std_logic_vector.
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant caller_name : in string := "base_procedure"
);
-- -- Same as above but without fetch_is_accepted.
-- -- Will trigger alert with alert_level if not OK.
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
);
-- -- - This version does not use vvc_channel.
-- -- - Fetches result from a VVC
-- -- - Requires that result is available (i.e. already executed in respective VVC)
-- -- - Logs with ID ID_UVVM_CMD_RESULT
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
);
-- -- Same as above but without fetch_is_accepted.
-- -- Will trigger alert with alert_level if not OK.
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- VVC executor QUEUED command
-- - Inserts delay for 'delay' clock cycles
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- See description above
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- VVC executor QUEUED command
-- - Inserts delay for a given time
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in time;
constant msg : in string := ""
);
-------------------------------------------
-- insert_delay
-------------------------------------------
-- See description above
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in time;
constant msg : in string := ""
);
-------------------------------------------
-- terminate_current_command
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Terminates the current command being processed in the VVC executor
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
);
-------------------------------------------
-- terminate_all_commands
-------------------------------------------
-- VVC interpreter IMMEDIATE command
-- - Terminates the current command being processed in the VVC executor, and
-- flushes the command queue
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
);
-- Returns the index of the last queued command
impure function get_last_received_cmd_idx(
signal vvc_target : in t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
) return natural;
end package td_vvc_framework_common_methods_pkg;
package body td_vvc_framework_common_methods_pkg is
--=========================================================================================
-- Methods
--=========================================================================================
-- NOTE: ALL VVCs using this td_vvc_framework_common_methods_pkg package MUST have the following declared in their local vvc_cmd_pkg.
-- - The enumerated t_operation (e.g. AWAIT_COMPLETION, ENABLE_LOG_MSG, etc.)
-- Any VVC based on an older version of td_vvc_framework_common_methods_pkg must - if new operators have been introduced in td_vvc_framework_common_methods_pkg either
-- a) include the new operator(s) in its t_operation, or
-- b) change the use-reference to an older common_methods package.
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant timeout : in time;
constant msg : in string := ""
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := -1; -- All commands must be completed (i.e. not just a selected command index)
shared_vvc_cmd.timeout := timeout;
send_command_to_vvc(vvc_target, timeout);
end procedure;
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant timeout : in time;
constant msg : in string := ""
) is
begin
await_completion(vvc_target, vvc_instance_idx, NA, timeout, msg);
end procedure;
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := ""
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := wanted_idx;
shared_vvc_cmd.timeout := timeout;
send_command_to_vvc(vvc_target, timeout);
end procedure;
procedure await_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant timeout : in time;
constant msg : in string := ""
) is
begin
await_completion(vvc_target, vvc_instance_idx, NA, wanted_idx, timeout, msg);
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0 -- Useful when being called by multiple sequencers
) is
constant proc_name : string := "await_any_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_ANY_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := -1; -- All commands must be completed (i.e. not just a selected command index)
shared_vvc_cmd.gen_integer_array(1) := awaiting_completion_idx;
shared_vvc_cmd.timeout := timeout;
if lastness = LAST then
shared_vvc_cmd.gen_boolean := true; -- LAST
else
shared_vvc_cmd.gen_boolean := false; -- NOT_LAST
end if;
send_command_to_vvc(vvc_target, timeout); -- sets vvc_target.trigger, then waits until global_vvc_ack = '1' for timeout
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0
) is
begin
await_any_completion(vvc_target, vvc_instance_idx, NA, lastness, timeout, msg, awaiting_completion_idx);
end procedure;
-- The two below are as the two above, except with wanted_idx as parameter
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0 -- Useful when being called by multiple sequencers
) is
constant proc_name : string := "await_any_completion";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ", " & to_string(timeout, ns) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, AWAIT_ANY_COMPLETION);
shared_vvc_cmd.gen_integer_array(0) := wanted_idx;
shared_vvc_cmd.gen_integer_array(1) := awaiting_completion_idx;
shared_vvc_cmd.timeout := timeout;
if lastness = LAST then
-- LAST
shared_vvc_cmd.gen_boolean := true;
else
-- NOT_LAST : Timeout must be handled in interpreter_await_any_completion
-- becuase the command is always acknowledged immediately by the VVC to allow the sequencer to continue
shared_vvc_cmd.gen_boolean := false;
end if;
send_command_to_vvc(vvc_target, timeout);
end procedure;
procedure await_any_completion(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in natural;
constant lastness : in t_lastness;
constant timeout : in time := 100 ns;
constant msg : in string := "";
constant awaiting_completion_idx : in natural := 0 -- Useful when being called by multiple sequencers
) is
begin
await_any_completion(vvc_target, vvc_instance_idx, NA, wanted_idx, lastness, timeout, msg, awaiting_completion_idx);
end procedure;
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
) is
constant proc_name : string := "disable_log_msg";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_upper(to_string(msg_id)) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, DISABLE_LOG_MSG);
shared_vvc_cmd.msg_id := msg_id;
shared_vvc_cmd.quietness := quietness;
send_command_to_vvc(vvc_target);
end procedure;
procedure disable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
) is
begin
disable_log_msg(vvc_target, vvc_instance_idx, NA, msg_id, msg, quietness);
end procedure;
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
) is
constant proc_name : string := "enable_log_msg";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_upper(to_string(msg_id)) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, ENABLE_LOG_MSG);
shared_vvc_cmd.msg_id := msg_id;
shared_vvc_cmd.quietness := quietness;
send_command_to_vvc(vvc_target);
end procedure;
procedure enable_log_msg(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : t_quietness := NON_QUIET
) is
begin
enable_log_msg(vvc_target, vvc_instance_idx, NA, msg_id, msg, quietness);
end procedure;
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant msg : in string := ""
) is
constant proc_name : string := "flush_command_queue";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, FLUSH_COMMAND_QUEUE);
send_command_to_vvc(vvc_target);
end procedure;
procedure flush_command_queue(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string := ""
) is
begin
flush_command_queue(vvc_target, vvc_instance_idx, NA, msg);
end procedure;
-- Requires that result is available (i.e. already executed in respective VVC)
-- The four next procedures are overloads for when 'result' is of type work.vvc_cmd_pkg.t_vvc_result
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR;
constant caller_name : in string := "base_procedure"
) is
constant proc_name : string := "fetch_result";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ")";
begin
await_semaphore_in_delta_cycles(protected_response_semaphore);
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, FETCH_RESULT);
shared_vvc_cmd.gen_integer_array(0) := wanted_idx;
send_command_to_vvc(vvc_target);
-- Post process
result := shared_vvc_response.result;
fetch_is_accepted := shared_vvc_response.fetch_is_accepted;
if caller_name = "base_procedure" then
log(ID_UVVM_CMD_RESULT, proc_call & ": Legal=>" & to_string(shared_vvc_response.fetch_is_accepted) & ", Result=>" & to_string(result) & format_command_idx(shared_cmd_idx), C_SCOPE); -- Get and ack the new command
end if;
release_semaphore(protected_response_semaphore);
end procedure;
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
) is
variable v_fetch_is_accepted : boolean;
constant proc_name : string := "fetch_result";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(wanted_idx) & ")";
begin
fetch_result(vvc_target, vvc_instance_idx, vvc_channel, wanted_idx, result, v_fetch_is_accepted, msg, alert_level, proc_name & "_with_check_of_ok");
if v_fetch_is_accepted then
log(ID_UVVM_CMD_RESULT, proc_call & ": Legal=>" & to_string(v_fetch_is_accepted) & ", Result=>" & format_command_idx(shared_cmd_idx), C_SCOPE); -- Get and ack the new command
else
alert(alert_level, "fetch_result(" & to_string(wanted_idx) & "): " & add_msg_delimiter(msg) & "." &
" Failed. Trying to fetch result from not yet executed command or from command with no result stored. " & format_command_idx(shared_cmd_idx), C_SCOPE);
end if;
end procedure;
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
variable fetch_is_accepted : out boolean;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
) is
begin
fetch_result(vvc_target, vvc_instance_idx, NA, wanted_idx, result, fetch_is_accepted, msg, alert_level);
end procedure;
procedure fetch_result(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant wanted_idx : in integer;
variable result : out t_vvc_result;
constant msg : in string := "";
constant alert_level : in t_alert_level := TB_ERROR
) is
begin
fetch_result(vvc_target, vvc_instance_idx, NA, wanted_idx, result, msg, alert_level);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(delay) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, QUEUED, INSERT_DELAY);
shared_vvc_cmd.gen_integer_array(0) := delay;
send_command_to_vvc(vvc_target);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in natural; -- in clock cycles
constant msg : in string := ""
) is
begin
insert_delay(vvc_target, vvc_instance_idx, NA, delay, msg);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant delay : in time;
constant msg : in string := ""
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ", " & to_string(delay) & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, QUEUED, INSERT_DELAY);
shared_vvc_cmd.delay := delay;
send_command_to_vvc(vvc_target);
end procedure;
procedure insert_delay(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant delay : in time;
constant msg : in string := ""
) is
begin
insert_delay(vvc_target, vvc_instance_idx, NA, delay, msg);
end procedure;
procedure terminate_current_command(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
) is
constant proc_name : string := "terminate_current_command";
constant proc_call : string := proc_name & "(" & to_string(vvc_target, vvc_instance_idx, vvc_channel) -- First part common for all
& ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(vvc_target, vvc_instance_idx, vvc_channel, proc_call, msg, IMMEDIATE, TERMINATE_CURRENT_COMMAND);
send_command_to_vvc(vvc_target);
end procedure;
procedure terminate_all_commands(
signal vvc_target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
) is
begin
flush_command_queue(vvc_target, vvc_instance_idx, vvc_channel,msg);
terminate_current_command(vvc_target, vvc_instance_idx, vvc_channel, msg);
end procedure;
-- Returns the index of the last queued command
impure function get_last_received_cmd_idx(
signal vvc_target : in t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel := NA;
constant msg : in string := ""
) return natural is
variable v_cmd_idx : integer := -1;
begin
v_cmd_idx := shared_vvc_last_received_cmd_idx(vvc_channel, vvc_instance_idx);
check_value(v_cmd_idx /= -1, tb_error, "Channel " & to_string(vvc_channel) & " not supported on VVC " & vvc_target.vvc_name, C_SCOPE, ID_NEVER);
if v_cmd_idx /= -1 then
return v_cmd_idx;
else
-- return 0 in case of failure
return 0;
end if;
end function;
end package body td_vvc_framework_common_methods_pkg;
|
entity Controller_2 is
port(
Rb,Reset,Eq,D7,D711,D2312,CLK:in bit;
State_debug:out integer range 0 to 3;
Sp,Roll,Win,Lose,Clear:out bit:='0');
end entity Controller_2;
architecture Behavior of Controller_2 is
signal State,NextState:integer range 0 to 3:=0;
begin
State_debug<=State;
process(Rb,Reset,State,Eq,D7,D711,D2312)
begin
--Roll<=Rb;
case State is
when 0 =>
if(D711='1')then Win<='1';NextState<=2;
elsif(D2312='1') then Lose<='1';NextState<=3;
else NextState<=1;Sp<='1';
end if;
when 2=>
if(Reset='1') then Win<='0';Lose<='0';NextState<=0;Sp<='0';--Clear<='1';
end if;
when 3=>
if(Reset='1') then Lose<='0';Win<='0';NextState<=0;Sp<='0';--Clear<='1';
end if;
when 1=>
if(Eq='1')then Win<='1' ;NextState<=2;
elsif(D7='1')then Lose<='1';NextState<=3;
end if;
end case;
end process;
Roll<=Rb;
Clear<='1' when Reset='1' and (State=2 or State=3) else '0';
process(CLK)
begin
if CLK'event and CLK = '1' then
State <= NextState;
end if;
end process;
end architecture Behavior;
|
-- NEED RESULT: ARCH00022: Unassociated scalar ports with globally static subtype take on default expression passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00022
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (2)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00022)
-- ENT00022_Test_Bench(ARCH00022_Test_Bench)
--
-- REVISION HISTORY:
--
-- 26-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00022 of GENERIC_STANDARD_TYPES is
begin
L1 :
block
port (
i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
i_character_1, i_character_2 : character
:= c_character_1 ;
i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
i_time_1, i_time_2 : time
:= c_time_1 ;
i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
i_real_1, i_real_2 : real
:= c_real_1 ;
i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1
) ;
port map (
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open
) ;
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_boolean_1 = c_boolean_1
and i_boolean_2 = c_boolean_1 ;
correct := correct and i_bit_1 = c_bit_1
and i_bit_2 = c_bit_1 ;
correct := correct and i_severity_level_1 = c_severity_level_1
and i_severity_level_2 = c_severity_level_1 ;
correct := correct and i_character_1 = c_character_1
and i_character_2 = c_character_1 ;
correct := correct and i_t_enum1_1 = c_t_enum1_1
and i_t_enum1_2 = c_t_enum1_1 ;
correct := correct and i_st_enum1_1 = c_st_enum1_1
and i_st_enum1_2 = c_st_enum1_1 ;
correct := correct and i_integer_1 = c_integer_1
and i_integer_2 = c_integer_1 ;
correct := correct and i_t_int1_1 = c_t_int1_1
and i_t_int1_2 = c_t_int1_1 ;
correct := correct and i_st_int1_1 = c_st_int1_1
and i_st_int1_2 = c_st_int1_1 ;
correct := correct and i_time_1 = c_time_1
and i_time_2 = c_time_1 ;
correct := correct and i_t_phys1_1 = c_t_phys1_1
and i_t_phys1_2 = c_t_phys1_1 ;
correct := correct and i_st_phys1_1 = c_st_phys1_1
and i_st_phys1_2 = c_st_phys1_1 ;
correct := correct and i_real_1 = c_real_1
and i_real_2 = c_real_1 ;
correct := correct and i_t_real1_1 = c_t_real1_1
and i_t_real1_2 = c_t_real1_1 ;
correct := correct and i_st_real1_1 = c_st_real1_1
and i_st_real1_2 = c_st_real1_1 ;
test_report ( "ARCH00022" ,
"Unassociated scalar ports with globally static subtype" &
" take on default expression" ,
correct) ;
wait ;
end process ;
end block L1 ;
end ARCH00022 ;
--
entity ENT00022_Test_Bench is
end ENT00022_Test_Bench ;
--
architecture ARCH00022_Test_Bench of ENT00022_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00022 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00022_Test_Bench ;
|
----------------------------------------------------------------------------------
-- Company: UMASS DARTMOUTH
-- Engineer: Christopher Parks ([email protected])
--
-- Create Date: 15:30:00 04/22/2016
-- Module Name: jump_unit - Behavioral
-- Target Devices: Spartan3E XC3S500E-4FG320
-- Description:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity jump_unit is
Port ( CLK : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR (3 downto 0);
CCR : in STD_LOGIC_VECTOR(3 downto 0);
MASK : in STD_LOGIC_VECTOR (3 downto 0);
IMMD : in STD_LOGIC_VECTOR (15 downto 0);
BRSIG : out STD_LOGIC);
end jump_unit;
architecture Combinational of jump_unit is
begin
BRSIG <= '1' when OP = x"F" and MASK = CCR else
'0';
end Combinational;
|
----------------------------------------------------------------------------------
-- Company: UMASS DARTMOUTH
-- Engineer: Christopher Parks ([email protected])
--
-- Create Date: 15:30:00 04/22/2016
-- Module Name: jump_unit - Behavioral
-- Target Devices: Spartan3E XC3S500E-4FG320
-- Description:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity jump_unit is
Port ( CLK : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR (3 downto 0);
CCR : in STD_LOGIC_VECTOR(3 downto 0);
MASK : in STD_LOGIC_VECTOR (3 downto 0);
IMMD : in STD_LOGIC_VECTOR (15 downto 0);
BRSIG : out STD_LOGIC);
end jump_unit;
architecture Combinational of jump_unit is
begin
BRSIG <= '1' when OP = x"F" and MASK = CCR else
'0';
end Combinational;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Sat Jun 4 16:53:15 2016
-- Host : Dries007-Arch running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/ClockDivider/ClockDivider_sim_netlist.vhdl
-- Design : ClockDivider
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ClockDivider_ClockDivider_clk_wiz is
port (
clk : in STD_LOGIC;
clk_vga : out STD_LOGIC;
clk_cpu : out STD_LOGIC;
clk_2cpu : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ClockDivider_ClockDivider_clk_wiz : entity is "ClockDivider_clk_wiz";
end ClockDivider_ClockDivider_clk_wiz;
architecture STRUCTURE of ClockDivider_ClockDivider_clk_wiz is
signal clk_2cpu_ClockDivider : STD_LOGIC;
signal clk_ClockDivider : STD_LOGIC;
signal clk_cpu_ClockDivider : STD_LOGIC;
signal clk_vga_ClockDivider : STD_LOGIC;
signal clkfbout_ClockDivider : STD_LOGIC;
signal clkfbout_buf_ClockDivider : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_ClockDivider,
O => clkfbout_buf_ClockDivider
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk,
O => clk_ClockDivider
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_vga_ClockDivider,
O => clk_vga
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_cpu_ClockDivider,
O => clk_cpu
);
clkout3_buf: unisim.vcomponents.BUFG
port map (
I => clk_2cpu_ClockDivider,
O => clk_2cpu
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 54.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 10.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 120,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 60,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_ClockDivider,
CLKFBOUT => clkfbout_ClockDivider,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_ClockDivider,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_vga_ClockDivider,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk_cpu_ClockDivider,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => clk_2cpu_ClockDivider,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ClockDivider is
port (
clk : in STD_LOGIC;
clk_vga : out STD_LOGIC;
clk_cpu : out STD_LOGIC;
clk_2cpu : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ClockDivider : entity is true;
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of ClockDivider : entity is "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=3,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end ClockDivider;
architecture STRUCTURE of ClockDivider is
begin
inst: entity work.ClockDivider_ClockDivider_clk_wiz
port map (
clk => clk,
clk_2cpu => clk_2cpu,
clk_cpu => clk_cpu,
clk_vga => clk_vga
);
end STRUCTURE;
|
-- file: clk_video_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___192.969______0.000______50.0______237.070____275.507
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_video_clk_wiz is
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_193MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_video_clk_wiz;
architecture xilinx of clk_video_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_100MHz_clk_video : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_clk_video : std_logic;
signal clkfbout_buf_clk_video : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_193MHz_clk_video : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_bufg : BUFG
port map
(O => clk_100MHz_clk_video,
I => clk_100MHz);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 4,
CLKFBOUT_MULT_F => 30.875,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 4.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_clk_video,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_193MHz_clk_video,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_clk_video,
CLKIN1 => clk_100MHz_clk_video,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
locked <= locked_int;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_clk_video,
I => clkfbout_clk_video);
clkout1_buf : BUFG
port map
(O => clk_193MHz,
I => clk_193MHz_clk_video);
end xilinx;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1775.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b02x00p11n01i01775ent IS
END c09s05b02x00p11n01i01775ent;
ARCHITECTURE c09s05b02x00p11n01i01775arch OF c09s05b02x00p11n01i01775ent IS
signal i : integer := 21;
signal j : boolean ;
BEGIN
with i select
j <= transport
TRUE when 1 to 19, -- No_failure_here
-- Valid expression for a choice
FALSE when 20 to 29,
TRUE when 30 to 49,
FALSE when others;
TESTING: PROCESS(j)
BEGIN
assert NOT(j = FALSE)
report "***PASSED TEST: c09s05b02x00p11n01i01775"
severity NOTE;
assert (j = FALSE)
report "***FAILED TEST: c09s05b02x00p11n01i01775 - Each value of the type of the select expression should be represented once and exactly once."
severity ERROR;
END PROCESS TESTING;
END c09s05b02x00p11n01i01775arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1775.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b02x00p11n01i01775ent IS
END c09s05b02x00p11n01i01775ent;
ARCHITECTURE c09s05b02x00p11n01i01775arch OF c09s05b02x00p11n01i01775ent IS
signal i : integer := 21;
signal j : boolean ;
BEGIN
with i select
j <= transport
TRUE when 1 to 19, -- No_failure_here
-- Valid expression for a choice
FALSE when 20 to 29,
TRUE when 30 to 49,
FALSE when others;
TESTING: PROCESS(j)
BEGIN
assert NOT(j = FALSE)
report "***PASSED TEST: c09s05b02x00p11n01i01775"
severity NOTE;
assert (j = FALSE)
report "***FAILED TEST: c09s05b02x00p11n01i01775 - Each value of the type of the select expression should be represented once and exactly once."
severity ERROR;
END PROCESS TESTING;
END c09s05b02x00p11n01i01775arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1775.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b02x00p11n01i01775ent IS
END c09s05b02x00p11n01i01775ent;
ARCHITECTURE c09s05b02x00p11n01i01775arch OF c09s05b02x00p11n01i01775ent IS
signal i : integer := 21;
signal j : boolean ;
BEGIN
with i select
j <= transport
TRUE when 1 to 19, -- No_failure_here
-- Valid expression for a choice
FALSE when 20 to 29,
TRUE when 30 to 49,
FALSE when others;
TESTING: PROCESS(j)
BEGIN
assert NOT(j = FALSE)
report "***PASSED TEST: c09s05b02x00p11n01i01775"
severity NOTE;
assert (j = FALSE)
report "***FAILED TEST: c09s05b02x00p11n01i01775 - Each value of the type of the select expression should be represented once and exactly once."
severity ERROR;
END PROCESS TESTING;
END c09s05b02x00p11n01i01775arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1218.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p26n03i01218ent IS
END c08s01b00x00p26n03i01218ent;
ARCHITECTURE c08s01b00x00p26n03i01218arch OF c08s01b00x00p26n03i01218ent IS
signal I : bit := '0';
BEGIN
TESTING: PROCESS
constant t1 : time := 100 ns;
constant t2 : time := 10 ns;
BEGIN
I <= '1' after 200 ns;
wait on I for (t1 - t2);
assert NOT( I = '0' )
report "***PASSED TEST: c08s01b00x00p26n03i01218"
severity NOTE;
assert ( I = '0' )
report "***FAILED TEST: c08s01b00x00p26n03i01218 - The FOR clause in a WAIT statement must evaluate to a positive value."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p26n03i01218arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1218.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p26n03i01218ent IS
END c08s01b00x00p26n03i01218ent;
ARCHITECTURE c08s01b00x00p26n03i01218arch OF c08s01b00x00p26n03i01218ent IS
signal I : bit := '0';
BEGIN
TESTING: PROCESS
constant t1 : time := 100 ns;
constant t2 : time := 10 ns;
BEGIN
I <= '1' after 200 ns;
wait on I for (t1 - t2);
assert NOT( I = '0' )
report "***PASSED TEST: c08s01b00x00p26n03i01218"
severity NOTE;
assert ( I = '0' )
report "***FAILED TEST: c08s01b00x00p26n03i01218 - The FOR clause in a WAIT statement must evaluate to a positive value."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p26n03i01218arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1218.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p26n03i01218ent IS
END c08s01b00x00p26n03i01218ent;
ARCHITECTURE c08s01b00x00p26n03i01218arch OF c08s01b00x00p26n03i01218ent IS
signal I : bit := '0';
BEGIN
TESTING: PROCESS
constant t1 : time := 100 ns;
constant t2 : time := 10 ns;
BEGIN
I <= '1' after 200 ns;
wait on I for (t1 - t2);
assert NOT( I = '0' )
report "***PASSED TEST: c08s01b00x00p26n03i01218"
severity NOTE;
assert ( I = '0' )
report "***FAILED TEST: c08s01b00x00p26n03i01218 - The FOR clause in a WAIT statement must evaluate to a positive value."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p26n03i01218arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
error : out std_ulogic;
address : out std_logic_vector(19 downto 2);
data : inout std_logic_vector(31 downto 0);
ramsn : out std_logic_vector (1 downto 0);
mben : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
pio : inout std_logic_vector(17 downto 0); -- I/O port
-- switch : in std_logic_vector(7 downto 0); -- switches
-- button : in std_logic_vector(2 downto 0); -- buttons
ps2clk : inout std_logic;
ps2data : inout std_logic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic;
vid_g : out std_logic;
vid_b : out std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+
CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, nerror : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, rst : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clkval : std_logic_vector(1 downto 0);
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 0;
signal stati : ahbstat_in_type;
signal dac_clk, clk1x, vid_clock, video_clk, clkvga : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
nerror <= not dbgo(0).error;
error_pad : outpad generic map (tech => padtech) port map (error, nerror);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- dcomgen : if CFG_AHB_UART = 1 generate
-- dcom0: ahbuart -- Debug UART
-- generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
-- port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
-- end generate;
-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
rommask => 16#000#, iomask => 16#000#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 18, tech => padtech)
port map (address, memo.address(19 downto 2));
ramsa_pad : outpad generic map (tech => padtech)
port map (ramsn(0), memo.ramsn(0));
ramsb_pad : outpad generic map (tech => padtech)
port map (ramsn(1), memo.ramsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
mben_pads : outpadv generic map (tech => padtech, width => 4)
port map (mben, memo.mben);
data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (data, memo.data(31 downto 0),
memo.vbdrive(31 downto 0), memi.data(31 downto 0));
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, dac_clk);
dac_clk <= not video_clk;
b1 : techbuf generic map (2, virtex2) port map (clkval(0), video_clk);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
clkvga <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (clkvga, video_clk);
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 20000, clk2 => 25000)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_JTAG), clk_sel);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, dac_clk);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpad generic map (tech => padtech)
port map (vid_r, vgao.video_out_r(7));
video_out_g_pad : outpad generic map (tech => padtech)
port map (vid_g, vgao.video_out_g(7));
video_out_b_pad : outpad generic map (tech => padtech)
port map (vid_b, vgao.video_out_b(7));
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => 18)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
pio_pads : iopadvv generic map (width => 18, tech => padtech)
port map (pio, gpioo.dout(17 downto 0), gpioo.oen(17 downto 0),
gpioi.din(17 downto 0));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+FG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Digilent XC3S1000 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
library IEEE;
use ieee.std_logic_1164.all;
entity test_bench_sign_extend is
end test_bench_sign_extend;
architecture behav of test_bench_sign_extend is
component sign_extend
port(
instr15_0 : in std_logic_vector(15 downto 0);
clk, rst, pre, ce : in std_logic;
output : out std_logic_vector(31 downto 0));
end component;
--Inputs
signal instr15_0 : std_logic_vector(15 downto 0) := (others => '0');
signal clk, rst, pre, ce : std_logic :='0';
--Outputs
signal output : std_logic_vector(31 downto 0);
begin
test_bench: sign_extend port map(
instr15_0 => instr15_0,
clk => clk,
rst => rst,
pre => pre,
ce => ce,
output => output
);
stim_proc: process
begin
wait for 50 ns;
instr15_0 <= "0110000000011111";
clk <= '1';
rst <= '0';
pre <= '0';
ce <= '1';
wait;
end process;
end; |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: tsotnep:userLibrary:audio_mixer:1.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY week1_audio_mixer_0_0 IS
PORT (
audio_mixed_a_b_left_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_mixed_a_b_right_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_a_left_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_a_right_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_b_left_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_b_right_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END week1_audio_mixer_0_0;
ARCHITECTURE week1_audio_mixer_0_0_arch OF week1_audio_mixer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF week1_audio_mixer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT top_level IS
GENERIC (
size : INTEGER
);
PORT (
audio_mixed_a_b_left_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_mixed_a_b_right_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_a_left_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_a_right_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_b_left_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
audio_channel_b_right_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT top_level;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF week1_audio_mixer_0_0_arch: ARCHITECTURE IS "top_level,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF week1_audio_mixer_0_0_arch : ARCHITECTURE IS "week1_audio_mixer_0_0,top_level,{}";
BEGIN
U0 : top_level
GENERIC MAP (
size => 24
)
PORT MAP (
audio_mixed_a_b_left_out => audio_mixed_a_b_left_out,
audio_mixed_a_b_right_out => audio_mixed_a_b_right_out,
audio_channel_a_left_in => audio_channel_a_left_in,
audio_channel_a_right_in => audio_channel_a_right_in,
audio_channel_b_left_in => audio_channel_b_left_in,
audio_channel_b_right_in => audio_channel_b_right_in
);
END week1_audio_mixer_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity rom_constant is
port (
clk : in std_logic;
a : out std_logic_vector(7 downto 0)
);
end rom_constant;
architecture rtl of rom_constant is
constant C_IEND : std_logic_vector(12*8-1 downto 0) := (others => '1');
signal index : integer := 0;
begin
process(clk)
begin
if rising_edge(clk) then
a <= C_IEND(index*8-1 downto (index-1)*8);
if index < 12 then
index <= index + 1;
else
index <= 0;
end if;
end if;
end process;
end rtl;
|
-- $Id: tb_nexys4d_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4d_dram - sim
-- Description: Test bench for nexys4d (base+dram)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_nexys4d_core
-- serport/tb/serport_master_tb
-- nexys4d_dram_aif [UUT]
--
-- To test: generic, any nexys4d_dram_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2016.2-2018.2; ghdl 0.33-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-30 1099 1.0 Initial version (derived from tb_nexys4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys4dlib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys4d_dram is
end tb_nexys4d_dram;
architecture sim of tb_nexys4d_dram is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal IO_DDR2_DQ : slv16 := (others=>'Z');
signal IO_DDR2_DQS_P : slv2 := (others=>'Z');
signal IO_DDR2_DQS_N : slv2 := (others=>'Z');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N4CORE : entity work.tb_nexys4d_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
UUT : nexys4d_dram_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
DDR2_DQ => IO_DDR2_DQ,
DDR2_DQS_P => IO_DDR2_DQS_P,
DDR2_DQS_N => IO_DDR2_DQS_N,
DDR2_ADDR => open,
DDR2_BA => open,
DDR2_RAS_N => open,
DDR2_CAS_N => open,
DDR2_WE_N => open,
DDR2_CK_P => open,
DDR2_CK_N => open,
DDR2_CKE => open,
DDR2_CS_N => open,
DDR2_DM => open,
DDR2_ODT => open
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rx_bridge_fifo.vhd when simulating
-- the core, rx_bridge_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rx_bridge_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END rx_bridge_fifo;
ARCHITECTURE rx_bridge_fifo_a OF rx_bridge_fifo IS
-- synthesis translate_off
COMPONENT wrapped_rx_bridge_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rx_bridge_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 11,
c_default_value => "BlankString",
c_din_width => 32,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 32,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "2kx18",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 3,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 2047,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 2046,
c_prog_full_type => 3,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 11,
c_rd_depth => 2048,
c_rd_freq => 1,
c_rd_pntr_width => 11,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 11,
c_wr_depth => 2048,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 11,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rx_bridge_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => prog_empty_thresh,
prog_full_thresh => prog_full_thresh,
dout => dout,
full => full,
empty => empty,
prog_full => prog_full,
prog_empty => prog_empty
);
-- synthesis translate_on
END rx_bridge_fifo_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rx_bridge_fifo.vhd when simulating
-- the core, rx_bridge_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rx_bridge_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END rx_bridge_fifo;
ARCHITECTURE rx_bridge_fifo_a OF rx_bridge_fifo IS
-- synthesis translate_off
COMPONENT wrapped_rx_bridge_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rx_bridge_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 11,
c_default_value => "BlankString",
c_din_width => 32,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 32,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "2kx18",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 3,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 2047,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 2046,
c_prog_full_type => 3,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 11,
c_rd_depth => 2048,
c_rd_freq => 1,
c_rd_pntr_width => 11,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 11,
c_wr_depth => 2048,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 11,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rx_bridge_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => prog_empty_thresh,
prog_full_thresh => prog_full_thresh,
dout => dout,
full => full,
empty => empty,
prog_full => prog_full,
prog_empty => prog_empty
);
-- synthesis translate_on
END rx_bridge_fifo_a;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY DEFENDER_BROM IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END DEFENDER_BROM;
ARCHITECTURE DEFENDER_BROM_arch OF DEFENDER_BROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DEFENDER_BROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DEFENDER_BROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DEFENDER_BROM_arch : ARCHITECTURE IS "DEFENDER_BROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DEFENDER_BROM_arch: ARCHITECTURE IS "DEFENDER_BROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=DEFENDER_BROM.mif,C_INIT_FILE=DEFENDER_BROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=4096,C_READ_DEPTH_A=4096,C_ADDRA_WIDTH=12,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=4096,C_READ_DEPTH_B=4096,C_ADDRB_WIDTH=12,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "DEFENDER_BROM.mif",
C_INIT_FILE => "DEFENDER_BROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 4096,
C_READ_DEPTH_A => 4096,
C_ADDRA_WIDTH => 12,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 4096,
C_READ_DEPTH_B => 4096,
C_ADDRB_WIDTH => 12,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END DEFENDER_BROM_arch;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_594 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_594;
architecture augh of mul_594 is
signal tmp_res : signed(46 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_594 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_594;
architecture augh of mul_594 is
signal tmp_res : signed(46 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
-------------------------------------------------------------------------------
-- Title : Synchronizer chain
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : gc_sync_ffs.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-06-14
-- Last update: 2014-07-31
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Synchronizer chain and edge detector.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 - 2010 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-06-14 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity gc_sync_ffs is
generic(
g_sync_edge : string := "positive"
);
port(
clk_i : in std_logic; -- clock from the destination clock domain
rst_n_i : in std_logic; -- reset
data_i : in std_logic; -- async input
synced_o : out std_logic; -- synchronized output
npulse_o : out std_logic; -- negative edge detect output (single-clock
-- pulse)
ppulse_o : out std_logic -- positive edge detect output (single-clock
-- pulse)
);
end gc_sync_ffs;
architecture behavioral of gc_sync_ffs is
signal sync0, sync1, sync2 : std_logic;
attribute shreg_extract : string;
attribute shreg_extract of sync0 : signal is "no";
attribute shreg_extract of sync1 : signal is "no";
attribute shreg_extract of sync2 : signal is "no";
attribute keep : string;
attribute keep of sync0 : signal is "true";
attribute keep of sync1 : signal is "true";
begin
sync_posedge : if (g_sync_edge = "positive") generate
process(clk_i, rst_n_i)
begin
if(rst_n_i = '0') then
sync0 <= '0';
sync1 <= '0';
sync2 <= '0';
synced_o <= '0';
npulse_o <= '0';
ppulse_o <= '0';
elsif rising_edge(clk_i) then
sync0 <= data_i;
sync1 <= sync0;
sync2 <= sync1;
synced_o <= sync1;
npulse_o <= sync2 and not sync1;
ppulse_o <= not sync2 and sync1;
end if;
end process;
end generate sync_posedge;
sync_negedge : if(g_sync_edge = "negative") generate
process(clk_i, rst_n_i)
begin
if(rst_n_i = '0') then
sync0 <= '0';
sync1 <= '0';
sync2 <= '0';
synced_o <= '0';
npulse_o <= '0';
ppulse_o <= '0';
elsif falling_edge(clk_i) then
sync0 <= data_i;
sync1 <= sync0;
sync2 <= sync1;
synced_o <= sync1;
npulse_o <= sync2 and not sync1;
ppulse_o <= not sync2 and sync1;
end if;
end process;
end generate sync_negedge;
end behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1373.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01373ent IS
END c08s05b00x00p03n01i01373ent;
ARCHITECTURE c08s05b00x00p03n01i01373arch OF c08s05b00x00p03n01i01373ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr2 : st_arr2 := c_st_arr2_1 ;
--
BEGIN
v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01373"
severity NOTE;
assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01373 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01373arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1373.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01373ent IS
END c08s05b00x00p03n01i01373ent;
ARCHITECTURE c08s05b00x00p03n01i01373arch OF c08s05b00x00p03n01i01373ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr2 : st_arr2 := c_st_arr2_1 ;
--
BEGIN
v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01373"
severity NOTE;
assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01373 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01373arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1373.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01373ent IS
END c08s05b00x00p03n01i01373ent;
ARCHITECTURE c08s05b00x00p03n01i01373arch OF c08s05b00x00p03n01i01373ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr2 : st_arr2 := c_st_arr2_1 ;
--
BEGIN
v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01373"
severity NOTE;
assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01373 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01373arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:33:27 11/15/2013
-- Design Name:
-- Module Name: ShiftRegister - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ShiftRegister is
Port ( Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
Enable : in STD_LOGIC;
D : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end ShiftRegister;
architecture Behavioral of ShiftRegister is
signal q_i : std_logic_vector (7 downto 0);
begin
PROCESS (clk, reset)
BEGIN
IF reset = '0' THEN
q_i <= "00000000";
ELSIF clk'event AND clk='1' THEN
IF enable = '1' THEN
q_i <= D & q_i(7 downto 1);
ELSE
q_i <= q_i;
END IF;
END IF;
END PROCESS;
Q <= q_i;
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- simple module that connects the buttons on our Master 21EDA board.
-- based on labs from Altera
-- ftp://ftp.altera.com/up/pub/Altera_Material/11.1/Laboratory_Exercises/Digital_Logic/DE2/vhdl/lab2_VHDL.pdf
ENTITY part1 IS
PORT (SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- (3)=A, (2)=B, (1)=C, (0)=D
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
ENABLE : OUT STD_LOGIC); -- segments of our displays
END part1;
ARCHITECTURE Behavior OF part1 IS
BEGIN
ENABLE <= '0';
-- SEG A : F0 = A B C D' + B' C D + A' C' + A' B' ;
LEDSEG(0) <= (SW(3) AND SW(2) AND SW(1) AND NOT SW(0)) OR
(NOT SW(2) AND SW(1) AND SW(0)) OR
(NOT SW(3) AND NOT SW(1)) OR
(NOT SW(3) AND NOT SW(2));
-- SEG B : F1 = B' C D' + A' C' + B' C' D + A' B' ;
LEDSEG(1) <= (NOT SW(2) AND SW(1) AND NOT SW(0)) OR
(NOT SW(3) AND NOT SW(1)) OR
(NOT SW(2) AND NOT SW(1) AND SW (0)) OR
(NOT SW(3) AND NOT SW(2));
-- SEG C : F2 = B C' D + A' B' + A' C' ;
LEDSEG(2) <= (SW(2) AND NOT SW(1) AND SW(0)) OR
(NOT SW(3) AND NOT SW(2)) OR
(NOT SW(3) AND NOT SW(1));
-- SEG D : F3 = A' D' + B C D' + B' C D + B' C' D' + A' C' ;
LEDSEG(3) <= (NOT SW(3) AND NOT SW(0)) OR
(SW(2) AND SW(1) AND NOT SW(0)) OR
(NOT SW(2) AND SW(1) AND SW(0)) OR
(NOT SW(2) AND NOT SW(1) AND NOT SW(0)) OR
(NOT SW(3) AND NOT SW(1));
-- SEG E : F4 = A' C' + B' C + D';
LEDSEG(4) <= (NOT SW(3) AND NOT SW(1)) OR
(NOT SW(2) AND SW(1)) OR
(NOT SW(0));
-- SEG F : F5 = A B D' + A' B' + B C' + C' D';
LEDSEG(5) <= (SW(3) AND SW(2) AND NOT SW(0)) OR
(NOT SW(3) AND NOT SW(2)) OR
(SW(2) AND NOT SW(1)) OR
(NOT SW(1) AND NOT SW(0));
-- SED G : A B C + B' C' D' + A' C' + A' B' ;
LEDSEG(6) <= (SW(3) AND SW(2) AND SW(1)) OR
(NOT SW(2) AND NOT SW(1) AND NOT SW(0)) OR
(NOT SW(3) AND NOT SW(1)) OR
(NOT SW(3) AND NOT SW(2));
END Behavior; |
entity ent is
end entity;
architecture a of ent is
begin
main : process is
begin
report to_string(1);
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process is
begin
report to_string(1);
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process is
begin
report to_string(1);
wait;
end process;
end architecture;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_dec_flechas IS
END tb_dec_flechas;
ARCHITECTURE behavior OF tb_dec_flechas IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dec_flechas
PORT(
action : IN std_logic_vector(1 downto 0);
led_flechas : OUT std_logic_vector(6 downto 0);
flecha_ctrl : OUT std_logic
);
END COMPONENT;
--Inputs
signal action : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal led_flechas : std_logic_vector(6 downto 0);
signal flecha_ctrl : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: dec_flechas PORT MAP (
action => action,
led_flechas => led_flechas,
flecha_ctrl => flecha_ctrl
);
-- Stimulus process
stim_proc: process
begin
-- insert stimulus here
action <= "00";
WAIT FOR 20 ns;
action <= "01";
WAIT FOR 20 ns;
action <= "10";
WAIT FOR 20 ns;
action <= "11";
WAIT FOR 20 ns;
action <= "01";
WAIT FOR 20 ns;
ASSERT false
REPORT "Simulación finalizada. Test superado."
SEVERITY FAILURE;
wait;
end process;
END;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_2_block4.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block4
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_2_block4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_11 : IN std_logic; -- ufix1
dout_4_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_12_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_12_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_11_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_11_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_12_re_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_12_im_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block4;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block4 IS
-- Signals
SIGNAL dout_4_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_4_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_12_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_12_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_11_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_11_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_12_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_12_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
dout_4_re_signed <= signed(dout_4_re);
dout_4_im_signed <= signed(dout_4_im);
dout_12_re_signed <= signed(dout_12_re);
dout_12_im_signed <= signed(dout_12_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 18);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_4_re_signed, dout_4_im_signed,
dout_12_re_signed, dout_12_im_signed, dout_1_vld, rotate_11)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_11 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_4_re_signed, 18) + resize(dout_12_im_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_4_re_signed, 18) - resize(dout_12_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_4_im_signed, 18) + resize(dout_12_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_4_im_signed, 18) - resize(dout_12_re_signed, 18);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_4_re_signed, 18) + resize(dout_12_re_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_4_re_signed, 18) - resize(dout_12_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_4_im_signed, 18) + resize(dout_12_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_4_im_signed, 18) - resize(dout_12_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_11_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_11_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_12_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_12_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_11_re <= std_logic_vector(dout_11_re_tmp);
dout_11_im <= std_logic_vector(dout_11_im_tmp);
dout_12_re_1 <= std_logic_vector(dout_12_re_tmp);
dout_12_im_1 <= std_logic_vector(dout_12_im_tmp);
END rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\lms_pcore.vhd
-- Created: 2015-06-19 16:39:46
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: -1
-- Target subsystem base rate: -1
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: lms_pcore
-- Source Path: lms_pcore
-- Hierarchy Level: 0
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY lms_pcore IS
PORT( IPCORE_CLK : IN std_logic; -- ufix1
IPCORE_RESETN : IN std_logic; -- ufix1
AXI4_Lite_ACLK : IN std_logic; -- ufix1
AXI4_Lite_ARESETN : IN std_logic; -- ufix1
AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_AWVALID : IN std_logic; -- ufix1
AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4
AXI4_Lite_WVALID : IN std_logic; -- ufix1
AXI4_Lite_BREADY : IN std_logic; -- ufix1
AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_ARVALID : IN std_logic; -- ufix1
AXI4_Lite_RREADY : IN std_logic; -- ufix1
AXI4_Lite_AWREADY : OUT std_logic; -- ufix1
AXI4_Lite_WREADY : OUT std_logic; -- ufix1
AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_BVALID : OUT std_logic; -- ufix1
AXI4_Lite_ARREADY : OUT std_logic; -- ufix1
AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_RVALID : OUT std_logic -- ufix1
);
END lms_pcore;
ARCHITECTURE rtl OF lms_pcore IS
-- Component Declarations
COMPONENT lms_pcore_dut
PORT( clk : IN std_logic; -- ufix1
reset : IN std_logic;
dut_enable : IN std_logic; -- ufix1
x_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
d_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
ce_out : OUT std_logic; -- ufix1
e_k : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END COMPONENT;
COMPONENT lms_pcore_cop
PORT( clk : IN std_logic; -- ufix1
reset : IN std_logic;
in_strobe : IN std_logic; -- ufix1
cop_enable : IN std_logic; -- ufix1
out_ready : OUT std_logic; -- ufix1
dut_enable : OUT std_logic; -- ufix1
reg_strobe : OUT std_logic -- ufix1
);
END COMPONENT;
COMPONENT lms_pcore_axi_lite
PORT( reset : IN std_logic;
AXI4_Lite_ACLK : IN std_logic; -- ufix1
AXI4_Lite_ARESETN : IN std_logic; -- ufix1
AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_AWVALID : IN std_logic; -- ufix1
AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4
AXI4_Lite_WVALID : IN std_logic; -- ufix1
AXI4_Lite_BREADY : IN std_logic; -- ufix1
AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_ARVALID : IN std_logic; -- ufix1
AXI4_Lite_RREADY : IN std_logic; -- ufix1
read_cop_out_ready : IN std_logic; -- ufix1
cop_reg_strobe : IN std_logic; -- ufix1
read_e_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
AXI4_Lite_AWREADY : OUT std_logic; -- ufix1
AXI4_Lite_WREADY : OUT std_logic; -- ufix1
AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_BVALID : OUT std_logic; -- ufix1
AXI4_Lite_ARREADY : OUT std_logic; -- ufix1
AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_RVALID : OUT std_logic; -- ufix1
write_axi_enable : OUT std_logic; -- ufix1
strobe_cop_in_strobe : OUT std_logic; -- ufix1
write_x_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
write_d_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
reset_internal : OUT std_logic -- ufix1
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : lms_pcore_dut
USE ENTITY work.lms_pcore_dut(rtl);
FOR ALL : lms_pcore_cop
USE ENTITY work.lms_pcore_cop(rtl);
FOR ALL : lms_pcore_axi_lite
USE ENTITY work.lms_pcore_axi_lite(rtl);
-- Signals
SIGNAL reset : std_logic;
SIGNAL reset_cm : std_logic; -- ufix1
SIGNAL cop_dut_enable : std_logic; -- ufix1
SIGNAL write_x_k : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL write_d_k : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL ce_out_sig : std_logic; -- ufix1
SIGNAL e_k_sig : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL reset_internal : std_logic; -- ufix1
SIGNAL strobe_cop_in_strobe : std_logic; -- ufix1
SIGNAL write_axi_enable : std_logic; -- ufix1
SIGNAL cop_out_ready : std_logic; -- ufix1
SIGNAL cop_reg_strobe : std_logic; -- ufix1
SIGNAL AXI4_Lite_BRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2
SIGNAL AXI4_Lite_RDATA_tmp : std_logic_vector(31 DOWNTO 0); -- ufix32
SIGNAL AXI4_Lite_RRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2
BEGIN
u_lms_pcore_dut_inst : lms_pcore_dut
PORT MAP( clk => IPCORE_CLK, -- ufix1
reset => reset,
dut_enable => cop_dut_enable, -- ufix1
x_k => write_x_k, -- sfix16_En14
d_k => write_d_k, -- sfix16_En14
ce_out => ce_out_sig, -- ufix1
e_k => e_k_sig -- sfix16_En14
);
u_lms_pcore_cop_inst : lms_pcore_cop
PORT MAP( clk => IPCORE_CLK, -- ufix1
reset => reset,
in_strobe => strobe_cop_in_strobe, -- ufix1
cop_enable => write_axi_enable, -- ufix1
out_ready => cop_out_ready, -- ufix1
dut_enable => cop_dut_enable, -- ufix1
reg_strobe => cop_reg_strobe -- ufix1
);
u_lms_pcore_axi_lite_inst : lms_pcore_axi_lite
PORT MAP( reset => reset,
AXI4_Lite_ACLK => AXI4_Lite_ACLK, -- ufix1
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN, -- ufix1
AXI4_Lite_AWADDR => AXI4_Lite_AWADDR, -- ufix16
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID, -- ufix1
AXI4_Lite_WDATA => AXI4_Lite_WDATA, -- ufix32
AXI4_Lite_WSTRB => AXI4_Lite_WSTRB, -- ufix4
AXI4_Lite_WVALID => AXI4_Lite_WVALID, -- ufix1
AXI4_Lite_BREADY => AXI4_Lite_BREADY, -- ufix1
AXI4_Lite_ARADDR => AXI4_Lite_ARADDR, -- ufix16
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID, -- ufix1
AXI4_Lite_RREADY => AXI4_Lite_RREADY, -- ufix1
read_cop_out_ready => cop_out_ready, -- ufix1
cop_reg_strobe => strobe_cop_in_strobe, -- ufix1
read_e_k => e_k_sig, -- sfix16_En14
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY, -- ufix1
AXI4_Lite_WREADY => AXI4_Lite_WREADY, -- ufix1
AXI4_Lite_BRESP => AXI4_Lite_BRESP_tmp, -- ufix2
AXI4_Lite_BVALID => AXI4_Lite_BVALID, -- ufix1
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY, -- ufix1
AXI4_Lite_RDATA => AXI4_Lite_RDATA_tmp, -- ufix32
AXI4_Lite_RRESP => AXI4_Lite_RRESP_tmp, -- ufix2
AXI4_Lite_RVALID => AXI4_Lite_RVALID, -- ufix1
write_axi_enable => write_axi_enable, -- ufix1
strobe_cop_in_strobe => strobe_cop_in_strobe, -- ufix1
write_x_k => write_x_k, -- sfix16_En14
write_d_k => write_d_k, -- sfix16_En14
reset_internal => reset_internal -- ufix1
);
reset_cm <= NOT IPCORE_RESETN;
reset <= reset_cm OR reset_internal;
AXI4_Lite_BRESP <= AXI4_Lite_BRESP_tmp;
AXI4_Lite_RDATA <= AXI4_Lite_RDATA_tmp;
AXI4_Lite_RRESP <= AXI4_Lite_RRESP_tmp;
END rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\lms_pcore.vhd
-- Created: 2015-06-19 16:39:46
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: -1
-- Target subsystem base rate: -1
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: lms_pcore
-- Source Path: lms_pcore
-- Hierarchy Level: 0
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY lms_pcore IS
PORT( IPCORE_CLK : IN std_logic; -- ufix1
IPCORE_RESETN : IN std_logic; -- ufix1
AXI4_Lite_ACLK : IN std_logic; -- ufix1
AXI4_Lite_ARESETN : IN std_logic; -- ufix1
AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_AWVALID : IN std_logic; -- ufix1
AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4
AXI4_Lite_WVALID : IN std_logic; -- ufix1
AXI4_Lite_BREADY : IN std_logic; -- ufix1
AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_ARVALID : IN std_logic; -- ufix1
AXI4_Lite_RREADY : IN std_logic; -- ufix1
AXI4_Lite_AWREADY : OUT std_logic; -- ufix1
AXI4_Lite_WREADY : OUT std_logic; -- ufix1
AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_BVALID : OUT std_logic; -- ufix1
AXI4_Lite_ARREADY : OUT std_logic; -- ufix1
AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_RVALID : OUT std_logic -- ufix1
);
END lms_pcore;
ARCHITECTURE rtl OF lms_pcore IS
-- Component Declarations
COMPONENT lms_pcore_dut
PORT( clk : IN std_logic; -- ufix1
reset : IN std_logic;
dut_enable : IN std_logic; -- ufix1
x_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
d_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
ce_out : OUT std_logic; -- ufix1
e_k : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END COMPONENT;
COMPONENT lms_pcore_cop
PORT( clk : IN std_logic; -- ufix1
reset : IN std_logic;
in_strobe : IN std_logic; -- ufix1
cop_enable : IN std_logic; -- ufix1
out_ready : OUT std_logic; -- ufix1
dut_enable : OUT std_logic; -- ufix1
reg_strobe : OUT std_logic -- ufix1
);
END COMPONENT;
COMPONENT lms_pcore_axi_lite
PORT( reset : IN std_logic;
AXI4_Lite_ACLK : IN std_logic; -- ufix1
AXI4_Lite_ARESETN : IN std_logic; -- ufix1
AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_AWVALID : IN std_logic; -- ufix1
AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4
AXI4_Lite_WVALID : IN std_logic; -- ufix1
AXI4_Lite_BREADY : IN std_logic; -- ufix1
AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_ARVALID : IN std_logic; -- ufix1
AXI4_Lite_RREADY : IN std_logic; -- ufix1
read_cop_out_ready : IN std_logic; -- ufix1
cop_reg_strobe : IN std_logic; -- ufix1
read_e_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
AXI4_Lite_AWREADY : OUT std_logic; -- ufix1
AXI4_Lite_WREADY : OUT std_logic; -- ufix1
AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_BVALID : OUT std_logic; -- ufix1
AXI4_Lite_ARREADY : OUT std_logic; -- ufix1
AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_RVALID : OUT std_logic; -- ufix1
write_axi_enable : OUT std_logic; -- ufix1
strobe_cop_in_strobe : OUT std_logic; -- ufix1
write_x_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
write_d_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
reset_internal : OUT std_logic -- ufix1
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : lms_pcore_dut
USE ENTITY work.lms_pcore_dut(rtl);
FOR ALL : lms_pcore_cop
USE ENTITY work.lms_pcore_cop(rtl);
FOR ALL : lms_pcore_axi_lite
USE ENTITY work.lms_pcore_axi_lite(rtl);
-- Signals
SIGNAL reset : std_logic;
SIGNAL reset_cm : std_logic; -- ufix1
SIGNAL cop_dut_enable : std_logic; -- ufix1
SIGNAL write_x_k : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL write_d_k : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL ce_out_sig : std_logic; -- ufix1
SIGNAL e_k_sig : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL reset_internal : std_logic; -- ufix1
SIGNAL strobe_cop_in_strobe : std_logic; -- ufix1
SIGNAL write_axi_enable : std_logic; -- ufix1
SIGNAL cop_out_ready : std_logic; -- ufix1
SIGNAL cop_reg_strobe : std_logic; -- ufix1
SIGNAL AXI4_Lite_BRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2
SIGNAL AXI4_Lite_RDATA_tmp : std_logic_vector(31 DOWNTO 0); -- ufix32
SIGNAL AXI4_Lite_RRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2
BEGIN
u_lms_pcore_dut_inst : lms_pcore_dut
PORT MAP( clk => IPCORE_CLK, -- ufix1
reset => reset,
dut_enable => cop_dut_enable, -- ufix1
x_k => write_x_k, -- sfix16_En14
d_k => write_d_k, -- sfix16_En14
ce_out => ce_out_sig, -- ufix1
e_k => e_k_sig -- sfix16_En14
);
u_lms_pcore_cop_inst : lms_pcore_cop
PORT MAP( clk => IPCORE_CLK, -- ufix1
reset => reset,
in_strobe => strobe_cop_in_strobe, -- ufix1
cop_enable => write_axi_enable, -- ufix1
out_ready => cop_out_ready, -- ufix1
dut_enable => cop_dut_enable, -- ufix1
reg_strobe => cop_reg_strobe -- ufix1
);
u_lms_pcore_axi_lite_inst : lms_pcore_axi_lite
PORT MAP( reset => reset,
AXI4_Lite_ACLK => AXI4_Lite_ACLK, -- ufix1
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN, -- ufix1
AXI4_Lite_AWADDR => AXI4_Lite_AWADDR, -- ufix16
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID, -- ufix1
AXI4_Lite_WDATA => AXI4_Lite_WDATA, -- ufix32
AXI4_Lite_WSTRB => AXI4_Lite_WSTRB, -- ufix4
AXI4_Lite_WVALID => AXI4_Lite_WVALID, -- ufix1
AXI4_Lite_BREADY => AXI4_Lite_BREADY, -- ufix1
AXI4_Lite_ARADDR => AXI4_Lite_ARADDR, -- ufix16
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID, -- ufix1
AXI4_Lite_RREADY => AXI4_Lite_RREADY, -- ufix1
read_cop_out_ready => cop_out_ready, -- ufix1
cop_reg_strobe => strobe_cop_in_strobe, -- ufix1
read_e_k => e_k_sig, -- sfix16_En14
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY, -- ufix1
AXI4_Lite_WREADY => AXI4_Lite_WREADY, -- ufix1
AXI4_Lite_BRESP => AXI4_Lite_BRESP_tmp, -- ufix2
AXI4_Lite_BVALID => AXI4_Lite_BVALID, -- ufix1
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY, -- ufix1
AXI4_Lite_RDATA => AXI4_Lite_RDATA_tmp, -- ufix32
AXI4_Lite_RRESP => AXI4_Lite_RRESP_tmp, -- ufix2
AXI4_Lite_RVALID => AXI4_Lite_RVALID, -- ufix1
write_axi_enable => write_axi_enable, -- ufix1
strobe_cop_in_strobe => strobe_cop_in_strobe, -- ufix1
write_x_k => write_x_k, -- sfix16_En14
write_d_k => write_d_k, -- sfix16_En14
reset_internal => reset_internal -- ufix1
);
reset_cm <= NOT IPCORE_RESETN;
reset <= reset_cm OR reset_internal;
AXI4_Lite_BRESP <= AXI4_Lite_BRESP_tmp;
AXI4_Lite_RDATA <= AXI4_Lite_RDATA_tmp;
AXI4_Lite_RRESP <= AXI4_Lite_RRESP_tmp;
END rtl;
|
-- $Id: tst_rlink_cuff.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_rlink_cuff - syn
-- Description: tester for rlink over cuff
--
-- Dependencies: vlib/rlink/rlink_core8
-- vlib/rlink/rlink_rlbmux
-- vlib/serport/serport_1clock
-- ../tst_rlink/rbd_tst_rlink
-- vlib/rbus/rb_sres_or_2
-- vlib/genlib/led_pulse_stretch
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-02 467 1.0.1 use 64 usec led pulse width
-- 2012-12-29 466 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity tst_rlink_cuff is -- tester for rlink over cuff
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RB_MREQ_TOP : out rb_mreq_type; -- rbus: request
RB_SRES_TOP : in rb_sres_type; -- rbus: response from top level
SWI : in slv8; -- hio: switches
BTN : in slv4; -- hio: buttons
LED : out slv8; -- hio: leds
DSP_DAT : out slv16; -- hio: display data
DSP_DP : out slv4; -- hio: display decimal points
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RTS_N : out slbit; -- receive rts (uart view, act.low)
CTS_N : in slbit; -- transmit cts (uart view, act.low)
FX2_RXDATA : in slv8; -- fx2: receiver data out
FX2_RXVAL : in slbit; -- fx2: receiver data valid
FX2_RXHOLD : out slbit; -- fx2: receiver data hold
FX2_TXDATA : out slv8; -- fx2: transmit data in
FX2_TXENA : out slbit; -- fx2: transmit data enable
FX2_TXBUSY : in slbit; -- fx2: transmit busy
FX2_TX2DATA : out slv8; -- fx2: transmit 2 data in
FX2_TX2ENA : out slbit; -- fx2: transmit 2 data enable
FX2_TX2BUSY : in slbit; -- fx2: transmit 2 busy
FX2_MONI : in fx2ctl_moni_type -- fx2: fx2ctl monitor
);
end tst_rlink_cuff;
architecture syn of tst_rlink_cuff is
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv3 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
signal SER_RXDATA : slv8 := (others=>'0');
signal SER_RXVAL : slbit := '0';
signal SER_RXHOLD : slbit := '0';
signal SER_TXDATA : slv8 := (others=>'0');
signal SER_TXENA : slbit := '0';
signal SER_TXBUSY : slbit := '0';
signal FX2_TX2ENA_L : slbit := '0';
signal FX2_TXENA_L : slbit := '0';
signal FX2_TX2ENA_LED : slbit := '0';
signal FX2_TXENA_LED : slbit := '0';
signal FX2_RXVAL_LED : slbit := '0';
signal R_LEDDIV : slv6 := (others=>'0'); -- clock divider for LED pulses
signal R_LEDCE : slbit := '0'; -- ce every 64 usec
begin
RLCORE : rlink_core8
generic map (
ATOWIDTH => 6,
ITOWIDTH => 6,
CPREF => c_rlink_cpref,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon)
port map (
CLK => CLK,
CE_INT => CE_MSEC,
RESET => RESET,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
RLBMUX : rlink_rlbmux
port map (
SEL => SWI(2),
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
P0_RXDATA => SER_RXDATA,
P0_RXVAL => SER_RXVAL,
P0_RXHOLD => SER_RXHOLD,
P0_TXDATA => SER_TXDATA,
P0_TXENA => SER_TXENA,
P0_TXBUSY => SER_TXBUSY,
P1_RXDATA => FX2_RXDATA,
P1_RXVAL => FX2_RXVAL,
P1_RXHOLD => FX2_RXHOLD,
P1_TXDATA => FX2_TXDATA,
P1_TXENA => FX2_TXENA_L,
P1_TXBUSY => FX2_TXBUSY
);
SERPORT : serport_1clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_ser2rri_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => SWI(1),
ENAESC => SWI(1),
RXDATA => SER_RXDATA,
RXVAL => SER_RXVAL,
RXHOLD => SER_RXHOLD,
TXDATA => SER_TXDATA,
TXENA => SER_TXENA,
TXBUSY => SER_TXBUSY,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXSD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
RB_SRES_OR1 : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_TOP,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_OR => RB_SRES
);
TX2ENA_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => FX2_TX2ENA_L,
POUT => FX2_TX2ENA_LED
);
TXENA_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => FX2_TXENA_L,
POUT => FX2_TXENA_LED
);
RXVAL_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => FX2_RXVAL,
POUT => FX2_RXVAL_LED
);
proc_clkdiv: process (CLK)
begin
if rising_edge(CLK) then
R_LEDCE <= '0';
if CE_USEC = '1' then
R_LEDDIV <= slv(unsigned(R_LEDDIV) - 1);
if unsigned(R_LEDDIV) = 0 then
R_LEDCE <= '1';
end if;
end if;
end if;
end process proc_clkdiv;
proc_hiomux : process (SWI, SER_MONI, STAT, FX2_TX2BUSY,
FX2_TX2ENA_LED, FX2_TXENA_LED, FX2_RXVAL_LED)
begin
DSP_DAT <= SER_MONI.abclkdiv;
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
if SWI(2) = '0' then
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
else
DSP_DP(3) <= FX2_TX2BUSY;
DSP_DP(2) <= FX2_TX2ENA_LED;
DSP_DP(1) <= FX2_TXENA_LED;
DSP_DP(0) <= FX2_RXVAL_LED;
end if;
end process proc_hiomux;
RB_MREQ_TOP <= RB_MREQ;
FX2_TX2ENA <= FX2_TX2ENA_L;
FX2_TXENA <= FX2_TXENA_L;
end syn;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 4;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity submodule is
port (
clk : in std_logic;
arg : in std_logic_vector(15 downto 0);
res : out std_logic_vector(15 downto 0)
);
end submodule;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sliced_ex is
port (
clk : in std_logic;
arg_a : in signed(7 downto 0);
arg_b : in signed(7 downto 0);
res_a : out signed(7 downto 0);
res_b : out signed(7 downto 0)
);
end sliced_ex;
architecture rtl of sliced_ex is
signal tmp : signed(15 downto 0);
begin
SUB_MODULE : entity work.submodule
port map (
clk => clk,
arg( 7 downto 0) => std_logic_vector(arg_a),
arg(15 downto 8) => std_logic_vector(arg_b),
-- The casting of a sliced output causes an exception.
-- Casting of the entire output bus does work
-- signed(res) => tmp -- (this would work)
signed(res( 7 downto 0)) => res_a,
signed(res(15 downto 8)) => res_b
);
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1570.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01570ent IS
END c08s10b00x00p03n01i01570ent;
ARCHITECTURE c08s10b00x00p03n01i01570arch OF c08s10b00x00p03n01i01570ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 0;
variable done : boolean := false;
BEGIN
L1: for i in boolean loop
k := 5;
while not done loop
done := true ;
next ;
k := 3;
end loop ;
m := m + 1;
end loop L1;
assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***PASSED TEST: c08s10b00x00p03n01i01570"
severity NOTE;
assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***FAILED TEST: c08s10b00x00p03n01i01570 - A next statement is used without a loop label, it occurs only within a loop and it refers to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01570arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1570.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01570ent IS
END c08s10b00x00p03n01i01570ent;
ARCHITECTURE c08s10b00x00p03n01i01570arch OF c08s10b00x00p03n01i01570ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 0;
variable done : boolean := false;
BEGIN
L1: for i in boolean loop
k := 5;
while not done loop
done := true ;
next ;
k := 3;
end loop ;
m := m + 1;
end loop L1;
assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***PASSED TEST: c08s10b00x00p03n01i01570"
severity NOTE;
assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***FAILED TEST: c08s10b00x00p03n01i01570 - A next statement is used without a loop label, it occurs only within a loop and it refers to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01570arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1570.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01570ent IS
END c08s10b00x00p03n01i01570ent;
ARCHITECTURE c08s10b00x00p03n01i01570arch OF c08s10b00x00p03n01i01570ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : integer := 0;
variable done : boolean := false;
BEGIN
L1: for i in boolean loop
k := 5;
while not done loop
done := true ;
next ;
k := 3;
end loop ;
m := m + 1;
end loop L1;
assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***PASSED TEST: c08s10b00x00p03n01i01570"
severity NOTE;
assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
report "***FAILED TEST: c08s10b00x00p03n01i01570 - A next statement is used without a loop label, it occurs only within a loop and it refers to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01570arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2628.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02628ent IS
END c13s03b01x00p02n01i02628ent;
ARCHITECTURE c13s03b01x00p02n01i02628arch OF c13s03b01x00p02n01i02628ent IS
BEGIN
TESTING: PROCESS
variable k;k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02628 - Identifier can not contain ';'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02628arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2628.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02628ent IS
END c13s03b01x00p02n01i02628ent;
ARCHITECTURE c13s03b01x00p02n01i02628arch OF c13s03b01x00p02n01i02628ent IS
BEGIN
TESTING: PROCESS
variable k;k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02628 - Identifier can not contain ';'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02628arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2628.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02628ent IS
END c13s03b01x00p02n01i02628ent;
ARCHITECTURE c13s03b01x00p02n01i02628arch OF c13s03b01x00p02n01i02628ent IS
BEGIN
TESTING: PROCESS
variable k;k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02628 - Identifier can not contain ';'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02628arch;
|
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